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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.25 97.82 96.03 93.34 100.00 98.52 98.76 96.29


Total test records in report: 1000
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T819 /workspace/coverage/default/12.lc_ctrl_smoke.1749775815 Jun 09 01:30:48 PM PDT 24 Jun 09 01:30:51 PM PDT 24 174288962 ps
T820 /workspace/coverage/default/30.lc_ctrl_sec_token_digest.186714126 Jun 09 01:32:41 PM PDT 24 Jun 09 01:32:56 PM PDT 24 640743071 ps
T821 /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3821207336 Jun 09 01:30:52 PM PDT 24 Jun 09 01:31:03 PM PDT 24 5491492086 ps
T822 /workspace/coverage/default/42.lc_ctrl_sec_token_mux.353989454 Jun 09 01:33:34 PM PDT 24 Jun 09 01:33:41 PM PDT 24 256248339 ps
T823 /workspace/coverage/default/8.lc_ctrl_errors.3241012456 Jun 09 01:30:19 PM PDT 24 Jun 09 01:30:39 PM PDT 24 907538090 ps
T824 /workspace/coverage/default/44.lc_ctrl_sec_token_mux.2443336875 Jun 09 01:33:39 PM PDT 24 Jun 09 01:33:46 PM PDT 24 1016123629 ps
T825 /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2597513179 Jun 09 01:30:41 PM PDT 24 Jun 09 01:31:07 PM PDT 24 876705471 ps
T826 /workspace/coverage/default/48.lc_ctrl_smoke.4184587842 Jun 09 01:33:54 PM PDT 24 Jun 09 01:33:57 PM PDT 24 215476204 ps
T827 /workspace/coverage/default/33.lc_ctrl_state_post_trans.1088255705 Jun 09 01:32:53 PM PDT 24 Jun 09 01:33:02 PM PDT 24 140275709 ps
T828 /workspace/coverage/default/14.lc_ctrl_prog_failure.868252340 Jun 09 01:31:03 PM PDT 24 Jun 09 01:31:06 PM PDT 24 66148292 ps
T829 /workspace/coverage/default/17.lc_ctrl_state_post_trans.37102509 Jun 09 01:31:25 PM PDT 24 Jun 09 01:31:33 PM PDT 24 120216961 ps
T830 /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.52816032 Jun 09 01:31:08 PM PDT 24 Jun 09 01:32:29 PM PDT 24 2589760690 ps
T831 /workspace/coverage/default/47.lc_ctrl_state_failure.2259694566 Jun 09 01:33:50 PM PDT 24 Jun 09 01:34:12 PM PDT 24 308736893 ps
T832 /workspace/coverage/default/2.lc_ctrl_stress_all.1405866156 Jun 09 01:29:22 PM PDT 24 Jun 09 01:32:08 PM PDT 24 32173372407 ps
T833 /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.136173301 Jun 09 01:32:20 PM PDT 24 Jun 09 01:32:21 PM PDT 24 18616393 ps
T834 /workspace/coverage/default/6.lc_ctrl_sec_mubi.1538461145 Jun 09 01:29:57 PM PDT 24 Jun 09 01:30:13 PM PDT 24 652376639 ps
T835 /workspace/coverage/default/26.lc_ctrl_errors.491872672 Jun 09 01:32:19 PM PDT 24 Jun 09 01:32:30 PM PDT 24 397195571 ps
T836 /workspace/coverage/default/29.lc_ctrl_jtag_access.3023697133 Jun 09 01:32:32 PM PDT 24 Jun 09 01:32:40 PM PDT 24 1346409901 ps
T837 /workspace/coverage/default/19.lc_ctrl_jtag_errors.1470251545 Jun 09 01:31:40 PM PDT 24 Jun 09 01:32:45 PM PDT 24 9994897433 ps
T838 /workspace/coverage/default/18.lc_ctrl_smoke.2949900767 Jun 09 01:31:32 PM PDT 24 Jun 09 01:31:34 PM PDT 24 44210360 ps
T839 /workspace/coverage/default/46.lc_ctrl_security_escalation.2888411089 Jun 09 01:33:51 PM PDT 24 Jun 09 01:33:59 PM PDT 24 2941226258 ps
T840 /workspace/coverage/default/17.lc_ctrl_security_escalation.737274922 Jun 09 01:31:25 PM PDT 24 Jun 09 01:31:35 PM PDT 24 1022334816 ps
T841 /workspace/coverage/default/1.lc_ctrl_jtag_smoke.1079384508 Jun 09 01:29:13 PM PDT 24 Jun 09 01:29:20 PM PDT 24 452371835 ps
T842 /workspace/coverage/default/22.lc_ctrl_stress_all.2588178838 Jun 09 01:32:05 PM PDT 24 Jun 09 01:33:49 PM PDT 24 71099360404 ps
T843 /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.786104871 Jun 09 01:29:22 PM PDT 24 Jun 09 01:33:15 PM PDT 24 12148139344 ps
T844 /workspace/coverage/default/11.lc_ctrl_alert_test.2418415866 Jun 09 01:30:47 PM PDT 24 Jun 09 01:30:49 PM PDT 24 26790340 ps
T845 /workspace/coverage/default/46.lc_ctrl_alert_test.3455703328 Jun 09 01:33:51 PM PDT 24 Jun 09 01:33:53 PM PDT 24 22728033 ps
T846 /workspace/coverage/default/15.lc_ctrl_jtag_errors.1116426523 Jun 09 01:31:15 PM PDT 24 Jun 09 01:31:37 PM PDT 24 2594991242 ps
T847 /workspace/coverage/default/0.lc_ctrl_smoke.405411652 Jun 09 01:28:55 PM PDT 24 Jun 09 01:28:58 PM PDT 24 56902368 ps
T848 /workspace/coverage/default/15.lc_ctrl_state_post_trans.3217590329 Jun 09 01:31:13 PM PDT 24 Jun 09 01:31:21 PM PDT 24 74655356 ps
T71 /workspace/coverage/default/31.lc_ctrl_stress_all.3753129711 Jun 09 01:32:46 PM PDT 24 Jun 09 01:35:58 PM PDT 24 4392306108 ps
T849 /workspace/coverage/default/8.lc_ctrl_sec_token_mux.421908468 Jun 09 01:30:23 PM PDT 24 Jun 09 01:30:30 PM PDT 24 824774770 ps
T850 /workspace/coverage/default/33.lc_ctrl_state_failure.2216329597 Jun 09 01:32:49 PM PDT 24 Jun 09 01:33:15 PM PDT 24 212641622 ps
T851 /workspace/coverage/default/20.lc_ctrl_smoke.1472820331 Jun 09 01:31:52 PM PDT 24 Jun 09 01:31:56 PM PDT 24 99185072 ps
T852 /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.37538323 Jun 09 01:29:45 PM PDT 24 Jun 09 01:29:46 PM PDT 24 14241620 ps
T853 /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.1800905254 Jun 09 01:31:31 PM PDT 24 Jun 09 01:31:34 PM PDT 24 362664572 ps
T211 /workspace/coverage/default/6.lc_ctrl_claim_transition_if.2117996645 Jun 09 01:29:59 PM PDT 24 Jun 09 01:30:00 PM PDT 24 47787832 ps
T854 /workspace/coverage/default/43.lc_ctrl_prog_failure.979579509 Jun 09 01:33:34 PM PDT 24 Jun 09 01:33:36 PM PDT 24 25766627 ps
T72 /workspace/coverage/default/4.lc_ctrl_regwen_during_op.3961608996 Jun 09 01:29:46 PM PDT 24 Jun 09 01:30:04 PM PDT 24 275428136 ps
T855 /workspace/coverage/default/16.lc_ctrl_sec_token_mux.1867731363 Jun 09 01:31:26 PM PDT 24 Jun 09 01:31:35 PM PDT 24 356703958 ps
T856 /workspace/coverage/default/1.lc_ctrl_alert_test.3166186 Jun 09 01:29:18 PM PDT 24 Jun 09 01:29:19 PM PDT 24 52516808 ps
T857 /workspace/coverage/default/34.lc_ctrl_errors.1986550180 Jun 09 01:32:58 PM PDT 24 Jun 09 01:33:16 PM PDT 24 2465619854 ps
T858 /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.888586022 Jun 09 01:32:59 PM PDT 24 Jun 09 01:33:00 PM PDT 24 94196483 ps
T859 /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3107507666 Jun 09 01:30:31 PM PDT 24 Jun 09 01:30:56 PM PDT 24 891420697 ps
T860 /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3113655806 Jun 09 01:28:54 PM PDT 24 Jun 09 01:28:55 PM PDT 24 46770846 ps
T861 /workspace/coverage/default/34.lc_ctrl_smoke.4207198973 Jun 09 01:32:56 PM PDT 24 Jun 09 01:33:00 PM PDT 24 100074314 ps
T862 /workspace/coverage/default/19.lc_ctrl_prog_failure.1805442546 Jun 09 01:31:42 PM PDT 24 Jun 09 01:31:43 PM PDT 24 15194229 ps
T863 /workspace/coverage/default/17.lc_ctrl_stress_all.210686624 Jun 09 01:31:33 PM PDT 24 Jun 09 01:37:44 PM PDT 24 53769064667 ps
T864 /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2971771849 Jun 09 01:32:04 PM PDT 24 Jun 09 01:32:05 PM PDT 24 39129160 ps
T865 /workspace/coverage/default/40.lc_ctrl_alert_test.3757050188 Jun 09 01:33:25 PM PDT 24 Jun 09 01:33:26 PM PDT 24 65416646 ps
T866 /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.987347528 Jun 09 01:31:28 PM PDT 24 Jun 09 01:32:08 PM PDT 24 15360929838 ps
T867 /workspace/coverage/default/12.lc_ctrl_stress_all.2586485475 Jun 09 01:30:55 PM PDT 24 Jun 09 01:32:45 PM PDT 24 75021260394 ps
T868 /workspace/coverage/default/18.lc_ctrl_jtag_smoke.3752906707 Jun 09 01:31:33 PM PDT 24 Jun 09 01:31:43 PM PDT 24 1366479074 ps
T869 /workspace/coverage/default/11.lc_ctrl_state_post_trans.1581770581 Jun 09 01:30:42 PM PDT 24 Jun 09 01:30:52 PM PDT 24 285443162 ps
T870 /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1930721732 Jun 09 01:30:09 PM PDT 24 Jun 09 01:30:10 PM PDT 24 12660861 ps
T871 /workspace/coverage/default/35.lc_ctrl_stress_all.3903167478 Jun 09 01:33:02 PM PDT 24 Jun 09 01:35:57 PM PDT 24 15295938524 ps
T872 /workspace/coverage/default/49.lc_ctrl_stress_all.2346496471 Jun 09 01:33:59 PM PDT 24 Jun 09 01:35:20 PM PDT 24 8110494954 ps
T873 /workspace/coverage/default/8.lc_ctrl_state_post_trans.1585445763 Jun 09 01:30:20 PM PDT 24 Jun 09 01:30:28 PM PDT 24 65517974 ps
T874 /workspace/coverage/default/39.lc_ctrl_errors.531451555 Jun 09 01:33:19 PM PDT 24 Jun 09 01:33:33 PM PDT 24 317119288 ps
T875 /workspace/coverage/default/48.lc_ctrl_prog_failure.3410325092 Jun 09 01:33:55 PM PDT 24 Jun 09 01:33:57 PM PDT 24 113743256 ps
T169 /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.659213479 Jun 09 01:33:45 PM PDT 24 Jun 09 01:52:19 PM PDT 24 176094639448 ps
T171 /workspace/coverage/default/21.lc_ctrl_state_failure.3466308624 Jun 09 01:31:52 PM PDT 24 Jun 09 01:32:14 PM PDT 24 987072482 ps
T73 /workspace/coverage/default/13.lc_ctrl_alert_test.4243513435 Jun 09 01:31:05 PM PDT 24 Jun 09 01:31:07 PM PDT 24 22436536 ps
T101 /workspace/coverage/default/3.lc_ctrl_sec_cm.278168469 Jun 09 01:29:31 PM PDT 24 Jun 09 01:29:57 PM PDT 24 119869409 ps
T172 /workspace/coverage/default/32.lc_ctrl_state_failure.3371217410 Jun 09 01:32:45 PM PDT 24 Jun 09 01:33:16 PM PDT 24 271306708 ps
T144 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1696092187 Jun 09 01:25:15 PM PDT 24 Jun 09 01:25:17 PM PDT 24 13478494 ps
T113 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.4004392135 Jun 09 01:26:48 PM PDT 24 Jun 09 01:26:50 PM PDT 24 21389292 ps
T145 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2856944040 Jun 09 01:24:41 PM PDT 24 Jun 09 01:24:42 PM PDT 24 67733794 ps
T121 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1370040579 Jun 09 01:24:47 PM PDT 24 Jun 09 01:24:54 PM PDT 24 269634504 ps
T122 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3353973688 Jun 09 01:26:37 PM PDT 24 Jun 09 01:26:39 PM PDT 24 300668915 ps
T110 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3388879093 Jun 09 01:25:27 PM PDT 24 Jun 09 01:25:29 PM PDT 24 24452962 ps
T117 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2516446978 Jun 09 01:26:49 PM PDT 24 Jun 09 01:26:51 PM PDT 24 64468471 ps
T118 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.512453237 Jun 09 01:25:19 PM PDT 24 Jun 09 01:25:20 PM PDT 24 22305661 ps
T119 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2784027104 Jun 09 01:26:44 PM PDT 24 Jun 09 01:26:45 PM PDT 24 45531831 ps
T111 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2979207260 Jun 09 01:26:28 PM PDT 24 Jun 09 01:26:33 PM PDT 24 410521189 ps
T188 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.768359801 Jun 09 01:24:40 PM PDT 24 Jun 09 01:24:41 PM PDT 24 42410359 ps
T158 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1176760620 Jun 09 01:26:56 PM PDT 24 Jun 09 01:26:57 PM PDT 24 62808390 ps
T140 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3085499764 Jun 09 01:25:53 PM PDT 24 Jun 09 01:25:59 PM PDT 24 817937014 ps
T120 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.430454464 Jun 09 01:26:05 PM PDT 24 Jun 09 01:26:07 PM PDT 24 20229055 ps
T876 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.4090579632 Jun 09 01:25:27 PM PDT 24 Jun 09 01:25:28 PM PDT 24 106652617 ps
T159 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2220295294 Jun 09 01:25:43 PM PDT 24 Jun 09 01:25:44 PM PDT 24 67350572 ps
T143 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2992228816 Jun 09 01:25:16 PM PDT 24 Jun 09 01:25:18 PM PDT 24 174561285 ps
T114 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.887016107 Jun 09 01:25:00 PM PDT 24 Jun 09 01:25:02 PM PDT 24 210766571 ps
T877 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1734776848 Jun 09 01:25:32 PM PDT 24 Jun 09 01:25:34 PM PDT 24 152714705 ps
T208 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.231680168 Jun 09 01:24:49 PM PDT 24 Jun 09 01:25:04 PM PDT 24 2714349907 ps
T112 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2333792750 Jun 09 01:26:37 PM PDT 24 Jun 09 01:26:42 PM PDT 24 156848739 ps
T189 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2788814959 Jun 09 01:26:38 PM PDT 24 Jun 09 01:26:39 PM PDT 24 23922733 ps
T878 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.937457241 Jun 09 01:25:58 PM PDT 24 Jun 09 01:26:00 PM PDT 24 55610707 ps
T879 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1247224284 Jun 09 01:24:45 PM PDT 24 Jun 09 01:24:48 PM PDT 24 67243351 ps
T880 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2714896637 Jun 09 01:25:02 PM PDT 24 Jun 09 01:25:03 PM PDT 24 32095803 ps
T881 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1481949763 Jun 09 01:25:01 PM PDT 24 Jun 09 01:25:02 PM PDT 24 35058955 ps
T190 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1497323958 Jun 09 01:25:38 PM PDT 24 Jun 09 01:25:40 PM PDT 24 139161238 ps
T191 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.4074906529 Jun 09 01:24:39 PM PDT 24 Jun 09 01:24:40 PM PDT 24 48346921 ps
T882 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3816260925 Jun 09 01:25:46 PM PDT 24 Jun 09 01:25:47 PM PDT 24 217823227 ps
T141 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.271225717 Jun 09 01:25:52 PM PDT 24 Jun 09 01:25:54 PM PDT 24 124974790 ps
T200 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.764320141 Jun 09 01:26:35 PM PDT 24 Jun 09 01:26:36 PM PDT 24 27544942 ps
T124 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1916244023 Jun 09 01:26:17 PM PDT 24 Jun 09 01:26:19 PM PDT 24 57203745 ps
T201 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1818703697 Jun 09 01:26:54 PM PDT 24 Jun 09 01:26:55 PM PDT 24 40435481 ps
T883 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.16141236 Jun 09 01:25:22 PM PDT 24 Jun 09 01:25:38 PM PDT 24 8955280266 ps
T202 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3808734614 Jun 09 01:25:21 PM PDT 24 Jun 09 01:25:22 PM PDT 24 16116496 ps
T127 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.847068984 Jun 09 01:26:53 PM PDT 24 Jun 09 01:26:54 PM PDT 24 100960958 ps
T115 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1372838647 Jun 09 01:24:40 PM PDT 24 Jun 09 01:24:42 PM PDT 24 101333541 ps
T142 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1110803105 Jun 09 01:26:17 PM PDT 24 Jun 09 01:26:18 PM PDT 24 93266824 ps
T170 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3807822497 Jun 09 01:24:44 PM PDT 24 Jun 09 01:24:46 PM PDT 24 36960463 ps
T884 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1304757522 Jun 09 01:25:58 PM PDT 24 Jun 09 01:26:00 PM PDT 24 662338156 ps
T885 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2527136189 Jun 09 01:25:32 PM PDT 24 Jun 09 01:25:34 PM PDT 24 16751648 ps
T203 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.44479243 Jun 09 01:24:53 PM PDT 24 Jun 09 01:24:54 PM PDT 24 15536627 ps
T204 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1425430076 Jun 09 01:26:50 PM PDT 24 Jun 09 01:26:52 PM PDT 24 370142802 ps
T205 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1194408717 Jun 09 01:24:44 PM PDT 24 Jun 09 01:24:46 PM PDT 24 22785119 ps
T131 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.95877795 Jun 09 01:26:40 PM PDT 24 Jun 09 01:26:42 PM PDT 24 359303705 ps
T886 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1308819382 Jun 09 01:25:58 PM PDT 24 Jun 09 01:25:59 PM PDT 24 21692386 ps
T206 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1294023731 Jun 09 01:26:16 PM PDT 24 Jun 09 01:26:18 PM PDT 24 66627049 ps
T887 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3238311949 Jun 09 01:25:39 PM PDT 24 Jun 09 01:25:42 PM PDT 24 393901418 ps
T888 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.800548594 Jun 09 01:26:44 PM PDT 24 Jun 09 01:26:45 PM PDT 24 303115236 ps
T889 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.13266634 Jun 09 01:25:01 PM PDT 24 Jun 09 01:25:03 PM PDT 24 58486341 ps
T890 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2009085745 Jun 09 01:26:55 PM PDT 24 Jun 09 01:26:57 PM PDT 24 26468620 ps
T891 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3212570350 Jun 09 01:25:17 PM PDT 24 Jun 09 01:25:31 PM PDT 24 11265923505 ps
T207 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.34467740 Jun 09 01:25:54 PM PDT 24 Jun 09 01:25:55 PM PDT 24 45630679 ps
T892 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.933346300 Jun 09 01:26:21 PM PDT 24 Jun 09 01:26:25 PM PDT 24 148268093 ps
T116 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2593721522 Jun 09 01:25:15 PM PDT 24 Jun 09 01:25:18 PM PDT 24 237116382 ps
T893 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3311891833 Jun 09 01:25:21 PM PDT 24 Jun 09 01:25:23 PM PDT 24 50357179 ps
T894 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2653461072 Jun 09 01:26:20 PM PDT 24 Jun 09 01:26:23 PM PDT 24 1049711575 ps
T125 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.4282839662 Jun 09 01:26:48 PM PDT 24 Jun 09 01:26:51 PM PDT 24 1631249275 ps
T895 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3989106880 Jun 09 01:25:39 PM PDT 24 Jun 09 01:25:41 PM PDT 24 54152276 ps
T896 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.788201942 Jun 09 01:26:14 PM PDT 24 Jun 09 01:26:16 PM PDT 24 217604287 ps
T132 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2608527971 Jun 09 01:26:45 PM PDT 24 Jun 09 01:26:48 PM PDT 24 124921632 ps
T897 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1645197953 Jun 09 01:24:27 PM PDT 24 Jun 09 01:24:29 PM PDT 24 37069314 ps
T898 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2666034423 Jun 09 01:24:38 PM PDT 24 Jun 09 01:24:40 PM PDT 24 18156227 ps
T133 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.311299350 Jun 09 01:26:10 PM PDT 24 Jun 09 01:26:13 PM PDT 24 251582700 ps
T899 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1140498414 Jun 09 01:26:55 PM PDT 24 Jun 09 01:26:56 PM PDT 24 41400197 ps
T900 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.597706560 Jun 09 01:26:37 PM PDT 24 Jun 09 01:26:39 PM PDT 24 127187165 ps
T901 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2505978681 Jun 09 01:26:31 PM PDT 24 Jun 09 01:26:33 PM PDT 24 42152118 ps
T902 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2447963503 Jun 09 01:24:39 PM PDT 24 Jun 09 01:24:43 PM PDT 24 1675795977 ps
T903 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1054539275 Jun 09 01:24:55 PM PDT 24 Jun 09 01:25:07 PM PDT 24 448565273 ps
T136 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2773044276 Jun 09 01:25:26 PM PDT 24 Jun 09 01:25:30 PM PDT 24 386059914 ps
T192 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.4152605018 Jun 09 01:26:31 PM PDT 24 Jun 09 01:26:32 PM PDT 24 24950257 ps
T904 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2224823998 Jun 09 01:26:21 PM PDT 24 Jun 09 01:26:24 PM PDT 24 135933352 ps
T905 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.4075093321 Jun 09 01:25:59 PM PDT 24 Jun 09 01:26:01 PM PDT 24 37210431 ps
T906 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1751543594 Jun 09 01:24:39 PM PDT 24 Jun 09 01:24:42 PM PDT 24 104462147 ps
T139 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2873717511 Jun 09 01:26:05 PM PDT 24 Jun 09 01:26:08 PM PDT 24 105014764 ps
T907 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1128360707 Jun 09 01:26:32 PM PDT 24 Jun 09 01:26:36 PM PDT 24 233322602 ps
T908 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.102779519 Jun 09 01:25:59 PM PDT 24 Jun 09 01:26:00 PM PDT 24 51276057 ps
T909 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3219466438 Jun 09 01:25:53 PM PDT 24 Jun 09 01:25:54 PM PDT 24 64783849 ps
T910 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2792073235 Jun 09 01:25:05 PM PDT 24 Jun 09 01:25:06 PM PDT 24 54489093 ps
T911 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3690586813 Jun 09 01:26:09 PM PDT 24 Jun 09 01:26:13 PM PDT 24 119468487 ps
T912 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4258040605 Jun 09 01:25:16 PM PDT 24 Jun 09 01:25:19 PM PDT 24 347814929 ps
T913 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1233281252 Jun 09 01:26:08 PM PDT 24 Jun 09 01:26:12 PM PDT 24 261175013 ps
T914 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1003558534 Jun 09 01:24:49 PM PDT 24 Jun 09 01:24:50 PM PDT 24 113426755 ps
T193 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2063833124 Jun 09 01:25:22 PM PDT 24 Jun 09 01:25:24 PM PDT 24 57296753 ps
T915 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3707312072 Jun 09 01:26:22 PM PDT 24 Jun 09 01:26:24 PM PDT 24 28077355 ps
T128 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3133040499 Jun 09 01:26:43 PM PDT 24 Jun 09 01:26:46 PM PDT 24 247962624 ps
T194 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2198312148 Jun 09 01:25:43 PM PDT 24 Jun 09 01:25:44 PM PDT 24 46959215 ps
T916 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3940210927 Jun 09 01:25:22 PM PDT 24 Jun 09 01:25:29 PM PDT 24 733906070 ps
T917 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2873267897 Jun 09 01:26:01 PM PDT 24 Jun 09 01:26:08 PM PDT 24 302909550 ps
T918 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.191356636 Jun 09 01:26:06 PM PDT 24 Jun 09 01:26:08 PM PDT 24 164398694 ps
T919 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2130760555 Jun 09 01:26:21 PM PDT 24 Jun 09 01:26:39 PM PDT 24 696240789 ps
T920 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3586463624 Jun 09 01:25:27 PM PDT 24 Jun 09 01:25:30 PM PDT 24 50325589 ps
T921 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1153527439 Jun 09 01:26:11 PM PDT 24 Jun 09 01:26:35 PM PDT 24 3067044863 ps
T922 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2969300585 Jun 09 01:25:21 PM PDT 24 Jun 09 01:25:23 PM PDT 24 19919522 ps
T923 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3687739765 Jun 09 01:25:21 PM PDT 24 Jun 09 01:25:25 PM PDT 24 128793147 ps
T924 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.4062008118 Jun 09 01:25:58 PM PDT 24 Jun 09 01:26:13 PM PDT 24 1158755573 ps
T925 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2549676822 Jun 09 01:26:21 PM PDT 24 Jun 09 01:26:22 PM PDT 24 17545688 ps
T926 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.129365519 Jun 09 01:26:21 PM PDT 24 Jun 09 01:26:23 PM PDT 24 19605464 ps
T195 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.330366447 Jun 09 01:25:16 PM PDT 24 Jun 09 01:25:17 PM PDT 24 23194135 ps
T927 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.111611303 Jun 09 01:26:55 PM PDT 24 Jun 09 01:26:57 PM PDT 24 14485474 ps
T928 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.453566353 Jun 09 01:26:28 PM PDT 24 Jun 09 01:26:31 PM PDT 24 181546888 ps
T929 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.4271400215 Jun 09 01:26:44 PM PDT 24 Jun 09 01:26:45 PM PDT 24 249359893 ps
T930 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3575842447 Jun 09 01:26:17 PM PDT 24 Jun 09 01:26:34 PM PDT 24 1116958354 ps
T931 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3089941483 Jun 09 01:26:44 PM PDT 24 Jun 09 01:26:48 PM PDT 24 506944846 ps
T129 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.612979783 Jun 09 01:26:54 PM PDT 24 Jun 09 01:26:57 PM PDT 24 192430496 ps
T932 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.699873618 Jun 09 01:25:54 PM PDT 24 Jun 09 01:25:55 PM PDT 24 140995231 ps
T933 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3784268180 Jun 09 01:25:53 PM PDT 24 Jun 09 01:25:55 PM PDT 24 60632387 ps
T934 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3998077402 Jun 09 01:24:22 PM PDT 24 Jun 09 01:24:24 PM PDT 24 453464865 ps
T935 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1647039723 Jun 09 01:25:01 PM PDT 24 Jun 09 01:25:02 PM PDT 24 16555944 ps
T936 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2085809510 Jun 09 01:25:58 PM PDT 24 Jun 09 01:26:00 PM PDT 24 83575862 ps
T937 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.4022621207 Jun 09 01:26:42 PM PDT 24 Jun 09 01:26:44 PM PDT 24 52517127 ps
T938 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2753848857 Jun 09 01:26:31 PM PDT 24 Jun 09 01:26:33 PM PDT 24 98041531 ps
T939 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1500622383 Jun 09 01:26:33 PM PDT 24 Jun 09 01:26:34 PM PDT 24 22641421 ps
T940 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3426407474 Jun 09 01:24:39 PM PDT 24 Jun 09 01:24:41 PM PDT 24 221308767 ps
T941 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1242914306 Jun 09 01:25:46 PM PDT 24 Jun 09 01:25:50 PM PDT 24 46193669 ps
T942 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2956310871 Jun 09 01:26:26 PM PDT 24 Jun 09 01:26:27 PM PDT 24 59113690 ps
T943 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.66020723 Jun 09 01:26:10 PM PDT 24 Jun 09 01:26:12 PM PDT 24 22131237 ps
T944 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3232303688 Jun 09 01:26:32 PM PDT 24 Jun 09 01:26:33 PM PDT 24 46172505 ps
T945 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1309963369 Jun 09 01:25:37 PM PDT 24 Jun 09 01:25:56 PM PDT 24 907926751 ps
T946 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2301543127 Jun 09 01:25:13 PM PDT 24 Jun 09 01:25:17 PM PDT 24 89785344 ps
T130 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1083729208 Jun 09 01:25:42 PM PDT 24 Jun 09 01:25:45 PM PDT 24 112481859 ps
T947 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.417681124 Jun 09 01:26:10 PM PDT 24 Jun 09 01:26:13 PM PDT 24 168679518 ps
T135 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.288718259 Jun 09 01:25:59 PM PDT 24 Jun 09 01:26:02 PM PDT 24 129151853 ps
T948 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1586670644 Jun 09 01:26:37 PM PDT 24 Jun 09 01:26:39 PM PDT 24 16657466 ps
T949 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2845811268 Jun 09 01:25:15 PM PDT 24 Jun 09 01:25:32 PM PDT 24 6088177470 ps
T950 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2964283643 Jun 09 01:24:54 PM PDT 24 Jun 09 01:24:56 PM PDT 24 339724750 ps
T951 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3605148571 Jun 09 01:26:15 PM PDT 24 Jun 09 01:26:17 PM PDT 24 71655627 ps
T952 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1499911699 Jun 09 01:26:28 PM PDT 24 Jun 09 01:26:30 PM PDT 24 433700125 ps
T953 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1880137767 Jun 09 01:26:01 PM PDT 24 Jun 09 01:26:29 PM PDT 24 2119611135 ps
T954 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.600307837 Jun 09 01:26:16 PM PDT 24 Jun 09 01:26:22 PM PDT 24 2076948953 ps
T126 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3489796444 Jun 09 01:26:49 PM PDT 24 Jun 09 01:26:52 PM PDT 24 354043484 ps
T137 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2138616043 Jun 09 01:26:40 PM PDT 24 Jun 09 01:26:42 PM PDT 24 218044113 ps
T138 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3480897122 Jun 09 01:26:56 PM PDT 24 Jun 09 01:26:58 PM PDT 24 268897208 ps
T955 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2520670930 Jun 09 01:25:22 PM PDT 24 Jun 09 01:25:24 PM PDT 24 26851420 ps
T956 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.852925441 Jun 09 01:26:46 PM PDT 24 Jun 09 01:26:48 PM PDT 24 174430285 ps
T957 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.884515104 Jun 09 01:26:16 PM PDT 24 Jun 09 01:26:18 PM PDT 24 47433503 ps
T958 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1859944337 Jun 09 01:26:32 PM PDT 24 Jun 09 01:26:34 PM PDT 24 43846605 ps
T959 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.834298328 Jun 09 01:26:08 PM PDT 24 Jun 09 01:26:09 PM PDT 24 27797998 ps
T196 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.4044083839 Jun 09 01:24:44 PM PDT 24 Jun 09 01:24:45 PM PDT 24 46638232 ps
T960 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2234115539 Jun 09 01:26:39 PM PDT 24 Jun 09 01:26:40 PM PDT 24 112141842 ps
T961 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3694088726 Jun 09 01:25:46 PM PDT 24 Jun 09 01:25:50 PM PDT 24 123169306 ps
T962 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2396291632 Jun 09 01:25:57 PM PDT 24 Jun 09 01:26:02 PM PDT 24 161969253 ps
T963 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1450778696 Jun 09 01:26:48 PM PDT 24 Jun 09 01:26:49 PM PDT 24 25403963 ps
T964 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1924356835 Jun 09 01:26:39 PM PDT 24 Jun 09 01:26:40 PM PDT 24 56252422 ps
T965 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.913947488 Jun 09 01:26:50 PM PDT 24 Jun 09 01:26:54 PM PDT 24 76030242 ps
T966 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.4192818339 Jun 09 01:25:39 PM PDT 24 Jun 09 01:25:41 PM PDT 24 30767008 ps
T197 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1339623158 Jun 09 01:25:22 PM PDT 24 Jun 09 01:25:23 PM PDT 24 53828885 ps
T967 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3920291441 Jun 09 01:24:38 PM PDT 24 Jun 09 01:24:48 PM PDT 24 965746430 ps
T968 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3890606498 Jun 09 01:25:54 PM PDT 24 Jun 09 01:25:57 PM PDT 24 444566017 ps
T198 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3809842174 Jun 09 01:26:26 PM PDT 24 Jun 09 01:26:27 PM PDT 24 45300742 ps
T969 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3910734827 Jun 09 01:26:05 PM PDT 24 Jun 09 01:26:07 PM PDT 24 172999287 ps
T970 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1799711821 Jun 09 01:26:53 PM PDT 24 Jun 09 01:26:54 PM PDT 24 13844705 ps
T971 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1753724260 Jun 09 01:25:35 PM PDT 24 Jun 09 01:25:38 PM PDT 24 218805023 ps
T972 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.4284470994 Jun 09 01:25:12 PM PDT 24 Jun 09 01:25:14 PM PDT 24 184963789 ps
T973 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1716284923 Jun 09 01:25:54 PM PDT 24 Jun 09 01:26:00 PM PDT 24 1669671568 ps
T974 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1730082204 Jun 09 01:26:20 PM PDT 24 Jun 09 01:26:22 PM PDT 24 37082192 ps
T975 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3392555439 Jun 09 01:25:20 PM PDT 24 Jun 09 01:25:23 PM PDT 24 1844557632 ps
T976 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2326903326 Jun 09 01:26:10 PM PDT 24 Jun 09 01:26:11 PM PDT 24 108092653 ps
T977 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2533691934 Jun 09 01:26:36 PM PDT 24 Jun 09 01:26:39 PM PDT 24 85103526 ps
T134 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1377861886 Jun 09 01:25:01 PM PDT 24 Jun 09 01:25:05 PM PDT 24 115395719 ps
T978 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1422180046 Jun 09 01:25:37 PM PDT 24 Jun 09 01:25:43 PM PDT 24 872533581 ps
T979 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1159919419 Jun 09 01:26:54 PM PDT 24 Jun 09 01:26:58 PM PDT 24 371404225 ps
T199 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1588311047 Jun 09 01:26:51 PM PDT 24 Jun 09 01:26:53 PM PDT 24 18267403 ps
T980 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2104770834 Jun 09 01:26:22 PM PDT 24 Jun 09 01:26:24 PM PDT 24 127078230 ps
T981 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2225900895 Jun 09 01:25:59 PM PDT 24 Jun 09 01:26:02 PM PDT 24 249631899 ps
T982 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1326761967 Jun 09 01:26:10 PM PDT 24 Jun 09 01:26:17 PM PDT 24 264029813 ps
T983 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.314546780 Jun 09 01:25:15 PM PDT 24 Jun 09 01:25:17 PM PDT 24 72777146 ps
T984 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3278969061 Jun 09 01:25:38 PM PDT 24 Jun 09 01:25:40 PM PDT 24 78670466 ps
T985 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3384185329 Jun 09 01:26:21 PM PDT 24 Jun 09 01:26:24 PM PDT 24 34991215 ps
T986 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2611136599 Jun 09 01:26:04 PM PDT 24 Jun 09 01:26:05 PM PDT 24 31151060 ps
T987 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1548745421 Jun 09 01:26:16 PM PDT 24 Jun 09 01:26:17 PM PDT 24 12420039 ps
T988 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3797053449 Jun 09 01:25:31 PM PDT 24 Jun 09 01:25:32 PM PDT 24 13235801 ps
T989 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2742601796 Jun 09 01:26:21 PM PDT 24 Jun 09 01:26:23 PM PDT 24 85427936 ps
T990 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.289009235 Jun 09 01:26:50 PM PDT 24 Jun 09 01:26:51 PM PDT 24 63140430 ps
T123 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.163656431 Jun 09 01:26:39 PM PDT 24 Jun 09 01:26:42 PM PDT 24 86919395 ps
T991 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1530613323 Jun 09 01:26:36 PM PDT 24 Jun 09 01:26:39 PM PDT 24 157389939 ps
T992 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2946910475 Jun 09 01:26:43 PM PDT 24 Jun 09 01:26:44 PM PDT 24 80596253 ps
T993 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1317804407 Jun 09 01:26:56 PM PDT 24 Jun 09 01:26:58 PM PDT 24 173973220 ps
T994 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2459939228 Jun 09 01:26:17 PM PDT 24 Jun 09 01:26:19 PM PDT 24 102052736 ps
T995 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1729432818 Jun 09 01:25:01 PM PDT 24 Jun 09 01:25:03 PM PDT 24 87798941 ps
T996 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1997103154 Jun 09 01:26:37 PM PDT 24 Jun 09 01:26:40 PM PDT 24 588622708 ps
T997 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1266636669 Jun 09 01:25:48 PM PDT 24 Jun 09 01:25:50 PM PDT 24 72370784 ps
T998 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1302442419 Jun 09 01:26:30 PM PDT 24 Jun 09 01:26:31 PM PDT 24 24994180 ps
T999 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.507374728 Jun 09 01:26:02 PM PDT 24 Jun 09 01:26:03 PM PDT 24 17091982 ps
T1000 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2731365402 Jun 09 01:25:54 PM PDT 24 Jun 09 01:25:56 PM PDT 24 141514438 ps

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.75836906
Short name T2
Test name
Test status
Simulation time 4430979958 ps
CPU time 81.64 seconds
Started Jun 09 01:33:58 PM PDT 24
Finished Jun 09 01:35:20 PM PDT 24
Peak memory 250972 kb
Host smart-31cec1c9-f912-4237-bc00-b3f71d7f345f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75836906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.lc_ctrl_stress_all.75836906
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.528357881
Short name T17
Test name
Test status
Simulation time 146111079871 ps
CPU time 500.48 seconds
Started Jun 09 01:34:03 PM PDT 24
Finished Jun 09 01:42:24 PM PDT 24
Peak memory 289980 kb
Host smart-256fc7f2-78a7-41c0-a739-df7f385374ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=528357881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.528357881
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.1641886153
Short name T165
Test name
Test status
Simulation time 406889055 ps
CPU time 9.77 seconds
Started Jun 09 01:32:24 PM PDT 24
Finished Jun 09 01:32:34 PM PDT 24
Peak memory 226060 kb
Host smart-9de626a3-ba42-41de-a509-198766a8086f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641886153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1641886153
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.1966278444
Short name T11
Test name
Test status
Simulation time 2879943963 ps
CPU time 12.67 seconds
Started Jun 09 01:32:19 PM PDT 24
Finished Jun 09 01:32:32 PM PDT 24
Peak memory 218980 kb
Host smart-808a497d-108e-40de-8d9a-20639136c43f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966278444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.1966278444
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.430454464
Short name T120
Test name
Test status
Simulation time 20229055 ps
CPU time 1.59 seconds
Started Jun 09 01:26:05 PM PDT 24
Finished Jun 09 01:26:07 PM PDT 24
Peak memory 219612 kb
Host smart-f8850882-b503-4301-8026-0027f56c4405
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430454464 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.430454464
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.88708208
Short name T13
Test name
Test status
Simulation time 1507670894 ps
CPU time 9.96 seconds
Started Jun 09 01:33:51 PM PDT 24
Finished Jun 09 01:34:01 PM PDT 24
Peak memory 218232 kb
Host smart-14e8d5d3-51ff-4074-9605-a5f0a8a9fd38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88708208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.88708208
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.73248519
Short name T15
Test name
Test status
Simulation time 13526845867 ps
CPU time 198.1 seconds
Started Jun 09 01:30:30 PM PDT 24
Finished Jun 09 01:33:49 PM PDT 24
Peak memory 283664 kb
Host smart-06b84dbf-6636-4bf8-b978-f68ad29e9065
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73248519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.lc_ctrl_stress_all.73248519
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.4264984812
Short name T49
Test name
Test status
Simulation time 443959627 ps
CPU time 23.44 seconds
Started Jun 09 01:29:44 PM PDT 24
Finished Jun 09 01:30:08 PM PDT 24
Peak memory 281200 kb
Host smart-baeada16-fcf2-4d1d-bbd2-234f900149ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264984812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.4264984812
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.73016635
Short name T6
Test name
Test status
Simulation time 130393422 ps
CPU time 2.81 seconds
Started Jun 09 01:31:30 PM PDT 24
Finished Jun 09 01:31:33 PM PDT 24
Peak memory 217192 kb
Host smart-e49244e6-38db-4552-bf71-c5a2e1657bb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73016635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.73016635
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2832138338
Short name T168
Test name
Test status
Simulation time 822393922 ps
CPU time 10.86 seconds
Started Jun 09 01:31:41 PM PDT 24
Finished Jun 09 01:31:52 PM PDT 24
Peak memory 218220 kb
Host smart-9d5db716-a53f-41b3-91e4-9256fdef7a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832138338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2832138338
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2979207260
Short name T111
Test name
Test status
Simulation time 410521189 ps
CPU time 4.01 seconds
Started Jun 09 01:26:28 PM PDT 24
Finished Jun 09 01:26:33 PM PDT 24
Peak memory 218168 kb
Host smart-862ff5d2-8420-4872-9fee-47b8dc3b1a3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979207260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.2979207260
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3085499764
Short name T140
Test name
Test status
Simulation time 817937014 ps
CPU time 5.61 seconds
Started Jun 09 01:25:53 PM PDT 24
Finished Jun 09 01:25:59 PM PDT 24
Peak memory 209896 kb
Host smart-b6bf1921-b4b1-49f9-8944-d5370a0a9d22
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085499764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3085499764
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.404313489
Short name T1
Test name
Test status
Simulation time 18398631 ps
CPU time 1.17 seconds
Started Jun 09 01:33:57 PM PDT 24
Finished Jun 09 01:33:58 PM PDT 24
Peak memory 209060 kb
Host smart-0103233c-2e75-4a76-ba01-dca2e84fa154
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404313489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.404313489
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2788814959
Short name T189
Test name
Test status
Simulation time 23922733 ps
CPU time 0.84 seconds
Started Jun 09 01:26:38 PM PDT 24
Finished Jun 09 01:26:39 PM PDT 24
Peak memory 209096 kb
Host smart-2a5f12ef-2d62-4973-8cec-ad1c4bdf2596
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788814959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2788814959
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.400703271
Short name T89
Test name
Test status
Simulation time 20273683862 ps
CPU time 443.71 seconds
Started Jun 09 01:30:43 PM PDT 24
Finished Jun 09 01:38:07 PM PDT 24
Peak memory 438628 kb
Host smart-3acd53ae-b77a-4d1d-9b2e-2af8b3cf7dda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=400703271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.400703271
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2773044276
Short name T136
Test name
Test status
Simulation time 386059914 ps
CPU time 3.72 seconds
Started Jun 09 01:25:26 PM PDT 24
Finished Jun 09 01:25:30 PM PDT 24
Peak memory 223208 kb
Host smart-9bf911ec-025e-41dc-92bf-e86d9dfeb3a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773044276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2773044276
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.644961859
Short name T108
Test name
Test status
Simulation time 7591533162 ps
CPU time 72.61 seconds
Started Jun 09 01:29:32 PM PDT 24
Finished Jun 09 01:30:44 PM PDT 24
Peak memory 267752 kb
Host smart-3c02813c-e771-4d5d-8b4a-0825d696a6dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644961859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.644961859
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.3065615485
Short name T54
Test name
Test status
Simulation time 26495367 ps
CPU time 2.04 seconds
Started Jun 09 01:31:57 PM PDT 24
Finished Jun 09 01:32:00 PM PDT 24
Peak memory 213980 kb
Host smart-8e288983-af28-4013-b0f8-b63904f4ff56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065615485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3065615485
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.869505985
Short name T46
Test name
Test status
Simulation time 6731084963 ps
CPU time 13.48 seconds
Started Jun 09 01:33:47 PM PDT 24
Finished Jun 09 01:34:01 PM PDT 24
Peak memory 218360 kb
Host smart-19ba4d63-8006-455e-9724-8d3d635dcdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869505985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.869505985
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.163656431
Short name T123
Test name
Test status
Simulation time 86919395 ps
CPU time 2.95 seconds
Started Jun 09 01:26:39 PM PDT 24
Finished Jun 09 01:26:42 PM PDT 24
Peak memory 222860 kb
Host smart-2c5eccb6-7de8-40e1-ac67-c08513fefb61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163656431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_
err.163656431
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1751543594
Short name T906
Test name
Test status
Simulation time 104462147 ps
CPU time 2.63 seconds
Started Jun 09 01:24:39 PM PDT 24
Finished Jun 09 01:24:42 PM PDT 24
Peak memory 218536 kb
Host smart-2dab3ba5-c22d-4a55-aad1-82655a748608
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751543594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1751543594
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.2449392139
Short name T465
Test name
Test status
Simulation time 2452510007 ps
CPU time 86.26 seconds
Started Jun 09 01:29:06 PM PDT 24
Finished Jun 09 01:30:32 PM PDT 24
Peak memory 246764 kb
Host smart-49a58dab-df69-4c27-ab05-40041d915a5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449392139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.2449392139
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1372838647
Short name T115
Test name
Test status
Simulation time 101333541 ps
CPU time 1.81 seconds
Started Jun 09 01:24:40 PM PDT 24
Finished Jun 09 01:24:42 PM PDT 24
Peak memory 222144 kb
Host smart-932684d2-54a9-4040-8262-4e59188b49a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372838647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.1372838647
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.447537809
Short name T14
Test name
Test status
Simulation time 946006247 ps
CPU time 30.66 seconds
Started Jun 09 01:31:15 PM PDT 24
Finished Jun 09 01:31:46 PM PDT 24
Peak memory 247272 kb
Host smart-3ae649b8-3cf9-44f6-98a6-00e30af58687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447537809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.447537809
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1194408717
Short name T205
Test name
Test status
Simulation time 22785119 ps
CPU time 1.53 seconds
Started Jun 09 01:24:44 PM PDT 24
Finished Jun 09 01:24:46 PM PDT 24
Peak memory 209968 kb
Host smart-b6d874ec-e644-4fa8-8798-2bf2fe9ab4ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194408717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.1194408717
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1084430205
Short name T12
Test name
Test status
Simulation time 43958993 ps
CPU time 0.86 seconds
Started Jun 09 01:33:32 PM PDT 24
Finished Jun 09 01:33:34 PM PDT 24
Peak memory 211992 kb
Host smart-5d645d45-ea3c-4679-bd37-8882a9483892
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084430205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.1084430205
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1377861886
Short name T134
Test name
Test status
Simulation time 115395719 ps
CPU time 4.23 seconds
Started Jun 09 01:25:01 PM PDT 24
Finished Jun 09 01:25:05 PM PDT 24
Peak memory 218232 kb
Host smart-4cf3fa21-5a03-4a16-a706-ee505e7f986b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377861886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.1377861886
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.4282839662
Short name T125
Test name
Test status
Simulation time 1631249275 ps
CPU time 3.02 seconds
Started Jun 09 01:26:48 PM PDT 24
Finished Jun 09 01:26:51 PM PDT 24
Peak memory 222444 kb
Host smart-1df58018-aec3-443e-b145-0ce7fa102559
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282839662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.4282839662
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3489796444
Short name T126
Test name
Test status
Simulation time 354043484 ps
CPU time 2.47 seconds
Started Jun 09 01:26:49 PM PDT 24
Finished Jun 09 01:26:52 PM PDT 24
Peak memory 218256 kb
Host smart-40a57200-f276-4d86-8102-8c39163fb2aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489796444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3489796444
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2873717511
Short name T139
Test name
Test status
Simulation time 105014764 ps
CPU time 2.82 seconds
Started Jun 09 01:26:05 PM PDT 24
Finished Jun 09 01:26:08 PM PDT 24
Peak memory 222424 kb
Host smart-cf239de5-3f69-464c-ad99-088c374f0b58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873717511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.2873717511
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3581091189
Short name T212
Test name
Test status
Simulation time 24929706 ps
CPU time 0.94 seconds
Started Jun 09 01:29:01 PM PDT 24
Finished Jun 09 01:29:02 PM PDT 24
Peak memory 209012 kb
Host smart-d409b3d0-973a-445a-bd2f-ae3fb5c1ccce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581091189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3581091189
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.3244005483
Short name T3
Test name
Test status
Simulation time 29880550 ps
CPU time 0.77 seconds
Started Jun 09 01:29:46 PM PDT 24
Finished Jun 09 01:29:47 PM PDT 24
Peak memory 208976 kb
Host smart-6ad58be4-357e-4f7a-b3f9-2fcb2d4d54ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244005483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.3244005483
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.2117996645
Short name T211
Test name
Test status
Simulation time 47787832 ps
CPU time 0.86 seconds
Started Jun 09 01:29:59 PM PDT 24
Finished Jun 09 01:30:00 PM PDT 24
Peak memory 209000 kb
Host smart-bc27d059-e1c0-4200-8c6c-2ba617091c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117996645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.2117996645
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.4269486755
Short name T210
Test name
Test status
Simulation time 27002715 ps
CPU time 0.83 seconds
Started Jun 09 01:30:24 PM PDT 24
Finished Jun 09 01:30:26 PM PDT 24
Peak memory 209076 kb
Host smart-6361565c-8f23-4c56-9901-e6f63b02589d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269486755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.4269486755
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2593721522
Short name T116
Test name
Test status
Simulation time 237116382 ps
CPU time 3.28 seconds
Started Jun 09 01:25:15 PM PDT 24
Finished Jun 09 01:25:18 PM PDT 24
Peak memory 218152 kb
Host smart-461be213-5343-40ec-bc2d-052ab7d2c91d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593721522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2593721522
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.3448955035
Short name T42
Test name
Test status
Simulation time 172238326783 ps
CPU time 656.81 seconds
Started Jun 09 01:31:10 PM PDT 24
Finished Jun 09 01:42:07 PM PDT 24
Peak memory 279984 kb
Host smart-05ebd1b1-745f-44d6-b37e-f1ec53a50935
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3448955035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.3448955035
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.3259881462
Short name T21
Test name
Test status
Simulation time 23873088 ps
CPU time 1.3 seconds
Started Jun 09 01:29:42 PM PDT 24
Finished Jun 09 01:29:43 PM PDT 24
Peak memory 213832 kb
Host smart-d13f49c7-43eb-4af5-a588-36d7aca6f63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259881462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3259881462
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.443670197
Short name T59
Test name
Test status
Simulation time 43367276 ps
CPU time 1.44 seconds
Started Jun 09 01:32:25 PM PDT 24
Finished Jun 09 01:32:27 PM PDT 24
Peak memory 213768 kb
Host smart-811fcd0d-0adb-42dd-9c35-502bc32db464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443670197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.443670197
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.4044083839
Short name T196
Test name
Test status
Simulation time 46638232 ps
CPU time 1.03 seconds
Started Jun 09 01:24:44 PM PDT 24
Finished Jun 09 01:24:45 PM PDT 24
Peak memory 218096 kb
Host smart-e1fefcac-5186-4323-9538-b2566ede821c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044083839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.4044083839
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1247224284
Short name T879
Test name
Test status
Simulation time 67243351 ps
CPU time 1.73 seconds
Started Jun 09 01:24:45 PM PDT 24
Finished Jun 09 01:24:48 PM PDT 24
Peak memory 209964 kb
Host smart-d5fb68e5-79d0-4f2d-b97c-55f89f1a3f17
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247224284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.1247224284
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.768359801
Short name T188
Test name
Test status
Simulation time 42410359 ps
CPU time 1.02 seconds
Started Jun 09 01:24:40 PM PDT 24
Finished Jun 09 01:24:41 PM PDT 24
Peak memory 210424 kb
Host smart-d63dcc8b-dacc-4878-abcc-13b7abf696c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768359801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset
.768359801
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3807822497
Short name T170
Test name
Test status
Simulation time 36960463 ps
CPU time 1.02 seconds
Started Jun 09 01:24:44 PM PDT 24
Finished Jun 09 01:24:46 PM PDT 24
Peak memory 218196 kb
Host smart-b34899d8-a37b-48a4-bb6d-93fbeb077b23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807822497 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3807822497
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.4074906529
Short name T191
Test name
Test status
Simulation time 48346921 ps
CPU time 1.03 seconds
Started Jun 09 01:24:39 PM PDT 24
Finished Jun 09 01:24:40 PM PDT 24
Peak memory 218152 kb
Host smart-ac0c55cc-b7bf-4ac9-974a-5dff74ce044f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074906529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.4074906529
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2856944040
Short name T145
Test name
Test status
Simulation time 67733794 ps
CPU time 1.04 seconds
Started Jun 09 01:24:41 PM PDT 24
Finished Jun 09 01:24:42 PM PDT 24
Peak memory 209832 kb
Host smart-0b95c352-6a92-4d35-897c-148bab6c0637
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856944040 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.2856944040
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2447963503
Short name T902
Test name
Test status
Simulation time 1675795977 ps
CPU time 4.15 seconds
Started Jun 09 01:24:39 PM PDT 24
Finished Jun 09 01:24:43 PM PDT 24
Peak memory 209852 kb
Host smart-1d59382c-dd09-4e77-a8d7-ff85d2e77aba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447963503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.2447963503
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3920291441
Short name T967
Test name
Test status
Simulation time 965746430 ps
CPU time 9.52 seconds
Started Jun 09 01:24:38 PM PDT 24
Finished Jun 09 01:24:48 PM PDT 24
Peak memory 209868 kb
Host smart-655deb52-d3c3-4502-88a4-d0281e3c25ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920291441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.3920291441
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3998077402
Short name T934
Test name
Test status
Simulation time 453464865 ps
CPU time 1.6 seconds
Started Jun 09 01:24:22 PM PDT 24
Finished Jun 09 01:24:24 PM PDT 24
Peak memory 218080 kb
Host smart-162616e6-df84-4a08-aa9e-57b6e81adada
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998077402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3998077402
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3426407474
Short name T940
Test name
Test status
Simulation time 221308767 ps
CPU time 1.59 seconds
Started Jun 09 01:24:39 PM PDT 24
Finished Jun 09 01:24:41 PM PDT 24
Peak memory 218240 kb
Host smart-eaf6e6b4-519a-4db2-8110-52128a8abe7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342640
7474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3426407474
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1645197953
Short name T897
Test name
Test status
Simulation time 37069314 ps
CPU time 1.49 seconds
Started Jun 09 01:24:27 PM PDT 24
Finished Jun 09 01:24:29 PM PDT 24
Peak memory 209920 kb
Host smart-d31cb174-7012-4024-a75c-cb7ce3788d0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645197953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.1645197953
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2666034423
Short name T898
Test name
Test status
Simulation time 18156227 ps
CPU time 1.26 seconds
Started Jun 09 01:24:38 PM PDT 24
Finished Jun 09 01:24:40 PM PDT 24
Peak memory 209948 kb
Host smart-b3f87ca0-0948-41b1-a149-75628a30974b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666034423 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.2666034423
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1481949763
Short name T881
Test name
Test status
Simulation time 35058955 ps
CPU time 1.28 seconds
Started Jun 09 01:25:01 PM PDT 24
Finished Jun 09 01:25:02 PM PDT 24
Peak memory 210028 kb
Host smart-99d1b125-1ffd-4fb6-80ab-e1c7cd9626d5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481949763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.1481949763
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1729432818
Short name T995
Test name
Test status
Simulation time 87798941 ps
CPU time 1.82 seconds
Started Jun 09 01:25:01 PM PDT 24
Finished Jun 09 01:25:03 PM PDT 24
Peak memory 209940 kb
Host smart-34518294-1386-4686-a236-a43cac1822ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729432818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.1729432818
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2714896637
Short name T880
Test name
Test status
Simulation time 32095803 ps
CPU time 1.03 seconds
Started Jun 09 01:25:02 PM PDT 24
Finished Jun 09 01:25:03 PM PDT 24
Peak memory 212140 kb
Host smart-47e89352-f8b3-4c5e-9b75-e1b294b040be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714896637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.2714896637
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.4284470994
Short name T972
Test name
Test status
Simulation time 184963789 ps
CPU time 1.09 seconds
Started Jun 09 01:25:12 PM PDT 24
Finished Jun 09 01:25:14 PM PDT 24
Peak memory 219604 kb
Host smart-7c61e323-c5ec-4050-bf78-51b1ead3cc83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284470994 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.4284470994
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1647039723
Short name T935
Test name
Test status
Simulation time 16555944 ps
CPU time 1.12 seconds
Started Jun 09 01:25:01 PM PDT 24
Finished Jun 09 01:25:02 PM PDT 24
Peak memory 218144 kb
Host smart-be6ef68a-f674-4387-a6b0-417a349f69dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647039723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1647039723
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.13266634
Short name T889
Test name
Test status
Simulation time 58486341 ps
CPU time 2.1 seconds
Started Jun 09 01:25:01 PM PDT 24
Finished Jun 09 01:25:03 PM PDT 24
Peak memory 209404 kb
Host smart-7232d56a-b639-4625-a7ad-e6aa98245048
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13266634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_alert_test.13266634
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1054539275
Short name T903
Test name
Test status
Simulation time 448565273 ps
CPU time 11.81 seconds
Started Jun 09 01:24:55 PM PDT 24
Finished Jun 09 01:25:07 PM PDT 24
Peak memory 209632 kb
Host smart-cf202326-5de1-4979-8dc0-dfcb690227a0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054539275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1054539275
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.231680168
Short name T208
Test name
Test status
Simulation time 2714349907 ps
CPU time 15.14 seconds
Started Jun 09 01:24:49 PM PDT 24
Finished Jun 09 01:25:04 PM PDT 24
Peak memory 218192 kb
Host smart-ca07e7de-8ba9-46ed-a680-0dc8c915fd1b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231680168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.231680168
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1370040579
Short name T121
Test name
Test status
Simulation time 269634504 ps
CPU time 6.02 seconds
Started Jun 09 01:24:47 PM PDT 24
Finished Jun 09 01:24:54 PM PDT 24
Peak memory 218048 kb
Host smart-9c73241c-bdca-4778-a411-13fbab9baf18
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370040579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1370040579
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2964283643
Short name T950
Test name
Test status
Simulation time 339724750 ps
CPU time 2.19 seconds
Started Jun 09 01:24:54 PM PDT 24
Finished Jun 09 01:24:56 PM PDT 24
Peak memory 219328 kb
Host smart-cd604816-28c6-441c-9161-4ca804d28f1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296428
3643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2964283643
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1003558534
Short name T914
Test name
Test status
Simulation time 113426755 ps
CPU time 1.22 seconds
Started Jun 09 01:24:49 PM PDT 24
Finished Jun 09 01:24:50 PM PDT 24
Peak memory 209876 kb
Host smart-466f6917-459d-40dd-8850-62b91711caa0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003558534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1003558534
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.44479243
Short name T203
Test name
Test status
Simulation time 15536627 ps
CPU time 0.99 seconds
Started Jun 09 01:24:53 PM PDT 24
Finished Jun 09 01:24:54 PM PDT 24
Peak memory 209972 kb
Host smart-46e07aed-b5ee-4383-9af0-bf9d28b44fc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44479243 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.44479243
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2792073235
Short name T910
Test name
Test status
Simulation time 54489093 ps
CPU time 1.23 seconds
Started Jun 09 01:25:05 PM PDT 24
Finished Jun 09 01:25:06 PM PDT 24
Peak memory 211840 kb
Host smart-3742a630-e893-4f16-adb3-8af5253a32e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792073235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.2792073235
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.887016107
Short name T114
Test name
Test status
Simulation time 210766571 ps
CPU time 2.18 seconds
Started Jun 09 01:25:00 PM PDT 24
Finished Jun 09 01:25:02 PM PDT 24
Peak memory 218236 kb
Host smart-e1a3f44f-44e4-4fc6-89c0-4f8d998cec0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887016107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.887016107
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1500622383
Short name T939
Test name
Test status
Simulation time 22641421 ps
CPU time 1.14 seconds
Started Jun 09 01:26:33 PM PDT 24
Finished Jun 09 01:26:34 PM PDT 24
Peak memory 219160 kb
Host smart-cdaacffa-21bd-414c-a835-692f9a76bc0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500622383 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1500622383
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.4152605018
Short name T192
Test name
Test status
Simulation time 24950257 ps
CPU time 0.86 seconds
Started Jun 09 01:26:31 PM PDT 24
Finished Jun 09 01:26:32 PM PDT 24
Peak memory 209940 kb
Host smart-eb6d6b13-2e4c-4ee0-ba31-fd69b6a77e81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152605018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.4152605018
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.764320141
Short name T200
Test name
Test status
Simulation time 27544942 ps
CPU time 1.1 seconds
Started Jun 09 01:26:35 PM PDT 24
Finished Jun 09 01:26:36 PM PDT 24
Peak memory 218124 kb
Host smart-0ed2f00e-6ef9-45f4-8206-dd938c32c351
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764320141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.764320141
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1128360707
Short name T907
Test name
Test status
Simulation time 233322602 ps
CPU time 3.24 seconds
Started Jun 09 01:26:32 PM PDT 24
Finished Jun 09 01:26:36 PM PDT 24
Peak memory 218124 kb
Host smart-b2f533a9-4c42-4a00-b58e-f1d6149c4b15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128360707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1128360707
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1859944337
Short name T958
Test name
Test status
Simulation time 43846605 ps
CPU time 1.76 seconds
Started Jun 09 01:26:32 PM PDT 24
Finished Jun 09 01:26:34 PM PDT 24
Peak memory 218144 kb
Host smart-ef5ed98f-24db-475f-b738-dc23099c630e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859944337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1859944337
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1586670644
Short name T948
Test name
Test status
Simulation time 16657466 ps
CPU time 1.02 seconds
Started Jun 09 01:26:37 PM PDT 24
Finished Jun 09 01:26:39 PM PDT 24
Peak memory 218284 kb
Host smart-5c22a606-c5ff-4e72-a022-f1d1485b015e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586670644 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1586670644
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3232303688
Short name T944
Test name
Test status
Simulation time 46172505 ps
CPU time 1.02 seconds
Started Jun 09 01:26:32 PM PDT 24
Finished Jun 09 01:26:33 PM PDT 24
Peak memory 209952 kb
Host smart-6e1bbc45-317f-4cd3-9ccb-987fc4a75d6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232303688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3232303688
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2505978681
Short name T901
Test name
Test status
Simulation time 42152118 ps
CPU time 1.8 seconds
Started Jun 09 01:26:31 PM PDT 24
Finished Jun 09 01:26:33 PM PDT 24
Peak memory 218188 kb
Host smart-7d8afad9-6afe-4dc6-bf3d-14aaec74e3d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505978681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.2505978681
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1530613323
Short name T991
Test name
Test status
Simulation time 157389939 ps
CPU time 2.4 seconds
Started Jun 09 01:26:36 PM PDT 24
Finished Jun 09 01:26:39 PM PDT 24
Peak memory 218136 kb
Host smart-776f0e42-b71c-4192-83db-a69ba749bd30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530613323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1530613323
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2753848857
Short name T938
Test name
Test status
Simulation time 98041531 ps
CPU time 2.18 seconds
Started Jun 09 01:26:31 PM PDT 24
Finished Jun 09 01:26:33 PM PDT 24
Peak memory 222760 kb
Host smart-30c0dcfc-6185-443c-9a31-2e77d366cec1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753848857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.2753848857
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2533691934
Short name T977
Test name
Test status
Simulation time 85103526 ps
CPU time 2.46 seconds
Started Jun 09 01:26:36 PM PDT 24
Finished Jun 09 01:26:39 PM PDT 24
Peak memory 220456 kb
Host smart-5eb35490-d329-4555-bb70-44de9048451b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533691934 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2533691934
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3353973688
Short name T122
Test name
Test status
Simulation time 300668915 ps
CPU time 1.08 seconds
Started Jun 09 01:26:37 PM PDT 24
Finished Jun 09 01:26:39 PM PDT 24
Peak memory 209912 kb
Host smart-a0ff581d-a326-4a1c-b6b6-61bd3ade79d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353973688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3353973688
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1997103154
Short name T996
Test name
Test status
Simulation time 588622708 ps
CPU time 3.15 seconds
Started Jun 09 01:26:37 PM PDT 24
Finished Jun 09 01:26:40 PM PDT 24
Peak memory 218372 kb
Host smart-3ae86294-b68d-4177-9f58-90ffda21a8a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997103154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1997103154
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2138616043
Short name T137
Test name
Test status
Simulation time 218044113 ps
CPU time 2.07 seconds
Started Jun 09 01:26:40 PM PDT 24
Finished Jun 09 01:26:42 PM PDT 24
Peak memory 222652 kb
Host smart-2f406df9-d07b-4ca7-9261-58fe13e056ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138616043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.2138616043
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1924356835
Short name T964
Test name
Test status
Simulation time 56252422 ps
CPU time 1.16 seconds
Started Jun 09 01:26:39 PM PDT 24
Finished Jun 09 01:26:40 PM PDT 24
Peak memory 219244 kb
Host smart-288de7b6-209e-464f-b7a3-5d98b4f9bacb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924356835 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1924356835
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.597706560
Short name T900
Test name
Test status
Simulation time 127187165 ps
CPU time 0.9 seconds
Started Jun 09 01:26:37 PM PDT 24
Finished Jun 09 01:26:39 PM PDT 24
Peak memory 209944 kb
Host smart-cf35004c-5f0f-4a7b-b978-a6df63f8b77d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597706560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.597706560
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2234115539
Short name T960
Test name
Test status
Simulation time 112141842 ps
CPU time 1.17 seconds
Started Jun 09 01:26:39 PM PDT 24
Finished Jun 09 01:26:40 PM PDT 24
Peak memory 209748 kb
Host smart-19465ce3-932c-4afa-8f15-7d6a9ede3586
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234115539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2234115539
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.95877795
Short name T131
Test name
Test status
Simulation time 359303705 ps
CPU time 2.56 seconds
Started Jun 09 01:26:40 PM PDT 24
Finished Jun 09 01:26:42 PM PDT 24
Peak memory 219312 kb
Host smart-564b8507-932e-4568-ac32-c87706a4a66c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95877795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.95877795
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.4022621207
Short name T937
Test name
Test status
Simulation time 52517127 ps
CPU time 1.67 seconds
Started Jun 09 01:26:42 PM PDT 24
Finished Jun 09 01:26:44 PM PDT 24
Peak memory 219168 kb
Host smart-51e8507d-81b8-4cad-8988-bb9e9bbd4f98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022621207 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.4022621207
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2784027104
Short name T119
Test name
Test status
Simulation time 45531831 ps
CPU time 0.85 seconds
Started Jun 09 01:26:44 PM PDT 24
Finished Jun 09 01:26:45 PM PDT 24
Peak memory 209612 kb
Host smart-0c760ee7-51d3-473a-b8ce-34005c9ce158
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784027104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2784027104
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.4271400215
Short name T929
Test name
Test status
Simulation time 249359893 ps
CPU time 1.3 seconds
Started Jun 09 01:26:44 PM PDT 24
Finished Jun 09 01:26:45 PM PDT 24
Peak memory 218120 kb
Host smart-29e55902-3ff3-4890-af8f-1d5154fcf6b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271400215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.4271400215
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2333792750
Short name T112
Test name
Test status
Simulation time 156848739 ps
CPU time 4.82 seconds
Started Jun 09 01:26:37 PM PDT 24
Finished Jun 09 01:26:42 PM PDT 24
Peak memory 218144 kb
Host smart-6b070736-9cfc-404d-a83c-d0766939d55f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333792750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2333792750
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2608527971
Short name T132
Test name
Test status
Simulation time 124921632 ps
CPU time 2.15 seconds
Started Jun 09 01:26:45 PM PDT 24
Finished Jun 09 01:26:48 PM PDT 24
Peak memory 218104 kb
Host smart-8f9b30e9-f2f0-47bf-8608-27231599f3c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608527971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2608527971
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.800548594
Short name T888
Test name
Test status
Simulation time 303115236 ps
CPU time 1.47 seconds
Started Jun 09 01:26:44 PM PDT 24
Finished Jun 09 01:26:45 PM PDT 24
Peak memory 218312 kb
Host smart-c9316522-65ca-4d83-a24c-8e136b7b1d2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800548594 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.800548594
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2946910475
Short name T992
Test name
Test status
Simulation time 80596253 ps
CPU time 0.83 seconds
Started Jun 09 01:26:43 PM PDT 24
Finished Jun 09 01:26:44 PM PDT 24
Peak memory 209744 kb
Host smart-207a1867-6a10-42f5-91a8-aa5940e0f8a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946910475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2946910475
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.852925441
Short name T956
Test name
Test status
Simulation time 174430285 ps
CPU time 1.43 seconds
Started Jun 09 01:26:46 PM PDT 24
Finished Jun 09 01:26:48 PM PDT 24
Peak memory 211824 kb
Host smart-f181fcea-3181-48a2-9e7a-21ffa64e43fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852925441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.852925441
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3089941483
Short name T931
Test name
Test status
Simulation time 506944846 ps
CPU time 3.9 seconds
Started Jun 09 01:26:44 PM PDT 24
Finished Jun 09 01:26:48 PM PDT 24
Peak memory 218196 kb
Host smart-68f27be0-d609-4db8-888f-9464cc5780a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089941483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.3089941483
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3133040499
Short name T128
Test name
Test status
Simulation time 247962624 ps
CPU time 2.8 seconds
Started Jun 09 01:26:43 PM PDT 24
Finished Jun 09 01:26:46 PM PDT 24
Peak memory 223040 kb
Host smart-6cc0da83-fb11-4669-98c5-441c6843e255
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133040499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.3133040499
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.4004392135
Short name T113
Test name
Test status
Simulation time 21389292 ps
CPU time 1.35 seconds
Started Jun 09 01:26:48 PM PDT 24
Finished Jun 09 01:26:50 PM PDT 24
Peak memory 218204 kb
Host smart-459436be-e703-4065-99c4-01b72907686d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004392135 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.4004392135
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1450778696
Short name T963
Test name
Test status
Simulation time 25403963 ps
CPU time 0.85 seconds
Started Jun 09 01:26:48 PM PDT 24
Finished Jun 09 01:26:49 PM PDT 24
Peak memory 209972 kb
Host smart-9471fdd9-0ef0-4289-b9ce-f6cc01181a54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450778696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1450778696
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1425430076
Short name T204
Test name
Test status
Simulation time 370142802 ps
CPU time 1.44 seconds
Started Jun 09 01:26:50 PM PDT 24
Finished Jun 09 01:26:52 PM PDT 24
Peak memory 209980 kb
Host smart-bf7a6b02-a9d5-4f22-b2c6-8e6b7bc7a239
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425430076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.1425430076
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.913947488
Short name T965
Test name
Test status
Simulation time 76030242 ps
CPU time 3 seconds
Started Jun 09 01:26:50 PM PDT 24
Finished Jun 09 01:26:54 PM PDT 24
Peak memory 218144 kb
Host smart-5121fb14-cd97-4f2d-b67e-e470bb27d6ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913947488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.913947488
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2516446978
Short name T117
Test name
Test status
Simulation time 64468471 ps
CPU time 1.51 seconds
Started Jun 09 01:26:49 PM PDT 24
Finished Jun 09 01:26:51 PM PDT 24
Peak memory 219584 kb
Host smart-84cfa6d5-1051-4e7b-bae9-3d3ff72a816b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516446978 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2516446978
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1588311047
Short name T199
Test name
Test status
Simulation time 18267403 ps
CPU time 1.14 seconds
Started Jun 09 01:26:51 PM PDT 24
Finished Jun 09 01:26:53 PM PDT 24
Peak memory 209948 kb
Host smart-a3b7617b-0c7f-45c4-be2d-709a3e5174f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588311047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1588311047
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.289009235
Short name T990
Test name
Test status
Simulation time 63140430 ps
CPU time 1.05 seconds
Started Jun 09 01:26:50 PM PDT 24
Finished Jun 09 01:26:51 PM PDT 24
Peak memory 209768 kb
Host smart-120e48d6-79ad-4ca7-b459-547adf0fce53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289009235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_same_csr_outstanding.289009235
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.847068984
Short name T127
Test name
Test status
Simulation time 100960958 ps
CPU time 1.27 seconds
Started Jun 09 01:26:53 PM PDT 24
Finished Jun 09 01:26:54 PM PDT 24
Peak memory 218112 kb
Host smart-f02913d8-1bf8-4c4e-93cc-ee7de7aac964
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847068984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.847068984
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1140498414
Short name T899
Test name
Test status
Simulation time 41400197 ps
CPU time 1.11 seconds
Started Jun 09 01:26:55 PM PDT 24
Finished Jun 09 01:26:56 PM PDT 24
Peak memory 219284 kb
Host smart-9e5e6c38-ca67-4e22-b9cc-5cf5358167d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140498414 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1140498414
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.111611303
Short name T927
Test name
Test status
Simulation time 14485474 ps
CPU time 1.05 seconds
Started Jun 09 01:26:55 PM PDT 24
Finished Jun 09 01:26:57 PM PDT 24
Peak memory 209336 kb
Host smart-68f7d03f-51ce-4dd3-96eb-ff1f9847a99d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111611303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.111611303
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1799711821
Short name T970
Test name
Test status
Simulation time 13844705 ps
CPU time 0.99 seconds
Started Jun 09 01:26:53 PM PDT 24
Finished Jun 09 01:26:54 PM PDT 24
Peak memory 218128 kb
Host smart-2d7d1d01-a46d-4df8-b913-f5d5d116bb88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799711821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.1799711821
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1159919419
Short name T979
Test name
Test status
Simulation time 371404225 ps
CPU time 3.35 seconds
Started Jun 09 01:26:54 PM PDT 24
Finished Jun 09 01:26:58 PM PDT 24
Peak memory 219156 kb
Host smart-4221c19c-9d4b-4acb-a0c0-41d8f5283bc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159919419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1159919419
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.612979783
Short name T129
Test name
Test status
Simulation time 192430496 ps
CPU time 2 seconds
Started Jun 09 01:26:54 PM PDT 24
Finished Jun 09 01:26:57 PM PDT 24
Peak memory 222216 kb
Host smart-1503f33a-706e-4229-bb7e-716129859b15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612979783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg_
err.612979783
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2009085745
Short name T890
Test name
Test status
Simulation time 26468620 ps
CPU time 1.52 seconds
Started Jun 09 01:26:55 PM PDT 24
Finished Jun 09 01:26:57 PM PDT 24
Peak memory 218408 kb
Host smart-59ee5428-3a18-4ed1-aaa3-7d61418c396c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009085745 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2009085745
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1176760620
Short name T158
Test name
Test status
Simulation time 62808390 ps
CPU time 0.96 seconds
Started Jun 09 01:26:56 PM PDT 24
Finished Jun 09 01:26:57 PM PDT 24
Peak memory 209940 kb
Host smart-3d820391-acf4-4db6-8679-ce79100bf3a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176760620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1176760620
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1818703697
Short name T201
Test name
Test status
Simulation time 40435481 ps
CPU time 1.37 seconds
Started Jun 09 01:26:54 PM PDT 24
Finished Jun 09 01:26:55 PM PDT 24
Peak memory 212016 kb
Host smart-882dad08-da1f-4507-8511-37b66dd1ec33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818703697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.1818703697
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1317804407
Short name T993
Test name
Test status
Simulation time 173973220 ps
CPU time 2.1 seconds
Started Jun 09 01:26:56 PM PDT 24
Finished Jun 09 01:26:58 PM PDT 24
Peak memory 218140 kb
Host smart-7e72993d-f7dd-449a-b5c1-7407acbc6b73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317804407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.1317804407
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3480897122
Short name T138
Test name
Test status
Simulation time 268897208 ps
CPU time 1.91 seconds
Started Jun 09 01:26:56 PM PDT 24
Finished Jun 09 01:26:58 PM PDT 24
Peak memory 222640 kb
Host smart-d5d424b8-237b-45f4-8e27-3f66eb3964b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480897122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.3480897122
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2063833124
Short name T193
Test name
Test status
Simulation time 57296753 ps
CPU time 1.33 seconds
Started Jun 09 01:25:22 PM PDT 24
Finished Jun 09 01:25:24 PM PDT 24
Peak memory 209948 kb
Host smart-c36fdc29-9ea8-4153-86f3-ba33e39c89fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063833124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.2063833124
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3311891833
Short name T893
Test name
Test status
Simulation time 50357179 ps
CPU time 1.99 seconds
Started Jun 09 01:25:21 PM PDT 24
Finished Jun 09 01:25:23 PM PDT 24
Peak memory 209932 kb
Host smart-709ffc3f-cfbe-45fc-9056-ddb0efdb7b24
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311891833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.3311891833
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.330366447
Short name T195
Test name
Test status
Simulation time 23194135 ps
CPU time 1.09 seconds
Started Jun 09 01:25:16 PM PDT 24
Finished Jun 09 01:25:17 PM PDT 24
Peak memory 212108 kb
Host smart-900f331d-a9b2-4844-bbb3-122f0459b281
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330366447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_reset
.330366447
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2520670930
Short name T955
Test name
Test status
Simulation time 26851420 ps
CPU time 1.48 seconds
Started Jun 09 01:25:22 PM PDT 24
Finished Jun 09 01:25:24 PM PDT 24
Peak memory 218452 kb
Host smart-c9bad2b3-7568-4353-85f3-1c74d904376e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520670930 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2520670930
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1339623158
Short name T197
Test name
Test status
Simulation time 53828885 ps
CPU time 0.88 seconds
Started Jun 09 01:25:22 PM PDT 24
Finished Jun 09 01:25:23 PM PDT 24
Peak memory 209944 kb
Host smart-06c06ec6-11a3-48d7-9d4d-b3304f14c017
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339623158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1339623158
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1696092187
Short name T144
Test name
Test status
Simulation time 13478494 ps
CPU time 0.85 seconds
Started Jun 09 01:25:15 PM PDT 24
Finished Jun 09 01:25:17 PM PDT 24
Peak memory 209616 kb
Host smart-03d4bd4e-0d01-4c17-8837-fa923ef7c50b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696092187 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1696092187
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3212570350
Short name T891
Test name
Test status
Simulation time 11265923505 ps
CPU time 13.88 seconds
Started Jun 09 01:25:17 PM PDT 24
Finished Jun 09 01:25:31 PM PDT 24
Peak memory 217996 kb
Host smart-38c10264-17bc-4a69-b394-a67b0cf7ba1a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212570350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.3212570350
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2845811268
Short name T949
Test name
Test status
Simulation time 6088177470 ps
CPU time 15.88 seconds
Started Jun 09 01:25:15 PM PDT 24
Finished Jun 09 01:25:32 PM PDT 24
Peak memory 210160 kb
Host smart-872a1e03-e652-416c-bab8-f6c513e8d0fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845811268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.2845811268
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4258040605
Short name T912
Test name
Test status
Simulation time 347814929 ps
CPU time 2.67 seconds
Started Jun 09 01:25:16 PM PDT 24
Finished Jun 09 01:25:19 PM PDT 24
Peak memory 211352 kb
Host smart-2e505085-e364-4ca1-9fa2-c2256f5bf268
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258040605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.4258040605
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2301543127
Short name T946
Test name
Test status
Simulation time 89785344 ps
CPU time 3.35 seconds
Started Jun 09 01:25:13 PM PDT 24
Finished Jun 09 01:25:17 PM PDT 24
Peak memory 219140 kb
Host smart-90ba0a54-8fe9-4757-9770-a0184d010e24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230154
3127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2301543127
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2992228816
Short name T143
Test name
Test status
Simulation time 174561285 ps
CPU time 1.48 seconds
Started Jun 09 01:25:16 PM PDT 24
Finished Jun 09 01:25:18 PM PDT 24
Peak memory 209916 kb
Host smart-201d5bc6-03ae-45e4-b953-a424390b0c9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992228816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.2992228816
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.512453237
Short name T118
Test name
Test status
Simulation time 22305661 ps
CPU time 1.27 seconds
Started Jun 09 01:25:19 PM PDT 24
Finished Jun 09 01:25:20 PM PDT 24
Peak memory 212260 kb
Host smart-2ae5a902-b13a-42ec-b554-f31cb2521e5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512453237 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.512453237
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2969300585
Short name T922
Test name
Test status
Simulation time 19919522 ps
CPU time 1.25 seconds
Started Jun 09 01:25:21 PM PDT 24
Finished Jun 09 01:25:23 PM PDT 24
Peak memory 211992 kb
Host smart-ec096e26-c234-417f-bc96-7bbb9bca3a9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969300585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.2969300585
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.314546780
Short name T983
Test name
Test status
Simulation time 72777146 ps
CPU time 1.37 seconds
Started Jun 09 01:25:15 PM PDT 24
Finished Jun 09 01:25:17 PM PDT 24
Peak memory 218476 kb
Host smart-ad85e1fe-8577-44e1-8582-907c3f97ea9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314546780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.314546780
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1497323958
Short name T190
Test name
Test status
Simulation time 139161238 ps
CPU time 1.4 seconds
Started Jun 09 01:25:38 PM PDT 24
Finished Jun 09 01:25:40 PM PDT 24
Peak memory 210236 kb
Host smart-249efb08-e588-4f27-9ef6-b8a4e6e669c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497323958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.1497323958
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1734776848
Short name T877
Test name
Test status
Simulation time 152714705 ps
CPU time 1.7 seconds
Started Jun 09 01:25:32 PM PDT 24
Finished Jun 09 01:25:34 PM PDT 24
Peak memory 209932 kb
Host smart-d3cb9f40-bca0-426d-84cc-1a0ef57b80be
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734776848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.1734776848
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2527136189
Short name T885
Test name
Test status
Simulation time 16751648 ps
CPU time 1.21 seconds
Started Jun 09 01:25:32 PM PDT 24
Finished Jun 09 01:25:34 PM PDT 24
Peak memory 212056 kb
Host smart-29705411-68bb-4116-93df-490cbdcaa138
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527136189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.2527136189
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.4192818339
Short name T966
Test name
Test status
Simulation time 30767008 ps
CPU time 1.7 seconds
Started Jun 09 01:25:39 PM PDT 24
Finished Jun 09 01:25:41 PM PDT 24
Peak memory 220124 kb
Host smart-28446236-91d7-4663-8fde-232d619fdc54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192818339 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.4192818339
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3797053449
Short name T988
Test name
Test status
Simulation time 13235801 ps
CPU time 1 seconds
Started Jun 09 01:25:31 PM PDT 24
Finished Jun 09 01:25:32 PM PDT 24
Peak memory 209980 kb
Host smart-2d1fbe6b-aeee-4060-8a77-f61b99b04570
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797053449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.3797053449
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.4090579632
Short name T876
Test name
Test status
Simulation time 106652617 ps
CPU time 1.16 seconds
Started Jun 09 01:25:27 PM PDT 24
Finished Jun 09 01:25:28 PM PDT 24
Peak memory 209936 kb
Host smart-ea9c6b18-2503-4255-ac23-90aeaef48b9b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090579632 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.4090579632
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3940210927
Short name T916
Test name
Test status
Simulation time 733906070 ps
CPU time 6.88 seconds
Started Jun 09 01:25:22 PM PDT 24
Finished Jun 09 01:25:29 PM PDT 24
Peak memory 209524 kb
Host smart-56e17727-9e0d-4803-aff5-6da7d1bf832c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940210927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3940210927
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.16141236
Short name T883
Test name
Test status
Simulation time 8955280266 ps
CPU time 16.26 seconds
Started Jun 09 01:25:22 PM PDT 24
Finished Jun 09 01:25:38 PM PDT 24
Peak memory 209940 kb
Host smart-26cf6026-6986-40f3-a257-2b4fbbddf306
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16141236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.16141236
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3392555439
Short name T975
Test name
Test status
Simulation time 1844557632 ps
CPU time 2.71 seconds
Started Jun 09 01:25:20 PM PDT 24
Finished Jun 09 01:25:23 PM PDT 24
Peak memory 211508 kb
Host smart-6af0a664-572a-400a-b212-e6f07d9f6add
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392555439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3392555439
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3586463624
Short name T920
Test name
Test status
Simulation time 50325589 ps
CPU time 2.1 seconds
Started Jun 09 01:25:27 PM PDT 24
Finished Jun 09 01:25:30 PM PDT 24
Peak memory 219964 kb
Host smart-2dbbf052-53c0-4e9a-b9df-d62f11fa746e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358646
3624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3586463624
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3687739765
Short name T923
Test name
Test status
Simulation time 128793147 ps
CPU time 3.47 seconds
Started Jun 09 01:25:21 PM PDT 24
Finished Jun 09 01:25:25 PM PDT 24
Peak memory 218048 kb
Host smart-c12ee4fd-0487-485d-ad30-c80c461e1b9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687739765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.3687739765
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3808734614
Short name T202
Test name
Test status
Simulation time 16116496 ps
CPU time 1.18 seconds
Started Jun 09 01:25:21 PM PDT 24
Finished Jun 09 01:25:22 PM PDT 24
Peak memory 218056 kb
Host smart-0f8eae84-99e8-4cb3-9c98-d3a8f62afc4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808734614 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3808734614
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1753724260
Short name T971
Test name
Test status
Simulation time 218805023 ps
CPU time 1.88 seconds
Started Jun 09 01:25:35 PM PDT 24
Finished Jun 09 01:25:38 PM PDT 24
Peak memory 209908 kb
Host smart-9e7bb000-4b96-479f-a7dd-af43421b7ec6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753724260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.1753724260
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3388879093
Short name T110
Test name
Test status
Simulation time 24452962 ps
CPU time 1.64 seconds
Started Jun 09 01:25:27 PM PDT 24
Finished Jun 09 01:25:29 PM PDT 24
Peak memory 218584 kb
Host smart-3cf17d9a-7cb0-47be-ab50-6fc90ce23e95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388879093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.3388879093
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3784268180
Short name T933
Test name
Test status
Simulation time 60632387 ps
CPU time 1.19 seconds
Started Jun 09 01:25:53 PM PDT 24
Finished Jun 09 01:25:55 PM PDT 24
Peak memory 209952 kb
Host smart-889c91fe-9a0b-4a2e-998d-6d17a808a033
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784268180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.3784268180
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1266636669
Short name T997
Test name
Test status
Simulation time 72370784 ps
CPU time 1.32 seconds
Started Jun 09 01:25:48 PM PDT 24
Finished Jun 09 01:25:50 PM PDT 24
Peak memory 209940 kb
Host smart-b4b8f1e9-c65b-4571-8867-04780ce557c9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266636669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.1266636669
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2198312148
Short name T194
Test name
Test status
Simulation time 46959215 ps
CPU time 1.01 seconds
Started Jun 09 01:25:43 PM PDT 24
Finished Jun 09 01:25:44 PM PDT 24
Peak memory 211120 kb
Host smart-c4ee02c0-0ddd-4a6e-bca1-9ba3d2f6fbc2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198312148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.2198312148
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.699873618
Short name T932
Test name
Test status
Simulation time 140995231 ps
CPU time 1.44 seconds
Started Jun 09 01:25:54 PM PDT 24
Finished Jun 09 01:25:55 PM PDT 24
Peak memory 219344 kb
Host smart-2aa69570-d7fe-4d64-b489-1686903dd4ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699873618 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.699873618
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2220295294
Short name T159
Test name
Test status
Simulation time 67350572 ps
CPU time 0.86 seconds
Started Jun 09 01:25:43 PM PDT 24
Finished Jun 09 01:25:44 PM PDT 24
Peak memory 209788 kb
Host smart-53974550-c90e-402e-91d2-9f101b39a236
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220295294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2220295294
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3816260925
Short name T882
Test name
Test status
Simulation time 217823227 ps
CPU time 0.98 seconds
Started Jun 09 01:25:46 PM PDT 24
Finished Jun 09 01:25:47 PM PDT 24
Peak memory 209832 kb
Host smart-d8aae777-6604-452e-98ff-08c63ac966f4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816260925 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3816260925
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1422180046
Short name T978
Test name
Test status
Simulation time 872533581 ps
CPU time 5.53 seconds
Started Jun 09 01:25:37 PM PDT 24
Finished Jun 09 01:25:43 PM PDT 24
Peak memory 209912 kb
Host smart-227683d3-10a7-4b28-9fc0-39f3289fef1c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422180046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.1422180046
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1309963369
Short name T945
Test name
Test status
Simulation time 907926751 ps
CPU time 18.27 seconds
Started Jun 09 01:25:37 PM PDT 24
Finished Jun 09 01:25:56 PM PDT 24
Peak memory 209664 kb
Host smart-403c6073-c512-431b-a142-b9cf5dc9158d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309963369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.1309963369
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3989106880
Short name T895
Test name
Test status
Simulation time 54152276 ps
CPU time 2.02 seconds
Started Jun 09 01:25:39 PM PDT 24
Finished Jun 09 01:25:41 PM PDT 24
Peak memory 218064 kb
Host smart-3fe511f9-e476-4be8-a711-19a2d37a97b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989106880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3989106880
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3694088726
Short name T961
Test name
Test status
Simulation time 123169306 ps
CPU time 4.17 seconds
Started Jun 09 01:25:46 PM PDT 24
Finished Jun 09 01:25:50 PM PDT 24
Peak memory 218208 kb
Host smart-add18dc2-54e4-4003-a460-58b92d91d20a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369408
8726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3694088726
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3238311949
Short name T887
Test name
Test status
Simulation time 393901418 ps
CPU time 2.93 seconds
Started Jun 09 01:25:39 PM PDT 24
Finished Jun 09 01:25:42 PM PDT 24
Peak memory 209856 kb
Host smart-eeedb65f-9913-457f-878c-b5d3fdcc5b63
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238311949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.3238311949
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3278969061
Short name T984
Test name
Test status
Simulation time 78670466 ps
CPU time 1.32 seconds
Started Jun 09 01:25:38 PM PDT 24
Finished Jun 09 01:25:40 PM PDT 24
Peak memory 218144 kb
Host smart-2f1ca3e4-ebe7-46d1-83ff-9e84222e9005
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278969061 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.3278969061
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.34467740
Short name T207
Test name
Test status
Simulation time 45630679 ps
CPU time 0.99 seconds
Started Jun 09 01:25:54 PM PDT 24
Finished Jun 09 01:25:55 PM PDT 24
Peak memory 210164 kb
Host smart-24e50bf3-b327-405e-bd62-7d7a51ff69e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34467740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_s
ame_csr_outstanding.34467740
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1242914306
Short name T941
Test name
Test status
Simulation time 46193669 ps
CPU time 3.29 seconds
Started Jun 09 01:25:46 PM PDT 24
Finished Jun 09 01:25:50 PM PDT 24
Peak memory 218144 kb
Host smart-9b8202a0-06fc-4d81-afbe-bf5f7769fc85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242914306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1242914306
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1083729208
Short name T130
Test name
Test status
Simulation time 112481859 ps
CPU time 2.97 seconds
Started Jun 09 01:25:42 PM PDT 24
Finished Jun 09 01:25:45 PM PDT 24
Peak memory 223044 kb
Host smart-172bba9f-08e3-4f4e-8edc-f111d9510369
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083729208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1083729208
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.507374728
Short name T999
Test name
Test status
Simulation time 17091982 ps
CPU time 1.24 seconds
Started Jun 09 01:26:02 PM PDT 24
Finished Jun 09 01:26:03 PM PDT 24
Peak memory 219776 kb
Host smart-5a8b4525-fa0f-49b4-b36c-63b9ee976533
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507374728 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.507374728
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1308819382
Short name T886
Test name
Test status
Simulation time 21692386 ps
CPU time 0.94 seconds
Started Jun 09 01:25:58 PM PDT 24
Finished Jun 09 01:25:59 PM PDT 24
Peak memory 209948 kb
Host smart-87686f93-a824-479a-a599-f63cc5842ac4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308819382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1308819382
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3219466438
Short name T909
Test name
Test status
Simulation time 64783849 ps
CPU time 1.09 seconds
Started Jun 09 01:25:53 PM PDT 24
Finished Jun 09 01:25:54 PM PDT 24
Peak memory 209852 kb
Host smart-5d71e2b7-deed-40df-a06a-0f7457874c08
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219466438 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.3219466438
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1716284923
Short name T973
Test name
Test status
Simulation time 1669671568 ps
CPU time 5.29 seconds
Started Jun 09 01:25:54 PM PDT 24
Finished Jun 09 01:26:00 PM PDT 24
Peak memory 209636 kb
Host smart-356cf10e-f7de-4f53-b785-cd56f20cf3b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716284923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1716284923
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3890606498
Short name T968
Test name
Test status
Simulation time 444566017 ps
CPU time 3.01 seconds
Started Jun 09 01:25:54 PM PDT 24
Finished Jun 09 01:25:57 PM PDT 24
Peak memory 211828 kb
Host smart-1fa87f4d-a73d-4f3f-b475-dc7308872f45
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890606498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3890606498
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2396291632
Short name T962
Test name
Test status
Simulation time 161969253 ps
CPU time 5.25 seconds
Started Jun 09 01:25:57 PM PDT 24
Finished Jun 09 01:26:02 PM PDT 24
Peak memory 219364 kb
Host smart-f13e4cd2-3876-4093-a390-06172edc7bfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239629
1632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2396291632
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.271225717
Short name T141
Test name
Test status
Simulation time 124974790 ps
CPU time 1.07 seconds
Started Jun 09 01:25:52 PM PDT 24
Finished Jun 09 01:25:54 PM PDT 24
Peak memory 209884 kb
Host smart-bb7c8867-230d-4847-b15a-c322c1d8d249
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271225717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.271225717
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2731365402
Short name T1000
Test name
Test status
Simulation time 141514438 ps
CPU time 1.38 seconds
Started Jun 09 01:25:54 PM PDT 24
Finished Jun 09 01:25:56 PM PDT 24
Peak memory 209968 kb
Host smart-f8bfb876-ad33-4699-b033-49f7b4ae7470
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731365402 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.2731365402
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.4075093321
Short name T905
Test name
Test status
Simulation time 37210431 ps
CPU time 1.38 seconds
Started Jun 09 01:25:59 PM PDT 24
Finished Jun 09 01:26:01 PM PDT 24
Peak memory 218152 kb
Host smart-f3d602a5-93d8-4346-a0d1-739b4772eac1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075093321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.4075093321
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.102779519
Short name T908
Test name
Test status
Simulation time 51276057 ps
CPU time 1.49 seconds
Started Jun 09 01:25:59 PM PDT 24
Finished Jun 09 01:26:00 PM PDT 24
Peak memory 219132 kb
Host smart-37abd340-d25e-4237-8a64-54ac81c2c5ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102779519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.102779519
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.288718259
Short name T135
Test name
Test status
Simulation time 129151853 ps
CPU time 2.49 seconds
Started Jun 09 01:25:59 PM PDT 24
Finished Jun 09 01:26:02 PM PDT 24
Peak memory 218156 kb
Host smart-a6260116-57e1-4dbc-a080-cfe2b22720f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288718259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_e
rr.288718259
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.834298328
Short name T959
Test name
Test status
Simulation time 27797998 ps
CPU time 1.05 seconds
Started Jun 09 01:26:08 PM PDT 24
Finished Jun 09 01:26:09 PM PDT 24
Peak memory 209632 kb
Host smart-5a3c7f7b-274b-445f-8e6f-c11650f160e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834298328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.834298328
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2225900895
Short name T981
Test name
Test status
Simulation time 249631899 ps
CPU time 2.38 seconds
Started Jun 09 01:25:59 PM PDT 24
Finished Jun 09 01:26:02 PM PDT 24
Peak memory 209788 kb
Host smart-205a125d-0ed1-4914-bd2a-eca15cf7974c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225900895 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2225900895
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.4062008118
Short name T924
Test name
Test status
Simulation time 1158755573 ps
CPU time 14.34 seconds
Started Jun 09 01:25:58 PM PDT 24
Finished Jun 09 01:26:13 PM PDT 24
Peak memory 209616 kb
Host smart-8039e051-8355-4fa2-b607-ac6410e6ac9b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062008118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.4062008118
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1880137767
Short name T953
Test name
Test status
Simulation time 2119611135 ps
CPU time 27.25 seconds
Started Jun 09 01:26:01 PM PDT 24
Finished Jun 09 01:26:29 PM PDT 24
Peak memory 217688 kb
Host smart-e6c5d42d-57c2-4585-b042-74c66270edfc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880137767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1880137767
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1304757522
Short name T884
Test name
Test status
Simulation time 662338156 ps
CPU time 1.87 seconds
Started Jun 09 01:25:58 PM PDT 24
Finished Jun 09 01:26:00 PM PDT 24
Peak memory 211396 kb
Host smart-8c6f944e-6285-4185-ad67-654a90f7177e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304757522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1304757522
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2873267897
Short name T917
Test name
Test status
Simulation time 302909550 ps
CPU time 6.49 seconds
Started Jun 09 01:26:01 PM PDT 24
Finished Jun 09 01:26:08 PM PDT 24
Peak memory 223376 kb
Host smart-df621184-a5c9-4b0b-a497-71ffcb8cce25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287326
7897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2873267897
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.937457241
Short name T878
Test name
Test status
Simulation time 55610707 ps
CPU time 1.35 seconds
Started Jun 09 01:25:58 PM PDT 24
Finished Jun 09 01:26:00 PM PDT 24
Peak memory 210104 kb
Host smart-07b86523-939c-4db8-a17e-0251fb1d188e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937457241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.937457241
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2085809510
Short name T936
Test name
Test status
Simulation time 83575862 ps
CPU time 1.81 seconds
Started Jun 09 01:25:58 PM PDT 24
Finished Jun 09 01:26:00 PM PDT 24
Peak memory 209944 kb
Host smart-0f2be4ae-a220-4718-b4a6-a4ce376d7fbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085809510 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.2085809510
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2611136599
Short name T986
Test name
Test status
Simulation time 31151060 ps
CPU time 1.5 seconds
Started Jun 09 01:26:04 PM PDT 24
Finished Jun 09 01:26:05 PM PDT 24
Peak memory 209944 kb
Host smart-943bb786-c758-4ef8-ae73-7d025efb65c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611136599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.2611136599
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1233281252
Short name T913
Test name
Test status
Simulation time 261175013 ps
CPU time 3.95 seconds
Started Jun 09 01:26:08 PM PDT 24
Finished Jun 09 01:26:12 PM PDT 24
Peak memory 218136 kb
Host smart-39408062-9588-4e6f-b5a2-902b84a9f382
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233281252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1233281252
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1916244023
Short name T124
Test name
Test status
Simulation time 57203745 ps
CPU time 1.87 seconds
Started Jun 09 01:26:17 PM PDT 24
Finished Jun 09 01:26:19 PM PDT 24
Peak memory 218264 kb
Host smart-83a2a6bc-c13c-4206-a480-8fbd817ce95b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916244023 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1916244023
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1548745421
Short name T987
Test name
Test status
Simulation time 12420039 ps
CPU time 0.92 seconds
Started Jun 09 01:26:16 PM PDT 24
Finished Jun 09 01:26:17 PM PDT 24
Peak memory 210024 kb
Host smart-e32a36e6-c85e-430a-bfe5-a681a565478a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548745421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1548745421
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2326903326
Short name T976
Test name
Test status
Simulation time 108092653 ps
CPU time 1.3 seconds
Started Jun 09 01:26:10 PM PDT 24
Finished Jun 09 01:26:11 PM PDT 24
Peak memory 209272 kb
Host smart-4e84ad08-96a2-417e-a827-58b4c13dc8e1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326903326 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2326903326
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1326761967
Short name T982
Test name
Test status
Simulation time 264029813 ps
CPU time 6.77 seconds
Started Jun 09 01:26:10 PM PDT 24
Finished Jun 09 01:26:17 PM PDT 24
Peak memory 209908 kb
Host smart-eff20132-328c-4c5e-94b9-1c610c4fb79d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326761967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1326761967
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1153527439
Short name T921
Test name
Test status
Simulation time 3067044863 ps
CPU time 23.37 seconds
Started Jun 09 01:26:11 PM PDT 24
Finished Jun 09 01:26:35 PM PDT 24
Peak memory 209864 kb
Host smart-4d090e46-c29e-4306-9462-29854b47f26a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153527439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1153527439
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3910734827
Short name T969
Test name
Test status
Simulation time 172999287 ps
CPU time 1.79 seconds
Started Jun 09 01:26:05 PM PDT 24
Finished Jun 09 01:26:07 PM PDT 24
Peak memory 211340 kb
Host smart-4bb92ad9-0dd8-4b04-ba29-82dd67dd6908
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910734827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3910734827
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3690586813
Short name T911
Test name
Test status
Simulation time 119468487 ps
CPU time 3.92 seconds
Started Jun 09 01:26:09 PM PDT 24
Finished Jun 09 01:26:13 PM PDT 24
Peak memory 218224 kb
Host smart-8a31f0a7-ca68-4f5e-98b3-d78870b1a5af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369058
6813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3690586813
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.191356636
Short name T918
Test name
Test status
Simulation time 164398694 ps
CPU time 1.09 seconds
Started Jun 09 01:26:06 PM PDT 24
Finished Jun 09 01:26:08 PM PDT 24
Peak memory 217832 kb
Host smart-9e89b950-88d4-4c41-ada5-a4f973d51283
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191356636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.191356636
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.66020723
Short name T943
Test name
Test status
Simulation time 22131237 ps
CPU time 1.21 seconds
Started Jun 09 01:26:10 PM PDT 24
Finished Jun 09 01:26:12 PM PDT 24
Peak memory 212128 kb
Host smart-6a0fe013-2ff1-4810-8824-7f98580fc5c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66020723 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.66020723
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1294023731
Short name T206
Test name
Test status
Simulation time 66627049 ps
CPU time 1.1 seconds
Started Jun 09 01:26:16 PM PDT 24
Finished Jun 09 01:26:18 PM PDT 24
Peak memory 210164 kb
Host smart-579b60f5-049b-4ba8-810c-e35407dababe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294023731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.1294023731
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.417681124
Short name T947
Test name
Test status
Simulation time 168679518 ps
CPU time 2.88 seconds
Started Jun 09 01:26:10 PM PDT 24
Finished Jun 09 01:26:13 PM PDT 24
Peak memory 218396 kb
Host smart-67735ad1-0113-472c-ad5f-b4fd85286e0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417681124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.417681124
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.311299350
Short name T133
Test name
Test status
Simulation time 251582700 ps
CPU time 2.7 seconds
Started Jun 09 01:26:10 PM PDT 24
Finished Jun 09 01:26:13 PM PDT 24
Peak memory 218152 kb
Host smart-0a5c848e-fab8-4024-ab3c-c3e3d61d9c82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311299350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.311299350
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.129365519
Short name T926
Test name
Test status
Simulation time 19605464 ps
CPU time 1.33 seconds
Started Jun 09 01:26:21 PM PDT 24
Finished Jun 09 01:26:23 PM PDT 24
Peak memory 219316 kb
Host smart-b62bfc0f-2c58-4a0c-95d6-ed401573f0d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129365519 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.129365519
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3707312072
Short name T915
Test name
Test status
Simulation time 28077355 ps
CPU time 1.04 seconds
Started Jun 09 01:26:22 PM PDT 24
Finished Jun 09 01:26:24 PM PDT 24
Peak memory 209604 kb
Host smart-43de5e0d-584a-4f79-8369-43ef1a639d60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707312072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3707312072
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.788201942
Short name T896
Test name
Test status
Simulation time 217604287 ps
CPU time 1.15 seconds
Started Jun 09 01:26:14 PM PDT 24
Finished Jun 09 01:26:16 PM PDT 24
Peak memory 209820 kb
Host smart-88f5a133-e283-4c32-b8a2-a0d8335bd2ca
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788201942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.lc_ctrl_jtag_alert_test.788201942
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.600307837
Short name T954
Test name
Test status
Simulation time 2076948953 ps
CPU time 5.78 seconds
Started Jun 09 01:26:16 PM PDT 24
Finished Jun 09 01:26:22 PM PDT 24
Peak memory 217628 kb
Host smart-45f23ae8-7fbb-457b-84f4-1d71aec9b4b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600307837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.600307837
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3575842447
Short name T930
Test name
Test status
Simulation time 1116958354 ps
CPU time 16.17 seconds
Started Jun 09 01:26:17 PM PDT 24
Finished Jun 09 01:26:34 PM PDT 24
Peak memory 209704 kb
Host smart-45f72ad1-50df-4684-9437-e64795322459
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575842447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3575842447
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1110803105
Short name T142
Test name
Test status
Simulation time 93266824 ps
CPU time 1.61 seconds
Started Jun 09 01:26:17 PM PDT 24
Finished Jun 09 01:26:18 PM PDT 24
Peak memory 211524 kb
Host smart-146341b0-5758-4c83-bcf3-9ab51669ae4a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110803105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.1110803105
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2459939228
Short name T994
Test name
Test status
Simulation time 102052736 ps
CPU time 1.41 seconds
Started Jun 09 01:26:17 PM PDT 24
Finished Jun 09 01:26:19 PM PDT 24
Peak memory 218776 kb
Host smart-09311b7d-aebc-47fe-9107-231286ea6a12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245993
9228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2459939228
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.884515104
Short name T957
Test name
Test status
Simulation time 47433503 ps
CPU time 1.79 seconds
Started Jun 09 01:26:16 PM PDT 24
Finished Jun 09 01:26:18 PM PDT 24
Peak memory 217748 kb
Host smart-eb06fdd2-1620-4cb5-b223-c4d9d1202739
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884515104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.884515104
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3605148571
Short name T951
Test name
Test status
Simulation time 71655627 ps
CPU time 1.43 seconds
Started Jun 09 01:26:15 PM PDT 24
Finished Jun 09 01:26:17 PM PDT 24
Peak memory 218180 kb
Host smart-1bc63369-1642-4869-accf-3c3ff5925437
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605148571 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3605148571
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1730082204
Short name T974
Test name
Test status
Simulation time 37082192 ps
CPU time 1.04 seconds
Started Jun 09 01:26:20 PM PDT 24
Finished Jun 09 01:26:22 PM PDT 24
Peak memory 209944 kb
Host smart-8819702a-89a1-494c-8791-8db424bb6623
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730082204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.1730082204
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3384185329
Short name T985
Test name
Test status
Simulation time 34991215 ps
CPU time 2.46 seconds
Started Jun 09 01:26:21 PM PDT 24
Finished Jun 09 01:26:24 PM PDT 24
Peak memory 218340 kb
Host smart-68f8a46f-a65e-4418-ab3c-2f50812da7ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384185329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3384185329
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2104770834
Short name T980
Test name
Test status
Simulation time 127078230 ps
CPU time 2.09 seconds
Started Jun 09 01:26:22 PM PDT 24
Finished Jun 09 01:26:24 PM PDT 24
Peak memory 222568 kb
Host smart-58c7626c-4e1d-4412-9fdf-042434cc83a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104770834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2104770834
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1302442419
Short name T998
Test name
Test status
Simulation time 24994180 ps
CPU time 1.49 seconds
Started Jun 09 01:26:30 PM PDT 24
Finished Jun 09 01:26:31 PM PDT 24
Peak memory 218840 kb
Host smart-d6b60e47-13a1-40fa-b7e0-49b42d676d93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302442419 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1302442419
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3809842174
Short name T198
Test name
Test status
Simulation time 45300742 ps
CPU time 0.89 seconds
Started Jun 09 01:26:26 PM PDT 24
Finished Jun 09 01:26:27 PM PDT 24
Peak memory 209972 kb
Host smart-0225d304-a88a-459d-a8e3-0ad321ff201f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809842174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3809842174
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1499911699
Short name T952
Test name
Test status
Simulation time 433700125 ps
CPU time 1.92 seconds
Started Jun 09 01:26:28 PM PDT 24
Finished Jun 09 01:26:30 PM PDT 24
Peak memory 209956 kb
Host smart-d03706c5-d4cc-4953-aa95-1a5d605b98f7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499911699 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1499911699
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2653461072
Short name T894
Test name
Test status
Simulation time 1049711575 ps
CPU time 2.63 seconds
Started Jun 09 01:26:20 PM PDT 24
Finished Jun 09 01:26:23 PM PDT 24
Peak memory 210012 kb
Host smart-d876d334-c55f-414c-a047-1c90d90a5567
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653461072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2653461072
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2130760555
Short name T919
Test name
Test status
Simulation time 696240789 ps
CPU time 17.63 seconds
Started Jun 09 01:26:21 PM PDT 24
Finished Jun 09 01:26:39 PM PDT 24
Peak memory 217704 kb
Host smart-3a305439-d87f-4596-aca1-eb5e85d4f79c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130760555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2130760555
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.933346300
Short name T892
Test name
Test status
Simulation time 148268093 ps
CPU time 3.88 seconds
Started Jun 09 01:26:21 PM PDT 24
Finished Jun 09 01:26:25 PM PDT 24
Peak memory 218088 kb
Host smart-63292284-78af-4b25-b0d1-866992a976aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933346300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.933346300
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2224823998
Short name T904
Test name
Test status
Simulation time 135933352 ps
CPU time 2.16 seconds
Started Jun 09 01:26:21 PM PDT 24
Finished Jun 09 01:26:24 PM PDT 24
Peak memory 219320 kb
Host smart-4f41e140-ec56-4157-a349-82a84b6e92cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222482
3998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2224823998
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2742601796
Short name T989
Test name
Test status
Simulation time 85427936 ps
CPU time 1.83 seconds
Started Jun 09 01:26:21 PM PDT 24
Finished Jun 09 01:26:23 PM PDT 24
Peak memory 209920 kb
Host smart-65c55a7b-b847-44f3-bfb7-9fd4f0d9ae55
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742601796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.2742601796
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2549676822
Short name T925
Test name
Test status
Simulation time 17545688 ps
CPU time 1.12 seconds
Started Jun 09 01:26:21 PM PDT 24
Finished Jun 09 01:26:22 PM PDT 24
Peak memory 209948 kb
Host smart-16b7a972-7b9b-4f20-b67d-17ed645f7ebe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549676822 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2549676822
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2956310871
Short name T942
Test name
Test status
Simulation time 59113690 ps
CPU time 1.13 seconds
Started Jun 09 01:26:26 PM PDT 24
Finished Jun 09 01:26:27 PM PDT 24
Peak memory 209936 kb
Host smart-8f99fbce-57df-4c47-a15a-78e8f508a0c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956310871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2956310871
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.453566353
Short name T928
Test name
Test status
Simulation time 181546888 ps
CPU time 2.81 seconds
Started Jun 09 01:26:28 PM PDT 24
Finished Jun 09 01:26:31 PM PDT 24
Peak memory 218340 kb
Host smart-f6c3d3a9-61df-499c-a4a9-7c3f90ca5211
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453566353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.453566353
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.1534633118
Short name T513
Test name
Test status
Simulation time 73822423 ps
CPU time 1.15 seconds
Started Jun 09 01:29:05 PM PDT 24
Finished Jun 09 01:29:07 PM PDT 24
Peak memory 209044 kb
Host smart-59bfee9e-b631-4bbb-bdca-af0312174bfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534633118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1534633118
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1328599569
Short name T727
Test name
Test status
Simulation time 381146343 ps
CPU time 12.98 seconds
Started Jun 09 01:28:58 PM PDT 24
Finished Jun 09 01:29:11 PM PDT 24
Peak memory 218300 kb
Host smart-6c66e90b-7ff5-48be-8c2b-1d3d77ea20e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328599569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1328599569
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2464237100
Short name T31
Test name
Test status
Simulation time 1215000004 ps
CPU time 20.08 seconds
Started Jun 09 01:29:00 PM PDT 24
Finished Jun 09 01:29:20 PM PDT 24
Peak memory 217448 kb
Host smart-9fa28b1a-e484-4ac3-a8c0-00466be86e17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464237100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2464237100
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.388596879
Short name T739
Test name
Test status
Simulation time 1409808522 ps
CPU time 40.34 seconds
Started Jun 09 01:28:59 PM PDT 24
Finished Jun 09 01:29:40 PM PDT 24
Peak memory 218204 kb
Host smart-088dc586-4540-4300-93ad-c0ea8a3bc7f6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388596879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_err
ors.388596879
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.3667863883
Short name T183
Test name
Test status
Simulation time 420418163 ps
CPU time 5.74 seconds
Started Jun 09 01:28:59 PM PDT 24
Finished Jun 09 01:29:05 PM PDT 24
Peak memory 217640 kb
Host smart-f5929243-0abc-4c5a-82b7-3d9429df1d49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667863883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.3
667863883
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.1032498710
Short name T620
Test name
Test status
Simulation time 2158851609 ps
CPU time 7.07 seconds
Started Jun 09 01:29:01 PM PDT 24
Finished Jun 09 01:29:09 PM PDT 24
Peak memory 224328 kb
Host smart-1e53015d-a8b3-41ed-aa41-d4989aa9b339
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032498710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.1032498710
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2389431814
Short name T474
Test name
Test status
Simulation time 3281688029 ps
CPU time 10.33 seconds
Started Jun 09 01:29:06 PM PDT 24
Finished Jun 09 01:29:16 PM PDT 24
Peak memory 217744 kb
Host smart-7046a79e-66a6-4790-865a-a23aa8bf88b7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389431814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.2389431814
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1789607578
Short name T100
Test name
Test status
Simulation time 2527743494 ps
CPU time 8.41 seconds
Started Jun 09 01:29:02 PM PDT 24
Finished Jun 09 01:29:10 PM PDT 24
Peak memory 217748 kb
Host smart-793da7e5-2a51-4cd5-a9ed-a84bda3602c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789607578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
1789607578
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1200994938
Short name T294
Test name
Test status
Simulation time 4450764965 ps
CPU time 134.38 seconds
Started Jun 09 01:29:01 PM PDT 24
Finished Jun 09 01:31:16 PM PDT 24
Peak memory 283668 kb
Host smart-e714bffc-c90d-4e5f-84b0-e134c10f3fb9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200994938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1200994938
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.3331775015
Short name T562
Test name
Test status
Simulation time 355204715 ps
CPU time 12.21 seconds
Started Jun 09 01:29:00 PM PDT 24
Finished Jun 09 01:29:13 PM PDT 24
Peak memory 250804 kb
Host smart-8fcd6653-9e70-4686-96d9-498ccdf79041
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331775015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.3331775015
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.3024914181
Short name T56
Test name
Test status
Simulation time 383700917 ps
CPU time 5.02 seconds
Started Jun 09 01:28:59 PM PDT 24
Finished Jun 09 01:29:04 PM PDT 24
Peak memory 218228 kb
Host smart-4edd77ce-a4c4-40fa-a7c3-c5d3aeac5d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024914181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3024914181
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.2851777346
Short name T674
Test name
Test status
Simulation time 561205550 ps
CPU time 17.82 seconds
Started Jun 09 01:29:02 PM PDT 24
Finished Jun 09 01:29:20 PM PDT 24
Peak memory 214192 kb
Host smart-d2c64d84-039b-49e5-b19c-d6e51bc27e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851777346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2851777346
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2186226366
Short name T86
Test name
Test status
Simulation time 837661572 ps
CPU time 34.78 seconds
Started Jun 09 01:29:06 PM PDT 24
Finished Jun 09 01:29:41 PM PDT 24
Peak memory 284304 kb
Host smart-37be5114-2319-4a19-a91d-8f60ab342652
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186226366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2186226366
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.3773752127
Short name T542
Test name
Test status
Simulation time 201578047 ps
CPU time 11.63 seconds
Started Jun 09 01:29:06 PM PDT 24
Finished Jun 09 01:29:18 PM PDT 24
Peak memory 226072 kb
Host smart-34483551-a3c8-46fa-b084-7511bce7ee3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773752127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.3773752127
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.729044201
Short name T804
Test name
Test status
Simulation time 423417502 ps
CPU time 12.57 seconds
Started Jun 09 01:29:07 PM PDT 24
Finished Jun 09 01:29:20 PM PDT 24
Peak memory 226108 kb
Host smart-587d85bb-4195-4c0a-87f3-d7811a6c3ef7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729044201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_dig
est.729044201
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1816153009
Short name T415
Test name
Test status
Simulation time 651867271 ps
CPU time 8.47 seconds
Started Jun 09 01:29:07 PM PDT 24
Finished Jun 09 01:29:16 PM PDT 24
Peak memory 218292 kb
Host smart-67719eb9-6941-40ae-a8a9-154f8f018dab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816153009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1
816153009
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.3193817705
Short name T664
Test name
Test status
Simulation time 591204299 ps
CPU time 7.16 seconds
Started Jun 09 01:29:01 PM PDT 24
Finished Jun 09 01:29:08 PM PDT 24
Peak memory 225136 kb
Host smart-d3de0ad6-018f-47f9-8051-b0cc8bd1b558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193817705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3193817705
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.405411652
Short name T847
Test name
Test status
Simulation time 56902368 ps
CPU time 2.62 seconds
Started Jun 09 01:28:55 PM PDT 24
Finished Jun 09 01:28:58 PM PDT 24
Peak memory 214684 kb
Host smart-b5ab8c01-820d-495f-949c-0be6c54bf499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405411652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.405411652
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.141168307
Short name T311
Test name
Test status
Simulation time 354461830 ps
CPU time 29.13 seconds
Started Jun 09 01:28:51 PM PDT 24
Finished Jun 09 01:29:20 PM PDT 24
Peak memory 250920 kb
Host smart-8af6b322-0c42-4d03-aaa1-b6010b49cb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141168307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.141168307
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.558037829
Short name T254
Test name
Test status
Simulation time 103778391 ps
CPU time 8.82 seconds
Started Jun 09 01:28:56 PM PDT 24
Finished Jun 09 01:29:05 PM PDT 24
Peak memory 250924 kb
Host smart-5560628a-26c0-4127-ab0b-ea6e9a44b67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558037829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.558037829
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.4229514186
Short name T149
Test name
Test status
Simulation time 64858319561 ps
CPU time 962.18 seconds
Started Jun 09 01:29:06 PM PDT 24
Finished Jun 09 01:45:09 PM PDT 24
Peak memory 300364 kb
Host smart-a58ccb0d-c8aa-499b-b6ad-ebdf023d2b54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4229514186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.4229514186
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3113655806
Short name T860
Test name
Test status
Simulation time 46770846 ps
CPU time 0.89 seconds
Started Jun 09 01:28:54 PM PDT 24
Finished Jun 09 01:28:55 PM PDT 24
Peak memory 211960 kb
Host smart-07bded3f-31b0-4b49-bac3-cd3811c18692
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113655806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.3113655806
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3166186
Short name T856
Test name
Test status
Simulation time 52516808 ps
CPU time 1.02 seconds
Started Jun 09 01:29:18 PM PDT 24
Finished Jun 09 01:29:19 PM PDT 24
Peak memory 208964 kb
Host smart-bf8e026d-73bc-490d-9e1c-20314e32d858
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3166186
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2664230419
Short name T220
Test name
Test status
Simulation time 31785707 ps
CPU time 0.85 seconds
Started Jun 09 01:29:12 PM PDT 24
Finished Jun 09 01:29:13 PM PDT 24
Peak memory 209008 kb
Host smart-2b11f11e-5cc0-43b4-b03c-8d8683d1ce96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664230419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2664230419
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.2562368848
Short name T491
Test name
Test status
Simulation time 740302635 ps
CPU time 17.59 seconds
Started Jun 09 01:29:10 PM PDT 24
Finished Jun 09 01:29:27 PM PDT 24
Peak memory 218232 kb
Host smart-51f05035-bd1b-4652-8dd7-5337dee78b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562368848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2562368848
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1438800610
Short name T27
Test name
Test status
Simulation time 3145325035 ps
CPU time 16.31 seconds
Started Jun 09 01:29:10 PM PDT 24
Finished Jun 09 01:29:26 PM PDT 24
Peak memory 217788 kb
Host smart-5898da8f-c98b-499d-86ff-b2afa1c11a9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438800610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1438800610
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2173133117
Short name T302
Test name
Test status
Simulation time 1625195065 ps
CPU time 38.79 seconds
Started Jun 09 01:29:11 PM PDT 24
Finished Jun 09 01:29:50 PM PDT 24
Peak memory 218200 kb
Host smart-3fc34f06-5dd8-4314-aa9a-0cb43ccd4e09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173133117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2173133117
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2731479526
Short name T500
Test name
Test status
Simulation time 489396347 ps
CPU time 6.35 seconds
Started Jun 09 01:29:12 PM PDT 24
Finished Jun 09 01:29:18 PM PDT 24
Peak memory 217340 kb
Host smart-39f5c9e1-f8dc-47c4-977e-4bd5931bdda5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731479526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
731479526
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2140556302
Short name T774
Test name
Test status
Simulation time 2534678652 ps
CPU time 17.38 seconds
Started Jun 09 01:29:09 PM PDT 24
Finished Jun 09 01:29:26 PM PDT 24
Peak memory 224928 kb
Host smart-439c70df-9ede-476f-bb8f-af251787a8b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140556302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2140556302
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1950594054
Short name T450
Test name
Test status
Simulation time 9953708046 ps
CPU time 31.15 seconds
Started Jun 09 01:29:11 PM PDT 24
Finished Jun 09 01:29:42 PM PDT 24
Peak memory 217748 kb
Host smart-22461535-3e04-4abc-8da2-896bc007f964
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950594054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.1950594054
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.1079384508
Short name T841
Test name
Test status
Simulation time 452371835 ps
CPU time 7.31 seconds
Started Jun 09 01:29:13 PM PDT 24
Finished Jun 09 01:29:20 PM PDT 24
Peak memory 217704 kb
Host smart-aebd6fa6-094a-4a9c-93b3-df2522d1acce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079384508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
1079384508
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.1424971590
Short name T456
Test name
Test status
Simulation time 4998601583 ps
CPU time 54.02 seconds
Started Jun 09 01:29:11 PM PDT 24
Finished Jun 09 01:30:05 PM PDT 24
Peak memory 267252 kb
Host smart-722304c6-5b59-4a45-86ad-b1681526ab8e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424971590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.1424971590
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3442320837
Short name T237
Test name
Test status
Simulation time 9534138151 ps
CPU time 14.31 seconds
Started Jun 09 01:29:12 PM PDT 24
Finished Jun 09 01:29:26 PM PDT 24
Peak memory 222548 kb
Host smart-8e32fb26-64e1-4786-a8a7-9f870ce5c6b2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442320837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.3442320837
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.3552739564
Short name T548
Test name
Test status
Simulation time 26711514 ps
CPU time 1.7 seconds
Started Jun 09 01:29:12 PM PDT 24
Finished Jun 09 01:29:14 PM PDT 24
Peak memory 221844 kb
Host smart-f8468c54-a0e6-4d9a-bd49-13a000a0aea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552739564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.3552739564
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2855307257
Short name T366
Test name
Test status
Simulation time 3807471868 ps
CPU time 14 seconds
Started Jun 09 01:29:11 PM PDT 24
Finished Jun 09 01:29:25 PM PDT 24
Peak memory 217820 kb
Host smart-40d0f5d2-d89e-4c77-a7b9-bd0477a0211e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855307257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2855307257
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.2730923825
Short name T87
Test name
Test status
Simulation time 275599462 ps
CPU time 35.03 seconds
Started Jun 09 01:29:16 PM PDT 24
Finished Jun 09 01:29:51 PM PDT 24
Peak memory 269796 kb
Host smart-f69febac-d788-4b25-89bb-5007628f2be9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730923825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2730923825
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1471238740
Short name T743
Test name
Test status
Simulation time 1043224151 ps
CPU time 12.95 seconds
Started Jun 09 01:29:11 PM PDT 24
Finished Jun 09 01:29:24 PM PDT 24
Peak memory 226184 kb
Host smart-692d4325-e587-48aa-9bbc-189df4ccc77b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471238740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1471238740
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.219303060
Short name T362
Test name
Test status
Simulation time 1619563287 ps
CPU time 12.42 seconds
Started Jun 09 01:29:15 PM PDT 24
Finished Jun 09 01:29:28 PM PDT 24
Peak memory 226076 kb
Host smart-3faef484-cc2c-47f6-aafc-fb9b53f31ad0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219303060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dig
est.219303060
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.922349960
Short name T221
Test name
Test status
Simulation time 261956225 ps
CPU time 10.04 seconds
Started Jun 09 01:29:15 PM PDT 24
Finished Jun 09 01:29:25 PM PDT 24
Peak memory 226084 kb
Host smart-ce80bdfc-95d9-4d91-9e00-eeec3fc467ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922349960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.922349960
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.2016633510
Short name T45
Test name
Test status
Simulation time 344538404 ps
CPU time 7.29 seconds
Started Jun 09 01:29:10 PM PDT 24
Finished Jun 09 01:29:18 PM PDT 24
Peak memory 224680 kb
Host smart-4aeb5342-1aab-48c9-8699-72685156c175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016633510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2016633510
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.292828937
Short name T33
Test name
Test status
Simulation time 71377921 ps
CPU time 2.64 seconds
Started Jun 09 01:29:04 PM PDT 24
Finished Jun 09 01:29:07 PM PDT 24
Peak memory 214876 kb
Host smart-b92b44e0-ef3c-4d39-bd85-e2d0681c232c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292828937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.292828937
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.1417753715
Short name T754
Test name
Test status
Simulation time 675168159 ps
CPU time 25.87 seconds
Started Jun 09 01:29:06 PM PDT 24
Finished Jun 09 01:29:32 PM PDT 24
Peak memory 250900 kb
Host smart-3441d082-84b4-49bd-b1f4-f20dad8226e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417753715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1417753715
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1263853796
Short name T63
Test name
Test status
Simulation time 184701455 ps
CPU time 3.23 seconds
Started Jun 09 01:29:13 PM PDT 24
Finished Jun 09 01:29:16 PM PDT 24
Peak memory 220888 kb
Host smart-c36bff34-1c20-4ff7-93b5-400cc016f6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263853796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1263853796
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.1513832226
Short name T527
Test name
Test status
Simulation time 40444106020 ps
CPU time 311.68 seconds
Started Jun 09 01:29:16 PM PDT 24
Finished Jun 09 01:34:28 PM PDT 24
Peak memory 268664 kb
Host smart-24172992-d42e-4fa9-882f-71b6aa89941a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513832226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.1513832226
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.740957999
Short name T176
Test name
Test status
Simulation time 17456790 ps
CPU time 0.86 seconds
Started Jun 09 01:29:08 PM PDT 24
Finished Jun 09 01:29:09 PM PDT 24
Peak memory 211904 kb
Host smart-424f48bd-5225-491a-a15f-a156f35a000c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740957999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctr
l_volatile_unlock_smoke.740957999
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.1141454777
Short name T70
Test name
Test status
Simulation time 16232762 ps
CPU time 0.91 seconds
Started Jun 09 01:30:42 PM PDT 24
Finished Jun 09 01:30:43 PM PDT 24
Peak memory 208968 kb
Host smart-4c14d61b-72cf-4b3a-a8ed-73a725b58adb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141454777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.1141454777
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.1820729047
Short name T756
Test name
Test status
Simulation time 1001697119 ps
CPU time 16.43 seconds
Started Jun 09 01:30:37 PM PDT 24
Finished Jun 09 01:30:54 PM PDT 24
Peak memory 218304 kb
Host smart-2e1d228d-6e34-4c3b-94c4-3b1882a501fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820729047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1820729047
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.2119821352
Short name T515
Test name
Test status
Simulation time 131835058 ps
CPU time 2.12 seconds
Started Jun 09 01:30:37 PM PDT 24
Finished Jun 09 01:30:39 PM PDT 24
Peak memory 217092 kb
Host smart-258b1b4e-9a91-40eb-b8b0-f7f1c1652e67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119821352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.2119821352
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2402520200
Short name T341
Test name
Test status
Simulation time 14200321406 ps
CPU time 51.62 seconds
Started Jun 09 01:30:37 PM PDT 24
Finished Jun 09 01:31:29 PM PDT 24
Peak memory 219720 kb
Host smart-973e4395-ed84-492a-8f68-fae03bd2e5aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402520200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2402520200
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1152870563
Short name T560
Test name
Test status
Simulation time 581837178 ps
CPU time 4.62 seconds
Started Jun 09 01:30:36 PM PDT 24
Finished Jun 09 01:30:41 PM PDT 24
Peak memory 223036 kb
Host smart-d1c6985c-6dbb-4417-9ef5-a15002961b76
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152870563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1152870563
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3803574353
Short name T365
Test name
Test status
Simulation time 369471502 ps
CPU time 6.66 seconds
Started Jun 09 01:30:37 PM PDT 24
Finished Jun 09 01:30:44 PM PDT 24
Peak memory 217716 kb
Host smart-d83691e9-9575-4468-9d93-25a6d90c3e58
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803574353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.3803574353
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.655169610
Short name T279
Test name
Test status
Simulation time 4513626670 ps
CPU time 98.7 seconds
Started Jun 09 01:30:37 PM PDT 24
Finished Jun 09 01:32:16 PM PDT 24
Peak memory 283664 kb
Host smart-f6e1728e-7f6c-4f18-91c8-485c6ade78cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655169610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_state_failure.655169610
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.1020486807
Short name T105
Test name
Test status
Simulation time 939372240 ps
CPU time 14.89 seconds
Started Jun 09 01:30:37 PM PDT 24
Finished Jun 09 01:30:52 PM PDT 24
Peak memory 227228 kb
Host smart-ffa5ae14-9dbd-4bd4-abf6-b887b7525300
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020486807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.1020486807
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.3932075623
Short name T273
Test name
Test status
Simulation time 221758275 ps
CPU time 3.37 seconds
Started Jun 09 01:30:35 PM PDT 24
Finished Jun 09 01:30:39 PM PDT 24
Peak memory 218224 kb
Host smart-6efdc709-c4b6-4b95-9f43-0bb9abc7f99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932075623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.3932075623
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.520234576
Short name T435
Test name
Test status
Simulation time 292876278 ps
CPU time 12.41 seconds
Started Jun 09 01:30:37 PM PDT 24
Finished Jun 09 01:30:50 PM PDT 24
Peak memory 218940 kb
Host smart-98233e85-0786-4ef6-ae50-f349db77bb37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520234576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.520234576
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.2243267332
Short name T428
Test name
Test status
Simulation time 257543570 ps
CPU time 10.13 seconds
Started Jun 09 01:30:41 PM PDT 24
Finished Jun 09 01:30:52 PM PDT 24
Peak memory 218276 kb
Host smart-988199c0-59cd-4faa-8986-40a04baf4cc7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243267332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.2243267332
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.913001281
Short name T57
Test name
Test status
Simulation time 290657936 ps
CPU time 11.24 seconds
Started Jun 09 01:30:40 PM PDT 24
Finished Jun 09 01:30:51 PM PDT 24
Peak memory 218264 kb
Host smart-4242142a-b041-4392-bd97-ad15941e6776
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913001281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.913001281
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1990801739
Short name T22
Test name
Test status
Simulation time 231711474 ps
CPU time 9.26 seconds
Started Jun 09 01:30:38 PM PDT 24
Finished Jun 09 01:30:48 PM PDT 24
Peak memory 226080 kb
Host smart-5aae095f-ffed-4375-95d1-a61636f0411f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990801739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1990801739
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.1018556538
Short name T786
Test name
Test status
Simulation time 253154942 ps
CPU time 3.54 seconds
Started Jun 09 01:30:30 PM PDT 24
Finished Jun 09 01:30:34 PM PDT 24
Peak memory 214720 kb
Host smart-6874637f-f2d2-4ca5-a101-4660f3dae189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018556538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1018556538
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.2620119575
Short name T803
Test name
Test status
Simulation time 392925252 ps
CPU time 18.86 seconds
Started Jun 09 01:30:33 PM PDT 24
Finished Jun 09 01:30:53 PM PDT 24
Peak memory 250912 kb
Host smart-97e38861-5b9e-495f-8c12-e5da1e676677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620119575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.2620119575
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2197919722
Short name T229
Test name
Test status
Simulation time 145443008 ps
CPU time 6.31 seconds
Started Jun 09 01:30:38 PM PDT 24
Finished Jun 09 01:30:45 PM PDT 24
Peak memory 250404 kb
Host smart-354e5c85-f6e0-496f-8d63-178f8db1ff67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197919722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2197919722
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.3887677185
Short name T714
Test name
Test status
Simulation time 40737622442 ps
CPU time 301.86 seconds
Started Jun 09 01:30:43 PM PDT 24
Finished Jun 09 01:35:45 PM PDT 24
Peak memory 221156 kb
Host smart-ba6646f6-45ce-4943-bc78-d6fe9ba782f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887677185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.3887677185
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.33648527
Short name T609
Test name
Test status
Simulation time 134950090 ps
CPU time 0.85 seconds
Started Jun 09 01:30:31 PM PDT 24
Finished Jun 09 01:30:32 PM PDT 24
Peak memory 217828 kb
Host smart-910ec734-e88f-420c-9af6-41bb242c8cf2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33648527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_volatile_unlock_smoke.33648527
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.2418415866
Short name T844
Test name
Test status
Simulation time 26790340 ps
CPU time 1.37 seconds
Started Jun 09 01:30:47 PM PDT 24
Finished Jun 09 01:30:49 PM PDT 24
Peak memory 208984 kb
Host smart-040d5f41-4fcf-4f57-a541-db32fb0dc781
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418415866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2418415866
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.1768412715
Short name T764
Test name
Test status
Simulation time 1136594865 ps
CPU time 13.82 seconds
Started Jun 09 01:30:43 PM PDT 24
Finished Jun 09 01:30:57 PM PDT 24
Peak memory 218388 kb
Host smart-32d2c2ef-4d59-4dcb-9b5f-7167c536d4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768412715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.1768412715
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1505228183
Short name T309
Test name
Test status
Simulation time 998598846 ps
CPU time 3.42 seconds
Started Jun 09 01:30:41 PM PDT 24
Finished Jun 09 01:30:45 PM PDT 24
Peak memory 217084 kb
Host smart-f97e0b56-1eb1-41a3-bea6-50ace9d1af7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505228183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1505228183
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2993391154
Short name T421
Test name
Test status
Simulation time 22127297891 ps
CPU time 72.17 seconds
Started Jun 09 01:30:45 PM PDT 24
Finished Jun 09 01:31:57 PM PDT 24
Peak memory 220896 kb
Host smart-b5c74938-ddb5-45b1-b11c-170c99d439f7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993391154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2993391154
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1480579684
Short name T344
Test name
Test status
Simulation time 278218309 ps
CPU time 5.03 seconds
Started Jun 09 01:30:44 PM PDT 24
Finished Jun 09 01:30:49 PM PDT 24
Peak memory 222832 kb
Host smart-3de4734c-b13e-4eb3-9147-ddfc7ce63fdc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480579684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.1480579684
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.4035325022
Short name T422
Test name
Test status
Simulation time 760239990 ps
CPU time 5.89 seconds
Started Jun 09 01:30:44 PM PDT 24
Finished Jun 09 01:30:50 PM PDT 24
Peak memory 217656 kb
Host smart-e0a773c7-c873-4142-8484-931f0d5db638
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035325022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.4035325022
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2597513179
Short name T825
Test name
Test status
Simulation time 876705471 ps
CPU time 26.5 seconds
Started Jun 09 01:30:41 PM PDT 24
Finished Jun 09 01:31:07 PM PDT 24
Peak memory 250836 kb
Host smart-faccfee3-7fbe-4190-bc8c-55f8cdf11dba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597513179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.2597513179
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3264731253
Short name T384
Test name
Test status
Simulation time 441051290 ps
CPU time 14.13 seconds
Started Jun 09 01:30:43 PM PDT 24
Finished Jun 09 01:30:57 PM PDT 24
Peak memory 218184 kb
Host smart-7f683178-c52f-40b3-ae9b-c274c792d505
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264731253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3264731253
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.3041454578
Short name T323
Test name
Test status
Simulation time 282903612 ps
CPU time 3.04 seconds
Started Jun 09 01:30:43 PM PDT 24
Finished Jun 09 01:30:46 PM PDT 24
Peak memory 218216 kb
Host smart-50a87b27-ab7e-4f0f-97e3-d58364239a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041454578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3041454578
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.1111361018
Short name T361
Test name
Test status
Simulation time 700205258 ps
CPU time 9.49 seconds
Started Jun 09 01:30:44 PM PDT 24
Finished Jun 09 01:30:54 PM PDT 24
Peak memory 218288 kb
Host smart-b093930a-f2e9-4de0-8d71-ae329c736ee6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111361018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.1111361018
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1264791661
Short name T608
Test name
Test status
Simulation time 619025928 ps
CPU time 8.38 seconds
Started Jun 09 01:30:45 PM PDT 24
Finished Jun 09 01:30:54 PM PDT 24
Peak memory 218276 kb
Host smart-fe692f57-79c4-4d82-88e8-fce34e4f3489
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264791661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1264791661
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1467867441
Short name T576
Test name
Test status
Simulation time 672420177 ps
CPU time 12.48 seconds
Started Jun 09 01:30:41 PM PDT 24
Finished Jun 09 01:30:54 PM PDT 24
Peak memory 218268 kb
Host smart-5b019664-b493-4dc7-833d-8669e79b461a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467867441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
1467867441
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1861286132
Short name T679
Test name
Test status
Simulation time 941250779 ps
CPU time 12.51 seconds
Started Jun 09 01:30:42 PM PDT 24
Finished Jun 09 01:30:54 PM PDT 24
Peak memory 218372 kb
Host smart-25d19e3d-4247-40b8-b5f2-ae8d34f1b418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861286132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1861286132
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.566154993
Short name T404
Test name
Test status
Simulation time 114765613 ps
CPU time 1.6 seconds
Started Jun 09 01:30:44 PM PDT 24
Finished Jun 09 01:30:46 PM PDT 24
Peak memory 213928 kb
Host smart-66c2c608-a9d1-4dc8-9131-01e588b8543b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566154993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.566154993
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.78256083
Short name T460
Test name
Test status
Simulation time 550723947 ps
CPU time 30.69 seconds
Started Jun 09 01:30:43 PM PDT 24
Finished Jun 09 01:31:14 PM PDT 24
Peak memory 250904 kb
Host smart-bc6b13be-a8d6-4a9c-b472-9ebdb1ebc0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78256083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.78256083
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.1581770581
Short name T869
Test name
Test status
Simulation time 285443162 ps
CPU time 9.19 seconds
Started Jun 09 01:30:42 PM PDT 24
Finished Jun 09 01:30:52 PM PDT 24
Peak memory 250884 kb
Host smart-93c63619-adf5-4e97-90b8-0674aa780c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581770581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1581770581
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.3301997111
Short name T530
Test name
Test status
Simulation time 52430816736 ps
CPU time 181.93 seconds
Started Jun 09 01:30:47 PM PDT 24
Finished Jun 09 01:33:49 PM PDT 24
Peak memory 275708 kb
Host smart-debb6891-01fc-444f-8f4d-5acfee254dbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301997111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.3301997111
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.762189362
Short name T150
Test name
Test status
Simulation time 12598924849 ps
CPU time 374.47 seconds
Started Jun 09 01:30:47 PM PDT 24
Finished Jun 09 01:37:02 PM PDT 24
Peak memory 272708 kb
Host smart-8aa0eb4f-14cb-4b6f-a7d6-79e9e38c3323
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=762189362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.762189362
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1479142948
Short name T296
Test name
Test status
Simulation time 96702986 ps
CPU time 0.88 seconds
Started Jun 09 01:30:43 PM PDT 24
Finished Jun 09 01:30:44 PM PDT 24
Peak memory 212060 kb
Host smart-b38251a6-a608-425e-ada7-8a17cfe99766
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479142948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.1479142948
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.537180877
Short name T510
Test name
Test status
Simulation time 27701475 ps
CPU time 0.99 seconds
Started Jun 09 01:30:51 PM PDT 24
Finished Jun 09 01:30:53 PM PDT 24
Peak memory 208964 kb
Host smart-30fff434-ffb7-40fc-a865-8ee886724414
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537180877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.537180877
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1952231785
Short name T720
Test name
Test status
Simulation time 1568423466 ps
CPU time 13.22 seconds
Started Jun 09 01:30:46 PM PDT 24
Finished Jun 09 01:30:59 PM PDT 24
Peak memory 218224 kb
Host smart-fc5aeeb1-b641-4ca3-bd9e-e3088317f0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952231785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1952231785
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.954182543
Short name T647
Test name
Test status
Simulation time 3605701745 ps
CPU time 8.91 seconds
Started Jun 09 01:30:51 PM PDT 24
Finished Jun 09 01:31:00 PM PDT 24
Peak memory 217808 kb
Host smart-6d867655-b96b-402e-a4ef-fa035173e24a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954182543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.954182543
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.2841811879
Short name T722
Test name
Test status
Simulation time 1366538497 ps
CPU time 20.96 seconds
Started Jun 09 01:30:54 PM PDT 24
Finished Jun 09 01:31:15 PM PDT 24
Peak memory 225328 kb
Host smart-61f80ed6-c903-49c5-9b18-095be375f434
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841811879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.2841811879
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1779578653
Short name T733
Test name
Test status
Simulation time 830268002 ps
CPU time 12.1 seconds
Started Jun 09 01:30:52 PM PDT 24
Finished Jun 09 01:31:04 PM PDT 24
Peak memory 225180 kb
Host smart-0ae92341-1b18-4298-9ccc-aec401fc002d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779578653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1779578653
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1859554592
Short name T504
Test name
Test status
Simulation time 321461993 ps
CPU time 3.01 seconds
Started Jun 09 01:30:46 PM PDT 24
Finished Jun 09 01:30:49 PM PDT 24
Peak memory 217720 kb
Host smart-ee4abe6d-c5f8-49de-856b-60d93e874898
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859554592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1859554592
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1649610090
Short name T388
Test name
Test status
Simulation time 1738133865 ps
CPU time 41.2 seconds
Started Jun 09 01:30:53 PM PDT 24
Finished Jun 09 01:31:34 PM PDT 24
Peak memory 267232 kb
Host smart-5c55dacf-533f-4c77-a9a2-97a35db7f08c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649610090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1649610090
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2214593732
Short name T242
Test name
Test status
Simulation time 759584576 ps
CPU time 10.71 seconds
Started Jun 09 01:30:52 PM PDT 24
Finished Jun 09 01:31:03 PM PDT 24
Peak memory 245632 kb
Host smart-f0c0f223-deac-4420-aa66-02fcf03b93d1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214593732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.2214593732
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.2152727143
Short name T573
Test name
Test status
Simulation time 87796710 ps
CPU time 3.49 seconds
Started Jun 09 01:30:45 PM PDT 24
Finished Jun 09 01:30:49 PM PDT 24
Peak memory 218240 kb
Host smart-12965d3c-a6f7-4f41-b800-c749c4fa56ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152727143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2152727143
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.3279381682
Short name T512
Test name
Test status
Simulation time 5443294432 ps
CPU time 16.16 seconds
Started Jun 09 01:30:52 PM PDT 24
Finished Jun 09 01:31:08 PM PDT 24
Peak memory 220208 kb
Host smart-c1d0098b-f55c-4a2b-af18-f78b04162bff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279381682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.3279381682
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2976242564
Short name T663
Test name
Test status
Simulation time 779162005 ps
CPU time 15.95 seconds
Started Jun 09 01:30:52 PM PDT 24
Finished Jun 09 01:31:08 PM PDT 24
Peak memory 218268 kb
Host smart-6aed93ac-550b-46d4-a6b7-81b39beaf7ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976242564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.2976242564
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3821207336
Short name T821
Test name
Test status
Simulation time 5491492086 ps
CPU time 10.66 seconds
Started Jun 09 01:30:52 PM PDT 24
Finished Jun 09 01:31:03 PM PDT 24
Peak memory 225972 kb
Host smart-f4efa0c8-9602-4fc6-bbf8-54bb88992f5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821207336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3821207336
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.1364174531
Short name T653
Test name
Test status
Simulation time 2497396412 ps
CPU time 8.33 seconds
Started Jun 09 01:30:48 PM PDT 24
Finished Jun 09 01:30:56 PM PDT 24
Peak memory 225292 kb
Host smart-a6dd9a93-b4cd-4de9-8ddb-9ebe7f8e18c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364174531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.1364174531
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.1749775815
Short name T819
Test name
Test status
Simulation time 174288962 ps
CPU time 3.16 seconds
Started Jun 09 01:30:48 PM PDT 24
Finished Jun 09 01:30:51 PM PDT 24
Peak memory 214840 kb
Host smart-4c0a68aa-28ac-4444-b155-6ee8e5cc33f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749775815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.1749775815
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.683614398
Short name T721
Test name
Test status
Simulation time 538906315 ps
CPU time 31.06 seconds
Started Jun 09 01:30:45 PM PDT 24
Finished Jun 09 01:31:17 PM PDT 24
Peak memory 250912 kb
Host smart-79553586-9b91-4147-a6c1-4a92a6b9ef9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683614398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.683614398
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2534187849
Short name T587
Test name
Test status
Simulation time 79424457 ps
CPU time 7.71 seconds
Started Jun 09 01:30:48 PM PDT 24
Finished Jun 09 01:30:56 PM PDT 24
Peak memory 250904 kb
Host smart-fe84c2f0-7c52-47ba-babf-3bebe592f5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534187849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2534187849
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2586485475
Short name T867
Test name
Test status
Simulation time 75021260394 ps
CPU time 110.03 seconds
Started Jun 09 01:30:55 PM PDT 24
Finished Jun 09 01:32:45 PM PDT 24
Peak memory 271372 kb
Host smart-0d243ccb-5252-423a-82d6-c1f9e2125042
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586485475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2586485475
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1754144604
Short name T770
Test name
Test status
Simulation time 40360779 ps
CPU time 0.78 seconds
Started Jun 09 01:30:45 PM PDT 24
Finished Jun 09 01:30:46 PM PDT 24
Peak memory 208096 kb
Host smart-20790390-29cd-48cd-b5e4-f42d67a787ea
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754144604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.1754144604
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.4243513435
Short name T73
Test name
Test status
Simulation time 22436536 ps
CPU time 0.87 seconds
Started Jun 09 01:31:05 PM PDT 24
Finished Jun 09 01:31:07 PM PDT 24
Peak memory 208984 kb
Host smart-9382c5a3-035b-4576-a69b-9dca7c6ae4db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243513435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.4243513435
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.3402334924
Short name T642
Test name
Test status
Simulation time 1790687714 ps
CPU time 13.02 seconds
Started Jun 09 01:30:58 PM PDT 24
Finished Jun 09 01:31:11 PM PDT 24
Peak memory 218420 kb
Host smart-d8166011-43c3-4d54-81a6-00b849a1edde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402334924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.3402334924
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.4060387359
Short name T32
Test name
Test status
Simulation time 781625645 ps
CPU time 16.79 seconds
Started Jun 09 01:30:59 PM PDT 24
Finished Jun 09 01:31:16 PM PDT 24
Peak memory 217344 kb
Host smart-f50cf1e1-d071-4291-8603-de2233933d44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060387359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.4060387359
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.2156926766
Short name T225
Test name
Test status
Simulation time 1308559861 ps
CPU time 21.52 seconds
Started Jun 09 01:30:58 PM PDT 24
Finished Jun 09 01:31:20 PM PDT 24
Peak memory 218160 kb
Host smart-1adb8823-a56f-4f8f-b5aa-9f4e13f7750b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156926766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.2156926766
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2549517455
Short name T394
Test name
Test status
Simulation time 182150989 ps
CPU time 3.94 seconds
Started Jun 09 01:30:58 PM PDT 24
Finished Jun 09 01:31:03 PM PDT 24
Peak memory 218120 kb
Host smart-3a31b280-06c7-4d15-afba-899fac6477ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549517455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2549517455
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2045581849
Short name T800
Test name
Test status
Simulation time 357890871 ps
CPU time 5.04 seconds
Started Jun 09 01:30:58 PM PDT 24
Finished Jun 09 01:31:04 PM PDT 24
Peak memory 217692 kb
Host smart-3b079d4d-5faa-4209-9013-365c5e140c0c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045581849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2045581849
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2137638729
Short name T472
Test name
Test status
Simulation time 2005563769 ps
CPU time 70.52 seconds
Started Jun 09 01:30:59 PM PDT 24
Finished Jun 09 01:32:10 PM PDT 24
Peak memory 267224 kb
Host smart-6a7d6a77-1c82-447f-8737-cf37257a4881
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137638729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2137638729
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1917701152
Short name T723
Test name
Test status
Simulation time 654624722 ps
CPU time 12.03 seconds
Started Jun 09 01:30:58 PM PDT 24
Finished Jun 09 01:31:11 PM PDT 24
Peak memory 246684 kb
Host smart-219cbef7-797a-47c4-b730-e446bb2982a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917701152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1917701152
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.115409793
Short name T493
Test name
Test status
Simulation time 43441095 ps
CPU time 1.53 seconds
Started Jun 09 01:30:58 PM PDT 24
Finished Jun 09 01:31:00 PM PDT 24
Peak memory 221876 kb
Host smart-e160a871-4429-449a-9ae3-1591c8f991bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115409793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.115409793
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.1756938422
Short name T706
Test name
Test status
Simulation time 449387875 ps
CPU time 13.67 seconds
Started Jun 09 01:30:58 PM PDT 24
Finished Jun 09 01:31:12 PM PDT 24
Peak memory 218928 kb
Host smart-110ff5b5-a14d-4129-8f9c-b70db60601c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756938422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.1756938422
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.1516384970
Short name T643
Test name
Test status
Simulation time 862953582 ps
CPU time 10.07 seconds
Started Jun 09 01:31:02 PM PDT 24
Finished Jun 09 01:31:12 PM PDT 24
Peak memory 226268 kb
Host smart-988bdf1e-127e-48f0-87b5-9c562bf6d94c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516384970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.1516384970
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.3165875771
Short name T525
Test name
Test status
Simulation time 703251234 ps
CPU time 10.22 seconds
Started Jun 09 01:31:00 PM PDT 24
Finished Jun 09 01:31:11 PM PDT 24
Peak memory 218284 kb
Host smart-e70944fa-9d84-4bd6-8be1-bd22d25f6301
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165875771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
3165875771
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2674661067
Short name T666
Test name
Test status
Simulation time 4664547721 ps
CPU time 12.24 seconds
Started Jun 09 01:30:59 PM PDT 24
Finished Jun 09 01:31:12 PM PDT 24
Peak memory 226136 kb
Host smart-97e0964b-f643-4db3-acd9-42830e4c6877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674661067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2674661067
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.96156772
Short name T412
Test name
Test status
Simulation time 21264088 ps
CPU time 1.54 seconds
Started Jun 09 01:30:53 PM PDT 24
Finished Jun 09 01:30:55 PM PDT 24
Peak memory 217756 kb
Host smart-70f69110-2a40-4abc-9fd7-b5162295b041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96156772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.96156772
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.3859292122
Short name T660
Test name
Test status
Simulation time 180544289 ps
CPU time 20.55 seconds
Started Jun 09 01:30:52 PM PDT 24
Finished Jun 09 01:31:13 PM PDT 24
Peak memory 250928 kb
Host smart-5d352cd8-6ff4-49e1-a908-de767821d961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859292122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.3859292122
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1882614197
Short name T505
Test name
Test status
Simulation time 183241807 ps
CPU time 8.56 seconds
Started Jun 09 01:30:57 PM PDT 24
Finished Jun 09 01:31:06 PM PDT 24
Peak memory 250904 kb
Host smart-fc847496-449c-443d-8af2-0636c53974cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882614197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1882614197
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3837091435
Short name T648
Test name
Test status
Simulation time 9742587712 ps
CPU time 28.23 seconds
Started Jun 09 01:31:03 PM PDT 24
Finished Jun 09 01:31:32 PM PDT 24
Peak memory 246180 kb
Host smart-41738276-8cef-48ac-b897-ea127100de31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837091435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3837091435
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.2094844276
Short name T147
Test name
Test status
Simulation time 272758820391 ps
CPU time 1626.81 seconds
Started Jun 09 01:31:04 PM PDT 24
Finished Jun 09 01:58:11 PM PDT 24
Peak memory 349468 kb
Host smart-8218885f-c161-49a3-b523-eac13e027ae8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2094844276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.2094844276
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.743564600
Short name T240
Test name
Test status
Simulation time 12713617 ps
CPU time 0.86 seconds
Started Jun 09 01:30:51 PM PDT 24
Finished Jun 09 01:30:52 PM PDT 24
Peak memory 211856 kb
Host smart-54394eed-9c37-461b-8d0a-1246355c55b7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743564600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_volatile_unlock_smoke.743564600
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.3033083368
Short name T310
Test name
Test status
Simulation time 19746240 ps
CPU time 1.17 seconds
Started Jun 09 01:31:09 PM PDT 24
Finished Jun 09 01:31:11 PM PDT 24
Peak memory 208912 kb
Host smart-ff067e08-63a7-40ba-9eb5-57f6a5b07ae5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033083368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3033083368
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.1352508577
Short name T356
Test name
Test status
Simulation time 1664159083 ps
CPU time 17.6 seconds
Started Jun 09 01:31:05 PM PDT 24
Finished Jun 09 01:31:22 PM PDT 24
Peak memory 218172 kb
Host smart-bcde5c3a-62a6-4dca-8fdc-0de6788b0021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352508577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1352508577
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.1438460577
Short name T316
Test name
Test status
Simulation time 2344798987 ps
CPU time 13.24 seconds
Started Jun 09 01:31:09 PM PDT 24
Finished Jun 09 01:31:23 PM PDT 24
Peak memory 217492 kb
Host smart-ba454f46-4596-4b02-8804-b3ae78281bb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438460577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.1438460577
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.377670783
Short name T814
Test name
Test status
Simulation time 2160682749 ps
CPU time 34.31 seconds
Started Jun 09 01:31:11 PM PDT 24
Finished Jun 09 01:31:45 PM PDT 24
Peak memory 218252 kb
Host smart-add72abb-24f3-4e7f-b101-0f3789e44fa4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377670783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_er
rors.377670783
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.514632578
Short name T166
Test name
Test status
Simulation time 1059168185 ps
CPU time 2.73 seconds
Started Jun 09 01:31:08 PM PDT 24
Finished Jun 09 01:31:11 PM PDT 24
Peak memory 218116 kb
Host smart-7b166f2d-8283-42bd-8f7e-b2c45a4ef6b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514632578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag
_prog_failure.514632578
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.839930866
Short name T298
Test name
Test status
Simulation time 45238945 ps
CPU time 1.36 seconds
Started Jun 09 01:31:03 PM PDT 24
Finished Jun 09 01:31:05 PM PDT 24
Peak memory 217788 kb
Host smart-71e67da4-06e5-4be3-ab74-de58159e0e85
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839930866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.
839930866
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.52816032
Short name T830
Test name
Test status
Simulation time 2589760690 ps
CPU time 81.13 seconds
Started Jun 09 01:31:08 PM PDT 24
Finished Jun 09 01:32:29 PM PDT 24
Peak memory 276668 kb
Host smart-118657b9-c8b8-4b3b-83cd-63608e730ea5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52816032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag
_state_failure.52816032
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2489674908
Short name T813
Test name
Test status
Simulation time 1694720041 ps
CPU time 27.78 seconds
Started Jun 09 01:31:09 PM PDT 24
Finished Jun 09 01:31:37 PM PDT 24
Peak memory 250324 kb
Host smart-1c6b0d7a-9bdd-4d7d-8c08-b3237a48e998
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489674908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.2489674908
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.868252340
Short name T828
Test name
Test status
Simulation time 66148292 ps
CPU time 2.64 seconds
Started Jun 09 01:31:03 PM PDT 24
Finished Jun 09 01:31:06 PM PDT 24
Peak memory 218224 kb
Host smart-75c37c41-5ff4-4a89-bc24-7ba323de885d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868252340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.868252340
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.2434807133
Short name T58
Test name
Test status
Simulation time 996842531 ps
CPU time 14.91 seconds
Started Jun 09 01:31:10 PM PDT 24
Finished Jun 09 01:31:25 PM PDT 24
Peak memory 219028 kb
Host smart-40378276-cad8-4462-8425-1068218d9566
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434807133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2434807133
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.2196341472
Short name T551
Test name
Test status
Simulation time 9674544026 ps
CPU time 14.39 seconds
Started Jun 09 01:31:09 PM PDT 24
Finished Jun 09 01:31:23 PM PDT 24
Peak memory 226136 kb
Host smart-12ea5ff6-3491-4d20-b3d6-9d2d366e2b72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196341472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.2196341472
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1062209509
Short name T462
Test name
Test status
Simulation time 675224547 ps
CPU time 13.12 seconds
Started Jun 09 01:31:11 PM PDT 24
Finished Jun 09 01:31:24 PM PDT 24
Peak memory 226096 kb
Host smart-a04f4d99-62d3-4ea4-9f55-5754c7529e0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062209509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
1062209509
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.3880520733
Short name T534
Test name
Test status
Simulation time 205194727 ps
CPU time 9.48 seconds
Started Jun 09 01:31:01 PM PDT 24
Finished Jun 09 01:31:11 PM PDT 24
Peak memory 218552 kb
Host smart-8bf1a3de-1399-4c69-9709-b608b33232ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880520733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.3880520733
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1471287144
Short name T257
Test name
Test status
Simulation time 229778561 ps
CPU time 3.45 seconds
Started Jun 09 01:31:03 PM PDT 24
Finished Jun 09 01:31:07 PM PDT 24
Peak memory 217756 kb
Host smart-a66a5cf1-59df-4d95-95e4-5209563abce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471287144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1471287144
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2458421297
Short name T407
Test name
Test status
Simulation time 307722585 ps
CPU time 30.73 seconds
Started Jun 09 01:31:06 PM PDT 24
Finished Jun 09 01:31:37 PM PDT 24
Peak memory 250908 kb
Host smart-9b36a580-b0f2-47c3-ad3e-cbf1c6873a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458421297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2458421297
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.3682336540
Short name T266
Test name
Test status
Simulation time 332886245 ps
CPU time 3.2 seconds
Started Jun 09 01:31:07 PM PDT 24
Finished Jun 09 01:31:10 PM PDT 24
Peak memory 222444 kb
Host smart-04fbb741-ca4b-4f70-843f-7118d1e79108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682336540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3682336540
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.3859054064
Short name T594
Test name
Test status
Simulation time 10372291737 ps
CPU time 92.39 seconds
Started Jun 09 01:31:09 PM PDT 24
Finished Jun 09 01:32:41 PM PDT 24
Peak memory 267316 kb
Host smart-d2823f1e-b733-46b1-893d-ffb06a90c163
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859054064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.3859054064
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2019191094
Short name T543
Test name
Test status
Simulation time 13052625 ps
CPU time 0.86 seconds
Started Jun 09 01:31:02 PM PDT 24
Finished Jun 09 01:31:03 PM PDT 24
Peak memory 211964 kb
Host smart-0f07cbfb-081c-46dc-9a90-aaa3046f6515
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019191094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.2019191094
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.127528041
Short name T234
Test name
Test status
Simulation time 81672953 ps
CPU time 1.11 seconds
Started Jun 09 01:31:22 PM PDT 24
Finished Jun 09 01:31:23 PM PDT 24
Peak memory 208968 kb
Host smart-f4d2b118-96f0-4cd3-be85-c865e8a9c443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127528041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.127528041
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2250248310
Short name T99
Test name
Test status
Simulation time 1046708684 ps
CPU time 10.26 seconds
Started Jun 09 01:31:18 PM PDT 24
Finished Jun 09 01:31:28 PM PDT 24
Peak memory 218224 kb
Host smart-4acb3ec4-048c-4d27-a616-865c7bbee7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250248310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2250248310
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.574395529
Short name T162
Test name
Test status
Simulation time 210816950 ps
CPU time 1.07 seconds
Started Jun 09 01:31:16 PM PDT 24
Finished Jun 09 01:31:17 PM PDT 24
Peak memory 217156 kb
Host smart-f595e93a-6630-4c05-b9e8-a5b07260fb71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574395529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.574395529
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1116426523
Short name T846
Test name
Test status
Simulation time 2594991242 ps
CPU time 22.46 seconds
Started Jun 09 01:31:15 PM PDT 24
Finished Jun 09 01:31:37 PM PDT 24
Peak memory 226060 kb
Host smart-8a0453de-e242-4a99-90b6-c98deba67ae6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116426523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1116426523
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.3379943528
Short name T711
Test name
Test status
Simulation time 1097169753 ps
CPU time 8.77 seconds
Started Jun 09 01:31:16 PM PDT 24
Finished Jun 09 01:31:25 PM PDT 24
Peak memory 224448 kb
Host smart-e75c699b-f3d1-4acf-b692-60efcae49b0e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379943528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.3379943528
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3053800896
Short name T77
Test name
Test status
Simulation time 2445684499 ps
CPU time 4.45 seconds
Started Jun 09 01:31:16 PM PDT 24
Finished Jun 09 01:31:21 PM PDT 24
Peak memory 217748 kb
Host smart-6a2ef927-ef44-4e20-bc57-56fec87e13c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053800896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.3053800896
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2464340321
Short name T659
Test name
Test status
Simulation time 10743322922 ps
CPU time 61.52 seconds
Started Jun 09 01:31:15 PM PDT 24
Finished Jun 09 01:32:17 PM PDT 24
Peak memory 275480 kb
Host smart-2c4cd3ec-cca9-4ad9-b059-3e0458904ade
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464340321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.2464340321
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.3090258084
Short name T326
Test name
Test status
Simulation time 426457022 ps
CPU time 12.97 seconds
Started Jun 09 01:31:15 PM PDT 24
Finished Jun 09 01:31:28 PM PDT 24
Peak memory 250828 kb
Host smart-fbf4bec8-bd68-4e62-8e73-ca6c2061217d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090258084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.3090258084
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1626115971
Short name T734
Test name
Test status
Simulation time 23228132 ps
CPU time 1.68 seconds
Started Jun 09 01:31:15 PM PDT 24
Finished Jun 09 01:31:17 PM PDT 24
Peak memory 221924 kb
Host smart-508881e1-dcce-4532-aaad-093fffdb0551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626115971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1626115971
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.1314509468
Short name T487
Test name
Test status
Simulation time 3771363615 ps
CPU time 23.85 seconds
Started Jun 09 01:31:15 PM PDT 24
Finished Jun 09 01:31:39 PM PDT 24
Peak memory 218984 kb
Host smart-393382a6-abfa-4a6c-8a92-7915019ce480
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314509468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1314509468
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2992319960
Short name T597
Test name
Test status
Simulation time 1345328870 ps
CPU time 9.78 seconds
Started Jun 09 01:31:21 PM PDT 24
Finished Jun 09 01:31:31 PM PDT 24
Peak memory 218256 kb
Host smart-2f36db75-f709-4f4d-99bd-e149c0b0e190
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992319960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2992319960
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.391597512
Short name T627
Test name
Test status
Simulation time 715011783 ps
CPU time 8.57 seconds
Started Jun 09 01:31:18 PM PDT 24
Finished Jun 09 01:31:27 PM PDT 24
Peak memory 218268 kb
Host smart-7f20d941-89d5-483c-95c8-dac1bc49d3d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391597512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.391597512
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.1629686220
Short name T737
Test name
Test status
Simulation time 556294182 ps
CPU time 10.75 seconds
Started Jun 09 01:31:14 PM PDT 24
Finished Jun 09 01:31:25 PM PDT 24
Peak memory 218288 kb
Host smart-d7cc091d-3cdd-4143-88bc-5b87ff3901fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629686220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.1629686220
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1886728842
Short name T74
Test name
Test status
Simulation time 34779616 ps
CPU time 2.1 seconds
Started Jun 09 01:31:13 PM PDT 24
Finished Jun 09 01:31:16 PM PDT 24
Peak memory 217812 kb
Host smart-92fb3bfd-3de0-452c-95af-a741ab81b3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886728842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1886728842
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.3217590329
Short name T848
Test name
Test status
Simulation time 74655356 ps
CPU time 7.46 seconds
Started Jun 09 01:31:13 PM PDT 24
Finished Jun 09 01:31:21 PM PDT 24
Peak memory 250668 kb
Host smart-96783cb9-104d-4aa8-90a5-08af7d11243f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217590329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.3217590329
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3080002439
Short name T458
Test name
Test status
Simulation time 852843039 ps
CPU time 12.88 seconds
Started Jun 09 01:31:20 PM PDT 24
Finished Jun 09 01:31:33 PM PDT 24
Peak memory 226068 kb
Host smart-6a31cda2-e595-4307-9931-8c259f927517
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080002439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3080002439
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.279869626
Short name T90
Test name
Test status
Simulation time 145411910323 ps
CPU time 714.12 seconds
Started Jun 09 01:31:20 PM PDT 24
Finished Jun 09 01:43:14 PM PDT 24
Peak memory 333024 kb
Host smart-3722c794-ecdf-43b9-a7de-a8e82b665bca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=279869626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.279869626
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.4203802266
Short name T524
Test name
Test status
Simulation time 63839320 ps
CPU time 1.19 seconds
Started Jun 09 01:31:11 PM PDT 24
Finished Jun 09 01:31:12 PM PDT 24
Peak memory 217852 kb
Host smart-3f4bf33c-2879-4caa-8cd2-82494b943fbf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203802266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.4203802266
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2197581260
Short name T613
Test name
Test status
Simulation time 77919190 ps
CPU time 0.88 seconds
Started Jun 09 01:31:26 PM PDT 24
Finished Jun 09 01:31:27 PM PDT 24
Peak memory 208948 kb
Host smart-ef62c308-5472-44a3-86fe-f50c1e0d2e6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197581260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2197581260
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.2097419225
Short name T569
Test name
Test status
Simulation time 390882604 ps
CPU time 12.42 seconds
Started Jun 09 01:31:20 PM PDT 24
Finished Jun 09 01:31:32 PM PDT 24
Peak memory 218320 kb
Host smart-8f47977c-79e4-4175-a482-3370a6e9b046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097419225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.2097419225
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.3079067390
Short name T26
Test name
Test status
Simulation time 430065066 ps
CPU time 6.01 seconds
Started Jun 09 01:31:20 PM PDT 24
Finished Jun 09 01:31:26 PM PDT 24
Peak memory 217408 kb
Host smart-752a5206-ee91-4c92-84c8-bc5852f0df6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079067390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.3079067390
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.173164879
Short name T633
Test name
Test status
Simulation time 2855776362 ps
CPU time 41.91 seconds
Started Jun 09 01:31:19 PM PDT 24
Finished Jun 09 01:32:01 PM PDT 24
Peak memory 225716 kb
Host smart-df74d41e-c6ad-4ffc-97b3-c1570ab6a640
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173164879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_er
rors.173164879
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.957065171
Short name T634
Test name
Test status
Simulation time 114631212 ps
CPU time 4.23 seconds
Started Jun 09 01:31:20 PM PDT 24
Finished Jun 09 01:31:24 PM PDT 24
Peak memory 221828 kb
Host smart-dca86df8-c762-431a-ae09-4ee72acd65ed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957065171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag
_prog_failure.957065171
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3928060797
Short name T526
Test name
Test status
Simulation time 382386143 ps
CPU time 3.05 seconds
Started Jun 09 01:31:21 PM PDT 24
Finished Jun 09 01:31:24 PM PDT 24
Peak memory 217696 kb
Host smart-705503d5-aa76-49b5-a4f8-7a43713590f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928060797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3928060797
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.159777500
Short name T707
Test name
Test status
Simulation time 21925458885 ps
CPU time 51.83 seconds
Started Jun 09 01:31:19 PM PDT 24
Finished Jun 09 01:32:11 PM PDT 24
Peak memory 277920 kb
Host smart-d53c629c-a4b5-4efa-9439-21ccde2c685a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159777500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_state_failure.159777500
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.1276216426
Short name T508
Test name
Test status
Simulation time 799751397 ps
CPU time 11.19 seconds
Started Jun 09 01:31:18 PM PDT 24
Finished Jun 09 01:31:29 PM PDT 24
Peak memory 247184 kb
Host smart-14bf767f-da17-496d-b581-af36544a67c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276216426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.1276216426
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2932302623
Short name T498
Test name
Test status
Simulation time 40416239 ps
CPU time 2.61 seconds
Started Jun 09 01:31:20 PM PDT 24
Finished Jun 09 01:31:23 PM PDT 24
Peak memory 218228 kb
Host smart-84e63528-3738-43c8-b097-ac025bb32916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932302623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2932302623
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1804452453
Short name T488
Test name
Test status
Simulation time 379439776 ps
CPU time 18.73 seconds
Started Jun 09 01:31:24 PM PDT 24
Finished Jun 09 01:31:42 PM PDT 24
Peak memory 218936 kb
Host smart-a093fe5e-ea56-41f8-8b7c-d7a989b3ef12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804452453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1804452453
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1276794783
Short name T806
Test name
Test status
Simulation time 620641308 ps
CPU time 23.57 seconds
Started Jun 09 01:31:27 PM PDT 24
Finished Jun 09 01:31:50 PM PDT 24
Peak memory 226100 kb
Host smart-ead2f180-11ac-4598-acd8-fc363383793c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276794783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.1276794783
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.1867731363
Short name T855
Test name
Test status
Simulation time 356703958 ps
CPU time 8.41 seconds
Started Jun 09 01:31:26 PM PDT 24
Finished Jun 09 01:31:35 PM PDT 24
Peak memory 218272 kb
Host smart-2a8364f7-b17d-4d26-92d6-0be38b8e248c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867731363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
1867731363
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.1693834751
Short name T387
Test name
Test status
Simulation time 1600875148 ps
CPU time 13.08 seconds
Started Jun 09 01:31:19 PM PDT 24
Finished Jun 09 01:31:33 PM PDT 24
Peak memory 218364 kb
Host smart-3c8b7ea7-6fed-4ae2-a14f-4d317d1a546d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693834751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1693834751
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3647179442
Short name T776
Test name
Test status
Simulation time 22775042 ps
CPU time 1.94 seconds
Started Jun 09 01:31:22 PM PDT 24
Finished Jun 09 01:31:24 PM PDT 24
Peak memory 214260 kb
Host smart-37907ab2-0d1d-4cb4-81e9-e138c48c564e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647179442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3647179442
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2240045716
Short name T522
Test name
Test status
Simulation time 898307246 ps
CPU time 24.94 seconds
Started Jun 09 01:31:19 PM PDT 24
Finished Jun 09 01:31:44 PM PDT 24
Peak memory 250952 kb
Host smart-dc5d2e58-49aa-4951-a19f-b5d0d87e4dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240045716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2240045716
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.2244350934
Short name T94
Test name
Test status
Simulation time 55446772 ps
CPU time 6.69 seconds
Started Jun 09 01:31:20 PM PDT 24
Finished Jun 09 01:31:27 PM PDT 24
Peak memory 248596 kb
Host smart-e4d5722a-fe71-438a-a103-b4d3f00e6546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244350934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.2244350934
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1000919766
Short name T24
Test name
Test status
Simulation time 5638599671 ps
CPU time 91.93 seconds
Started Jun 09 01:31:25 PM PDT 24
Finished Jun 09 01:32:57 PM PDT 24
Peak memory 226304 kb
Host smart-bc1ef30c-74d2-4f8b-a9dd-08970004f14a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000919766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1000919766
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.783435712
Short name T520
Test name
Test status
Simulation time 64511341 ps
CPU time 0.88 seconds
Started Jun 09 01:31:22 PM PDT 24
Finished Jun 09 01:31:23 PM PDT 24
Peak memory 212964 kb
Host smart-353d471f-8c89-4175-815a-5474981d6a9f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783435712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.783435712
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1598141020
Short name T477
Test name
Test status
Simulation time 50593783 ps
CPU time 0.85 seconds
Started Jun 09 01:31:34 PM PDT 24
Finished Jun 09 01:31:35 PM PDT 24
Peak memory 208804 kb
Host smart-1e0b370c-8287-4e65-a481-5e315dd7efad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598141020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1598141020
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.941739835
Short name T667
Test name
Test status
Simulation time 2073923308 ps
CPU time 16.17 seconds
Started Jun 09 01:31:27 PM PDT 24
Finished Jun 09 01:31:44 PM PDT 24
Peak memory 218288 kb
Host smart-dd8d2967-5e8e-436f-a4f1-05d17307112e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941739835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.941739835
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3407575170
Short name T547
Test name
Test status
Simulation time 2865129451 ps
CPU time 52.98 seconds
Started Jun 09 01:31:33 PM PDT 24
Finished Jun 09 01:32:26 PM PDT 24
Peak memory 218908 kb
Host smart-6d752f65-a5b6-451a-b128-15859e72b111
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407575170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3407575170
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.1800905254
Short name T853
Test name
Test status
Simulation time 362664572 ps
CPU time 2.39 seconds
Started Jun 09 01:31:31 PM PDT 24
Finished Jun 09 01:31:34 PM PDT 24
Peak memory 221708 kb
Host smart-f506aca1-9a12-4d86-a433-66c9000280cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800905254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.1800905254
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.2245163098
Short name T818
Test name
Test status
Simulation time 1873145201 ps
CPU time 8.11 seconds
Started Jun 09 01:31:27 PM PDT 24
Finished Jun 09 01:31:35 PM PDT 24
Peak memory 217684 kb
Host smart-6c3f1c31-7afb-4b97-b235-5ec2745b30b2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245163098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.2245163098
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.987347528
Short name T866
Test name
Test status
Simulation time 15360929838 ps
CPU time 40.04 seconds
Started Jun 09 01:31:28 PM PDT 24
Finished Jun 09 01:32:08 PM PDT 24
Peak memory 275476 kb
Host smart-4dad8081-9264-4edb-aede-f09cbee6a6a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987347528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.987347528
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3206095845
Short name T245
Test name
Test status
Simulation time 1042568316 ps
CPU time 33.16 seconds
Started Jun 09 01:31:25 PM PDT 24
Finished Jun 09 01:31:58 PM PDT 24
Peak memory 250848 kb
Host smart-82e2c3b3-a1ba-4954-8811-e76ef94154e1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206095845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.3206095845
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1924023821
Short name T321
Test name
Test status
Simulation time 70701601 ps
CPU time 3.46 seconds
Started Jun 09 01:31:26 PM PDT 24
Finished Jun 09 01:31:30 PM PDT 24
Peak memory 218200 kb
Host smart-c1c43ae2-5332-4340-9978-a3ab13af5c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924023821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1924023821
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.2122543437
Short name T575
Test name
Test status
Simulation time 4935208386 ps
CPU time 10.74 seconds
Started Jun 09 01:31:33 PM PDT 24
Finished Jun 09 01:31:44 PM PDT 24
Peak memory 220064 kb
Host smart-c1a3f570-03e9-47ac-a765-53fcb86c2181
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122543437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.2122543437
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1820655992
Short name T374
Test name
Test status
Simulation time 9517842427 ps
CPU time 14.56 seconds
Started Jun 09 01:31:33 PM PDT 24
Finished Jun 09 01:31:48 PM PDT 24
Peak memory 218388 kb
Host smart-d75b6c7c-6231-4554-bed1-de6428c78251
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820655992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1820655992
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3248670346
Short name T322
Test name
Test status
Simulation time 304205249 ps
CPU time 11.33 seconds
Started Jun 09 01:31:33 PM PDT 24
Finished Jun 09 01:31:44 PM PDT 24
Peak memory 218272 kb
Host smart-654f8e44-e0c1-4bc2-a860-65cbeb1c6459
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248670346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
3248670346
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.737274922
Short name T840
Test name
Test status
Simulation time 1022334816 ps
CPU time 9.99 seconds
Started Jun 09 01:31:25 PM PDT 24
Finished Jun 09 01:31:35 PM PDT 24
Peak memory 226084 kb
Host smart-b9636af9-ea70-4faa-9d32-d1e1b4d2959e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737274922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.737274922
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.4159621001
Short name T175
Test name
Test status
Simulation time 126826716 ps
CPU time 2.27 seconds
Started Jun 09 01:31:25 PM PDT 24
Finished Jun 09 01:31:27 PM PDT 24
Peak memory 214564 kb
Host smart-d6d6cf96-eaa1-4044-aeee-aff62c374e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159621001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.4159621001
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.835182621
Short name T232
Test name
Test status
Simulation time 1351817674 ps
CPU time 17.23 seconds
Started Jun 09 01:31:27 PM PDT 24
Finished Jun 09 01:31:44 PM PDT 24
Peak memory 250980 kb
Host smart-a695b63f-e402-4ea9-98f2-8381962631cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835182621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.835182621
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.37102509
Short name T829
Test name
Test status
Simulation time 120216961 ps
CPU time 7.02 seconds
Started Jun 09 01:31:25 PM PDT 24
Finished Jun 09 01:31:33 PM PDT 24
Peak memory 250892 kb
Host smart-769b79b5-27c9-4a78-9756-99084e681c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37102509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.37102509
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.210686624
Short name T863
Test name
Test status
Simulation time 53769064667 ps
CPU time 370.66 seconds
Started Jun 09 01:31:33 PM PDT 24
Finished Jun 09 01:37:44 PM PDT 24
Peak memory 234324 kb
Host smart-9ba6b1e2-e345-4c02-be11-f8483b9f0ba3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210686624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.210686624
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.797765985
Short name T615
Test name
Test status
Simulation time 42498263 ps
CPU time 0.91 seconds
Started Jun 09 01:31:25 PM PDT 24
Finished Jun 09 01:31:26 PM PDT 24
Peak memory 211884 kb
Host smart-8feb0969-33a7-4ce3-b9ae-2d842248afd5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797765985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.797765985
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.972417819
Short name T292
Test name
Test status
Simulation time 18550968 ps
CPU time 1.13 seconds
Started Jun 09 01:31:36 PM PDT 24
Finished Jun 09 01:31:37 PM PDT 24
Peak memory 208976 kb
Host smart-48f5b7dd-43c6-4d06-bfcf-61055af3da64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972417819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.972417819
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3750659217
Short name T555
Test name
Test status
Simulation time 1503238827 ps
CPU time 12.48 seconds
Started Jun 09 01:31:32 PM PDT 24
Finished Jun 09 01:31:45 PM PDT 24
Peak memory 226080 kb
Host smart-c7f2040f-453f-435c-9837-39b36853e4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750659217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3750659217
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.1341936705
Short name T728
Test name
Test status
Simulation time 3727955255 ps
CPU time 19.95 seconds
Started Jun 09 01:31:31 PM PDT 24
Finished Jun 09 01:31:51 PM PDT 24
Peak memory 217804 kb
Host smart-10631f25-f319-449b-87e0-be497d94a685
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341936705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.1341936705
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.3815166912
Short name T16
Test name
Test status
Simulation time 1330295190 ps
CPU time 41.53 seconds
Started Jun 09 01:31:34 PM PDT 24
Finished Jun 09 01:32:16 PM PDT 24
Peak memory 218216 kb
Host smart-6a0f1ce4-e09a-4eb4-be24-af743d981fe2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815166912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.3815166912
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3881401585
Short name T301
Test name
Test status
Simulation time 332789366 ps
CPU time 9.01 seconds
Started Jun 09 01:31:33 PM PDT 24
Finished Jun 09 01:31:42 PM PDT 24
Peak memory 223100 kb
Host smart-67187270-09a0-4b52-b699-128e39736a45
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881401585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3881401585
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.3752906707
Short name T868
Test name
Test status
Simulation time 1366479074 ps
CPU time 9.15 seconds
Started Jun 09 01:31:33 PM PDT 24
Finished Jun 09 01:31:43 PM PDT 24
Peak memory 217692 kb
Host smart-a881262a-1e3f-495e-946a-71c2317bc60c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752906707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.3752906707
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1184418190
Short name T730
Test name
Test status
Simulation time 1871039549 ps
CPU time 77.72 seconds
Started Jun 09 01:31:29 PM PDT 24
Finished Jun 09 01:32:47 PM PDT 24
Peak memory 283796 kb
Host smart-efb648d5-ebf7-4061-85fd-785d90025ba7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184418190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1184418190
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1710903381
Short name T107
Test name
Test status
Simulation time 647957069 ps
CPU time 15.33 seconds
Started Jun 09 01:31:32 PM PDT 24
Finished Jun 09 01:31:48 PM PDT 24
Peak memory 250844 kb
Host smart-e168f12c-c8b6-4e6c-b659-307103c54267
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710903381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.1710903381
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3042378414
Short name T391
Test name
Test status
Simulation time 203084612 ps
CPU time 2.64 seconds
Started Jun 09 01:31:33 PM PDT 24
Finished Jun 09 01:31:36 PM PDT 24
Peak memory 218304 kb
Host smart-2138a2ff-4b9b-4cdb-809f-87f55da431e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042378414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3042378414
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.2674787331
Short name T182
Test name
Test status
Simulation time 673441250 ps
CPU time 9.37 seconds
Started Jun 09 01:31:37 PM PDT 24
Finished Jun 09 01:31:47 PM PDT 24
Peak memory 218404 kb
Host smart-ff1aaf8b-0e60-4343-84c8-29bef479eeb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674787331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2674787331
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.228666812
Short name T550
Test name
Test status
Simulation time 3734700926 ps
CPU time 7.66 seconds
Started Jun 09 01:31:36 PM PDT 24
Finished Jun 09 01:31:44 PM PDT 24
Peak memory 218324 kb
Host smart-bf9db29c-a537-4fa6-b741-806b716a7ce8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228666812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_di
gest.228666812
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2512122611
Short name T18
Test name
Test status
Simulation time 595536206 ps
CPU time 8.99 seconds
Started Jun 09 01:31:36 PM PDT 24
Finished Jun 09 01:31:45 PM PDT 24
Peak memory 218268 kb
Host smart-e1facad9-a053-4076-b08d-e62de490bee6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512122611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2512122611
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2068692896
Short name T792
Test name
Test status
Simulation time 3676748705 ps
CPU time 8.65 seconds
Started Jun 09 01:31:31 PM PDT 24
Finished Jun 09 01:31:40 PM PDT 24
Peak memory 225652 kb
Host smart-1d2bdad5-1c77-424a-af33-88f76e50beca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068692896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2068692896
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.2949900767
Short name T838
Test name
Test status
Simulation time 44210360 ps
CPU time 2.01 seconds
Started Jun 09 01:31:32 PM PDT 24
Finished Jun 09 01:31:34 PM PDT 24
Peak memory 217760 kb
Host smart-046965c2-9322-467d-b423-f28eafdc8aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949900767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2949900767
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.3814022384
Short name T228
Test name
Test status
Simulation time 350605287 ps
CPU time 32.39 seconds
Started Jun 09 01:31:30 PM PDT 24
Finished Jun 09 01:32:03 PM PDT 24
Peak memory 250916 kb
Host smart-d6abac2c-ac77-46e4-a227-564c56295990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814022384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.3814022384
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.1900922
Short name T669
Test name
Test status
Simulation time 54043328 ps
CPU time 8.27 seconds
Started Jun 09 01:31:33 PM PDT 24
Finished Jun 09 01:31:41 PM PDT 24
Peak memory 242724 kb
Host smart-083e6db6-4fa5-43a3-9ef0-ba05b91f58b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1900922
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2125295261
Short name T591
Test name
Test status
Simulation time 14018110309 ps
CPU time 39.95 seconds
Started Jun 09 01:31:36 PM PDT 24
Finished Jun 09 01:32:16 PM PDT 24
Peak memory 250956 kb
Host smart-832e4244-def0-4f83-a1f7-322396870112
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125295261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2125295261
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2240166851
Short name T284
Test name
Test status
Simulation time 39485809 ps
CPU time 1.25 seconds
Started Jun 09 01:31:33 PM PDT 24
Finished Jun 09 01:31:35 PM PDT 24
Peak memory 213216 kb
Host smart-8c2eac1b-d2e7-4d31-a91d-7142cefd3aca
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240166851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.2240166851
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.1314923653
Short name T395
Test name
Test status
Simulation time 28104662 ps
CPU time 0.86 seconds
Started Jun 09 01:31:46 PM PDT 24
Finished Jun 09 01:31:47 PM PDT 24
Peak memory 208820 kb
Host smart-ce5d5980-2ced-461b-9ae1-9a674281b20f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314923653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1314923653
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.2993429078
Short name T801
Test name
Test status
Simulation time 3577696057 ps
CPU time 15.14 seconds
Started Jun 09 01:31:41 PM PDT 24
Finished Jun 09 01:31:57 PM PDT 24
Peak memory 217868 kb
Host smart-d11040c2-5aa1-4e94-a4a4-83df00abf635
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993429078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.2993429078
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.1470251545
Short name T837
Test name
Test status
Simulation time 9994897433 ps
CPU time 64.16 seconds
Started Jun 09 01:31:40 PM PDT 24
Finished Jun 09 01:32:45 PM PDT 24
Peak memory 218920 kb
Host smart-4d942f55-d4a8-4fbd-ac78-51a78c7cf3a1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470251545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.1470251545
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.3573792788
Short name T445
Test name
Test status
Simulation time 226540685 ps
CPU time 4.38 seconds
Started Jun 09 01:31:43 PM PDT 24
Finished Jun 09 01:31:48 PM PDT 24
Peak memory 218192 kb
Host smart-a3f6d5b3-6f43-4959-b3db-52a1c5efc11d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573792788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.3573792788
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1248905516
Short name T787
Test name
Test status
Simulation time 707320194 ps
CPU time 5.44 seconds
Started Jun 09 01:31:42 PM PDT 24
Finished Jun 09 01:31:47 PM PDT 24
Peak memory 217772 kb
Host smart-6099f499-06f4-46e0-bdbc-538e5fb548f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248905516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1248905516
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.1097201412
Short name T541
Test name
Test status
Simulation time 1194804939 ps
CPU time 53.77 seconds
Started Jun 09 01:31:40 PM PDT 24
Finished Jun 09 01:32:34 PM PDT 24
Peak memory 267224 kb
Host smart-86cb5412-1bc4-4494-b9f0-ae9b62785347
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097201412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.1097201412
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1976479422
Short name T307
Test name
Test status
Simulation time 424610202 ps
CPU time 8.08 seconds
Started Jun 09 01:31:46 PM PDT 24
Finished Jun 09 01:31:55 PM PDT 24
Peak memory 223980 kb
Host smart-f5e26bef-97b9-4d48-824d-781340984c2f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976479422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1976479422
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.1805442546
Short name T862
Test name
Test status
Simulation time 15194229 ps
CPU time 1.41 seconds
Started Jun 09 01:31:42 PM PDT 24
Finished Jun 09 01:31:43 PM PDT 24
Peak memory 218228 kb
Host smart-5eb41299-36dc-400c-b5c9-b52a2dd94d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805442546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.1805442546
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.299951787
Short name T755
Test name
Test status
Simulation time 1065868238 ps
CPU time 14 seconds
Started Jun 09 01:31:40 PM PDT 24
Finished Jun 09 01:31:55 PM PDT 24
Peak memory 218936 kb
Host smart-a4c84e8e-6197-43c3-a222-55844717987c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299951787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.299951787
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3596053407
Short name T53
Test name
Test status
Simulation time 3401814197 ps
CPU time 12.29 seconds
Started Jun 09 01:31:48 PM PDT 24
Finished Jun 09 01:32:00 PM PDT 24
Peak memory 226132 kb
Host smart-72c617c5-9db4-4b65-981c-5db016a007f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596053407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.3596053407
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.3114399794
Short name T440
Test name
Test status
Simulation time 3306363180 ps
CPU time 9.57 seconds
Started Jun 09 01:31:40 PM PDT 24
Finished Jun 09 01:31:49 PM PDT 24
Peak memory 218488 kb
Host smart-3d429dd9-4a19-49b9-9dc2-56fbc31d12de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114399794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
3114399794
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.212005986
Short name T810
Test name
Test status
Simulation time 289790618 ps
CPU time 8.87 seconds
Started Jun 09 01:31:40 PM PDT 24
Finished Jun 09 01:31:49 PM PDT 24
Peak memory 226104 kb
Host smart-e7273d56-866d-42e0-a844-afdbfcf54959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212005986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.212005986
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1071981050
Short name T342
Test name
Test status
Simulation time 90895473 ps
CPU time 1.38 seconds
Started Jun 09 01:31:45 PM PDT 24
Finished Jun 09 01:31:47 PM PDT 24
Peak memory 213864 kb
Host smart-dcb021eb-6f01-4898-806c-3ec15e9e0c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071981050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1071981050
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1096823477
Short name T494
Test name
Test status
Simulation time 853853991 ps
CPU time 23.04 seconds
Started Jun 09 01:31:40 PM PDT 24
Finished Jun 09 01:32:04 PM PDT 24
Peak memory 250916 kb
Host smart-339dc87c-244b-470f-8428-565a8caae36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096823477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1096823477
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.3727457684
Short name T226
Test name
Test status
Simulation time 77540311 ps
CPU time 4 seconds
Started Jun 09 01:31:43 PM PDT 24
Finished Jun 09 01:31:48 PM PDT 24
Peak memory 222256 kb
Host smart-7a5ea298-0d84-4c41-9afa-3d59d430fcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727457684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3727457684
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.388755027
Short name T482
Test name
Test status
Simulation time 2268244477 ps
CPU time 71.08 seconds
Started Jun 09 01:31:53 PM PDT 24
Finished Jun 09 01:33:04 PM PDT 24
Peak memory 250900 kb
Host smart-bb5a7fe6-66a1-4711-8839-871164fa1bc7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388755027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.388755027
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.110121957
Short name T109
Test name
Test status
Simulation time 38439324079 ps
CPU time 557.57 seconds
Started Jun 09 01:31:49 PM PDT 24
Finished Jun 09 01:41:07 PM PDT 24
Peak memory 422104 kb
Host smart-171b7444-3075-4913-affd-781f4d50be8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=110121957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.110121957
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.1032176409
Short name T274
Test name
Test status
Simulation time 20055501 ps
CPU time 0.86 seconds
Started Jun 09 01:31:41 PM PDT 24
Finished Jun 09 01:31:42 PM PDT 24
Peak memory 208236 kb
Host smart-637a27e7-0ea1-4291-bd52-c471ae0e778f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032176409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.1032176409
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.2334024326
Short name T85
Test name
Test status
Simulation time 12357519 ps
CPU time 0.79 seconds
Started Jun 09 01:29:22 PM PDT 24
Finished Jun 09 01:29:23 PM PDT 24
Peak memory 208744 kb
Host smart-9752848e-7960-485e-853a-897e1ca4f584
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334024326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2334024326
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.575752166
Short name T173
Test name
Test status
Simulation time 13918664 ps
CPU time 0.88 seconds
Started Jun 09 01:29:17 PM PDT 24
Finished Jun 09 01:29:18 PM PDT 24
Peak memory 208976 kb
Host smart-2f3d31b9-6078-4c21-8b75-8e1324aa5235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575752166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.575752166
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.3636961984
Short name T334
Test name
Test status
Simulation time 431191195 ps
CPU time 9.64 seconds
Started Jun 09 01:29:17 PM PDT 24
Finished Jun 09 01:29:27 PM PDT 24
Peak memory 218220 kb
Host smart-2b30dd3d-222b-492b-b3bd-9e4e453d80de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636961984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.3636961984
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1237994103
Short name T9
Test name
Test status
Simulation time 1479179987 ps
CPU time 4.11 seconds
Started Jun 09 01:30:10 PM PDT 24
Finished Jun 09 01:30:14 PM PDT 24
Peak memory 217432 kb
Host smart-7eb9cdd6-db92-4df8-b66e-acf5e5fe20a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237994103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1237994103
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.3046957072
Short name T36
Test name
Test status
Simulation time 5407064984 ps
CPU time 63.14 seconds
Started Jun 09 01:29:22 PM PDT 24
Finished Jun 09 01:30:25 PM PDT 24
Peak memory 226068 kb
Host smart-158d787c-14f4-45bd-b142-c748c8aa9d03
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046957072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.3046957072
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.2074729004
Short name T689
Test name
Test status
Simulation time 1551314238 ps
CPU time 10.43 seconds
Started Jun 09 01:29:23 PM PDT 24
Finished Jun 09 01:29:33 PM PDT 24
Peak memory 217624 kb
Host smart-558a0e54-c4e6-4be9-b088-0ef371cc287f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074729004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.2
074729004
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.4271044826
Short name T282
Test name
Test status
Simulation time 84310215 ps
CPU time 2.32 seconds
Started Jun 09 01:29:21 PM PDT 24
Finished Jun 09 01:29:24 PM PDT 24
Peak memory 221768 kb
Host smart-7386dd7f-29f9-42d9-b577-286ab97ca2b2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271044826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.4271044826
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2300690232
Short name T78
Test name
Test status
Simulation time 2780369866 ps
CPU time 10.33 seconds
Started Jun 09 01:29:20 PM PDT 24
Finished Jun 09 01:29:31 PM PDT 24
Peak memory 217760 kb
Host smart-6ca7f16f-ce03-4997-ade8-c42dd5b50747
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300690232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.2300690232
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.4134490863
Short name T596
Test name
Test status
Simulation time 2571207144 ps
CPU time 15.79 seconds
Started Jun 09 01:29:16 PM PDT 24
Finished Jun 09 01:29:32 PM PDT 24
Peak memory 217752 kb
Host smart-8417dd42-3976-4acd-83ea-732e2a6c7bb6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134490863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
4134490863
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.3154497453
Short name T463
Test name
Test status
Simulation time 4609862924 ps
CPU time 33.52 seconds
Started Jun 09 01:29:15 PM PDT 24
Finished Jun 09 01:29:49 PM PDT 24
Peak memory 267276 kb
Host smart-2dc79ac4-6ff6-40a4-bea0-fbf799978bf7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154497453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.3154497453
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3860121858
Short name T531
Test name
Test status
Simulation time 1247952177 ps
CPU time 39.46 seconds
Started Jun 09 01:30:11 PM PDT 24
Finished Jun 09 01:30:51 PM PDT 24
Peak memory 250848 kb
Host smart-7eef958e-0071-4ecf-a736-e02f774cb3b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860121858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.3860121858
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2341381440
Short name T386
Test name
Test status
Simulation time 56829304 ps
CPU time 1.62 seconds
Started Jun 09 01:29:17 PM PDT 24
Finished Jun 09 01:29:19 PM PDT 24
Peak memory 221700 kb
Host smart-963744de-8a18-45cf-b273-cf52957f3136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341381440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2341381440
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1329156444
Short name T187
Test name
Test status
Simulation time 214138066 ps
CPU time 11.86 seconds
Started Jun 09 01:29:17 PM PDT 24
Finished Jun 09 01:29:29 PM PDT 24
Peak memory 217728 kb
Host smart-050da21e-fbd6-4174-af2d-efde701cc2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329156444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1329156444
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2158917920
Short name T50
Test name
Test status
Simulation time 102531659 ps
CPU time 25.35 seconds
Started Jun 09 01:29:24 PM PDT 24
Finished Jun 09 01:29:50 PM PDT 24
Peak memory 282236 kb
Host smart-6d1457e0-69c7-41a1-8a1f-a8e3adfa3cb5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158917920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2158917920
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.3342090388
Short name T607
Test name
Test status
Simulation time 240417925 ps
CPU time 11.8 seconds
Started Jun 09 01:29:23 PM PDT 24
Finished Jun 09 01:29:35 PM PDT 24
Peak memory 218272 kb
Host smart-a2a1a6e6-2ee6-4cf9-bb0f-a03dffde3423
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342090388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.3342090388
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2603088050
Short name T571
Test name
Test status
Simulation time 1573928713 ps
CPU time 10.71 seconds
Started Jun 09 01:29:22 PM PDT 24
Finished Jun 09 01:29:33 PM PDT 24
Peak memory 218272 kb
Host smart-cd9bb934-a722-4028-8500-00a3ffe1e662
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603088050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2603088050
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1527473847
Short name T468
Test name
Test status
Simulation time 1419627346 ps
CPU time 13.17 seconds
Started Jun 09 01:29:22 PM PDT 24
Finished Jun 09 01:29:35 PM PDT 24
Peak memory 218264 kb
Host smart-0efca110-d5d9-43ba-9e66-9c61bbc2b52e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527473847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.1
527473847
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.1947479215
Short name T796
Test name
Test status
Simulation time 475409308 ps
CPU time 8.52 seconds
Started Jun 09 01:29:14 PM PDT 24
Finished Jun 09 01:29:23 PM PDT 24
Peak memory 226088 kb
Host smart-67186ac8-d028-425e-9a01-ff777a2a5be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947479215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1947479215
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.2584517990
Short name T670
Test name
Test status
Simulation time 42042462 ps
CPU time 2.95 seconds
Started Jun 09 01:29:15 PM PDT 24
Finished Jun 09 01:29:18 PM PDT 24
Peak memory 217776 kb
Host smart-67e90e4a-5d55-43b0-be27-cd5666472e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584517990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.2584517990
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.2587927725
Short name T431
Test name
Test status
Simulation time 3703145023 ps
CPU time 24.31 seconds
Started Jun 09 01:29:19 PM PDT 24
Finished Jun 09 01:29:43 PM PDT 24
Peak memory 250956 kb
Host smart-26b99207-1e70-4159-a7ea-0d3aab98d8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587927725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.2587927725
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.317394988
Short name T93
Test name
Test status
Simulation time 70130075 ps
CPU time 8.37 seconds
Started Jun 09 01:29:14 PM PDT 24
Finished Jun 09 01:29:23 PM PDT 24
Peak memory 250868 kb
Host smart-8b2d54ef-dec0-4e87-b5b5-1bc8b0cf523d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317394988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.317394988
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1405866156
Short name T832
Test name
Test status
Simulation time 32173372407 ps
CPU time 165.69 seconds
Started Jun 09 01:29:22 PM PDT 24
Finished Jun 09 01:32:08 PM PDT 24
Peak memory 250936 kb
Host smart-e8619650-0ad4-4c92-9d5f-05e6c2d8d617
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405866156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1405866156
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.786104871
Short name T843
Test name
Test status
Simulation time 12148139344 ps
CPU time 233.06 seconds
Started Jun 09 01:29:22 PM PDT 24
Finished Jun 09 01:33:15 PM PDT 24
Peak memory 283936 kb
Host smart-e49b23ab-655e-49e4-a920-f1d5e6592a98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=786104871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.786104871
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1556451723
Short name T650
Test name
Test status
Simulation time 11251960 ps
CPU time 0.95 seconds
Started Jun 09 01:29:16 PM PDT 24
Finished Jun 09 01:29:17 PM PDT 24
Peak memory 211848 kb
Host smart-87af9972-94ce-4143-89e7-be72f472e76c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556451723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.1556451723
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.3591982683
Short name T665
Test name
Test status
Simulation time 19414325 ps
CPU time 0.91 seconds
Started Jun 09 01:31:54 PM PDT 24
Finished Jun 09 01:31:55 PM PDT 24
Peak memory 208960 kb
Host smart-5ca2749a-b345-47c7-af58-1d776a719dbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591982683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.3591982683
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.1935566025
Short name T775
Test name
Test status
Simulation time 677522632 ps
CPU time 14.62 seconds
Started Jun 09 01:31:47 PM PDT 24
Finished Jun 09 01:32:02 PM PDT 24
Peak memory 218220 kb
Host smart-c90e8b26-b969-401a-af3d-5f23f405936b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935566025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1935566025
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.3304499664
Short name T461
Test name
Test status
Simulation time 12534167294 ps
CPU time 8.29 seconds
Started Jun 09 01:31:46 PM PDT 24
Finished Jun 09 01:31:55 PM PDT 24
Peak memory 217772 kb
Host smart-61b4ec41-57e4-49f4-bd37-4adfa6421c1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304499664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.3304499664
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.3858633777
Short name T623
Test name
Test status
Simulation time 202519899 ps
CPU time 2.32 seconds
Started Jun 09 01:31:48 PM PDT 24
Finished Jun 09 01:31:50 PM PDT 24
Peak memory 222176 kb
Host smart-6e3edf1f-7d4f-4b71-a0d4-75f6934b803c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858633777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.3858633777
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.454930906
Short name T545
Test name
Test status
Simulation time 615737640 ps
CPU time 17.43 seconds
Started Jun 09 01:31:52 PM PDT 24
Finished Jun 09 01:32:10 PM PDT 24
Peak memory 226096 kb
Host smart-35c84b5e-7b3f-4e07-85f1-e68a9a63146a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454930906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.454930906
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.1233922175
Short name T52
Test name
Test status
Simulation time 3595569274 ps
CPU time 23.95 seconds
Started Jun 09 01:31:51 PM PDT 24
Finished Jun 09 01:32:16 PM PDT 24
Peak memory 218324 kb
Host smart-fe9d7bd9-edf5-4012-85ae-1ee254bac830
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233922175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.1233922175
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1120476414
Short name T588
Test name
Test status
Simulation time 339917120 ps
CPU time 10.45 seconds
Started Jun 09 01:31:47 PM PDT 24
Finished Jun 09 01:31:57 PM PDT 24
Peak memory 226092 kb
Host smart-db370407-6058-4388-a4a7-9dbafc363c45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120476414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1120476414
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.815534181
Short name T768
Test name
Test status
Simulation time 501221199 ps
CPU time 11.39 seconds
Started Jun 09 01:31:47 PM PDT 24
Finished Jun 09 01:31:59 PM PDT 24
Peak memory 226084 kb
Host smart-a12c303b-62b3-4038-8414-edff1834bd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815534181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.815534181
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1472820331
Short name T851
Test name
Test status
Simulation time 99185072 ps
CPU time 3.02 seconds
Started Jun 09 01:31:52 PM PDT 24
Finished Jun 09 01:31:56 PM PDT 24
Peak memory 214712 kb
Host smart-999aeaf9-ef5b-44b6-aeef-368e747e987a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472820331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1472820331
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.2916810807
Short name T243
Test name
Test status
Simulation time 1373575871 ps
CPU time 39.28 seconds
Started Jun 09 01:31:48 PM PDT 24
Finished Jun 09 01:32:27 PM PDT 24
Peak memory 250912 kb
Host smart-3ff26f24-72a7-44a5-ae35-5b32aa8e43c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916810807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2916810807
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.2471447506
Short name T606
Test name
Test status
Simulation time 67362046 ps
CPU time 6.72 seconds
Started Jun 09 01:31:47 PM PDT 24
Finished Jun 09 01:31:54 PM PDT 24
Peak memory 242720 kb
Host smart-0694df25-1162-4916-a79f-d18e7611afb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471447506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2471447506
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.412207772
Short name T281
Test name
Test status
Simulation time 5640724725 ps
CPU time 308.03 seconds
Started Jun 09 01:31:52 PM PDT 24
Finished Jun 09 01:37:01 PM PDT 24
Peak memory 267348 kb
Host smart-8482b197-9d46-451e-9872-61240dd0534b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412207772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.412207772
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.314147913
Short name T91
Test name
Test status
Simulation time 51753699058 ps
CPU time 1546.99 seconds
Started Jun 09 01:31:52 PM PDT 24
Finished Jun 09 01:57:40 PM PDT 24
Peak memory 332956 kb
Host smart-a702064d-a36b-4ac3-91bb-cd1b686254dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=314147913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.314147913
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1148338524
Short name T614
Test name
Test status
Simulation time 49893556 ps
CPU time 0.86 seconds
Started Jun 09 01:31:48 PM PDT 24
Finished Jun 09 01:31:49 PM PDT 24
Peak memory 211968 kb
Host smart-39124946-cabe-4805-bbab-d69a5371f123
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148338524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1148338524
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.332836974
Short name T333
Test name
Test status
Simulation time 199159680 ps
CPU time 1.23 seconds
Started Jun 09 01:32:00 PM PDT 24
Finished Jun 09 01:32:02 PM PDT 24
Peak memory 209088 kb
Host smart-a1af5969-c1b9-4550-8890-93c93cf424b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332836974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.332836974
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.622114553
Short name T777
Test name
Test status
Simulation time 258569218 ps
CPU time 9.77 seconds
Started Jun 09 01:31:53 PM PDT 24
Finished Jun 09 01:32:03 PM PDT 24
Peak memory 218324 kb
Host smart-7be5c913-88b0-4a74-a2e5-4b7221b58278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622114553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.622114553
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.2872397785
Short name T507
Test name
Test status
Simulation time 4591105165 ps
CPU time 11.5 seconds
Started Jun 09 01:31:52 PM PDT 24
Finished Jun 09 01:32:04 PM PDT 24
Peak memory 217828 kb
Host smart-3cf2f55a-4621-45ce-a74d-aeee0bf28261
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872397785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.2872397785
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.312146351
Short name T430
Test name
Test status
Simulation time 76888528 ps
CPU time 2.74 seconds
Started Jun 09 01:31:52 PM PDT 24
Finished Jun 09 01:31:55 PM PDT 24
Peak memory 222576 kb
Host smart-0349e216-3bd8-4f77-9e07-15741dda4f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312146351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.312146351
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.3974011392
Short name T637
Test name
Test status
Simulation time 299588169 ps
CPU time 14.78 seconds
Started Jun 09 01:31:52 PM PDT 24
Finished Jun 09 01:32:07 PM PDT 24
Peak memory 226088 kb
Host smart-9eec6913-9d95-4974-89b1-8ceff69346d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974011392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3974011392
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2977964798
Short name T434
Test name
Test status
Simulation time 1201015999 ps
CPU time 13 seconds
Started Jun 09 01:32:00 PM PDT 24
Finished Jun 09 01:32:13 PM PDT 24
Peak memory 218264 kb
Host smart-7dd7341d-e050-4136-89ed-52a41fb67ad8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977964798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2977964798
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3045863319
Short name T762
Test name
Test status
Simulation time 867570045 ps
CPU time 8.83 seconds
Started Jun 09 01:31:59 PM PDT 24
Finished Jun 09 01:32:08 PM PDT 24
Peak memory 218256 kb
Host smart-d46fd56b-bb0a-4529-9bca-7241d6c05b36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045863319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3045863319
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.203729710
Short name T48
Test name
Test status
Simulation time 1257476995 ps
CPU time 13.88 seconds
Started Jun 09 01:31:56 PM PDT 24
Finished Jun 09 01:32:11 PM PDT 24
Peak memory 226044 kb
Host smart-a6780d9b-f6dc-4e47-ac7e-00b2039aa082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203729710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.203729710
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1280503592
Short name T290
Test name
Test status
Simulation time 183600308 ps
CPU time 3.01 seconds
Started Jun 09 01:31:52 PM PDT 24
Finished Jun 09 01:31:56 PM PDT 24
Peak memory 217764 kb
Host smart-3541e66c-75f7-4dc8-8933-a2ffc7a08876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280503592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1280503592
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.3466308624
Short name T171
Test name
Test status
Simulation time 987072482 ps
CPU time 21.24 seconds
Started Jun 09 01:31:52 PM PDT 24
Finished Jun 09 01:32:14 PM PDT 24
Peak memory 250992 kb
Host smart-e003ad74-c8fd-489f-aaa2-10e957c524e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466308624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3466308624
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3614540200
Short name T793
Test name
Test status
Simulation time 107226341 ps
CPU time 8.16 seconds
Started Jun 09 01:31:53 PM PDT 24
Finished Jun 09 01:32:02 PM PDT 24
Peak memory 250900 kb
Host smart-c85737d3-7645-4795-94a1-491291c630e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614540200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3614540200
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.982490357
Short name T654
Test name
Test status
Simulation time 18535129372 ps
CPU time 163.08 seconds
Started Jun 09 01:32:00 PM PDT 24
Finished Jun 09 01:34:43 PM PDT 24
Peak memory 251608 kb
Host smart-a73b367b-cc32-43f7-925f-77173cbbe30a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982490357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.982490357
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.4271663690
Short name T794
Test name
Test status
Simulation time 71232011 ps
CPU time 0.95 seconds
Started Jun 09 01:31:53 PM PDT 24
Finished Jun 09 01:31:54 PM PDT 24
Peak memory 211972 kb
Host smart-adb09293-bd72-4de5-ae24-fc9152798b41
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271663690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.4271663690
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2790450054
Short name T403
Test name
Test status
Simulation time 20262837 ps
CPU time 0.94 seconds
Started Jun 09 01:32:04 PM PDT 24
Finished Jun 09 01:32:06 PM PDT 24
Peak memory 209032 kb
Host smart-c8ff776f-0704-42e0-940e-4dbabab72c4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790450054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2790450054
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2821562826
Short name T255
Test name
Test status
Simulation time 565495786 ps
CPU time 13.49 seconds
Started Jun 09 01:31:57 PM PDT 24
Finished Jun 09 01:32:11 PM PDT 24
Peak memory 218252 kb
Host smart-4141112c-cceb-4b1c-8f1a-9f7efe89ef0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821562826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2821562826
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.2613815566
Short name T805
Test name
Test status
Simulation time 1064590538 ps
CPU time 12.26 seconds
Started Jun 09 01:32:04 PM PDT 24
Finished Jun 09 01:32:17 PM PDT 24
Peak memory 217456 kb
Host smart-4ee7d474-b10c-455d-9bae-b029bef460a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613815566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.2613815566
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2134956275
Short name T518
Test name
Test status
Simulation time 186583375 ps
CPU time 3.52 seconds
Started Jun 09 01:31:59 PM PDT 24
Finished Jun 09 01:32:03 PM PDT 24
Peak memory 222712 kb
Host smart-fd146366-e36e-4964-b5c6-6642233aecc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134956275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2134956275
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.209585100
Short name T578
Test name
Test status
Simulation time 508048325 ps
CPU time 9.68 seconds
Started Jun 09 01:32:05 PM PDT 24
Finished Jun 09 01:32:15 PM PDT 24
Peak memory 226104 kb
Host smart-210dfe20-450b-483d-a599-95c507c2f12c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209585100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.209585100
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.2784677793
Short name T782
Test name
Test status
Simulation time 2080840293 ps
CPU time 18.72 seconds
Started Jun 09 01:32:04 PM PDT 24
Finished Jun 09 01:32:23 PM PDT 24
Peak memory 218260 kb
Host smart-765747c7-83cf-47fd-b293-d489e94c278b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784677793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.2784677793
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.240199895
Short name T164
Test name
Test status
Simulation time 495990181 ps
CPU time 6.86 seconds
Started Jun 09 01:32:04 PM PDT 24
Finished Jun 09 01:32:11 PM PDT 24
Peak memory 225188 kb
Host smart-19006082-9ec8-4f0b-946e-1d4936ef3703
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240199895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.240199895
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.979645776
Short name T216
Test name
Test status
Simulation time 407613513 ps
CPU time 10.9 seconds
Started Jun 09 01:32:03 PM PDT 24
Finished Jun 09 01:32:14 PM PDT 24
Peak memory 226056 kb
Host smart-14233821-7c81-4519-94cc-fab47db7d282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979645776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.979645776
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.348035816
Short name T809
Test name
Test status
Simulation time 1480257433 ps
CPU time 31.86 seconds
Started Jun 09 01:31:59 PM PDT 24
Finished Jun 09 01:32:31 PM PDT 24
Peak memory 250968 kb
Host smart-43665804-3e3d-4de0-a035-1cf0cd91b2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348035816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.348035816
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1529569855
Short name T501
Test name
Test status
Simulation time 240189461 ps
CPU time 7.55 seconds
Started Jun 09 01:32:00 PM PDT 24
Finished Jun 09 01:32:07 PM PDT 24
Peak memory 250884 kb
Host smart-b8eef1ea-8e9c-492d-99db-acf0dd5d2390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529569855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1529569855
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2588178838
Short name T842
Test name
Test status
Simulation time 71099360404 ps
CPU time 103.3 seconds
Started Jun 09 01:32:05 PM PDT 24
Finished Jun 09 01:33:49 PM PDT 24
Peak memory 268840 kb
Host smart-5854e56d-d301-48ef-bcd9-e1e7effcb4c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588178838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2588178838
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.939091493
Short name T423
Test name
Test status
Simulation time 14810410 ps
CPU time 0.87 seconds
Started Jun 09 01:31:56 PM PDT 24
Finished Jun 09 01:31:57 PM PDT 24
Peak memory 212132 kb
Host smart-cc71fe53-9450-43da-8afc-7cdc39ff0476
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939091493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct
rl_volatile_unlock_smoke.939091493
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.2139076495
Short name T275
Test name
Test status
Simulation time 64069622 ps
CPU time 1.03 seconds
Started Jun 09 01:32:11 PM PDT 24
Finished Jun 09 01:32:12 PM PDT 24
Peak memory 208968 kb
Host smart-3f60251e-1260-444b-b066-7bcdfb67dc07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139076495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2139076495
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3712426836
Short name T484
Test name
Test status
Simulation time 453344212 ps
CPU time 15.25 seconds
Started Jun 09 01:32:05 PM PDT 24
Finished Jun 09 01:32:21 PM PDT 24
Peak memory 218248 kb
Host smart-eab781e7-7c0a-4c29-89d0-70d32a6c371d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712426836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3712426836
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2687586505
Short name T30
Test name
Test status
Simulation time 2598107133 ps
CPU time 6.34 seconds
Started Jun 09 01:32:06 PM PDT 24
Finished Jun 09 01:32:12 PM PDT 24
Peak memory 217700 kb
Host smart-e26bef81-2991-4a8d-82f2-88d55c983514
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687586505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2687586505
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.235896329
Short name T222
Test name
Test status
Simulation time 30526817 ps
CPU time 1.46 seconds
Started Jun 09 01:32:04 PM PDT 24
Finished Jun 09 01:32:05 PM PDT 24
Peak memory 218224 kb
Host smart-8f74a2ca-9d23-4836-bcca-12e8556c728c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235896329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.235896329
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.2007367246
Short name T651
Test name
Test status
Simulation time 679461188 ps
CPU time 19.12 seconds
Started Jun 09 01:32:02 PM PDT 24
Finished Jun 09 01:32:21 PM PDT 24
Peak memory 218936 kb
Host smart-0bd3c2ff-3932-4a0b-af10-c671439d5c65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007367246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.2007367246
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1010614006
Short name T758
Test name
Test status
Simulation time 926555602 ps
CPU time 9.98 seconds
Started Jun 09 01:32:09 PM PDT 24
Finished Jun 09 01:32:19 PM PDT 24
Peak memory 226080 kb
Host smart-78ec3357-6f97-447f-bebb-f0532fea7b95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010614006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.1010614006
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3272877206
Short name T320
Test name
Test status
Simulation time 904909165 ps
CPU time 8.88 seconds
Started Jun 09 01:32:06 PM PDT 24
Finished Jun 09 01:32:15 PM PDT 24
Peak memory 218304 kb
Host smart-334a1bf0-0714-425e-96e9-2cc3d3746e2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272877206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
3272877206
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.928449022
Short name T377
Test name
Test status
Simulation time 1182865658 ps
CPU time 10.93 seconds
Started Jun 09 01:32:10 PM PDT 24
Finished Jun 09 01:32:21 PM PDT 24
Peak memory 218312 kb
Host smart-e2993e96-1b47-4917-93c2-607b008b0208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928449022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.928449022
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.2824108533
Short name T68
Test name
Test status
Simulation time 118591137 ps
CPU time 3.12 seconds
Started Jun 09 01:32:03 PM PDT 24
Finished Jun 09 01:32:06 PM PDT 24
Peak memory 217764 kb
Host smart-c593ed88-c2c8-4520-b8a0-a6cdf5bd2a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824108533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2824108533
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.1148313564
Short name T287
Test name
Test status
Simulation time 2444548682 ps
CPU time 17.72 seconds
Started Jun 09 01:32:10 PM PDT 24
Finished Jun 09 01:32:28 PM PDT 24
Peak memory 250968 kb
Host smart-f20940ff-9484-4053-a982-94c6828652ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148313564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1148313564
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.1341853701
Short name T325
Test name
Test status
Simulation time 106796438 ps
CPU time 8.09 seconds
Started Jun 09 01:32:05 PM PDT 24
Finished Jun 09 01:32:13 PM PDT 24
Peak memory 250904 kb
Host smart-c9e2a466-e98a-45df-ae7a-d776bd05375e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341853701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.1341853701
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.4258276565
Short name T186
Test name
Test status
Simulation time 11357578554 ps
CPU time 81.05 seconds
Started Jun 09 01:32:09 PM PDT 24
Finished Jun 09 01:33:31 PM PDT 24
Peak memory 252708 kb
Host smart-ea424feb-9bc6-4af7-9786-4d457d768c06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258276565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.4258276565
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.1824980702
Short name T155
Test name
Test status
Simulation time 47032871436 ps
CPU time 2588.7 seconds
Started Jun 09 01:32:08 PM PDT 24
Finished Jun 09 02:15:17 PM PDT 24
Peak memory 1502944 kb
Host smart-5de41fd7-d00a-4802-b121-9de50015f8cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1824980702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.1824980702
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2971771849
Short name T864
Test name
Test status
Simulation time 39129160 ps
CPU time 0.95 seconds
Started Jun 09 01:32:04 PM PDT 24
Finished Jun 09 01:32:05 PM PDT 24
Peak memory 212008 kb
Host smart-581dd7f4-e7a1-4d2e-b969-374eb33bc322
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971771849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.2971771849
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.2546695505
Short name T443
Test name
Test status
Simulation time 30611887 ps
CPU time 1.07 seconds
Started Jun 09 01:32:12 PM PDT 24
Finished Jun 09 01:32:13 PM PDT 24
Peak memory 208984 kb
Host smart-229f92a6-436d-447e-8966-5f1d8efae7cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546695505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.2546695505
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2429062910
Short name T409
Test name
Test status
Simulation time 295462631 ps
CPU time 10.4 seconds
Started Jun 09 01:32:11 PM PDT 24
Finished Jun 09 01:32:22 PM PDT 24
Peak memory 218228 kb
Host smart-aea528f1-6f9e-480a-b1d4-b81bba006d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429062910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2429062910
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.1971372307
Short name T641
Test name
Test status
Simulation time 864964377 ps
CPU time 2.93 seconds
Started Jun 09 01:32:13 PM PDT 24
Finished Jun 09 01:32:16 PM PDT 24
Peak memory 217308 kb
Host smart-a4257cb9-4038-4f48-996b-772a202cddf8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971372307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.1971372307
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.2304314392
Short name T736
Test name
Test status
Simulation time 426106899 ps
CPU time 4.61 seconds
Started Jun 09 01:32:07 PM PDT 24
Finished Jun 09 01:32:12 PM PDT 24
Peak memory 218212 kb
Host smart-212536f1-c51d-4861-8c6a-94deec596ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304314392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.2304314392
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2383952916
Short name T537
Test name
Test status
Simulation time 1507145942 ps
CPU time 12.9 seconds
Started Jun 09 01:32:13 PM PDT 24
Finished Jun 09 01:32:26 PM PDT 24
Peak memory 218356 kb
Host smart-b9fd900c-5078-485a-a417-9082fba2511c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383952916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2383952916
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1360462440
Short name T427
Test name
Test status
Simulation time 1249466742 ps
CPU time 9.04 seconds
Started Jun 09 01:32:11 PM PDT 24
Finished Jun 09 01:32:20 PM PDT 24
Peak memory 218272 kb
Host smart-f222ad94-306a-4a27-bfe4-d427ba1acf26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360462440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1360462440
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3362297152
Short name T566
Test name
Test status
Simulation time 1178336265 ps
CPU time 12.32 seconds
Started Jun 09 01:32:09 PM PDT 24
Finished Jun 09 01:32:21 PM PDT 24
Peak memory 218264 kb
Host smart-352fdf88-925b-407f-841d-0d25374cb8f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362297152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3362297152
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.1497695408
Short name T585
Test name
Test status
Simulation time 2344494672 ps
CPU time 11.34 seconds
Started Jun 09 01:32:12 PM PDT 24
Finished Jun 09 01:32:24 PM PDT 24
Peak memory 226140 kb
Host smart-5915a867-a061-4b7d-be59-dad891b18d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497695408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.1497695408
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.3264884451
Short name T406
Test name
Test status
Simulation time 56953098 ps
CPU time 3.1 seconds
Started Jun 09 01:32:10 PM PDT 24
Finished Jun 09 01:32:13 PM PDT 24
Peak memory 217756 kb
Host smart-0b3707f0-b974-43a4-a873-a9fc53898272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264884451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3264884451
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.3998735774
Short name T649
Test name
Test status
Simulation time 323161178 ps
CPU time 28.12 seconds
Started Jun 09 01:32:09 PM PDT 24
Finished Jun 09 01:32:37 PM PDT 24
Peak memory 250888 kb
Host smart-246a10eb-422c-4c57-8894-caaeb0db7725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998735774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.3998735774
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.694477311
Short name T432
Test name
Test status
Simulation time 694115675 ps
CPU time 6.28 seconds
Started Jun 09 01:32:08 PM PDT 24
Finished Jun 09 01:32:15 PM PDT 24
Peak memory 250340 kb
Host smart-06fb1ff7-c63a-4a58-84ff-1e3d6186143e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694477311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.694477311
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.2948909559
Short name T717
Test name
Test status
Simulation time 18380158349 ps
CPU time 150.55 seconds
Started Jun 09 01:32:15 PM PDT 24
Finished Jun 09 01:34:46 PM PDT 24
Peak memory 276436 kb
Host smart-514dc48e-359c-43e9-96ff-face651aacb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948909559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.2948909559
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1499083371
Short name T104
Test name
Test status
Simulation time 15832281 ps
CPU time 1.14 seconds
Started Jun 09 01:32:08 PM PDT 24
Finished Jun 09 01:32:09 PM PDT 24
Peak memory 213088 kb
Host smart-a562f07e-8e98-4337-8ab7-891b499472d1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499083371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.1499083371
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.3461507196
Short name T696
Test name
Test status
Simulation time 62923682 ps
CPU time 1.1 seconds
Started Jun 09 01:32:20 PM PDT 24
Finished Jun 09 01:32:21 PM PDT 24
Peak memory 208980 kb
Host smart-a520fd6c-1d19-4410-a463-3db818292b72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461507196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3461507196
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.117354878
Short name T238
Test name
Test status
Simulation time 593729936 ps
CPU time 25.87 seconds
Started Jun 09 01:32:16 PM PDT 24
Finished Jun 09 01:32:42 PM PDT 24
Peak memory 226088 kb
Host smart-70b73f33-04d8-4c6b-901a-be41e47f3c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117354878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.117354878
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.4135432073
Short name T506
Test name
Test status
Simulation time 77860555 ps
CPU time 1.63 seconds
Started Jun 09 01:32:13 PM PDT 24
Finished Jun 09 01:32:15 PM PDT 24
Peak memory 217092 kb
Host smart-5c670911-598a-40f3-b347-fc4d90817912
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135432073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.4135432073
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.3175301294
Short name T678
Test name
Test status
Simulation time 132873779 ps
CPU time 4.03 seconds
Started Jun 09 01:32:14 PM PDT 24
Finished Jun 09 01:32:18 PM PDT 24
Peak memory 222340 kb
Host smart-e5356d70-effc-4641-9624-33336c2c364d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175301294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.3175301294
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.2342473778
Short name T523
Test name
Test status
Simulation time 951049631 ps
CPU time 11.2 seconds
Started Jun 09 01:32:15 PM PDT 24
Finished Jun 09 01:32:27 PM PDT 24
Peak memory 218936 kb
Host smart-da07b137-0b76-4afb-b6b5-76464f9b0e39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342473778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2342473778
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1509313240
Short name T781
Test name
Test status
Simulation time 1414406229 ps
CPU time 8.39 seconds
Started Jun 09 01:32:14 PM PDT 24
Finished Jun 09 01:32:23 PM PDT 24
Peak memory 226092 kb
Host smart-76bc191f-17a5-4c31-88ab-f35d5342c543
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509313240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1509313240
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3883448980
Short name T289
Test name
Test status
Simulation time 5621990831 ps
CPU time 7.61 seconds
Started Jun 09 01:32:15 PM PDT 24
Finished Jun 09 01:32:23 PM PDT 24
Peak memory 226136 kb
Host smart-9b9646da-5c0d-4781-a057-2f0915f86054
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883448980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
3883448980
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.3554817592
Short name T178
Test name
Test status
Simulation time 256271969 ps
CPU time 10.16 seconds
Started Jun 09 01:32:12 PM PDT 24
Finished Jun 09 01:32:22 PM PDT 24
Peak memory 218296 kb
Host smart-cddeadc0-de1f-4e66-bda5-d95e2c58023b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554817592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.3554817592
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.1183328597
Short name T373
Test name
Test status
Simulation time 1036923289 ps
CPU time 2.23 seconds
Started Jun 09 01:32:14 PM PDT 24
Finished Jun 09 01:32:17 PM PDT 24
Peak memory 217760 kb
Host smart-4fd81767-990f-4d76-a025-d74dd961eb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183328597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.1183328597
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.2218623987
Short name T684
Test name
Test status
Simulation time 298247086 ps
CPU time 18.65 seconds
Started Jun 09 01:32:14 PM PDT 24
Finished Jun 09 01:32:33 PM PDT 24
Peak memory 250876 kb
Host smart-e0dbe590-487c-47c9-a225-e363b8a00f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218623987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2218623987
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.1016387963
Short name T288
Test name
Test status
Simulation time 226080709 ps
CPU time 6.69 seconds
Started Jun 09 01:32:16 PM PDT 24
Finished Jun 09 01:32:23 PM PDT 24
Peak memory 247096 kb
Host smart-a2f3f929-ec45-4007-9183-24885084deb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016387963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.1016387963
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.3658323789
Short name T84
Test name
Test status
Simulation time 1766761682 ps
CPU time 40.56 seconds
Started Jun 09 01:32:18 PM PDT 24
Finished Jun 09 01:32:58 PM PDT 24
Peak memory 248188 kb
Host smart-5ef02d27-70dc-46e1-a47f-3a18a601825b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658323789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.3658323789
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2281507961
Short name T600
Test name
Test status
Simulation time 16259893 ps
CPU time 0.95 seconds
Started Jun 09 01:32:16 PM PDT 24
Finished Jun 09 01:32:17 PM PDT 24
Peak memory 211868 kb
Host smart-4942568a-84a6-4aa8-b58d-20f8860df946
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281507961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2281507961
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.3662660519
Short name T328
Test name
Test status
Simulation time 65687291 ps
CPU time 0.94 seconds
Started Jun 09 01:32:19 PM PDT 24
Finished Jun 09 01:32:20 PM PDT 24
Peak memory 208900 kb
Host smart-7ded9273-84bd-4ef8-9efc-08ca1125e056
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662660519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.3662660519
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.491872672
Short name T835
Test name
Test status
Simulation time 397195571 ps
CPU time 11.09 seconds
Started Jun 09 01:32:19 PM PDT 24
Finished Jun 09 01:32:30 PM PDT 24
Peak memory 218228 kb
Host smart-e92c3ead-7ad7-47b1-91d4-c72c0e87987c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491872672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.491872672
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.2675331534
Short name T411
Test name
Test status
Simulation time 368110575 ps
CPU time 9.54 seconds
Started Jun 09 01:32:22 PM PDT 24
Finished Jun 09 01:32:32 PM PDT 24
Peak memory 217252 kb
Host smart-903498c8-4ab2-4a8e-9120-63b8022d87df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675331534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.2675331534
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3878726499
Short name T710
Test name
Test status
Simulation time 43607422 ps
CPU time 1.73 seconds
Started Jun 09 01:32:20 PM PDT 24
Finished Jun 09 01:32:22 PM PDT 24
Peak memory 222036 kb
Host smart-6d256e42-3d54-47c0-a9fe-3caf81441367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878726499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3878726499
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.322811351
Short name T725
Test name
Test status
Simulation time 958379209 ps
CPU time 7.89 seconds
Started Jun 09 01:32:18 PM PDT 24
Finished Jun 09 01:32:27 PM PDT 24
Peak memory 226088 kb
Host smart-a99518c9-15b8-4a51-bab5-c24b51543fa8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322811351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_di
gest.322811351
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3121706978
Short name T783
Test name
Test status
Simulation time 1292851490 ps
CPU time 11.31 seconds
Started Jun 09 01:32:21 PM PDT 24
Finished Jun 09 01:32:32 PM PDT 24
Peak memory 226072 kb
Host smart-fbe386dc-5773-47bd-b4b8-9fdc0933d8ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121706978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3121706978
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2061285744
Short name T330
Test name
Test status
Simulation time 542415048 ps
CPU time 6.81 seconds
Started Jun 09 01:32:20 PM PDT 24
Finished Jun 09 01:32:27 PM PDT 24
Peak memory 218304 kb
Host smart-ddcc1a3d-1881-4b70-9cc4-ae478001b5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061285744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2061285744
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.1782149192
Short name T586
Test name
Test status
Simulation time 179261404 ps
CPU time 1.38 seconds
Started Jun 09 01:32:19 PM PDT 24
Finished Jun 09 01:32:20 PM PDT 24
Peak memory 217764 kb
Host smart-86d32645-22ba-4ecd-a73c-6539c2cb05ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782149192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1782149192
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3982146716
Short name T808
Test name
Test status
Simulation time 744009437 ps
CPU time 18.83 seconds
Started Jun 09 01:32:20 PM PDT 24
Finished Jun 09 01:32:39 PM PDT 24
Peak memory 250912 kb
Host smart-663a8d0b-ff38-4e90-9ea8-839eef86574f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982146716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3982146716
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.2707103850
Short name T276
Test name
Test status
Simulation time 445985323 ps
CPU time 6.49 seconds
Started Jun 09 01:32:20 PM PDT 24
Finished Jun 09 01:32:26 PM PDT 24
Peak memory 250448 kb
Host smart-6bcf2503-d33b-4a61-93a5-68f80a3c28e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707103850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.2707103850
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.2157303335
Short name T732
Test name
Test status
Simulation time 35837766226 ps
CPU time 219.51 seconds
Started Jun 09 01:32:22 PM PDT 24
Finished Jun 09 01:36:02 PM PDT 24
Peak memory 272644 kb
Host smart-070f49bd-2a0e-46e7-a496-aaf91dc7747f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157303335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.2157303335
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1343647469
Short name T662
Test name
Test status
Simulation time 38768586 ps
CPU time 0.85 seconds
Started Jun 09 01:32:19 PM PDT 24
Finished Jun 09 01:32:20 PM PDT 24
Peak memory 211892 kb
Host smart-98d3ba19-e74c-4cc2-b487-cbb0baf47fa7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343647469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1343647469
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.1640464016
Short name T163
Test name
Test status
Simulation time 57704702 ps
CPU time 0.83 seconds
Started Jun 09 01:32:24 PM PDT 24
Finished Jun 09 01:32:25 PM PDT 24
Peak memory 208980 kb
Host smart-97b5fcf0-1b0c-41ab-aa2a-71fea4d6ba32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640464016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.1640464016
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.2989156924
Short name T446
Test name
Test status
Simulation time 4097367911 ps
CPU time 9.52 seconds
Started Jun 09 01:32:26 PM PDT 24
Finished Jun 09 01:32:36 PM PDT 24
Peak memory 218352 kb
Host smart-900f98ea-a5e3-4fcc-8101-6d302287bb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989156924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2989156924
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.2546064526
Short name T420
Test name
Test status
Simulation time 165380733 ps
CPU time 5.09 seconds
Started Jun 09 01:32:25 PM PDT 24
Finished Jun 09 01:32:31 PM PDT 24
Peak memory 217476 kb
Host smart-1803b55e-1f20-431d-a352-4f3f13f09a26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546064526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.2546064526
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.2952850963
Short name T675
Test name
Test status
Simulation time 67495147 ps
CPU time 1.93 seconds
Started Jun 09 01:32:20 PM PDT 24
Finished Jun 09 01:32:22 PM PDT 24
Peak memory 222176 kb
Host smart-f8a068e8-a4c0-4e12-b6a3-a49e28b8c877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952850963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.2952850963
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.1881159462
Short name T812
Test name
Test status
Simulation time 507139444 ps
CPU time 12.27 seconds
Started Jun 09 01:32:26 PM PDT 24
Finished Jun 09 01:32:38 PM PDT 24
Peak memory 218284 kb
Host smart-17da82e5-795b-4634-8a45-c7d387f8f78e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881159462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.1881159462
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2886797418
Short name T686
Test name
Test status
Simulation time 257180470 ps
CPU time 8.41 seconds
Started Jun 09 01:32:26 PM PDT 24
Finished Jun 09 01:32:35 PM PDT 24
Peak memory 226120 kb
Host smart-1fc1d64b-325a-4c65-94c8-f5ba02eca31a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886797418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2886797418
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.3832554699
Short name T457
Test name
Test status
Simulation time 932379041 ps
CPU time 9.9 seconds
Started Jun 09 01:32:25 PM PDT 24
Finished Jun 09 01:32:35 PM PDT 24
Peak memory 225624 kb
Host smart-60113095-6279-42ba-9aac-691720d9794a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832554699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
3832554699
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3435082150
Short name T509
Test name
Test status
Simulation time 523969551 ps
CPU time 28.19 seconds
Started Jun 09 01:32:19 PM PDT 24
Finished Jun 09 01:32:48 PM PDT 24
Peak memory 250968 kb
Host smart-6746f60d-8c79-4932-9e2f-f67c7bda7bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435082150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3435082150
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.2825884005
Short name T278
Test name
Test status
Simulation time 63443769 ps
CPU time 2.9 seconds
Started Jun 09 01:32:21 PM PDT 24
Finished Jun 09 01:32:24 PM PDT 24
Peak memory 218228 kb
Host smart-87a1a672-7552-45a4-99ce-24e1c4543ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825884005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.2825884005
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.156263543
Short name T41
Test name
Test status
Simulation time 56441255060 ps
CPU time 100.83 seconds
Started Jun 09 01:32:24 PM PDT 24
Finished Jun 09 01:34:05 PM PDT 24
Peak memory 264476 kb
Host smart-eaf0966c-8937-4ef2-9fee-9b824c500946
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156263543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.156263543
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.639040287
Short name T157
Test name
Test status
Simulation time 232129756685 ps
CPU time 960.29 seconds
Started Jun 09 01:32:26 PM PDT 24
Finished Jun 09 01:48:27 PM PDT 24
Peak memory 316544 kb
Host smart-a1bc2316-4d7c-4d71-a829-35b866c13ac3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=639040287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.639040287
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.136173301
Short name T833
Test name
Test status
Simulation time 18616393 ps
CPU time 0.9 seconds
Started Jun 09 01:32:20 PM PDT 24
Finished Jun 09 01:32:21 PM PDT 24
Peak memory 211928 kb
Host smart-f7c70edb-5902-422a-9925-156f40d1e4d6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136173301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ct
rl_volatile_unlock_smoke.136173301
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.97753823
Short name T452
Test name
Test status
Simulation time 14778658 ps
CPU time 1.01 seconds
Started Jun 09 01:32:28 PM PDT 24
Finished Jun 09 01:32:29 PM PDT 24
Peak memory 209008 kb
Host smart-1d7a0e84-d684-4bb2-a8c8-0fae44423a81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97753823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.97753823
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.2320167542
Short name T436
Test name
Test status
Simulation time 4624911646 ps
CPU time 25.96 seconds
Started Jun 09 01:32:25 PM PDT 24
Finished Jun 09 01:32:52 PM PDT 24
Peak memory 219192 kb
Host smart-de1b9afe-6229-4213-982b-e9a1f818760b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320167542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.2320167542
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1970508439
Short name T657
Test name
Test status
Simulation time 1492139056 ps
CPU time 5.18 seconds
Started Jun 09 01:32:25 PM PDT 24
Finished Jun 09 01:32:31 PM PDT 24
Peak memory 217428 kb
Host smart-bf98b029-b829-4882-86ab-427b8bc85068
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970508439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1970508439
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.523918939
Short name T475
Test name
Test status
Simulation time 61236095 ps
CPU time 1.95 seconds
Started Jun 09 01:32:28 PM PDT 24
Finished Jun 09 01:32:30 PM PDT 24
Peak memory 222200 kb
Host smart-7f73daf9-81a0-4a5c-a285-befd144c8e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523918939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.523918939
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.3026751225
Short name T549
Test name
Test status
Simulation time 253654643 ps
CPU time 11.68 seconds
Started Jun 09 01:32:27 PM PDT 24
Finished Jun 09 01:32:39 PM PDT 24
Peak memory 219108 kb
Host smart-02a63f44-cc5d-4238-9c29-d5e012691de6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026751225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3026751225
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.357317183
Short name T766
Test name
Test status
Simulation time 2500795789 ps
CPU time 8.82 seconds
Started Jun 09 01:32:32 PM PDT 24
Finished Jun 09 01:32:41 PM PDT 24
Peak memory 218336 kb
Host smart-b11d75a0-9a03-44e6-9ef8-8101dd4173f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357317183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_di
gest.357317183
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.71191584
Short name T231
Test name
Test status
Simulation time 394149622 ps
CPU time 10.01 seconds
Started Jun 09 01:32:33 PM PDT 24
Finished Jun 09 01:32:43 PM PDT 24
Peak memory 225408 kb
Host smart-d3958152-a391-473a-924a-2c7704a28845
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71191584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.71191584
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2703764094
Short name T401
Test name
Test status
Simulation time 601970612 ps
CPU time 12.27 seconds
Started Jun 09 01:32:26 PM PDT 24
Finished Jun 09 01:32:39 PM PDT 24
Peak memory 225900 kb
Host smart-36ab991b-28cd-458a-b643-80bf11b29d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703764094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2703764094
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2047185155
Short name T742
Test name
Test status
Simulation time 209412960 ps
CPU time 2.8 seconds
Started Jun 09 01:32:25 PM PDT 24
Finished Jun 09 01:32:28 PM PDT 24
Peak memory 214328 kb
Host smart-4ad6b84d-18bc-4714-aa91-5d79e2472044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047185155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2047185155
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.3631044973
Short name T256
Test name
Test status
Simulation time 986545710 ps
CPU time 25.47 seconds
Started Jun 09 01:32:26 PM PDT 24
Finished Jun 09 01:32:52 PM PDT 24
Peak memory 250888 kb
Host smart-eaba0510-c9bb-419b-9386-b0f08c2d10ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631044973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3631044973
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.1564221997
Short name T152
Test name
Test status
Simulation time 284605981 ps
CPU time 4.65 seconds
Started Jun 09 01:32:26 PM PDT 24
Finished Jun 09 01:32:31 PM PDT 24
Peak memory 222876 kb
Host smart-299935eb-1569-4f69-b09e-857669709b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564221997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.1564221997
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.1398223303
Short name T599
Test name
Test status
Simulation time 5640009516 ps
CPU time 171.2 seconds
Started Jun 09 01:32:30 PM PDT 24
Finished Jun 09 01:35:22 PM PDT 24
Peak memory 226140 kb
Host smart-d6778f2a-3b5b-48da-8829-22fb5d3f43ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398223303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.1398223303
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3758066091
Short name T745
Test name
Test status
Simulation time 41656679 ps
CPU time 1 seconds
Started Jun 09 01:32:26 PM PDT 24
Finished Jun 09 01:32:27 PM PDT 24
Peak memory 212956 kb
Host smart-7ea58a22-0279-41a6-8219-6a27d9e3b6d6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758066091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3758066091
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.695433959
Short name T261
Test name
Test status
Simulation time 20128397 ps
CPU time 0.93 seconds
Started Jun 09 01:32:32 PM PDT 24
Finished Jun 09 01:32:34 PM PDT 24
Peak memory 209180 kb
Host smart-896cc308-758b-40c1-ad7c-3c63349e34ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695433959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.695433959
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.1369381939
Short name T92
Test name
Test status
Simulation time 2388549178 ps
CPU time 12.89 seconds
Started Jun 09 01:32:31 PM PDT 24
Finished Jun 09 01:32:45 PM PDT 24
Peak memory 218352 kb
Host smart-6aa96038-6a6d-4870-9414-fa489834cc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369381939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1369381939
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.3023697133
Short name T836
Test name
Test status
Simulation time 1346409901 ps
CPU time 7.92 seconds
Started Jun 09 01:32:32 PM PDT 24
Finished Jun 09 01:32:40 PM PDT 24
Peak memory 217504 kb
Host smart-c87bcdaa-666c-4796-8e1f-251b68b212e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023697133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.3023697133
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.2649227770
Short name T372
Test name
Test status
Simulation time 157400493 ps
CPU time 2.56 seconds
Started Jun 09 01:32:31 PM PDT 24
Finished Jun 09 01:32:34 PM PDT 24
Peak memory 222096 kb
Host smart-b2408b97-7a64-4430-83d9-faa3944df32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649227770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.2649227770
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.2119097519
Short name T467
Test name
Test status
Simulation time 618366143 ps
CPU time 12.05 seconds
Started Jun 09 01:32:34 PM PDT 24
Finished Jun 09 01:32:47 PM PDT 24
Peak memory 218948 kb
Host smart-3aa54dc1-50bd-4eb5-9133-be8f324f888c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119097519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.2119097519
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2953684269
Short name T340
Test name
Test status
Simulation time 465962089 ps
CPU time 11.98 seconds
Started Jun 09 01:32:36 PM PDT 24
Finished Jun 09 01:32:48 PM PDT 24
Peak memory 218260 kb
Host smart-1148c4ab-01fb-48a2-a9fb-7bb667ea151d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953684269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.2953684269
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.286584322
Short name T177
Test name
Test status
Simulation time 490245800 ps
CPU time 8.48 seconds
Started Jun 09 01:32:35 PM PDT 24
Finished Jun 09 01:32:43 PM PDT 24
Peak memory 226080 kb
Host smart-adc0d5b7-da19-48c2-a042-1c3febf9945d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286584322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.286584322
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1526342064
Short name T593
Test name
Test status
Simulation time 711832844 ps
CPU time 10.56 seconds
Started Jun 09 01:32:30 PM PDT 24
Finished Jun 09 01:32:41 PM PDT 24
Peak memory 226104 kb
Host smart-62b4760a-a30b-4275-a8d4-712e36a75797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526342064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1526342064
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.667339716
Short name T371
Test name
Test status
Simulation time 60737773 ps
CPU time 2.49 seconds
Started Jun 09 01:32:31 PM PDT 24
Finished Jun 09 01:32:34 PM PDT 24
Peak memory 214760 kb
Host smart-6251847d-a4ee-49e5-a0fc-b4a0335acde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667339716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.667339716
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.1341740693
Short name T693
Test name
Test status
Simulation time 862530429 ps
CPU time 17.64 seconds
Started Jun 09 01:32:30 PM PDT 24
Finished Jun 09 01:32:48 PM PDT 24
Peak memory 250908 kb
Host smart-4c4f1715-45a3-40c0-92f6-88fc98609e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341740693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1341740693
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.3197583997
Short name T628
Test name
Test status
Simulation time 1086459186 ps
CPU time 3.59 seconds
Started Jun 09 01:32:29 PM PDT 24
Finished Jun 09 01:32:33 PM PDT 24
Peak memory 222416 kb
Host smart-90cf7f9f-b448-49af-a484-b9252e837560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197583997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3197583997
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.724644045
Short name T338
Test name
Test status
Simulation time 19320527421 ps
CPU time 153.5 seconds
Started Jun 09 01:32:35 PM PDT 24
Finished Jun 09 01:35:09 PM PDT 24
Peak memory 239020 kb
Host smart-3c1a47a6-6fc8-4425-8798-ecb85570142e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724644045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.724644045
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.621669367
Short name T329
Test name
Test status
Simulation time 14117916 ps
CPU time 1.07 seconds
Started Jun 09 01:32:28 PM PDT 24
Finished Jun 09 01:32:30 PM PDT 24
Peak memory 211984 kb
Host smart-285f668a-6218-46f6-ac66-bd82ae507f87
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621669367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct
rl_volatile_unlock_smoke.621669367
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1624884624
Short name T503
Test name
Test status
Simulation time 30675396 ps
CPU time 0.96 seconds
Started Jun 09 01:29:37 PM PDT 24
Finished Jun 09 01:29:38 PM PDT 24
Peak memory 208912 kb
Host smart-f91be5aa-7e12-49d7-b58f-c4c65c3fbd48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624884624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1624884624
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3596371237
Short name T572
Test name
Test status
Simulation time 43014617 ps
CPU time 0.93 seconds
Started Jun 09 01:29:33 PM PDT 24
Finished Jun 09 01:29:34 PM PDT 24
Peak memory 208976 kb
Host smart-9c28c0b7-0ec5-4019-98ef-1f04652cd8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596371237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3596371237
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2679233065
Short name T746
Test name
Test status
Simulation time 215259280 ps
CPU time 10.29 seconds
Started Jun 09 01:29:28 PM PDT 24
Finished Jun 09 01:29:38 PM PDT 24
Peak memory 218220 kb
Host smart-631b8030-6fa0-4148-a64c-37b9074829f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679233065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2679233065
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3277519498
Short name T447
Test name
Test status
Simulation time 404008206 ps
CPU time 4.84 seconds
Started Jun 09 01:29:35 PM PDT 24
Finished Jun 09 01:29:40 PM PDT 24
Peak memory 217248 kb
Host smart-2d770d0a-06ce-48fb-80f0-fc3cb822ad35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277519498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3277519498
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.2250607688
Short name T35
Test name
Test status
Simulation time 12865437724 ps
CPU time 72.13 seconds
Started Jun 09 01:29:32 PM PDT 24
Finished Jun 09 01:30:44 PM PDT 24
Peak memory 226060 kb
Host smart-7a26073f-99e8-4859-9c4a-6ce31854ef07
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250607688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.2250607688
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.488416841
Short name T753
Test name
Test status
Simulation time 194275434 ps
CPU time 1.9 seconds
Started Jun 09 01:29:32 PM PDT 24
Finished Jun 09 01:29:34 PM PDT 24
Peak memory 217808 kb
Host smart-b52030fd-7470-484f-a337-b2ad1cd86d23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488416841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.488416841
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1789259828
Short name T180
Test name
Test status
Simulation time 137729342 ps
CPU time 5.24 seconds
Started Jun 09 01:29:31 PM PDT 24
Finished Jun 09 01:29:36 PM PDT 24
Peak memory 221960 kb
Host smart-8e67fc48-e1fe-4892-8755-51c88dbc8611
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789259828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1789259828
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3255588287
Short name T811
Test name
Test status
Simulation time 941468942 ps
CPU time 11.78 seconds
Started Jun 09 01:29:35 PM PDT 24
Finished Jun 09 01:29:47 PM PDT 24
Peak memory 217868 kb
Host smart-ad86960a-beb2-4f76-ad05-5802bc99b0b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255588287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.3255588287
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2949472692
Short name T402
Test name
Test status
Simulation time 2005795912 ps
CPU time 9.28 seconds
Started Jun 09 01:29:32 PM PDT 24
Finished Jun 09 01:29:41 PM PDT 24
Peak memory 217704 kb
Host smart-623cdf88-2d5e-46b4-86db-a7a125e22422
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949472692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2949472692
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2443490148
Short name T315
Test name
Test status
Simulation time 6495303592 ps
CPU time 46.42 seconds
Started Jun 09 01:29:33 PM PDT 24
Finished Jun 09 01:30:20 PM PDT 24
Peak memory 250888 kb
Host smart-abb0be52-0a36-4dda-bbe4-ee0e918ca139
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443490148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2443490148
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.2410777542
Short name T476
Test name
Test status
Simulation time 12403455038 ps
CPU time 34.5 seconds
Started Jun 09 01:29:31 PM PDT 24
Finished Jun 09 01:30:06 PM PDT 24
Peak memory 226320 kb
Host smart-e3fef528-b647-4a75-a00e-992e563ab454
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410777542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.2410777542
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1696023096
Short name T583
Test name
Test status
Simulation time 25006014 ps
CPU time 1.95 seconds
Started Jun 09 01:29:28 PM PDT 24
Finished Jun 09 01:29:30 PM PDT 24
Peak memory 218224 kb
Host smart-8a07c296-3a22-4873-bd1a-d8590f2aef67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696023096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1696023096
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.3313745776
Short name T271
Test name
Test status
Simulation time 505240813 ps
CPU time 9.47 seconds
Started Jun 09 01:29:33 PM PDT 24
Finished Jun 09 01:29:43 PM PDT 24
Peak memory 217728 kb
Host smart-5826e8bb-902a-4e1f-a4dd-e1bfbf4db10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313745776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3313745776
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.278168469
Short name T101
Test name
Test status
Simulation time 119869409 ps
CPU time 25.2 seconds
Started Jun 09 01:29:31 PM PDT 24
Finished Jun 09 01:29:57 PM PDT 24
Peak memory 284264 kb
Host smart-78bdaf88-2b8d-440d-9501-a51e49e373a7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278168469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.278168469
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.2952939885
Short name T771
Test name
Test status
Simulation time 583692300 ps
CPU time 11.97 seconds
Started Jun 09 01:29:32 PM PDT 24
Finished Jun 09 01:29:44 PM PDT 24
Peak memory 218940 kb
Host smart-57c9ecfc-ed48-446f-951d-9a43d5852cca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952939885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.2952939885
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.1074142100
Short name T317
Test name
Test status
Simulation time 412998047 ps
CPU time 15.18 seconds
Started Jun 09 01:29:33 PM PDT 24
Finished Jun 09 01:29:48 PM PDT 24
Peak memory 226104 kb
Host smart-e2fa64ea-b96c-479b-8d2d-6810ebdd5cd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074142100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.1074142100
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.375942881
Short name T345
Test name
Test status
Simulation time 356162751 ps
CPU time 10.11 seconds
Started Jun 09 01:29:33 PM PDT 24
Finished Jun 09 01:29:43 PM PDT 24
Peak memory 218260 kb
Host smart-d6149396-d8d5-4256-9beb-af30452b8442
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375942881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.375942881
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.2879416359
Short name T215
Test name
Test status
Simulation time 739000303 ps
CPU time 5.75 seconds
Started Jun 09 01:29:27 PM PDT 24
Finished Jun 09 01:29:33 PM PDT 24
Peak memory 224980 kb
Host smart-b6670fba-fe1a-4404-bac7-75c16159ad52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879416359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.2879416359
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.3664001305
Short name T635
Test name
Test status
Simulation time 488253607 ps
CPU time 5.67 seconds
Started Jun 09 01:29:23 PM PDT 24
Finished Jun 09 01:29:29 PM PDT 24
Peak memory 217792 kb
Host smart-72bd6887-be0b-4b9a-80bd-cd330b0f6edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664001305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3664001305
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.874910814
Short name T244
Test name
Test status
Simulation time 291339200 ps
CPU time 26.61 seconds
Started Jun 09 01:29:26 PM PDT 24
Finished Jun 09 01:29:53 PM PDT 24
Peak memory 250980 kb
Host smart-f7e47693-3257-46fb-809f-6833a8c04e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874910814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.874910814
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1926427505
Short name T364
Test name
Test status
Simulation time 88015540 ps
CPU time 3.67 seconds
Started Jun 09 01:29:28 PM PDT 24
Finished Jun 09 01:29:32 PM PDT 24
Peak memory 222956 kb
Host smart-72dc86dd-0611-4bac-93d2-4d65383cf560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926427505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1926427505
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1336593449
Short name T655
Test name
Test status
Simulation time 14688855 ps
CPU time 1.09 seconds
Started Jun 09 01:29:27 PM PDT 24
Finished Jun 09 01:29:28 PM PDT 24
Peak memory 211824 kb
Host smart-a61a1c57-f039-4f36-98df-9ff69951a533
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336593449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1336593449
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.936698513
Short name T540
Test name
Test status
Simulation time 17101584 ps
CPU time 1.05 seconds
Started Jun 09 01:32:40 PM PDT 24
Finished Jun 09 01:32:41 PM PDT 24
Peak memory 208964 kb
Host smart-ca917559-ad73-411e-9fc3-fe0d137ea231
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936698513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.936698513
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.1064024918
Short name T729
Test name
Test status
Simulation time 398808441 ps
CPU time 9.69 seconds
Started Jun 09 01:32:40 PM PDT 24
Finished Jun 09 01:32:50 PM PDT 24
Peak memory 218220 kb
Host smart-9a7e94b0-f618-4d24-9600-35cc3f26ca51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064024918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1064024918
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.2523368447
Short name T167
Test name
Test status
Simulation time 60878649 ps
CPU time 1.14 seconds
Started Jun 09 01:32:41 PM PDT 24
Finished Jun 09 01:32:43 PM PDT 24
Peak memory 217068 kb
Host smart-a3f59e64-ca9f-4fe2-8c5b-d8f5f963e559
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523368447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.2523368447
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3160119764
Short name T227
Test name
Test status
Simulation time 228663259 ps
CPU time 4 seconds
Started Jun 09 01:32:41 PM PDT 24
Finished Jun 09 01:32:46 PM PDT 24
Peak memory 222372 kb
Host smart-96d24ed1-9823-4aad-8f8e-8c36624c3a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160119764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3160119764
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.767107272
Short name T466
Test name
Test status
Simulation time 707262830 ps
CPU time 7.31 seconds
Started Jun 09 01:32:41 PM PDT 24
Finished Jun 09 01:32:48 PM PDT 24
Peak memory 226084 kb
Host smart-6ec762be-6a0b-4cc8-a604-d720a2884c7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767107272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.767107272
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.186714126
Short name T820
Test name
Test status
Simulation time 640743071 ps
CPU time 14.54 seconds
Started Jun 09 01:32:41 PM PDT 24
Finished Jun 09 01:32:56 PM PDT 24
Peak memory 226072 kb
Host smart-dea1ea2a-5a8d-4aa3-bfe5-c2fedb13781e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186714126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_di
gest.186714126
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1568332891
Short name T247
Test name
Test status
Simulation time 521922229 ps
CPU time 11.89 seconds
Started Jun 09 01:32:39 PM PDT 24
Finished Jun 09 01:32:51 PM PDT 24
Peak memory 218284 kb
Host smart-6c8dffab-6351-48d6-8c4c-00c6b8bb2ea4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568332891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1568332891
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.3730018763
Short name T300
Test name
Test status
Simulation time 1107231455 ps
CPU time 11.15 seconds
Started Jun 09 01:32:44 PM PDT 24
Finished Jun 09 01:32:55 PM PDT 24
Peak memory 226080 kb
Host smart-07f5e59b-a82a-4532-a8a3-f62fa77968d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730018763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3730018763
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.3515119844
Short name T267
Test name
Test status
Simulation time 52993635 ps
CPU time 1.35 seconds
Started Jun 09 01:32:36 PM PDT 24
Finished Jun 09 01:32:37 PM PDT 24
Peak memory 213876 kb
Host smart-b4fc8b3f-0cff-4b8a-97ba-0565081d5fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515119844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3515119844
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.3389440840
Short name T233
Test name
Test status
Simulation time 234932756 ps
CPU time 31.57 seconds
Started Jun 09 01:32:40 PM PDT 24
Finished Jun 09 01:33:12 PM PDT 24
Peak memory 250924 kb
Host smart-9b421ddd-dfd3-4c97-a542-8da95cdb809a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389440840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3389440840
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.2846232420
Short name T692
Test name
Test status
Simulation time 69679972 ps
CPU time 5.98 seconds
Started Jun 09 01:32:40 PM PDT 24
Finished Jun 09 01:32:47 PM PDT 24
Peak memory 247044 kb
Host smart-4076c581-510a-4983-97cc-41646daf9a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846232420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2846232420
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.2530687802
Short name T410
Test name
Test status
Simulation time 8812325260 ps
CPU time 145.54 seconds
Started Jun 09 01:32:42 PM PDT 24
Finished Jun 09 01:35:07 PM PDT 24
Peak memory 282760 kb
Host smart-697a6081-bcc8-4d9f-a687-37937b4537e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530687802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.2530687802
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.4244820398
Short name T425
Test name
Test status
Simulation time 30910999 ps
CPU time 0.9 seconds
Started Jun 09 01:32:35 PM PDT 24
Finished Jun 09 01:32:36 PM PDT 24
Peak memory 211956 kb
Host smart-aa258f0a-820d-417a-96da-a97ab1ac51f3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244820398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.4244820398
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.4047559340
Short name T88
Test name
Test status
Simulation time 12595454 ps
CPU time 0.96 seconds
Started Jun 09 01:32:46 PM PDT 24
Finished Jun 09 01:32:47 PM PDT 24
Peak memory 208964 kb
Host smart-7b6e9b2b-0a76-4b5e-bfd9-1615e0f13143
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047559340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.4047559340
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1628656281
Short name T380
Test name
Test status
Simulation time 365828474 ps
CPU time 16.36 seconds
Started Jun 09 01:32:44 PM PDT 24
Finished Jun 09 01:33:00 PM PDT 24
Peak memory 218232 kb
Host smart-caf0f031-6393-4ebc-bc35-2fcea2c47d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628656281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1628656281
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.1336041724
Short name T8
Test name
Test status
Simulation time 581684318 ps
CPU time 4.51 seconds
Started Jun 09 01:32:44 PM PDT 24
Finished Jun 09 01:32:49 PM PDT 24
Peak memory 217124 kb
Host smart-966bae0b-4b82-4dd6-b1f6-c08c9efee241
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336041724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.1336041724
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.878512738
Short name T705
Test name
Test status
Simulation time 164687524 ps
CPU time 3.62 seconds
Started Jun 09 01:32:38 PM PDT 24
Finished Jun 09 01:32:42 PM PDT 24
Peak memory 222760 kb
Host smart-c26dda94-52aa-4e25-8b91-081e2c53d23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878512738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.878512738
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.3659225630
Short name T363
Test name
Test status
Simulation time 2108230912 ps
CPU time 22.3 seconds
Started Jun 09 01:32:44 PM PDT 24
Finished Jun 09 01:33:06 PM PDT 24
Peak memory 219948 kb
Host smart-c41652bb-fa03-4757-a24e-aa917754cd25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659225630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.3659225630
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.335289211
Short name T451
Test name
Test status
Simulation time 1118322914 ps
CPU time 7.74 seconds
Started Jun 09 01:32:48 PM PDT 24
Finished Jun 09 01:32:56 PM PDT 24
Peak memory 218220 kb
Host smart-b16f21a1-eada-433b-bc62-a2f4098ec16e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335289211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_di
gest.335289211
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2790104952
Short name T557
Test name
Test status
Simulation time 396154149 ps
CPU time 14.37 seconds
Started Jun 09 01:32:45 PM PDT 24
Finished Jun 09 01:33:00 PM PDT 24
Peak memory 218276 kb
Host smart-90f89096-d0d8-4e21-a29b-87aa95c3cf46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790104952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
2790104952
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.2913810687
Short name T799
Test name
Test status
Simulation time 1301396816 ps
CPU time 8.87 seconds
Started Jun 09 01:32:44 PM PDT 24
Finished Jun 09 01:32:53 PM PDT 24
Peak memory 218320 kb
Host smart-536cbb8b-60ff-45a0-ab9e-3659ec36e329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913810687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.2913810687
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.4243679876
Short name T426
Test name
Test status
Simulation time 27419942 ps
CPU time 1.52 seconds
Started Jun 09 01:32:43 PM PDT 24
Finished Jun 09 01:32:44 PM PDT 24
Peak memory 213964 kb
Host smart-5940775a-3675-4b26-9477-b0a5d8be94ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243679876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.4243679876
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.4040404760
Short name T632
Test name
Test status
Simulation time 243210302 ps
CPU time 17.51 seconds
Started Jun 09 01:32:41 PM PDT 24
Finished Jun 09 01:32:58 PM PDT 24
Peak memory 250924 kb
Host smart-f5c737b7-8f49-447b-a5cd-cc0c56577b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040404760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.4040404760
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.2934015127
Short name T347
Test name
Test status
Simulation time 132229903 ps
CPU time 2.7 seconds
Started Jun 09 01:32:41 PM PDT 24
Finished Jun 09 01:32:44 PM PDT 24
Peak memory 226300 kb
Host smart-1c3c816a-0b4c-4d8d-b150-126163a04a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934015127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.2934015127
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3753129711
Short name T71
Test name
Test status
Simulation time 4392306108 ps
CPU time 191.4 seconds
Started Jun 09 01:32:46 PM PDT 24
Finished Jun 09 01:35:58 PM PDT 24
Peak memory 332860 kb
Host smart-4e4d6d4f-655d-4c9f-8a41-bd9af4dd7788
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753129711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3753129711
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.402224409
Short name T454
Test name
Test status
Simulation time 78592526 ps
CPU time 1 seconds
Started Jun 09 01:32:40 PM PDT 24
Finished Jun 09 01:32:42 PM PDT 24
Peak memory 212984 kb
Host smart-6454e53d-32ab-40b0-993b-07397cc69748
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402224409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ct
rl_volatile_unlock_smoke.402224409
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1611342901
Short name T376
Test name
Test status
Simulation time 19520015 ps
CPU time 0.89 seconds
Started Jun 09 01:32:52 PM PDT 24
Finished Jun 09 01:32:53 PM PDT 24
Peak memory 208892 kb
Host smart-4f231ab0-fdbf-4699-8cd9-47d3b9ed6b14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611342901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1611342901
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.1614730792
Short name T389
Test name
Test status
Simulation time 394747762 ps
CPU time 15.81 seconds
Started Jun 09 01:32:52 PM PDT 24
Finished Jun 09 01:33:08 PM PDT 24
Peak memory 218228 kb
Host smart-0331e736-f54a-499a-b9df-f5b30bf4acef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614730792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.1614730792
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.774534561
Short name T564
Test name
Test status
Simulation time 781017532 ps
CPU time 5.81 seconds
Started Jun 09 01:32:52 PM PDT 24
Finished Jun 09 01:32:58 PM PDT 24
Peak memory 217164 kb
Host smart-a8371f8c-5d4f-4786-af60-cb3afdfb0512
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774534561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.774534561
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.2755202539
Short name T224
Test name
Test status
Simulation time 59650947 ps
CPU time 2.65 seconds
Started Jun 09 01:32:51 PM PDT 24
Finished Jun 09 01:32:54 PM PDT 24
Peak memory 218264 kb
Host smart-c69cca7d-856c-448a-929d-a6321e5c9bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755202539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.2755202539
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.2535566680
Short name T712
Test name
Test status
Simulation time 2088292482 ps
CPU time 15.26 seconds
Started Jun 09 01:32:50 PM PDT 24
Finished Jun 09 01:33:06 PM PDT 24
Peak memory 218292 kb
Host smart-b28ffedd-e769-4540-a0a5-f5fd64b96c0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535566680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.2535566680
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.1452455445
Short name T605
Test name
Test status
Simulation time 1904530709 ps
CPU time 14.37 seconds
Started Jun 09 01:32:54 PM PDT 24
Finished Jun 09 01:33:08 PM PDT 24
Peak memory 218268 kb
Host smart-d47a9455-5ed1-4be2-bbbe-8ccc84b6cf2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452455445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.1452455445
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1578304747
Short name T20
Test name
Test status
Simulation time 278414089 ps
CPU time 8.17 seconds
Started Jun 09 01:32:53 PM PDT 24
Finished Jun 09 01:33:01 PM PDT 24
Peak memory 218264 kb
Host smart-0a26fcd8-0d32-4bfc-83b7-ea73f2927e9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578304747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1578304747
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3013590792
Short name T750
Test name
Test status
Simulation time 1192250477 ps
CPU time 11.65 seconds
Started Jun 09 01:32:52 PM PDT 24
Finished Jun 09 01:33:04 PM PDT 24
Peak memory 226068 kb
Host smart-9d1949d1-551d-4aaf-8c0f-105df8565f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013590792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3013590792
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.1349986071
Short name T469
Test name
Test status
Simulation time 336904671 ps
CPU time 4.12 seconds
Started Jun 09 01:32:46 PM PDT 24
Finished Jun 09 01:32:50 PM PDT 24
Peak memory 217840 kb
Host smart-7a973fb0-09d2-4217-baca-5dd94b3c7741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349986071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.1349986071
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3371217410
Short name T172
Test name
Test status
Simulation time 271306708 ps
CPU time 31.36 seconds
Started Jun 09 01:32:45 PM PDT 24
Finished Jun 09 01:33:16 PM PDT 24
Peak memory 250928 kb
Host smart-7301a7b3-f72e-49b9-9c13-146f8f9b06e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371217410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3371217410
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.3408509422
Short name T554
Test name
Test status
Simulation time 55645746 ps
CPU time 5.7 seconds
Started Jun 09 01:32:47 PM PDT 24
Finished Jun 09 01:32:53 PM PDT 24
Peak memory 246660 kb
Host smart-798b7e45-08d8-43e4-bb73-6fc8e7a01db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408509422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3408509422
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.2372029916
Short name T590
Test name
Test status
Simulation time 14782449832 ps
CPU time 260.01 seconds
Started Jun 09 01:32:50 PM PDT 24
Finished Jun 09 01:37:10 PM PDT 24
Peak memory 249228 kb
Host smart-ad23fb9e-260c-44c1-bf6b-7f242f0911f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372029916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.2372029916
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3429751017
Short name T181
Test name
Test status
Simulation time 62484830 ps
CPU time 1 seconds
Started Jun 09 01:32:43 PM PDT 24
Finished Jun 09 01:32:45 PM PDT 24
Peak memory 211912 kb
Host smart-82cdf0cf-2d76-499f-9336-02c490a5faf5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429751017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.3429751017
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1308528530
Short name T630
Test name
Test status
Simulation time 94525368 ps
CPU time 1.07 seconds
Started Jun 09 01:32:55 PM PDT 24
Finished Jun 09 01:32:56 PM PDT 24
Peak memory 209096 kb
Host smart-ef29fa90-d8fd-4c47-84e5-0a0709bdc506
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308528530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1308528530
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.474187284
Short name T397
Test name
Test status
Simulation time 1636665084 ps
CPU time 12.55 seconds
Started Jun 09 01:32:51 PM PDT 24
Finished Jun 09 01:33:04 PM PDT 24
Peak memory 218224 kb
Host smart-8354eede-5944-4c31-9ddc-eca1687ed238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474187284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.474187284
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.2505617883
Short name T673
Test name
Test status
Simulation time 1493928302 ps
CPU time 8.67 seconds
Started Jun 09 01:32:50 PM PDT 24
Finished Jun 09 01:32:59 PM PDT 24
Peak memory 217416 kb
Host smart-e89056b6-a8ef-460c-a02f-4f67778b628d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505617883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.2505617883
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.234373835
Short name T681
Test name
Test status
Simulation time 60134884 ps
CPU time 1.51 seconds
Started Jun 09 01:32:51 PM PDT 24
Finished Jun 09 01:32:53 PM PDT 24
Peak memory 222060 kb
Host smart-dd9f54a9-6e26-41d9-8f8b-c8c0fdc2f3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234373835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.234373835
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1052591017
Short name T676
Test name
Test status
Simulation time 502670296 ps
CPU time 19.95 seconds
Started Jun 09 01:32:49 PM PDT 24
Finished Jun 09 01:33:09 PM PDT 24
Peak memory 218352 kb
Host smart-66e40d94-cdc3-4048-b569-20f3b448bc32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052591017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1052591017
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3988770027
Short name T349
Test name
Test status
Simulation time 705087278 ps
CPU time 13.94 seconds
Started Jun 09 01:32:51 PM PDT 24
Finished Jun 09 01:33:05 PM PDT 24
Peak memory 218288 kb
Host smart-f9c399bc-c54b-4a42-bc4e-1d0210c8a106
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988770027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.3988770027
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2094003526
Short name T230
Test name
Test status
Simulation time 1445954001 ps
CPU time 9.15 seconds
Started Jun 09 01:32:51 PM PDT 24
Finished Jun 09 01:33:01 PM PDT 24
Peak memory 226100 kb
Host smart-8a3fa67b-ac48-4442-97a1-2c66d3619415
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094003526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2094003526
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.1493797329
Short name T539
Test name
Test status
Simulation time 414453439 ps
CPU time 10.55 seconds
Started Jun 09 01:32:52 PM PDT 24
Finished Jun 09 01:33:03 PM PDT 24
Peak memory 224880 kb
Host smart-8cbaffe0-00a4-4844-8357-7798295454f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493797329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.1493797329
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.3320025944
Short name T784
Test name
Test status
Simulation time 33487763 ps
CPU time 2.17 seconds
Started Jun 09 01:32:51 PM PDT 24
Finished Jun 09 01:32:53 PM PDT 24
Peak memory 214396 kb
Host smart-5023b95c-42ec-4b7c-b963-7454d588e1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320025944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3320025944
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2216329597
Short name T850
Test name
Test status
Simulation time 212641622 ps
CPU time 26.16 seconds
Started Jun 09 01:32:49 PM PDT 24
Finished Jun 09 01:33:15 PM PDT 24
Peak memory 250916 kb
Host smart-2dd07009-695b-4328-a1d3-ee724069d871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216329597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2216329597
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1088255705
Short name T827
Test name
Test status
Simulation time 140275709 ps
CPU time 8.96 seconds
Started Jun 09 01:32:53 PM PDT 24
Finished Jun 09 01:33:02 PM PDT 24
Peak memory 250904 kb
Host smart-b8c23512-0a2a-413f-a524-bf929900b86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088255705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1088255705
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1273458531
Short name T429
Test name
Test status
Simulation time 2066061181 ps
CPU time 82.6 seconds
Started Jun 09 01:32:52 PM PDT 24
Finished Jun 09 01:34:14 PM PDT 24
Peak memory 247660 kb
Host smart-e0bfb59e-c645-41d2-bb10-147396c26f16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273458531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1273458531
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.782841539
Short name T367
Test name
Test status
Simulation time 12555946 ps
CPU time 0.85 seconds
Started Jun 09 01:32:52 PM PDT 24
Finished Jun 09 01:32:53 PM PDT 24
Peak memory 211880 kb
Host smart-c955cffc-8155-4370-b90c-39b523728af6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782841539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct
rl_volatile_unlock_smoke.782841539
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.598272176
Short name T357
Test name
Test status
Simulation time 27602793 ps
CPU time 0.89 seconds
Started Jun 09 01:32:57 PM PDT 24
Finished Jun 09 01:32:58 PM PDT 24
Peak memory 208832 kb
Host smart-6e8b1093-22d2-4f58-a4b1-a16518185040
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598272176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.598272176
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.1986550180
Short name T857
Test name
Test status
Simulation time 2465619854 ps
CPU time 18.07 seconds
Started Jun 09 01:32:58 PM PDT 24
Finished Jun 09 01:33:16 PM PDT 24
Peak memory 218288 kb
Host smart-1e64329c-749a-4554-bca0-3806d1197f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986550180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1986550180
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.4014625622
Short name T379
Test name
Test status
Simulation time 607023441 ps
CPU time 7.46 seconds
Started Jun 09 01:32:59 PM PDT 24
Finished Jun 09 01:33:07 PM PDT 24
Peak memory 217088 kb
Host smart-51b5950d-4803-4647-8206-00cb2aa5ff1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014625622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.4014625622
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.2049615327
Short name T102
Test name
Test status
Simulation time 341824783 ps
CPU time 3.29 seconds
Started Jun 09 01:32:58 PM PDT 24
Finished Jun 09 01:33:02 PM PDT 24
Peak memory 218224 kb
Host smart-29425161-7b12-4f27-862c-98fffe6dc51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049615327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2049615327
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.3417218143
Short name T701
Test name
Test status
Simulation time 538901969 ps
CPU time 11.85 seconds
Started Jun 09 01:32:56 PM PDT 24
Finished Jun 09 01:33:08 PM PDT 24
Peak memory 226092 kb
Host smart-87a78eb5-b3e5-4db2-8172-122ff1c10392
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417218143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.3417218143
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.741827992
Short name T703
Test name
Test status
Simulation time 1553200527 ps
CPU time 10.73 seconds
Started Jun 09 01:32:58 PM PDT 24
Finished Jun 09 01:33:09 PM PDT 24
Peak memory 218284 kb
Host smart-98c37f83-ef69-472f-b159-d4a022a73193
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741827992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.741827992
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.747826083
Short name T219
Test name
Test status
Simulation time 215804443 ps
CPU time 8.64 seconds
Started Jun 09 01:32:58 PM PDT 24
Finished Jun 09 01:33:07 PM PDT 24
Peak memory 218236 kb
Host smart-ecd2e674-b0b0-4f08-8e3a-c5ba9471ce5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747826083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.747826083
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.2689721976
Short name T47
Test name
Test status
Simulation time 2693527950 ps
CPU time 10.07 seconds
Started Jun 09 01:32:58 PM PDT 24
Finished Jun 09 01:33:08 PM PDT 24
Peak memory 226144 kb
Host smart-50334298-e756-417c-a6c5-a6b17e6cf47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689721976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.2689721976
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.4207198973
Short name T861
Test name
Test status
Simulation time 100074314 ps
CPU time 3.01 seconds
Started Jun 09 01:32:56 PM PDT 24
Finished Jun 09 01:33:00 PM PDT 24
Peak memory 214880 kb
Host smart-a67fa0f8-158f-481e-a0bd-f7b4ef243d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207198973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.4207198973
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.3198463268
Short name T297
Test name
Test status
Simulation time 2170100194 ps
CPU time 20.31 seconds
Started Jun 09 01:32:56 PM PDT 24
Finished Jun 09 01:33:16 PM PDT 24
Peak memory 250976 kb
Host smart-07816ba4-bb73-4f41-9e2f-9f43e5ebfc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198463268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.3198463268
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.1553266371
Short name T239
Test name
Test status
Simulation time 73218147 ps
CPU time 3.19 seconds
Started Jun 09 01:32:57 PM PDT 24
Finished Jun 09 01:33:00 PM PDT 24
Peak memory 226288 kb
Host smart-42e10db4-4c39-40fd-89e7-a2aa597da20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553266371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1553266371
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3139089300
Short name T304
Test name
Test status
Simulation time 2566249131 ps
CPU time 59.37 seconds
Started Jun 09 01:32:55 PM PDT 24
Finished Jun 09 01:33:55 PM PDT 24
Peak memory 277624 kb
Host smart-e3a2692a-1301-45de-9fe0-48c85cc9eabd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139089300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3139089300
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.4030325966
Short name T485
Test name
Test status
Simulation time 14187922 ps
CPU time 0.75 seconds
Started Jun 09 01:33:00 PM PDT 24
Finished Jun 09 01:33:01 PM PDT 24
Peak memory 208088 kb
Host smart-d64ec71c-3b64-48bc-b554-1a560ffa90a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030325966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.4030325966
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.1195772416
Short name T740
Test name
Test status
Simulation time 41785761 ps
CPU time 0.96 seconds
Started Jun 09 01:33:03 PM PDT 24
Finished Jun 09 01:33:04 PM PDT 24
Peak memory 208904 kb
Host smart-3338a01e-6591-4b68-8093-505895f06185
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195772416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1195772416
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3110272821
Short name T103
Test name
Test status
Simulation time 271485166 ps
CPU time 8.72 seconds
Started Jun 09 01:33:01 PM PDT 24
Finished Jun 09 01:33:10 PM PDT 24
Peak memory 218304 kb
Host smart-748c87ca-466e-453c-ac3c-b66b3b5c3a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110272821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3110272821
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.4219032506
Short name T375
Test name
Test status
Simulation time 1002797579 ps
CPU time 17.74 seconds
Started Jun 09 01:33:05 PM PDT 24
Finished Jun 09 01:33:23 PM PDT 24
Peak memory 217124 kb
Host smart-cd8b0f1a-e86a-4d4f-8077-f079d3cf801b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219032506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.4219032506
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.1429585228
Short name T106
Test name
Test status
Simulation time 77929273 ps
CPU time 3.68 seconds
Started Jun 09 01:33:05 PM PDT 24
Finished Jun 09 01:33:09 PM PDT 24
Peak memory 218228 kb
Host smart-4b3b00c5-a02b-48a8-96b2-f22735107f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429585228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1429585228
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.2100068266
Short name T698
Test name
Test status
Simulation time 593907142 ps
CPU time 12.89 seconds
Started Jun 09 01:33:01 PM PDT 24
Finished Jun 09 01:33:14 PM PDT 24
Peak memory 218940 kb
Host smart-76dbf849-1c30-4274-956e-898789aff394
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100068266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2100068266
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.1927849
Short name T265
Test name
Test status
Simulation time 1389152812 ps
CPU time 9.14 seconds
Started Jun 09 01:33:02 PM PDT 24
Finished Jun 09 01:33:11 PM PDT 24
Peak memory 218220 kb
Host smart-06d37a3b-5c54-4dd4-8093-49dec2ea977d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dige
st_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_dige
st.1927849
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1474440761
Short name T731
Test name
Test status
Simulation time 8368021624 ps
CPU time 12.88 seconds
Started Jun 09 01:33:02 PM PDT 24
Finished Jun 09 01:33:15 PM PDT 24
Peak memory 218324 kb
Host smart-0f0922c5-a133-480c-bcb0-f5e84c3a664f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474440761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
1474440761
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.589852106
Short name T382
Test name
Test status
Simulation time 2742422403 ps
CPU time 7.37 seconds
Started Jun 09 01:33:01 PM PDT 24
Finished Jun 09 01:33:09 PM PDT 24
Peak memory 224820 kb
Host smart-5c01e0b8-3d70-4b4a-ae8a-0a3a668cad81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589852106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.589852106
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.458155898
Short name T79
Test name
Test status
Simulation time 129412642 ps
CPU time 2.22 seconds
Started Jun 09 01:32:54 PM PDT 24
Finished Jun 09 01:32:57 PM PDT 24
Peak memory 217744 kb
Host smart-f2bae652-d8ef-4b58-8c0e-9b983d721123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458155898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.458155898
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.2315801826
Short name T769
Test name
Test status
Simulation time 338044141 ps
CPU time 28.96 seconds
Started Jun 09 01:32:58 PM PDT 24
Finished Jun 09 01:33:27 PM PDT 24
Peak memory 250912 kb
Host smart-78f3491b-e941-411e-b421-912d2c94b86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315801826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.2315801826
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.2253480103
Short name T816
Test name
Test status
Simulation time 129657775 ps
CPU time 6.6 seconds
Started Jun 09 01:32:57 PM PDT 24
Finished Jun 09 01:33:04 PM PDT 24
Peak memory 246744 kb
Host smart-4c5ea165-a842-451a-bc53-995a6c830a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253480103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.2253480103
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.3903167478
Short name T871
Test name
Test status
Simulation time 15295938524 ps
CPU time 174.2 seconds
Started Jun 09 01:33:02 PM PDT 24
Finished Jun 09 01:35:57 PM PDT 24
Peak memory 250976 kb
Host smart-229603ee-071a-42b2-ad84-6c89504d75f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903167478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.3903167478
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1880769349
Short name T151
Test name
Test status
Simulation time 32040176692 ps
CPU time 270.73 seconds
Started Jun 09 01:33:02 PM PDT 24
Finished Jun 09 01:37:33 PM PDT 24
Peak memory 292660 kb
Host smart-7a346a6c-5045-4054-bc72-337a47132ba9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1880769349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.1880769349
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.888586022
Short name T858
Test name
Test status
Simulation time 94196483 ps
CPU time 0.85 seconds
Started Jun 09 01:32:59 PM PDT 24
Finished Jun 09 01:33:00 PM PDT 24
Peak memory 211932 kb
Host smart-cdac0967-ad79-4f93-8a94-46f711b34c73
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888586022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ct
rl_volatile_unlock_smoke.888586022
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.1794360039
Short name T418
Test name
Test status
Simulation time 30340294 ps
CPU time 0.85 seconds
Started Jun 09 01:33:08 PM PDT 24
Finished Jun 09 01:33:09 PM PDT 24
Peak memory 208820 kb
Host smart-8ce92b90-5d68-4d50-89dc-2237eccef40c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794360039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.1794360039
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.1562729395
Short name T350
Test name
Test status
Simulation time 231728663 ps
CPU time 11.97 seconds
Started Jun 09 01:33:04 PM PDT 24
Finished Jun 09 01:33:16 PM PDT 24
Peak memory 226080 kb
Host smart-7821e876-7e44-4bca-9199-88220e3bf0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562729395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.1562729395
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1089686120
Short name T29
Test name
Test status
Simulation time 222806123 ps
CPU time 5.67 seconds
Started Jun 09 01:33:01 PM PDT 24
Finished Jun 09 01:33:07 PM PDT 24
Peak memory 217168 kb
Host smart-b347f288-0e63-4739-9210-81fb13b42a31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089686120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1089686120
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.1246454146
Short name T378
Test name
Test status
Simulation time 109748237 ps
CPU time 3.07 seconds
Started Jun 09 01:33:01 PM PDT 24
Finished Jun 09 01:33:04 PM PDT 24
Peak memory 222476 kb
Host smart-3c801ff1-f104-46fa-a553-8c3b545bf8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246454146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1246454146
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1793306783
Short name T260
Test name
Test status
Simulation time 362375965 ps
CPU time 16.59 seconds
Started Jun 09 01:33:03 PM PDT 24
Finished Jun 09 01:33:20 PM PDT 24
Peak memory 218344 kb
Host smart-a4956346-f024-466a-978c-1c007658f1e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793306783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1793306783
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3925236188
Short name T603
Test name
Test status
Simulation time 1585761793 ps
CPU time 14.16 seconds
Started Jun 09 01:33:01 PM PDT 24
Finished Jun 09 01:33:16 PM PDT 24
Peak memory 218268 kb
Host smart-fbadc4e2-6a86-4624-b687-b62daa3137ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925236188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.3925236188
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3029343337
Short name T556
Test name
Test status
Simulation time 326415811 ps
CPU time 11.87 seconds
Started Jun 09 01:33:01 PM PDT 24
Finished Jun 09 01:33:14 PM PDT 24
Peak memory 218268 kb
Host smart-314e3e8b-4e9d-4b90-85ff-e039b5d5de66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029343337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3029343337
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.973517896
Short name T335
Test name
Test status
Simulation time 3308119986 ps
CPU time 13.33 seconds
Started Jun 09 01:33:02 PM PDT 24
Finished Jun 09 01:33:16 PM PDT 24
Peak memory 226140 kb
Host smart-7434782a-f222-4a72-9268-07212d066734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973517896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.973517896
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2289533238
Short name T470
Test name
Test status
Simulation time 143480813 ps
CPU time 1.92 seconds
Started Jun 09 01:33:02 PM PDT 24
Finished Jun 09 01:33:04 PM PDT 24
Peak memory 214072 kb
Host smart-7118de43-8ad3-4dc2-86d0-627419cf2d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289533238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2289533238
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.2619578926
Short name T455
Test name
Test status
Simulation time 240786084 ps
CPU time 26.37 seconds
Started Jun 09 01:33:01 PM PDT 24
Finished Jun 09 01:33:28 PM PDT 24
Peak memory 250916 kb
Host smart-3b2afd67-4cff-40c7-a615-b089999a9de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619578926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2619578926
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.1074044
Short name T295
Test name
Test status
Simulation time 396455265 ps
CPU time 6.9 seconds
Started Jun 09 01:33:06 PM PDT 24
Finished Jun 09 01:33:13 PM PDT 24
Peak memory 250468 kb
Host smart-d2fa9acb-58c9-4adc-beec-6cc4171b90c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.1074044
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.796281879
Short name T708
Test name
Test status
Simulation time 7482163795 ps
CPU time 46.98 seconds
Started Jun 09 01:33:05 PM PDT 24
Finished Jun 09 01:33:52 PM PDT 24
Peak memory 254032 kb
Host smart-6492f030-3771-4f88-84e8-91545c857ea3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796281879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.796281879
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.2649596756
Short name T156
Test name
Test status
Simulation time 7745740732 ps
CPU time 286.33 seconds
Started Jun 09 01:33:07 PM PDT 24
Finished Jun 09 01:37:54 PM PDT 24
Peak memory 496784 kb
Host smart-ce5bd704-bf7d-4b27-96e3-2c22a09fb21c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2649596756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.2649596756
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.4047160980
Short name T492
Test name
Test status
Simulation time 19010385 ps
CPU time 1 seconds
Started Jun 09 01:33:04 PM PDT 24
Finished Jun 09 01:33:05 PM PDT 24
Peak memory 211964 kb
Host smart-880eb1f7-e3da-43d5-a5a4-2aae434bd73e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047160980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.4047160980
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.1352832997
Short name T312
Test name
Test status
Simulation time 58139704 ps
CPU time 0.88 seconds
Started Jun 09 01:33:09 PM PDT 24
Finished Jun 09 01:33:10 PM PDT 24
Peak memory 208928 kb
Host smart-985582f7-7063-4649-9d0c-963544c99064
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352832997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.1352832997
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.3904081367
Short name T416
Test name
Test status
Simulation time 3333457897 ps
CPU time 9.73 seconds
Started Jun 09 01:33:06 PM PDT 24
Finished Jun 09 01:33:16 PM PDT 24
Peak memory 218992 kb
Host smart-a31f8383-f11b-42f0-ad32-f2aac43a5d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904081367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.3904081367
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.2138348765
Short name T383
Test name
Test status
Simulation time 390845724 ps
CPU time 4.2 seconds
Started Jun 09 01:33:06 PM PDT 24
Finished Jun 09 01:33:10 PM PDT 24
Peak memory 217416 kb
Host smart-69b72cc7-5048-48a9-99d1-d479342c935b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138348765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.2138348765
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2300475153
Short name T217
Test name
Test status
Simulation time 110174986 ps
CPU time 4.92 seconds
Started Jun 09 01:33:08 PM PDT 24
Finished Jun 09 01:33:13 PM PDT 24
Peak memory 218224 kb
Host smart-8304ff49-aa1b-404a-a2f4-065bfcbc5306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300475153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2300475153
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.1182511887
Short name T789
Test name
Test status
Simulation time 1194577437 ps
CPU time 13.54 seconds
Started Jun 09 01:33:06 PM PDT 24
Finished Jun 09 01:33:20 PM PDT 24
Peak memory 218936 kb
Host smart-82ac407e-7781-462d-8e02-d62e73417da0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182511887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.1182511887
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2311697785
Short name T798
Test name
Test status
Simulation time 352084071 ps
CPU time 10.06 seconds
Started Jun 09 01:33:07 PM PDT 24
Finished Jun 09 01:33:17 PM PDT 24
Peak memory 218264 kb
Host smart-f1f3d084-1236-4dfc-a3e9-2d408de1f52f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311697785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2311697785
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.1171711225
Short name T414
Test name
Test status
Simulation time 433878881 ps
CPU time 8.08 seconds
Started Jun 09 01:33:07 PM PDT 24
Finished Jun 09 01:33:15 PM PDT 24
Peak memory 218276 kb
Host smart-77b3c617-8f89-49d7-a333-8f96d3d783f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171711225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
1171711225
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.4227968599
Short name T424
Test name
Test status
Simulation time 315274309 ps
CPU time 11.98 seconds
Started Jun 09 01:33:06 PM PDT 24
Finished Jun 09 01:33:18 PM PDT 24
Peak memory 218340 kb
Host smart-ad79f4a0-f114-4c85-b2b3-eb75975e0aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227968599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.4227968599
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.1981848171
Short name T80
Test name
Test status
Simulation time 77995741 ps
CPU time 2.43 seconds
Started Jun 09 01:33:05 PM PDT 24
Finished Jun 09 01:33:08 PM PDT 24
Peak memory 214488 kb
Host smart-d449b8d7-bda1-4ca4-9aa7-8ff8a54966b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981848171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.1981848171
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.2703608483
Short name T616
Test name
Test status
Simulation time 672987898 ps
CPU time 29.14 seconds
Started Jun 09 01:33:09 PM PDT 24
Finished Jun 09 01:33:38 PM PDT 24
Peak memory 250924 kb
Host smart-17a40e24-0eb3-4dd3-9e6b-530d7b8c6226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703608483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2703608483
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.2487037786
Short name T704
Test name
Test status
Simulation time 77638497 ps
CPU time 8.44 seconds
Started Jun 09 01:33:07 PM PDT 24
Finished Jun 09 01:33:16 PM PDT 24
Peak memory 243188 kb
Host smart-bfaaf782-d78f-41e4-b989-292a03d75de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487037786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.2487037786
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.51584888
Short name T759
Test name
Test status
Simulation time 2204283549 ps
CPU time 69.96 seconds
Started Jun 09 01:33:07 PM PDT 24
Finished Jun 09 01:34:17 PM PDT 24
Peak memory 267680 kb
Host smart-14b122ed-006e-4511-9bf1-bf420ef0687b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51584888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.lc_ctrl_stress_all.51584888
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1063965158
Short name T568
Test name
Test status
Simulation time 43605743 ps
CPU time 0.87 seconds
Started Jun 09 01:33:08 PM PDT 24
Finished Jun 09 01:33:09 PM PDT 24
Peak memory 211848 kb
Host smart-27c24e58-9ddb-493d-9094-4de1f6183311
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063965158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1063965158
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.1072813677
Short name T598
Test name
Test status
Simulation time 38364105 ps
CPU time 1.28 seconds
Started Jun 09 01:33:18 PM PDT 24
Finished Jun 09 01:33:19 PM PDT 24
Peak memory 208988 kb
Host smart-2f61e3d7-9e5b-44f6-b022-f3916043bc87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072813677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1072813677
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.1304064717
Short name T604
Test name
Test status
Simulation time 276879821 ps
CPU time 14.15 seconds
Started Jun 09 01:33:14 PM PDT 24
Finished Jun 09 01:33:28 PM PDT 24
Peak memory 218244 kb
Host smart-5929489e-226a-44f0-b922-fe201aa8417f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304064717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1304064717
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3209511514
Short name T28
Test name
Test status
Simulation time 1800051368 ps
CPU time 10.48 seconds
Started Jun 09 01:33:16 PM PDT 24
Finished Jun 09 01:33:26 PM PDT 24
Peak memory 217232 kb
Host smart-e2402c7f-6340-4842-9013-c010ae7896b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209511514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.3209511514
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.2803690189
Short name T448
Test name
Test status
Simulation time 623952407 ps
CPU time 3.92 seconds
Started Jun 09 01:33:15 PM PDT 24
Finished Jun 09 01:33:19 PM PDT 24
Peak memory 222356 kb
Host smart-d09b733d-545a-47a4-bc8a-6e74ffc7009f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803690189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.2803690189
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.2705007178
Short name T306
Test name
Test status
Simulation time 3320136819 ps
CPU time 20.57 seconds
Started Jun 09 01:33:13 PM PDT 24
Finished Jun 09 01:33:34 PM PDT 24
Peak memory 219572 kb
Host smart-26346d2c-3222-4884-8a34-854fde8d7c3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705007178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.2705007178
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.785660032
Short name T263
Test name
Test status
Simulation time 1868514971 ps
CPU time 11.43 seconds
Started Jun 09 01:33:14 PM PDT 24
Finished Jun 09 01:33:26 PM PDT 24
Peak memory 218272 kb
Host smart-e2ded010-9085-445c-bc08-2b61eef82ec9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785660032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_di
gest.785660032
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.1840544282
Short name T486
Test name
Test status
Simulation time 347336308 ps
CPU time 9.21 seconds
Started Jun 09 01:33:13 PM PDT 24
Finished Jun 09 01:33:23 PM PDT 24
Peak memory 218252 kb
Host smart-dac5e923-f4dc-440c-bd6f-f6a481909452
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840544282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
1840544282
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2707760188
Short name T400
Test name
Test status
Simulation time 674651716 ps
CPU time 6.13 seconds
Started Jun 09 01:33:15 PM PDT 24
Finished Jun 09 01:33:21 PM PDT 24
Peak memory 218296 kb
Host smart-f4a0bc2e-bd6a-4665-9904-ade91a96a921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707760188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2707760188
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.2754982147
Short name T735
Test name
Test status
Simulation time 189743872 ps
CPU time 2.78 seconds
Started Jun 09 01:33:14 PM PDT 24
Finished Jun 09 01:33:17 PM PDT 24
Peak memory 214648 kb
Host smart-7a8768aa-f963-4617-bbaf-b5e6277d6cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754982147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.2754982147
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3158167282
Short name T385
Test name
Test status
Simulation time 416375112 ps
CPU time 22.01 seconds
Started Jun 09 01:33:13 PM PDT 24
Finished Jun 09 01:33:35 PM PDT 24
Peak memory 250884 kb
Host smart-a9decc15-7ac8-417d-9ea4-e70bf37052f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158167282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3158167282
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3033268493
Short name T640
Test name
Test status
Simulation time 362859203 ps
CPU time 8.25 seconds
Started Jun 09 01:33:11 PM PDT 24
Finished Jun 09 01:33:20 PM PDT 24
Peak memory 250896 kb
Host smart-d6b96786-43eb-408f-b8a9-adee95cc9053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033268493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3033268493
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.3967812076
Short name T625
Test name
Test status
Simulation time 34876518586 ps
CPU time 184.28 seconds
Started Jun 09 01:33:12 PM PDT 24
Finished Jun 09 01:36:16 PM PDT 24
Peak memory 273724 kb
Host smart-349e7de3-4843-46df-8ec6-434079e9219c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967812076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.3967812076
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.821497262
Short name T148
Test name
Test status
Simulation time 85366992069 ps
CPU time 931.28 seconds
Started Jun 09 01:33:14 PM PDT 24
Finished Jun 09 01:48:46 PM PDT 24
Peak memory 461748 kb
Host smart-a5f832d9-2897-4afa-b402-ec7763c1c525
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=821497262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.821497262
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1613505608
Short name T773
Test name
Test status
Simulation time 167183439 ps
CPU time 0.9 seconds
Started Jun 09 01:33:15 PM PDT 24
Finished Jun 09 01:33:17 PM PDT 24
Peak memory 211916 kb
Host smart-35d3c925-5601-418f-88cc-24eb9f0d7744
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613505608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.1613505608
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.138818308
Short name T611
Test name
Test status
Simulation time 332733792 ps
CPU time 1.1 seconds
Started Jun 09 01:33:22 PM PDT 24
Finished Jun 09 01:33:23 PM PDT 24
Peak memory 208988 kb
Host smart-6cbfbfaa-85cf-4db1-aa07-5c0823abd9c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138818308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.138818308
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.531451555
Short name T874
Test name
Test status
Simulation time 317119288 ps
CPU time 13.37 seconds
Started Jun 09 01:33:19 PM PDT 24
Finished Jun 09 01:33:33 PM PDT 24
Peak memory 218220 kb
Host smart-3bec89ab-323c-4dbb-a82a-cda70f046053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531451555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.531451555
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2555686892
Short name T353
Test name
Test status
Simulation time 1406375206 ps
CPU time 3.43 seconds
Started Jun 09 01:33:19 PM PDT 24
Finished Jun 09 01:33:23 PM PDT 24
Peak memory 217172 kb
Host smart-c7693669-f6cf-4291-bc5d-5cd5f5368f29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555686892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2555686892
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.98033822
Short name T629
Test name
Test status
Simulation time 500503681 ps
CPU time 2.48 seconds
Started Jun 09 01:33:18 PM PDT 24
Finished Jun 09 01:33:21 PM PDT 24
Peak memory 222084 kb
Host smart-8ba815c7-a7ba-49e3-9730-1a762f4c629f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98033822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.98033822
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1390682571
Short name T536
Test name
Test status
Simulation time 608258605 ps
CPU time 10.14 seconds
Started Jun 09 01:33:18 PM PDT 24
Finished Jun 09 01:33:28 PM PDT 24
Peak memory 218328 kb
Host smart-29a005fd-e11b-44bc-999e-60e2affa31bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390682571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1390682571
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3994592539
Short name T767
Test name
Test status
Simulation time 828172899 ps
CPU time 10.13 seconds
Started Jun 09 01:33:19 PM PDT 24
Finished Jun 09 01:33:30 PM PDT 24
Peak memory 218276 kb
Host smart-698278a4-9674-4602-83d1-624be46d3472
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994592539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3994592539
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.213758346
Short name T449
Test name
Test status
Simulation time 302820322 ps
CPU time 9.68 seconds
Started Jun 09 01:33:17 PM PDT 24
Finished Jun 09 01:33:27 PM PDT 24
Peak memory 218328 kb
Host smart-0f597a64-e690-4ecb-a5f0-bdc9bf12e0fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213758346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.213758346
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3910472108
Short name T709
Test name
Test status
Simulation time 1039770601 ps
CPU time 7.19 seconds
Started Jun 09 01:33:17 PM PDT 24
Finished Jun 09 01:33:24 PM PDT 24
Peak memory 225012 kb
Host smart-f407e0da-fa55-424b-9b88-f76d23dda48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910472108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3910472108
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.3194897979
Short name T442
Test name
Test status
Simulation time 346050974 ps
CPU time 1.51 seconds
Started Jun 09 01:33:19 PM PDT 24
Finished Jun 09 01:33:20 PM PDT 24
Peak memory 222312 kb
Host smart-aaf5db42-1926-4fec-b184-d0f00ce92c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194897979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3194897979
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3403640067
Short name T612
Test name
Test status
Simulation time 606151331 ps
CPU time 29.08 seconds
Started Jun 09 01:33:19 PM PDT 24
Finished Jun 09 01:33:48 PM PDT 24
Peak memory 250908 kb
Host smart-66a019dc-0c45-46b7-8b28-3f9583a3247a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403640067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3403640067
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.3632687205
Short name T303
Test name
Test status
Simulation time 243238641 ps
CPU time 6.69 seconds
Started Jun 09 01:33:19 PM PDT 24
Finished Jun 09 01:33:25 PM PDT 24
Peak memory 247028 kb
Host smart-4c13ac80-cc54-4ba5-9b81-c5c5d69fe7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632687205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3632687205
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.698518844
Short name T291
Test name
Test status
Simulation time 9346123638 ps
CPU time 28.81 seconds
Started Jun 09 01:33:17 PM PDT 24
Finished Jun 09 01:33:46 PM PDT 24
Peak memory 251036 kb
Host smart-693136e1-8a13-4458-b01d-0c4b815177bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698518844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.698518844
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3613432354
Short name T685
Test name
Test status
Simulation time 194522774 ps
CPU time 0.97 seconds
Started Jun 09 01:33:19 PM PDT 24
Finished Jun 09 01:33:21 PM PDT 24
Peak memory 217760 kb
Host smart-64623ac6-a349-48d5-ac27-fb9c0fccc8c2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613432354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.3613432354
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.1407211331
Short name T559
Test name
Test status
Simulation time 31828621 ps
CPU time 1.12 seconds
Started Jun 09 01:29:43 PM PDT 24
Finished Jun 09 01:29:44 PM PDT 24
Peak memory 209008 kb
Host smart-23dc2c0c-22ea-4f5a-82cc-c7f775850048
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407211331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.1407211331
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.813048003
Short name T213
Test name
Test status
Simulation time 20125671 ps
CPU time 0.79 seconds
Started Jun 09 01:29:48 PM PDT 24
Finished Jun 09 01:29:49 PM PDT 24
Peak memory 208992 kb
Host smart-f1ecb2da-55da-4f87-8be1-ec69b4e4af80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813048003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.813048003
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.388080986
Short name T802
Test name
Test status
Simulation time 583094793 ps
CPU time 14.71 seconds
Started Jun 09 01:29:37 PM PDT 24
Finished Jun 09 01:29:52 PM PDT 24
Peak memory 218236 kb
Host smart-23418b5c-69a6-4951-a872-f1759ff5fc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388080986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.388080986
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.2112163223
Short name T638
Test name
Test status
Simulation time 1080145048 ps
CPU time 8.06 seconds
Started Jun 09 01:29:42 PM PDT 24
Finished Jun 09 01:29:51 PM PDT 24
Peak memory 217388 kb
Host smart-d2692cf0-48a6-47fd-bba5-7549142e7935
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112163223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.2112163223
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.3249414678
Short name T610
Test name
Test status
Simulation time 4089650999 ps
CPU time 40.71 seconds
Started Jun 09 01:29:43 PM PDT 24
Finished Jun 09 01:30:24 PM PDT 24
Peak memory 218916 kb
Host smart-fd0ceb1a-d7e6-4528-a25b-fd618b4011f6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249414678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.3249414678
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.3550364230
Short name T815
Test name
Test status
Simulation time 222329990 ps
CPU time 4.74 seconds
Started Jun 09 01:29:43 PM PDT 24
Finished Jun 09 01:29:48 PM PDT 24
Peak memory 217808 kb
Host smart-81d5c636-2d3b-4c7a-a50c-d44381e54d8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550364230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.3
550364230
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.212406321
Short name T589
Test name
Test status
Simulation time 126907272 ps
CPU time 2.75 seconds
Started Jun 09 01:29:44 PM PDT 24
Finished Jun 09 01:29:47 PM PDT 24
Peak memory 221544 kb
Host smart-e8314a4f-8588-45c0-bd09-508f441035ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212406321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.212406321
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.210572044
Short name T519
Test name
Test status
Simulation time 1171824722 ps
CPU time 15.14 seconds
Started Jun 09 01:29:43 PM PDT 24
Finished Jun 09 01:29:59 PM PDT 24
Peak memory 217688 kb
Host smart-4bac4834-f1b7-4100-8beb-9ab3eb1176eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210572044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_regwen_during_op.210572044
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.3504229477
Short name T314
Test name
Test status
Simulation time 1367559539 ps
CPU time 9.62 seconds
Started Jun 09 01:29:42 PM PDT 24
Finished Jun 09 01:29:52 PM PDT 24
Peak memory 217696 kb
Host smart-887af27c-43be-412a-9528-8c9e693fdb44
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504229477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
3504229477
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1196769212
Short name T779
Test name
Test status
Simulation time 1597355171 ps
CPU time 36.42 seconds
Started Jun 09 01:29:43 PM PDT 24
Finished Jun 09 01:30:20 PM PDT 24
Peak memory 250852 kb
Host smart-9b7a55d5-2618-4a94-8c46-4e18a3516304
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196769212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.1196769212
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.3060447072
Short name T496
Test name
Test status
Simulation time 772665035 ps
CPU time 15.45 seconds
Started Jun 09 01:29:42 PM PDT 24
Finished Jun 09 01:29:58 PM PDT 24
Peak memory 250520 kb
Host smart-94cd309d-913e-4459-a647-50ed7861b5f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060447072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.3060447072
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.421106997
Short name T574
Test name
Test status
Simulation time 573795129 ps
CPU time 4.64 seconds
Started Jun 09 01:29:36 PM PDT 24
Finished Jun 09 01:29:41 PM PDT 24
Peak memory 222840 kb
Host smart-aafd43dc-c610-4000-972b-7dab87f3e6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421106997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.421106997
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.3961608996
Short name T72
Test name
Test status
Simulation time 275428136 ps
CPU time 17.78 seconds
Started Jun 09 01:29:46 PM PDT 24
Finished Jun 09 01:30:04 PM PDT 24
Peak memory 217764 kb
Host smart-dc68408b-f7a4-4172-a490-6b062c57b725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961608996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.3961608996
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.167375129
Short name T351
Test name
Test status
Simulation time 2598974789 ps
CPU time 14.98 seconds
Started Jun 09 01:29:41 PM PDT 24
Finished Jun 09 01:29:57 PM PDT 24
Peak memory 226160 kb
Host smart-0810f81d-53e1-4700-9152-3f0d9d35090b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167375129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.167375129
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1946994523
Short name T236
Test name
Test status
Simulation time 728130387 ps
CPU time 10.92 seconds
Started Jun 09 01:29:47 PM PDT 24
Finished Jun 09 01:29:58 PM PDT 24
Peak memory 218276 kb
Host smart-8d77ef02-5cb5-4e65-8631-0d7172638657
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946994523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1946994523
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1861665436
Short name T360
Test name
Test status
Simulation time 1083205451 ps
CPU time 9.82 seconds
Started Jun 09 01:29:42 PM PDT 24
Finished Jun 09 01:29:52 PM PDT 24
Peak memory 226084 kb
Host smart-b6c41a2e-1fba-4738-b29d-ef965b2a0318
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861665436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.1
861665436
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.1892853868
Short name T44
Test name
Test status
Simulation time 1362478881 ps
CPU time 13.41 seconds
Started Jun 09 01:29:44 PM PDT 24
Finished Jun 09 01:29:57 PM PDT 24
Peak memory 226088 kb
Host smart-0a6d65ea-d7b3-4bec-8a0d-42a49665d66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892853868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.1892853868
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.1561511922
Short name T235
Test name
Test status
Simulation time 387640747 ps
CPU time 2.84 seconds
Started Jun 09 01:29:38 PM PDT 24
Finished Jun 09 01:29:41 PM PDT 24
Peak memory 214808 kb
Host smart-a44e903e-ba84-451c-b1a7-91cf68e594f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561511922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1561511922
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.3927559338
Short name T514
Test name
Test status
Simulation time 389853692 ps
CPU time 31.59 seconds
Started Jun 09 01:29:37 PM PDT 24
Finished Jun 09 01:30:09 PM PDT 24
Peak memory 251000 kb
Host smart-918e9bb4-d2e8-4c54-b215-ee34a1b96be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927559338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3927559338
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.2454267480
Short name T797
Test name
Test status
Simulation time 195273309 ps
CPU time 3.53 seconds
Started Jun 09 01:29:38 PM PDT 24
Finished Jun 09 01:29:42 PM PDT 24
Peak memory 222600 kb
Host smart-97f482e4-1d98-4f92-8834-761997868504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454267480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2454267480
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.453190456
Short name T646
Test name
Test status
Simulation time 6542203272 ps
CPU time 158.79 seconds
Started Jun 09 01:29:48 PM PDT 24
Finished Jun 09 01:32:27 PM PDT 24
Peak memory 278220 kb
Host smart-46d887ab-7213-473a-b1d0-20b22f5fc21b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453190456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.453190456
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1891661822
Short name T658
Test name
Test status
Simulation time 47145385 ps
CPU time 0.85 seconds
Started Jun 09 01:29:36 PM PDT 24
Finished Jun 09 01:29:37 PM PDT 24
Peak memory 211864 kb
Host smart-9726f074-bdfa-48cc-af00-ba6201e1844b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891661822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.1891661822
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.3757050188
Short name T865
Test name
Test status
Simulation time 65416646 ps
CPU time 1.02 seconds
Started Jun 09 01:33:25 PM PDT 24
Finished Jun 09 01:33:26 PM PDT 24
Peak memory 208888 kb
Host smart-5a70f429-c06f-4307-81c0-b0dde252942e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757050188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3757050188
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.3029888993
Short name T538
Test name
Test status
Simulation time 359307349 ps
CPU time 16.22 seconds
Started Jun 09 01:33:23 PM PDT 24
Finished Jun 09 01:33:39 PM PDT 24
Peak memory 218328 kb
Host smart-2840a6cf-a83d-4336-9bec-8bab8248f496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029888993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.3029888993
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.977308068
Short name T413
Test name
Test status
Simulation time 332579981 ps
CPU time 1.79 seconds
Started Jun 09 01:33:25 PM PDT 24
Finished Jun 09 01:33:27 PM PDT 24
Peak memory 217096 kb
Host smart-21739761-bfce-44fd-98be-a06518a9bf50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977308068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.977308068
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.1036345520
Short name T259
Test name
Test status
Simulation time 102070622 ps
CPU time 2.03 seconds
Started Jun 09 01:33:25 PM PDT 24
Finished Jun 09 01:33:27 PM PDT 24
Peak memory 218232 kb
Host smart-a98ada49-b560-4463-9688-9c5b9788b253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036345520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1036345520
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1098332276
Short name T690
Test name
Test status
Simulation time 700871277 ps
CPU time 13.48 seconds
Started Jun 09 01:33:25 PM PDT 24
Finished Jun 09 01:33:39 PM PDT 24
Peak memory 218352 kb
Host smart-bb22b29a-1fd6-40b9-a314-17b8814facc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098332276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1098332276
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2751718715
Short name T528
Test name
Test status
Simulation time 1666868649 ps
CPU time 10.11 seconds
Started Jun 09 01:33:22 PM PDT 24
Finished Jun 09 01:33:32 PM PDT 24
Peak memory 218384 kb
Host smart-0abf6b3e-ee4e-453b-891d-a619dd628461
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751718715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2751718715
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3345656222
Short name T668
Test name
Test status
Simulation time 888521100 ps
CPU time 17.69 seconds
Started Jun 09 01:33:23 PM PDT 24
Finished Jun 09 01:33:41 PM PDT 24
Peak memory 218272 kb
Host smart-4e3c826f-86b0-456f-9ec3-9cf1e68d247b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345656222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
3345656222
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.944403648
Short name T262
Test name
Test status
Simulation time 925593669 ps
CPU time 6.59 seconds
Started Jun 09 01:33:23 PM PDT 24
Finished Jun 09 01:33:30 PM PDT 24
Peak memory 224596 kb
Host smart-7ff062f8-33c5-49b6-93d1-097adcc4dbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944403648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.944403648
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.792990009
Short name T399
Test name
Test status
Simulation time 235756648 ps
CPU time 2.43 seconds
Started Jun 09 01:33:20 PM PDT 24
Finished Jun 09 01:33:22 PM PDT 24
Peak memory 214456 kb
Host smart-0c23cff3-ea2a-4cea-add4-79a2b8ee234d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792990009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.792990009
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.631476954
Short name T639
Test name
Test status
Simulation time 1279721550 ps
CPU time 33.6 seconds
Started Jun 09 01:33:17 PM PDT 24
Finished Jun 09 01:33:51 PM PDT 24
Peak memory 250892 kb
Host smart-213aca3e-2b6a-4663-ad11-72036709b315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631476954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.631476954
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2320063355
Short name T370
Test name
Test status
Simulation time 78139228 ps
CPU time 2.81 seconds
Started Jun 09 01:33:22 PM PDT 24
Finished Jun 09 01:33:25 PM PDT 24
Peak memory 218140 kb
Host smart-22264d9f-4e60-401a-bef2-d7dbe45752e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320063355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2320063355
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1399107994
Short name T5
Test name
Test status
Simulation time 16491912723 ps
CPU time 46.15 seconds
Started Jun 09 01:33:24 PM PDT 24
Finished Jun 09 01:34:11 PM PDT 24
Peak memory 268668 kb
Host smart-580bedc1-8c8e-4b8e-b46e-0165d0402f4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399107994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1399107994
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2461577831
Short name T433
Test name
Test status
Simulation time 18131435 ps
CPU time 0.92 seconds
Started Jun 09 01:33:17 PM PDT 24
Finished Jun 09 01:33:18 PM PDT 24
Peak memory 213120 kb
Host smart-90cf67ec-e8cf-4939-b88a-904670be7a7a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461577831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.2461577831
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.703078041
Short name T464
Test name
Test status
Simulation time 25073774 ps
CPU time 1.33 seconds
Started Jun 09 01:33:29 PM PDT 24
Finished Jun 09 01:33:30 PM PDT 24
Peak memory 209044 kb
Host smart-132e555b-4d40-442b-ad34-aa1386450ca5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703078041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.703078041
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2393000982
Short name T308
Test name
Test status
Simulation time 344222684 ps
CPU time 10.34 seconds
Started Jun 09 01:33:32 PM PDT 24
Finished Jun 09 01:33:43 PM PDT 24
Peak memory 218244 kb
Host smart-c08e2125-9513-4a9b-962d-547a65e1ac45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393000982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2393000982
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2627167439
Short name T369
Test name
Test status
Simulation time 420150014 ps
CPU time 4.88 seconds
Started Jun 09 01:33:29 PM PDT 24
Finished Jun 09 01:33:34 PM PDT 24
Peak memory 217268 kb
Host smart-9d474b7e-5875-43d3-ae5a-ee077076c5e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627167439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.2627167439
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.1474300595
Short name T97
Test name
Test status
Simulation time 77104016 ps
CPU time 2.67 seconds
Started Jun 09 01:33:30 PM PDT 24
Finished Jun 09 01:33:33 PM PDT 24
Peak memory 222316 kb
Host smart-042c77da-d448-43a9-81bd-e0d7f53f7f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474300595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.1474300595
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.1644833407
Short name T37
Test name
Test status
Simulation time 390797430 ps
CPU time 11.35 seconds
Started Jun 09 01:33:29 PM PDT 24
Finished Jun 09 01:33:41 PM PDT 24
Peak memory 226088 kb
Host smart-23f5c618-08b7-4a5e-8171-2f871400e04c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644833407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1644833407
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.3699221297
Short name T405
Test name
Test status
Simulation time 2728027242 ps
CPU time 21.73 seconds
Started Jun 09 01:33:31 PM PDT 24
Finished Jun 09 01:33:53 PM PDT 24
Peak memory 218324 kb
Host smart-e84f3dfe-58c0-42bf-b7af-4e2f42aa84e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699221297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.3699221297
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.3917136033
Short name T293
Test name
Test status
Simulation time 897078972 ps
CPU time 14.78 seconds
Started Jun 09 01:33:29 PM PDT 24
Finished Jun 09 01:33:44 PM PDT 24
Peak memory 226080 kb
Host smart-0e67ad0e-5a26-4fe7-8f2a-80bc89cf13b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917136033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
3917136033
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3599637722
Short name T497
Test name
Test status
Simulation time 901364613 ps
CPU time 9.29 seconds
Started Jun 09 01:33:31 PM PDT 24
Finished Jun 09 01:33:41 PM PDT 24
Peak memory 226072 kb
Host smart-150ddcf2-2d04-4ea0-8c86-9c5855f1ef33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599637722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3599637722
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2850040621
Short name T62
Test name
Test status
Simulation time 299570343 ps
CPU time 4.32 seconds
Started Jun 09 01:33:24 PM PDT 24
Finished Jun 09 01:33:28 PM PDT 24
Peak memory 217764 kb
Host smart-cf7c4afb-dfa1-43a6-b8a3-0eafe5d4dc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850040621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2850040621
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2351592712
Short name T343
Test name
Test status
Simulation time 805933490 ps
CPU time 32.91 seconds
Started Jun 09 01:33:28 PM PDT 24
Finished Jun 09 01:34:01 PM PDT 24
Peak memory 250992 kb
Host smart-229e5854-a5d6-4d96-9b13-92ed6f0f6cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351592712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2351592712
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.1116104068
Short name T652
Test name
Test status
Simulation time 55800340 ps
CPU time 2.67 seconds
Started Jun 09 01:33:29 PM PDT 24
Finished Jun 09 01:33:31 PM PDT 24
Peak memory 218144 kb
Host smart-c457d4bc-e17c-40a3-be70-434f3f96093d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116104068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.1116104068
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.3470529964
Short name T517
Test name
Test status
Simulation time 6367764533 ps
CPU time 159.47 seconds
Started Jun 09 01:33:30 PM PDT 24
Finished Jun 09 01:36:09 PM PDT 24
Peak memory 283672 kb
Host smart-8412ddee-8394-49a6-a8ba-93cfa9251398
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470529964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.3470529964
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.2870995321
Short name T631
Test name
Test status
Simulation time 14839315583 ps
CPU time 134.5 seconds
Started Jun 09 01:33:29 PM PDT 24
Finished Jun 09 01:35:44 PM PDT 24
Peak memory 251180 kb
Host smart-ed386e47-cfba-442d-9f7c-987ecf6689d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2870995321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.2870995321
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2285225323
Short name T624
Test name
Test status
Simulation time 11244537 ps
CPU time 0.85 seconds
Started Jun 09 01:33:24 PM PDT 24
Finished Jun 09 01:33:25 PM PDT 24
Peak memory 211944 kb
Host smart-fb1a4bfd-5805-46ce-8c4c-46be38846e7b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285225323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.2285225323
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1623974800
Short name T581
Test name
Test status
Simulation time 19263117 ps
CPU time 0.92 seconds
Started Jun 09 01:33:34 PM PDT 24
Finished Jun 09 01:33:35 PM PDT 24
Peak memory 208964 kb
Host smart-76f86d8b-4423-4f9c-8de8-3e4ceecec0c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623974800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1623974800
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2962050989
Short name T715
Test name
Test status
Simulation time 808222800 ps
CPU time 9.03 seconds
Started Jun 09 01:33:36 PM PDT 24
Finished Jun 09 01:33:45 PM PDT 24
Peak memory 218272 kb
Host smart-f5c94f0a-4453-4087-b0cf-73db49579267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962050989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2962050989
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.2327964698
Short name T185
Test name
Test status
Simulation time 256293198 ps
CPU time 3.65 seconds
Started Jun 09 01:33:34 PM PDT 24
Finished Jun 09 01:33:38 PM PDT 24
Peak memory 217256 kb
Host smart-96fd0cae-a332-4cc4-a638-01fb986a5d5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327964698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.2327964698
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.1495564003
Short name T580
Test name
Test status
Simulation time 25915487 ps
CPU time 1.62 seconds
Started Jun 09 01:33:35 PM PDT 24
Finished Jun 09 01:33:36 PM PDT 24
Peak memory 218284 kb
Host smart-901fcd45-58d6-40a6-b8dc-2f6148b6246a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495564003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1495564003
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.661651781
Short name T348
Test name
Test status
Simulation time 812304258 ps
CPU time 24.13 seconds
Started Jun 09 01:33:33 PM PDT 24
Finished Jun 09 01:33:57 PM PDT 24
Peak memory 218936 kb
Host smart-099d903a-eb59-479a-910c-e5654921ba66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661651781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.661651781
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.579753304
Short name T270
Test name
Test status
Simulation time 677866722 ps
CPU time 8.94 seconds
Started Jun 09 01:33:40 PM PDT 24
Finished Jun 09 01:33:49 PM PDT 24
Peak memory 225712 kb
Host smart-35699cf1-67c1-4414-b94c-d5c5d72643da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579753304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_di
gest.579753304
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.353989454
Short name T822
Test name
Test status
Simulation time 256248339 ps
CPU time 6.6 seconds
Started Jun 09 01:33:34 PM PDT 24
Finished Jun 09 01:33:41 PM PDT 24
Peak memory 225356 kb
Host smart-3f0621a4-0992-4e91-8620-a88874aac790
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353989454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.353989454
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.695344484
Short name T529
Test name
Test status
Simulation time 5052380214 ps
CPU time 10.13 seconds
Started Jun 09 01:33:35 PM PDT 24
Finished Jun 09 01:33:45 PM PDT 24
Peak memory 218332 kb
Host smart-27b83bc8-0e48-46ff-86b7-2efbe7c906b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695344484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.695344484
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2882762059
Short name T60
Test name
Test status
Simulation time 61474296 ps
CPU time 2.24 seconds
Started Jun 09 01:33:29 PM PDT 24
Finished Jun 09 01:33:32 PM PDT 24
Peak memory 214304 kb
Host smart-6c0ff917-84b3-49df-b5be-2ebd761059e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882762059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2882762059
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.4017521867
Short name T51
Test name
Test status
Simulation time 424068692 ps
CPU time 24.22 seconds
Started Jun 09 01:33:40 PM PDT 24
Finished Jun 09 01:34:04 PM PDT 24
Peak memory 250980 kb
Host smart-5e45eb0b-1a3b-44dc-8d5e-4658a5128003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017521867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.4017521867
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.23890891
Short name T744
Test name
Test status
Simulation time 151526208 ps
CPU time 8.48 seconds
Started Jun 09 01:33:38 PM PDT 24
Finished Jun 09 01:33:47 PM PDT 24
Peak memory 250920 kb
Host smart-6beebcf7-f4bd-4545-a082-c8ab1c64d1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23890891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.23890891
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.3055219956
Short name T269
Test name
Test status
Simulation time 14201188111 ps
CPU time 367.82 seconds
Started Jun 09 01:33:33 PM PDT 24
Finished Jun 09 01:39:41 PM PDT 24
Peak memory 283684 kb
Host smart-2d07109a-29bb-4396-865d-f2781bc00a73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055219956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.3055219956
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.1156611517
Short name T695
Test name
Test status
Simulation time 144297913 ps
CPU time 0.9 seconds
Started Jun 09 01:33:39 PM PDT 24
Finished Jun 09 01:33:40 PM PDT 24
Peak memory 208960 kb
Host smart-71a09d19-0517-4b51-a102-f25457abc3e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156611517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.1156611517
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.140826619
Short name T697
Test name
Test status
Simulation time 222109823 ps
CPU time 8.53 seconds
Started Jun 09 01:33:39 PM PDT 24
Finished Jun 09 01:33:47 PM PDT 24
Peak memory 218308 kb
Host smart-e8eaba84-e4b2-48fe-a73b-d02b85bc9810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140826619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.140826619
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.2946526412
Short name T546
Test name
Test status
Simulation time 814794156 ps
CPU time 5.38 seconds
Started Jun 09 01:33:34 PM PDT 24
Finished Jun 09 01:33:40 PM PDT 24
Peak memory 217256 kb
Host smart-06077daf-ad33-4e88-bae7-bc212e6c7ff0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946526412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.2946526412
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.979579509
Short name T854
Test name
Test status
Simulation time 25766627 ps
CPU time 1.39 seconds
Started Jun 09 01:33:34 PM PDT 24
Finished Jun 09 01:33:36 PM PDT 24
Peak memory 221636 kb
Host smart-ca6bcb69-4e8a-4af2-bb94-5712c4765504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979579509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.979579509
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.3819001077
Short name T174
Test name
Test status
Simulation time 511426042 ps
CPU time 15.47 seconds
Started Jun 09 01:33:40 PM PDT 24
Finished Jun 09 01:33:55 PM PDT 24
Peak memory 218340 kb
Host smart-8fa101a9-223e-4e20-98ce-37403d0f6284
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819001077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.3819001077
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1553503316
Short name T218
Test name
Test status
Simulation time 2742002743 ps
CPU time 18.03 seconds
Started Jun 09 01:33:39 PM PDT 24
Finished Jun 09 01:33:58 PM PDT 24
Peak memory 226144 kb
Host smart-eec9a74f-d3c4-48d3-a882-f43fd4194086
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553503316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.1553503316
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2608968470
Short name T700
Test name
Test status
Simulation time 1883125448 ps
CPU time 16.25 seconds
Started Jun 09 01:33:41 PM PDT 24
Finished Jun 09 01:33:58 PM PDT 24
Peak memory 226080 kb
Host smart-1e6ee66f-82ec-4bd6-85f2-70559343126e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608968470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2608968470
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.1745800610
Short name T778
Test name
Test status
Simulation time 284320882 ps
CPU time 11.89 seconds
Started Jun 09 01:33:34 PM PDT 24
Finished Jun 09 01:33:47 PM PDT 24
Peak memory 218296 kb
Host smart-7c87fa2b-c923-4574-aa6a-50565fc239ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745800610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1745800610
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.2099029328
Short name T565
Test name
Test status
Simulation time 114934850 ps
CPU time 2.41 seconds
Started Jun 09 01:33:33 PM PDT 24
Finished Jun 09 01:33:36 PM PDT 24
Peak memory 214576 kb
Host smart-dcc591a6-0081-4376-a738-6593b071908a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099029328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.2099029328
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.3357382876
Short name T672
Test name
Test status
Simulation time 397508545 ps
CPU time 33.15 seconds
Started Jun 09 01:33:36 PM PDT 24
Finished Jun 09 01:34:10 PM PDT 24
Peak memory 250940 kb
Host smart-b4fa0568-41a5-4c20-9a10-45e69a5b8889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357382876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3357382876
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.387140459
Short name T444
Test name
Test status
Simulation time 75192840 ps
CPU time 3.15 seconds
Started Jun 09 01:33:40 PM PDT 24
Finished Jun 09 01:33:43 PM PDT 24
Peak memory 226336 kb
Host smart-80e7bdff-a8f8-40ab-ab8f-844e7da9d2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387140459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.387140459
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.3917846034
Short name T81
Test name
Test status
Simulation time 7370625197 ps
CPU time 62.83 seconds
Started Jun 09 01:33:42 PM PDT 24
Finished Jun 09 01:34:45 PM PDT 24
Peak memory 250956 kb
Host smart-39070509-cb05-4fa7-b360-0bfe79cec175
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917846034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.3917846034
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.1570245508
Short name T43
Test name
Test status
Simulation time 51081364740 ps
CPU time 1790.01 seconds
Started Jun 09 01:33:41 PM PDT 24
Finished Jun 09 02:03:32 PM PDT 24
Peak memory 949732 kb
Host smart-cda01cb2-e9f1-402e-99fe-83fd7483538e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1570245508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.1570245508
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.494682435
Short name T544
Test name
Test status
Simulation time 71130106 ps
CPU time 0.93 seconds
Started Jun 09 01:33:40 PM PDT 24
Finished Jun 09 01:33:41 PM PDT 24
Peak memory 211920 kb
Host smart-88d23738-1181-459a-bbce-3bebecc968a0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494682435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ct
rl_volatile_unlock_smoke.494682435
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1770040501
Short name T592
Test name
Test status
Simulation time 30960937 ps
CPU time 0.9 seconds
Started Jun 09 01:33:44 PM PDT 24
Finished Jun 09 01:33:45 PM PDT 24
Peak memory 209048 kb
Host smart-d7ab1781-7e62-490d-bcef-4d16b6dda16b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770040501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1770040501
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.4148051979
Short name T408
Test name
Test status
Simulation time 1554338704 ps
CPU time 15.95 seconds
Started Jun 09 01:33:39 PM PDT 24
Finished Jun 09 01:33:55 PM PDT 24
Peak memory 218136 kb
Host smart-e6ff9e81-e997-4036-b2b9-a6c6eae8acd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148051979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.4148051979
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.2902051196
Short name T601
Test name
Test status
Simulation time 658891286 ps
CPU time 1.68 seconds
Started Jun 09 01:33:41 PM PDT 24
Finished Jun 09 01:33:42 PM PDT 24
Peak memory 217096 kb
Host smart-fbd4d71f-482d-4892-a006-f7abd943d30f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902051196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.2902051196
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.603221484
Short name T749
Test name
Test status
Simulation time 75635850 ps
CPU time 1.65 seconds
Started Jun 09 01:33:39 PM PDT 24
Finished Jun 09 01:33:41 PM PDT 24
Peak memory 218236 kb
Host smart-77f36958-1665-4840-8a3c-7af99ceef391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603221484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.603221484
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.507121850
Short name T398
Test name
Test status
Simulation time 1043246773 ps
CPU time 17.68 seconds
Started Jun 09 01:33:41 PM PDT 24
Finished Jun 09 01:33:59 PM PDT 24
Peak memory 218612 kb
Host smart-6a618441-2bac-4aac-88d7-eb3f3a2c2211
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507121850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.507121850
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.1478449756
Short name T699
Test name
Test status
Simulation time 2118370991 ps
CPU time 13.71 seconds
Started Jun 09 01:33:43 PM PDT 24
Finished Jun 09 01:33:57 PM PDT 24
Peak memory 218360 kb
Host smart-c4522453-0cf1-456e-85db-7eab2b79a897
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478449756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.1478449756
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.2443336875
Short name T824
Test name
Test status
Simulation time 1016123629 ps
CPU time 7.39 seconds
Started Jun 09 01:33:39 PM PDT 24
Finished Jun 09 01:33:46 PM PDT 24
Peak memory 226104 kb
Host smart-3342db6e-1036-40fe-ba83-9d7c08cbca15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443336875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
2443336875
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1137125232
Short name T772
Test name
Test status
Simulation time 299880908 ps
CPU time 9.53 seconds
Started Jun 09 01:33:43 PM PDT 24
Finished Jun 09 01:33:52 PM PDT 24
Peak memory 218292 kb
Host smart-ed188b8d-bfe1-4cd8-b64b-5a29b79c94b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137125232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1137125232
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.1156650846
Short name T75
Test name
Test status
Simulation time 229697069 ps
CPU time 3.3 seconds
Started Jun 09 01:33:39 PM PDT 24
Finished Jun 09 01:33:43 PM PDT 24
Peak memory 215116 kb
Host smart-94af4989-18d5-415f-8e7d-7580f0978355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156650846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.1156650846
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2387793207
Short name T687
Test name
Test status
Simulation time 4279769876 ps
CPU time 34.99 seconds
Started Jun 09 01:33:42 PM PDT 24
Finished Jun 09 01:34:17 PM PDT 24
Peak memory 250972 kb
Host smart-06262cab-2fca-477e-ae89-17762914e118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387793207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2387793207
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.2664415746
Short name T688
Test name
Test status
Simulation time 84456027 ps
CPU time 7.69 seconds
Started Jun 09 01:33:39 PM PDT 24
Finished Jun 09 01:33:47 PM PDT 24
Peak memory 250352 kb
Host smart-26186c72-73c9-4df4-a718-0a0105966334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664415746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.2664415746
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2585025901
Short name T83
Test name
Test status
Simulation time 19661833837 ps
CPU time 333.16 seconds
Started Jun 09 01:33:44 PM PDT 24
Finished Jun 09 01:39:17 PM PDT 24
Peak memory 280392 kb
Host smart-e27fdeb0-9a38-4fde-814d-10bd8c91d734
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585025901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2585025901
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.659213479
Short name T169
Test name
Test status
Simulation time 176094639448 ps
CPU time 1114.08 seconds
Started Jun 09 01:33:45 PM PDT 24
Finished Jun 09 01:52:19 PM PDT 24
Peak memory 279412 kb
Host smart-72ed1d0b-9761-48a7-b0f5-a32f4e842d64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=659213479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.659213479
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1537143394
Short name T677
Test name
Test status
Simulation time 25413775 ps
CPU time 0.86 seconds
Started Jun 09 01:33:41 PM PDT 24
Finished Jun 09 01:33:42 PM PDT 24
Peak memory 211892 kb
Host smart-ed3c0774-b59a-4977-a965-664c612b005f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537143394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.1537143394
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.217980109
Short name T67
Test name
Test status
Simulation time 46780060 ps
CPU time 1.02 seconds
Started Jun 09 01:33:44 PM PDT 24
Finished Jun 09 01:33:45 PM PDT 24
Peak memory 208972 kb
Host smart-c46b074a-e00d-4510-8675-c934b65c90f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217980109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.217980109
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.4044918451
Short name T584
Test name
Test status
Simulation time 447561380 ps
CPU time 11.4 seconds
Started Jun 09 01:33:44 PM PDT 24
Finished Jun 09 01:33:55 PM PDT 24
Peak memory 218228 kb
Host smart-e1a608f8-c1b9-4dc4-8747-67bc00c04d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044918451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.4044918451
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.2481435506
Short name T417
Test name
Test status
Simulation time 527654784 ps
CPU time 3.56 seconds
Started Jun 09 01:33:45 PM PDT 24
Finished Jun 09 01:33:49 PM PDT 24
Peak memory 217136 kb
Host smart-43530a0f-3714-4e0d-9e4c-f82432ad55b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481435506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.2481435506
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.3261666063
Short name T511
Test name
Test status
Simulation time 89894005 ps
CPU time 1.73 seconds
Started Jun 09 01:33:44 PM PDT 24
Finished Jun 09 01:33:46 PM PDT 24
Peak memory 221956 kb
Host smart-c7252c3b-be73-4c82-b4c3-3546d4954d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261666063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.3261666063
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.3362717632
Short name T439
Test name
Test status
Simulation time 1592308357 ps
CPU time 13.87 seconds
Started Jun 09 01:33:47 PM PDT 24
Finished Jun 09 01:34:01 PM PDT 24
Peak memory 218936 kb
Host smart-ab80f1a0-78af-4901-964d-8b9921ba3fef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362717632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.3362717632
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3519724641
Short name T246
Test name
Test status
Simulation time 321630535 ps
CPU time 11.15 seconds
Started Jun 09 01:33:45 PM PDT 24
Finished Jun 09 01:33:57 PM PDT 24
Peak memory 218272 kb
Host smart-3e88f446-a76b-46aa-a3d3-d4e89b12cfd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519724641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3519724641
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.199090476
Short name T19
Test name
Test status
Simulation time 1575918645 ps
CPU time 8.68 seconds
Started Jun 09 01:33:47 PM PDT 24
Finished Jun 09 01:33:56 PM PDT 24
Peak memory 218268 kb
Host smart-9568a0c2-1974-428a-ac8c-534fbcb99c9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199090476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.199090476
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.837100983
Short name T69
Test name
Test status
Simulation time 154985487 ps
CPU time 3.34 seconds
Started Jun 09 01:33:45 PM PDT 24
Finished Jun 09 01:33:49 PM PDT 24
Peak memory 217784 kb
Host smart-8dd63098-a64a-469e-b426-e9f20d513e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837100983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.837100983
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.927051835
Short name T313
Test name
Test status
Simulation time 340973432 ps
CPU time 20.81 seconds
Started Jun 09 01:33:44 PM PDT 24
Finished Jun 09 01:34:05 PM PDT 24
Peak memory 250900 kb
Host smart-fa3d7b06-a83b-43d2-8e06-833b83917685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927051835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.927051835
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.833321396
Short name T471
Test name
Test status
Simulation time 166803419 ps
CPU time 8.3 seconds
Started Jun 09 01:33:44 PM PDT 24
Finished Jun 09 01:33:53 PM PDT 24
Peak memory 250916 kb
Host smart-d03bd8ba-75ec-4e83-ba8a-ff872e2a7d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833321396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.833321396
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.2384622567
Short name T25
Test name
Test status
Simulation time 3010845761 ps
CPU time 129.69 seconds
Started Jun 09 01:33:44 PM PDT 24
Finished Jun 09 01:35:54 PM PDT 24
Peak memory 250944 kb
Host smart-0e131a48-0452-421f-931b-5f1c92b59809
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384622567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.2384622567
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.337587788
Short name T724
Test name
Test status
Simulation time 112211071 ps
CPU time 1.03 seconds
Started Jun 09 01:33:44 PM PDT 24
Finished Jun 09 01:33:46 PM PDT 24
Peak memory 217760 kb
Host smart-8ba4614f-cdae-4a3e-ae9d-5315d031c126
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337587788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ct
rl_volatile_unlock_smoke.337587788
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3455703328
Short name T845
Test name
Test status
Simulation time 22728033 ps
CPU time 1.3 seconds
Started Jun 09 01:33:51 PM PDT 24
Finished Jun 09 01:33:53 PM PDT 24
Peak memory 208992 kb
Host smart-036d931c-84dd-4740-9e2b-3f5f4619e2a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455703328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3455703328
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.3800667821
Short name T38
Test name
Test status
Simulation time 237178712 ps
CPU time 12.03 seconds
Started Jun 09 01:33:49 PM PDT 24
Finished Jun 09 01:34:01 PM PDT 24
Peak memory 218324 kb
Host smart-5061d401-edef-4cd9-970b-a11bd11e1f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800667821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3800667821
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.2489829354
Short name T788
Test name
Test status
Simulation time 176554606 ps
CPU time 5.12 seconds
Started Jun 09 01:33:52 PM PDT 24
Finished Jun 09 01:33:57 PM PDT 24
Peak memory 217396 kb
Host smart-e0a49605-7a55-4799-92cc-fce28018538f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489829354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.2489829354
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3623072379
Short name T318
Test name
Test status
Simulation time 38251979 ps
CPU time 2.51 seconds
Started Jun 09 01:33:52 PM PDT 24
Finished Jun 09 01:33:55 PM PDT 24
Peak memory 222108 kb
Host smart-35547e7a-87a0-4bc4-8df8-6c59991e1762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623072379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3623072379
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.19012476
Short name T636
Test name
Test status
Simulation time 2047843666 ps
CPU time 16.89 seconds
Started Jun 09 01:33:53 PM PDT 24
Finished Jun 09 01:34:10 PM PDT 24
Peak memory 218916 kb
Host smart-002293bd-8023-492b-a34b-bd308ae3754d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19012476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.19012476
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.723015797
Short name T419
Test name
Test status
Simulation time 426002773 ps
CPU time 10.89 seconds
Started Jun 09 01:33:48 PM PDT 24
Finished Jun 09 01:33:59 PM PDT 24
Peak memory 218284 kb
Host smart-26861c2b-7228-4fb4-8258-68b86653be66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723015797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_di
gest.723015797
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.2888411089
Short name T839
Test name
Test status
Simulation time 2941226258 ps
CPU time 7.59 seconds
Started Jun 09 01:33:51 PM PDT 24
Finished Jun 09 01:33:59 PM PDT 24
Peak memory 226204 kb
Host smart-e90194ed-164d-4c77-8ef9-63cb600dd9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888411089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.2888411089
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.425120571
Short name T55
Test name
Test status
Simulation time 70822343 ps
CPU time 4.31 seconds
Started Jun 09 01:33:47 PM PDT 24
Finished Jun 09 01:33:51 PM PDT 24
Peak memory 214252 kb
Host smart-f9b961ed-b725-4653-ae2c-f8aab4d762da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425120571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.425120571
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3581408175
Short name T223
Test name
Test status
Simulation time 1003092663 ps
CPU time 18.71 seconds
Started Jun 09 01:33:47 PM PDT 24
Finished Jun 09 01:34:06 PM PDT 24
Peak memory 250888 kb
Host smart-e851380b-af29-4081-b1a3-f11a78e23c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581408175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3581408175
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.1071791535
Short name T277
Test name
Test status
Simulation time 235586255 ps
CPU time 3.24 seconds
Started Jun 09 01:33:44 PM PDT 24
Finished Jun 09 01:33:47 PM PDT 24
Peak memory 218248 kb
Host smart-8d0c7e3a-990f-4999-91cf-6cc7758850d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071791535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1071791535
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.3260363753
Short name T726
Test name
Test status
Simulation time 47160054356 ps
CPU time 136.21 seconds
Started Jun 09 01:33:50 PM PDT 24
Finished Jun 09 01:36:07 PM PDT 24
Peak memory 250908 kb
Host smart-ba0b9aac-dfdf-47ef-bb34-5ab7a125447a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260363753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.3260363753
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1099653763
Short name T748
Test name
Test status
Simulation time 21378037 ps
CPU time 0.97 seconds
Started Jun 09 01:33:45 PM PDT 24
Finished Jun 09 01:33:46 PM PDT 24
Peak memory 211892 kb
Host smart-d40df282-8c0e-449c-8b79-232c7885adff
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099653763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.1099653763
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.3797891556
Short name T680
Test name
Test status
Simulation time 709886913 ps
CPU time 14.39 seconds
Started Jun 09 01:33:51 PM PDT 24
Finished Jun 09 01:34:06 PM PDT 24
Peak memory 218172 kb
Host smart-3f2cde1a-ac36-466f-bb70-a187f9afe134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797891556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.3797891556
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.278321320
Short name T765
Test name
Test status
Simulation time 80160019 ps
CPU time 1.79 seconds
Started Jun 09 01:33:51 PM PDT 24
Finished Jun 09 01:33:53 PM PDT 24
Peak memory 217084 kb
Host smart-5b2a3fcb-b150-4167-ab43-5f93cc35fed1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278321320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.278321320
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.318530244
Short name T702
Test name
Test status
Simulation time 283920368 ps
CPU time 3.31 seconds
Started Jun 09 01:33:52 PM PDT 24
Finished Jun 09 01:33:56 PM PDT 24
Peak memory 218236 kb
Host smart-ee0773bc-8625-4270-b625-04a7590fc57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318530244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.318530244
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.2546908269
Short name T480
Test name
Test status
Simulation time 767200857 ps
CPU time 10.32 seconds
Started Jun 09 01:33:50 PM PDT 24
Finished Jun 09 01:34:01 PM PDT 24
Peak memory 225584 kb
Host smart-0cd05d1e-2583-4caf-ba75-26e85e13f928
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546908269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.2546908269
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.2861120858
Short name T251
Test name
Test status
Simulation time 189229924 ps
CPU time 7.37 seconds
Started Jun 09 01:33:51 PM PDT 24
Finished Jun 09 01:33:59 PM PDT 24
Peak memory 218240 kb
Host smart-97c67aa0-e478-452b-8eb5-23ccaec19aef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861120858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.2861120858
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2354751243
Short name T268
Test name
Test status
Simulation time 1028888495 ps
CPU time 9.48 seconds
Started Jun 09 01:33:50 PM PDT 24
Finished Jun 09 01:33:59 PM PDT 24
Peak memory 226084 kb
Host smart-7677fa1b-effa-430e-aa3e-15481b62ab35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354751243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2354751243
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.4203349931
Short name T319
Test name
Test status
Simulation time 2312634394 ps
CPU time 11.11 seconds
Started Jun 09 01:33:52 PM PDT 24
Finished Jun 09 01:34:04 PM PDT 24
Peak memory 218404 kb
Host smart-fdae0aa0-4117-4b78-9d58-09225025462b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203349931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.4203349931
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2493583705
Short name T346
Test name
Test status
Simulation time 284488632 ps
CPU time 1.4 seconds
Started Jun 09 01:33:49 PM PDT 24
Finished Jun 09 01:33:51 PM PDT 24
Peak memory 217760 kb
Host smart-8321c5dc-161c-4e93-b5c7-ce64e98c11fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493583705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2493583705
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.2259694566
Short name T831
Test name
Test status
Simulation time 308736893 ps
CPU time 21.54 seconds
Started Jun 09 01:33:50 PM PDT 24
Finished Jun 09 01:34:12 PM PDT 24
Peak memory 250928 kb
Host smart-f8ce75c2-9e47-4e2c-a0d3-e6bf2c6b6713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259694566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.2259694566
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3623813832
Short name T337
Test name
Test status
Simulation time 104190701 ps
CPU time 6.81 seconds
Started Jun 09 01:33:50 PM PDT 24
Finished Jun 09 01:33:57 PM PDT 24
Peak memory 250704 kb
Host smart-4f5f5ea8-fedb-426f-bc44-93d6cd2471fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623813832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3623813832
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.590354201
Short name T390
Test name
Test status
Simulation time 1260696180 ps
CPU time 45.95 seconds
Started Jun 09 01:33:55 PM PDT 24
Finished Jun 09 01:34:42 PM PDT 24
Peak memory 270836 kb
Host smart-8835eb38-be34-482b-8927-6a42a80d61f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590354201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.590354201
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2632994264
Short name T96
Test name
Test status
Simulation time 121340816 ps
CPU time 0.96 seconds
Started Jun 09 01:33:51 PM PDT 24
Finished Jun 09 01:33:52 PM PDT 24
Peak memory 211992 kb
Host smart-4313be8e-795b-4a93-b213-577635ca2975
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632994264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2632994264
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1057004507
Short name T299
Test name
Test status
Simulation time 77664537 ps
CPU time 1.16 seconds
Started Jun 09 01:34:01 PM PDT 24
Finished Jun 09 01:34:02 PM PDT 24
Peak memory 208976 kb
Host smart-a070f9d2-9c92-4e99-95fe-314d74d7f5cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057004507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1057004507
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1078783128
Short name T264
Test name
Test status
Simulation time 5984077939 ps
CPU time 13.27 seconds
Started Jun 09 01:33:56 PM PDT 24
Finished Jun 09 01:34:10 PM PDT 24
Peak memory 218616 kb
Host smart-9c0dcb34-0a66-40c0-a9e1-0b55454e0860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078783128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1078783128
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.1045124706
Short name T738
Test name
Test status
Simulation time 4508891344 ps
CPU time 25.73 seconds
Started Jun 09 01:33:57 PM PDT 24
Finished Jun 09 01:34:23 PM PDT 24
Peak memory 217796 kb
Host smart-312bc4e6-7f63-49ce-83c7-0c0dd184ab05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045124706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.1045124706
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.3410325092
Short name T875
Test name
Test status
Simulation time 113743256 ps
CPU time 2.04 seconds
Started Jun 09 01:33:55 PM PDT 24
Finished Jun 09 01:33:57 PM PDT 24
Peak memory 218216 kb
Host smart-71138bec-fd3c-496b-a6dc-bc256c4c1ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410325092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3410325092
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.223319381
Short name T602
Test name
Test status
Simulation time 397347087 ps
CPU time 16.31 seconds
Started Jun 09 01:33:56 PM PDT 24
Finished Jun 09 01:34:12 PM PDT 24
Peak memory 226088 kb
Host smart-06e083c1-047a-4658-bb8e-07c6d7d94baa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223319381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.223319381
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.2880772396
Short name T478
Test name
Test status
Simulation time 3135812381 ps
CPU time 20.1 seconds
Started Jun 09 01:33:55 PM PDT 24
Finished Jun 09 01:34:15 PM PDT 24
Peak memory 219000 kb
Host smart-47e88c10-3273-4cd6-a138-bda4c4773458
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880772396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.2880772396
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.2443999733
Short name T757
Test name
Test status
Simulation time 625447346 ps
CPU time 21.26 seconds
Started Jun 09 01:33:55 PM PDT 24
Finished Jun 09 01:34:16 PM PDT 24
Peak memory 226088 kb
Host smart-781b4df5-9eec-4aca-bba3-cfb9cfa41001
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443999733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
2443999733
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.330301090
Short name T682
Test name
Test status
Simulation time 1536725814 ps
CPU time 10.72 seconds
Started Jun 09 01:33:55 PM PDT 24
Finished Jun 09 01:34:06 PM PDT 24
Peak memory 218356 kb
Host smart-c7c1be2e-15df-4fc3-a5f0-0e41e14bfcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330301090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.330301090
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.4184587842
Short name T826
Test name
Test status
Simulation time 215476204 ps
CPU time 3.03 seconds
Started Jun 09 01:33:54 PM PDT 24
Finished Jun 09 01:33:57 PM PDT 24
Peak memory 217944 kb
Host smart-1cb019d2-56df-4f1b-a552-5ba05fb6e0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184587842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.4184587842
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3833166608
Short name T617
Test name
Test status
Simulation time 634826174 ps
CPU time 18.96 seconds
Started Jun 09 01:33:57 PM PDT 24
Finished Jun 09 01:34:16 PM PDT 24
Peak memory 250932 kb
Host smart-e65040cf-8a4c-42b1-8ad4-01c78abf81e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833166608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3833166608
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3309558659
Short name T807
Test name
Test status
Simulation time 614297110 ps
CPU time 6.25 seconds
Started Jun 09 01:33:55 PM PDT 24
Finished Jun 09 01:34:01 PM PDT 24
Peak memory 246320 kb
Host smart-2e4cbf0f-91f4-4f37-96d8-8592f0309264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309558659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3309558659
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3551369204
Short name T209
Test name
Test status
Simulation time 11607098 ps
CPU time 0.89 seconds
Started Jun 09 01:33:58 PM PDT 24
Finished Jun 09 01:33:59 PM PDT 24
Peak memory 211932 kb
Host smart-911bbdbb-2f8c-4a8f-b6e7-5c3368466da1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551369204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3551369204
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.2390249793
Short name T396
Test name
Test status
Simulation time 68481291 ps
CPU time 1.11 seconds
Started Jun 09 01:34:09 PM PDT 24
Finished Jun 09 01:34:10 PM PDT 24
Peak memory 208952 kb
Host smart-1d8ce263-e4f5-42d2-8be2-f477219c1266
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390249793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.2390249793
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3911977205
Short name T39
Test name
Test status
Simulation time 917636439 ps
CPU time 10.03 seconds
Started Jun 09 01:34:00 PM PDT 24
Finished Jun 09 01:34:11 PM PDT 24
Peak memory 218276 kb
Host smart-63e7c56b-8157-403a-ae3c-9ac98fe8e9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911977205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3911977205
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.3479669187
Short name T10
Test name
Test status
Simulation time 404643792 ps
CPU time 3.07 seconds
Started Jun 09 01:34:00 PM PDT 24
Finished Jun 09 01:34:03 PM PDT 24
Peak memory 217136 kb
Host smart-07aef030-1ef2-4c8d-b344-abf03d88f768
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479669187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.3479669187
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.579572389
Short name T241
Test name
Test status
Simulation time 196502815 ps
CPU time 2.18 seconds
Started Jun 09 01:34:01 PM PDT 24
Finished Jun 09 01:34:03 PM PDT 24
Peak memory 222172 kb
Host smart-b1c8e265-1ae0-4d8c-99cf-b82683d7bf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579572389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.579572389
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.3837508433
Short name T305
Test name
Test status
Simulation time 1896123757 ps
CPU time 17.85 seconds
Started Jun 09 01:33:59 PM PDT 24
Finished Jun 09 01:34:17 PM PDT 24
Peak memory 218936 kb
Host smart-ed21be98-36a6-4cbe-9cc1-e83c66194c1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837508433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.3837508433
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.4220825373
Short name T161
Test name
Test status
Simulation time 169126270 ps
CPU time 8.62 seconds
Started Jun 09 01:33:59 PM PDT 24
Finished Jun 09 01:34:08 PM PDT 24
Peak memory 225868 kb
Host smart-fbbd59d6-b71f-4555-b428-bfd6427fa9fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220825373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.4220825373
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.964555134
Short name T368
Test name
Test status
Simulation time 1214364492 ps
CPU time 8.94 seconds
Started Jun 09 01:34:03 PM PDT 24
Finished Jun 09 01:34:12 PM PDT 24
Peak memory 218184 kb
Host smart-7724a93a-e464-48e0-828c-fce1148157d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964555134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.964555134
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.688249041
Short name T283
Test name
Test status
Simulation time 2184964852 ps
CPU time 10.35 seconds
Started Jun 09 01:34:02 PM PDT 24
Finished Jun 09 01:34:13 PM PDT 24
Peak memory 226128 kb
Host smart-79f2f6f9-cd56-4b5f-9da7-79d1d50244be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688249041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.688249041
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.2269265030
Short name T718
Test name
Test status
Simulation time 144199471 ps
CPU time 2.77 seconds
Started Jun 09 01:34:02 PM PDT 24
Finished Jun 09 01:34:05 PM PDT 24
Peak memory 217756 kb
Host smart-9ea2c8be-b2f1-45cf-8c2b-3de208894317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269265030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.2269265030
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.220993983
Short name T286
Test name
Test status
Simulation time 1383366964 ps
CPU time 27.02 seconds
Started Jun 09 01:34:00 PM PDT 24
Finished Jun 09 01:34:27 PM PDT 24
Peak memory 250992 kb
Host smart-af8539df-6ba2-4e72-9aed-955d76d84a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220993983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.220993983
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1964180259
Short name T622
Test name
Test status
Simulation time 75752816 ps
CPU time 6.37 seconds
Started Jun 09 01:34:03 PM PDT 24
Finished Jun 09 01:34:09 PM PDT 24
Peak memory 250404 kb
Host smart-051bdd88-78d5-4168-a6e7-cc85b5068ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964180259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1964180259
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2346496471
Short name T872
Test name
Test status
Simulation time 8110494954 ps
CPU time 80.62 seconds
Started Jun 09 01:33:59 PM PDT 24
Finished Jun 09 01:35:20 PM PDT 24
Peak memory 250948 kb
Host smart-5b8ddeb9-0c29-4b22-b56f-4da61090ca69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346496471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2346496471
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1359257535
Short name T561
Test name
Test status
Simulation time 82901847 ps
CPU time 0.98 seconds
Started Jun 09 01:34:00 PM PDT 24
Finished Jun 09 01:34:01 PM PDT 24
Peak memory 212944 kb
Host smart-cd896510-d8cf-4425-a44f-fc66e17e4327
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359257535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1359257535
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.2782158252
Short name T671
Test name
Test status
Simulation time 38207074 ps
CPU time 0.93 seconds
Started Jun 09 01:29:54 PM PDT 24
Finished Jun 09 01:29:56 PM PDT 24
Peak memory 209032 kb
Host smart-53005606-d518-4e8c-bc31-f5c381e70e2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782158252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.2782158252
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.509973597
Short name T645
Test name
Test status
Simulation time 1117905288 ps
CPU time 23.06 seconds
Started Jun 09 01:29:43 PM PDT 24
Finished Jun 09 01:30:07 PM PDT 24
Peak memory 218300 kb
Host smart-d6df9c1f-7adb-4b3d-9f10-e985a7ada403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509973597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.509973597
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.1534319888
Short name T713
Test name
Test status
Simulation time 1369504894 ps
CPU time 16.63 seconds
Started Jun 09 01:29:46 PM PDT 24
Finished Jun 09 01:30:03 PM PDT 24
Peak memory 217232 kb
Host smart-82b4b31e-1c55-4477-b586-9f59a3d44351
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534319888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.1534319888
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.490308247
Short name T381
Test name
Test status
Simulation time 3374545130 ps
CPU time 30.17 seconds
Started Jun 09 01:29:49 PM PDT 24
Finished Jun 09 01:30:20 PM PDT 24
Peak memory 219052 kb
Host smart-2f1eb964-88c3-4689-b997-6d19f63895ca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490308247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.490308247
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.3319812775
Short name T626
Test name
Test status
Simulation time 325381136 ps
CPU time 8.66 seconds
Started Jun 09 01:29:47 PM PDT 24
Finished Jun 09 01:29:56 PM PDT 24
Peak memory 217832 kb
Host smart-97d3fdee-dc4b-42fd-a1f7-44009cd591ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319812775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.3
319812775
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.2134907869
Short name T473
Test name
Test status
Simulation time 166370696 ps
CPU time 3.64 seconds
Started Jun 09 01:29:45 PM PDT 24
Finished Jun 09 01:29:49 PM PDT 24
Peak memory 222804 kb
Host smart-740602bc-757a-44c9-aff3-902397ea4a2d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134907869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.2134907869
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1205753849
Short name T98
Test name
Test status
Simulation time 1181602551 ps
CPU time 20.37 seconds
Started Jun 09 01:29:54 PM PDT 24
Finished Jun 09 01:30:14 PM PDT 24
Peak memory 217732 kb
Host smart-9c853752-a9c6-4f3e-a458-b973d1360690
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205753849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.1205753849
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3901679842
Short name T66
Test name
Test status
Simulation time 3465747589 ps
CPU time 20.98 seconds
Started Jun 09 01:29:46 PM PDT 24
Finished Jun 09 01:30:08 PM PDT 24
Peak memory 217748 kb
Host smart-411ba3e0-12ce-4697-8a4a-b961084166bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901679842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3901679842
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3083921409
Short name T339
Test name
Test status
Simulation time 3881480393 ps
CPU time 51 seconds
Started Jun 09 01:29:46 PM PDT 24
Finished Jun 09 01:30:38 PM PDT 24
Peak memory 276480 kb
Host smart-87e227c7-6168-490d-b818-a2a051dc4977
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083921409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3083921409
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.297023881
Short name T751
Test name
Test status
Simulation time 408678031 ps
CPU time 13.18 seconds
Started Jun 09 01:29:47 PM PDT 24
Finished Jun 09 01:30:01 PM PDT 24
Peak memory 250848 kb
Host smart-85997fb7-df7b-437c-bc01-9b6e78086669
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297023881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_state_post_trans.297023881
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.2674602768
Short name T481
Test name
Test status
Simulation time 111268308 ps
CPU time 2.64 seconds
Started Jun 09 01:29:45 PM PDT 24
Finished Jun 09 01:29:48 PM PDT 24
Peak memory 218216 kb
Host smart-fb035795-2d79-41ce-b523-3c464dd1c1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674602768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.2674602768
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.2142236148
Short name T582
Test name
Test status
Simulation time 320918996 ps
CPU time 11.21 seconds
Started Jun 09 01:29:47 PM PDT 24
Finished Jun 09 01:29:58 PM PDT 24
Peak memory 217772 kb
Host smart-24e32164-63d7-4368-894d-1875527f9e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142236148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2142236148
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2828134049
Short name T272
Test name
Test status
Simulation time 1087956082 ps
CPU time 8.81 seconds
Started Jun 09 01:29:54 PM PDT 24
Finished Jun 09 01:30:03 PM PDT 24
Peak memory 226084 kb
Host smart-966f2848-4994-4352-910b-29dabd00fcc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828134049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2828134049
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.990559616
Short name T441
Test name
Test status
Simulation time 771138201 ps
CPU time 16.64 seconds
Started Jun 09 01:29:52 PM PDT 24
Finished Jun 09 01:30:09 PM PDT 24
Peak memory 218456 kb
Host smart-e5cc3143-fa51-4a4d-a009-9dea8bcf7c74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990559616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dig
est.990559616
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.4180560709
Short name T327
Test name
Test status
Simulation time 255836639 ps
CPU time 10.26 seconds
Started Jun 09 01:29:52 PM PDT 24
Finished Jun 09 01:30:03 PM PDT 24
Peak memory 218276 kb
Host smart-0482cba0-1c0e-40f0-a789-cb4d08c7e0cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180560709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.4
180560709
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.4255544610
Short name T332
Test name
Test status
Simulation time 250716928 ps
CPU time 7.6 seconds
Started Jun 09 01:29:42 PM PDT 24
Finished Jun 09 01:29:50 PM PDT 24
Peak memory 218204 kb
Host smart-09b033e1-a2ae-44df-a668-59a4ea8ac7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255544610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.4255544610
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.498863597
Short name T595
Test name
Test status
Simulation time 457651694 ps
CPU time 17.89 seconds
Started Jun 09 01:29:47 PM PDT 24
Finished Jun 09 01:30:06 PM PDT 24
Peak memory 250912 kb
Host smart-eb2a79b1-fb61-44ce-9ee1-107b3c9a5b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498863597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.498863597
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.378906571
Short name T618
Test name
Test status
Simulation time 57064406 ps
CPU time 8.15 seconds
Started Jun 09 01:29:43 PM PDT 24
Finished Jun 09 01:29:51 PM PDT 24
Peak memory 250900 kb
Host smart-34b41b22-a893-4c55-b1a7-658d3e863890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378906571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.378906571
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.4156384023
Short name T76
Test name
Test status
Simulation time 5282122487 ps
CPU time 82.71 seconds
Started Jun 09 01:29:56 PM PDT 24
Finished Jun 09 01:31:19 PM PDT 24
Peak memory 251452 kb
Host smart-962806b2-d327-4361-80d2-109e7001e117
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156384023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.4156384023
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.37538323
Short name T852
Test name
Test status
Simulation time 14241620 ps
CPU time 1.11 seconds
Started Jun 09 01:29:45 PM PDT 24
Finished Jun 09 01:29:46 PM PDT 24
Peak memory 211896 kb
Host smart-9eb7bee7-fb4a-4edf-bea9-063c9bc1a858
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37538323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_volatile_unlock_smoke.37538323
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.1785238975
Short name T479
Test name
Test status
Simulation time 21219960 ps
CPU time 0.98 seconds
Started Jun 09 01:30:04 PM PDT 24
Finished Jun 09 01:30:05 PM PDT 24
Peak memory 209060 kb
Host smart-8f146c28-be04-489d-af2f-444612f271ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785238975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1785238975
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.714032818
Short name T438
Test name
Test status
Simulation time 246688065 ps
CPU time 9.68 seconds
Started Jun 09 01:29:55 PM PDT 24
Finished Jun 09 01:30:05 PM PDT 24
Peak memory 218328 kb
Host smart-686c485d-a990-448d-86c5-fbe64c6a2e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714032818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.714032818
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1556327223
Short name T535
Test name
Test status
Simulation time 111751973 ps
CPU time 1.15 seconds
Started Jun 09 01:29:59 PM PDT 24
Finished Jun 09 01:30:00 PM PDT 24
Peak memory 217172 kb
Host smart-632c026e-66f7-4725-b2ab-9ca7cef69ab6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556327223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1556327223
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.435580882
Short name T791
Test name
Test status
Simulation time 10332241964 ps
CPU time 58.77 seconds
Started Jun 09 01:29:58 PM PDT 24
Finished Jun 09 01:30:57 PM PDT 24
Peak memory 226072 kb
Host smart-9cedfab3-b9d2-4cf8-b806-55de03edd1a1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435580882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_err
ors.435580882
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1905366050
Short name T393
Test name
Test status
Simulation time 1238814392 ps
CPU time 8.11 seconds
Started Jun 09 01:29:58 PM PDT 24
Finished Jun 09 01:30:07 PM PDT 24
Peak memory 217600 kb
Host smart-f5c33724-c5e1-4f74-8906-fe9b14eb6ba7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905366050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
905366050
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.1873711396
Short name T780
Test name
Test status
Simulation time 681751768 ps
CPU time 9.87 seconds
Started Jun 09 01:29:58 PM PDT 24
Finished Jun 09 01:30:08 PM PDT 24
Peak memory 222924 kb
Host smart-b002a8a0-2ca2-410b-936f-1dc27a049efe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873711396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.1873711396
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.67270353
Short name T490
Test name
Test status
Simulation time 4585571895 ps
CPU time 16.74 seconds
Started Jun 09 01:29:57 PM PDT 24
Finished Jun 09 01:30:14 PM PDT 24
Peak memory 217752 kb
Host smart-6d1cf424-7915-4693-8638-3c6441ee6009
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67270353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jt
ag_regwen_during_op.67270353
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.518338548
Short name T250
Test name
Test status
Simulation time 154051532 ps
CPU time 3.46 seconds
Started Jun 09 01:29:57 PM PDT 24
Finished Jun 09 01:30:00 PM PDT 24
Peak memory 217684 kb
Host smart-b81ddbae-37ec-4abf-a83d-106d711d7c4b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518338548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.518338548
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.289934734
Short name T570
Test name
Test status
Simulation time 4436604620 ps
CPU time 46.08 seconds
Started Jun 09 01:29:58 PM PDT 24
Finished Jun 09 01:30:44 PM PDT 24
Peak memory 251088 kb
Host smart-5d0a9540-8e69-4f0e-99b3-ee7fa370b20f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289934734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_state_failure.289934734
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3052767974
Short name T489
Test name
Test status
Simulation time 2871424208 ps
CPU time 12.63 seconds
Started Jun 09 01:29:59 PM PDT 24
Finished Jun 09 01:30:12 PM PDT 24
Peak memory 250368 kb
Host smart-929c2cd5-6631-40dd-ad4c-41664fc561c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052767974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.3052767974
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3285591321
Short name T790
Test name
Test status
Simulation time 86902406 ps
CPU time 1.78 seconds
Started Jun 09 01:29:53 PM PDT 24
Finished Jun 09 01:29:55 PM PDT 24
Peak memory 221960 kb
Host smart-579f8c43-35eb-4454-96c6-c17b0c815960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285591321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3285591321
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2537554636
Short name T644
Test name
Test status
Simulation time 659079602 ps
CPU time 12.83 seconds
Started Jun 09 01:29:59 PM PDT 24
Finished Jun 09 01:30:12 PM PDT 24
Peak memory 214664 kb
Host smart-efb6682a-b163-4b0d-9477-fc222d59e449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537554636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2537554636
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.1538461145
Short name T834
Test name
Test status
Simulation time 652376639 ps
CPU time 15.61 seconds
Started Jun 09 01:29:57 PM PDT 24
Finished Jun 09 01:30:13 PM PDT 24
Peak memory 219020 kb
Host smart-442a2ab4-16a8-4b1c-a244-dfbf89d63541
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538461145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1538461145
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1904684875
Short name T579
Test name
Test status
Simulation time 6010315933 ps
CPU time 13.1 seconds
Started Jun 09 01:30:01 PM PDT 24
Finished Jun 09 01:30:14 PM PDT 24
Peak memory 226332 kb
Host smart-956eb8a6-009e-4b0a-bc2d-4083cbf3e2d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904684875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.1904684875
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.593694103
Short name T392
Test name
Test status
Simulation time 225973556 ps
CPU time 7.86 seconds
Started Jun 09 01:30:04 PM PDT 24
Finished Jun 09 01:30:12 PM PDT 24
Peak memory 226084 kb
Host smart-93ca5656-df00-4809-9fd1-d8cfabb610a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593694103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.593694103
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.3599597168
Short name T285
Test name
Test status
Simulation time 1121436772 ps
CPU time 8.96 seconds
Started Jun 09 01:29:58 PM PDT 24
Finished Jun 09 01:30:08 PM PDT 24
Peak memory 218360 kb
Host smart-422880c2-c365-4b46-a1e7-1dcfa1660fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599597168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3599597168
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.857252390
Short name T719
Test name
Test status
Simulation time 203188346 ps
CPU time 2.39 seconds
Started Jun 09 01:29:54 PM PDT 24
Finished Jun 09 01:29:56 PM PDT 24
Peak memory 214500 kb
Host smart-ab80c059-265d-484e-af82-45f2b9255f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857252390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.857252390
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.1680816952
Short name T358
Test name
Test status
Simulation time 426877215 ps
CPU time 24.05 seconds
Started Jun 09 01:29:53 PM PDT 24
Finished Jun 09 01:30:17 PM PDT 24
Peak memory 251000 kb
Host smart-a16a512f-4fd0-4429-8d10-ee30707bd922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680816952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1680816952
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.32995546
Short name T4
Test name
Test status
Simulation time 1837480990 ps
CPU time 3.73 seconds
Started Jun 09 01:29:53 PM PDT 24
Finished Jun 09 01:29:57 PM PDT 24
Peak memory 226348 kb
Host smart-3639bbdb-b59c-4ac8-ae2c-408d8ddfe901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32995546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.32995546
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.551743325
Short name T40
Test name
Test status
Simulation time 38796244314 ps
CPU time 236.45 seconds
Started Jun 09 01:30:04 PM PDT 24
Finished Jun 09 01:34:01 PM PDT 24
Peak memory 283708 kb
Host smart-3dae285c-7ac2-46a2-9756-b11c7b73240b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551743325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.551743325
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.1986585388
Short name T146
Test name
Test status
Simulation time 34293933656 ps
CPU time 266.07 seconds
Started Jun 09 01:30:04 PM PDT 24
Finished Jun 09 01:34:30 PM PDT 24
Peak memory 333020 kb
Host smart-a126e74c-a066-44ad-9b38-32ccd5ba7ffb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1986585388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.1986585388
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.27213547
Short name T532
Test name
Test status
Simulation time 48623683 ps
CPU time 1.05 seconds
Started Jun 09 01:29:54 PM PDT 24
Finished Jun 09 01:29:55 PM PDT 24
Peak memory 212940 kb
Host smart-ee2460a0-8ee2-4f25-8c95-0ba54a98f102
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27213547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_volatile_unlock_smoke.27213547
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.282264527
Short name T324
Test name
Test status
Simulation time 81456511 ps
CPU time 0.92 seconds
Started Jun 09 01:30:15 PM PDT 24
Finished Jun 09 01:30:16 PM PDT 24
Peak memory 209032 kb
Host smart-bd8c98f2-e5c1-4c65-bf4d-c66b977a9da5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282264527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.282264527
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1930721732
Short name T870
Test name
Test status
Simulation time 12660861 ps
CPU time 0.83 seconds
Started Jun 09 01:30:09 PM PDT 24
Finished Jun 09 01:30:10 PM PDT 24
Peak memory 208828 kb
Host smart-d86ae3d2-e67a-4ea7-a7a7-efea97b1ea5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930721732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1930721732
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.510906497
Short name T577
Test name
Test status
Simulation time 1748302317 ps
CPU time 14.86 seconds
Started Jun 09 01:30:04 PM PDT 24
Finished Jun 09 01:30:19 PM PDT 24
Peak memory 218228 kb
Host smart-2400db4e-0270-4d86-9498-857a1a9dcb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510906497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.510906497
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.3637444342
Short name T61
Test name
Test status
Simulation time 117248194 ps
CPU time 2.28 seconds
Started Jun 09 01:30:08 PM PDT 24
Finished Jun 09 01:30:11 PM PDT 24
Peak memory 217100 kb
Host smart-2d35cb3a-6b67-4c9b-a039-1425be620f25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637444342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.3637444342
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.227871041
Short name T459
Test name
Test status
Simulation time 9815790016 ps
CPU time 36.1 seconds
Started Jun 09 01:30:09 PM PDT 24
Finished Jun 09 01:30:45 PM PDT 24
Peak memory 218904 kb
Host smart-f23dc33a-15e0-4e59-b288-07c45f740be8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227871041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_err
ors.227871041
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.3593690001
Short name T553
Test name
Test status
Simulation time 227719494 ps
CPU time 6.47 seconds
Started Jun 09 01:30:09 PM PDT 24
Finished Jun 09 01:30:15 PM PDT 24
Peak memory 217668 kb
Host smart-4c578685-6d51-40a4-b971-a9a744807980
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593690001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.3
593690001
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.3472701495
Short name T619
Test name
Test status
Simulation time 193999898 ps
CPU time 3.84 seconds
Started Jun 09 01:30:09 PM PDT 24
Finished Jun 09 01:30:13 PM PDT 24
Peak memory 221768 kb
Host smart-d4b2abe8-189a-4476-a90d-2aaa0a48bc20
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472701495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.3472701495
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2078770040
Short name T495
Test name
Test status
Simulation time 1545403238 ps
CPU time 13.66 seconds
Started Jun 09 01:30:11 PM PDT 24
Finished Jun 09 01:30:25 PM PDT 24
Peak memory 217708 kb
Host smart-1c8c755c-9d41-47eb-90ee-73748fe1b009
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078770040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.2078770040
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.2485108414
Short name T761
Test name
Test status
Simulation time 1319258453 ps
CPU time 4.4 seconds
Started Jun 09 01:30:09 PM PDT 24
Finished Jun 09 01:30:13 PM PDT 24
Peak memory 217692 kb
Host smart-a4c61d7f-7d55-4def-9ce7-d1872402c787
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485108414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
2485108414
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1417370593
Short name T499
Test name
Test status
Simulation time 2649030302 ps
CPU time 92.15 seconds
Started Jun 09 01:30:07 PM PDT 24
Finished Jun 09 01:31:40 PM PDT 24
Peak memory 270180 kb
Host smart-6605186f-1745-43c3-96cb-66f2154c1993
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417370593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1417370593
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2892562949
Short name T747
Test name
Test status
Simulation time 1092285822 ps
CPU time 13.25 seconds
Started Jun 09 01:30:08 PM PDT 24
Finished Jun 09 01:30:22 PM PDT 24
Peak memory 250860 kb
Host smart-e5a38c27-ef5f-4205-8338-2ea4e8900962
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892562949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2892562949
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.867227793
Short name T558
Test name
Test status
Simulation time 25169319 ps
CPU time 1.79 seconds
Started Jun 09 01:30:04 PM PDT 24
Finished Jun 09 01:30:06 PM PDT 24
Peak memory 222048 kb
Host smart-069c9dee-c0e8-4e56-a128-c1a0a782b443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867227793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.867227793
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.1445288970
Short name T483
Test name
Test status
Simulation time 359977921 ps
CPU time 10 seconds
Started Jun 09 01:30:09 PM PDT 24
Finished Jun 09 01:30:19 PM PDT 24
Peak memory 217768 kb
Host smart-f03871bb-faa9-44df-bf77-936120bdb398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445288970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.1445288970
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.2064561817
Short name T741
Test name
Test status
Simulation time 324055403 ps
CPU time 13.6 seconds
Started Jun 09 01:30:10 PM PDT 24
Finished Jun 09 01:30:24 PM PDT 24
Peak memory 218944 kb
Host smart-9a5bdf72-b339-4510-bdef-c7163f7400cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064561817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2064561817
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3361762084
Short name T248
Test name
Test status
Simulation time 307984751 ps
CPU time 9.76 seconds
Started Jun 09 01:30:08 PM PDT 24
Finished Jun 09 01:30:18 PM PDT 24
Peak memory 218240 kb
Host smart-c3ab3541-bf62-4b1a-bd4e-85104cacd842
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361762084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3361762084
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2752474042
Short name T760
Test name
Test status
Simulation time 647306019 ps
CPU time 8.15 seconds
Started Jun 09 01:30:10 PM PDT 24
Finished Jun 09 01:30:18 PM PDT 24
Peak memory 218272 kb
Host smart-30a0b6af-5344-4425-ac67-2a5b8593b844
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752474042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2
752474042
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.296667989
Short name T331
Test name
Test status
Simulation time 416958454 ps
CPU time 15.22 seconds
Started Jun 09 01:30:10 PM PDT 24
Finished Jun 09 01:30:25 PM PDT 24
Peak memory 218288 kb
Host smart-08c1c1a0-006f-41cd-bc42-ec69e17b5073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296667989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.296667989
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1100110433
Short name T154
Test name
Test status
Simulation time 42455101 ps
CPU time 1.36 seconds
Started Jun 09 01:30:04 PM PDT 24
Finished Jun 09 01:30:05 PM PDT 24
Peak memory 217744 kb
Host smart-f8e8b634-ae91-40e8-90c3-e7aff2c27b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100110433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1100110433
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.295467229
Short name T352
Test name
Test status
Simulation time 244456794 ps
CPU time 33.05 seconds
Started Jun 09 01:30:05 PM PDT 24
Finished Jun 09 01:30:38 PM PDT 24
Peak memory 250912 kb
Host smart-55b407be-d602-4017-99f0-d3a14e0aafb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295467229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.295467229
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.3972709531
Short name T64
Test name
Test status
Simulation time 72969248 ps
CPU time 7.75 seconds
Started Jun 09 01:30:03 PM PDT 24
Finished Jun 09 01:30:11 PM PDT 24
Peak memory 250712 kb
Host smart-995075bc-427e-44de-b4cc-bbbecd2cb555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972709531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3972709531
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.3733956338
Short name T795
Test name
Test status
Simulation time 111827742404 ps
CPU time 328.45 seconds
Started Jun 09 01:30:10 PM PDT 24
Finished Jun 09 01:35:38 PM PDT 24
Peak memory 283688 kb
Host smart-b8b5386a-f9c9-472c-ac08-e069cd81f582
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733956338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.3733956338
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.2094749098
Short name T694
Test name
Test status
Simulation time 16962640918 ps
CPU time 397.54 seconds
Started Jun 09 01:30:12 PM PDT 24
Finished Jun 09 01:36:50 PM PDT 24
Peak memory 259640 kb
Host smart-d9275cc1-3ec1-49bf-9351-93c577a67c53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2094749098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.2094749098
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3379018286
Short name T716
Test name
Test status
Simulation time 33267343 ps
CPU time 0.82 seconds
Started Jun 09 01:30:06 PM PDT 24
Finished Jun 09 01:30:07 PM PDT 24
Peak memory 211876 kb
Host smart-4839ff33-1466-432c-90f8-913badf10510
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379018286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.3379018286
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1560069816
Short name T336
Test name
Test status
Simulation time 60987867 ps
CPU time 0.83 seconds
Started Jun 09 01:30:25 PM PDT 24
Finished Jun 09 01:30:27 PM PDT 24
Peak memory 208764 kb
Host smart-14067115-2712-4355-b56d-65ac70be572b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560069816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1560069816
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.3227598202
Short name T214
Test name
Test status
Simulation time 28203785 ps
CPU time 0.87 seconds
Started Jun 09 01:30:21 PM PDT 24
Finished Jun 09 01:30:22 PM PDT 24
Peak memory 209024 kb
Host smart-e90a1545-0e6b-4704-a27b-d3cca5a74947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227598202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.3227598202
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.3241012456
Short name T823
Test name
Test status
Simulation time 907538090 ps
CPU time 19.37 seconds
Started Jun 09 01:30:19 PM PDT 24
Finished Jun 09 01:30:39 PM PDT 24
Peak memory 218240 kb
Host smart-337fdab8-d9ee-4a25-8217-4cc4e829a94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241012456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3241012456
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.3471198543
Short name T763
Test name
Test status
Simulation time 99160864 ps
CPU time 1.3 seconds
Started Jun 09 01:30:20 PM PDT 24
Finished Jun 09 01:30:22 PM PDT 24
Peak memory 217188 kb
Host smart-4b3dca02-2145-43b8-9db3-e543aef81999
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471198543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3471198543
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.3535398987
Short name T23
Test name
Test status
Simulation time 1458497890 ps
CPU time 25.88 seconds
Started Jun 09 01:30:20 PM PDT 24
Finished Jun 09 01:30:47 PM PDT 24
Peak memory 218220 kb
Host smart-dfcfc1f0-ed08-47ed-ae46-9db4361f4626
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535398987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.3535398987
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2549723978
Short name T7
Test name
Test status
Simulation time 5444838758 ps
CPU time 29.55 seconds
Started Jun 09 01:30:21 PM PDT 24
Finished Jun 09 01:30:51 PM PDT 24
Peak memory 217860 kb
Host smart-70c00c43-f4fe-4fa0-9d45-517039a56be4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549723978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
549723978
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.4079192998
Short name T621
Test name
Test status
Simulation time 332204445 ps
CPU time 3.14 seconds
Started Jun 09 01:30:19 PM PDT 24
Finished Jun 09 01:30:22 PM PDT 24
Peak memory 218108 kb
Host smart-1f14715e-c0cf-4fd6-991d-980ecd90bbaf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079192998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.4079192998
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1845124610
Short name T82
Test name
Test status
Simulation time 1126767245 ps
CPU time 26.46 seconds
Started Jun 09 01:30:22 PM PDT 24
Finished Jun 09 01:30:49 PM PDT 24
Peak memory 217688 kb
Host smart-3b2fa72e-18b9-4816-8cf6-42666c44063c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845124610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.1845124610
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2541345715
Short name T785
Test name
Test status
Simulation time 401676432 ps
CPU time 5.61 seconds
Started Jun 09 01:30:20 PM PDT 24
Finished Jun 09 01:30:25 PM PDT 24
Peak memory 217700 kb
Host smart-096ffb99-5250-4bb4-8ccc-940927982747
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541345715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2541345715
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.790670398
Short name T179
Test name
Test status
Simulation time 2308795497 ps
CPU time 32.1 seconds
Started Jun 09 01:30:21 PM PDT 24
Finished Jun 09 01:30:53 PM PDT 24
Peak memory 250896 kb
Host smart-8630b0f2-0b8c-41bd-89d5-38a2d8de8210
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790670398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_state_failure.790670398
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3477245572
Short name T249
Test name
Test status
Simulation time 937729520 ps
CPU time 11.24 seconds
Started Jun 09 01:30:20 PM PDT 24
Finished Jun 09 01:30:31 PM PDT 24
Peak memory 221896 kb
Host smart-bdc1fe87-9790-475e-82e9-529fd8cc8b85
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477245572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.3477245572
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2036518478
Short name T252
Test name
Test status
Simulation time 97474139 ps
CPU time 3.58 seconds
Started Jun 09 01:30:14 PM PDT 24
Finished Jun 09 01:30:18 PM PDT 24
Peak memory 222548 kb
Host smart-bf07bf9f-da0c-46b8-8b91-e014187c6cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036518478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2036518478
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3549482883
Short name T533
Test name
Test status
Simulation time 1010589023 ps
CPU time 8.39 seconds
Started Jun 09 01:30:18 PM PDT 24
Finished Jun 09 01:30:27 PM PDT 24
Peak memory 217844 kb
Host smart-5468af84-d2bb-4746-ba7d-aca057cf9996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549482883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3549482883
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3857950471
Short name T280
Test name
Test status
Simulation time 340899673 ps
CPU time 14.35 seconds
Started Jun 09 01:30:22 PM PDT 24
Finished Jun 09 01:30:37 PM PDT 24
Peak memory 218936 kb
Host smart-a325a146-4bc5-428f-b417-79d00a39191e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857950471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3857950471
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2045535705
Short name T563
Test name
Test status
Simulation time 3953085529 ps
CPU time 11.95 seconds
Started Jun 09 01:30:20 PM PDT 24
Finished Jun 09 01:30:32 PM PDT 24
Peak memory 226112 kb
Host smart-95279181-f3b9-46ab-a839-fd1529c420ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045535705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2045535705
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.421908468
Short name T849
Test name
Test status
Simulation time 824774770 ps
CPU time 6.91 seconds
Started Jun 09 01:30:23 PM PDT 24
Finished Jun 09 01:30:30 PM PDT 24
Peak memory 218268 kb
Host smart-a17c9988-1d2a-4e85-a62d-7aea675ac25d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421908468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.421908468
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.3414934243
Short name T817
Test name
Test status
Simulation time 930197038 ps
CPU time 7.69 seconds
Started Jun 09 01:30:20 PM PDT 24
Finished Jun 09 01:30:28 PM PDT 24
Peak memory 224948 kb
Host smart-72073f25-ca8e-46bd-b8b9-ec7005532200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414934243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3414934243
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.311785525
Short name T160
Test name
Test status
Simulation time 50973628 ps
CPU time 1.88 seconds
Started Jun 09 01:30:14 PM PDT 24
Finished Jun 09 01:30:16 PM PDT 24
Peak memory 214336 kb
Host smart-c2ae7d6e-afb6-448f-9e30-4285cc5315bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311785525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.311785525
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.2788562213
Short name T65
Test name
Test status
Simulation time 169283251 ps
CPU time 17.27 seconds
Started Jun 09 01:30:13 PM PDT 24
Finished Jun 09 01:30:30 PM PDT 24
Peak memory 250916 kb
Host smart-b189e8e9-55c1-4b3e-bfda-74c59494f652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788562213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2788562213
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.1585445763
Short name T873
Test name
Test status
Simulation time 65517974 ps
CPU time 8.19 seconds
Started Jun 09 01:30:20 PM PDT 24
Finished Jun 09 01:30:28 PM PDT 24
Peak memory 242796 kb
Host smart-baf2c933-66d4-4144-94a2-7b787f8314f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585445763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.1585445763
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3333429597
Short name T184
Test name
Test status
Simulation time 38192177694 ps
CPU time 77.35 seconds
Started Jun 09 01:30:26 PM PDT 24
Finished Jun 09 01:31:43 PM PDT 24
Peak memory 245096 kb
Host smart-a96ce87b-4671-434f-b675-29711c649357
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333429597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3333429597
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.280966591
Short name T258
Test name
Test status
Simulation time 12343725 ps
CPU time 0.98 seconds
Started Jun 09 01:30:12 PM PDT 24
Finished Jun 09 01:30:14 PM PDT 24
Peak memory 211856 kb
Host smart-54ce6f62-a8e6-4d53-8028-a98a58346bfd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280966591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr
l_volatile_unlock_smoke.280966591
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.2487216123
Short name T95
Test name
Test status
Simulation time 47509228 ps
CPU time 1.1 seconds
Started Jun 09 01:30:32 PM PDT 24
Finished Jun 09 01:30:33 PM PDT 24
Peak memory 209056 kb
Host smart-90aca9af-1123-40eb-9a19-d1dd9ce725a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487216123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.2487216123
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1452968775
Short name T34
Test name
Test status
Simulation time 382692309 ps
CPU time 13.26 seconds
Started Jun 09 01:30:25 PM PDT 24
Finished Jun 09 01:30:39 PM PDT 24
Peak memory 218236 kb
Host smart-dd35d85d-eee8-467c-887f-40d7f3805f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452968775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1452968775
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.2246316358
Short name T521
Test name
Test status
Simulation time 1477617998 ps
CPU time 6.36 seconds
Started Jun 09 01:30:31 PM PDT 24
Finished Jun 09 01:30:38 PM PDT 24
Peak memory 217172 kb
Host smart-8e30b775-0476-46ee-a813-c3c0a20f0256
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246316358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.2246316358
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1994703234
Short name T437
Test name
Test status
Simulation time 20809962336 ps
CPU time 27.92 seconds
Started Jun 09 01:30:25 PM PDT 24
Finished Jun 09 01:30:54 PM PDT 24
Peak memory 218616 kb
Host smart-2f6d5f69-c7d9-42c1-aa6a-0deb71580159
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994703234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1994703234
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2330093593
Short name T552
Test name
Test status
Simulation time 1542340504 ps
CPU time 9.35 seconds
Started Jun 09 01:30:31 PM PDT 24
Finished Jun 09 01:30:41 PM PDT 24
Peak memory 217572 kb
Host smart-48cf3bd5-d2f7-4a6f-b004-e7b9c21119a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330093593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
330093593
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.900846551
Short name T683
Test name
Test status
Simulation time 68565352 ps
CPU time 2.09 seconds
Started Jun 09 01:30:31 PM PDT 24
Finished Jun 09 01:30:34 PM PDT 24
Peak memory 221740 kb
Host smart-e38cf62b-2708-4467-b870-e29092ef6eea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900846551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
prog_failure.900846551
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3107507666
Short name T859
Test name
Test status
Simulation time 891420697 ps
CPU time 24.15 seconds
Started Jun 09 01:30:31 PM PDT 24
Finished Jun 09 01:30:56 PM PDT 24
Peak memory 217692 kb
Host smart-de3adebc-b5d1-411d-a983-472be4a76803
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107507666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3107507666
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.301638038
Short name T752
Test name
Test status
Simulation time 310009569 ps
CPU time 3.16 seconds
Started Jun 09 01:30:27 PM PDT 24
Finished Jun 09 01:30:30 PM PDT 24
Peak memory 217684 kb
Host smart-b4ac3200-a3ea-4fc1-98c3-143f2e20bf73
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301638038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.301638038
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3835502432
Short name T354
Test name
Test status
Simulation time 2639272055 ps
CPU time 39.62 seconds
Started Jun 09 01:30:25 PM PDT 24
Finished Jun 09 01:31:05 PM PDT 24
Peak memory 275968 kb
Host smart-e61fa57c-ca3b-4785-8506-a2760e732a64
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835502432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3835502432
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1031289029
Short name T656
Test name
Test status
Simulation time 3094906072 ps
CPU time 30.32 seconds
Started Jun 09 01:30:24 PM PDT 24
Finished Jun 09 01:30:55 PM PDT 24
Peak memory 250892 kb
Host smart-1b892b0f-3c03-4d0e-8857-7a0700292818
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031289029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1031289029
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.979481042
Short name T661
Test name
Test status
Simulation time 97221214 ps
CPU time 2.04 seconds
Started Jun 09 01:30:25 PM PDT 24
Finished Jun 09 01:30:27 PM PDT 24
Peak memory 218212 kb
Host smart-1acfca49-b7cc-4603-a107-fd08e09ee7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979481042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.979481042
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1295199421
Short name T355
Test name
Test status
Simulation time 306107697 ps
CPU time 12.33 seconds
Started Jun 09 01:30:25 PM PDT 24
Finished Jun 09 01:30:38 PM PDT 24
Peak memory 214732 kb
Host smart-9ad67961-1267-42ca-aa2c-b2b9449858da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295199421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1295199421
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1795949442
Short name T691
Test name
Test status
Simulation time 245446853 ps
CPU time 10.42 seconds
Started Jun 09 01:30:31 PM PDT 24
Finished Jun 09 01:30:41 PM PDT 24
Peak memory 226084 kb
Host smart-2f84212a-a726-472f-87a8-0729b8e8847d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795949442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1795949442
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.599257199
Short name T359
Test name
Test status
Simulation time 481489833 ps
CPU time 8 seconds
Started Jun 09 01:30:32 PM PDT 24
Finished Jun 09 01:30:41 PM PDT 24
Peak memory 218272 kb
Host smart-cd10f0cd-885e-49f7-81bd-c3b869ba56d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599257199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dig
est.599257199
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3983951501
Short name T153
Test name
Test status
Simulation time 2268880465 ps
CPU time 11.56 seconds
Started Jun 09 01:30:34 PM PDT 24
Finished Jun 09 01:30:46 PM PDT 24
Peak memory 226136 kb
Host smart-eac12c44-aa7f-4e34-a9bb-a78591a4010a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983951501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3
983951501
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.2942377380
Short name T502
Test name
Test status
Simulation time 1210823574 ps
CPU time 12.09 seconds
Started Jun 09 01:30:25 PM PDT 24
Finished Jun 09 01:30:38 PM PDT 24
Peak memory 226104 kb
Host smart-82f16d23-1ed2-40f1-96e2-7608172adaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942377380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2942377380
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.251361370
Short name T516
Test name
Test status
Simulation time 107917449 ps
CPU time 2.24 seconds
Started Jun 09 01:30:31 PM PDT 24
Finished Jun 09 01:30:33 PM PDT 24
Peak memory 214360 kb
Host smart-ca8fe0e5-e3cb-4d0a-9c2b-a4278057dca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251361370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.251361370
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.1699831290
Short name T253
Test name
Test status
Simulation time 174057411 ps
CPU time 20.5 seconds
Started Jun 09 01:30:31 PM PDT 24
Finished Jun 09 01:30:52 PM PDT 24
Peak memory 250916 kb
Host smart-95914288-5b9c-41fa-bb0f-1a92ff6803e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699831290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1699831290
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1102858091
Short name T567
Test name
Test status
Simulation time 67177061 ps
CPU time 7.4 seconds
Started Jun 09 01:30:27 PM PDT 24
Finished Jun 09 01:30:35 PM PDT 24
Peak memory 250920 kb
Host smart-6f1dc5da-1312-48a4-b151-96d795414097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102858091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1102858091
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3542625428
Short name T453
Test name
Test status
Simulation time 25785639 ps
CPU time 0.89 seconds
Started Jun 09 01:30:24 PM PDT 24
Finished Jun 09 01:30:25 PM PDT 24
Peak memory 217756 kb
Host smart-46aca3e1-17e3-4491-9182-3e72e0ceeabb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542625428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.3542625428
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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