Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101842879

1

T1

1694

T2

19320

T3

25205

auto[1]

1430837

1

T11

3366

T13

1881

T15

198

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101845466

1

T1

1694

T2

19320

T3

25205

auto[1]

1428250

1

T11

3564

T13

1485

T15

198

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7119524	1			T1	89		T2	472		T3	6045
auto[IdleSt]	22490919	1			T1	1605		T2	146		T3	2511
auto[ClkMuxSt]	35064	1			T2	8		T3	65		T4	13
auto[CntIncrSt]	34777	1			T2	5		T3	65		T4	13
auto[CntProgSt]	1696596	1			T2	206		T3	2439		T4	187
auto[TransCheckSt]	26757	1			T2	5		T3	65		T4	13
auto[TokenHashSt]	40438013	1			T2	17184		T3	3580		T4	268
auto[FlashRmaSt]	28142	1			T2	28		T3	45		T4	73
auto[TokenCheck0St]	12386	1			T2	5		T3	26		T4	13
auto[TokenCheck1St]	9092	1			T2	5		T3	8		T4	13
auto[TransProgSt]	441788	1			T2	220		T4	153		T13	1053
auto[PostTransSt]	12667329	1			T2	1036		T3	10356		T4	1361
auto[ScrapSt]	95713	1			T21	6		T40	9		T44	36
auto[EscalateSt]	6808737	1			T11	9609		T13	4215		T15	553
auto[InvalidSt]	11366705	1			T11	9953		T13	1655		T7	90606

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2174	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11366705	1			T11	9953		T13	1655		T7	90606
EscalateSt	6808737	1			T11	9609		T13	4215		T15	553
ScrapSt	95713	1			T21	6		T40	9		T44	36
PostTransSt	12667329	1			T2	1036		T3	10356		T4	1361
TransProgSt	441788	1			T2	220		T4	153		T13	1053
TokenCheck1St	9092	1			T2	5		T3	8		T4	13
TokenCheck0St	12386	1			T2	5		T3	26		T4	13
FlashRmaSt	28142	1			T2	28		T3	45		T4	73
TokenHashSt	40438013	1			T2	17184		T3	3580		T4	268
TransCheckSt	26757	1			T2	5		T3	65		T4	13
CntProgSt	1696596	1			T2	206		T3	2439		T4	187
CntIncrSt	34777	1			T2	5		T3	65		T4	13
ClkMuxSt	35064	1			T2	8		T3	65		T4	13
IdleSt	22490919	1			T1	1605		T2	146		T3	2511
ResetSt	7119524	1			T1	89		T2	472		T3	6045
arcs[ResetSt=>IdleSt]	53896	1			T1	1		T2	5		T3	66
arcs[IdleSt=>ScrapSt]	276	1			T21	2		T40	3		T44	1
arcs[IdleSt=>ClkMuxSt]	34845	1			T2	5		T3	65		T4	13
arcs[ClkMuxSt=>CntIncrSt]	34777	1			T2	5		T3	65		T4	13
arcs[CntIncrSt=>PostTransSt]	1743	1			T15	3		T16	7		T17	17
arcs[CntIncrSt=>CntProgSt]	32961	1			T2	5		T3	65		T4	13
arcs[CntProgSt=>PostTransSt]	5029	1			T13	13		T15	4		T20	15
arcs[CntProgSt=>TransCheckSt]	26757	1			T2	5		T3	65		T4	13
arcs[TransCheckSt=>PostTransSt]	3708	1			T3	32		T15	8		T16	10
arcs[TransCheckSt=>TokenHashSt]	22948	1			T2	5		T3	33		T4	13
arcs[TokenHashSt=>PostTransSt]	9859	1			T3	7		T12	1		T13	14
arcs[TokenHashSt=>FlashRmaSt]	12473	1			T2	5		T3	26		T4	13
arcs[FlashRmaSt=>TokenCheck0St]	12386	1			T2	5		T3	26		T4	13
arcs[TokenCheck0St=>PostTransSt]	3273	1			T3	18		T13	9		T15	7
arcs[TokenCheck0St=>TokenCheck1St]	9092	1			T2	5		T3	8		T4	13
arcs[TokenCheck1St=>PostTransSt]	655	1			T3	8		T22	1		T17	1
arcs[TransProgSt=>PostTransSt]	7521	1			T2	5		T4	13		T13	39
arcs[IdleSt=>EscalateSt]	225	1			T21	8		T52	9		T54	9
arcs[ClkMuxSt=>EscalateSt]	68	1			T40	1		T52	5		T53	4
arcs[CntIncrSt=>EscalateSt]	73	1			T21	2		T40	4		T53	2
arcs[CntProgSt=>EscalateSt]	1175	1			T21	24		T40	38		T52	6
arcs[TransCheckSt=>EscalateSt]	101	1			T52	4		T60	1		T54	9
arcs[TokenHashSt=>EscalateSt]	616	1			T21	8		T40	9		T26	2
arcs[FlashRmaSt=>EscalateSt]	87	1			T21	1		T40	3		T52	2
arcs[TokenCheck0St=>EscalateSt]	21	1			T53	1		T58	2		T59	2
arcs[TokenCheck1St=>EscalateSt]	136	1			T21	2		T40	3		T52	2
arcs[TransProgSt=>EscalateSt]	780	1			T21	19		T40	21		T52	9
arcs[PostTransSt=>EscalateSt]	5268	1			T13	13		T15	4		T20	15
arcs[InvalidSt=>EscalateSt]	14372	1			T11	70		T13	21		T7	43

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7119370	1			T1	89		T2	472		T3	6045
auto[0]	auto[IdleSt]	22490776	1			T1	1605		T2	146		T3	2511
auto[0]	auto[ClkMuxSt]	35022	1			T2	8		T3	65		T4	13
auto[0]	auto[CntIncrSt]	34723	1			T2	5		T3	65		T4	13
auto[0]	auto[CntProgSt]	1695785	1			T2	206		T3	2439		T4	187
auto[0]	auto[TransCheckSt]	26688	1			T2	5		T3	65		T4	13
auto[0]	auto[TokenHashSt]	40437609	1			T2	17184		T3	3580		T4	268
auto[0]	auto[FlashRmaSt]	28080	1			T2	28		T3	45		T4	73
auto[0]	auto[TokenCheck0St]	12374	1			T2	5		T3	26		T4	13
auto[0]	auto[TokenCheck1St]	9002	1			T2	5		T3	8		T4	13
auto[0]	auto[TransProgSt]	441252	1			T2	220		T4	153		T13	1053
auto[0]	auto[PostTransSt]	12664643	1			T2	1036		T3	10356		T4	1361
auto[0]	auto[ScrapSt]	95666	1			T21	6		T40	7		T44	36
auto[0]	auto[EscalateSt]	5390174	1			T11	6277		T13	2353		T15	357
auto[0]	auto[InvalidSt]	11359541	1			T11	9919		T13	1643		T7	90582
auto[1]	auto[ResetSt]	154	1			T21	3		T40	5		T52	2
auto[1]	auto[IdleSt]	143	1			T21	6		T52	3		T54	6
auto[1]	auto[ClkMuxSt]	42	1			T52	3		T53	3		T60	2
auto[1]	auto[CntIncrSt]	54	1			T21	2		T40	3		T53	1
auto[1]	auto[CntProgSt]	811	1			T21	19		T40	24		T52	5
auto[1]	auto[TransCheckSt]	69	1			T52	3		T54	7		T227	4
auto[1]	auto[TokenHashSt]	404	1			T21	4		T40	5		T52	12
auto[1]	auto[FlashRmaSt]	62	1			T21	1		T40	3		T52	1
auto[1]	auto[TokenCheck0St]	12	1			T53	1		T59	1		T228	1
auto[1]	auto[TokenCheck1St]	90	1			T21	1		T40	1		T52	2
auto[1]	auto[TransProgSt]	536	1			T21	14		T40	15		T52	8
auto[1]	auto[PostTransSt]	2686	1			T13	7		T15	2		T20	5
auto[1]	auto[ScrapSt]	47	1			T40	2		T52	1		T53	3
auto[1]	auto[EscalateSt]	1418563	1			T11	3332		T13	1862		T15	196
auto[1]	auto[InvalidSt]	7164	1			T11	34		T13	12		T7	24

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7119344	1			T1	89		T2	472		T3	6045
auto[0]	auto[IdleSt]	22490769	1			T1	1605		T2	146		T3	2511
auto[0]	auto[ClkMuxSt]	35016	1			T2	8		T3	65		T4	13
auto[0]	auto[CntIncrSt]	34732	1			T2	5		T3	65		T4	13
auto[0]	auto[CntProgSt]	1695825	1			T2	206		T3	2439		T4	187
auto[0]	auto[TransCheckSt]	26689	1			T2	5		T3	65		T4	13
auto[0]	auto[TokenHashSt]	40437606	1			T2	17184		T3	3580		T4	268
auto[0]	auto[FlashRmaSt]	28087	1			T2	28		T3	45		T4	73
auto[0]	auto[TokenCheck0St]	12372	1			T2	5		T3	26		T4	13
auto[0]	auto[TokenCheck1St]	9002	1			T2	5		T3	8		T4	13
auto[0]	auto[TransProgSt]	441269	1			T2	220		T4	153		T13	1053
auto[0]	auto[PostTransSt]	12664673	1			T2	1036		T3	10356		T4	1361
auto[0]	auto[ScrapSt]	95675	1			T21	4		T40	6		T44	36
auto[0]	auto[EscalateSt]	5392736	1			T11	6081		T13	2745		T15	357
auto[0]	auto[InvalidSt]	11359497	1			T11	9917		T13	1646		T7	90587
auto[1]	auto[ResetSt]	180	1			T21	3		T40	5		T52	4
auto[1]	auto[IdleSt]	150	1			T21	4		T52	6		T54	7
auto[1]	auto[ClkMuxSt]	48	1			T40	1		T52	4		T53	2
auto[1]	auto[CntIncrSt]	45	1			T40	3		T53	1		T60	1
auto[1]	auto[CntProgSt]	771	1			T21	16		T40	27		T52	2
auto[1]	auto[TransCheckSt]	68	1			T52	2		T60	1		T54	6
auto[1]	auto[TokenHashSt]	407	1			T21	5		T40	7		T26	2
auto[1]	auto[FlashRmaSt]	55	1			T21	1		T40	2		T52	2
auto[1]	auto[TokenCheck0St]	14	1			T58	2		T59	1		T229	2
auto[1]	auto[TokenCheck1St]	90	1			T21	1		T40	2		T52	1
auto[1]	auto[TransProgSt]	519	1			T21	14		T40	12		T52	5
auto[1]	auto[PostTransSt]	2656	1			T13	6		T15	2		T20	10
auto[1]	auto[ScrapSt]	38	1			T21	2		T40	3		T53	2
auto[1]	auto[EscalateSt]	1416001	1			T11	3528		T13	1470		T15	196
auto[1]	auto[InvalidSt]	7208	1			T11	36		T13	9		T7	19