Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54389 |
1 |
|
|
T1 |
11 |
|
T2 |
78 |
|
T4 |
170 |
auto[1] |
2313 |
1 |
|
|
T13 |
7 |
|
T14 |
16 |
|
T15 |
14 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55965 |
1 |
|
|
T1 |
11 |
|
T2 |
78 |
|
T4 |
170 |
auto[1] |
737 |
1 |
|
|
T51 |
14 |
|
T16 |
14 |
|
T39 |
12 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54930 |
1 |
|
|
T1 |
8 |
|
T2 |
78 |
|
T4 |
161 |
auto[1] |
1772 |
1 |
|
|
T1 |
3 |
|
T4 |
9 |
|
T5 |
1 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54905 |
1 |
|
|
T1 |
11 |
|
T2 |
78 |
|
T4 |
161 |
auto[1] |
1797 |
1 |
|
|
T4 |
9 |
|
T14 |
33 |
|
T75 |
1 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54862 |
1 |
|
|
T1 |
11 |
|
T2 |
78 |
|
T4 |
157 |
auto[1] |
1840 |
1 |
|
|
T4 |
13 |
|
T5 |
1 |
|
T14 |
29 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
51900 |
1 |
|
|
T1 |
7 |
|
T2 |
78 |
|
T4 |
136 |
no_err_inj |
4802 |
1 |
|
|
T1 |
4 |
|
T4 |
34 |
|
T5 |
5 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54416 |
1 |
|
|
T1 |
11 |
|
T2 |
78 |
|
T4 |
170 |
auto[1] |
2286 |
1 |
|
|
T13 |
9 |
|
T14 |
20 |
|
T15 |
11 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56005 |
1 |
|
|
T1 |
11 |
|
T2 |
78 |
|
T4 |
170 |
auto[1] |
697 |
1 |
|
|
T51 |
18 |
|
T16 |
24 |
|
T39 |
15 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39619 |
1 |
|
|
T2 |
78 |
|
T4 |
119 |
|
T9 |
91 |
auto[1] |
17083 |
1 |
|
|
T1 |
11 |
|
T4 |
51 |
|
T5 |
10 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54833 |
1 |
|
|
T1 |
10 |
|
T2 |
78 |
|
T4 |
157 |
auto[1] |
1869 |
1 |
|
|
T1 |
1 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54885 |
1 |
|
|
T1 |
10 |
|
T2 |
78 |
|
T4 |
162 |
auto[1] |
1817 |
1 |
|
|
T1 |
1 |
|
T4 |
8 |
|
T14 |
41 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54878 |
1 |
|
|
T1 |
11 |
|
T2 |
78 |
|
T4 |
161 |
auto[1] |
1824 |
1 |
|
|
T4 |
9 |
|
T5 |
1 |
|
T14 |
40 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54547 |
1 |
|
|
T1 |
11 |
|
T2 |
78 |
|
T4 |
170 |
auto[1] |
2155 |
1 |
|
|
T13 |
9 |
|
T14 |
22 |
|
T15 |
14 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54583 |
1 |
|
|
T1 |
11 |
|
T2 |
78 |
|
T4 |
122 |
auto[1] |
2119 |
1 |
|
|
T4 |
48 |
|
T14 |
19 |
|
T49 |
16 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55946 |
1 |
|
|
T1 |
11 |
|
T2 |
78 |
|
T4 |
170 |
auto[1] |
756 |
1 |
|
|
T51 |
15 |
|
T16 |
22 |
|
T39 |
19 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55922 |
1 |
|
|
T1 |
11 |
|
T2 |
78 |
|
T4 |
170 |
auto[1] |
780 |
1 |
|
|
T51 |
9 |
|
T16 |
15 |
|
T39 |
8 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55968 |
1 |
|
|
T1 |
11 |
|
T2 |
78 |
|
T4 |
170 |
auto[1] |
734 |
1 |
|
|
T51 |
10 |
|
T16 |
18 |
|
T39 |
20 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54043 |
1 |
|
|
T2 |
78 |
|
T4 |
170 |
|
T9 |
91 |
auto[1] |
2659 |
1 |
|
|
T1 |
11 |
|
T5 |
10 |
|
T19 |
13 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52871 |
1 |
|
|
T1 |
11 |
|
T4 |
170 |
|
T5 |
10 |
auto[1] |
3831 |
1 |
|
|
T2 |
78 |
|
T9 |
91 |
|
T18 |
88 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54840 |
1 |
|
|
T1 |
10 |
|
T2 |
78 |
|
T4 |
162 |
auto[1] |
1862 |
1 |
|
|
T1 |
1 |
|
T4 |
8 |
|
T5 |
1 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54773 |
1 |
|
|
T1 |
11 |
|
T2 |
78 |
|
T4 |
165 |
auto[1] |
1929 |
1 |
|
|
T4 |
5 |
|
T14 |
38 |
|
T75 |
1 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54788 |
1 |
|
|
T1 |
10 |
|
T2 |
78 |
|
T4 |
156 |
auto[1] |
1914 |
1 |
|
|
T1 |
1 |
|
T4 |
14 |
|
T14 |
44 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54459 |
1 |
|
|
T1 |
11 |
|
T2 |
78 |
|
T4 |
170 |
auto[1] |
2243 |
1 |
|
|
T13 |
13 |
|
T14 |
15 |
|
T15 |
16 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50621 |
1 |
|
|
T1 |
11 |
|
T2 |
78 |
|
T4 |
170 |
auto[1] |
6081 |
1 |
|
|
T13 |
4 |
|
T14 |
10 |
|
T15 |
11 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52890 |
1 |
|
|
T1 |
11 |
|
T2 |
78 |
|
T4 |
170 |
auto[1] |
3812 |
1 |
|
|
T12 |
64 |
|
T50 |
60 |
|
T17 |
81 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56702 |
1 |
|
|
T1 |
11 |
|
T2 |
78 |
|
T4 |
170 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54543 |
1 |
|
|
T1 |
11 |
|
T2 |
78 |
|
T4 |
170 |
auto[1] |
2159 |
1 |
|
|
T13 |
7 |
|
T14 |
17 |
|
T15 |
11 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54402 |
1 |
|
|
T1 |
11 |
|
T2 |
78 |
|
T4 |
170 |
auto[1] |
2300 |
1 |
|
|
T13 |
7 |
|
T14 |
26 |
|
T15 |
16 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54429 |
1 |
|
|
T1 |
11 |
|
T2 |
78 |
|
T4 |
170 |
auto[1] |
2273 |
1 |
|
|
T13 |
7 |
|
T14 |
22 |
|
T15 |
6 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
50587 |
1 |
|
|
T2 |
78 |
|
T4 |
136 |
|
T9 |
91 |
auto[0] |
no_err_inj |
3456 |
1 |
|
|
T4 |
34 |
|
T10 |
9 |
|
T11 |
9 |
auto[1] |
err_inj |
1313 |
1 |
|
|
T1 |
7 |
|
T5 |
5 |
|
T19 |
4 |
auto[1] |
no_err_inj |
1346 |
1 |
|
|
T1 |
4 |
|
T5 |
5 |
|
T19 |
9 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52257 |
1 |
|
|
T2 |
78 |
|
T4 |
165 |
|
T9 |
91 |
auto[0] |
auto[1] |
1786 |
1 |
|
|
T4 |
5 |
|
T14 |
38 |
|
T77 |
8 |
auto[1] |
auto[0] |
2516 |
1 |
|
|
T1 |
11 |
|
T5 |
10 |
|
T19 |
13 |
auto[1] |
auto[1] |
143 |
1 |
|
|
T75 |
1 |
|
T76 |
1 |
|
T33 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52376 |
1 |
|
|
T2 |
78 |
|
T4 |
162 |
|
T9 |
91 |
auto[0] |
auto[1] |
1667 |
1 |
|
|
T4 |
8 |
|
T14 |
41 |
|
T77 |
3 |
auto[1] |
auto[0] |
2509 |
1 |
|
|
T1 |
10 |
|
T5 |
10 |
|
T19 |
13 |
auto[1] |
auto[1] |
150 |
1 |
|
|
T1 |
1 |
|
T75 |
1 |
|
T76 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52263 |
1 |
|
|
T2 |
78 |
|
T4 |
156 |
|
T9 |
91 |
auto[0] |
auto[1] |
1780 |
1 |
|
|
T4 |
14 |
|
T14 |
44 |
|
T77 |
8 |
auto[1] |
auto[0] |
2525 |
1 |
|
|
T1 |
10 |
|
T5 |
10 |
|
T19 |
13 |
auto[1] |
auto[1] |
134 |
1 |
|
|
T1 |
1 |
|
T75 |
1 |
|
T76 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52384 |
1 |
|
|
T2 |
78 |
|
T4 |
161 |
|
T9 |
91 |
auto[0] |
auto[1] |
1659 |
1 |
|
|
T4 |
9 |
|
T14 |
33 |
|
T77 |
7 |
auto[1] |
auto[0] |
2521 |
1 |
|
|
T1 |
11 |
|
T5 |
10 |
|
T19 |
13 |
auto[1] |
auto[1] |
138 |
1 |
|
|
T75 |
1 |
|
T76 |
1 |
|
T33 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52357 |
1 |
|
|
T2 |
78 |
|
T4 |
157 |
|
T9 |
91 |
auto[0] |
auto[1] |
1686 |
1 |
|
|
T4 |
13 |
|
T14 |
29 |
|
T77 |
4 |
auto[1] |
auto[0] |
2505 |
1 |
|
|
T1 |
11 |
|
T5 |
9 |
|
T19 |
13 |
auto[1] |
auto[1] |
154 |
1 |
|
|
T5 |
1 |
|
T33 |
1 |
|
T38 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52434 |
1 |
|
|
T2 |
78 |
|
T4 |
161 |
|
T9 |
91 |
auto[0] |
auto[1] |
1609 |
1 |
|
|
T4 |
9 |
|
T14 |
36 |
|
T77 |
11 |
auto[1] |
auto[0] |
2496 |
1 |
|
|
T1 |
8 |
|
T5 |
9 |
|
T19 |
13 |
auto[1] |
auto[1] |
163 |
1 |
|
|
T1 |
3 |
|
T5 |
1 |
|
T76 |
3 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38204 |
1 |
|
|
T2 |
78 |
|
T4 |
119 |
|
T9 |
91 |
auto[0] |
auto[1] |
1415 |
1 |
|
|
T13 |
7 |
|
T14 |
11 |
|
T37 |
11 |
auto[1] |
auto[0] |
16185 |
1 |
|
|
T1 |
11 |
|
T4 |
51 |
|
T5 |
10 |
auto[1] |
auto[1] |
898 |
1 |
|
|
T14 |
5 |
|
T15 |
14 |
|
T35 |
4 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38206 |
1 |
|
|
T2 |
78 |
|
T4 |
119 |
|
T9 |
91 |
auto[0] |
auto[1] |
1413 |
1 |
|
|
T13 |
9 |
|
T14 |
11 |
|
T37 |
8 |
auto[1] |
auto[0] |
16210 |
1 |
|
|
T1 |
11 |
|
T4 |
51 |
|
T5 |
10 |
auto[1] |
auto[1] |
873 |
1 |
|
|
T14 |
9 |
|
T15 |
11 |
|
T35 |
8 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38563 |
1 |
|
|
T2 |
78 |
|
T4 |
103 |
|
T9 |
91 |
auto[0] |
auto[1] |
1056 |
1 |
|
|
T4 |
16 |
|
T49 |
16 |
|
T215 |
8 |
auto[1] |
auto[0] |
16020 |
1 |
|
|
T1 |
11 |
|
T4 |
19 |
|
T5 |
10 |
auto[1] |
auto[1] |
1063 |
1 |
|
|
T4 |
32 |
|
T14 |
19 |
|
T21 |
1 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38299 |
1 |
|
|
T2 |
78 |
|
T4 |
119 |
|
T9 |
91 |
auto[0] |
auto[1] |
1320 |
1 |
|
|
T13 |
9 |
|
T14 |
16 |
|
T37 |
12 |
auto[1] |
auto[0] |
16248 |
1 |
|
|
T1 |
11 |
|
T4 |
51 |
|
T5 |
10 |
auto[1] |
auto[1] |
835 |
1 |
|
|
T14 |
6 |
|
T15 |
14 |
|
T35 |
10 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34418 |
1 |
|
|
T2 |
78 |
|
T4 |
119 |
|
T9 |
91 |
auto[0] |
auto[1] |
5201 |
1 |
|
|
T13 |
4 |
|
T14 |
7 |
|
T37 |
14 |
auto[1] |
auto[0] |
16203 |
1 |
|
|
T1 |
11 |
|
T4 |
51 |
|
T5 |
10 |
auto[1] |
auto[1] |
880 |
1 |
|
|
T14 |
3 |
|
T15 |
11 |
|
T35 |
13 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38474 |
1 |
|
|
T2 |
78 |
|
T4 |
114 |
|
T9 |
91 |
auto[0] |
auto[1] |
1145 |
1 |
|
|
T4 |
5 |
|
T14 |
9 |
|
T75 |
1 |
auto[1] |
auto[0] |
16299 |
1 |
|
|
T1 |
11 |
|
T4 |
51 |
|
T5 |
10 |
auto[1] |
auto[1] |
784 |
1 |
|
|
T14 |
29 |
|
T84 |
7 |
|
T48 |
16 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38535 |
1 |
|
|
T2 |
78 |
|
T4 |
111 |
|
T9 |
91 |
auto[0] |
auto[1] |
1084 |
1 |
|
|
T4 |
8 |
|
T14 |
3 |
|
T77 |
5 |
auto[1] |
auto[0] |
16305 |
1 |
|
|
T1 |
10 |
|
T4 |
51 |
|
T5 |
9 |
auto[1] |
auto[1] |
778 |
1 |
|
|
T1 |
1 |
|
T5 |
1 |
|
T14 |
34 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38589 |
1 |
|
|
T2 |
78 |
|
T4 |
111 |
|
T9 |
91 |
auto[0] |
auto[1] |
1030 |
1 |
|
|
T4 |
8 |
|
T14 |
7 |
|
T75 |
1 |
auto[1] |
auto[0] |
16296 |
1 |
|
|
T1 |
10 |
|
T4 |
51 |
|
T5 |
10 |
auto[1] |
auto[1] |
787 |
1 |
|
|
T1 |
1 |
|
T14 |
34 |
|
T84 |
7 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38552 |
1 |
|
|
T2 |
78 |
|
T4 |
106 |
|
T9 |
91 |
auto[0] |
auto[1] |
1067 |
1 |
|
|
T4 |
13 |
|
T14 |
9 |
|
T77 |
9 |
auto[1] |
auto[0] |
16281 |
1 |
|
|
T1 |
10 |
|
T4 |
51 |
|
T5 |
9 |
auto[1] |
auto[1] |
802 |
1 |
|
|
T1 |
1 |
|
T5 |
1 |
|
T14 |
25 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38575 |
1 |
|
|
T2 |
78 |
|
T4 |
110 |
|
T9 |
91 |
auto[0] |
auto[1] |
1044 |
1 |
|
|
T4 |
9 |
|
T14 |
9 |
|
T75 |
1 |
auto[1] |
auto[0] |
16330 |
1 |
|
|
T1 |
11 |
|
T4 |
51 |
|
T5 |
10 |
auto[1] |
auto[1] |
753 |
1 |
|
|
T14 |
24 |
|
T84 |
7 |
|
T48 |
17 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38599 |
1 |
|
|
T2 |
78 |
|
T4 |
110 |
|
T9 |
91 |
auto[0] |
auto[1] |
1020 |
1 |
|
|
T4 |
9 |
|
T14 |
6 |
|
T76 |
3 |
auto[1] |
auto[0] |
16331 |
1 |
|
|
T1 |
8 |
|
T4 |
51 |
|
T5 |
9 |
auto[1] |
auto[1] |
752 |
1 |
|
|
T1 |
3 |
|
T5 |
1 |
|
T14 |
30 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38240 |
1 |
|
|
T2 |
78 |
|
T4 |
119 |
|
T9 |
91 |
auto[0] |
auto[1] |
1379 |
1 |
|
|
T13 |
7 |
|
T14 |
10 |
|
T37 |
18 |
auto[1] |
auto[0] |
16189 |
1 |
|
|
T1 |
11 |
|
T4 |
51 |
|
T5 |
10 |
auto[1] |
auto[1] |
894 |
1 |
|
|
T14 |
12 |
|
T15 |
6 |
|
T35 |
17 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38208 |
1 |
|
|
T2 |
78 |
|
T4 |
119 |
|
T9 |
91 |
auto[0] |
auto[1] |
1411 |
1 |
|
|
T13 |
7 |
|
T14 |
17 |
|
T37 |
10 |
auto[1] |
auto[0] |
16194 |
1 |
|
|
T1 |
11 |
|
T4 |
51 |
|
T5 |
10 |
auto[1] |
auto[1] |
889 |
1 |
|
|
T14 |
9 |
|
T15 |
16 |
|
T35 |
10 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38142 |
1 |
|
|
T2 |
78 |
|
T4 |
119 |
|
T9 |
91 |
auto[0] |
auto[1] |
1477 |
1 |
|
|
T75 |
12 |
|
T76 |
15 |
|
T33 |
11 |
auto[1] |
auto[0] |
15901 |
1 |
|
|
T4 |
51 |
|
T11 |
9 |
|
T14 |
359 |
auto[1] |
auto[1] |
1182 |
1 |
|
|
T1 |
11 |
|
T5 |
10 |
|
T19 |
13 |