Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

118345863

1

T1

99771

T2

29173

T3

1120

auto[1]

1418784

1

T1

196

T2

10101

T4

5626

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

118355097

1

T1

99575

T2

29533

T3

1120

auto[1]

1409550

1

T1

392

T2

9741

T4

5529

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7507818	1			T1	1246		T2	6857		T3	114
auto[IdleSt]	23810534	1			T1	25565		T2	5860		T3	16
auto[ClkMuxSt]	38983	1			T1	4		T2	62		T3	1
auto[CntIncrSt]	38676	1			T1	4		T2	62		T3	1
auto[CntProgSt]	1708348	1			T1	694		T2	612		T3	50
auto[TransCheckSt]	30008	1			T1	4		T2	33		T3	1
auto[TokenHashSt]	52494548	1			T1	179		T2	10444		T3	108
auto[FlashRmaSt]	30148	1			T1	16		T2	50		T4	117
auto[TokenCheck0St]	13489	1			T1	4		T2	21		T4	30
auto[TokenCheck1St]	9810	1			T1	4		T2	20		T4	30
auto[TransProgSt]	378422	1			T1	372		T2	53		T4	161
auto[PostTransSt]	14619842	1			T1	23271		T3	829		T4	36499
auto[ScrapSt]	178537	1			T2	3		T4	1659		T11	3464
auto[EscalateSt]	7052013	1			T1	25670		T2	15197		T4	30824
auto[InvalidSt]	11851564	1			T1	22933		T4	4747		T5	3999

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1907	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11851564	1			T1	22933		T4	4747		T5	3999
EscalateSt	7052013	1			T1	25670		T2	15197		T4	30824
ScrapSt	178537	1			T2	3		T4	1659		T11	3464
PostTransSt	14619842	1			T1	23271		T3	829		T4	36499
TransProgSt	378422	1			T1	372		T2	53		T4	161
TokenCheck1St	9810	1			T1	4		T2	20		T4	30
TokenCheck0St	13489	1			T1	4		T2	21		T4	30
FlashRmaSt	30148	1			T1	16		T2	50		T4	117
TokenHashSt	52494548	1			T1	179		T2	10444		T3	108
TransCheckSt	30008	1			T1	4		T2	33		T3	1
CntProgSt	1708348	1			T1	694		T2	612		T3	50
CntIncrSt	38676	1			T1	4		T2	62		T3	1
ClkMuxSt	38983	1			T1	4		T2	62		T3	1
IdleSt	23810534	1			T1	25565		T2	5860		T3	16
ResetSt	7507818	1			T1	1246		T2	6857		T3	114
arcs[ResetSt=>IdleSt]	57159	1			T1	12		T2	70		T3	1
arcs[IdleSt=>ScrapSt]	267	1			T2	1		T4	4		T11	2
arcs[IdleSt=>ClkMuxSt]	38747	1			T1	4		T2	62		T3	1
arcs[ClkMuxSt=>CntIncrSt]	38676	1			T1	4		T2	62		T3	1
arcs[CntIncrSt=>PostTransSt]	2302	1			T13	7		T14	26		T15	16
arcs[CntIncrSt=>CntProgSt]	36314	1			T1	4		T2	62		T3	1
arcs[CntProgSt=>PostTransSt]	5122	1			T4	48		T13	7		T14	35
arcs[CntProgSt=>TransCheckSt]	30008	1			T1	4		T2	33		T3	1
arcs[TransCheckSt=>PostTransSt]	4161	1			T12	33		T13	7		T14	22
arcs[TransCheckSt=>TokenHashSt]	25744	1			T1	4		T2	33		T3	1
arcs[TokenHashSt=>PostTransSt]	11484	1			T3	1		T12	7		T13	24
arcs[TokenHashSt=>FlashRmaSt]	13579	1			T1	4		T2	24		T4	30
arcs[FlashRmaSt=>TokenCheck0St]	13489	1			T1	4		T2	21		T4	30
arcs[TokenCheck0St=>PostTransSt]	3652	1			T12	19		T13	9		T14	15
arcs[TokenCheck0St=>TokenCheck1St]	9810	1			T1	4		T2	20		T4	30
arcs[TokenCheck1St=>PostTransSt]	732	1			T12	5		T14	4		T15	1
arcs[TransProgSt=>PostTransSt]	8151	1			T1	4		T4	30		T9	3
arcs[IdleSt=>EscalateSt]	202	1			T2	6		T44	7		T45	4
arcs[ClkMuxSt=>EscalateSt]	71	1			T9	3		T18	1		T43	2
arcs[CntIncrSt=>EscalateSt]	60	1			T9	1		T18	1		T44	2
arcs[CntProgSt=>EscalateSt]	1184	1			T2	29		T9	34		T18	30
arcs[TransCheckSt=>EscalateSt]	103	1			T44	1		T45	6		T43	10
arcs[TokenHashSt=>EscalateSt]	681	1			T2	9		T9	13		T18	15
arcs[FlashRmaSt=>EscalateSt]	90	1			T2	3		T9	1		T44	2
arcs[TokenCheck0St=>EscalateSt]	27	1			T2	1		T9	1		T18	1
arcs[TokenCheck1St=>EscalateSt]	127	1			T2	2		T9	4		T18	5
arcs[TransProgSt=>EscalateSt]	800	1			T2	18		T9	25		T18	28
arcs[PostTransSt=>EscalateSt]	5348	1			T4	48		T9	3		T13	7
arcs[InvalidSt=>EscalateSt]	13681	1			T1	6		T4	65		T5	4

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7507648	1			T1	1246		T2	6850		T3	114
auto[0]	auto[IdleSt]	23810399	1			T1	25565		T2	5857		T3	16
auto[0]	auto[ClkMuxSt]	38933	1			T1	4		T2	62		T3	1
auto[0]	auto[CntIncrSt]	38628	1			T1	4		T2	62		T3	1
auto[0]	auto[CntProgSt]	1707576	1			T1	694		T2	595		T3	50
auto[0]	auto[TransCheckSt]	29930	1			T1	4		T2	33		T3	1
auto[0]	auto[TokenHashSt]	52494110	1			T1	179		T2	10436		T3	108
auto[0]	auto[FlashRmaSt]	30088	1			T1	16		T2	48		T4	117
auto[0]	auto[TokenCheck0St]	13471	1			T1	4		T2	20		T4	30
auto[0]	auto[TokenCheck1St]	9713	1			T1	4		T2	18		T4	30
auto[0]	auto[TransProgSt]	377912	1			T1	372		T2	42		T4	161
auto[0]	auto[PostTransSt]	14617089	1			T1	23271		T3	829		T4	36476
auto[0]	auto[ScrapSt]	178493	1			T2	2		T4	1659		T11	3464
auto[0]	auto[EscalateSt]	5645276	1			T1	25476		T2	5148		T4	25255
auto[0]	auto[InvalidSt]	11844690	1			T1	22931		T4	4713		T5	3996
auto[1]	auto[ResetSt]	170	1			T2	7		T9	4		T18	3
auto[1]	auto[IdleSt]	135	1			T2	3		T44	7		T45	2
auto[1]	auto[ClkMuxSt]	50	1			T9	2		T18	1		T43	1
auto[1]	auto[CntIncrSt]	48	1			T9	1		T18	1		T44	2
auto[1]	auto[CntProgSt]	772	1			T2	17		T9	25		T18	15
auto[1]	auto[TransCheckSt]	78	1			T44	1		T45	4		T43	8
auto[1]	auto[TokenHashSt]	438	1			T2	8		T9	6		T18	11
auto[1]	auto[FlashRmaSt]	60	1			T2	2		T45	2		T43	2
auto[1]	auto[TokenCheck0St]	18	1			T2	1		T9	1		T44	2
auto[1]	auto[TokenCheck1St]	97	1			T2	2		T9	3		T18	3
auto[1]	auto[TransProgSt]	510	1			T2	11		T9	14		T18	18
auto[1]	auto[PostTransSt]	2753	1			T4	23		T9	3		T13	2
auto[1]	auto[ScrapSt]	44	1			T2	1		T18	2		T43	2
auto[1]	auto[EscalateSt]	1406737	1			T1	194		T2	10049		T4	5569
auto[1]	auto[InvalidSt]	6874	1			T1	2		T4	34		T5	3

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7507648	1			T1	1246		T2	6852		T3	114
auto[0]	auto[IdleSt]	23810396	1			T1	25565		T2	5855		T3	16
auto[0]	auto[ClkMuxSt]	38936	1			T1	4		T2	62		T3	1
auto[0]	auto[CntIncrSt]	38638	1			T1	4		T2	62		T3	1
auto[0]	auto[CntProgSt]	1707540	1			T1	694		T2	590		T3	50
auto[0]	auto[TransCheckSt]	29941	1			T1	4		T2	33		T3	1
auto[0]	auto[TokenHashSt]	52494104	1			T1	179		T2	10442		T3	108
auto[0]	auto[FlashRmaSt]	30084	1			T1	16		T2	49		T4	117
auto[0]	auto[TokenCheck0St]	13468	1			T1	4		T2	20		T4	30
auto[0]	auto[TokenCheck1St]	9730	1			T1	4		T2	20		T4	30
auto[0]	auto[TransProgSt]	377887	1			T1	372		T2	40		T4	161
auto[0]	auto[PostTransSt]	14617188	1			T1	23271		T3	829		T4	36474
auto[0]	auto[ScrapSt]	178505	1			T2	2		T4	1659		T11	3464
auto[0]	auto[EscalateSt]	5654368	1			T1	25282		T2	5506		T4	25351
auto[0]	auto[InvalidSt]	11844757	1			T1	22929		T4	4716		T5	3998
auto[1]	auto[ResetSt]	170	1			T2	5		T9	3		T18	4
auto[1]	auto[IdleSt]	138	1			T2	5		T44	5		T45	4
auto[1]	auto[ClkMuxSt]	47	1			T9	1		T18	1		T43	2
auto[1]	auto[CntIncrSt]	38	1			T44	2		T45	1		T43	1
auto[1]	auto[CntProgSt]	808	1			T2	22		T9	21		T18	26
auto[1]	auto[TransCheckSt]	67	1			T45	2		T43	9		T214	3
auto[1]	auto[TokenHashSt]	444	1			T2	2		T9	11		T18	10
auto[1]	auto[FlashRmaSt]	64	1			T2	1		T9	1		T44	2
auto[1]	auto[TokenCheck0St]	21	1			T2	1		T18	1		T43	1
auto[1]	auto[TokenCheck1St]	80	1			T9	4		T18	4		T44	2
auto[1]	auto[TransProgSt]	535	1			T2	13		T9	13		T18	16
auto[1]	auto[PostTransSt]	2654	1			T4	25		T9	1		T13	5
auto[1]	auto[ScrapSt]	32	1			T2	1		T18	1		T43	1
auto[1]	auto[EscalateSt]	1397645	1			T1	388		T2	9691		T4	5473
auto[1]	auto[InvalidSt]	6807	1			T1	4		T4	31		T5	1