Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53210 |
1 |
|
|
T1 |
72 |
|
T2 |
75 |
|
T3 |
60 |
auto[1] |
1847 |
1 |
|
|
T1 |
11 |
|
T2 |
13 |
|
T3 |
10 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54324 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[1] |
733 |
1 |
|
|
T32 |
20 |
|
T21 |
23 |
|
T54 |
15 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53058 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[1] |
1999 |
1 |
|
|
T11 |
5 |
|
T5 |
10 |
|
T49 |
7 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53071 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[1] |
1986 |
1 |
|
|
T11 |
6 |
|
T5 |
7 |
|
T49 |
9 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53056 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[1] |
2001 |
1 |
|
|
T11 |
8 |
|
T5 |
9 |
|
T49 |
18 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
50189 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
no_err_inj |
4868 |
1 |
|
|
T13 |
5 |
|
T4 |
6 |
|
T14 |
7 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53172 |
1 |
|
|
T1 |
72 |
|
T2 |
76 |
|
T3 |
62 |
auto[1] |
1885 |
1 |
|
|
T1 |
11 |
|
T2 |
12 |
|
T3 |
8 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54314 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[1] |
743 |
1 |
|
|
T32 |
18 |
|
T21 |
10 |
|
T54 |
13 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
39060 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[1] |
15997 |
1 |
|
|
T4 |
10 |
|
T5 |
83 |
|
T6 |
14 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53163 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[1] |
1894 |
1 |
|
|
T11 |
8 |
|
T4 |
1 |
|
T14 |
2 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53038 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[1] |
2019 |
1 |
|
|
T11 |
10 |
|
T4 |
1 |
|
T14 |
1 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53028 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[1] |
2029 |
1 |
|
|
T11 |
11 |
|
T5 |
11 |
|
T49 |
8 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53151 |
1 |
|
|
T1 |
73 |
|
T2 |
78 |
|
T3 |
63 |
auto[1] |
1906 |
1 |
|
|
T1 |
10 |
|
T2 |
10 |
|
T3 |
7 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52709 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[1] |
2348 |
1 |
|
|
T12 |
19 |
|
T15 |
4 |
|
T31 |
4 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54231 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[1] |
826 |
1 |
|
|
T32 |
20 |
|
T21 |
26 |
|
T54 |
17 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54271 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[1] |
786 |
1 |
|
|
T32 |
23 |
|
T21 |
18 |
|
T54 |
15 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54321 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[1] |
736 |
1 |
|
|
T32 |
19 |
|
T21 |
12 |
|
T54 |
13 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52308 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[1] |
2749 |
1 |
|
|
T4 |
10 |
|
T14 |
11 |
|
T24 |
11 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51334 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[1] |
3723 |
1 |
|
|
T50 |
70 |
|
T48 |
70 |
|
T63 |
91 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53052 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[1] |
2005 |
1 |
|
|
T11 |
6 |
|
T4 |
1 |
|
T5 |
11 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53117 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[1] |
1940 |
1 |
|
|
T11 |
8 |
|
T4 |
1 |
|
T14 |
1 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53158 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[1] |
1899 |
1 |
|
|
T11 |
3 |
|
T5 |
11 |
|
T49 |
9 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53210 |
1 |
|
|
T1 |
80 |
|
T2 |
73 |
|
T3 |
60 |
auto[1] |
1847 |
1 |
|
|
T1 |
3 |
|
T2 |
15 |
|
T3 |
10 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49499 |
1 |
|
|
T1 |
62 |
|
T2 |
75 |
|
T3 |
61 |
auto[1] |
5558 |
1 |
|
|
T1 |
21 |
|
T2 |
13 |
|
T3 |
9 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51316 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[1] |
3741 |
1 |
|
|
T59 |
70 |
|
T60 |
73 |
|
T61 |
77 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55057 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53096 |
1 |
|
|
T1 |
73 |
|
T2 |
80 |
|
T3 |
64 |
auto[1] |
1961 |
1 |
|
|
T1 |
10 |
|
T2 |
8 |
|
T3 |
6 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53201 |
1 |
|
|
T1 |
76 |
|
T2 |
81 |
|
T3 |
57 |
auto[1] |
1856 |
1 |
|
|
T1 |
7 |
|
T2 |
7 |
|
T3 |
13 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53136 |
1 |
|
|
T1 |
73 |
|
T2 |
78 |
|
T3 |
63 |
auto[1] |
1921 |
1 |
|
|
T1 |
10 |
|
T2 |
10 |
|
T3 |
7 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
48839 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[0] |
no_err_inj |
3469 |
1 |
|
|
T13 |
5 |
|
T6 |
14 |
|
T17 |
11 |
auto[1] |
err_inj |
1350 |
1 |
|
|
T4 |
4 |
|
T14 |
4 |
|
T24 |
9 |
auto[1] |
no_err_inj |
1399 |
1 |
|
|
T4 |
6 |
|
T14 |
7 |
|
T24 |
2 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50521 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[0] |
auto[1] |
1787 |
1 |
|
|
T11 |
8 |
|
T5 |
6 |
|
T49 |
7 |
auto[1] |
auto[0] |
2596 |
1 |
|
|
T4 |
9 |
|
T14 |
10 |
|
T24 |
9 |
auto[1] |
auto[1] |
153 |
1 |
|
|
T4 |
1 |
|
T14 |
1 |
|
T24 |
2 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50444 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[0] |
auto[1] |
1864 |
1 |
|
|
T11 |
10 |
|
T5 |
10 |
|
T49 |
9 |
auto[1] |
auto[0] |
2594 |
1 |
|
|
T4 |
9 |
|
T14 |
10 |
|
T24 |
8 |
auto[1] |
auto[1] |
155 |
1 |
|
|
T4 |
1 |
|
T14 |
1 |
|
T24 |
3 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50564 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[0] |
auto[1] |
1744 |
1 |
|
|
T11 |
3 |
|
T5 |
11 |
|
T49 |
9 |
auto[1] |
auto[0] |
2594 |
1 |
|
|
T4 |
10 |
|
T14 |
11 |
|
T24 |
8 |
auto[1] |
auto[1] |
155 |
1 |
|
|
T24 |
3 |
|
T107 |
3 |
|
T29 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50475 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[0] |
auto[1] |
1833 |
1 |
|
|
T11 |
6 |
|
T5 |
7 |
|
T49 |
9 |
auto[1] |
auto[0] |
2596 |
1 |
|
|
T4 |
10 |
|
T14 |
11 |
|
T24 |
10 |
auto[1] |
auto[1] |
153 |
1 |
|
|
T24 |
1 |
|
T251 |
1 |
|
T28 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50458 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[0] |
auto[1] |
1850 |
1 |
|
|
T11 |
8 |
|
T5 |
9 |
|
T49 |
18 |
auto[1] |
auto[0] |
2598 |
1 |
|
|
T4 |
10 |
|
T14 |
11 |
|
T24 |
11 |
auto[1] |
auto[1] |
151 |
1 |
|
|
T217 |
1 |
|
T51 |
1 |
|
T123 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50455 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[0] |
auto[1] |
1853 |
1 |
|
|
T11 |
5 |
|
T5 |
10 |
|
T49 |
7 |
auto[1] |
auto[0] |
2603 |
1 |
|
|
T4 |
10 |
|
T14 |
11 |
|
T24 |
11 |
auto[1] |
auto[1] |
146 |
1 |
|
|
T251 |
1 |
|
T29 |
1 |
|
T217 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37863 |
1 |
|
|
T1 |
72 |
|
T2 |
75 |
|
T3 |
60 |
auto[0] |
auto[1] |
1197 |
1 |
|
|
T1 |
11 |
|
T2 |
13 |
|
T3 |
10 |
auto[1] |
auto[0] |
15347 |
1 |
|
|
T4 |
10 |
|
T5 |
83 |
|
T6 |
14 |
auto[1] |
auto[1] |
650 |
1 |
|
|
T26 |
8 |
|
T29 |
9 |
|
T51 |
10 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37822 |
1 |
|
|
T1 |
72 |
|
T2 |
76 |
|
T3 |
62 |
auto[0] |
auto[1] |
1238 |
1 |
|
|
T1 |
11 |
|
T2 |
12 |
|
T3 |
8 |
auto[1] |
auto[0] |
15350 |
1 |
|
|
T4 |
10 |
|
T5 |
83 |
|
T6 |
14 |
auto[1] |
auto[1] |
647 |
1 |
|
|
T26 |
8 |
|
T29 |
12 |
|
T51 |
5 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37764 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[0] |
auto[1] |
1296 |
1 |
|
|
T12 |
19 |
|
T15 |
4 |
|
T31 |
4 |
auto[1] |
auto[0] |
14945 |
1 |
|
|
T4 |
10 |
|
T5 |
83 |
|
T6 |
14 |
auto[1] |
auto[1] |
1052 |
1 |
|
|
T69 |
9 |
|
T252 |
19 |
|
T108 |
10 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37798 |
1 |
|
|
T1 |
73 |
|
T2 |
78 |
|
T3 |
63 |
auto[0] |
auto[1] |
1262 |
1 |
|
|
T1 |
10 |
|
T2 |
10 |
|
T3 |
7 |
auto[1] |
auto[0] |
15353 |
1 |
|
|
T4 |
10 |
|
T5 |
83 |
|
T6 |
14 |
auto[1] |
auto[1] |
644 |
1 |
|
|
T26 |
16 |
|
T29 |
7 |
|
T51 |
7 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34080 |
1 |
|
|
T1 |
62 |
|
T2 |
75 |
|
T3 |
61 |
auto[0] |
auto[1] |
4980 |
1 |
|
|
T1 |
21 |
|
T2 |
13 |
|
T3 |
9 |
auto[1] |
auto[0] |
15419 |
1 |
|
|
T4 |
10 |
|
T5 |
83 |
|
T6 |
14 |
auto[1] |
auto[1] |
578 |
1 |
|
|
T26 |
10 |
|
T29 |
7 |
|
T51 |
8 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37995 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[0] |
auto[1] |
1065 |
1 |
|
|
T11 |
8 |
|
T14 |
1 |
|
T49 |
7 |
auto[1] |
auto[0] |
15122 |
1 |
|
|
T4 |
9 |
|
T5 |
77 |
|
T6 |
14 |
auto[1] |
auto[1] |
875 |
1 |
|
|
T4 |
1 |
|
T5 |
6 |
|
T24 |
2 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37935 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[0] |
auto[1] |
1125 |
1 |
|
|
T11 |
6 |
|
T49 |
11 |
|
T99 |
5 |
auto[1] |
auto[0] |
15117 |
1 |
|
|
T4 |
9 |
|
T5 |
72 |
|
T6 |
14 |
auto[1] |
auto[1] |
880 |
1 |
|
|
T4 |
1 |
|
T5 |
11 |
|
T27 |
7 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37890 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[0] |
auto[1] |
1170 |
1 |
|
|
T11 |
10 |
|
T14 |
1 |
|
T49 |
9 |
auto[1] |
auto[0] |
15148 |
1 |
|
|
T4 |
9 |
|
T5 |
73 |
|
T6 |
14 |
auto[1] |
auto[1] |
849 |
1 |
|
|
T4 |
1 |
|
T5 |
10 |
|
T24 |
3 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38011 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[0] |
auto[1] |
1049 |
1 |
|
|
T11 |
8 |
|
T14 |
2 |
|
T49 |
2 |
auto[1] |
auto[0] |
15152 |
1 |
|
|
T4 |
9 |
|
T5 |
75 |
|
T6 |
14 |
auto[1] |
auto[1] |
845 |
1 |
|
|
T4 |
1 |
|
T5 |
8 |
|
T27 |
9 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37935 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[0] |
auto[1] |
1125 |
1 |
|
|
T11 |
6 |
|
T49 |
9 |
|
T99 |
12 |
auto[1] |
auto[0] |
15136 |
1 |
|
|
T4 |
10 |
|
T5 |
76 |
|
T6 |
14 |
auto[1] |
auto[1] |
861 |
1 |
|
|
T5 |
7 |
|
T24 |
1 |
|
T27 |
9 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37944 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[0] |
auto[1] |
1116 |
1 |
|
|
T11 |
5 |
|
T49 |
7 |
|
T99 |
2 |
auto[1] |
auto[0] |
15114 |
1 |
|
|
T4 |
10 |
|
T5 |
73 |
|
T6 |
14 |
auto[1] |
auto[1] |
883 |
1 |
|
|
T5 |
10 |
|
T27 |
9 |
|
T29 |
1 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37819 |
1 |
|
|
T1 |
73 |
|
T2 |
78 |
|
T3 |
63 |
auto[0] |
auto[1] |
1241 |
1 |
|
|
T1 |
10 |
|
T2 |
10 |
|
T3 |
7 |
auto[1] |
auto[0] |
15317 |
1 |
|
|
T4 |
10 |
|
T5 |
83 |
|
T6 |
14 |
auto[1] |
auto[1] |
680 |
1 |
|
|
T26 |
9 |
|
T29 |
9 |
|
T51 |
7 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37857 |
1 |
|
|
T1 |
76 |
|
T2 |
81 |
|
T3 |
57 |
auto[0] |
auto[1] |
1203 |
1 |
|
|
T1 |
7 |
|
T2 |
7 |
|
T3 |
13 |
auto[1] |
auto[0] |
15344 |
1 |
|
|
T4 |
10 |
|
T5 |
83 |
|
T6 |
14 |
auto[1] |
auto[1] |
653 |
1 |
|
|
T26 |
13 |
|
T29 |
13 |
|
T51 |
9 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37496 |
1 |
|
|
T1 |
83 |
|
T2 |
88 |
|
T3 |
70 |
auto[0] |
auto[1] |
1564 |
1 |
|
|
T14 |
11 |
|
T253 |
12 |
|
T107 |
15 |
auto[1] |
auto[0] |
14812 |
1 |
|
|
T5 |
83 |
|
T6 |
14 |
|
T25 |
7 |
auto[1] |
auto[1] |
1185 |
1 |
|
|
T4 |
10 |
|
T24 |
11 |
|
T28 |
10 |