Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

95520445

1

T1

24692

T2

42618

T3

24826

auto[1]

1401289

1

T1

297

T2

495

T3

297

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

95498946

1

T1

24197

T2

42321

T3

24430

auto[1]

1422788

1

T1

792

T2

792

T3

693

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7634497	1			T1	7585		T2	15386		T3	6689
auto[IdleSt]	21762659	1			T1	2873		T2	7227		T3	2511
auto[ClkMuxSt]	36156	1			T1	83		T2	88		T3	70
auto[CntIncrSt]	35909	1			T1	83		T2	88		T3	70
auto[CntProgSt]	1557576	1			T1	141		T2	992		T3	796
auto[TransCheckSt]	27969	1			T1	65		T2	68		T3	47
auto[TokenHashSt]	32608375	1			T1	1068		T2	3473		T3	3715
auto[FlashRmaSt]	29571	1			T1	49		T2	85		T3	15
auto[TokenCheck0St]	12955	1			T1	21		T2	22		T3	15
auto[TokenCheck1St]	9602	1			T1	12		T2	11		T3	9
auto[TransProgSt]	391690	1			T1	20		T2	118		T3	116
auto[PostTransSt]	12416270	1			T1	11509		T2	13816		T3	9775
auto[ScrapSt]	123394	1			T50	3		T23	14		T51	6
auto[EscalateSt]	7239824	1			T1	1480		T2	1739		T3	1295
auto[InvalidSt]	13033177	1			T11	8970		T4	7002		T14	265

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2110	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	13033177	1			T11	8970		T4	7002		T14	265
EscalateSt	7239824	1			T1	1480		T2	1739		T3	1295
ScrapSt	123394	1			T50	3		T23	14		T51	6
PostTransSt	12416270	1			T1	11509		T2	13816		T3	9775
TransProgSt	391690	1			T1	20		T2	118		T3	116
TokenCheck1St	9602	1			T1	12		T2	11		T3	9
TokenCheck0St	12955	1			T1	21		T2	22		T3	15
FlashRmaSt	29571	1			T1	49		T2	85		T3	15
TokenHashSt	32608375	1			T1	1068		T2	3473		T3	3715
TransCheckSt	27969	1			T1	65		T2	68		T3	47
CntProgSt	1557576	1			T1	141		T2	992		T3	796
CntIncrSt	35909	1			T1	83		T2	88		T3	70
ClkMuxSt	36156	1			T1	83		T2	88		T3	70
IdleSt	21762659	1			T1	2873		T2	7227		T3	2511
ResetSt	7634497	1			T1	7585		T2	15386		T3	6689
arcs[ResetSt=>IdleSt]	55314	1			T1	84		T2	89		T3	71
arcs[IdleSt=>ScrapSt]	284	1			T50	1		T23	1		T51	1
arcs[IdleSt=>ClkMuxSt]	35977	1			T1	83		T2	88		T3	70
arcs[ClkMuxSt=>CntIncrSt]	35909	1			T1	83		T2	88		T3	70
arcs[CntIncrSt=>PostTransSt]	1859	1			T1	7		T2	7		T3	13
arcs[CntIncrSt=>CntProgSt]	33989	1			T1	76		T2	81		T3	57
arcs[CntProgSt=>PostTransSt]	4900	1			T1	11		T2	13		T3	10
arcs[CntProgSt=>TransCheckSt]	27969	1			T1	65		T2	68		T3	47
arcs[TransCheckSt=>PostTransSt]	3767	1			T1	10		T2	10		T3	7
arcs[TransCheckSt=>TokenHashSt]	24076	1			T1	55		T2	58		T3	40
arcs[TokenHashSt=>PostTransSt]	10334	1			T1	34		T2	36		T3	25
arcs[TokenHashSt=>FlashRmaSt]	13063	1			T1	21		T2	22		T3	15
arcs[FlashRmaSt=>TokenCheck0St]	12955	1			T1	21		T2	22		T3	15
arcs[TokenCheck0St=>PostTransSt]	3317	1			T1	9		T2	11		T3	6
arcs[TokenCheck0St=>TokenCheck1St]	9602	1			T1	12		T2	11		T3	9
arcs[TokenCheck1St=>PostTransSt]	683	1			T1	2		T2	1		T3	2
arcs[TransProgSt=>PostTransSt]	8066	1			T1	10		T2	10		T3	7
arcs[IdleSt=>EscalateSt]	124	1			T63	9		T62	6		T64	6
arcs[ClkMuxSt=>EscalateSt]	68	1			T50	1		T48	3		T62	1
arcs[CntIncrSt=>EscalateSt]	61	1			T50	2		T48	2		T62	2
arcs[CntProgSt=>EscalateSt]	1120	1			T50	13		T48	28		T63	15
arcs[TransCheckSt=>EscalateSt]	126	1			T50	3		T63	10		T62	1
arcs[TokenHashSt=>EscalateSt]	679	1			T50	24		T48	12		T63	18
arcs[FlashRmaSt=>EscalateSt]	108	1			T50	2		T48	2		T63	4
arcs[TokenCheck0St=>EscalateSt]	36	1			T50	2		T64	1		T68	1
arcs[TokenCheck1St=>EscalateSt]	150	1			T50	3		T48	4		T63	2
arcs[TransProgSt=>EscalateSt]	703	1			T50	8		T48	13		T63	7
arcs[PostTransSt=>EscalateSt]	5142	1			T1	11		T2	13		T3	10
arcs[InvalidSt=>EscalateSt]	14642	1			T11	51		T4	4		T14	4

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7634316	1			T1	7585		T2	15386		T3	6689
auto[0]	auto[IdleSt]	21762581	1			T1	2873		T2	7227		T3	2511
auto[0]	auto[ClkMuxSt]	36110	1			T1	83		T2	88		T3	70
auto[0]	auto[CntIncrSt]	35869	1			T1	83		T2	88		T3	70
auto[0]	auto[CntProgSt]	1556843	1			T1	141		T2	992		T3	796
auto[0]	auto[TransCheckSt]	27892	1			T1	65		T2	68		T3	47
auto[0]	auto[TokenHashSt]	32607914	1			T1	1068		T2	3473		T3	3715
auto[0]	auto[FlashRmaSt]	29490	1			T1	49		T2	85		T3	15
auto[0]	auto[TokenCheck0St]	12932	1			T1	21		T2	22		T3	15
auto[0]	auto[TokenCheck1St]	9497	1			T1	12		T2	11		T3	9
auto[0]	auto[TransProgSt]	391216	1			T1	20		T2	118		T3	116
auto[0]	auto[PostTransSt]	12413710	1			T1	11506		T2	13811		T3	9772
auto[0]	auto[ScrapSt]	123355	1			T50	3		T23	14		T51	6
auto[0]	auto[EscalateSt]	5850718	1			T1	1186		T2	1249		T3	1001
auto[0]	auto[InvalidSt]	13025892	1			T11	8939		T4	6999		T14	265
auto[1]	auto[ResetSt]	181	1			T50	4		T48	1		T63	4
auto[1]	auto[IdleSt]	78	1			T63	7		T62	3		T64	2
auto[1]	auto[ClkMuxSt]	46	1			T50	1		T48	1		T62	1
auto[1]	auto[CntIncrSt]	40	1			T48	2		T62	1		T248	1
auto[1]	auto[CntProgSt]	733	1			T50	10		T48	16		T63	12
auto[1]	auto[TransCheckSt]	77	1			T50	3		T63	5		T68	1
auto[1]	auto[TokenHashSt]	461	1			T50	12		T48	8		T63	13
auto[1]	auto[FlashRmaSt]	81	1			T50	1		T48	1		T63	4
auto[1]	auto[TokenCheck0St]	23	1			T50	1		T64	1		T68	1
auto[1]	auto[TokenCheck1St]	105	1			T50	1		T48	4		T63	2
auto[1]	auto[TransProgSt]	474	1			T50	5		T48	8		T63	4
auto[1]	auto[PostTransSt]	2560	1			T1	3		T2	5		T3	3
auto[1]	auto[ScrapSt]	39	1			T62	1		T64	3		T249	1
auto[1]	auto[EscalateSt]	1389106	1			T1	294		T2	490		T3	294
auto[1]	auto[InvalidSt]	7285	1			T11	31		T4	3		T5	39

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7634317	1			T1	7585		T2	15386		T3	6689
auto[0]	auto[IdleSt]	21762581	1			T1	2873		T2	7227		T3	2511
auto[0]	auto[ClkMuxSt]	36112	1			T1	83		T2	88		T3	70
auto[0]	auto[CntIncrSt]	35867	1			T1	83		T2	88		T3	70
auto[0]	auto[CntProgSt]	1556806	1			T1	141		T2	992		T3	796
auto[0]	auto[TransCheckSt]	27879	1			T1	65		T2	68		T3	47
auto[0]	auto[TokenHashSt]	32607921	1			T1	1068		T2	3473		T3	3715
auto[0]	auto[FlashRmaSt]	29501	1			T1	49		T2	85		T3	15
auto[0]	auto[TokenCheck0St]	12934	1			T1	21		T2	22		T3	15
auto[0]	auto[TokenCheck1St]	9504	1			T1	12		T2	11		T3	9
auto[0]	auto[TransProgSt]	391242	1			T1	20		T2	118		T3	116
auto[0]	auto[PostTransSt]	12413602	1			T1	11501		T2	13808		T3	9768
auto[0]	auto[ScrapSt]	123350	1			T50	2		T23	14		T51	6
auto[0]	auto[EscalateSt]	5829400	1			T1	696		T2	955		T3	609
auto[0]	auto[InvalidSt]	13025820	1			T11	8950		T4	7001		T14	261
auto[1]	auto[ResetSt]	180	1			T50	5		T48	2		T63	3
auto[1]	auto[IdleSt]	78	1			T63	4		T62	5		T64	4
auto[1]	auto[ClkMuxSt]	44	1			T50	1		T48	2		T62	1
auto[1]	auto[CntIncrSt]	42	1			T50	2		T48	2		T62	2
auto[1]	auto[CntProgSt]	770	1			T50	7		T48	19		T63	10
auto[1]	auto[TransCheckSt]	90	1			T50	2		T63	10		T62	1
auto[1]	auto[TokenHashSt]	454	1			T50	17		T48	10		T63	11
auto[1]	auto[FlashRmaSt]	70	1			T50	1		T48	2		T63	3
auto[1]	auto[TokenCheck0St]	21	1			T50	1		T64	1		T250	2
auto[1]	auto[TokenCheck1St]	98	1			T50	2		T48	2		T63	2
auto[1]	auto[TransProgSt]	448	1			T50	5		T48	8		T63	5
auto[1]	auto[PostTransSt]	2668	1			T1	8		T2	8		T3	7
auto[1]	auto[ScrapSt]	44	1			T50	1		T63	1		T64	1
auto[1]	auto[EscalateSt]	1410424	1			T1	784		T2	784		T3	686
auto[1]	auto[InvalidSt]	7357	1			T11	20		T4	1		T14	4