Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53013 |
1 |
|
|
T1 |
43 |
|
T2 |
50 |
|
T4 |
15 |
auto[1] |
1807 |
1 |
|
|
T15 |
8 |
|
T16 |
6 |
|
T17 |
3 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54022 |
1 |
|
|
T1 |
43 |
|
T2 |
50 |
|
T4 |
15 |
auto[1] |
798 |
1 |
|
|
T14 |
19 |
|
T59 |
25 |
|
T60 |
18 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52745 |
1 |
|
|
T1 |
43 |
|
T2 |
45 |
|
T4 |
14 |
auto[1] |
2075 |
1 |
|
|
T2 |
5 |
|
T4 |
1 |
|
T11 |
2 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52791 |
1 |
|
|
T1 |
43 |
|
T2 |
45 |
|
T4 |
14 |
auto[1] |
2029 |
1 |
|
|
T2 |
5 |
|
T4 |
1 |
|
T11 |
5 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52814 |
1 |
|
|
T1 |
43 |
|
T2 |
46 |
|
T4 |
14 |
auto[1] |
2006 |
1 |
|
|
T2 |
4 |
|
T4 |
1 |
|
T11 |
2 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
50058 |
1 |
|
|
T1 |
14 |
|
T2 |
50 |
|
T4 |
6 |
no_err_inj |
4762 |
1 |
|
|
T1 |
29 |
|
T4 |
9 |
|
T13 |
7 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53102 |
1 |
|
|
T1 |
43 |
|
T2 |
50 |
|
T4 |
15 |
auto[1] |
1718 |
1 |
|
|
T15 |
12 |
|
T16 |
5 |
|
T17 |
8 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54059 |
1 |
|
|
T1 |
43 |
|
T2 |
50 |
|
T4 |
15 |
auto[1] |
761 |
1 |
|
|
T14 |
12 |
|
T59 |
12 |
|
T60 |
14 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38439 |
1 |
|
|
T1 |
30 |
|
T4 |
15 |
|
T10 |
58 |
auto[1] |
16381 |
1 |
|
|
T1 |
13 |
|
T2 |
50 |
|
T27 |
61 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52771 |
1 |
|
|
T1 |
43 |
|
T2 |
44 |
|
T4 |
13 |
auto[1] |
2049 |
1 |
|
|
T2 |
6 |
|
T4 |
2 |
|
T11 |
4 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52730 |
1 |
|
|
T1 |
43 |
|
T2 |
42 |
|
T4 |
15 |
auto[1] |
2090 |
1 |
|
|
T2 |
8 |
|
T11 |
6 |
|
T58 |
1 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52723 |
1 |
|
|
T1 |
43 |
|
T2 |
42 |
|
T4 |
15 |
auto[1] |
2097 |
1 |
|
|
T2 |
8 |
|
T11 |
10 |
|
T13 |
1 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53025 |
1 |
|
|
T1 |
43 |
|
T2 |
50 |
|
T4 |
15 |
auto[1] |
1795 |
1 |
|
|
T15 |
10 |
|
T16 |
9 |
|
T17 |
10 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52677 |
1 |
|
|
T1 |
29 |
|
T2 |
50 |
|
T4 |
15 |
auto[1] |
2143 |
1 |
|
|
T1 |
14 |
|
T48 |
13 |
|
T21 |
40 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54044 |
1 |
|
|
T1 |
43 |
|
T2 |
50 |
|
T4 |
15 |
auto[1] |
776 |
1 |
|
|
T14 |
18 |
|
T59 |
10 |
|
T60 |
15 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54058 |
1 |
|
|
T1 |
43 |
|
T2 |
50 |
|
T4 |
15 |
auto[1] |
762 |
1 |
|
|
T14 |
15 |
|
T59 |
15 |
|
T60 |
12 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54023 |
1 |
|
|
T1 |
43 |
|
T2 |
50 |
|
T4 |
15 |
auto[1] |
797 |
1 |
|
|
T14 |
18 |
|
T59 |
15 |
|
T60 |
7 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51907 |
1 |
|
|
T1 |
43 |
|
T2 |
50 |
|
T10 |
58 |
auto[1] |
2913 |
1 |
|
|
T4 |
15 |
|
T13 |
13 |
|
T58 |
12 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51142 |
1 |
|
|
T1 |
43 |
|
T2 |
50 |
|
T4 |
15 |
auto[1] |
3678 |
1 |
|
|
T10 |
58 |
|
T23 |
90 |
|
T47 |
57 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52690 |
1 |
|
|
T1 |
43 |
|
T2 |
45 |
|
T4 |
15 |
auto[1] |
2130 |
1 |
|
|
T2 |
5 |
|
T11 |
13 |
|
T84 |
8 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52690 |
1 |
|
|
T1 |
43 |
|
T2 |
45 |
|
T4 |
14 |
auto[1] |
2130 |
1 |
|
|
T2 |
5 |
|
T4 |
1 |
|
T11 |
7 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52770 |
1 |
|
|
T1 |
43 |
|
T2 |
46 |
|
T4 |
15 |
auto[1] |
2050 |
1 |
|
|
T2 |
4 |
|
T11 |
5 |
|
T13 |
1 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53041 |
1 |
|
|
T1 |
43 |
|
T2 |
50 |
|
T4 |
15 |
auto[1] |
1779 |
1 |
|
|
T15 |
6 |
|
T16 |
7 |
|
T17 |
9 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49242 |
1 |
|
|
T1 |
43 |
|
T2 |
50 |
|
T4 |
15 |
auto[1] |
5578 |
1 |
|
|
T12 |
74 |
|
T24 |
70 |
|
T15 |
8 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51165 |
1 |
|
|
T1 |
43 |
|
T2 |
50 |
|
T4 |
15 |
auto[1] |
3655 |
1 |
|
|
T25 |
80 |
|
T56 |
50 |
|
T57 |
90 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54820 |
1 |
|
|
T1 |
43 |
|
T2 |
50 |
|
T4 |
15 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53066 |
1 |
|
|
T1 |
43 |
|
T2 |
50 |
|
T4 |
15 |
auto[1] |
1754 |
1 |
|
|
T15 |
7 |
|
T16 |
3 |
|
T17 |
10 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53011 |
1 |
|
|
T1 |
43 |
|
T2 |
50 |
|
T4 |
15 |
auto[1] |
1809 |
1 |
|
|
T15 |
4 |
|
T16 |
10 |
|
T17 |
7 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53028 |
1 |
|
|
T1 |
43 |
|
T2 |
50 |
|
T4 |
15 |
auto[1] |
1792 |
1 |
|
|
T15 |
13 |
|
T16 |
6 |
|
T17 |
6 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
48609 |
1 |
|
|
T1 |
14 |
|
T2 |
50 |
|
T10 |
58 |
auto[0] |
no_err_inj |
3298 |
1 |
|
|
T1 |
29 |
|
T21 |
7 |
|
T22 |
15 |
auto[1] |
err_inj |
1449 |
1 |
|
|
T4 |
6 |
|
T13 |
6 |
|
T58 |
4 |
auto[1] |
no_err_inj |
1464 |
1 |
|
|
T4 |
9 |
|
T13 |
7 |
|
T58 |
8 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49937 |
1 |
|
|
T1 |
43 |
|
T2 |
45 |
|
T10 |
58 |
auto[0] |
auto[1] |
1970 |
1 |
|
|
T2 |
5 |
|
T11 |
7 |
|
T84 |
16 |
auto[1] |
auto[0] |
2753 |
1 |
|
|
T4 |
14 |
|
T13 |
11 |
|
T58 |
10 |
auto[1] |
auto[1] |
160 |
1 |
|
|
T4 |
1 |
|
T13 |
2 |
|
T58 |
2 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49970 |
1 |
|
|
T1 |
43 |
|
T2 |
42 |
|
T10 |
58 |
auto[0] |
auto[1] |
1937 |
1 |
|
|
T2 |
8 |
|
T11 |
6 |
|
T84 |
10 |
auto[1] |
auto[0] |
2760 |
1 |
|
|
T4 |
15 |
|
T13 |
13 |
|
T58 |
11 |
auto[1] |
auto[1] |
153 |
1 |
|
|
T58 |
1 |
|
T21 |
5 |
|
T28 |
7 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50038 |
1 |
|
|
T1 |
43 |
|
T2 |
46 |
|
T10 |
58 |
auto[0] |
auto[1] |
1869 |
1 |
|
|
T2 |
4 |
|
T11 |
5 |
|
T84 |
5 |
auto[1] |
auto[0] |
2732 |
1 |
|
|
T4 |
15 |
|
T13 |
12 |
|
T58 |
12 |
auto[1] |
auto[1] |
181 |
1 |
|
|
T13 |
1 |
|
T21 |
2 |
|
T38 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50035 |
1 |
|
|
T1 |
43 |
|
T2 |
45 |
|
T10 |
58 |
auto[0] |
auto[1] |
1872 |
1 |
|
|
T2 |
5 |
|
T11 |
5 |
|
T84 |
7 |
auto[1] |
auto[0] |
2756 |
1 |
|
|
T4 |
14 |
|
T13 |
13 |
|
T58 |
11 |
auto[1] |
auto[1] |
157 |
1 |
|
|
T4 |
1 |
|
T58 |
1 |
|
T21 |
3 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50062 |
1 |
|
|
T1 |
43 |
|
T2 |
46 |
|
T10 |
58 |
auto[0] |
auto[1] |
1845 |
1 |
|
|
T2 |
4 |
|
T11 |
2 |
|
T84 |
8 |
auto[1] |
auto[0] |
2752 |
1 |
|
|
T4 |
14 |
|
T13 |
11 |
|
T58 |
12 |
auto[1] |
auto[1] |
161 |
1 |
|
|
T4 |
1 |
|
T13 |
2 |
|
T21 |
5 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49975 |
1 |
|
|
T1 |
43 |
|
T2 |
45 |
|
T10 |
58 |
auto[0] |
auto[1] |
1932 |
1 |
|
|
T2 |
5 |
|
T11 |
2 |
|
T84 |
5 |
auto[1] |
auto[0] |
2770 |
1 |
|
|
T4 |
14 |
|
T13 |
13 |
|
T58 |
12 |
auto[1] |
auto[1] |
143 |
1 |
|
|
T4 |
1 |
|
T21 |
2 |
|
T26 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37320 |
1 |
|
|
T1 |
30 |
|
T4 |
15 |
|
T10 |
58 |
auto[0] |
auto[1] |
1119 |
1 |
|
|
T15 |
8 |
|
T16 |
6 |
|
T17 |
3 |
auto[1] |
auto[0] |
15693 |
1 |
|
|
T1 |
13 |
|
T2 |
50 |
|
T27 |
61 |
auto[1] |
auto[1] |
688 |
1 |
|
|
T28 |
14 |
|
T29 |
6 |
|
T18 |
13 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37360 |
1 |
|
|
T1 |
30 |
|
T4 |
15 |
|
T10 |
58 |
auto[0] |
auto[1] |
1079 |
1 |
|
|
T15 |
12 |
|
T16 |
5 |
|
T17 |
8 |
auto[1] |
auto[0] |
15742 |
1 |
|
|
T1 |
13 |
|
T2 |
50 |
|
T27 |
61 |
auto[1] |
auto[1] |
639 |
1 |
|
|
T28 |
18 |
|
T29 |
9 |
|
T18 |
20 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37201 |
1 |
|
|
T1 |
19 |
|
T4 |
15 |
|
T10 |
58 |
auto[0] |
auto[1] |
1238 |
1 |
|
|
T1 |
11 |
|
T48 |
13 |
|
T21 |
17 |
auto[1] |
auto[0] |
15476 |
1 |
|
|
T1 |
10 |
|
T2 |
50 |
|
T27 |
61 |
auto[1] |
auto[1] |
905 |
1 |
|
|
T1 |
3 |
|
T21 |
23 |
|
T28 |
3 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37286 |
1 |
|
|
T1 |
30 |
|
T4 |
15 |
|
T10 |
58 |
auto[0] |
auto[1] |
1153 |
1 |
|
|
T15 |
10 |
|
T16 |
9 |
|
T17 |
10 |
auto[1] |
auto[0] |
15739 |
1 |
|
|
T1 |
13 |
|
T2 |
50 |
|
T27 |
61 |
auto[1] |
auto[1] |
642 |
1 |
|
|
T28 |
17 |
|
T29 |
12 |
|
T18 |
10 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33555 |
1 |
|
|
T1 |
30 |
|
T4 |
15 |
|
T10 |
58 |
auto[0] |
auto[1] |
4884 |
1 |
|
|
T12 |
74 |
|
T24 |
70 |
|
T15 |
8 |
auto[1] |
auto[0] |
15687 |
1 |
|
|
T1 |
13 |
|
T2 |
50 |
|
T27 |
61 |
auto[1] |
auto[1] |
694 |
1 |
|
|
T28 |
14 |
|
T29 |
12 |
|
T18 |
9 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37215 |
1 |
|
|
T1 |
30 |
|
T4 |
14 |
|
T10 |
58 |
auto[0] |
auto[1] |
1224 |
1 |
|
|
T4 |
1 |
|
T11 |
7 |
|
T13 |
2 |
auto[1] |
auto[0] |
15475 |
1 |
|
|
T1 |
13 |
|
T2 |
45 |
|
T27 |
55 |
auto[1] |
auto[1] |
906 |
1 |
|
|
T2 |
5 |
|
T27 |
6 |
|
T21 |
1 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37239 |
1 |
|
|
T1 |
30 |
|
T4 |
15 |
|
T10 |
58 |
auto[0] |
auto[1] |
1200 |
1 |
|
|
T11 |
13 |
|
T84 |
8 |
|
T21 |
9 |
auto[1] |
auto[0] |
15451 |
1 |
|
|
T1 |
13 |
|
T2 |
45 |
|
T27 |
52 |
auto[1] |
auto[1] |
930 |
1 |
|
|
T2 |
5 |
|
T27 |
9 |
|
T28 |
15 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37267 |
1 |
|
|
T1 |
30 |
|
T4 |
15 |
|
T10 |
58 |
auto[0] |
auto[1] |
1172 |
1 |
|
|
T11 |
6 |
|
T58 |
1 |
|
T84 |
10 |
auto[1] |
auto[0] |
15463 |
1 |
|
|
T1 |
13 |
|
T2 |
42 |
|
T27 |
55 |
auto[1] |
auto[1] |
918 |
1 |
|
|
T2 |
8 |
|
T27 |
6 |
|
T21 |
3 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37264 |
1 |
|
|
T1 |
30 |
|
T4 |
13 |
|
T10 |
58 |
auto[0] |
auto[1] |
1175 |
1 |
|
|
T4 |
2 |
|
T11 |
4 |
|
T84 |
6 |
auto[1] |
auto[0] |
15507 |
1 |
|
|
T1 |
13 |
|
T2 |
44 |
|
T27 |
54 |
auto[1] |
auto[1] |
874 |
1 |
|
|
T2 |
6 |
|
T27 |
7 |
|
T28 |
12 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37259 |
1 |
|
|
T1 |
30 |
|
T4 |
14 |
|
T10 |
58 |
auto[0] |
auto[1] |
1180 |
1 |
|
|
T4 |
1 |
|
T11 |
5 |
|
T58 |
1 |
auto[1] |
auto[0] |
15532 |
1 |
|
|
T1 |
13 |
|
T2 |
45 |
|
T27 |
54 |
auto[1] |
auto[1] |
849 |
1 |
|
|
T2 |
5 |
|
T27 |
7 |
|
T21 |
3 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37286 |
1 |
|
|
T1 |
30 |
|
T4 |
14 |
|
T10 |
58 |
auto[0] |
auto[1] |
1153 |
1 |
|
|
T4 |
1 |
|
T11 |
2 |
|
T84 |
5 |
auto[1] |
auto[0] |
15459 |
1 |
|
|
T1 |
13 |
|
T2 |
45 |
|
T27 |
54 |
auto[1] |
auto[1] |
922 |
1 |
|
|
T2 |
5 |
|
T27 |
7 |
|
T21 |
2 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37301 |
1 |
|
|
T1 |
30 |
|
T4 |
15 |
|
T10 |
58 |
auto[0] |
auto[1] |
1138 |
1 |
|
|
T15 |
13 |
|
T16 |
6 |
|
T17 |
6 |
auto[1] |
auto[0] |
15727 |
1 |
|
|
T1 |
13 |
|
T2 |
50 |
|
T27 |
61 |
auto[1] |
auto[1] |
654 |
1 |
|
|
T28 |
19 |
|
T29 |
8 |
|
T18 |
6 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37316 |
1 |
|
|
T1 |
30 |
|
T4 |
15 |
|
T10 |
58 |
auto[0] |
auto[1] |
1123 |
1 |
|
|
T15 |
4 |
|
T16 |
10 |
|
T17 |
7 |
auto[1] |
auto[0] |
15695 |
1 |
|
|
T1 |
13 |
|
T2 |
50 |
|
T27 |
61 |
auto[1] |
auto[1] |
686 |
1 |
|
|
T28 |
19 |
|
T29 |
23 |
|
T18 |
11 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36736 |
1 |
|
|
T1 |
30 |
|
T10 |
58 |
|
T11 |
54 |
auto[0] |
auto[1] |
1703 |
1 |
|
|
T4 |
15 |
|
T13 |
13 |
|
T58 |
12 |
auto[1] |
auto[0] |
15171 |
1 |
|
|
T1 |
13 |
|
T2 |
50 |
|
T27 |
61 |
auto[1] |
auto[1] |
1210 |
1 |
|
|
T21 |
24 |
|
T28 |
61 |
|
T29 |
6 |