Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102139399

1

T1

218364

T2

167655

T3

4852

auto[1]

1432708

1

T1

888

T2

2254

T4

396

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102122738

1

T1

218757

T2

168439

T3

4852

auto[1]

1449369

1

T1

495

T2

1470

T4

198

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7899125	1			T1	4244		T2	29852		T3	78
auto[IdleSt]	21038503	1			T1	63830		T2	12351		T3	4774
auto[ClkMuxSt]	34927	1			T1	41		T9	1		T4	9
auto[CntIncrSt]	34717	1			T1	41		T9	1		T4	9
auto[CntProgSt]	1673119	1			T1	501		T9	173		T4	141
auto[TransCheckSt]	27161	1			T1	27		T9	1		T4	9
auto[TokenHashSt]	38047889	1			T1	121641		T9	28		T4	185
auto[FlashRmaSt]	27954	1			T1	72		T4	9		T10	33
auto[TokenCheck0St]	12473	1			T1	27		T4	9		T10	17
auto[TokenCheck1St]	9266	1			T1	27		T4	9		T10	17
auto[TransProgSt]	443208	1			T1	360		T4	135		T10	28
auto[PostTransSt]	12432766	1			T1	22802		T9	912		T4	1596
auto[ScrapSt]	239327	1			T1	1173		T10	3		T22	1847
auto[EscalateSt]	7471969	1			T1	4466		T2	27543		T4	1028
auto[InvalidSt]	14177551	1			T2	100155		T4	422		T11	6980

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2152	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	14177551	1			T2	100155		T4	422		T11	6980
EscalateSt	7471969	1			T1	4466		T2	27543		T4	1028
ScrapSt	239327	1			T1	1173		T10	3		T22	1847
PostTransSt	12432766	1			T1	22802		T9	912		T4	1596
TransProgSt	443208	1			T1	360		T4	135		T10	28
TokenCheck1St	9266	1			T1	27		T4	9		T10	17
TokenCheck0St	12473	1			T1	27		T4	9		T10	17
FlashRmaSt	27954	1			T1	72		T4	9		T10	33
TokenHashSt	38047889	1			T1	121641		T9	28		T4	185
TransCheckSt	27161	1			T1	27		T9	1		T4	9
CntProgSt	1673119	1			T1	501		T9	173		T4	141
CntIncrSt	34717	1			T1	41		T9	1		T4	9
ClkMuxSt	34927	1			T1	41		T9	1		T4	9
IdleSt	21038503	1			T1	63830		T2	12351		T3	4774
ResetSt	7899125	1			T1	4244		T2	29852		T3	78
arcs[ResetSt=>IdleSt]	54843	1			T1	47		T2	43		T3	1
arcs[IdleSt=>ScrapSt]	303	1			T1	2		T10	1		T22	3
arcs[IdleSt=>ClkMuxSt]	34785	1			T1	41		T9	1		T4	9
arcs[ClkMuxSt=>CntIncrSt]	34717	1			T1	41		T9	1		T4	9
arcs[CntIncrSt=>PostTransSt]	1810	1			T15	4		T16	10		T17	7
arcs[CntIncrSt=>CntProgSt]	32846	1			T1	41		T9	1		T4	9
arcs[CntProgSt=>PostTransSt]	4706	1			T1	14		T14	19		T48	13
arcs[CntProgSt=>TransCheckSt]	27161	1			T1	27		T9	1		T4	9
arcs[TransCheckSt=>PostTransSt]	3611	1			T25	42		T15	13		T16	6
arcs[TransCheckSt=>TokenHashSt]	23408	1			T1	27		T9	1		T4	9
arcs[TokenHashSt=>PostTransSt]	10062	1			T9	1		T12	74		T14	8
arcs[TokenHashSt=>FlashRmaSt]	12576	1			T1	27		T4	9		T10	19
arcs[FlashRmaSt=>TokenCheck0St]	12473	1			T1	27		T4	9		T10	17
arcs[TokenCheck0St=>PostTransSt]	3186	1			T14	8		T25	20		T15	12
arcs[TokenCheck0St=>TokenCheck1St]	9266	1			T1	27		T4	9		T10	17
arcs[TokenCheck1St=>PostTransSt]	638	1			T14	1		T25	9		T16	1
arcs[TransProgSt=>PostTransSt]	7838	1			T1	27		T4	9		T10	9
arcs[IdleSt=>EscalateSt]	189	1			T47	6		T49	8		T50	12
arcs[ClkMuxSt=>EscalateSt]	68	1			T10	1		T23	2		T47	1
arcs[CntIncrSt=>EscalateSt]	61	1			T10	1		T23	3		T47	1
arcs[CntProgSt=>EscalateSt]	979	1			T10	12		T23	15		T47	19
arcs[TransCheckSt=>EscalateSt]	142	1			T10	8		T23	6		T51	6
arcs[TokenHashSt=>EscalateSt]	770	1			T10	15		T23	31		T16	1
arcs[FlashRmaSt=>EscalateSt]	103	1			T10	2		T23	4		T47	2
arcs[TokenCheck0St=>EscalateSt]	21	1			T51	1		T53	2		T50	2
arcs[TokenCheck1St=>EscalateSt]	131	1			T10	2		T23	5		T47	5
arcs[TransProgSt=>EscalateSt]	659	1			T10	6		T23	8		T47	13
arcs[PostTransSt=>EscalateSt]	4972	1			T1	14		T10	9		T14	19
arcs[InvalidSt=>EscalateSt]	15290	1			T2	38		T4	6		T11	39

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7898934	1			T1	4244		T2	29852		T3	78
auto[0]	auto[IdleSt]	21038383	1			T1	63830		T2	12351		T3	4774
auto[0]	auto[ClkMuxSt]	34884	1			T1	41		T9	1		T4	9
auto[0]	auto[CntIncrSt]	34672	1			T1	41		T9	1		T4	9
auto[0]	auto[CntProgSt]	1672485	1			T1	501		T9	173		T4	141
auto[0]	auto[TransCheckSt]	27055	1			T1	27		T9	1		T4	9
auto[0]	auto[TokenHashSt]	38047388	1			T1	121641		T9	28		T4	185
auto[0]	auto[FlashRmaSt]	27890	1			T1	72		T4	9		T10	33
auto[0]	auto[TokenCheck0St]	12459	1			T1	27		T4	9		T10	17
auto[0]	auto[TokenCheck1St]	9179	1			T1	27		T4	9		T10	16
auto[0]	auto[TransProgSt]	442763	1			T1	360		T4	135		T10	24
auto[0]	auto[PostTransSt]	12430252	1			T1	22793		T9	912		T4	1596
auto[0]	auto[ScrapSt]	239285	1			T1	1173		T10	2		T22	1847
auto[0]	auto[EscalateSt]	6051661	1			T1	3587		T2	25312		T4	636
auto[0]	auto[InvalidSt]	14169957	1			T2	100132		T4	418		T11	6956
auto[1]	auto[ResetSt]	191	1			T10	1		T23	6		T47	2
auto[1]	auto[IdleSt]	120	1			T47	3		T49	2		T50	8
auto[1]	auto[ClkMuxSt]	43	1			T23	2		T47	1		T51	1
auto[1]	auto[CntIncrSt]	45	1			T10	1		T23	3		T47	1
auto[1]	auto[CntProgSt]	634	1			T10	8		T23	9		T47	11
auto[1]	auto[TransCheckSt]	106	1			T10	6		T23	4		T51	3
auto[1]	auto[TokenHashSt]	501	1			T10	8		T23	22		T47	2
auto[1]	auto[FlashRmaSt]	64	1			T23	2		T47	2		T51	2
auto[1]	auto[TokenCheck0St]	14	1			T51	1		T53	2		T50	1
auto[1]	auto[TokenCheck1St]	87	1			T10	1		T23	4		T47	5
auto[1]	auto[TransProgSt]	445	1			T10	4		T23	6		T47	8
auto[1]	auto[PostTransSt]	2514	1			T1	9		T10	7		T14	8
auto[1]	auto[ScrapSt]	42	1			T10	1		T47	1		T228	1
auto[1]	auto[EscalateSt]	1420308	1			T1	879		T2	2231		T4	392
auto[1]	auto[InvalidSt]	7594	1			T2	23		T4	4		T11	24

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7898949	1			T1	4244		T2	29852		T3	78
auto[0]	auto[IdleSt]	21038371	1			T1	63830		T2	12351		T3	4774
auto[0]	auto[ClkMuxSt]	34877	1			T1	41		T9	1		T4	9
auto[0]	auto[CntIncrSt]	34679	1			T1	41		T9	1		T4	9
auto[0]	auto[CntProgSt]	1672471	1			T1	501		T9	173		T4	141
auto[0]	auto[TransCheckSt]	27076	1			T1	27		T9	1		T4	9
auto[0]	auto[TokenHashSt]	38047369	1			T1	121641		T9	28		T4	185
auto[0]	auto[FlashRmaSt]	27880	1			T1	72		T4	9		T10	31
auto[0]	auto[TokenCheck0St]	12459	1			T1	27		T4	9		T10	17
auto[0]	auto[TokenCheck1St]	9178	1			T1	27		T4	9		T10	16
auto[0]	auto[TransProgSt]	442765	1			T1	360		T4	135		T10	24
auto[0]	auto[PostTransSt]	12430229	1			T1	22797		T9	912		T4	1596
auto[0]	auto[ScrapSt]	239286	1			T1	1173		T10	3		T22	1847
auto[0]	auto[EscalateSt]	6035142	1			T1	3976		T2	26088		T4	832
auto[0]	auto[InvalidSt]	14169855	1			T2	100140		T4	420		T11	6965
auto[1]	auto[ResetSt]	176	1			T23	2		T47	2		T51	5
auto[1]	auto[IdleSt]	132	1			T47	5		T49	6		T50	9
auto[1]	auto[ClkMuxSt]	50	1			T10	1		T51	2		T229	1
auto[1]	auto[CntIncrSt]	38	1			T10	1		T23	3		T47	1
auto[1]	auto[CntProgSt]	648	1			T10	9		T23	10		T47	13
auto[1]	auto[TransCheckSt]	85	1			T10	4		T23	3		T51	5
auto[1]	auto[TokenHashSt]	520	1			T10	10		T23	22		T16	1
auto[1]	auto[FlashRmaSt]	74	1			T10	2		T23	3		T47	1
auto[1]	auto[TokenCheck0St]	14	1			T51	1		T53	1		T50	1
auto[1]	auto[TokenCheck1St]	88	1			T10	1		T23	3		T47	4
auto[1]	auto[TransProgSt]	443	1			T10	4		T23	5		T47	8
auto[1]	auto[PostTransSt]	2537	1			T1	5		T10	6		T14	11
auto[1]	auto[ScrapSt]	41	1			T47	1		T51	2		T228	1
auto[1]	auto[EscalateSt]	1436827	1			T1	490		T2	1455		T4	196
auto[1]	auto[InvalidSt]	7696	1			T2	15		T4	2		T11	15