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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.22 97.92 95.66 93.38 100.00 98.52 98.76 96.29


Total test records in report: 999
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T809 /workspace/coverage/default/17.lc_ctrl_jtag_errors.3161490384 Jun 21 06:29:21 PM PDT 24 Jun 21 06:30:04 PM PDT 24 15680032952 ps
T810 /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1257018538 Jun 21 06:28:44 PM PDT 24 Jun 21 06:29:29 PM PDT 24 4086204311 ps
T811 /workspace/coverage/default/9.lc_ctrl_state_post_trans.577692508 Jun 21 06:29:21 PM PDT 24 Jun 21 06:29:30 PM PDT 24 96784598 ps
T812 /workspace/coverage/default/23.lc_ctrl_sec_mubi.2888586992 Jun 21 06:29:58 PM PDT 24 Jun 21 06:30:17 PM PDT 24 507404299 ps
T813 /workspace/coverage/default/19.lc_ctrl_jtag_access.3865926345 Jun 21 06:29:44 PM PDT 24 Jun 21 06:29:47 PM PDT 24 241554018 ps
T814 /workspace/coverage/default/44.lc_ctrl_errors.2425498327 Jun 21 06:30:38 PM PDT 24 Jun 21 06:30:57 PM PDT 24 375744962 ps
T815 /workspace/coverage/default/22.lc_ctrl_security_escalation.3525175032 Jun 21 06:29:54 PM PDT 24 Jun 21 06:30:03 PM PDT 24 293532319 ps
T816 /workspace/coverage/default/31.lc_ctrl_prog_failure.2887363165 Jun 21 06:30:00 PM PDT 24 Jun 21 06:30:06 PM PDT 24 68880713 ps
T817 /workspace/coverage/default/8.lc_ctrl_prog_failure.3751471244 Jun 21 06:29:06 PM PDT 24 Jun 21 06:29:11 PM PDT 24 144008732 ps
T818 /workspace/coverage/default/36.lc_ctrl_sec_mubi.167138988 Jun 21 06:30:17 PM PDT 24 Jun 21 06:30:32 PM PDT 24 5114108278 ps
T819 /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2123764499 Jun 21 06:29:25 PM PDT 24 Jun 21 06:29:28 PM PDT 24 56238008 ps
T820 /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3470029087 Jun 21 06:29:56 PM PDT 24 Jun 21 06:29:59 PM PDT 24 12502911 ps
T821 /workspace/coverage/default/0.lc_ctrl_sec_mubi.1709189351 Jun 21 06:28:53 PM PDT 24 Jun 21 06:29:14 PM PDT 24 882973948 ps
T822 /workspace/coverage/default/22.lc_ctrl_jtag_access.353910866 Jun 21 06:29:52 PM PDT 24 Jun 21 06:30:04 PM PDT 24 409580469 ps
T823 /workspace/coverage/default/15.lc_ctrl_alert_test.231704526 Jun 21 06:29:36 PM PDT 24 Jun 21 06:29:39 PM PDT 24 55562573 ps
T824 /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3332691783 Jun 21 06:28:48 PM PDT 24 Jun 21 06:28:50 PM PDT 24 50535818 ps
T825 /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1839200515 Jun 21 06:29:10 PM PDT 24 Jun 21 06:29:24 PM PDT 24 299892665 ps
T826 /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2599113813 Jun 21 06:29:08 PM PDT 24 Jun 21 06:29:18 PM PDT 24 224093630 ps
T827 /workspace/coverage/default/33.lc_ctrl_sec_token_digest.4010540435 Jun 21 06:30:18 PM PDT 24 Jun 21 06:30:32 PM PDT 24 728366830 ps
T828 /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3859065352 Jun 21 06:30:49 PM PDT 24 Jun 21 06:30:51 PM PDT 24 11624637 ps
T829 /workspace/coverage/default/43.lc_ctrl_alert_test.3629890876 Jun 21 06:30:38 PM PDT 24 Jun 21 06:30:41 PM PDT 24 17627490 ps
T830 /workspace/coverage/default/7.lc_ctrl_state_failure.1297682058 Jun 21 06:28:58 PM PDT 24 Jun 21 06:29:24 PM PDT 24 1105593391 ps
T831 /workspace/coverage/default/23.lc_ctrl_smoke.1013204904 Jun 21 06:29:58 PM PDT 24 Jun 21 06:30:01 PM PDT 24 213606160 ps
T832 /workspace/coverage/default/36.lc_ctrl_jtag_access.3801579587 Jun 21 06:30:20 PM PDT 24 Jun 21 06:30:25 PM PDT 24 84968662 ps
T158 /workspace/coverage/default/16.lc_ctrl_errors.351410676 Jun 21 06:29:28 PM PDT 24 Jun 21 06:29:45 PM PDT 24 2551085936 ps
T833 /workspace/coverage/default/27.lc_ctrl_state_failure.1425359295 Jun 21 06:29:53 PM PDT 24 Jun 21 06:30:20 PM PDT 24 238570357 ps
T834 /workspace/coverage/default/19.lc_ctrl_alert_test.947002175 Jun 21 06:29:47 PM PDT 24 Jun 21 06:29:50 PM PDT 24 17977379 ps
T835 /workspace/coverage/default/9.lc_ctrl_jtag_errors.547042569 Jun 21 06:29:17 PM PDT 24 Jun 21 06:29:50 PM PDT 24 2168520661 ps
T148 /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.1938352497 Jun 21 06:30:17 PM PDT 24 Jun 21 06:44:29 PM PDT 24 112082251306 ps
T836 /workspace/coverage/default/29.lc_ctrl_stress_all.776124858 Jun 21 06:30:04 PM PDT 24 Jun 21 06:37:03 PM PDT 24 24631179984 ps
T837 /workspace/coverage/default/41.lc_ctrl_security_escalation.3569893840 Jun 21 06:30:21 PM PDT 24 Jun 21 06:30:38 PM PDT 24 373533233 ps
T838 /workspace/coverage/default/48.lc_ctrl_alert_test.902143949 Jun 21 06:30:43 PM PDT 24 Jun 21 06:30:47 PM PDT 24 18584037 ps
T839 /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.316707548 Jun 21 06:28:58 PM PDT 24 Jun 21 06:29:27 PM PDT 24 970912675 ps
T840 /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.4070225610 Jun 21 06:30:35 PM PDT 24 Jun 21 06:30:38 PM PDT 24 15422011 ps
T841 /workspace/coverage/default/27.lc_ctrl_stress_all.2613154940 Jun 21 06:29:54 PM PDT 24 Jun 21 06:31:53 PM PDT 24 5788895954 ps
T842 /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3190906300 Jun 21 06:29:06 PM PDT 24 Jun 21 06:29:17 PM PDT 24 288079470 ps
T149 /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.4264911291 Jun 21 06:29:47 PM PDT 24 Jun 21 06:38:34 PM PDT 24 27581493043 ps
T843 /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2473448271 Jun 21 06:29:12 PM PDT 24 Jun 21 06:29:33 PM PDT 24 4170169554 ps
T844 /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.566836945 Jun 21 06:30:41 PM PDT 24 Jun 21 06:30:45 PM PDT 24 23124406 ps
T845 /workspace/coverage/default/32.lc_ctrl_security_escalation.519886241 Jun 21 06:30:01 PM PDT 24 Jun 21 06:30:11 PM PDT 24 635407653 ps
T846 /workspace/coverage/default/8.lc_ctrl_state_failure.2474655404 Jun 21 06:29:08 PM PDT 24 Jun 21 06:29:33 PM PDT 24 1127038094 ps
T847 /workspace/coverage/default/45.lc_ctrl_alert_test.1228877509 Jun 21 06:30:41 PM PDT 24 Jun 21 06:30:45 PM PDT 24 77053421 ps
T848 /workspace/coverage/default/8.lc_ctrl_jtag_priority.3822034112 Jun 21 06:29:02 PM PDT 24 Jun 21 06:29:07 PM PDT 24 853985832 ps
T849 /workspace/coverage/default/1.lc_ctrl_jtag_priority.2011595581 Jun 21 06:28:49 PM PDT 24 Jun 21 06:29:05 PM PDT 24 1388180855 ps
T850 /workspace/coverage/default/46.lc_ctrl_sec_token_digest.2148102873 Jun 21 06:30:42 PM PDT 24 Jun 21 06:30:57 PM PDT 24 317303793 ps
T851 /workspace/coverage/default/37.lc_ctrl_state_post_trans.745207620 Jun 21 06:30:36 PM PDT 24 Jun 21 06:30:46 PM PDT 24 49294526 ps
T852 /workspace/coverage/default/18.lc_ctrl_state_failure.183887681 Jun 21 06:29:40 PM PDT 24 Jun 21 06:30:04 PM PDT 24 1151198286 ps
T853 /workspace/coverage/default/42.lc_ctrl_stress_all.1256584771 Jun 21 06:30:37 PM PDT 24 Jun 21 06:31:24 PM PDT 24 3001057812 ps
T854 /workspace/coverage/default/34.lc_ctrl_security_escalation.867178373 Jun 21 06:30:15 PM PDT 24 Jun 21 06:30:36 PM PDT 24 1098635752 ps
T855 /workspace/coverage/default/34.lc_ctrl_state_failure.1453097189 Jun 21 06:30:17 PM PDT 24 Jun 21 06:30:43 PM PDT 24 224076100 ps
T856 /workspace/coverage/default/6.lc_ctrl_jtag_smoke.4004760971 Jun 21 06:28:58 PM PDT 24 Jun 21 06:29:02 PM PDT 24 539066708 ps
T857 /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1382740690 Jun 21 06:30:05 PM PDT 24 Jun 21 06:30:15 PM PDT 24 173073343 ps
T858 /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.661319861 Jun 21 06:29:01 PM PDT 24 Jun 21 06:29:11 PM PDT 24 2647629812 ps
T859 /workspace/coverage/default/9.lc_ctrl_security_escalation.2965606543 Jun 21 06:29:27 PM PDT 24 Jun 21 06:29:39 PM PDT 24 414776700 ps
T860 /workspace/coverage/default/32.lc_ctrl_sec_token_mux.2801708094 Jun 21 06:30:07 PM PDT 24 Jun 21 06:30:17 PM PDT 24 1393651248 ps
T861 /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2808448488 Jun 21 06:29:06 PM PDT 24 Jun 21 06:29:10 PM PDT 24 899906605 ps
T862 /workspace/coverage/default/1.lc_ctrl_sec_token_mux.1089188824 Jun 21 06:28:50 PM PDT 24 Jun 21 06:28:59 PM PDT 24 505012939 ps
T863 /workspace/coverage/default/1.lc_ctrl_state_failure.3556108533 Jun 21 06:28:40 PM PDT 24 Jun 21 06:29:07 PM PDT 24 1110726740 ps
T864 /workspace/coverage/default/44.lc_ctrl_sec_mubi.4063114063 Jun 21 06:30:29 PM PDT 24 Jun 21 06:30:45 PM PDT 24 894753236 ps
T865 /workspace/coverage/default/33.lc_ctrl_security_escalation.4062508690 Jun 21 06:30:04 PM PDT 24 Jun 21 06:30:16 PM PDT 24 543754476 ps
T866 /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1372029255 Jun 21 06:29:54 PM PDT 24 Jun 21 06:30:09 PM PDT 24 673496312 ps
T867 /workspace/coverage/default/47.lc_ctrl_prog_failure.2967263189 Jun 21 06:30:46 PM PDT 24 Jun 21 06:30:51 PM PDT 24 602388187 ps
T868 /workspace/coverage/default/9.lc_ctrl_jtag_access.1243988325 Jun 21 06:29:15 PM PDT 24 Jun 21 06:29:23 PM PDT 24 822169199 ps
T869 /workspace/coverage/default/26.lc_ctrl_errors.784637194 Jun 21 06:29:56 PM PDT 24 Jun 21 06:30:11 PM PDT 24 1225348899 ps
T118 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3475413965 Jun 21 06:25:31 PM PDT 24 Jun 21 06:25:34 PM PDT 24 215544182 ps
T110 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3912167118 Jun 21 06:25:34 PM PDT 24 Jun 21 06:25:38 PM PDT 24 46317429 ps
T123 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.198737652 Jun 21 06:25:38 PM PDT 24 Jun 21 06:25:40 PM PDT 24 44564506 ps
T119 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.149145927 Jun 21 06:25:33 PM PDT 24 Jun 21 06:25:35 PM PDT 24 34519284 ps
T870 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2702272961 Jun 21 06:25:24 PM PDT 24 Jun 21 06:25:27 PM PDT 24 52750061 ps
T111 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.4081974365 Jun 21 06:25:47 PM PDT 24 Jun 21 06:25:54 PM PDT 24 205373651 ps
T120 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3830246797 Jun 21 06:25:17 PM PDT 24 Jun 21 06:25:19 PM PDT 24 68574349 ps
T139 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3905508154 Jun 21 06:25:41 PM PDT 24 Jun 21 06:25:47 PM PDT 24 315265461 ps
T112 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3728306331 Jun 21 06:25:42 PM PDT 24 Jun 21 06:25:47 PM PDT 24 451928144 ps
T871 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1693715501 Jun 21 06:25:27 PM PDT 24 Jun 21 06:25:34 PM PDT 24 2493484034 ps
T138 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3294444126 Jun 21 06:25:34 PM PDT 24 Jun 21 06:25:37 PM PDT 24 29852040 ps
T872 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3139537255 Jun 21 06:25:46 PM PDT 24 Jun 21 06:25:50 PM PDT 24 63019643 ps
T150 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3304229960 Jun 21 06:25:18 PM PDT 24 Jun 21 06:25:20 PM PDT 24 179461935 ps
T115 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.779810418 Jun 21 06:25:26 PM PDT 24 Jun 21 06:25:31 PM PDT 24 465023403 ps
T873 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1440729594 Jun 21 06:25:18 PM PDT 24 Jun 21 06:25:21 PM PDT 24 58155886 ps
T117 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.651520983 Jun 21 06:25:53 PM PDT 24 Jun 21 06:25:59 PM PDT 24 410022157 ps
T213 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1680826573 Jun 21 06:25:15 PM PDT 24 Jun 21 06:25:17 PM PDT 24 26919882 ps
T874 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3497772301 Jun 21 06:25:30 PM PDT 24 Jun 21 06:25:32 PM PDT 24 20989881 ps
T875 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4234594259 Jun 21 06:25:33 PM PDT 24 Jun 21 06:25:37 PM PDT 24 47121049 ps
T151 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1406719859 Jun 21 06:25:37 PM PDT 24 Jun 21 06:25:39 PM PDT 24 37218251 ps
T122 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3854389572 Jun 21 06:25:46 PM PDT 24 Jun 21 06:25:50 PM PDT 24 145961006 ps
T876 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1811005805 Jun 21 06:25:33 PM PDT 24 Jun 21 06:25:58 PM PDT 24 974563582 ps
T877 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.4185374390 Jun 21 06:25:37 PM PDT 24 Jun 21 06:25:56 PM PDT 24 1926049111 ps
T878 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3445687780 Jun 21 06:25:40 PM PDT 24 Jun 21 06:25:42 PM PDT 24 643646956 ps
T116 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3547147940 Jun 21 06:25:39 PM PDT 24 Jun 21 06:25:42 PM PDT 24 265281765 ps
T201 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3518628542 Jun 21 06:25:36 PM PDT 24 Jun 21 06:25:38 PM PDT 24 17963662 ps
T126 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3897732216 Jun 21 06:25:46 PM PDT 24 Jun 21 06:25:51 PM PDT 24 95907790 ps
T214 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.600712316 Jun 21 06:25:23 PM PDT 24 Jun 21 06:25:25 PM PDT 24 78333172 ps
T879 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2419181603 Jun 21 06:25:17 PM PDT 24 Jun 21 06:25:25 PM PDT 24 736645719 ps
T880 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3153043500 Jun 21 06:25:33 PM PDT 24 Jun 21 06:25:45 PM PDT 24 1894128321 ps
T881 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2815398959 Jun 21 06:25:39 PM PDT 24 Jun 21 06:26:10 PM PDT 24 8215097957 ps
T160 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3731940946 Jun 21 06:25:26 PM PDT 24 Jun 21 06:25:29 PM PDT 24 221018619 ps
T152 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.4145841396 Jun 21 06:25:43 PM PDT 24 Jun 21 06:25:45 PM PDT 24 221709843 ps
T129 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1830460968 Jun 21 06:25:46 PM PDT 24 Jun 21 06:25:51 PM PDT 24 33638242 ps
T170 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3238111723 Jun 21 06:25:26 PM PDT 24 Jun 21 06:25:29 PM PDT 24 47914726 ps
T215 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3724217099 Jun 21 06:25:24 PM PDT 24 Jun 21 06:25:26 PM PDT 24 18149892 ps
T135 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.4020869060 Jun 21 06:25:24 PM PDT 24 Jun 21 06:25:28 PM PDT 24 231276334 ps
T882 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2653150487 Jun 21 06:25:28 PM PDT 24 Jun 21 06:25:31 PM PDT 24 102308745 ps
T883 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4052454908 Jun 21 06:25:31 PM PDT 24 Jun 21 06:25:33 PM PDT 24 58219375 ps
T216 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3719987403 Jun 21 06:25:31 PM PDT 24 Jun 21 06:25:34 PM PDT 24 160601555 ps
T153 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.663704805 Jun 21 06:25:42 PM PDT 24 Jun 21 06:25:44 PM PDT 24 17370143 ps
T884 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1131870085 Jun 21 06:25:17 PM PDT 24 Jun 21 06:25:21 PM PDT 24 123473562 ps
T202 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3313175881 Jun 21 06:25:46 PM PDT 24 Jun 21 06:25:49 PM PDT 24 33693981 ps
T885 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1344782008 Jun 21 06:25:32 PM PDT 24 Jun 21 06:25:38 PM PDT 24 586969203 ps
T171 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1591120881 Jun 21 06:25:27 PM PDT 24 Jun 21 06:25:30 PM PDT 24 70483904 ps
T124 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.625833327 Jun 21 06:25:45 PM PDT 24 Jun 21 06:25:51 PM PDT 24 691871621 ps
T886 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.948021849 Jun 21 06:25:41 PM PDT 24 Jun 21 06:25:43 PM PDT 24 107589897 ps
T887 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.618015847 Jun 21 06:25:33 PM PDT 24 Jun 21 06:25:37 PM PDT 24 396976140 ps
T217 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1054805135 Jun 21 06:25:40 PM PDT 24 Jun 21 06:25:42 PM PDT 24 17884596 ps
T203 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1658863778 Jun 21 06:25:33 PM PDT 24 Jun 21 06:25:35 PM PDT 24 34995807 ps
T888 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4139793602 Jun 21 06:25:32 PM PDT 24 Jun 21 06:25:34 PM PDT 24 15890555 ps
T227 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.4023120512 Jun 21 06:25:45 PM PDT 24 Jun 21 06:25:51 PM PDT 24 438255912 ps
T889 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.819578614 Jun 21 06:25:37 PM PDT 24 Jun 21 06:25:40 PM PDT 24 152832627 ps
T128 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.456712371 Jun 21 06:25:48 PM PDT 24 Jun 21 06:25:53 PM PDT 24 46429059 ps
T890 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2095355475 Jun 21 06:25:39 PM PDT 24 Jun 21 06:25:41 PM PDT 24 43975302 ps
T891 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3902903556 Jun 21 06:25:31 PM PDT 24 Jun 21 06:25:33 PM PDT 24 26639144 ps
T204 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1343987813 Jun 21 06:25:24 PM PDT 24 Jun 21 06:25:26 PM PDT 24 345404431 ps
T218 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2909485107 Jun 21 06:25:38 PM PDT 24 Jun 21 06:25:40 PM PDT 24 35819037 ps
T892 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2619962851 Jun 21 06:25:32 PM PDT 24 Jun 21 06:25:36 PM PDT 24 256824775 ps
T219 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1691399533 Jun 21 06:25:49 PM PDT 24 Jun 21 06:25:52 PM PDT 24 27809280 ps
T893 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2857462519 Jun 21 06:25:17 PM PDT 24 Jun 21 06:25:19 PM PDT 24 59449368 ps
T894 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3924360289 Jun 21 06:25:25 PM PDT 24 Jun 21 06:25:27 PM PDT 24 44529464 ps
T895 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.197562126 Jun 21 06:25:16 PM PDT 24 Jun 21 06:25:20 PM PDT 24 105958313 ps
T125 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2792886619 Jun 21 06:25:31 PM PDT 24 Jun 21 06:25:34 PM PDT 24 543835144 ps
T133 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.4173186606 Jun 21 06:25:45 PM PDT 24 Jun 21 06:25:52 PM PDT 24 835309082 ps
T896 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3938306745 Jun 21 06:25:31 PM PDT 24 Jun 21 06:25:39 PM PDT 24 2478054164 ps
T897 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.985913867 Jun 21 06:25:28 PM PDT 24 Jun 21 06:25:33 PM PDT 24 239001860 ps
T898 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.4227223636 Jun 21 06:25:46 PM PDT 24 Jun 21 06:25:51 PM PDT 24 22803542 ps
T899 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.59865380 Jun 21 06:25:25 PM PDT 24 Jun 21 06:25:27 PM PDT 24 48154065 ps
T900 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.908605775 Jun 21 06:25:33 PM PDT 24 Jun 21 06:25:41 PM PDT 24 4058208062 ps
T901 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2927800294 Jun 21 06:25:37 PM PDT 24 Jun 21 06:25:40 PM PDT 24 107344914 ps
T902 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2225126794 Jun 21 06:25:19 PM PDT 24 Jun 21 06:25:27 PM PDT 24 1000248350 ps
T903 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2711376818 Jun 21 06:25:43 PM PDT 24 Jun 21 06:25:46 PM PDT 24 89194090 ps
T904 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2778903391 Jun 21 06:25:38 PM PDT 24 Jun 21 06:25:51 PM PDT 24 2043367334 ps
T205 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.4061134115 Jun 21 06:25:40 PM PDT 24 Jun 21 06:25:43 PM PDT 24 11934650 ps
T905 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1970238737 Jun 21 06:25:32 PM PDT 24 Jun 21 06:25:35 PM PDT 24 284235400 ps
T906 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1268290466 Jun 21 06:25:39 PM PDT 24 Jun 21 06:25:53 PM PDT 24 2407901060 ps
T907 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1227928947 Jun 21 06:25:46 PM PDT 24 Jun 21 06:25:50 PM PDT 24 31140789 ps
T134 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.385952023 Jun 21 06:25:36 PM PDT 24 Jun 21 06:25:40 PM PDT 24 689839713 ps
T908 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.300519562 Jun 21 06:25:42 PM PDT 24 Jun 21 06:25:45 PM PDT 24 31775887 ps
T909 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3807430291 Jun 21 06:25:45 PM PDT 24 Jun 21 06:25:52 PM PDT 24 103635076 ps
T910 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3804716012 Jun 21 06:25:44 PM PDT 24 Jun 21 06:25:47 PM PDT 24 273717930 ps
T911 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1331613933 Jun 21 06:25:42 PM PDT 24 Jun 21 06:25:47 PM PDT 24 173193697 ps
T912 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1361048692 Jun 21 06:25:24 PM PDT 24 Jun 21 06:25:26 PM PDT 24 125529161 ps
T913 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2382596842 Jun 21 06:25:42 PM PDT 24 Jun 21 06:25:45 PM PDT 24 83381015 ps
T914 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3303192417 Jun 21 06:25:37 PM PDT 24 Jun 21 06:25:42 PM PDT 24 107937814 ps
T915 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3049840952 Jun 21 06:25:17 PM PDT 24 Jun 21 06:25:19 PM PDT 24 75892909 ps
T916 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2575196593 Jun 21 06:25:46 PM PDT 24 Jun 21 06:25:50 PM PDT 24 19389157 ps
T917 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2486370206 Jun 21 06:25:46 PM PDT 24 Jun 21 06:25:50 PM PDT 24 33066397 ps
T918 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1878572563 Jun 21 06:25:24 PM PDT 24 Jun 21 06:25:27 PM PDT 24 27529193 ps
T919 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2412922554 Jun 21 06:25:43 PM PDT 24 Jun 21 06:25:45 PM PDT 24 14065313 ps
T920 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3369817592 Jun 21 06:25:18 PM PDT 24 Jun 21 06:25:23 PM PDT 24 268670708 ps
T921 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.342083251 Jun 21 06:25:42 PM PDT 24 Jun 21 06:25:46 PM PDT 24 77692550 ps
T922 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.882347643 Jun 21 06:25:47 PM PDT 24 Jun 21 06:25:51 PM PDT 24 13878501 ps
T923 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3720958114 Jun 21 06:25:30 PM PDT 24 Jun 21 06:25:32 PM PDT 24 175139869 ps
T924 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2032449483 Jun 21 06:25:20 PM PDT 24 Jun 21 06:25:22 PM PDT 24 87896378 ps
T925 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1257511702 Jun 21 06:25:31 PM PDT 24 Jun 21 06:25:34 PM PDT 24 19836284 ps
T926 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3733751827 Jun 21 06:25:27 PM PDT 24 Jun 21 06:25:30 PM PDT 24 89150905 ps
T927 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3159032136 Jun 21 06:25:45 PM PDT 24 Jun 21 06:25:47 PM PDT 24 88465019 ps
T928 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.4001831722 Jun 21 06:25:24 PM PDT 24 Jun 21 06:25:26 PM PDT 24 230154970 ps
T929 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1347265339 Jun 21 06:25:19 PM PDT 24 Jun 21 06:25:22 PM PDT 24 379999198 ps
T930 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.308204415 Jun 21 06:25:48 PM PDT 24 Jun 21 06:25:52 PM PDT 24 23536176 ps
T931 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.230261143 Jun 21 06:25:33 PM PDT 24 Jun 21 06:25:37 PM PDT 24 187895867 ps
T932 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1654041471 Jun 21 06:25:40 PM PDT 24 Jun 21 06:25:46 PM PDT 24 1511959995 ps
T933 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3088519285 Jun 21 06:25:42 PM PDT 24 Jun 21 06:25:46 PM PDT 24 148349913 ps
T934 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2355537001 Jun 21 06:25:17 PM PDT 24 Jun 21 06:25:19 PM PDT 24 34665315 ps
T935 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3696538714 Jun 21 06:25:23 PM PDT 24 Jun 21 06:25:27 PM PDT 24 55056554 ps
T936 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1008232166 Jun 21 06:25:40 PM PDT 24 Jun 21 06:25:43 PM PDT 24 40219603 ps
T937 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2545734888 Jun 21 06:25:40 PM PDT 24 Jun 21 06:25:43 PM PDT 24 21112978 ps
T127 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3639159335 Jun 21 06:25:45 PM PDT 24 Jun 21 06:25:48 PM PDT 24 67205794 ps
T938 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1200486813 Jun 21 06:25:45 PM PDT 24 Jun 21 06:25:49 PM PDT 24 148308757 ps
T939 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.998819487 Jun 21 06:25:33 PM PDT 24 Jun 21 06:25:36 PM PDT 24 24034111 ps
T131 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1951609080 Jun 21 06:25:24 PM PDT 24 Jun 21 06:25:29 PM PDT 24 285238924 ps
T940 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1960857683 Jun 21 06:25:46 PM PDT 24 Jun 21 06:25:50 PM PDT 24 54701626 ps
T941 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1466046211 Jun 21 06:25:37 PM PDT 24 Jun 21 06:25:38 PM PDT 24 38522927 ps
T942 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2395251716 Jun 21 06:25:25 PM PDT 24 Jun 21 06:25:29 PM PDT 24 1065695176 ps
T943 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.616816022 Jun 21 06:25:33 PM PDT 24 Jun 21 06:25:36 PM PDT 24 98358295 ps
T944 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3531035304 Jun 21 06:25:17 PM PDT 24 Jun 21 06:25:19 PM PDT 24 30523857 ps
T945 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.4054461231 Jun 21 06:25:39 PM PDT 24 Jun 21 06:25:41 PM PDT 24 61207767 ps
T946 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1604050049 Jun 21 06:25:36 PM PDT 24 Jun 21 06:26:03 PM PDT 24 1179729405 ps
T947 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2022439200 Jun 21 06:25:42 PM PDT 24 Jun 21 06:25:44 PM PDT 24 52677997 ps
T948 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1948366588 Jun 21 06:25:44 PM PDT 24 Jun 21 06:25:46 PM PDT 24 18927337 ps
T206 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2654485910 Jun 21 06:25:19 PM PDT 24 Jun 21 06:25:22 PM PDT 24 50183959 ps
T949 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3109984239 Jun 21 06:25:46 PM PDT 24 Jun 21 06:25:50 PM PDT 24 21445544 ps
T207 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3248468399 Jun 21 06:25:25 PM PDT 24 Jun 21 06:25:27 PM PDT 24 14307990 ps
T136 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2389328197 Jun 21 06:25:39 PM PDT 24 Jun 21 06:25:44 PM PDT 24 401198244 ps
T130 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4026146626 Jun 21 06:25:34 PM PDT 24 Jun 21 06:25:39 PM PDT 24 79635426 ps
T950 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1470483601 Jun 21 06:25:23 PM PDT 24 Jun 21 06:25:30 PM PDT 24 1948937867 ps
T121 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2069979442 Jun 21 06:25:19 PM PDT 24 Jun 21 06:25:23 PM PDT 24 243670418 ps
T951 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1242181909 Jun 21 06:25:37 PM PDT 24 Jun 21 06:25:41 PM PDT 24 71644066 ps
T952 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3017939321 Jun 21 06:25:42 PM PDT 24 Jun 21 06:25:44 PM PDT 24 24203988 ps
T953 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3506128672 Jun 21 06:25:30 PM PDT 24 Jun 21 06:25:32 PM PDT 24 51009710 ps
T208 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.692856444 Jun 21 06:25:31 PM PDT 24 Jun 21 06:25:33 PM PDT 24 184502195 ps
T954 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3465638178 Jun 21 06:25:43 PM PDT 24 Jun 21 06:25:45 PM PDT 24 98608319 ps
T955 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2063113033 Jun 21 06:25:40 PM PDT 24 Jun 21 06:25:43 PM PDT 24 168814188 ps
T956 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2908372361 Jun 21 06:25:42 PM PDT 24 Jun 21 06:25:45 PM PDT 24 29763528 ps
T957 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.618944974 Jun 21 06:25:32 PM PDT 24 Jun 21 06:25:35 PM PDT 24 418066047 ps
T958 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.809623407 Jun 21 06:25:47 PM PDT 24 Jun 21 06:25:51 PM PDT 24 31358396 ps
T959 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3053504444 Jun 21 06:25:30 PM PDT 24 Jun 21 06:25:32 PM PDT 24 23217166 ps
T209 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3068352084 Jun 21 06:25:19 PM PDT 24 Jun 21 06:25:21 PM PDT 24 20128342 ps
T960 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2464240870 Jun 21 06:25:25 PM PDT 24 Jun 21 06:25:27 PM PDT 24 45418554 ps
T961 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.135766804 Jun 21 06:25:43 PM PDT 24 Jun 21 06:25:45 PM PDT 24 1053317600 ps
T962 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1353787056 Jun 21 06:25:34 PM PDT 24 Jun 21 06:25:41 PM PDT 24 538335639 ps
T963 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.539435414 Jun 21 06:25:30 PM PDT 24 Jun 21 06:25:32 PM PDT 24 19547873 ps
T964 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4204873856 Jun 21 06:25:30 PM PDT 24 Jun 21 06:25:34 PM PDT 24 195184656 ps
T965 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3494208289 Jun 21 06:25:34 PM PDT 24 Jun 21 06:25:40 PM PDT 24 702127765 ps
T966 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.4230231561 Jun 21 06:25:46 PM PDT 24 Jun 21 06:25:50 PM PDT 24 13096626 ps
T967 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2239632292 Jun 21 06:25:31 PM PDT 24 Jun 21 06:25:34 PM PDT 24 48479022 ps
T968 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.641916328 Jun 21 06:25:19 PM PDT 24 Jun 21 06:25:22 PM PDT 24 39636560 ps
T132 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1148045053 Jun 21 06:25:45 PM PDT 24 Jun 21 06:25:49 PM PDT 24 100036653 ps
T969 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2150585924 Jun 21 06:25:32 PM PDT 24 Jun 21 06:25:35 PM PDT 24 98859841 ps
T970 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.4238986871 Jun 21 06:25:30 PM PDT 24 Jun 21 06:25:32 PM PDT 24 30849127 ps
T971 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3816096067 Jun 21 06:25:45 PM PDT 24 Jun 21 06:25:48 PM PDT 24 29893517 ps
T972 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3551623425 Jun 21 06:25:32 PM PDT 24 Jun 21 06:25:36 PM PDT 24 165865655 ps
T973 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4125225829 Jun 21 06:25:24 PM PDT 24 Jun 21 06:25:35 PM PDT 24 779123486 ps
T974 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.660027574 Jun 21 06:25:46 PM PDT 24 Jun 21 06:25:50 PM PDT 24 149539597 ps
T210 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3735098559 Jun 21 06:25:17 PM PDT 24 Jun 21 06:25:19 PM PDT 24 50611373 ps
T975 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3381151714 Jun 21 06:25:44 PM PDT 24 Jun 21 06:25:49 PM PDT 24 359989907 ps
T976 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.341684119 Jun 21 06:25:46 PM PDT 24 Jun 21 06:25:50 PM PDT 24 87252803 ps
T977 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.185466358 Jun 21 06:25:32 PM PDT 24 Jun 21 06:25:36 PM PDT 24 129023281 ps
T978 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.819682699 Jun 21 06:25:19 PM PDT 24 Jun 21 06:25:25 PM PDT 24 350492730 ps
T979 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1622104508 Jun 21 06:25:50 PM PDT 24 Jun 21 06:25:53 PM PDT 24 60331448 ps
T980 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.248194530 Jun 21 06:25:24 PM PDT 24 Jun 21 06:25:27 PM PDT 24 446319816 ps
T981 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3572391494 Jun 21 06:25:19 PM PDT 24 Jun 21 06:25:42 PM PDT 24 970964792 ps
T212 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.45179780 Jun 21 06:25:25 PM PDT 24 Jun 21 06:25:27 PM PDT 24 19549543 ps
T982 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2839705853 Jun 21 06:25:45 PM PDT 24 Jun 21 06:25:48 PM PDT 24 44484209 ps
T983 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.438235484 Jun 21 06:25:41 PM PDT 24 Jun 21 06:25:46 PM PDT 24 157719481 ps
T984 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1889361977 Jun 21 06:25:39 PM PDT 24 Jun 21 06:25:41 PM PDT 24 41139915 ps
T137 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.611954513 Jun 21 06:25:42 PM PDT 24 Jun 21 06:25:46 PM PDT 24 105177140 ps
T985 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2520152184 Jun 21 06:25:50 PM PDT 24 Jun 21 06:25:53 PM PDT 24 40969261 ps
T986 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4290296100 Jun 21 06:25:37 PM PDT 24 Jun 21 06:25:39 PM PDT 24 451515709 ps
T987 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2902373369 Jun 21 06:25:34 PM PDT 24 Jun 21 06:25:43 PM PDT 24 1541777721 ps
T988 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.53658385 Jun 21 06:25:19 PM PDT 24 Jun 21 06:25:22 PM PDT 24 151658540 ps
T989 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.4003371402 Jun 21 06:25:43 PM PDT 24 Jun 21 06:25:59 PM PDT 24 4775332440 ps
T990 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2346562998 Jun 21 06:25:45 PM PDT 24 Jun 21 06:25:48 PM PDT 24 11806480 ps
T991 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3575318826 Jun 21 06:25:23 PM PDT 24 Jun 21 06:25:25 PM PDT 24 42689003 ps
T992 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2421499060 Jun 21 06:25:37 PM PDT 24 Jun 21 06:25:39 PM PDT 24 24827491 ps
T211 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3644039332 Jun 21 06:25:41 PM PDT 24 Jun 21 06:25:43 PM PDT 24 15345039 ps
T993 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3831339014 Jun 21 06:25:37 PM PDT 24 Jun 21 06:25:40 PM PDT 24 56938603 ps
T994 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.452638505 Jun 21 06:25:33 PM PDT 24 Jun 21 06:25:35 PM PDT 24 48010802 ps
T995 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1630332282 Jun 21 06:25:27 PM PDT 24 Jun 21 06:25:29 PM PDT 24 100494750 ps
T996 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2132002501 Jun 21 06:25:39 PM PDT 24 Jun 21 06:25:41 PM PDT 24 101142654 ps
T997 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2517788276 Jun 21 06:25:18 PM PDT 24 Jun 21 06:25:21 PM PDT 24 161584208 ps
T998 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1074194678 Jun 21 06:25:22 PM PDT 24 Jun 21 06:25:25 PM PDT 24 526595473 ps
T999 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.327394444 Jun 21 06:25:31 PM PDT 24 Jun 21 06:25:35 PM PDT 24 47079875 ps

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.3440173570
Short name T1
Test name
Test status
Simulation time 8770103353 ps
CPU time 64.4 seconds
Started Jun 21 06:30:18 PM PDT 24
Finished Jun 21 06:31:25 PM PDT 24
Peak memory 226256 kb
Host smart-3b8e9276-3102-49ba-8228-acc712d35275
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440173570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.3440173570
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.2891991319
Short name T28
Test name
Test status
Simulation time 19848704481 ps
CPU time 674.24 seconds
Started Jun 21 06:30:15 PM PDT 24
Finished Jun 21 06:41:32 PM PDT 24
Peak memory 285528 kb
Host smart-38606d9d-3f02-4e34-8fab-e0439b32838d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2891991319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.2891991319
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2000390147
Short name T10
Test name
Test status
Simulation time 360975441 ps
CPU time 8.4 seconds
Started Jun 21 06:30:17 PM PDT 24
Finished Jun 21 06:30:28 PM PDT 24
Peak memory 225160 kb
Host smart-781f3fc7-61c5-4da3-8acc-355299753475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000390147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2000390147
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.1730810489
Short name T14
Test name
Test status
Simulation time 711252371 ps
CPU time 26.72 seconds
Started Jun 21 06:30:57 PM PDT 24
Finished Jun 21 06:31:26 PM PDT 24
Peak memory 219056 kb
Host smart-53990add-ba4a-43e0-96a3-2b0960f9d3ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730810489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1730810489
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3912167118
Short name T110
Test name
Test status
Simulation time 46317429 ps
CPU time 2.7 seconds
Started Jun 21 06:25:34 PM PDT 24
Finished Jun 21 06:25:38 PM PDT 24
Peak memory 217644 kb
Host smart-878e55d8-cc01-49b2-8f45-8b711ff780cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912167118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.3912167118
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2929397247
Short name T339
Test name
Test status
Simulation time 1518002771 ps
CPU time 10.22 seconds
Started Jun 21 06:29:25 PM PDT 24
Finished Jun 21 06:29:37 PM PDT 24
Peak memory 225900 kb
Host smart-47236715-f42c-43ce-a062-5ddaa5cd310c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929397247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2929397247
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.3709527541
Short name T18
Test name
Test status
Simulation time 59224066822 ps
CPU time 232.86 seconds
Started Jun 21 06:28:59 PM PDT 24
Finished Jun 21 06:32:53 PM PDT 24
Peak memory 284004 kb
Host smart-bb94819a-4219-4bc0-bcc7-d2b34cd7e679
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3709527541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.3709527541
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.1774497788
Short name T52
Test name
Test status
Simulation time 105803314 ps
CPU time 23.62 seconds
Started Jun 21 06:28:49 PM PDT 24
Finished Jun 21 06:29:13 PM PDT 24
Peak memory 269052 kb
Host smart-2e4bdb10-e3a9-4c77-8a4f-47915015971c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774497788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.1774497788
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.4173441700
Short name T25
Test name
Test status
Simulation time 311358562 ps
CPU time 7.79 seconds
Started Jun 21 06:30:21 PM PDT 24
Finished Jun 21 06:30:33 PM PDT 24
Peak memory 218384 kb
Host smart-615bae11-a645-4722-baf6-d9ccf2bece27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173441700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
4173441700
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.779810418
Short name T115
Test name
Test status
Simulation time 465023403 ps
CPU time 4.01 seconds
Started Jun 21 06:25:26 PM PDT 24
Finished Jun 21 06:25:31 PM PDT 24
Peak memory 217616 kb
Host smart-1907a9a4-5c56-48b6-b929-a95014df68c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779810418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_e
rr.779810418
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.1194743681
Short name T29
Test name
Test status
Simulation time 11806444950 ps
CPU time 218.2 seconds
Started Jun 21 06:30:43 PM PDT 24
Finished Jun 21 06:34:24 PM PDT 24
Peak memory 283852 kb
Host smart-e317c873-a1bc-472b-b243-42fbfa34350b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1194743681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.1194743681
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.351410676
Short name T158
Test name
Test status
Simulation time 2551085936 ps
CPU time 15.4 seconds
Started Jun 21 06:29:28 PM PDT 24
Finished Jun 21 06:29:45 PM PDT 24
Peak memory 219076 kb
Host smart-c5271611-d7fb-4fed-9f8d-e98faa146355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351410676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.351410676
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.1379359416
Short name T33
Test name
Test status
Simulation time 1029940834 ps
CPU time 5.63 seconds
Started Jun 21 06:28:50 PM PDT 24
Finished Jun 21 06:28:56 PM PDT 24
Peak memory 217352 kb
Host smart-d28bb0bb-a4c8-4c39-8fe8-9ba6c8332217
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379359416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.1379359416
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.297299379
Short name T88
Test name
Test status
Simulation time 61790030 ps
CPU time 1.07 seconds
Started Jun 21 06:29:02 PM PDT 24
Finished Jun 21 06:29:04 PM PDT 24
Peak memory 208988 kb
Host smart-0a46a782-df22-465f-8236-7dcc15287c92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297299379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.297299379
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3248468399
Short name T207
Test name
Test status
Simulation time 14307990 ps
CPU time 1.09 seconds
Started Jun 21 06:25:25 PM PDT 24
Finished Jun 21 06:25:27 PM PDT 24
Peak memory 209264 kb
Host smart-4d891bd0-29cf-4f93-aed5-efe210530704
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248468399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3248468399
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.149145927
Short name T119
Test name
Test status
Simulation time 34519284 ps
CPU time 1.11 seconds
Started Jun 21 06:25:33 PM PDT 24
Finished Jun 21 06:25:35 PM PDT 24
Peak memory 209228 kb
Host smart-a833cad6-b4ab-4fcf-b6c4-1e3ebc349bd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149145927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.149145927
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.521544468
Short name T4
Test name
Test status
Simulation time 122083962 ps
CPU time 7.16 seconds
Started Jun 21 06:29:29 PM PDT 24
Finished Jun 21 06:29:37 PM PDT 24
Peak memory 250396 kb
Host smart-0303c1b0-279c-4fe5-8fb5-0f653f790635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521544468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.521544468
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.4074508688
Short name T90
Test name
Test status
Simulation time 71644424748 ps
CPU time 416.48 seconds
Started Jun 21 06:29:26 PM PDT 24
Finished Jun 21 06:36:24 PM PDT 24
Peak memory 497000 kb
Host smart-0b98fafb-17e1-4b1f-9608-8fe79b441eff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4074508688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.4074508688
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2792886619
Short name T125
Test name
Test status
Simulation time 543835144 ps
CPU time 2.58 seconds
Started Jun 21 06:25:31 PM PDT 24
Finished Jun 21 06:25:34 PM PDT 24
Peak memory 222176 kb
Host smart-7cd0e696-1961-4cd8-b6f8-42222e716a70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792886619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.2792886619
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.395394725
Short name T17
Test name
Test status
Simulation time 238048536 ps
CPU time 11.51 seconds
Started Jun 21 06:30:04 PM PDT 24
Finished Jun 21 06:30:18 PM PDT 24
Peak memory 218252 kb
Host smart-b98e6afd-201a-4e71-b0b1-51f17e3ca939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395394725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.395394725
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3897732216
Short name T126
Test name
Test status
Simulation time 95907790 ps
CPU time 3.3 seconds
Started Jun 21 06:25:46 PM PDT 24
Finished Jun 21 06:25:51 PM PDT 24
Peak memory 217500 kb
Host smart-92d95118-f1df-4e40-b37b-5799f94a100c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897732216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3897732216
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.4020869060
Short name T135
Test name
Test status
Simulation time 231276334 ps
CPU time 3.04 seconds
Started Jun 21 06:25:24 PM PDT 24
Finished Jun 21 06:25:28 PM PDT 24
Peak memory 222196 kb
Host smart-0b8b7a58-80d2-4e2d-8691-2b02766d997e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020869060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.4020869060
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2389328197
Short name T136
Test name
Test status
Simulation time 401198244 ps
CPU time 4.34 seconds
Started Jun 21 06:25:39 PM PDT 24
Finished Jun 21 06:25:44 PM PDT 24
Peak memory 217540 kb
Host smart-91cbbd49-12ee-462e-9066-68e3be2a70c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389328197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2389328197
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3830246797
Short name T120
Test name
Test status
Simulation time 68574349 ps
CPU time 1.41 seconds
Started Jun 21 06:25:17 PM PDT 24
Finished Jun 21 06:25:19 PM PDT 24
Peak memory 211232 kb
Host smart-f3f3ee9c-09c1-4502-9b7d-477d68ec416f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830246797 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.3830246797
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1939086018
Short name T23
Test name
Test status
Simulation time 1580029176 ps
CPU time 12.31 seconds
Started Jun 21 06:30:10 PM PDT 24
Finished Jun 21 06:30:23 PM PDT 24
Peak memory 226196 kb
Host smart-1086e634-7f6b-4356-9541-b0e3707fa52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939086018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1939086018
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.718938899
Short name T9
Test name
Test status
Simulation time 52388070 ps
CPU time 0.85 seconds
Started Jun 21 06:29:10 PM PDT 24
Finished Jun 21 06:29:14 PM PDT 24
Peak memory 212028 kb
Host smart-6a0fe9d6-dfb0-421a-accd-bcae19808c04
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718938899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct
rl_volatile_unlock_smoke.718938899
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1148045053
Short name T132
Test name
Test status
Simulation time 100036653 ps
CPU time 3.01 seconds
Started Jun 21 06:25:45 PM PDT 24
Finished Jun 21 06:25:49 PM PDT 24
Peak memory 222176 kb
Host smart-fd581e6f-a3af-4670-b458-889c1324beae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148045053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1148045053
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.385952023
Short name T134
Test name
Test status
Simulation time 689839713 ps
CPU time 2.77 seconds
Started Jun 21 06:25:36 PM PDT 24
Finished Jun 21 06:25:40 PM PDT 24
Peak memory 221816 kb
Host smart-a3e743ce-f82b-4492-9133-b87409e8c1f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385952023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_e
rr.385952023
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.703676842
Short name T221
Test name
Test status
Simulation time 17870857 ps
CPU time 0.86 seconds
Started Jun 21 06:28:50 PM PDT 24
Finished Jun 21 06:28:52 PM PDT 24
Peak memory 209196 kb
Host smart-bfd387b4-50e9-4f62-983a-eb191f7348f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703676842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.703676842
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1767182021
Short name T223
Test name
Test status
Simulation time 22964162 ps
CPU time 0.86 seconds
Started Jun 21 06:28:45 PM PDT 24
Finished Jun 21 06:28:47 PM PDT 24
Peak memory 208964 kb
Host smart-e76449aa-845c-45b3-9c59-0875d633830e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767182021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1767182021
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3552623781
Short name T225
Test name
Test status
Simulation time 21585533 ps
CPU time 0.98 seconds
Started Jun 21 06:28:48 PM PDT 24
Finished Jun 21 06:28:50 PM PDT 24
Peak memory 209052 kb
Host smart-9f522f66-4ae4-4540-b748-2dd8133061cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552623781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3552623781
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.2159683861
Short name T226
Test name
Test status
Simulation time 13031957 ps
CPU time 0.86 seconds
Started Jun 21 06:29:07 PM PDT 24
Finished Jun 21 06:29:10 PM PDT 24
Peak memory 209048 kb
Host smart-93a376e7-495f-41ec-9be6-8cfae278cafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159683861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.2159683861
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.2895772048
Short name T26
Test name
Test status
Simulation time 215993598 ps
CPU time 9.23 seconds
Started Jun 21 06:30:01 PM PDT 24
Finished Jun 21 06:30:13 PM PDT 24
Peak memory 250604 kb
Host smart-c91eb0ed-c7b1-4606-8938-1bda696192c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895772048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2895772048
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1347265339
Short name T929
Test name
Test status
Simulation time 379999198 ps
CPU time 1.77 seconds
Started Jun 21 06:25:19 PM PDT 24
Finished Jun 21 06:25:22 PM PDT 24
Peak memory 218632 kb
Host smart-e9f4dd0b-0c48-4409-94f4-5fa61d8fd176
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134726
5339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1347265339
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.456712371
Short name T128
Test name
Test status
Simulation time 46429059 ps
CPU time 2.5 seconds
Started Jun 21 06:25:48 PM PDT 24
Finished Jun 21 06:25:53 PM PDT 24
Peak memory 217504 kb
Host smart-ef6ba5ba-8a6a-4a50-b71b-a4f05c0064c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456712371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_
err.456712371
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3639159335
Short name T127
Test name
Test status
Simulation time 67205794 ps
CPU time 2.61 seconds
Started Jun 21 06:25:45 PM PDT 24
Finished Jun 21 06:25:48 PM PDT 24
Peak memory 217528 kb
Host smart-e79b11dd-e999-488c-869c-50e12d67fda1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639159335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.3639159335
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1951609080
Short name T131
Test name
Test status
Simulation time 285238924 ps
CPU time 3.86 seconds
Started Jun 21 06:25:24 PM PDT 24
Finished Jun 21 06:25:29 PM PDT 24
Peak memory 217448 kb
Host smart-a05c7a6f-305d-49bd-a872-112c31faf5fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951609080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1951609080
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4026146626
Short name T130
Test name
Test status
Simulation time 79635426 ps
CPU time 3.36 seconds
Started Jun 21 06:25:34 PM PDT 24
Finished Jun 21 06:25:39 PM PDT 24
Peak memory 222456 kb
Host smart-79a29e60-ea27-4514-ab92-121a03556e8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026146626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.4026146626
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.560988117
Short name T15
Test name
Test status
Simulation time 295405977 ps
CPU time 9.55 seconds
Started Jun 21 06:29:44 PM PDT 24
Finished Jun 21 06:29:54 PM PDT 24
Peak memory 218308 kb
Host smart-9278b421-0cbf-4f5e-a6ec-5b0cebfb0029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560988117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.560988117
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2032449483
Short name T924
Test name
Test status
Simulation time 87896378 ps
CPU time 0.98 seconds
Started Jun 21 06:25:20 PM PDT 24
Finished Jun 21 06:25:22 PM PDT 24
Peak memory 209316 kb
Host smart-f6bacbdf-d1dd-426b-9805-1284e3a3bb32
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032449483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.2032449483
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3304229960
Short name T150
Test name
Test status
Simulation time 179461935 ps
CPU time 1.41 seconds
Started Jun 21 06:25:18 PM PDT 24
Finished Jun 21 06:25:20 PM PDT 24
Peak memory 216976 kb
Host smart-a99f5a4f-7d99-4b49-ad24-678d8789e8a8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304229960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3304229960
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2654485910
Short name T206
Test name
Test status
Simulation time 50183959 ps
CPU time 1.1 seconds
Started Jun 21 06:25:19 PM PDT 24
Finished Jun 21 06:25:22 PM PDT 24
Peak memory 209688 kb
Host smart-cf822c40-c7ab-42f9-b175-f68910476585
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654485910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2654485910
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2355537001
Short name T934
Test name
Test status
Simulation time 34665315 ps
CPU time 1.13 seconds
Started Jun 21 06:25:17 PM PDT 24
Finished Jun 21 06:25:19 PM PDT 24
Peak memory 218608 kb
Host smart-4cf7e58e-e5aa-4dc4-8fe0-45a8988130fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355537001 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2355537001
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3735098559
Short name T210
Test name
Test status
Simulation time 50611373 ps
CPU time 0.9 seconds
Started Jun 21 06:25:17 PM PDT 24
Finished Jun 21 06:25:19 PM PDT 24
Peak memory 209364 kb
Host smart-a2dd1c70-af1d-43e4-b185-e00a3d771212
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735098559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3735098559
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.641916328
Short name T968
Test name
Test status
Simulation time 39636560 ps
CPU time 1.62 seconds
Started Jun 21 06:25:19 PM PDT 24
Finished Jun 21 06:25:22 PM PDT 24
Peak memory 208764 kb
Host smart-f2c0f65d-6e3b-4a87-94cd-66cbf9554ee9
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641916328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.lc_ctrl_jtag_alert_test.641916328
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2419181603
Short name T879
Test name
Test status
Simulation time 736645719 ps
CPU time 6.59 seconds
Started Jun 21 06:25:17 PM PDT 24
Finished Jun 21 06:25:25 PM PDT 24
Peak memory 208884 kb
Host smart-8ece2e90-4f62-45d8-9b6a-26d28e63be57
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419181603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.2419181603
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.819682699
Short name T978
Test name
Test status
Simulation time 350492730 ps
CPU time 4.8 seconds
Started Jun 21 06:25:19 PM PDT 24
Finished Jun 21 06:25:25 PM PDT 24
Peak memory 209192 kb
Host smart-cec6444f-d973-46f7-acf7-662dbac161a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819682699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.819682699
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1131870085
Short name T884
Test name
Test status
Simulation time 123473562 ps
CPU time 3.57 seconds
Started Jun 21 06:25:17 PM PDT 24
Finished Jun 21 06:25:21 PM PDT 24
Peak memory 210952 kb
Host smart-f9749b63-7676-43ef-a04d-9c28cae97407
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131870085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1131870085
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2857462519
Short name T893
Test name
Test status
Simulation time 59449368 ps
CPU time 1.76 seconds
Started Jun 21 06:25:17 PM PDT 24
Finished Jun 21 06:25:19 PM PDT 24
Peak memory 217656 kb
Host smart-e345e9d1-104d-44c2-a4ed-792644e64a39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285746
2519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2857462519
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3696538714
Short name T935
Test name
Test status
Simulation time 55056554 ps
CPU time 2.13 seconds
Started Jun 21 06:25:23 PM PDT 24
Finished Jun 21 06:25:27 PM PDT 24
Peak memory 217300 kb
Host smart-0d29bb75-016e-4b03-88e2-8a2ce4ae0c82
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696538714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3696538714
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3531035304
Short name T944
Test name
Test status
Simulation time 30523857 ps
CPU time 1.21 seconds
Started Jun 21 06:25:17 PM PDT 24
Finished Jun 21 06:25:19 PM PDT 24
Peak memory 209324 kb
Host smart-96793f4d-7d9c-42c7-af6f-93420dae0c92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531035304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3531035304
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.197562126
Short name T895
Test name
Test status
Simulation time 105958313 ps
CPU time 2.44 seconds
Started Jun 21 06:25:16 PM PDT 24
Finished Jun 21 06:25:20 PM PDT 24
Peak memory 217660 kb
Host smart-c9c44dae-033c-4f56-8ab4-0f0997368db5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197562126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.197562126
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2069979442
Short name T121
Test name
Test status
Simulation time 243670418 ps
CPU time 2.75 seconds
Started Jun 21 06:25:19 PM PDT 24
Finished Jun 21 06:25:23 PM PDT 24
Peak memory 217540 kb
Host smart-09e29be1-526c-4982-8203-efb3c67d05f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069979442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.2069979442
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.53658385
Short name T988
Test name
Test status
Simulation time 151658540 ps
CPU time 1.98 seconds
Started Jun 21 06:25:19 PM PDT 24
Finished Jun 21 06:25:22 PM PDT 24
Peak memory 217348 kb
Host smart-85c40155-515e-4648-82a9-6f2f87bc8f13
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53658385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash.53658385
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.4001831722
Short name T928
Test name
Test status
Simulation time 230154970 ps
CPU time 1.15 seconds
Started Jun 21 06:25:24 PM PDT 24
Finished Jun 21 06:25:26 PM PDT 24
Peak memory 209856 kb
Host smart-6bee8268-2f93-4550-aca3-83ab2ac8c570
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001831722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.4001831722
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1630332282
Short name T995
Test name
Test status
Simulation time 100494750 ps
CPU time 1.69 seconds
Started Jun 21 06:25:27 PM PDT 24
Finished Jun 21 06:25:29 PM PDT 24
Peak memory 217716 kb
Host smart-b031e98e-287b-40d3-b2cb-faa06522ce4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630332282 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1630332282
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3068352084
Short name T209
Test name
Test status
Simulation time 20128342 ps
CPU time 0.99 seconds
Started Jun 21 06:25:19 PM PDT 24
Finished Jun 21 06:25:21 PM PDT 24
Peak memory 209288 kb
Host smart-23af28b4-0396-4cee-824e-3d33ab927b87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068352084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.3068352084
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1440729594
Short name T873
Test name
Test status
Simulation time 58155886 ps
CPU time 1.95 seconds
Started Jun 21 06:25:18 PM PDT 24
Finished Jun 21 06:25:21 PM PDT 24
Peak memory 208868 kb
Host smart-aa3214f7-6dfe-4785-81f6-1904e6af8b2a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440729594 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1440729594
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2225126794
Short name T902
Test name
Test status
Simulation time 1000248350 ps
CPU time 6.73 seconds
Started Jun 21 06:25:19 PM PDT 24
Finished Jun 21 06:25:27 PM PDT 24
Peak memory 209160 kb
Host smart-e7954e34-d425-450c-8fcd-78a922d9825b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225126794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2225126794
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3572391494
Short name T981
Test name
Test status
Simulation time 970964792 ps
CPU time 21.5 seconds
Started Jun 21 06:25:19 PM PDT 24
Finished Jun 21 06:25:42 PM PDT 24
Peak memory 209020 kb
Host smart-a5a49f50-36da-46a2-8379-8abd168ab4f8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572391494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3572391494
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2517788276
Short name T997
Test name
Test status
Simulation time 161584208 ps
CPU time 1.52 seconds
Started Jun 21 06:25:18 PM PDT 24
Finished Jun 21 06:25:21 PM PDT 24
Peak memory 210632 kb
Host smart-25501b3c-221c-4bb7-8ff1-f37d456a7c0d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517788276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.2517788276
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3049840952
Short name T915
Test name
Test status
Simulation time 75892909 ps
CPU time 1.38 seconds
Started Jun 21 06:25:17 PM PDT 24
Finished Jun 21 06:25:19 PM PDT 24
Peak memory 217272 kb
Host smart-529997ba-e495-4700-a0cf-8e8d532ecd1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049840952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.3049840952
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1680826573
Short name T213
Test name
Test status
Simulation time 26919882 ps
CPU time 1.13 seconds
Started Jun 21 06:25:15 PM PDT 24
Finished Jun 21 06:25:17 PM PDT 24
Peak memory 217532 kb
Host smart-4737e17d-a3ad-49c5-993e-3b63acd54c72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680826573 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1680826573
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.600712316
Short name T214
Test name
Test status
Simulation time 78333172 ps
CPU time 1.02 seconds
Started Jun 21 06:25:23 PM PDT 24
Finished Jun 21 06:25:25 PM PDT 24
Peak memory 209308 kb
Host smart-7774e992-2f98-4418-962d-bb3ee19c112d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600712316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.600712316
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3369817592
Short name T920
Test name
Test status
Simulation time 268670708 ps
CPU time 5.06 seconds
Started Jun 21 06:25:18 PM PDT 24
Finished Jun 21 06:25:23 PM PDT 24
Peak memory 218044 kb
Host smart-1bb15e6b-2f81-452d-801a-60c1ac57351d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369817592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.3369817592
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.300519562
Short name T908
Test name
Test status
Simulation time 31775887 ps
CPU time 1.36 seconds
Started Jun 21 06:25:42 PM PDT 24
Finished Jun 21 06:25:45 PM PDT 24
Peak memory 218976 kb
Host smart-69f86486-1ea6-4c10-8e54-f46bdb31e12d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300519562 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.300519562
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.663704805
Short name T153
Test name
Test status
Simulation time 17370143 ps
CPU time 0.86 seconds
Started Jun 21 06:25:42 PM PDT 24
Finished Jun 21 06:25:44 PM PDT 24
Peak memory 209344 kb
Host smart-a464e0fc-20a6-4326-acd3-abf984af8d1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663704805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.663704805
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3017939321
Short name T952
Test name
Test status
Simulation time 24203988 ps
CPU time 1.22 seconds
Started Jun 21 06:25:42 PM PDT 24
Finished Jun 21 06:25:44 PM PDT 24
Peak memory 217480 kb
Host smart-437b4cf6-42e2-48be-bb4d-f84efcf436bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017939321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3017939321
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1331613933
Short name T911
Test name
Test status
Simulation time 173193697 ps
CPU time 3.15 seconds
Started Jun 21 06:25:42 PM PDT 24
Finished Jun 21 06:25:47 PM PDT 24
Peak memory 217680 kb
Host smart-c8053332-6343-4b50-9a5a-8a779f2147d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331613933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1331613933
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3728306331
Short name T112
Test name
Test status
Simulation time 451928144 ps
CPU time 3.25 seconds
Started Jun 21 06:25:42 PM PDT 24
Finished Jun 21 06:25:47 PM PDT 24
Peak memory 222432 kb
Host smart-d7351269-0efc-4d2e-bc5b-b0479fd0dc98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728306331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.3728306331
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1008232166
Short name T936
Test name
Test status
Simulation time 40219603 ps
CPU time 1.65 seconds
Started Jun 21 06:25:40 PM PDT 24
Finished Jun 21 06:25:43 PM PDT 24
Peak memory 219916 kb
Host smart-66b4fcf1-809f-48d5-8f70-e6a303830837
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008232166 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1008232166
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3465638178
Short name T954
Test name
Test status
Simulation time 98608319 ps
CPU time 0.91 seconds
Started Jun 21 06:25:43 PM PDT 24
Finished Jun 21 06:25:45 PM PDT 24
Peak memory 209344 kb
Host smart-f35575bf-4e39-426c-b687-f91e09519389
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465638178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3465638178
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3088519285
Short name T933
Test name
Test status
Simulation time 148349913 ps
CPU time 1.93 seconds
Started Jun 21 06:25:42 PM PDT 24
Finished Jun 21 06:25:46 PM PDT 24
Peak memory 217540 kb
Host smart-0fba9e42-4deb-4977-96ac-b1ec366e3840
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088519285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.3088519285
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1889361977
Short name T984
Test name
Test status
Simulation time 41139915 ps
CPU time 1.59 seconds
Started Jun 21 06:25:39 PM PDT 24
Finished Jun 21 06:25:41 PM PDT 24
Peak memory 217628 kb
Host smart-52a95e50-e4e2-4cef-8e4b-2efd66c8eeb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889361977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1889361977
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3547147940
Short name T116
Test name
Test status
Simulation time 265281765 ps
CPU time 2.78 seconds
Started Jun 21 06:25:39 PM PDT 24
Finished Jun 21 06:25:42 PM PDT 24
Peak memory 221892 kb
Host smart-be9f3554-c7d1-4b91-904a-994fc4e8856f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547147940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3547147940
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.660027574
Short name T974
Test name
Test status
Simulation time 149539597 ps
CPU time 1.72 seconds
Started Jun 21 06:25:46 PM PDT 24
Finished Jun 21 06:25:50 PM PDT 24
Peak memory 217504 kb
Host smart-8f14f146-012a-47cc-9fd5-818b8f4c566f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660027574 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.660027574
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.882347643
Short name T922
Test name
Test status
Simulation time 13878501 ps
CPU time 1.06 seconds
Started Jun 21 06:25:47 PM PDT 24
Finished Jun 21 06:25:51 PM PDT 24
Peak memory 209332 kb
Host smart-f1a186c5-883a-4995-b089-fbcc08d79c0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882347643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.882347643
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3816096067
Short name T971
Test name
Test status
Simulation time 29893517 ps
CPU time 1.12 seconds
Started Jun 21 06:25:45 PM PDT 24
Finished Jun 21 06:25:48 PM PDT 24
Peak memory 209328 kb
Host smart-e72cc448-a852-49a3-a414-cccf299c526c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816096067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3816096067
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3303192417
Short name T914
Test name
Test status
Simulation time 107937814 ps
CPU time 4.59 seconds
Started Jun 21 06:25:37 PM PDT 24
Finished Jun 21 06:25:42 PM PDT 24
Peak memory 218356 kb
Host smart-f80b16f8-a60a-428e-a0fd-d7761c67dc96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303192417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3303192417
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.625833327
Short name T124
Test name
Test status
Simulation time 691871621 ps
CPU time 4.34 seconds
Started Jun 21 06:25:45 PM PDT 24
Finished Jun 21 06:25:51 PM PDT 24
Peak memory 217564 kb
Host smart-5a33cbda-8af4-40f9-9dee-2beffbbfb074
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625833327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_
err.625833327
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2486370206
Short name T917
Test name
Test status
Simulation time 33066397 ps
CPU time 0.98 seconds
Started Jun 21 06:25:46 PM PDT 24
Finished Jun 21 06:25:50 PM PDT 24
Peak memory 217584 kb
Host smart-a17f4bad-1eb4-4c85-b478-58c004fdbd34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486370206 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2486370206
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.4230231561
Short name T966
Test name
Test status
Simulation time 13096626 ps
CPU time 1.03 seconds
Started Jun 21 06:25:46 PM PDT 24
Finished Jun 21 06:25:50 PM PDT 24
Peak memory 209320 kb
Host smart-d2ecae1f-7bcf-4eea-95cb-0e847642c27c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230231561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.4230231561
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1691399533
Short name T219
Test name
Test status
Simulation time 27809280 ps
CPU time 1.4 seconds
Started Jun 21 06:25:49 PM PDT 24
Finished Jun 21 06:25:52 PM PDT 24
Peak memory 209328 kb
Host smart-340601f5-461a-47f6-84d3-f602c2268d77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691399533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.1691399533
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3807430291
Short name T909
Test name
Test status
Simulation time 103635076 ps
CPU time 4.59 seconds
Started Jun 21 06:25:45 PM PDT 24
Finished Jun 21 06:25:52 PM PDT 24
Peak memory 218196 kb
Host smart-e208fc8a-b73b-4bf4-a1be-85f951074a00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807430291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3807430291
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2575196593
Short name T916
Test name
Test status
Simulation time 19389157 ps
CPU time 1.33 seconds
Started Jun 21 06:25:46 PM PDT 24
Finished Jun 21 06:25:50 PM PDT 24
Peak memory 218692 kb
Host smart-7cbfaf39-df76-4c0a-8881-1de49889900d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575196593 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2575196593
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3313175881
Short name T202
Test name
Test status
Simulation time 33693981 ps
CPU time 0.92 seconds
Started Jun 21 06:25:46 PM PDT 24
Finished Jun 21 06:25:49 PM PDT 24
Peak memory 209324 kb
Host smart-53a23412-d10f-4802-b499-f7f0e07660fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313175881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3313175881
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3109984239
Short name T949
Test name
Test status
Simulation time 21445544 ps
CPU time 1.25 seconds
Started Jun 21 06:25:46 PM PDT 24
Finished Jun 21 06:25:50 PM PDT 24
Peak memory 209328 kb
Host smart-17908870-fd2b-42ff-bebe-9ff30e228a4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109984239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.3109984239
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1830460968
Short name T129
Test name
Test status
Simulation time 33638242 ps
CPU time 2.37 seconds
Started Jun 21 06:25:46 PM PDT 24
Finished Jun 21 06:25:51 PM PDT 24
Peak memory 217632 kb
Host smart-065de7b8-cc33-4b0f-89f7-9186f10d43a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830460968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.1830460968
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1200486813
Short name T938
Test name
Test status
Simulation time 148308757 ps
CPU time 1.96 seconds
Started Jun 21 06:25:45 PM PDT 24
Finished Jun 21 06:25:49 PM PDT 24
Peak memory 221864 kb
Host smart-bf386ecf-5de3-475e-b2c5-033ae7779323
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200486813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1200486813
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1948366588
Short name T948
Test name
Test status
Simulation time 18927337 ps
CPU time 1.58 seconds
Started Jun 21 06:25:44 PM PDT 24
Finished Jun 21 06:25:46 PM PDT 24
Peak memory 218956 kb
Host smart-aa58512b-6dfb-4e2c-b813-6b2e6bc9e850
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948366588 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.1948366588
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2520152184
Short name T985
Test name
Test status
Simulation time 40969261 ps
CPU time 0.91 seconds
Started Jun 21 06:25:50 PM PDT 24
Finished Jun 21 06:25:53 PM PDT 24
Peak memory 209312 kb
Host smart-85cba1c8-f834-4530-885d-9e3561dd7346
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520152184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2520152184
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1622104508
Short name T979
Test name
Test status
Simulation time 60331448 ps
CPU time 1.16 seconds
Started Jun 21 06:25:50 PM PDT 24
Finished Jun 21 06:25:53 PM PDT 24
Peak memory 217512 kb
Host smart-2718af9f-543d-432a-b3ab-eb8eb1b3eafd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622104508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.1622104508
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.4081974365
Short name T111
Test name
Test status
Simulation time 205373651 ps
CPU time 4.28 seconds
Started Jun 21 06:25:47 PM PDT 24
Finished Jun 21 06:25:54 PM PDT 24
Peak memory 217652 kb
Host smart-52670769-ca2d-4413-b9b9-7bf415d0d326
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081974365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.4081974365
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.4023120512
Short name T227
Test name
Test status
Simulation time 438255912 ps
CPU time 3.34 seconds
Started Jun 21 06:25:45 PM PDT 24
Finished Jun 21 06:25:51 PM PDT 24
Peak memory 217604 kb
Host smart-58f99a25-597a-4bef-88ee-fec0461e3e7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023120512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.4023120512
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2711376818
Short name T903
Test name
Test status
Simulation time 89194090 ps
CPU time 1.73 seconds
Started Jun 21 06:25:43 PM PDT 24
Finished Jun 21 06:25:46 PM PDT 24
Peak memory 217752 kb
Host smart-8ba85467-3e94-41bb-a884-eb8316034b32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711376818 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2711376818
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3139537255
Short name T872
Test name
Test status
Simulation time 63019643 ps
CPU time 0.92 seconds
Started Jun 21 06:25:46 PM PDT 24
Finished Jun 21 06:25:50 PM PDT 24
Peak memory 209328 kb
Host smart-9ac451bd-eeb9-4383-854f-9fc26c7238fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139537255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3139537255
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.809623407
Short name T958
Test name
Test status
Simulation time 31358396 ps
CPU time 1.21 seconds
Started Jun 21 06:25:47 PM PDT 24
Finished Jun 21 06:25:51 PM PDT 24
Peak memory 209320 kb
Host smart-7e9872a5-6ee9-4e56-8aed-8a96e0426d04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809623407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_same_csr_outstanding.809623407
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3854389572
Short name T122
Test name
Test status
Simulation time 145961006 ps
CPU time 2.25 seconds
Started Jun 21 06:25:46 PM PDT 24
Finished Jun 21 06:25:50 PM PDT 24
Peak memory 217648 kb
Host smart-dfa93c9c-2413-4991-9eb7-d5717f6ebc9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854389572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3854389572
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.308204415
Short name T930
Test name
Test status
Simulation time 23536176 ps
CPU time 1.7 seconds
Started Jun 21 06:25:48 PM PDT 24
Finished Jun 21 06:25:52 PM PDT 24
Peak memory 218556 kb
Host smart-06cda3fc-8b17-4c2f-a796-c8c44a43ea97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308204415 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.308204415
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2346562998
Short name T990
Test name
Test status
Simulation time 11806480 ps
CPU time 1.03 seconds
Started Jun 21 06:25:45 PM PDT 24
Finished Jun 21 06:25:48 PM PDT 24
Peak memory 209004 kb
Host smart-b7f2aa12-8170-4e11-baa1-6b52d583d852
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346562998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2346562998
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.4227223636
Short name T898
Test name
Test status
Simulation time 22803542 ps
CPU time 1.51 seconds
Started Jun 21 06:25:46 PM PDT 24
Finished Jun 21 06:25:51 PM PDT 24
Peak memory 211328 kb
Host smart-eaa6eb91-a84a-4bf8-b892-a0bccc5af994
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227223636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.4227223636
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.651520983
Short name T117
Test name
Test status
Simulation time 410022157 ps
CPU time 4.67 seconds
Started Jun 21 06:25:53 PM PDT 24
Finished Jun 21 06:25:59 PM PDT 24
Peak memory 217576 kb
Host smart-5a7535cc-dc0a-4bde-8689-360df9b02ce7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651520983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.651520983
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.341684119
Short name T976
Test name
Test status
Simulation time 87252803 ps
CPU time 1.38 seconds
Started Jun 21 06:25:46 PM PDT 24
Finished Jun 21 06:25:50 PM PDT 24
Peak memory 217620 kb
Host smart-4da1d748-0894-411b-ad04-746b3d548a30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341684119 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.341684119
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1960857683
Short name T940
Test name
Test status
Simulation time 54701626 ps
CPU time 1.12 seconds
Started Jun 21 06:25:46 PM PDT 24
Finished Jun 21 06:25:50 PM PDT 24
Peak memory 209328 kb
Host smart-34269dde-f88b-4a76-9b71-a7cf88287437
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960857683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.1960857683
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1227928947
Short name T907
Test name
Test status
Simulation time 31140789 ps
CPU time 1.12 seconds
Started Jun 21 06:25:46 PM PDT 24
Finished Jun 21 06:25:50 PM PDT 24
Peak memory 217468 kb
Host smart-68a5c5e8-32b9-42c8-abb6-5a20039d675e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227928947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.1227928947
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3804716012
Short name T910
Test name
Test status
Simulation time 273717930 ps
CPU time 2.39 seconds
Started Jun 21 06:25:44 PM PDT 24
Finished Jun 21 06:25:47 PM PDT 24
Peak memory 217664 kb
Host smart-5a5ea71d-b246-4299-a8ba-28e98617f40e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804716012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3804716012
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3159032136
Short name T927
Test name
Test status
Simulation time 88465019 ps
CPU time 1.59 seconds
Started Jun 21 06:25:45 PM PDT 24
Finished Jun 21 06:25:47 PM PDT 24
Peak memory 217600 kb
Host smart-22d2c82b-4738-4f3e-b56f-780819971614
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159032136 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3159032136
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2412922554
Short name T919
Test name
Test status
Simulation time 14065313 ps
CPU time 0.87 seconds
Started Jun 21 06:25:43 PM PDT 24
Finished Jun 21 06:25:45 PM PDT 24
Peak memory 209024 kb
Host smart-5441d0e5-2da4-4e9b-b405-b84659507d34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412922554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2412922554
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2839705853
Short name T982
Test name
Test status
Simulation time 44484209 ps
CPU time 1.47 seconds
Started Jun 21 06:25:45 PM PDT 24
Finished Jun 21 06:25:48 PM PDT 24
Peak memory 209376 kb
Host smart-3aeb5937-5f6f-463f-8d75-10b2a1e517e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839705853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2839705853
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3381151714
Short name T975
Test name
Test status
Simulation time 359989907 ps
CPU time 3.79 seconds
Started Jun 21 06:25:44 PM PDT 24
Finished Jun 21 06:25:49 PM PDT 24
Peak memory 218552 kb
Host smart-e27ffab1-f167-4858-a9b9-9a2d944e510b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381151714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3381151714
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.4173186606
Short name T133
Test name
Test status
Simulation time 835309082 ps
CPU time 4.42 seconds
Started Jun 21 06:25:45 PM PDT 24
Finished Jun 21 06:25:52 PM PDT 24
Peak memory 217520 kb
Host smart-d0d58db1-5d58-419d-92fd-688a3504ca97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173186606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.4173186606
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1343987813
Short name T204
Test name
Test status
Simulation time 345404431 ps
CPU time 1.35 seconds
Started Jun 21 06:25:24 PM PDT 24
Finished Jun 21 06:25:26 PM PDT 24
Peak memory 209328 kb
Host smart-43e30ce8-f79c-49fb-a42b-ecaf3bb778a0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343987813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.1343987813
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1878572563
Short name T918
Test name
Test status
Simulation time 27529193 ps
CPU time 1.49 seconds
Started Jun 21 06:25:24 PM PDT 24
Finished Jun 21 06:25:27 PM PDT 24
Peak memory 209304 kb
Host smart-4c7a6dd6-e2b0-4968-9d9a-392712f61c92
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878572563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.1878572563
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.45179780
Short name T212
Test name
Test status
Simulation time 19549543 ps
CPU time 1.05 seconds
Started Jun 21 06:25:25 PM PDT 24
Finished Jun 21 06:25:27 PM PDT 24
Peak memory 210312 kb
Host smart-6c802a1c-4d32-42a6-b5f0-4651f1100ca4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45179780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_reset.45179780
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3733751827
Short name T926
Test name
Test status
Simulation time 89150905 ps
CPU time 1.91 seconds
Started Jun 21 06:25:27 PM PDT 24
Finished Jun 21 06:25:30 PM PDT 24
Peak memory 219124 kb
Host smart-8243709f-932a-4564-97b6-c41a7a21a9fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733751827 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3733751827
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.59865380
Short name T899
Test name
Test status
Simulation time 48154065 ps
CPU time 1 seconds
Started Jun 21 06:25:25 PM PDT 24
Finished Jun 21 06:25:27 PM PDT 24
Peak memory 209332 kb
Host smart-71faa016-da2a-435c-ada2-d4d38b92abe2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59865380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.59865380
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3575318826
Short name T991
Test name
Test status
Simulation time 42689003 ps
CPU time 1.34 seconds
Started Jun 21 06:25:23 PM PDT 24
Finished Jun 21 06:25:25 PM PDT 24
Peak memory 208676 kb
Host smart-a2cc7bff-a188-4027-b225-7ada18085191
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575318826 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3575318826
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1693715501
Short name T871
Test name
Test status
Simulation time 2493484034 ps
CPU time 6.61 seconds
Started Jun 21 06:25:27 PM PDT 24
Finished Jun 21 06:25:34 PM PDT 24
Peak memory 209304 kb
Host smart-b3e9a5d5-ff64-447f-a34b-4fd74034e0a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693715501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1693715501
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1470483601
Short name T950
Test name
Test status
Simulation time 1948937867 ps
CPU time 5.73 seconds
Started Jun 21 06:25:23 PM PDT 24
Finished Jun 21 06:25:30 PM PDT 24
Peak memory 209332 kb
Host smart-48269c4c-5a62-4897-b013-ccc90955e2aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470483601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1470483601
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.985913867
Short name T897
Test name
Test status
Simulation time 239001860 ps
CPU time 3.81 seconds
Started Jun 21 06:25:28 PM PDT 24
Finished Jun 21 06:25:33 PM PDT 24
Peak memory 210676 kb
Host smart-09ce8193-4af2-4b7d-86a4-fdfeba374014
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985913867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.985913867
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3731940946
Short name T160
Test name
Test status
Simulation time 221018619 ps
CPU time 2.2 seconds
Started Jun 21 06:25:26 PM PDT 24
Finished Jun 21 06:25:29 PM PDT 24
Peak memory 217736 kb
Host smart-25f8fbbe-9f08-4f65-8ee0-76bfbb414ce2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373194
0946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3731940946
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3924360289
Short name T894
Test name
Test status
Simulation time 44529464 ps
CPU time 1.15 seconds
Started Jun 21 06:25:25 PM PDT 24
Finished Jun 21 06:25:27 PM PDT 24
Peak memory 217232 kb
Host smart-4b01717a-bbf3-43c2-97cd-63aadb60e01b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924360289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3924360289
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3724217099
Short name T215
Test name
Test status
Simulation time 18149892 ps
CPU time 1.02 seconds
Started Jun 21 06:25:24 PM PDT 24
Finished Jun 21 06:25:26 PM PDT 24
Peak memory 209328 kb
Host smart-e851e69f-911b-47b0-b6a0-1ad3d7dcdd04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724217099 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.3724217099
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1361048692
Short name T912
Test name
Test status
Simulation time 125529161 ps
CPU time 1.09 seconds
Started Jun 21 06:25:24 PM PDT 24
Finished Jun 21 06:25:26 PM PDT 24
Peak memory 209408 kb
Host smart-c5822b37-83ac-41cd-a192-7df41bddf280
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361048692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.1361048692
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3238111723
Short name T170
Test name
Test status
Simulation time 47914726 ps
CPU time 1.71 seconds
Started Jun 21 06:25:26 PM PDT 24
Finished Jun 21 06:25:29 PM PDT 24
Peak memory 217656 kb
Host smart-e21408d7-a866-4620-962c-9bd98bbc6577
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238111723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.3238111723
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.692856444
Short name T208
Test name
Test status
Simulation time 184502195 ps
CPU time 1.02 seconds
Started Jun 21 06:25:31 PM PDT 24
Finished Jun 21 06:25:33 PM PDT 24
Peak memory 209360 kb
Host smart-dfe987f1-a113-4fd3-abf2-ff8ef07f86c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692856444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing
.692856444
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2619962851
Short name T892
Test name
Test status
Simulation time 256824775 ps
CPU time 2.69 seconds
Started Jun 21 06:25:32 PM PDT 24
Finished Jun 21 06:25:36 PM PDT 24
Peak memory 217360 kb
Host smart-dbb0d2d6-fa8d-432b-bdfe-c1d2079f1cde
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619962851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2619962851
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.4054461231
Short name T945
Test name
Test status
Simulation time 61207767 ps
CPU time 0.93 seconds
Started Jun 21 06:25:39 PM PDT 24
Finished Jun 21 06:25:41 PM PDT 24
Peak memory 209736 kb
Host smart-321d4b7b-246e-4886-b0cc-a6b2c0feda35
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054461231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.4054461231
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.539435414
Short name T963
Test name
Test status
Simulation time 19547873 ps
CPU time 1.1 seconds
Started Jun 21 06:25:30 PM PDT 24
Finished Jun 21 06:25:32 PM PDT 24
Peak memory 217652 kb
Host smart-adeacd19-2a33-4e4e-8de5-d2d3cebf7e8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539435414 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.539435414
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4139793602
Short name T888
Test name
Test status
Simulation time 15890555 ps
CPU time 0.89 seconds
Started Jun 21 06:25:32 PM PDT 24
Finished Jun 21 06:25:34 PM PDT 24
Peak memory 209304 kb
Host smart-beab713d-edb6-42e1-9728-0c4443d37f86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139793602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.4139793602
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2702272961
Short name T870
Test name
Test status
Simulation time 52750061 ps
CPU time 1.25 seconds
Started Jun 21 06:25:24 PM PDT 24
Finished Jun 21 06:25:27 PM PDT 24
Peak memory 209220 kb
Host smart-d1308931-4f2a-4e99-bf7f-aa34c6edd941
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702272961 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2702272961
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2395251716
Short name T942
Test name
Test status
Simulation time 1065695176 ps
CPU time 3.2 seconds
Started Jun 21 06:25:25 PM PDT 24
Finished Jun 21 06:25:29 PM PDT 24
Peak memory 209300 kb
Host smart-c8a11e4b-dbc3-425f-856d-3387397c2227
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395251716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2395251716
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4125225829
Short name T973
Test name
Test status
Simulation time 779123486 ps
CPU time 10.31 seconds
Started Jun 21 06:25:24 PM PDT 24
Finished Jun 21 06:25:35 PM PDT 24
Peak memory 209024 kb
Host smart-7257d02c-c499-4c09-b2fe-19674f46d212
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125225829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.4125225829
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1074194678
Short name T998
Test name
Test status
Simulation time 526595473 ps
CPU time 2.49 seconds
Started Jun 21 06:25:22 PM PDT 24
Finished Jun 21 06:25:25 PM PDT 24
Peak memory 211000 kb
Host smart-b2b96642-9c53-4233-9bd3-e5304a589757
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074194678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.1074194678
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.248194530
Short name T980
Test name
Test status
Simulation time 446319816 ps
CPU time 2.58 seconds
Started Jun 21 06:25:24 PM PDT 24
Finished Jun 21 06:25:27 PM PDT 24
Peak memory 217688 kb
Host smart-73bb7563-2bf4-4fd8-bf9e-9d49286279c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248194
530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.248194530
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2653150487
Short name T882
Test name
Test status
Simulation time 102308745 ps
CPU time 1.51 seconds
Started Jun 21 06:25:28 PM PDT 24
Finished Jun 21 06:25:31 PM PDT 24
Peak memory 209280 kb
Host smart-132aeaa4-4289-44c1-b28d-5d9c9d8abeb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653150487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2653150487
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2464240870
Short name T960
Test name
Test status
Simulation time 45418554 ps
CPU time 1.31 seconds
Started Jun 21 06:25:25 PM PDT 24
Finished Jun 21 06:25:27 PM PDT 24
Peak memory 209320 kb
Host smart-ac2cbf76-4252-4c0e-8123-1bead6298222
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464240870 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2464240870
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3719987403
Short name T216
Test name
Test status
Simulation time 160601555 ps
CPU time 1.39 seconds
Started Jun 21 06:25:31 PM PDT 24
Finished Jun 21 06:25:34 PM PDT 24
Peak memory 211432 kb
Host smart-428d818b-2523-49c5-bc60-ef5263bba417
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719987403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.3719987403
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1591120881
Short name T171
Test name
Test status
Simulation time 70483904 ps
CPU time 2.29 seconds
Started Jun 21 06:25:27 PM PDT 24
Finished Jun 21 06:25:30 PM PDT 24
Peak memory 218092 kb
Host smart-ca2b2fc1-33a4-4958-9e91-02869a71c06c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591120881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.1591120881
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3902903556
Short name T891
Test name
Test status
Simulation time 26639144 ps
CPU time 1.18 seconds
Started Jun 21 06:25:31 PM PDT 24
Finished Jun 21 06:25:33 PM PDT 24
Peak memory 209352 kb
Host smart-94f96266-7bce-4027-95a0-cdfa6acea0a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902903556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.3902903556
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2150585924
Short name T969
Test name
Test status
Simulation time 98859841 ps
CPU time 1.31 seconds
Started Jun 21 06:25:32 PM PDT 24
Finished Jun 21 06:25:35 PM PDT 24
Peak memory 216844 kb
Host smart-e6e3f59c-e06d-47cf-833d-bfee94e124e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150585924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2150585924
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3518628542
Short name T201
Test name
Test status
Simulation time 17963662 ps
CPU time 1.08 seconds
Started Jun 21 06:25:36 PM PDT 24
Finished Jun 21 06:25:38 PM PDT 24
Peak memory 210336 kb
Host smart-6566a545-e68c-44a8-b43c-f3f3a50c84c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518628542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.3518628542
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3294444126
Short name T138
Test name
Test status
Simulation time 29852040 ps
CPU time 1.01 seconds
Started Jun 21 06:25:34 PM PDT 24
Finished Jun 21 06:25:37 PM PDT 24
Peak memory 217612 kb
Host smart-30858fd8-025c-4ecd-b392-04f028fbe715
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294444126 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3294444126
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3497772301
Short name T874
Test name
Test status
Simulation time 20989881 ps
CPU time 0.88 seconds
Started Jun 21 06:25:30 PM PDT 24
Finished Jun 21 06:25:32 PM PDT 24
Peak memory 208708 kb
Host smart-99a0858c-2cd7-404c-a1c2-f5695d711a0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497772301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3497772301
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1970238737
Short name T905
Test name
Test status
Simulation time 284235400 ps
CPU time 1.51 seconds
Started Jun 21 06:25:32 PM PDT 24
Finished Jun 21 06:25:35 PM PDT 24
Peak memory 209140 kb
Host smart-634259d4-f041-41db-bb60-551ca7e967a7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970238737 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1970238737
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3938306745
Short name T896
Test name
Test status
Simulation time 2478054164 ps
CPU time 6.26 seconds
Started Jun 21 06:25:31 PM PDT 24
Finished Jun 21 06:25:39 PM PDT 24
Peak memory 217280 kb
Host smart-c478bd17-4163-44d8-ae13-a51f765ddf71
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938306745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3938306745
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2902373369
Short name T987
Test name
Test status
Simulation time 1541777721 ps
CPU time 7 seconds
Started Jun 21 06:25:34 PM PDT 24
Finished Jun 21 06:25:43 PM PDT 24
Peak memory 209252 kb
Host smart-bb3e3892-9652-4e8d-8d59-cdecc3c2effb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902373369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.2902373369
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.618015847
Short name T887
Test name
Test status
Simulation time 396976140 ps
CPU time 2.54 seconds
Started Jun 21 06:25:33 PM PDT 24
Finished Jun 21 06:25:37 PM PDT 24
Peak memory 210728 kb
Host smart-dd05f133-6bda-49a2-967d-345e69a2ea1f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618015847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.618015847
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4204873856
Short name T964
Test name
Test status
Simulation time 195184656 ps
CPU time 2.54 seconds
Started Jun 21 06:25:30 PM PDT 24
Finished Jun 21 06:25:34 PM PDT 24
Peak memory 217600 kb
Host smart-cb98654f-751a-41a6-b535-a2316358ef21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420487
3856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4204873856
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3053504444
Short name T959
Test name
Test status
Simulation time 23217166 ps
CPU time 1.22 seconds
Started Jun 21 06:25:30 PM PDT 24
Finished Jun 21 06:25:32 PM PDT 24
Peak memory 209356 kb
Host smart-5d4bf8b5-59fa-48b3-a805-364933ffe598
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053504444 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.3053504444
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.998819487
Short name T939
Test name
Test status
Simulation time 24034111 ps
CPU time 1.28 seconds
Started Jun 21 06:25:33 PM PDT 24
Finished Jun 21 06:25:36 PM PDT 24
Peak memory 211484 kb
Host smart-fe093ab6-d329-40da-b3c1-11f9fc2e8116
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998819487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
same_csr_outstanding.998819487
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.616816022
Short name T943
Test name
Test status
Simulation time 98358295 ps
CPU time 1.25 seconds
Started Jun 21 06:25:33 PM PDT 24
Finished Jun 21 06:25:36 PM PDT 24
Peak memory 217572 kb
Host smart-2bfc7eb9-12dc-4870-ad87-a59653f46264
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616816022 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.616816022
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.452638505
Short name T994
Test name
Test status
Simulation time 48010802 ps
CPU time 0.85 seconds
Started Jun 21 06:25:33 PM PDT 24
Finished Jun 21 06:25:35 PM PDT 24
Peak memory 209188 kb
Host smart-710cad75-d5ec-4724-b84d-91adc889a133
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452638505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.452638505
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.230261143
Short name T931
Test name
Test status
Simulation time 187895867 ps
CPU time 1.39 seconds
Started Jun 21 06:25:33 PM PDT 24
Finished Jun 21 06:25:37 PM PDT 24
Peak memory 208752 kb
Host smart-0adb63cf-4e9d-4635-883e-804460ef3c63
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230261143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.lc_ctrl_jtag_alert_test.230261143
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.908605775
Short name T900
Test name
Test status
Simulation time 4058208062 ps
CPU time 6.59 seconds
Started Jun 21 06:25:33 PM PDT 24
Finished Jun 21 06:25:41 PM PDT 24
Peak memory 217352 kb
Host smart-0223b08f-c584-4b3e-be39-736f2f02a619
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908605775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.908605775
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1604050049
Short name T946
Test name
Test status
Simulation time 1179729405 ps
CPU time 26.18 seconds
Started Jun 21 06:25:36 PM PDT 24
Finished Jun 21 06:26:03 PM PDT 24
Peak memory 217088 kb
Host smart-eb8335a6-18c6-42ed-b3d8-b52a2936526b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604050049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1604050049
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4052454908
Short name T883
Test name
Test status
Simulation time 58219375 ps
CPU time 1.32 seconds
Started Jun 21 06:25:31 PM PDT 24
Finished Jun 21 06:25:33 PM PDT 24
Peak memory 210600 kb
Host smart-dad368dc-516e-41ff-bad6-7fa17ececcc3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052454908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.4052454908
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3551623425
Short name T972
Test name
Test status
Simulation time 165865655 ps
CPU time 2.74 seconds
Started Jun 21 06:25:32 PM PDT 24
Finished Jun 21 06:25:36 PM PDT 24
Peak memory 217584 kb
Host smart-0d66e0a0-10fc-4571-8362-3cca336bcf13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355162
3425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3551623425
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2239632292
Short name T967
Test name
Test status
Simulation time 48479022 ps
CPU time 1.84 seconds
Started Jun 21 06:25:31 PM PDT 24
Finished Jun 21 06:25:34 PM PDT 24
Peak memory 209264 kb
Host smart-13890e3e-1687-414f-b5ab-1a2d4388dae9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239632292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.2239632292
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2545734888
Short name T937
Test name
Test status
Simulation time 21112978 ps
CPU time 1.25 seconds
Started Jun 21 06:25:40 PM PDT 24
Finished Jun 21 06:25:43 PM PDT 24
Peak memory 209336 kb
Host smart-73c50a7f-2b6f-4eaa-9ba1-f6680dbfc4f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545734888 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.2545734888
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1257511702
Short name T925
Test name
Test status
Simulation time 19836284 ps
CPU time 1.52 seconds
Started Jun 21 06:25:31 PM PDT 24
Finished Jun 21 06:25:34 PM PDT 24
Peak memory 209428 kb
Host smart-2a56c995-3364-46e9-a1ad-d29d5404ee76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257511702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.1257511702
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.327394444
Short name T999
Test name
Test status
Simulation time 47079875 ps
CPU time 3.21 seconds
Started Jun 21 06:25:31 PM PDT 24
Finished Jun 21 06:25:35 PM PDT 24
Peak memory 217660 kb
Host smart-d7ff99a9-46ae-487c-bf79-d89ec04322f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327394444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.327394444
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.4238986871
Short name T970
Test name
Test status
Simulation time 30849127 ps
CPU time 1.87 seconds
Started Jun 21 06:25:30 PM PDT 24
Finished Jun 21 06:25:32 PM PDT 24
Peak memory 217616 kb
Host smart-25943d44-da2b-49ec-b898-a8eba36e66bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238986871 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.4238986871
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1658863778
Short name T203
Test name
Test status
Simulation time 34995807 ps
CPU time 0.84 seconds
Started Jun 21 06:25:33 PM PDT 24
Finished Jun 21 06:25:35 PM PDT 24
Peak memory 208728 kb
Host smart-9762134b-1993-4d71-9acf-0439da021fef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658863778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1658863778
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2063113033
Short name T955
Test name
Test status
Simulation time 168814188 ps
CPU time 1.63 seconds
Started Jun 21 06:25:40 PM PDT 24
Finished Jun 21 06:25:43 PM PDT 24
Peak memory 209252 kb
Host smart-22943f46-f639-47f9-ba51-c28d32596098
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063113033 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2063113033
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3153043500
Short name T880
Test name
Test status
Simulation time 1894128321 ps
CPU time 10.54 seconds
Started Jun 21 06:25:33 PM PDT 24
Finished Jun 21 06:25:45 PM PDT 24
Peak memory 209180 kb
Host smart-0ada2bf3-e6ea-4b9b-9a33-26eb2f8b01cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153043500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3153043500
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1654041471
Short name T932
Test name
Test status
Simulation time 1511959995 ps
CPU time 4.92 seconds
Started Jun 21 06:25:40 PM PDT 24
Finished Jun 21 06:25:46 PM PDT 24
Peak memory 209292 kb
Host smart-93079e4d-56a2-468c-a2e6-6660c64c93ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654041471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1654041471
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4234594259
Short name T875
Test name
Test status
Simulation time 47121049 ps
CPU time 1.85 seconds
Started Jun 21 06:25:33 PM PDT 24
Finished Jun 21 06:25:37 PM PDT 24
Peak memory 210628 kb
Host smart-cb707a19-4513-4dcd-93cc-ebdcc1ed19e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234594259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.4234594259
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.618944974
Short name T957
Test name
Test status
Simulation time 418066047 ps
CPU time 2.12 seconds
Started Jun 21 06:25:32 PM PDT 24
Finished Jun 21 06:25:35 PM PDT 24
Peak memory 217664 kb
Host smart-64777f2d-6f3f-4ff8-a717-cebdf5aa014e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618944
974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.618944974
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.185466358
Short name T977
Test name
Test status
Simulation time 129023281 ps
CPU time 1.92 seconds
Started Jun 21 06:25:32 PM PDT 24
Finished Jun 21 06:25:36 PM PDT 24
Peak memory 209348 kb
Host smart-cbfccc14-0162-4188-8aa6-e027c7fe8dfb
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185466358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.185466358
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3720958114
Short name T923
Test name
Test status
Simulation time 175139869 ps
CPU time 1.37 seconds
Started Jun 21 06:25:30 PM PDT 24
Finished Jun 21 06:25:32 PM PDT 24
Peak memory 211644 kb
Host smart-ae69c202-a765-43c7-9ed6-e570a660522b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720958114 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3720958114
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3506128672
Short name T953
Test name
Test status
Simulation time 51009710 ps
CPU time 2.08 seconds
Started Jun 21 06:25:30 PM PDT 24
Finished Jun 21 06:25:32 PM PDT 24
Peak memory 209244 kb
Host smart-c2f78c3e-f624-4dd4-bc82-8ecb56c31765
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506128672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.3506128672
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1353787056
Short name T962
Test name
Test status
Simulation time 538335639 ps
CPU time 4.95 seconds
Started Jun 21 06:25:34 PM PDT 24
Finished Jun 21 06:25:41 PM PDT 24
Peak memory 217684 kb
Host smart-bfa37bfb-913a-4ddd-ae6b-4a7acffe2135
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353787056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1353787056
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1344782008
Short name T885
Test name
Test status
Simulation time 586969203 ps
CPU time 4.07 seconds
Started Jun 21 06:25:32 PM PDT 24
Finished Jun 21 06:25:38 PM PDT 24
Peak memory 222348 kb
Host smart-206f1d81-1ecd-4f78-b4dd-4758aa0721eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344782008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.1344782008
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2927800294
Short name T901
Test name
Test status
Simulation time 107344914 ps
CPU time 1.7 seconds
Started Jun 21 06:25:37 PM PDT 24
Finished Jun 21 06:25:40 PM PDT 24
Peak memory 217588 kb
Host smart-9f851437-eb23-414a-b778-5a686c2ce8d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927800294 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.2927800294
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3644039332
Short name T211
Test name
Test status
Simulation time 15345039 ps
CPU time 1.09 seconds
Started Jun 21 06:25:41 PM PDT 24
Finished Jun 21 06:25:43 PM PDT 24
Peak memory 209044 kb
Host smart-3f415750-952c-4c2d-82e2-008db822a2d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644039332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.3644039332
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2421499060
Short name T992
Test name
Test status
Simulation time 24827491 ps
CPU time 0.93 seconds
Started Jun 21 06:25:37 PM PDT 24
Finished Jun 21 06:25:39 PM PDT 24
Peak memory 209088 kb
Host smart-640c67d7-3b79-4ef2-a2c7-ac19d7080c5b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421499060 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2421499060
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1268290466
Short name T906
Test name
Test status
Simulation time 2407901060 ps
CPU time 12.48 seconds
Started Jun 21 06:25:39 PM PDT 24
Finished Jun 21 06:25:53 PM PDT 24
Peak memory 208944 kb
Host smart-6beb1176-06dc-41fd-b497-dc72c0979ccc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268290466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1268290466
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1811005805
Short name T876
Test name
Test status
Simulation time 974563582 ps
CPU time 23.29 seconds
Started Jun 21 06:25:33 PM PDT 24
Finished Jun 21 06:25:58 PM PDT 24
Peak memory 208992 kb
Host smart-df1e6413-a761-4815-9e3c-4777d0bccb4e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811005805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1811005805
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3475413965
Short name T118
Test name
Test status
Simulation time 215544182 ps
CPU time 1.72 seconds
Started Jun 21 06:25:31 PM PDT 24
Finished Jun 21 06:25:34 PM PDT 24
Peak memory 210772 kb
Host smart-b0709160-2ad8-4c44-997b-9d814440b216
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475413965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3475413965
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.135766804
Short name T961
Test name
Test status
Simulation time 1053317600 ps
CPU time 1.52 seconds
Started Jun 21 06:25:43 PM PDT 24
Finished Jun 21 06:25:45 PM PDT 24
Peak memory 218712 kb
Host smart-b2715230-0b10-4400-adb2-ae2d8449bfb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135766
804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.135766804
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3494208289
Short name T965
Test name
Test status
Simulation time 702127765 ps
CPU time 4.32 seconds
Started Jun 21 06:25:34 PM PDT 24
Finished Jun 21 06:25:40 PM PDT 24
Peak memory 209196 kb
Host smart-1d39a9a9-e125-4325-9cf3-789e953dd1c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494208289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.3494208289
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2022439200
Short name T947
Test name
Test status
Simulation time 52677997 ps
CPU time 1.12 seconds
Started Jun 21 06:25:42 PM PDT 24
Finished Jun 21 06:25:44 PM PDT 24
Peak memory 209332 kb
Host smart-82ff6b78-f873-4570-9204-4bcb7c2e6b8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022439200 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2022439200
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3831339014
Short name T993
Test name
Test status
Simulation time 56938603 ps
CPU time 1.11 seconds
Started Jun 21 06:25:37 PM PDT 24
Finished Jun 21 06:25:40 PM PDT 24
Peak memory 209344 kb
Host smart-7a5d631a-a444-4d07-a708-65a28ec38d10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831339014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3831339014
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1242181909
Short name T951
Test name
Test status
Simulation time 71644066 ps
CPU time 2.99 seconds
Started Jun 21 06:25:37 PM PDT 24
Finished Jun 21 06:25:41 PM PDT 24
Peak memory 217688 kb
Host smart-d8fabd0a-f1ba-4e56-be81-13dea9253bdf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242181909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1242181909
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1406719859
Short name T151
Test name
Test status
Simulation time 37218251 ps
CPU time 1.27 seconds
Started Jun 21 06:25:37 PM PDT 24
Finished Jun 21 06:25:39 PM PDT 24
Peak memory 217588 kb
Host smart-41c51eac-92e0-4dad-a629-9f3a46608126
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406719859 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1406719859
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1054805135
Short name T217
Test name
Test status
Simulation time 17884596 ps
CPU time 1.14 seconds
Started Jun 21 06:25:40 PM PDT 24
Finished Jun 21 06:25:42 PM PDT 24
Peak memory 217196 kb
Host smart-e1a1cd3a-2a50-42d7-8ecf-3654e97f031d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054805135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.1054805135
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1466046211
Short name T941
Test name
Test status
Simulation time 38522927 ps
CPU time 0.89 seconds
Started Jun 21 06:25:37 PM PDT 24
Finished Jun 21 06:25:38 PM PDT 24
Peak memory 209156 kb
Host smart-60f5ab0a-5708-491c-92b6-220504d94b21
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466046211 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.1466046211
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.4003371402
Short name T989
Test name
Test status
Simulation time 4775332440 ps
CPU time 14.92 seconds
Started Jun 21 06:25:43 PM PDT 24
Finished Jun 21 06:25:59 PM PDT 24
Peak memory 209292 kb
Host smart-5f13ae67-ad09-49c9-ab82-9fb237253993
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003371402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.4003371402
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.4185374390
Short name T877
Test name
Test status
Simulation time 1926049111 ps
CPU time 18.76 seconds
Started Jun 21 06:25:37 PM PDT 24
Finished Jun 21 06:25:56 PM PDT 24
Peak memory 209192 kb
Host smart-0bdd1a13-bf57-475e-a342-4b4d642aec25
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185374390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.4185374390
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.948021849
Short name T886
Test name
Test status
Simulation time 107589897 ps
CPU time 1.27 seconds
Started Jun 21 06:25:41 PM PDT 24
Finished Jun 21 06:25:43 PM PDT 24
Peak memory 210656 kb
Host smart-6f627568-fa9f-4f51-a068-ad70e6d5347f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948021849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.948021849
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4290296100
Short name T986
Test name
Test status
Simulation time 451515709 ps
CPU time 1.9 seconds
Started Jun 21 06:25:37 PM PDT 24
Finished Jun 21 06:25:39 PM PDT 24
Peak memory 218748 kb
Host smart-711ab66b-67eb-40cc-a2b9-17787a2da15c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429029
6100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4290296100
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3445687780
Short name T878
Test name
Test status
Simulation time 643646956 ps
CPU time 1.25 seconds
Started Jun 21 06:25:40 PM PDT 24
Finished Jun 21 06:25:42 PM PDT 24
Peak memory 217300 kb
Host smart-f498e4cb-bb63-4fde-922e-afd059d84315
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445687780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.3445687780
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.342083251
Short name T921
Test name
Test status
Simulation time 77692550 ps
CPU time 1.85 seconds
Started Jun 21 06:25:42 PM PDT 24
Finished Jun 21 06:25:46 PM PDT 24
Peak memory 209320 kb
Host smart-76ae4eac-a525-46a4-98fb-cc834bd1b12e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342083251 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.342083251
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.4145841396
Short name T152
Test name
Test status
Simulation time 221709843 ps
CPU time 1.35 seconds
Started Jun 21 06:25:43 PM PDT 24
Finished Jun 21 06:25:45 PM PDT 24
Peak memory 217608 kb
Host smart-d5dda7ac-5259-4704-b75f-dee771deaa29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145841396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.4145841396
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.438235484
Short name T983
Test name
Test status
Simulation time 157719481 ps
CPU time 3.42 seconds
Started Jun 21 06:25:41 PM PDT 24
Finished Jun 21 06:25:46 PM PDT 24
Peak memory 217656 kb
Host smart-e0d47cf5-ba5f-451d-8330-60a4fc1d0136
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438235484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.438235484
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2382596842
Short name T913
Test name
Test status
Simulation time 83381015 ps
CPU time 1.55 seconds
Started Jun 21 06:25:42 PM PDT 24
Finished Jun 21 06:25:45 PM PDT 24
Peak memory 219676 kb
Host smart-0af34c49-f2f6-431d-a855-b159be2cd4dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382596842 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2382596842
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.4061134115
Short name T205
Test name
Test status
Simulation time 11934650 ps
CPU time 0.95 seconds
Started Jun 21 06:25:40 PM PDT 24
Finished Jun 21 06:25:43 PM PDT 24
Peak memory 209016 kb
Host smart-90e9ff11-86d6-401a-a8d7-7f0a82939ee9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061134115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.4061134115
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2095355475
Short name T890
Test name
Test status
Simulation time 43975302 ps
CPU time 1.11 seconds
Started Jun 21 06:25:39 PM PDT 24
Finished Jun 21 06:25:41 PM PDT 24
Peak memory 209252 kb
Host smart-9ca81751-8763-4f07-95de-ac8d55d82043
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095355475 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2095355475
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2778903391
Short name T904
Test name
Test status
Simulation time 2043367334 ps
CPU time 12.34 seconds
Started Jun 21 06:25:38 PM PDT 24
Finished Jun 21 06:25:51 PM PDT 24
Peak memory 217076 kb
Host smart-ce9347cc-ce8c-4a0f-b650-1865e6c6f0f6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778903391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2778903391
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2815398959
Short name T881
Test name
Test status
Simulation time 8215097957 ps
CPU time 29.72 seconds
Started Jun 21 06:25:39 PM PDT 24
Finished Jun 21 06:26:10 PM PDT 24
Peak memory 217244 kb
Host smart-a673649b-5f23-4438-a181-d6c29011fdd5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815398959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2815398959
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3905508154
Short name T139
Test name
Test status
Simulation time 315265461 ps
CPU time 4.44 seconds
Started Jun 21 06:25:41 PM PDT 24
Finished Jun 21 06:25:47 PM PDT 24
Peak memory 210708 kb
Host smart-64a2dfee-b6ed-42ee-8ea0-4f859c151ad7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905508154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3905508154
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2132002501
Short name T996
Test name
Test status
Simulation time 101142654 ps
CPU time 1.58 seconds
Started Jun 21 06:25:39 PM PDT 24
Finished Jun 21 06:25:41 PM PDT 24
Peak memory 218800 kb
Host smart-8af8ab27-58e5-4305-a25e-a34100f773bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213200
2501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2132002501
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.198737652
Short name T123
Test name
Test status
Simulation time 44564506 ps
CPU time 1.2 seconds
Started Jun 21 06:25:38 PM PDT 24
Finished Jun 21 06:25:40 PM PDT 24
Peak memory 209264 kb
Host smart-64aaea96-9925-40b4-a0a9-9d052b8d14c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198737652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.198737652
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2908372361
Short name T956
Test name
Test status
Simulation time 29763528 ps
CPU time 1.54 seconds
Started Jun 21 06:25:42 PM PDT 24
Finished Jun 21 06:25:45 PM PDT 24
Peak memory 209388 kb
Host smart-2e064a69-af1a-48fd-a8d0-59b3ef458857
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908372361 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2908372361
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2909485107
Short name T218
Test name
Test status
Simulation time 35819037 ps
CPU time 1.22 seconds
Started Jun 21 06:25:38 PM PDT 24
Finished Jun 21 06:25:40 PM PDT 24
Peak memory 209324 kb
Host smart-56e6c8b9-7664-4cdf-9df6-62712f8c691e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909485107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2909485107
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.819578614
Short name T889
Test name
Test status
Simulation time 152832627 ps
CPU time 2.8 seconds
Started Jun 21 06:25:37 PM PDT 24
Finished Jun 21 06:25:40 PM PDT 24
Peak memory 217744 kb
Host smart-b09aed1d-242e-4d66-bd6e-288a452b18c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819578614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.819578614
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.611954513
Short name T137
Test name
Test status
Simulation time 105177140 ps
CPU time 3.03 seconds
Started Jun 21 06:25:42 PM PDT 24
Finished Jun 21 06:25:46 PM PDT 24
Peak memory 222396 kb
Host smart-affeb840-cdcd-41dc-893c-4e65d03f44c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611954513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_e
rr.611954513
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.191161491
Short name T103
Test name
Test status
Simulation time 254581871 ps
CPU time 1.28 seconds
Started Jun 21 06:28:54 PM PDT 24
Finished Jun 21 06:28:57 PM PDT 24
Peak memory 208992 kb
Host smart-30f800d9-3e13-4e6b-a342-b6260fbf2490
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191161491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.191161491
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1596533315
Short name T302
Test name
Test status
Simulation time 3915848667 ps
CPU time 18.45 seconds
Started Jun 21 06:28:45 PM PDT 24
Finished Jun 21 06:29:04 PM PDT 24
Peak memory 218412 kb
Host smart-cfbd4e90-8042-436b-83c1-8d58c9eded11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596533315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1596533315
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.1174616013
Short name T416
Test name
Test status
Simulation time 4293103389 ps
CPU time 35.14 seconds
Started Jun 21 06:28:51 PM PDT 24
Finished Jun 21 06:29:28 PM PDT 24
Peak memory 219064 kb
Host smart-c20891e4-6a44-4f44-a67e-734871a5e0da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174616013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.1174616013
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.3839940989
Short name T670
Test name
Test status
Simulation time 531149418 ps
CPU time 4.23 seconds
Started Jun 21 06:28:30 PM PDT 24
Finished Jun 21 06:28:36 PM PDT 24
Peak memory 217456 kb
Host smart-80d21f5d-66f6-4dde-a0c0-6075508e0cd5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839940989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.3
839940989
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.938818025
Short name T784
Test name
Test status
Simulation time 723516596 ps
CPU time 11.27 seconds
Started Jun 21 06:28:52 PM PDT 24
Finished Jun 21 06:29:04 PM PDT 24
Peak memory 222044 kb
Host smart-8720e642-8d7b-450d-b479-529fd552dbea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938818025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
prog_failure.938818025
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3073399068
Short name T397
Test name
Test status
Simulation time 1919989613 ps
CPU time 15.22 seconds
Started Jun 21 06:28:53 PM PDT 24
Finished Jun 21 06:29:10 PM PDT 24
Peak memory 217740 kb
Host smart-fbc1daad-0109-47f3-b546-6e1609d225fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073399068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.3073399068
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2918219691
Short name T627
Test name
Test status
Simulation time 2735599657 ps
CPU time 8.77 seconds
Started Jun 21 06:28:41 PM PDT 24
Finished Jun 21 06:28:51 PM PDT 24
Peak memory 217828 kb
Host smart-556a99d7-990c-4235-8199-37d9b2d3d1aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918219691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
2918219691
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.488354786
Short name T633
Test name
Test status
Simulation time 1253240287 ps
CPU time 37.86 seconds
Started Jun 21 06:28:38 PM PDT 24
Finished Jun 21 06:29:17 PM PDT 24
Peak memory 252524 kb
Host smart-b5ba57a9-1935-46b2-b6a8-7cf222c50980
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488354786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_state_failure.488354786
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1636558674
Short name T556
Test name
Test status
Simulation time 5000543783 ps
CPU time 11.28 seconds
Started Jun 21 06:28:37 PM PDT 24
Finished Jun 21 06:28:49 PM PDT 24
Peak memory 226456 kb
Host smart-f1c30e7a-1ada-417e-9042-74ea93e0b0ed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636558674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.1636558674
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1706278360
Short name T288
Test name
Test status
Simulation time 67241585 ps
CPU time 2.64 seconds
Started Jun 21 06:28:36 PM PDT 24
Finished Jun 21 06:28:40 PM PDT 24
Peak memory 222104 kb
Host smart-c14d8647-1070-45e5-aefa-f8b93bc8dbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706278360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1706278360
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1162985974
Short name T631
Test name
Test status
Simulation time 363356513 ps
CPU time 19.44 seconds
Started Jun 21 06:28:47 PM PDT 24
Finished Jun 21 06:29:07 PM PDT 24
Peak memory 217904 kb
Host smart-8b99e468-8582-47cb-bb02-d15b2bc5166f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162985974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1162985974
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.1709189351
Short name T821
Test name
Test status
Simulation time 882973948 ps
CPU time 19.09 seconds
Started Jun 21 06:28:53 PM PDT 24
Finished Jun 21 06:29:14 PM PDT 24
Peak memory 219040 kb
Host smart-c1803b3d-eb6d-45be-8d67-f70bea1109a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709189351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.1709189351
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2482162142
Short name T659
Test name
Test status
Simulation time 1367397939 ps
CPU time 18.02 seconds
Started Jun 21 06:28:52 PM PDT 24
Finished Jun 21 06:29:11 PM PDT 24
Peak memory 226200 kb
Host smart-82843ba6-a51f-41f4-b8b3-f2952461da2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482162142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2482162142
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2141378428
Short name T538
Test name
Test status
Simulation time 428412364 ps
CPU time 8.3 seconds
Started Jun 21 06:28:51 PM PDT 24
Finished Jun 21 06:29:00 PM PDT 24
Peak memory 218380 kb
Host smart-eeb3fa48-2a43-4c8c-b754-52209955ca0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141378428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
141378428
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.687847500
Short name T744
Test name
Test status
Simulation time 343990734 ps
CPU time 12.73 seconds
Started Jun 21 06:28:51 PM PDT 24
Finished Jun 21 06:29:04 PM PDT 24
Peak memory 218480 kb
Host smart-1d890459-180f-4e8f-9ea6-d531758ed837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687847500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.687847500
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.873683062
Short name T653
Test name
Test status
Simulation time 32495028 ps
CPU time 1.64 seconds
Started Jun 21 06:28:40 PM PDT 24
Finished Jun 21 06:28:42 PM PDT 24
Peak memory 217852 kb
Host smart-898443ae-3b9a-42a6-b40e-6220419c6297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873683062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.873683062
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.1662779101
Short name T475
Test name
Test status
Simulation time 299331685 ps
CPU time 29.28 seconds
Started Jun 21 06:28:37 PM PDT 24
Finished Jun 21 06:29:07 PM PDT 24
Peak memory 251036 kb
Host smart-f89f9717-dee9-4c62-925d-2c2f4ba8c1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662779101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1662779101
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.3148292639
Short name T269
Test name
Test status
Simulation time 165082313 ps
CPU time 3.2 seconds
Started Jun 21 06:28:44 PM PDT 24
Finished Jun 21 06:28:48 PM PDT 24
Peak memory 222532 kb
Host smart-106417b5-11f5-4d9a-bd1a-89b8d69f3907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148292639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3148292639
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.2261172929
Short name T516
Test name
Test status
Simulation time 66794755372 ps
CPU time 355.99 seconds
Started Jun 21 06:28:44 PM PDT 24
Finished Jun 21 06:34:41 PM PDT 24
Peak memory 259376 kb
Host smart-fe83aad4-0c0a-4752-86fb-e046481a8ac8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261172929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.2261172929
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.4248698583
Short name T272
Test name
Test status
Simulation time 35722893 ps
CPU time 0.93 seconds
Started Jun 21 06:28:41 PM PDT 24
Finished Jun 21 06:28:43 PM PDT 24
Peak memory 211964 kb
Host smart-226451e1-a577-45e7-8c49-9039ac18a3a2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248698583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.4248698583
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1154275122
Short name T186
Test name
Test status
Simulation time 164817293 ps
CPU time 0.84 seconds
Started Jun 21 06:28:45 PM PDT 24
Finished Jun 21 06:28:47 PM PDT 24
Peak memory 208856 kb
Host smart-906e8379-01e6-4431-8e64-85c17ca9534a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154275122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1154275122
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2940621556
Short name T590
Test name
Test status
Simulation time 14061276 ps
CPU time 0.82 seconds
Started Jun 21 06:28:53 PM PDT 24
Finished Jun 21 06:28:55 PM PDT 24
Peak memory 208972 kb
Host smart-613e77bf-0c38-47da-909a-4b430fd98cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940621556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2940621556
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1870344365
Short name T798
Test name
Test status
Simulation time 713424169 ps
CPU time 13.6 seconds
Started Jun 21 06:28:45 PM PDT 24
Finished Jun 21 06:28:59 PM PDT 24
Peak memory 218328 kb
Host smart-78844d48-64da-41fb-9680-0eb14eb2592c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870344365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1870344365
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.2527595926
Short name T536
Test name
Test status
Simulation time 892855925 ps
CPU time 8.21 seconds
Started Jun 21 06:28:48 PM PDT 24
Finished Jun 21 06:28:57 PM PDT 24
Peak memory 217416 kb
Host smart-3b0d540f-b037-4e20-b7b8-8066493edcc0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527595926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2527595926
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.3062813433
Short name T552
Test name
Test status
Simulation time 6540278671 ps
CPU time 26.88 seconds
Started Jun 21 06:28:54 PM PDT 24
Finished Jun 21 06:29:23 PM PDT 24
Peak memory 218472 kb
Host smart-d5c86566-679d-4493-bf2c-9bbd22f861e7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062813433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.3062813433
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2011595581
Short name T849
Test name
Test status
Simulation time 1388180855 ps
CPU time 15.29 seconds
Started Jun 21 06:28:49 PM PDT 24
Finished Jun 21 06:29:05 PM PDT 24
Peak memory 217832 kb
Host smart-db91cbd0-f0a6-4559-b750-c7e1468bfc49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011595581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
011595581
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.82300325
Short name T630
Test name
Test status
Simulation time 133966804 ps
CPU time 3.14 seconds
Started Jun 21 06:28:54 PM PDT 24
Finished Jun 21 06:28:59 PM PDT 24
Peak memory 221820 kb
Host smart-65a27849-3827-4466-b8f7-c13c47394fde
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82300325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_p
rog_failure.82300325
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1042220833
Short name T512
Test name
Test status
Simulation time 755694694 ps
CPU time 20.6 seconds
Started Jun 21 06:28:52 PM PDT 24
Finished Jun 21 06:29:14 PM PDT 24
Peak memory 217488 kb
Host smart-f29181ba-d4ef-47a2-b560-de16ec56e680
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042220833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.1042220833
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.1042862942
Short name T191
Test name
Test status
Simulation time 172558743 ps
CPU time 3.49 seconds
Started Jun 21 06:28:49 PM PDT 24
Finished Jun 21 06:28:53 PM PDT 24
Peak memory 217732 kb
Host smart-50542e59-7aba-4433-a044-603b1a7af3df
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042862942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
1042862942
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3718003921
Short name T297
Test name
Test status
Simulation time 5881575820 ps
CPU time 55.3 seconds
Started Jun 21 06:28:50 PM PDT 24
Finished Jun 21 06:29:46 PM PDT 24
Peak memory 283604 kb
Host smart-f90b124e-8de6-4ff6-824d-8541100b7ccc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718003921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3718003921
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.4190399728
Short name T610
Test name
Test status
Simulation time 1359461794 ps
CPU time 13.83 seconds
Started Jun 21 06:28:47 PM PDT 24
Finished Jun 21 06:29:02 PM PDT 24
Peak memory 250956 kb
Host smart-4f0cb9a4-bbd5-4002-93bc-8be982260199
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190399728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.4190399728
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.324976326
Short name T254
Test name
Test status
Simulation time 274316539 ps
CPU time 2.98 seconds
Started Jun 21 06:28:42 PM PDT 24
Finished Jun 21 06:28:46 PM PDT 24
Peak memory 218268 kb
Host smart-2a890da7-7207-47f1-81f2-973bb1bd31ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324976326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.324976326
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.3498503350
Short name T190
Test name
Test status
Simulation time 818367622 ps
CPU time 13.89 seconds
Started Jun 21 06:28:46 PM PDT 24
Finished Jun 21 06:29:01 PM PDT 24
Peak memory 214696 kb
Host smart-40a5fa49-a52e-4c4a-ba20-c7981c4bee02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498503350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3498503350
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.1130131124
Short name T86
Test name
Test status
Simulation time 873013343 ps
CPU time 35.2 seconds
Started Jun 21 06:28:53 PM PDT 24
Finished Jun 21 06:29:30 PM PDT 24
Peak memory 270704 kb
Host smart-a3cdd110-feda-414c-bffc-09cfb112a516
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130131124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.1130131124
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.4085612005
Short name T177
Test name
Test status
Simulation time 545998809 ps
CPU time 16.68 seconds
Started Jun 21 06:28:52 PM PDT 24
Finished Jun 21 06:29:11 PM PDT 24
Peak memory 218568 kb
Host smart-fda5bd74-ae81-4e90-87a3-1883db662e12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085612005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.4085612005
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1923636576
Short name T543
Test name
Test status
Simulation time 302912564 ps
CPU time 7.56 seconds
Started Jun 21 06:28:52 PM PDT 24
Finished Jun 21 06:29:01 PM PDT 24
Peak memory 218392 kb
Host smart-a519b236-8ea3-455d-beee-3e066614fb07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923636576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1923636576
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.1089188824
Short name T862
Test name
Test status
Simulation time 505012939 ps
CPU time 7.64 seconds
Started Jun 21 06:28:50 PM PDT 24
Finished Jun 21 06:28:59 PM PDT 24
Peak memory 218396 kb
Host smart-b55ded3f-72fc-49d6-b43a-1d29b6d486a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089188824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.1
089188824
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.4159867925
Short name T178
Test name
Test status
Simulation time 214428107 ps
CPU time 6.41 seconds
Started Jun 21 06:28:48 PM PDT 24
Finished Jun 21 06:28:55 PM PDT 24
Peak memory 224584 kb
Host smart-5a17f4d8-f946-42b9-be7c-177c00bc9bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159867925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.4159867925
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.2988254961
Short name T477
Test name
Test status
Simulation time 108518912 ps
CPU time 7.53 seconds
Started Jun 21 06:28:34 PM PDT 24
Finished Jun 21 06:28:43 PM PDT 24
Peak memory 214716 kb
Host smart-1caaf2fd-8719-47f7-90f6-c11c3dfcac20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988254961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2988254961
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3556108533
Short name T863
Test name
Test status
Simulation time 1110726740 ps
CPU time 26.07 seconds
Started Jun 21 06:28:40 PM PDT 24
Finished Jun 21 06:29:07 PM PDT 24
Peak memory 251040 kb
Host smart-ddb83d96-093f-4ab0-82f8-11bb11a75c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556108533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3556108533
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.346630570
Short name T596
Test name
Test status
Simulation time 43056213 ps
CPU time 2.93 seconds
Started Jun 21 06:28:43 PM PDT 24
Finished Jun 21 06:28:46 PM PDT 24
Peak memory 222316 kb
Host smart-775b49a9-8bd5-485e-93b2-6d3defbfdf71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346630570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.346630570
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.207636809
Short name T761
Test name
Test status
Simulation time 2991928221 ps
CPU time 106.35 seconds
Started Jun 21 06:28:47 PM PDT 24
Finished Jun 21 06:30:34 PM PDT 24
Peak memory 251068 kb
Host smart-35c8acca-6563-479d-81a5-dca01c8390e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207636809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.207636809
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.331374654
Short name T600
Test name
Test status
Simulation time 12979639 ps
CPU time 0.95 seconds
Started Jun 21 06:28:41 PM PDT 24
Finished Jun 21 06:28:43 PM PDT 24
Peak memory 211928 kb
Host smart-ecf131f7-af4e-4412-bb3b-b700c3e7bed1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331374654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctr
l_volatile_unlock_smoke.331374654
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.176161293
Short name T752
Test name
Test status
Simulation time 22387274 ps
CPU time 0.91 seconds
Started Jun 21 06:29:12 PM PDT 24
Finished Jun 21 06:29:16 PM PDT 24
Peak memory 208952 kb
Host smart-01c353be-29be-4344-bcbe-f75aa5eefac9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176161293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.176161293
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.153655885
Short name T323
Test name
Test status
Simulation time 697222719 ps
CPU time 9.45 seconds
Started Jun 21 06:29:07 PM PDT 24
Finished Jun 21 06:29:18 PM PDT 24
Peak memory 226204 kb
Host smart-bf007826-902b-4cb8-ba69-5ad05c4ff591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153655885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.153655885
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1626532385
Short name T65
Test name
Test status
Simulation time 434981642 ps
CPU time 3.65 seconds
Started Jun 21 06:29:11 PM PDT 24
Finished Jun 21 06:29:17 PM PDT 24
Peak memory 217164 kb
Host smart-7b7dadec-34ee-43c9-b6eb-788f7fd43d5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626532385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1626532385
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.487535187
Short name T181
Test name
Test status
Simulation time 2217526521 ps
CPU time 34.02 seconds
Started Jun 21 06:29:09 PM PDT 24
Finished Jun 21 06:29:46 PM PDT 24
Peak memory 219032 kb
Host smart-514de6c8-5163-4e59-ac4f-5fd4b7e27686
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487535187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_er
rors.487535187
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.664635547
Short name T501
Test name
Test status
Simulation time 321578869 ps
CPU time 5.3 seconds
Started Jun 21 06:29:13 PM PDT 24
Finished Jun 21 06:29:20 PM PDT 24
Peak memory 221972 kb
Host smart-a2f11809-ca1b-4efa-8979-5ad280604398
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664635547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag
_prog_failure.664635547
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2819226311
Short name T525
Test name
Test status
Simulation time 1014931818 ps
CPU time 3.73 seconds
Started Jun 21 06:29:11 PM PDT 24
Finished Jun 21 06:29:17 PM PDT 24
Peak memory 217792 kb
Host smart-7b4b3876-ea11-4d7a-9e4f-2863562c38ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819226311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.2819226311
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3129015615
Short name T251
Test name
Test status
Simulation time 8685683860 ps
CPU time 78.67 seconds
Started Jun 21 06:29:12 PM PDT 24
Finished Jun 21 06:30:33 PM PDT 24
Peak memory 267592 kb
Host smart-a0251bae-ebea-4094-881a-7e6899e08b41
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129015615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.3129015615
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2535340485
Short name T255
Test name
Test status
Simulation time 1403420707 ps
CPU time 13.95 seconds
Started Jun 21 06:29:03 PM PDT 24
Finished Jun 21 06:29:18 PM PDT 24
Peak memory 250960 kb
Host smart-c44de735-7691-459a-9d54-7e5cb7a9f3bc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535340485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.2535340485
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.894782417
Short name T766
Test name
Test status
Simulation time 38224609 ps
CPU time 2.44 seconds
Started Jun 21 06:29:15 PM PDT 24
Finished Jun 21 06:29:24 PM PDT 24
Peak memory 218336 kb
Host smart-129b53c9-3347-4af3-a163-ef5832fb29dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894782417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.894782417
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.2787779593
Short name T334
Test name
Test status
Simulation time 388054218 ps
CPU time 13.42 seconds
Started Jun 21 06:29:11 PM PDT 24
Finished Jun 21 06:29:27 PM PDT 24
Peak memory 226204 kb
Host smart-4ac0d901-a138-49c5-8b4e-0167a833b16a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787779593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.2787779593
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.760897812
Short name T765
Test name
Test status
Simulation time 902689653 ps
CPU time 16.72 seconds
Started Jun 21 06:29:09 PM PDT 24
Finished Jun 21 06:29:29 PM PDT 24
Peak memory 218404 kb
Host smart-fe6ff0b2-e77c-4784-bf94-8e37124066ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760897812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di
gest.760897812
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.815064211
Short name T708
Test name
Test status
Simulation time 894534711 ps
CPU time 6.64 seconds
Started Jun 21 06:29:05 PM PDT 24
Finished Jun 21 06:29:12 PM PDT 24
Peak memory 226204 kb
Host smart-83ae369f-0db1-47a0-94ef-a58046724233
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815064211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.815064211
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.2435164339
Short name T701
Test name
Test status
Simulation time 851208876 ps
CPU time 6.78 seconds
Started Jun 21 06:29:10 PM PDT 24
Finished Jun 21 06:29:20 PM PDT 24
Peak memory 224752 kb
Host smart-70917bbe-d83e-4939-bb1f-0d60522b7544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435164339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.2435164339
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.761623354
Short name T756
Test name
Test status
Simulation time 37931921 ps
CPU time 1.65 seconds
Started Jun 21 06:29:01 PM PDT 24
Finished Jun 21 06:29:04 PM PDT 24
Peak memory 213908 kb
Host smart-4f226b1f-ee97-4660-8a76-3d6e1aa47269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761623354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.761623354
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.3848826996
Short name T308
Test name
Test status
Simulation time 1632138027 ps
CPU time 16.86 seconds
Started Jun 21 06:29:09 PM PDT 24
Finished Jun 21 06:29:29 PM PDT 24
Peak memory 251120 kb
Host smart-3c8208f5-3c5e-4e66-9b0d-7b3e4c7354f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848826996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.3848826996
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.574863498
Short name T675
Test name
Test status
Simulation time 87052102 ps
CPU time 8.08 seconds
Started Jun 21 06:29:10 PM PDT 24
Finished Jun 21 06:29:21 PM PDT 24
Peak memory 250436 kb
Host smart-b98c6592-0894-4b99-ab26-a1d61d170c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574863498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.574863498
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.3172158032
Short name T30
Test name
Test status
Simulation time 4840897246 ps
CPU time 40.48 seconds
Started Jun 21 06:29:25 PM PDT 24
Finished Jun 21 06:30:07 PM PDT 24
Peak memory 252008 kb
Host smart-112eb2b7-762c-486e-a58d-bc6b101d620d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172158032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.3172158032
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.1175177869
Short name T141
Test name
Test status
Simulation time 294516422727 ps
CPU time 313.5 seconds
Started Jun 21 06:29:13 PM PDT 24
Finished Jun 21 06:34:28 PM PDT 24
Peak memory 283916 kb
Host smart-6937e78a-55b2-4bf9-bc52-7453d73dc1ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1175177869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.1175177869
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.116184640
Short name T333
Test name
Test status
Simulation time 80629651 ps
CPU time 1.3 seconds
Started Jun 21 06:29:33 PM PDT 24
Finished Jun 21 06:29:35 PM PDT 24
Peak memory 209020 kb
Host smart-64bc4383-1bac-4878-b9a0-04d1540a353d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116184640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.116184640
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.200664458
Short name T678
Test name
Test status
Simulation time 1541467717 ps
CPU time 14.95 seconds
Started Jun 21 06:29:21 PM PDT 24
Finished Jun 21 06:29:38 PM PDT 24
Peak memory 218292 kb
Host smart-419115fe-d3d0-4359-8a37-6524749ff64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200664458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.200664458
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1375148322
Short name T496
Test name
Test status
Simulation time 218582822 ps
CPU time 6.01 seconds
Started Jun 21 06:29:19 PM PDT 24
Finished Jun 21 06:29:25 PM PDT 24
Peak memory 217164 kb
Host smart-5903a006-bda8-47a6-87fd-5deb96d32d91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375148322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1375148322
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.3149496737
Short name T102
Test name
Test status
Simulation time 1137462678 ps
CPU time 19.97 seconds
Started Jun 21 06:29:14 PM PDT 24
Finished Jun 21 06:29:35 PM PDT 24
Peak memory 218328 kb
Host smart-a0b684ea-f45f-4326-8f65-ffc1a1d9352c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149496737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.3149496737
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.413486961
Short name T238
Test name
Test status
Simulation time 99852078 ps
CPU time 2.34 seconds
Started Jun 21 06:29:34 PM PDT 24
Finished Jun 21 06:29:38 PM PDT 24
Peak memory 221824 kb
Host smart-aa82ffd6-1af4-479f-a0f8-f5d2a4a7a339
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413486961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_prog_failure.413486961
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3675017496
Short name T355
Test name
Test status
Simulation time 1388797765 ps
CPU time 5.49 seconds
Started Jun 21 06:29:21 PM PDT 24
Finished Jun 21 06:29:28 PM PDT 24
Peak memory 217744 kb
Host smart-2a853fe5-7455-44b6-8456-060c5f2d0ddc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675017496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.3675017496
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.1492781023
Short name T402
Test name
Test status
Simulation time 5681463001 ps
CPU time 65.36 seconds
Started Jun 21 06:29:24 PM PDT 24
Finished Jun 21 06:30:36 PM PDT 24
Peak memory 267432 kb
Host smart-fc024b3d-64ab-4e55-a5ed-18abb65309b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492781023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.1492781023
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3280304264
Short name T598
Test name
Test status
Simulation time 477437262 ps
CPU time 19.21 seconds
Started Jun 21 06:29:13 PM PDT 24
Finished Jun 21 06:29:38 PM PDT 24
Peak memory 250956 kb
Host smart-cab93bc4-4998-4b01-b4ff-f870f6ded098
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280304264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3280304264
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.1903276003
Short name T625
Test name
Test status
Simulation time 176007863 ps
CPU time 2.37 seconds
Started Jun 21 06:29:07 PM PDT 24
Finished Jun 21 06:29:12 PM PDT 24
Peak memory 218332 kb
Host smart-64ace3f6-827c-4bb4-bc21-e5dc50e14fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903276003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1903276003
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2650798550
Short name T294
Test name
Test status
Simulation time 256907497 ps
CPU time 10.85 seconds
Started Jun 21 06:29:07 PM PDT 24
Finished Jun 21 06:29:20 PM PDT 24
Peak memory 218464 kb
Host smart-63ddd166-d464-4956-9531-5c736edc942e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650798550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2650798550
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2527585180
Short name T443
Test name
Test status
Simulation time 995166797 ps
CPU time 10.25 seconds
Started Jun 21 06:29:20 PM PDT 24
Finished Jun 21 06:29:30 PM PDT 24
Peak memory 226220 kb
Host smart-40a006ef-5cdc-4613-a44f-1713defcb022
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527585180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2527585180
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3650400315
Short name T622
Test name
Test status
Simulation time 258282740 ps
CPU time 6.94 seconds
Started Jun 21 06:29:17 PM PDT 24
Finished Jun 21 06:29:25 PM PDT 24
Peak memory 224644 kb
Host smart-7bf48137-60de-4676-af02-7c171b239c4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650400315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3650400315
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2910131540
Short name T404
Test name
Test status
Simulation time 1749327416 ps
CPU time 10.46 seconds
Started Jun 21 06:29:09 PM PDT 24
Finished Jun 21 06:29:22 PM PDT 24
Peak memory 225536 kb
Host smart-742fe10b-4904-4b8f-84f5-b7f154bf45d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910131540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2910131540
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.1754488164
Short name T79
Test name
Test status
Simulation time 99838149 ps
CPU time 1.72 seconds
Started Jun 21 06:29:16 PM PDT 24
Finished Jun 21 06:29:19 PM PDT 24
Peak memory 214040 kb
Host smart-4cab6e84-fb8a-4421-8df9-8be70f93e6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754488164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.1754488164
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.2840720561
Short name T384
Test name
Test status
Simulation time 1183874265 ps
CPU time 25.97 seconds
Started Jun 21 06:29:25 PM PDT 24
Finished Jun 21 06:29:52 PM PDT 24
Peak memory 251060 kb
Host smart-afb42b16-5e6f-48f2-a482-bb19c368f18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840720561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.2840720561
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.643841698
Short name T249
Test name
Test status
Simulation time 182832635 ps
CPU time 6.62 seconds
Started Jun 21 06:29:13 PM PDT 24
Finished Jun 21 06:29:22 PM PDT 24
Peak memory 251028 kb
Host smart-19051360-5dbc-47ef-a3fd-0a6c7bb07b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643841698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.643841698
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.486214228
Short name T64
Test name
Test status
Simulation time 3095676928 ps
CPU time 139.99 seconds
Started Jun 21 06:29:23 PM PDT 24
Finished Jun 21 06:31:44 PM PDT 24
Peak memory 250492 kb
Host smart-7146ef76-1a4e-4529-8dcf-5166f539df1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486214228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.486214228
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2123764499
Short name T819
Test name
Test status
Simulation time 56238008 ps
CPU time 0.89 seconds
Started Jun 21 06:29:25 PM PDT 24
Finished Jun 21 06:29:28 PM PDT 24
Peak memory 211836 kb
Host smart-d6c5bed9-8f8f-46da-9bb7-3aa4e1d1cfce
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123764499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2123764499
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.2984509733
Short name T690
Test name
Test status
Simulation time 25889364 ps
CPU time 1 seconds
Started Jun 21 06:29:11 PM PDT 24
Finished Jun 21 06:29:15 PM PDT 24
Peak memory 208956 kb
Host smart-6de0f5ba-3785-4b9c-8acf-c8e07af9b6ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984509733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.2984509733
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.54235855
Short name T16
Test name
Test status
Simulation time 230983697 ps
CPU time 7.37 seconds
Started Jun 21 06:29:11 PM PDT 24
Finished Jun 21 06:29:21 PM PDT 24
Peak memory 218228 kb
Host smart-d35f18d4-a8c3-4ba8-96b2-542f3e09a1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54235855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.54235855
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.1046562256
Short name T34
Test name
Test status
Simulation time 317264933 ps
CPU time 4.72 seconds
Started Jun 21 06:29:12 PM PDT 24
Finished Jun 21 06:29:19 PM PDT 24
Peak memory 217352 kb
Host smart-531ddf15-d797-4b17-9fcc-423a97fbc902
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046562256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.1046562256
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.495731435
Short name T527
Test name
Test status
Simulation time 4456804290 ps
CPU time 64.83 seconds
Started Jun 21 06:29:21 PM PDT 24
Finished Jun 21 06:30:27 PM PDT 24
Peak memory 220148 kb
Host smart-c29e3712-b5cb-4a5c-a3e6-83757ad58b91
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495731435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_er
rors.495731435
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2723587899
Short name T564
Test name
Test status
Simulation time 546643856 ps
CPU time 4.86 seconds
Started Jun 21 06:29:09 PM PDT 24
Finished Jun 21 06:29:17 PM PDT 24
Peak memory 221936 kb
Host smart-304e576f-8608-4b31-b354-0f89b680dc41
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723587899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.2723587899
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2599113813
Short name T826
Test name
Test status
Simulation time 224093630 ps
CPU time 7.15 seconds
Started Jun 21 06:29:08 PM PDT 24
Finished Jun 21 06:29:18 PM PDT 24
Peak memory 217732 kb
Host smart-1b42869e-ebab-4f20-b766-2431a573af26
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599113813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2599113813
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3825862192
Short name T628
Test name
Test status
Simulation time 897607394 ps
CPU time 31.35 seconds
Started Jun 21 06:29:28 PM PDT 24
Finished Jun 21 06:30:01 PM PDT 24
Peak memory 250980 kb
Host smart-ef15bcae-a3e5-4bc9-b7a6-0db6981fc7d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825862192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3825862192
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.645522630
Short name T252
Test name
Test status
Simulation time 364782050 ps
CPU time 7.45 seconds
Started Jun 21 06:29:13 PM PDT 24
Finished Jun 21 06:29:22 PM PDT 24
Peak memory 223188 kb
Host smart-db2769e3-e6a0-4ff4-becc-a7f793fe65bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645522630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_
jtag_state_post_trans.645522630
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.2462681879
Short name T663
Test name
Test status
Simulation time 68158699 ps
CPU time 2.41 seconds
Started Jun 21 06:29:14 PM PDT 24
Finished Jun 21 06:29:18 PM PDT 24
Peak memory 222740 kb
Host smart-e7ecb9d8-aea8-451c-b403-d41630a81d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462681879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2462681879
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2567608206
Short name T338
Test name
Test status
Simulation time 853756202 ps
CPU time 9.55 seconds
Started Jun 21 06:29:12 PM PDT 24
Finished Jun 21 06:29:24 PM PDT 24
Peak memory 219052 kb
Host smart-2e06fb59-f595-4cc2-9a8c-20737cd13a8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567608206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2567608206
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.24573468
Short name T168
Test name
Test status
Simulation time 1209194409 ps
CPU time 11.6 seconds
Started Jun 21 06:29:28 PM PDT 24
Finished Jun 21 06:29:41 PM PDT 24
Peak memory 218384 kb
Host smart-8b95651b-6731-44b6-b670-d59dae9d69a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24573468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_dig
est.24573468
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1861031908
Short name T682
Test name
Test status
Simulation time 370729467 ps
CPU time 13.23 seconds
Started Jun 21 06:29:09 PM PDT 24
Finished Jun 21 06:29:25 PM PDT 24
Peak memory 226168 kb
Host smart-6661c9b4-e9a5-4aa8-8cc3-19991c47ba0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861031908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1861031908
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.453322432
Short name T790
Test name
Test status
Simulation time 1736711010 ps
CPU time 11.87 seconds
Started Jun 21 06:29:11 PM PDT 24
Finished Jun 21 06:29:26 PM PDT 24
Peak memory 226280 kb
Host smart-40f859a0-c2ce-4857-8559-1681f76fb175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453322432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.453322432
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.273309867
Short name T472
Test name
Test status
Simulation time 249886051 ps
CPU time 2.31 seconds
Started Jun 21 06:29:21 PM PDT 24
Finished Jun 21 06:29:25 PM PDT 24
Peak memory 217824 kb
Host smart-2dec0747-3151-4a86-9f81-28555e2acf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273309867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.273309867
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.4209903
Short name T231
Test name
Test status
Simulation time 574515880 ps
CPU time 29.81 seconds
Started Jun 21 06:29:24 PM PDT 24
Finished Jun 21 06:29:55 PM PDT 24
Peak memory 251040 kb
Host smart-d992b72e-cbc1-4f12-963c-10a2327dd837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.4209903
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.653441928
Short name T716
Test name
Test status
Simulation time 89207893 ps
CPU time 8.9 seconds
Started Jun 21 06:29:09 PM PDT 24
Finished Jun 21 06:29:20 PM PDT 24
Peak memory 250996 kb
Host smart-d4f129fc-9b3e-4fa8-b145-58f71e25a738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653441928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.653441928
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2499704210
Short name T740
Test name
Test status
Simulation time 10935000309 ps
CPU time 83.46 seconds
Started Jun 21 06:29:11 PM PDT 24
Finished Jun 21 06:30:37 PM PDT 24
Peak memory 274416 kb
Host smart-83c38d93-cf0e-4d6a-ad86-c9fc0daae1ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499704210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2499704210
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.183607508
Short name T401
Test name
Test status
Simulation time 13457072 ps
CPU time 1.1 seconds
Started Jun 21 06:29:18 PM PDT 24
Finished Jun 21 06:29:20 PM PDT 24
Peak memory 211928 kb
Host smart-d1242bdd-6f13-4747-b87c-5f26e8b9bee5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183607508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ct
rl_volatile_unlock_smoke.183607508
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.101269623
Short name T230
Test name
Test status
Simulation time 29987025 ps
CPU time 0.86 seconds
Started Jun 21 06:29:16 PM PDT 24
Finished Jun 21 06:29:18 PM PDT 24
Peak memory 208952 kb
Host smart-705abf69-353a-4381-b8da-cdbdb4f7cd42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101269623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.101269623
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1815271143
Short name T577
Test name
Test status
Simulation time 1267227948 ps
CPU time 7.9 seconds
Started Jun 21 06:29:23 PM PDT 24
Finished Jun 21 06:29:33 PM PDT 24
Peak memory 218428 kb
Host smart-962d3929-cbba-4e12-8116-dd25b81ed1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815271143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1815271143
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.669470265
Short name T702
Test name
Test status
Simulation time 340067615 ps
CPU time 9.72 seconds
Started Jun 21 06:29:21 PM PDT 24
Finished Jun 21 06:29:32 PM PDT 24
Peak memory 217620 kb
Host smart-bee68eb7-af35-4307-b246-9abe8f046b4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669470265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.669470265
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.3823375032
Short name T593
Test name
Test status
Simulation time 8362388928 ps
CPU time 60.27 seconds
Started Jun 21 06:29:20 PM PDT 24
Finished Jun 21 06:30:22 PM PDT 24
Peak memory 226232 kb
Host smart-6bed110b-1bde-4583-a225-69d28574302a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823375032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.3823375032
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2454326010
Short name T514
Test name
Test status
Simulation time 1377268722 ps
CPU time 10.37 seconds
Started Jun 21 06:29:25 PM PDT 24
Finished Jun 21 06:29:36 PM PDT 24
Peak memory 223060 kb
Host smart-6cc180ba-66c9-4ba5-8f64-4fbff5293d9a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454326010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2454326010
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2457199953
Short name T311
Test name
Test status
Simulation time 302425627 ps
CPU time 8.67 seconds
Started Jun 21 06:29:15 PM PDT 24
Finished Jun 21 06:29:25 PM PDT 24
Peak memory 217748 kb
Host smart-7d92202e-e320-4918-992d-8d34111a5c17
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457199953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2457199953
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2646704412
Short name T281
Test name
Test status
Simulation time 1173677242 ps
CPU time 40.61 seconds
Started Jun 21 06:29:34 PM PDT 24
Finished Jun 21 06:30:15 PM PDT 24
Peak memory 267356 kb
Host smart-b12f61e0-47a8-43ee-8ab9-bbb74c2795da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646704412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2646704412
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.2841819821
Short name T256
Test name
Test status
Simulation time 428970457 ps
CPU time 12.71 seconds
Started Jun 21 06:29:31 PM PDT 24
Finished Jun 21 06:29:44 PM PDT 24
Peak memory 250964 kb
Host smart-e3a0f6f4-e14d-40cf-8208-46a4be774350
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841819821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.2841819821
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.265287821
Short name T532
Test name
Test status
Simulation time 25636630 ps
CPU time 1.85 seconds
Started Jun 21 06:29:24 PM PDT 24
Finished Jun 21 06:29:27 PM PDT 24
Peak memory 222112 kb
Host smart-007793f0-cf75-4125-81b5-c69d16544aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265287821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.265287821
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.831144143
Short name T45
Test name
Test status
Simulation time 708130590 ps
CPU time 14.37 seconds
Started Jun 21 06:29:25 PM PDT 24
Finished Jun 21 06:29:41 PM PDT 24
Peak memory 219060 kb
Host smart-2dea1cad-8532-40bb-b14f-9003d2e6c43b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831144143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.831144143
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3740813821
Short name T279
Test name
Test status
Simulation time 484573982 ps
CPU time 16.99 seconds
Started Jun 21 06:29:18 PM PDT 24
Finished Jun 21 06:29:36 PM PDT 24
Peak memory 218392 kb
Host smart-53154b17-d508-4682-bda6-099db4f3acca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740813821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.3740813821
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.526279366
Short name T382
Test name
Test status
Simulation time 2905574514 ps
CPU time 21.87 seconds
Started Jun 21 06:29:08 PM PDT 24
Finished Jun 21 06:29:32 PM PDT 24
Peak memory 226256 kb
Host smart-8e2653f8-0846-4563-864d-d18fb0cea3db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526279366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.526279366
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2801607032
Short name T465
Test name
Test status
Simulation time 561479998 ps
CPU time 1.73 seconds
Started Jun 21 06:29:08 PM PDT 24
Finished Jun 21 06:29:12 PM PDT 24
Peak memory 217836 kb
Host smart-482fa014-1a35-4f2b-9015-c26f14886e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801607032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2801607032
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.734266025
Short name T193
Test name
Test status
Simulation time 323911678 ps
CPU time 25.94 seconds
Started Jun 21 06:29:26 PM PDT 24
Finished Jun 21 06:29:53 PM PDT 24
Peak memory 251028 kb
Host smart-8580ba9d-ef89-4876-8f7e-92a150dff739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734266025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.734266025
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.903546737
Short name T720
Test name
Test status
Simulation time 67139490 ps
CPU time 3.73 seconds
Started Jun 21 06:29:12 PM PDT 24
Finished Jun 21 06:29:18 PM PDT 24
Peak memory 226448 kb
Host smart-b4434fec-f04b-48ea-98fa-f39c1b07a498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903546737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.903546737
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3535340994
Short name T787
Test name
Test status
Simulation time 12836202628 ps
CPU time 99.57 seconds
Started Jun 21 06:29:26 PM PDT 24
Finished Jun 21 06:31:07 PM PDT 24
Peak memory 251096 kb
Host smart-a1a03e91-c938-4528-9479-dca6335c2761
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535340994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3535340994
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.1359402436
Short name T772
Test name
Test status
Simulation time 23100025981 ps
CPU time 239.91 seconds
Started Jun 21 06:29:32 PM PDT 24
Finished Jun 21 06:33:33 PM PDT 24
Peak memory 283948 kb
Host smart-9c079b42-8172-4662-8ddc-e05dea3beaf9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1359402436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.1359402436
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1342498096
Short name T474
Test name
Test status
Simulation time 18075205 ps
CPU time 0.93 seconds
Started Jun 21 06:29:27 PM PDT 24
Finished Jun 21 06:29:29 PM PDT 24
Peak memory 211972 kb
Host smart-dd8b89c4-76fe-4fcc-98aa-f06c1f56ab43
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342498096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.1342498096
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.1301270076
Short name T658
Test name
Test status
Simulation time 54102359 ps
CPU time 0.9 seconds
Started Jun 21 06:29:28 PM PDT 24
Finished Jun 21 06:29:30 PM PDT 24
Peak memory 208892 kb
Host smart-bdba1f71-0505-4916-be30-62b12e1a701b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301270076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.1301270076
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.1121037388
Short name T785
Test name
Test status
Simulation time 974635709 ps
CPU time 12.59 seconds
Started Jun 21 06:29:23 PM PDT 24
Finished Jun 21 06:29:37 PM PDT 24
Peak memory 218428 kb
Host smart-b96fc654-981e-40df-8fec-bb309a828caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121037388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1121037388
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.1438466145
Short name T350
Test name
Test status
Simulation time 175299649 ps
CPU time 2.89 seconds
Started Jun 21 06:29:31 PM PDT 24
Finished Jun 21 06:29:35 PM PDT 24
Peak memory 217300 kb
Host smart-5bb8d110-8c45-464e-8847-52aca81abbdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438466145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.1438466145
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1927948999
Short name T457
Test name
Test status
Simulation time 7913204401 ps
CPU time 59.59 seconds
Started Jun 21 06:29:14 PM PDT 24
Finished Jun 21 06:30:15 PM PDT 24
Peak memory 219168 kb
Host smart-25e320c7-bf30-499e-85cf-d0e3f12fd68b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927948999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1927948999
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2465901681
Short name T806
Test name
Test status
Simulation time 153650158 ps
CPU time 3.4 seconds
Started Jun 21 06:29:21 PM PDT 24
Finished Jun 21 06:29:26 PM PDT 24
Peak memory 223188 kb
Host smart-4ac53dbe-e7f3-4f92-8651-2797feadbed5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465901681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2465901681
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.2087487003
Short name T363
Test name
Test status
Simulation time 211448170 ps
CPU time 6.79 seconds
Started Jun 21 06:29:20 PM PDT 24
Finished Jun 21 06:29:29 PM PDT 24
Peak memory 217752 kb
Host smart-cd1ec7c3-8258-438d-b1c9-2e287aa1a318
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087487003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.2087487003
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.1340049275
Short name T522
Test name
Test status
Simulation time 6704185941 ps
CPU time 45.8 seconds
Started Jun 21 06:29:11 PM PDT 24
Finished Jun 21 06:29:59 PM PDT 24
Peak memory 276588 kb
Host smart-8ed7f8c6-083a-4a00-9487-81f1889441bb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340049275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.1340049275
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.242746215
Short name T750
Test name
Test status
Simulation time 1386049161 ps
CPU time 10.64 seconds
Started Jun 21 06:29:33 PM PDT 24
Finished Jun 21 06:29:44 PM PDT 24
Peak memory 250972 kb
Host smart-ea277b57-bca1-4e00-854c-8565a09e05ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242746215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.242746215
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.4261992041
Short name T619
Test name
Test status
Simulation time 38030297 ps
CPU time 1.6 seconds
Started Jun 21 06:29:09 PM PDT 24
Finished Jun 21 06:29:14 PM PDT 24
Peak memory 218356 kb
Host smart-bf8be380-5702-4c48-94b4-b578a5e27517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261992041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.4261992041
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.3896824255
Short name T317
Test name
Test status
Simulation time 304577343 ps
CPU time 9.33 seconds
Started Jun 21 06:29:22 PM PDT 24
Finished Jun 21 06:29:33 PM PDT 24
Peak memory 219060 kb
Host smart-d8d24ce4-bb3a-4a0c-881a-937f358e1276
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896824255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.3896824255
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1133124761
Short name T277
Test name
Test status
Simulation time 8238870774 ps
CPU time 10.74 seconds
Started Jun 21 06:29:38 PM PDT 24
Finished Jun 21 06:29:50 PM PDT 24
Peak memory 218452 kb
Host smart-6cbaff62-9c51-4c14-8d1b-a454a35b8caa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133124761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.1133124761
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.2022540524
Short name T507
Test name
Test status
Simulation time 989536858 ps
CPU time 7.98 seconds
Started Jun 21 06:29:26 PM PDT 24
Finished Jun 21 06:29:35 PM PDT 24
Peak memory 226192 kb
Host smart-a3a2e692-3ebf-43c7-b5e5-fc10ea5fca42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022540524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
2022540524
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.113360033
Short name T278
Test name
Test status
Simulation time 723068654 ps
CPU time 7.06 seconds
Started Jun 21 06:29:14 PM PDT 24
Finished Jun 21 06:29:22 PM PDT 24
Peak memory 225128 kb
Host smart-686dcb81-732a-4dc7-a4cd-93b1dbaf53b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113360033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.113360033
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.4176068014
Short name T427
Test name
Test status
Simulation time 299521367 ps
CPU time 7.22 seconds
Started Jun 21 06:29:21 PM PDT 24
Finished Jun 21 06:29:30 PM PDT 24
Peak memory 217828 kb
Host smart-efcf026e-4189-44d7-9fd1-55b15d3c37c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176068014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.4176068014
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.4022472739
Short name T359
Test name
Test status
Simulation time 676698494 ps
CPU time 23.31 seconds
Started Jun 21 06:29:24 PM PDT 24
Finished Jun 21 06:29:49 PM PDT 24
Peak memory 251024 kb
Host smart-11f05747-3154-49cb-b685-66acb7a8bcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022472739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.4022472739
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.3740176043
Short name T188
Test name
Test status
Simulation time 76171385 ps
CPU time 7.8 seconds
Started Jun 21 06:29:23 PM PDT 24
Finished Jun 21 06:29:32 PM PDT 24
Peak memory 251072 kb
Host smart-2bb29b7e-619a-4e6c-9513-48391e585836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740176043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3740176043
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.4174178361
Short name T356
Test name
Test status
Simulation time 5706206696 ps
CPU time 179.6 seconds
Started Jun 21 06:29:30 PM PDT 24
Finished Jun 21 06:32:31 PM PDT 24
Peak memory 267556 kb
Host smart-e1b457b7-d205-457e-a969-681ef5ab6ca7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174178361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.4174178361
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.901155223
Short name T409
Test name
Test status
Simulation time 47743668 ps
CPU time 0.81 seconds
Started Jun 21 06:29:13 PM PDT 24
Finished Jun 21 06:29:16 PM PDT 24
Peak memory 212016 kb
Host smart-ec6012cf-c6c0-4560-b19e-16a60b98588c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901155223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ct
rl_volatile_unlock_smoke.901155223
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.231704526
Short name T823
Test name
Test status
Simulation time 55562573 ps
CPU time 1.07 seconds
Started Jun 21 06:29:36 PM PDT 24
Finished Jun 21 06:29:39 PM PDT 24
Peak memory 208880 kb
Host smart-916a9d1d-b756-4b6f-84d3-b166e3d1d49c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231704526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.231704526
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.1194438002
Short name T491
Test name
Test status
Simulation time 1511277986 ps
CPU time 11.51 seconds
Started Jun 21 06:29:32 PM PDT 24
Finished Jun 21 06:29:44 PM PDT 24
Peak memory 218352 kb
Host smart-fb81abf6-706f-4bba-a7d7-0872e23f0206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194438002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.1194438002
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1495353414
Short name T341
Test name
Test status
Simulation time 2402425915 ps
CPU time 14.43 seconds
Started Jun 21 06:29:22 PM PDT 24
Finished Jun 21 06:29:38 PM PDT 24
Peak memory 217616 kb
Host smart-4a94d964-2612-493b-bc30-4a88b4f69d73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495353414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1495353414
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1870211794
Short name T797
Test name
Test status
Simulation time 7280925957 ps
CPU time 30.4 seconds
Started Jun 21 06:29:23 PM PDT 24
Finished Jun 21 06:29:55 PM PDT 24
Peak memory 219160 kb
Host smart-04376a5c-7e25-4e34-9556-069984aeb3a2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870211794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1870211794
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.1525414386
Short name T646
Test name
Test status
Simulation time 359064694 ps
CPU time 11.8 seconds
Started Jun 21 06:29:29 PM PDT 24
Finished Jun 21 06:29:42 PM PDT 24
Peak memory 223400 kb
Host smart-f3b42b93-60ec-4c15-9bf4-7a103018a711
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525414386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.1525414386
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1328260541
Short name T807
Test name
Test status
Simulation time 2268818656 ps
CPU time 4.83 seconds
Started Jun 21 06:29:32 PM PDT 24
Finished Jun 21 06:29:38 PM PDT 24
Peak memory 217768 kb
Host smart-e7ae15d6-fca7-44a3-8dc9-d4704a4650df
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328260541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1328260541
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2697224601
Short name T426
Test name
Test status
Simulation time 2620539133 ps
CPU time 84.14 seconds
Started Jun 21 06:29:35 PM PDT 24
Finished Jun 21 06:31:01 PM PDT 24
Peak memory 283456 kb
Host smart-fec19ddb-72d9-49f8-b1ec-bedbdb147179
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697224601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.2697224601
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1845337760
Short name T605
Test name
Test status
Simulation time 1675078559 ps
CPU time 17.41 seconds
Started Jun 21 06:29:28 PM PDT 24
Finished Jun 21 06:29:47 PM PDT 24
Peak memory 247668 kb
Host smart-c5c78224-7e99-4542-a288-62924abcf0ca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845337760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.1845337760
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.3424568397
Short name T342
Test name
Test status
Simulation time 39677523 ps
CPU time 1.86 seconds
Started Jun 21 06:29:22 PM PDT 24
Finished Jun 21 06:29:26 PM PDT 24
Peak memory 218284 kb
Host smart-f35f2f0e-8a00-4498-9beb-8a62acdf6d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424568397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.3424568397
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.1220860462
Short name T643
Test name
Test status
Simulation time 2734716180 ps
CPU time 17.19 seconds
Started Jun 21 06:29:33 PM PDT 24
Finished Jun 21 06:29:51 PM PDT 24
Peak memory 219132 kb
Host smart-5d4215df-cab9-4dfe-bb98-9c8d9f78b36f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220860462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1220860462
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2640370050
Short name T608
Test name
Test status
Simulation time 846528907 ps
CPU time 15.74 seconds
Started Jun 21 06:29:23 PM PDT 24
Finished Jun 21 06:29:45 PM PDT 24
Peak memory 226216 kb
Host smart-0f40b345-4278-43ab-87c7-a9e479e860f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640370050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2640370050
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.2245340997
Short name T520
Test name
Test status
Simulation time 1221322965 ps
CPU time 9.04 seconds
Started Jun 21 06:29:29 PM PDT 24
Finished Jun 21 06:29:39 PM PDT 24
Peak memory 226192 kb
Host smart-dca598b0-4cea-45a8-b3f8-bbc3e12053a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245340997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
2245340997
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3488220572
Short name T319
Test name
Test status
Simulation time 192484043 ps
CPU time 6.16 seconds
Started Jun 21 06:29:20 PM PDT 24
Finished Jun 21 06:29:37 PM PDT 24
Peak memory 226340 kb
Host smart-cdb31852-16be-4549-bb8d-54e0ccf63d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488220572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3488220572
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.2726234550
Short name T680
Test name
Test status
Simulation time 404776862 ps
CPU time 2.04 seconds
Started Jun 21 06:29:24 PM PDT 24
Finished Jun 21 06:29:28 PM PDT 24
Peak memory 217916 kb
Host smart-07dc6cf0-915c-4955-b608-4e9d8299f690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726234550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.2726234550
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.3192038275
Short name T147
Test name
Test status
Simulation time 783009314 ps
CPU time 23.85 seconds
Started Jun 21 06:29:23 PM PDT 24
Finished Jun 21 06:29:48 PM PDT 24
Peak memory 251044 kb
Host smart-2dddb624-8faf-4dcf-bc43-5cb2970fb787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192038275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3192038275
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1432045477
Short name T791
Test name
Test status
Simulation time 180082216 ps
CPU time 6.56 seconds
Started Jun 21 06:29:24 PM PDT 24
Finished Jun 21 06:29:32 PM PDT 24
Peak memory 250580 kb
Host smart-2db6f9c2-f39a-4475-9083-8bc6ba1273da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432045477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1432045477
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.67993231
Short name T235
Test name
Test status
Simulation time 19957697808 ps
CPU time 186.76 seconds
Started Jun 21 06:29:34 PM PDT 24
Finished Jun 21 06:32:41 PM PDT 24
Peak memory 321468 kb
Host smart-03873d3e-6a6b-4d1b-9bf9-2bcf5f238be9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67993231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.lc_ctrl_stress_all.67993231
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1793712401
Short name T428
Test name
Test status
Simulation time 216198058 ps
CPU time 0.92 seconds
Started Jun 21 06:29:23 PM PDT 24
Finished Jun 21 06:29:25 PM PDT 24
Peak memory 211916 kb
Host smart-c62a2ca9-5e57-481a-a014-cc0cf1a60edb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793712401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.1793712401
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.256218093
Short name T705
Test name
Test status
Simulation time 18986170 ps
CPU time 1.17 seconds
Started Jun 21 06:29:36 PM PDT 24
Finished Jun 21 06:29:40 PM PDT 24
Peak memory 208948 kb
Host smart-d09d7ab4-7880-47eb-8c90-d11bac63df5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256218093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.256218093
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.949673073
Short name T553
Test name
Test status
Simulation time 230012090 ps
CPU time 2.3 seconds
Started Jun 21 06:29:35 PM PDT 24
Finished Jun 21 06:29:38 PM PDT 24
Peak memory 217244 kb
Host smart-99fc2572-e4a9-45b6-83ec-2827b92c0fe0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949673073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.949673073
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3552940924
Short name T417
Test name
Test status
Simulation time 14388229681 ps
CPU time 27.77 seconds
Started Jun 21 06:29:28 PM PDT 24
Finished Jun 21 06:29:57 PM PDT 24
Peak memory 218972 kb
Host smart-cb81ca83-5929-4b8a-8768-db93c1e045ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552940924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3552940924
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.3232168789
Short name T463
Test name
Test status
Simulation time 815665798 ps
CPU time 13.18 seconds
Started Jun 21 06:29:35 PM PDT 24
Finished Jun 21 06:29:50 PM PDT 24
Peak memory 224364 kb
Host smart-01130234-a6ea-4d08-a7dd-ad6e4493d3ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232168789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.3232168789
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3187940962
Short name T649
Test name
Test status
Simulation time 247465273 ps
CPU time 4.41 seconds
Started Jun 21 06:29:17 PM PDT 24
Finished Jun 21 06:29:22 PM PDT 24
Peak memory 217720 kb
Host smart-b3400246-3ced-4915-9a9f-1f50897f1eaf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187940962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3187940962
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2963714867
Short name T455
Test name
Test status
Simulation time 1016766584 ps
CPU time 45.96 seconds
Started Jun 21 06:29:15 PM PDT 24
Finished Jun 21 06:30:02 PM PDT 24
Peak memory 248552 kb
Host smart-512f99ce-2dcb-4a23-a2a5-640c1021ae20
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963714867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2963714867
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.50377949
Short name T253
Test name
Test status
Simulation time 1244031762 ps
CPU time 36.95 seconds
Started Jun 21 06:29:33 PM PDT 24
Finished Jun 21 06:30:10 PM PDT 24
Peak memory 247748 kb
Host smart-6d6e6c09-e576-4e32-9acc-c223a7ae0a7c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50377949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_j
tag_state_post_trans.50377949
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2101216904
Short name T574
Test name
Test status
Simulation time 162529395 ps
CPU time 2.66 seconds
Started Jun 21 06:29:24 PM PDT 24
Finished Jun 21 06:29:29 PM PDT 24
Peak memory 222384 kb
Host smart-40810ca4-365c-4775-ba26-751517086a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101216904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2101216904
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1873621290
Short name T447
Test name
Test status
Simulation time 887151454 ps
CPU time 10.42 seconds
Started Jun 21 06:29:45 PM PDT 24
Finished Jun 21 06:29:57 PM PDT 24
Peak memory 218340 kb
Host smart-ee235708-ea4e-4559-ba4e-74de693f71f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873621290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1873621290
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1532433917
Short name T461
Test name
Test status
Simulation time 421781464 ps
CPU time 10.95 seconds
Started Jun 21 06:29:37 PM PDT 24
Finished Jun 21 06:29:50 PM PDT 24
Peak memory 218380 kb
Host smart-5c574e73-14d4-4c50-9ea6-aab92fce175e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532433917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.1532433917
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2377680797
Short name T484
Test name
Test status
Simulation time 808156381 ps
CPU time 7.93 seconds
Started Jun 21 06:29:22 PM PDT 24
Finished Jun 21 06:29:31 PM PDT 24
Peak memory 225364 kb
Host smart-f762f593-d392-4410-be9b-c1af589dd817
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377680797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2377680797
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.1939292431
Short name T424
Test name
Test status
Simulation time 221104343 ps
CPU time 7.23 seconds
Started Jun 21 06:29:41 PM PDT 24
Finished Jun 21 06:29:49 PM PDT 24
Peak memory 225276 kb
Host smart-aaad11ed-94b0-4100-b842-85610c0baf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939292431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1939292431
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.506170973
Short name T71
Test name
Test status
Simulation time 75659398 ps
CPU time 3.46 seconds
Started Jun 21 06:29:35 PM PDT 24
Finished Jun 21 06:29:39 PM PDT 24
Peak memory 217720 kb
Host smart-65d8d488-5947-4ea8-a8fe-7f64df66774d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506170973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.506170973
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1315221969
Short name T551
Test name
Test status
Simulation time 250759482 ps
CPU time 21.98 seconds
Started Jun 21 06:29:34 PM PDT 24
Finished Jun 21 06:29:57 PM PDT 24
Peak memory 251044 kb
Host smart-005acc7e-937a-4961-ac11-0606b9f334c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315221969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1315221969
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2681426218
Short name T260
Test name
Test status
Simulation time 5419291381 ps
CPU time 90.96 seconds
Started Jun 21 06:29:44 PM PDT 24
Finished Jun 21 06:31:16 PM PDT 24
Peak memory 275620 kb
Host smart-f36a7988-a9c3-4be0-aff5-2c6de0eed711
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681426218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2681426218
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1735175910
Short name T352
Test name
Test status
Simulation time 12467539 ps
CPU time 0.91 seconds
Started Jun 21 06:29:26 PM PDT 24
Finished Jun 21 06:29:28 PM PDT 24
Peak memory 211896 kb
Host smart-b583aaff-47a9-42a3-965b-1a2dbe02e1c2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735175910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.1735175910
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.506581961
Short name T471
Test name
Test status
Simulation time 41899905 ps
CPU time 1.29 seconds
Started Jun 21 06:29:34 PM PDT 24
Finished Jun 21 06:29:36 PM PDT 24
Peak memory 208964 kb
Host smart-fd530535-f6fb-497b-a981-190f9accf293
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506581961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.506581961
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.2501602601
Short name T43
Test name
Test status
Simulation time 422392199 ps
CPU time 13.53 seconds
Started Jun 21 06:29:22 PM PDT 24
Finished Jun 21 06:29:37 PM PDT 24
Peak memory 218508 kb
Host smart-63f3b706-5662-4512-b506-8e9cbbc98149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501602601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.2501602601
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.1053789528
Short name T367
Test name
Test status
Simulation time 246727605 ps
CPU time 7.52 seconds
Started Jun 21 06:29:45 PM PDT 24
Finished Jun 21 06:29:54 PM PDT 24
Peak memory 217332 kb
Host smart-7f8a0d97-6239-40d5-88c3-42afe9c38487
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053789528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.1053789528
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3161490384
Short name T809
Test name
Test status
Simulation time 15680032952 ps
CPU time 41.88 seconds
Started Jun 21 06:29:21 PM PDT 24
Finished Jun 21 06:30:04 PM PDT 24
Peak memory 226208 kb
Host smart-a6f936b4-4529-45ad-b7a3-859097d4b5c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161490384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3161490384
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3632818574
Short name T587
Test name
Test status
Simulation time 347618536 ps
CPU time 6.22 seconds
Started Jun 21 06:29:42 PM PDT 24
Finished Jun 21 06:29:49 PM PDT 24
Peak memory 223264 kb
Host smart-ae8f6cc3-5698-4768-b75e-2d4a7fd241ea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632818574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.3632818574
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1331406155
Short name T698
Test name
Test status
Simulation time 77533876 ps
CPU time 2 seconds
Started Jun 21 06:29:39 PM PDT 24
Finished Jun 21 06:29:43 PM PDT 24
Peak memory 217760 kb
Host smart-9d87dc41-112b-424c-a8e7-a39d1c0262c1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331406155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1331406155
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2014218687
Short name T534
Test name
Test status
Simulation time 1625003620 ps
CPU time 68.91 seconds
Started Jun 21 06:29:37 PM PDT 24
Finished Jun 21 06:30:48 PM PDT 24
Peak memory 251016 kb
Host smart-98b435db-dbf4-4ce9-97f8-7d92df561fdd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014218687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2014218687
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.361922091
Short name T389
Test name
Test status
Simulation time 2316818916 ps
CPU time 14.11 seconds
Started Jun 21 06:29:41 PM PDT 24
Finished Jun 21 06:29:57 PM PDT 24
Peak memory 250932 kb
Host smart-63f27026-2f35-42c4-829d-127e7bb999c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361922091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
jtag_state_post_trans.361922091
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.31436005
Short name T41
Test name
Test status
Simulation time 14332034 ps
CPU time 1.68 seconds
Started Jun 21 06:29:41 PM PDT 24
Finished Jun 21 06:29:45 PM PDT 24
Peak memory 221756 kb
Host smart-e9229913-45a9-4985-89bf-cc824245502e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31436005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.31436005
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.166333777
Short name T562
Test name
Test status
Simulation time 333853276 ps
CPU time 14.2 seconds
Started Jun 21 06:29:26 PM PDT 24
Finished Jun 21 06:29:41 PM PDT 24
Peak memory 226228 kb
Host smart-4f12a8d2-34b8-40ea-9864-663fb9b7e537
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166333777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.166333777
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.188871449
Short name T739
Test name
Test status
Simulation time 1130859468 ps
CPU time 13.32 seconds
Started Jun 21 06:29:41 PM PDT 24
Finished Jun 21 06:29:55 PM PDT 24
Peak memory 218380 kb
Host smart-40f0707a-8392-480a-ad69-aab0ff99e5a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188871449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_di
gest.188871449
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3918020346
Short name T167
Test name
Test status
Simulation time 426119840 ps
CPU time 14.52 seconds
Started Jun 21 06:29:32 PM PDT 24
Finished Jun 21 06:29:48 PM PDT 24
Peak memory 218376 kb
Host smart-7c8d2c41-7d63-462a-ac05-279dbb290a34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918020346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
3918020346
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3305900668
Short name T505
Test name
Test status
Simulation time 366851728 ps
CPU time 10.4 seconds
Started Jun 21 06:29:32 PM PDT 24
Finished Jun 21 06:29:44 PM PDT 24
Peak memory 226092 kb
Host smart-222e10be-e861-44ba-a315-bbca84724116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305900668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3305900668
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.769217542
Short name T439
Test name
Test status
Simulation time 84899582 ps
CPU time 3.34 seconds
Started Jun 21 06:29:39 PM PDT 24
Finished Jun 21 06:29:44 PM PDT 24
Peak memory 214840 kb
Host smart-d349996d-9be4-41f4-b2a3-ab68b9b2766e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769217542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.769217542
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.881727095
Short name T620
Test name
Test status
Simulation time 276390938 ps
CPU time 25.02 seconds
Started Jun 21 06:29:38 PM PDT 24
Finished Jun 21 06:30:05 PM PDT 24
Peak memory 251024 kb
Host smart-66dec401-d20e-4240-94ee-6e69a0293201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881727095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.881727095
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.351917835
Short name T180
Test name
Test status
Simulation time 65980612 ps
CPU time 8.68 seconds
Started Jun 21 06:29:37 PM PDT 24
Finished Jun 21 06:29:48 PM PDT 24
Peak memory 251024 kb
Host smart-c2151ae5-160d-458e-8146-6027d4f85f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351917835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.351917835
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.235516729
Short name T668
Test name
Test status
Simulation time 6198174090 ps
CPU time 294.14 seconds
Started Jun 21 06:29:32 PM PDT 24
Finished Jun 21 06:34:28 PM PDT 24
Peak memory 496748 kb
Host smart-60fe3dc5-2c31-4e95-bf76-dbc8cf45cbf0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235516729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.235516729
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3111346274
Short name T539
Test name
Test status
Simulation time 19128866 ps
CPU time 0.84 seconds
Started Jun 21 06:29:33 PM PDT 24
Finished Jun 21 06:29:35 PM PDT 24
Peak memory 211908 kb
Host smart-b72b02ee-5bee-4a60-bcdf-e111c43e99c0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111346274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.3111346274
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3284825863
Short name T347
Test name
Test status
Simulation time 13596489 ps
CPU time 0.86 seconds
Started Jun 21 06:29:45 PM PDT 24
Finished Jun 21 06:29:48 PM PDT 24
Peak memory 208816 kb
Host smart-67f7f6a0-ed00-43e8-979e-6224941f7f9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284825863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3284825863
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.1697495088
Short name T376
Test name
Test status
Simulation time 445050103 ps
CPU time 5.17 seconds
Started Jun 21 06:29:44 PM PDT 24
Finished Jun 21 06:29:50 PM PDT 24
Peak memory 217316 kb
Host smart-54ad5212-d12a-4da6-a5a2-4469d5cbc29d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697495088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.1697495088
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.3831477356
Short name T760
Test name
Test status
Simulation time 3341692491 ps
CPU time 26.95 seconds
Started Jun 21 06:29:37 PM PDT 24
Finished Jun 21 06:30:06 PM PDT 24
Peak memory 219048 kb
Host smart-b8e2e0b9-4adf-4aee-bcd0-9ae057c20434
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831477356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.3831477356
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.967246396
Short name T736
Test name
Test status
Simulation time 462661138 ps
CPU time 12.98 seconds
Started Jun 21 06:29:41 PM PDT 24
Finished Jun 21 06:29:55 PM PDT 24
Peak memory 223220 kb
Host smart-c4df76b1-ca4c-43a6-83ae-24d7684a62ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967246396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_prog_failure.967246396
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2132510181
Short name T22
Test name
Test status
Simulation time 2209399587 ps
CPU time 7.76 seconds
Started Jun 21 06:29:36 PM PDT 24
Finished Jun 21 06:29:46 PM PDT 24
Peak memory 217808 kb
Host smart-e3f902c9-7d8b-4e2b-8cf5-35b236288da1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132510181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2132510181
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3066641305
Short name T261
Test name
Test status
Simulation time 5944099215 ps
CPU time 97.75 seconds
Started Jun 21 06:29:40 PM PDT 24
Finished Jun 21 06:31:19 PM PDT 24
Peak memory 283808 kb
Host smart-45098e3b-928c-4e2f-a798-fd29800188ee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066641305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.3066641305
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2137083421
Short name T176
Test name
Test status
Simulation time 2519527408 ps
CPU time 10.82 seconds
Started Jun 21 06:29:37 PM PDT 24
Finished Jun 21 06:29:50 PM PDT 24
Peak memory 251024 kb
Host smart-695d0a43-35bd-4e62-a783-25fcd361834b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137083421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2137083421
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.1814162732
Short name T243
Test name
Test status
Simulation time 194251590 ps
CPU time 2.15 seconds
Started Jun 21 06:29:40 PM PDT 24
Finished Jun 21 06:29:44 PM PDT 24
Peak memory 218352 kb
Host smart-a7814092-b86e-4b09-9bf5-690773dbf2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814162732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.1814162732
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.1166539749
Short name T59
Test name
Test status
Simulation time 312758475 ps
CPU time 10.56 seconds
Started Jun 21 06:29:40 PM PDT 24
Finished Jun 21 06:29:52 PM PDT 24
Peak memory 218424 kb
Host smart-d45c0a6d-1cba-4f3c-bd7a-bdb742284738
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166539749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1166539749
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.3270573523
Short name T418
Test name
Test status
Simulation time 1915961202 ps
CPU time 17.22 seconds
Started Jun 21 06:29:36 PM PDT 24
Finished Jun 21 06:29:55 PM PDT 24
Peak memory 226204 kb
Host smart-85e974af-3d7a-41fb-9f9c-78ea68e19b50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270573523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.3270573523
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1297113333
Short name T783
Test name
Test status
Simulation time 857572700 ps
CPU time 11.03 seconds
Started Jun 21 06:29:41 PM PDT 24
Finished Jun 21 06:29:53 PM PDT 24
Peak memory 218396 kb
Host smart-e1087923-cd26-41e1-9914-1fbfb211be3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297113333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1297113333
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2679527992
Short name T161
Test name
Test status
Simulation time 3522396264 ps
CPU time 8.27 seconds
Started Jun 21 06:29:30 PM PDT 24
Finished Jun 21 06:29:39 PM PDT 24
Peak memory 226216 kb
Host smart-ead1f47a-2d71-44d5-9eaa-0bec5d9d88d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679527992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2679527992
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.2908849702
Short name T284
Test name
Test status
Simulation time 102499064 ps
CPU time 2.3 seconds
Started Jun 21 06:29:37 PM PDT 24
Finished Jun 21 06:29:41 PM PDT 24
Peak memory 214456 kb
Host smart-abde9384-86c3-4cd0-91ce-308594ae84b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908849702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2908849702
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.183887681
Short name T852
Test name
Test status
Simulation time 1151198286 ps
CPU time 22.71 seconds
Started Jun 21 06:29:40 PM PDT 24
Finished Jun 21 06:30:04 PM PDT 24
Peak memory 251024 kb
Host smart-b9164b25-8073-4991-8de7-d3eb179c5db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183887681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.183887681
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.4242428164
Short name T236
Test name
Test status
Simulation time 975355661 ps
CPU time 8.26 seconds
Started Jun 21 06:29:37 PM PDT 24
Finished Jun 21 06:29:48 PM PDT 24
Peak memory 251028 kb
Host smart-0b6a9fe3-e7a3-4ac8-89a3-fde9d8da941a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242428164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.4242428164
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.3905350590
Short name T199
Test name
Test status
Simulation time 4082212080 ps
CPU time 94.42 seconds
Started Jun 21 06:29:44 PM PDT 24
Finished Jun 21 06:31:19 PM PDT 24
Peak memory 275760 kb
Host smart-1b8931f2-9076-4c29-84de-07aa0edd3181
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905350590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.3905350590
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.2661629119
Short name T172
Test name
Test status
Simulation time 12691751871 ps
CPU time 324.36 seconds
Started Jun 21 06:29:36 PM PDT 24
Finished Jun 21 06:35:03 PM PDT 24
Peak memory 300712 kb
Host smart-15b3a114-418d-4422-9543-63714863b148
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2661629119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.2661629119
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2579760438
Short name T743
Test name
Test status
Simulation time 17633363 ps
CPU time 1 seconds
Started Jun 21 06:29:24 PM PDT 24
Finished Jun 21 06:29:26 PM PDT 24
Peak memory 217744 kb
Host smart-d43c9e1b-a050-48d6-af61-f65b8f22d2a0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579760438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.2579760438
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.947002175
Short name T834
Test name
Test status
Simulation time 17977379 ps
CPU time 1.11 seconds
Started Jun 21 06:29:47 PM PDT 24
Finished Jun 21 06:29:50 PM PDT 24
Peak memory 208868 kb
Host smart-56999390-7191-491c-9381-6eb2516b5f06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947002175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.947002175
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2888789418
Short name T584
Test name
Test status
Simulation time 323974464 ps
CPU time 15.76 seconds
Started Jun 21 06:29:43 PM PDT 24
Finished Jun 21 06:30:00 PM PDT 24
Peak memory 218356 kb
Host smart-2f40c57c-6ff0-4836-93e5-79d14cb87935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888789418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2888789418
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.3865926345
Short name T813
Test name
Test status
Simulation time 241554018 ps
CPU time 1.84 seconds
Started Jun 21 06:29:44 PM PDT 24
Finished Jun 21 06:29:47 PM PDT 24
Peak memory 217136 kb
Host smart-a6b76f18-e1f4-4349-8633-d2c6022e0671
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865926345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.3865926345
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.3787854172
Short name T567
Test name
Test status
Simulation time 2564155945 ps
CPU time 41.89 seconds
Started Jun 21 06:29:41 PM PDT 24
Finished Jun 21 06:30:25 PM PDT 24
Peak memory 226192 kb
Host smart-9b9ef9b8-6b92-4a43-af32-97616029fce4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787854172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.3787854172
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.4020518992
Short name T719
Test name
Test status
Simulation time 672966094 ps
CPU time 11.28 seconds
Started Jun 21 06:29:48 PM PDT 24
Finished Jun 21 06:30:01 PM PDT 24
Peak memory 225380 kb
Host smart-cbad9d06-fbb8-45d7-8d0d-8cd560e49b3c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020518992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.4020518992
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.4139901685
Short name T466
Test name
Test status
Simulation time 415822521 ps
CPU time 3.9 seconds
Started Jun 21 06:29:45 PM PDT 24
Finished Jun 21 06:29:50 PM PDT 24
Peak memory 217812 kb
Host smart-5e974cf4-a37c-4a75-9836-b6b9d99aedb7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139901685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.4139901685
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.1135035508
Short name T2
Test name
Test status
Simulation time 1769974312 ps
CPU time 61.28 seconds
Started Jun 21 06:29:42 PM PDT 24
Finished Jun 21 06:30:45 PM PDT 24
Peak memory 270128 kb
Host smart-53b7fc0e-1d21-43db-9096-a74444b3cc27
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135035508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.1135035508
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1559750743
Short name T533
Test name
Test status
Simulation time 6844278271 ps
CPU time 28.64 seconds
Started Jun 21 06:29:42 PM PDT 24
Finished Jun 21 06:30:12 PM PDT 24
Peak memory 250928 kb
Host smart-580fa2ce-ac3e-441b-8d33-f1676766fd89
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559750743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1559750743
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3543808693
Short name T189
Test name
Test status
Simulation time 89632323 ps
CPU time 1.72 seconds
Started Jun 21 06:29:46 PM PDT 24
Finished Jun 21 06:29:50 PM PDT 24
Peak memory 218412 kb
Host smart-a3ee3e9c-b0ec-4f0e-974e-8957176d017b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543808693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3543808693
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3040735366
Short name T258
Test name
Test status
Simulation time 4603712719 ps
CPU time 13.69 seconds
Started Jun 21 06:29:39 PM PDT 24
Finished Jun 21 06:29:54 PM PDT 24
Peak memory 219184 kb
Host smart-af79c3d6-a381-4dbc-b22b-08321350c218
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040735366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3040735366
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3905272941
Short name T490
Test name
Test status
Simulation time 390982533 ps
CPU time 15.18 seconds
Started Jun 21 06:30:04 PM PDT 24
Finished Jun 21 06:30:22 PM PDT 24
Peak memory 218416 kb
Host smart-0999f6be-c011-4459-9817-94db524aafb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905272941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.3905272941
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.1245137934
Short name T805
Test name
Test status
Simulation time 900856433 ps
CPU time 8.48 seconds
Started Jun 21 06:29:42 PM PDT 24
Finished Jun 21 06:29:51 PM PDT 24
Peak memory 218380 kb
Host smart-5178ee38-632e-4e52-b072-f05c79c2bf78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245137934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
1245137934
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.3603313892
Short name T157
Test name
Test status
Simulation time 382320689 ps
CPU time 10.43 seconds
Started Jun 21 06:29:47 PM PDT 24
Finished Jun 21 06:30:00 PM PDT 24
Peak memory 226196 kb
Host smart-b8e9f422-a12f-49d7-8687-af20026999be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603313892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.3603313892
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1246248232
Short name T741
Test name
Test status
Simulation time 53996996 ps
CPU time 1.7 seconds
Started Jun 21 06:29:45 PM PDT 24
Finished Jun 21 06:29:48 PM PDT 24
Peak memory 217792 kb
Host smart-99e7226e-0c53-453d-a5db-3ffaaf8727d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246248232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1246248232
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.4249630493
Short name T195
Test name
Test status
Simulation time 5484578938 ps
CPU time 33.34 seconds
Started Jun 21 06:29:41 PM PDT 24
Finished Jun 21 06:30:16 PM PDT 24
Peak memory 251112 kb
Host smart-2f5b4151-ed09-4394-9abc-67c064a564a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249630493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.4249630493
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2050321042
Short name T582
Test name
Test status
Simulation time 166312478 ps
CPU time 5.9 seconds
Started Jun 21 06:29:40 PM PDT 24
Finished Jun 21 06:29:48 PM PDT 24
Peak memory 246716 kb
Host smart-0cf864af-5da0-4050-996c-f0fa6f9937cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050321042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2050321042
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.4063530814
Short name T458
Test name
Test status
Simulation time 51352782698 ps
CPU time 291.91 seconds
Started Jun 21 06:29:43 PM PDT 24
Finished Jun 21 06:34:36 PM PDT 24
Peak memory 496336 kb
Host smart-4754e00f-81ba-4e90-8927-218d53704fab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063530814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.4063530814
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2361861553
Short name T146
Test name
Test status
Simulation time 18710991 ps
CPU time 0.9 seconds
Started Jun 21 06:29:36 PM PDT 24
Finished Jun 21 06:29:39 PM PDT 24
Peak memory 211924 kb
Host smart-0c8a8cdb-15bb-4d0d-8dcc-281015837d97
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361861553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.2361861553
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.1616113894
Short name T555
Test name
Test status
Simulation time 15989122 ps
CPU time 0.92 seconds
Started Jun 21 06:28:53 PM PDT 24
Finished Jun 21 06:28:55 PM PDT 24
Peak memory 208836 kb
Host smart-b015b5d4-edeb-43ff-9df1-7f7af6041dae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616113894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1616113894
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.1652464313
Short name T259
Test name
Test status
Simulation time 2316727593 ps
CPU time 13.3 seconds
Started Jun 21 06:28:54 PM PDT 24
Finished Jun 21 06:29:10 PM PDT 24
Peak memory 218400 kb
Host smart-ff0c0c5f-3933-46ee-ba8e-1d6a1600051d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652464313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.1652464313
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1315016203
Short name T31
Test name
Test status
Simulation time 2229050307 ps
CPU time 4.6 seconds
Started Jun 21 06:28:49 PM PDT 24
Finished Jun 21 06:28:54 PM PDT 24
Peak memory 217520 kb
Host smart-5b8d7af3-c586-4a0d-bf5b-fcd4b4fb8d18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315016203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1315016203
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.2290548170
Short name T420
Test name
Test status
Simulation time 3615914984 ps
CPU time 30.25 seconds
Started Jun 21 06:28:44 PM PDT 24
Finished Jun 21 06:29:15 PM PDT 24
Peak memory 219116 kb
Host smart-ca5c16a7-260e-40d9-9a4b-b217852fba1a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290548170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.2290548170
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.3863846442
Short name T454
Test name
Test status
Simulation time 4003146656 ps
CPU time 6.71 seconds
Started Jun 21 06:28:49 PM PDT 24
Finished Jun 21 06:28:56 PM PDT 24
Peak memory 218028 kb
Host smart-96359311-bca4-4f8f-bd8b-5c05210e458c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863846442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.3
863846442
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2971207453
Short name T429
Test name
Test status
Simulation time 450355896 ps
CPU time 2.25 seconds
Started Jun 21 06:28:41 PM PDT 24
Finished Jun 21 06:28:44 PM PDT 24
Peak memory 221828 kb
Host smart-124572cc-89e2-432c-b157-01a95da19f7f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971207453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2971207453
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.4192580778
Short name T773
Test name
Test status
Simulation time 913408318 ps
CPU time 27.11 seconds
Started Jun 21 06:28:52 PM PDT 24
Finished Jun 21 06:29:21 PM PDT 24
Peak memory 217528 kb
Host smart-16913dfd-8d1f-47a9-b613-33835f960ac3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192580778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.4192580778
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.778823441
Short name T492
Test name
Test status
Simulation time 303746436 ps
CPU time 4.59 seconds
Started Jun 21 06:28:51 PM PDT 24
Finished Jun 21 06:28:57 PM PDT 24
Peak memory 217756 kb
Host smart-12fcb3a4-1ef9-4048-a9af-b89e29aa9870
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778823441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.778823441
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1257018538
Short name T810
Test name
Test status
Simulation time 4086204311 ps
CPU time 44.5 seconds
Started Jun 21 06:28:44 PM PDT 24
Finished Jun 21 06:29:29 PM PDT 24
Peak memory 283756 kb
Host smart-072805fc-1db8-4fb3-97ff-77c72b70699d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257018538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.1257018538
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.4172231296
Short name T387
Test name
Test status
Simulation time 1522081249 ps
CPU time 11.56 seconds
Started Jun 21 06:28:54 PM PDT 24
Finished Jun 21 06:29:08 PM PDT 24
Peak memory 219348 kb
Host smart-5dbd3d28-06ce-43d1-9c19-feb8a1e80dee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172231296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.4172231296
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.1824742483
Short name T246
Test name
Test status
Simulation time 215613058 ps
CPU time 3.01 seconds
Started Jun 21 06:28:46 PM PDT 24
Finished Jun 21 06:28:50 PM PDT 24
Peak memory 218364 kb
Host smart-24a77c31-41b3-4a76-b747-61cc53031bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824742483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.1824742483
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.103072220
Short name T200
Test name
Test status
Simulation time 356682868 ps
CPU time 12.41 seconds
Started Jun 21 06:28:45 PM PDT 24
Finished Jun 21 06:28:58 PM PDT 24
Peak memory 214336 kb
Host smart-9f949290-4eaa-4bb8-84ec-525f8fa8390f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103072220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.103072220
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2092520819
Short name T85
Test name
Test status
Simulation time 254963590 ps
CPU time 22.26 seconds
Started Jun 21 06:28:52 PM PDT 24
Finished Jun 21 06:29:16 PM PDT 24
Peak memory 268128 kb
Host smart-cbca3ee0-f97f-40f5-be4b-2ac1797aa04c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092520819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2092520819
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.1887481761
Short name T586
Test name
Test status
Simulation time 2571369077 ps
CPU time 27.27 seconds
Started Jun 21 06:28:45 PM PDT 24
Finished Jun 21 06:29:13 PM PDT 24
Peak memory 226288 kb
Host smart-4f3e4d7e-09b8-462e-afe2-728d3384cdc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887481761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1887481761
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2468656452
Short name T747
Test name
Test status
Simulation time 1427691872 ps
CPU time 13.74 seconds
Started Jun 21 06:28:54 PM PDT 24
Finished Jun 21 06:29:10 PM PDT 24
Peak memory 218404 kb
Host smart-4562b487-7889-44c6-85f7-a4dc61ce92c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468656452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2468656452
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.3371531585
Short name T804
Test name
Test status
Simulation time 225959870 ps
CPU time 8.46 seconds
Started Jun 21 06:28:54 PM PDT 24
Finished Jun 21 06:29:04 PM PDT 24
Peak memory 226080 kb
Host smart-8c3c5e73-38e2-4aa8-90fd-5597c4b11b60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371531585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.3
371531585
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.2398188384
Short name T487
Test name
Test status
Simulation time 287669322 ps
CPU time 11.39 seconds
Started Jun 21 06:28:47 PM PDT 24
Finished Jun 21 06:28:59 PM PDT 24
Peak memory 218352 kb
Host smart-914da288-08c9-4213-b864-4a8e3911e551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398188384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2398188384
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.3609786234
Short name T560
Test name
Test status
Simulation time 29337266 ps
CPU time 2.02 seconds
Started Jun 21 06:28:54 PM PDT 24
Finished Jun 21 06:28:58 PM PDT 24
Peak memory 222388 kb
Host smart-52375f77-0ad8-43ee-be30-c0ad5c6c116a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609786234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3609786234
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.3529104219
Short name T639
Test name
Test status
Simulation time 190975683 ps
CPU time 27.82 seconds
Started Jun 21 06:28:44 PM PDT 24
Finished Jun 21 06:29:12 PM PDT 24
Peak memory 251148 kb
Host smart-72551f0f-cfd1-42f7-8081-9371b4952031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529104219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3529104219
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.572525347
Short name T13
Test name
Test status
Simulation time 310382280 ps
CPU time 2.9 seconds
Started Jun 21 06:28:52 PM PDT 24
Finished Jun 21 06:28:56 PM PDT 24
Peak memory 218232 kb
Host smart-73d0b6a9-bc46-45a8-9af7-266609be80ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572525347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.572525347
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2668786499
Short name T524
Test name
Test status
Simulation time 43838476671 ps
CPU time 273.06 seconds
Started Jun 21 06:28:53 PM PDT 24
Finished Jun 21 06:33:28 PM PDT 24
Peak memory 226152 kb
Host smart-a55511a5-dcf4-45bf-8a4c-d433c3767c68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668786499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2668786499
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3332691783
Short name T824
Test name
Test status
Simulation time 50535818 ps
CPU time 1.01 seconds
Started Jun 21 06:28:48 PM PDT 24
Finished Jun 21 06:28:50 PM PDT 24
Peak memory 211964 kb
Host smart-20d287dd-129f-4805-ada3-76188258ea5e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332691783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.3332691783
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.517043090
Short name T39
Test name
Test status
Simulation time 89130545 ps
CPU time 1.21 seconds
Started Jun 21 06:29:49 PM PDT 24
Finished Jun 21 06:29:53 PM PDT 24
Peak memory 208980 kb
Host smart-a54d3ddd-2b98-4794-9504-a3fc77a58aa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517043090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.517043090
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.2276222566
Short name T95
Test name
Test status
Simulation time 372658994 ps
CPU time 10.8 seconds
Started Jun 21 06:29:42 PM PDT 24
Finished Jun 21 06:29:54 PM PDT 24
Peak memory 218352 kb
Host smart-c7934145-cd9d-4575-813f-a092879cb752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276222566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2276222566
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.3692713859
Short name T36
Test name
Test status
Simulation time 152175407 ps
CPU time 4.22 seconds
Started Jun 21 06:29:43 PM PDT 24
Finished Jun 21 06:29:48 PM PDT 24
Peak memory 217104 kb
Host smart-c93e48a2-8cd5-4619-8d81-a69d2ce3d15f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692713859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.3692713859
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2643089625
Short name T232
Test name
Test status
Simulation time 63374815 ps
CPU time 1.7 seconds
Started Jun 21 06:29:45 PM PDT 24
Finished Jun 21 06:29:47 PM PDT 24
Peak memory 221992 kb
Host smart-f9607298-7aea-4041-85fd-bbc0c60c1880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643089625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2643089625
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.2254527748
Short name T624
Test name
Test status
Simulation time 1349943899 ps
CPU time 14.44 seconds
Started Jun 21 06:29:45 PM PDT 24
Finished Jun 21 06:30:02 PM PDT 24
Peak memory 219056 kb
Host smart-15893c70-b8df-4ead-b1e8-59bd490adc6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254527748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2254527748
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.4178685531
Short name T688
Test name
Test status
Simulation time 4566635805 ps
CPU time 16.2 seconds
Started Jun 21 06:29:44 PM PDT 24
Finished Jun 21 06:30:01 PM PDT 24
Peak memory 218468 kb
Host smart-a9b9fb78-37b5-4291-a64b-5138f15dd1d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178685531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.4178685531
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.891531159
Short name T730
Test name
Test status
Simulation time 911104480 ps
CPU time 8.02 seconds
Started Jun 21 06:29:46 PM PDT 24
Finished Jun 21 06:29:56 PM PDT 24
Peak memory 218332 kb
Host smart-846e1af4-92bf-48a8-b4f6-6f7d0408b5e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891531159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.891531159
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.4225346102
Short name T689
Test name
Test status
Simulation time 1431441180 ps
CPU time 8.37 seconds
Started Jun 21 06:29:48 PM PDT 24
Finished Jun 21 06:29:58 PM PDT 24
Peak memory 218500 kb
Host smart-ead11294-231b-4d5f-b529-973c4325392a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225346102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.4225346102
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.3867632990
Short name T324
Test name
Test status
Simulation time 29537486 ps
CPU time 1.5 seconds
Started Jun 21 06:29:47 PM PDT 24
Finished Jun 21 06:29:50 PM PDT 24
Peak memory 213956 kb
Host smart-b6797056-24b7-4417-8da8-bdff92fdd9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867632990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3867632990
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.2901768618
Short name T430
Test name
Test status
Simulation time 503937282 ps
CPU time 19.61 seconds
Started Jun 21 06:29:45 PM PDT 24
Finished Jun 21 06:30:06 PM PDT 24
Peak memory 250960 kb
Host smart-27f7030e-332e-4c90-a25c-90a1d1f6d7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901768618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2901768618
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.2336790510
Short name T515
Test name
Test status
Simulation time 241286349 ps
CPU time 7.05 seconds
Started Jun 21 06:29:48 PM PDT 24
Finished Jun 21 06:29:57 PM PDT 24
Peak memory 246640 kb
Host smart-da4ad629-2898-42e8-9018-b8440af9281f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336790510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2336790510
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1472202946
Short name T19
Test name
Test status
Simulation time 10281723224 ps
CPU time 103.58 seconds
Started Jun 21 06:29:49 PM PDT 24
Finished Jun 21 06:31:35 PM PDT 24
Peak memory 274244 kb
Host smart-d64a136b-8237-4ed7-a792-66fb22eea45b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472202946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.1472202946
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.4264911291
Short name T149
Test name
Test status
Simulation time 27581493043 ps
CPU time 525.78 seconds
Started Jun 21 06:29:47 PM PDT 24
Finished Jun 21 06:38:34 PM PDT 24
Peak memory 283772 kb
Host smart-2ec4af43-10ac-45df-8352-fc105780ce7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4264911291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.4264911291
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.4051243596
Short name T164
Test name
Test status
Simulation time 26261217 ps
CPU time 1.06 seconds
Started Jun 21 06:29:49 PM PDT 24
Finished Jun 21 06:29:52 PM PDT 24
Peak memory 211920 kb
Host smart-5b37b153-d714-4629-a12c-9280a0438b09
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051243596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.4051243596
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.1445334877
Short name T616
Test name
Test status
Simulation time 62630602 ps
CPU time 0.98 seconds
Started Jun 21 06:29:52 PM PDT 24
Finished Jun 21 06:29:54 PM PDT 24
Peak memory 208948 kb
Host smart-8bbadfe3-a02f-4c72-b3eb-5ae69c25b7af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445334877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1445334877
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.2465022413
Short name T285
Test name
Test status
Simulation time 1932926223 ps
CPU time 14.31 seconds
Started Jun 21 06:29:43 PM PDT 24
Finished Jun 21 06:29:59 PM PDT 24
Peak memory 218280 kb
Host smart-4d1d0a75-d570-41c1-896c-7f66b6939d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465022413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.2465022413
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.457292152
Short name T371
Test name
Test status
Simulation time 2096556676 ps
CPU time 4.89 seconds
Started Jun 21 06:29:49 PM PDT 24
Finished Jun 21 06:29:55 PM PDT 24
Peak memory 217200 kb
Host smart-63cf5d24-f54c-498b-9399-6c5a8dcd1e07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457292152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.457292152
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.1230480480
Short name T242
Test name
Test status
Simulation time 116750888 ps
CPU time 3.7 seconds
Started Jun 21 06:29:41 PM PDT 24
Finished Jun 21 06:29:46 PM PDT 24
Peak memory 222660 kb
Host smart-6f9cdbf2-cc6c-4182-b240-3deeb17a5cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230480480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1230480480
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.3368011873
Short name T738
Test name
Test status
Simulation time 438469858 ps
CPU time 11.69 seconds
Started Jun 21 06:29:52 PM PDT 24
Finished Jun 21 06:30:05 PM PDT 24
Peak memory 219056 kb
Host smart-3ca43f4a-d06b-4553-9cd4-b0b2a946fbbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368011873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3368011873
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1056964658
Short name T780
Test name
Test status
Simulation time 1430436698 ps
CPU time 13.34 seconds
Started Jun 21 06:29:45 PM PDT 24
Finished Jun 21 06:30:00 PM PDT 24
Peak memory 218388 kb
Host smart-c0f54cf7-99d1-4a53-9ed4-8361538ac60a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056964658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1056964658
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.771586302
Short name T375
Test name
Test status
Simulation time 296077288 ps
CPU time 8.3 seconds
Started Jun 21 06:30:01 PM PDT 24
Finished Jun 21 06:30:12 PM PDT 24
Peak memory 218380 kb
Host smart-8865dfbd-5f21-46b0-ac5e-5440c027cb6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771586302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.771586302
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.1030626145
Short name T312
Test name
Test status
Simulation time 965246836 ps
CPU time 9.92 seconds
Started Jun 21 06:29:46 PM PDT 24
Finished Jun 21 06:29:58 PM PDT 24
Peak memory 218404 kb
Host smart-7d537b26-790c-47c2-bfef-6ae972edb633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030626145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1030626145
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.3566652395
Short name T316
Test name
Test status
Simulation time 29257340 ps
CPU time 1.51 seconds
Started Jun 21 06:29:46 PM PDT 24
Finished Jun 21 06:29:49 PM PDT 24
Peak memory 217860 kb
Host smart-0e2f7beb-5052-4be8-9b7f-e7fdb22f67f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566652395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3566652395
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.825779264
Short name T11
Test name
Test status
Simulation time 2172996484 ps
CPU time 23.16 seconds
Started Jun 21 06:29:49 PM PDT 24
Finished Jun 21 06:30:14 PM PDT 24
Peak memory 250940 kb
Host smart-39610fe2-4e64-4f77-9f57-c993bd4f7022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825779264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.825779264
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.1963841229
Short name T340
Test name
Test status
Simulation time 378398469 ps
CPU time 8.44 seconds
Started Jun 21 06:29:48 PM PDT 24
Finished Jun 21 06:29:58 PM PDT 24
Peak memory 251060 kb
Host smart-75d39b92-3e6d-4165-a7f9-353c8dda238d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963841229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1963841229
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.1288486441
Short name T629
Test name
Test status
Simulation time 14833538172 ps
CPU time 180.59 seconds
Started Jun 21 06:29:53 PM PDT 24
Finished Jun 21 06:32:55 PM PDT 24
Peak memory 412688 kb
Host smart-88024882-0b89-4e4a-b65b-b4b4b83feeb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288486441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.1288486441
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1737144248
Short name T303
Test name
Test status
Simulation time 11887811 ps
CPU time 0.88 seconds
Started Jun 21 06:29:46 PM PDT 24
Finished Jun 21 06:29:48 PM PDT 24
Peak memory 211928 kb
Host smart-313fe8b3-ceef-453d-b32b-2c063806a0ad
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737144248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.1737144248
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.201572041
Short name T585
Test name
Test status
Simulation time 14452983 ps
CPU time 0.86 seconds
Started Jun 21 06:29:49 PM PDT 24
Finished Jun 21 06:29:52 PM PDT 24
Peak memory 208844 kb
Host smart-4a8eb86f-f1cf-4c2a-a99c-2ba4d923a424
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201572041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.201572041
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2210989654
Short name T666
Test name
Test status
Simulation time 2786695425 ps
CPU time 17.54 seconds
Started Jun 21 06:30:03 PM PDT 24
Finished Jun 21 06:30:23 PM PDT 24
Peak memory 218496 kb
Host smart-0776cafe-c1bb-414a-b639-33977b32f99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210989654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2210989654
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.353910866
Short name T822
Test name
Test status
Simulation time 409580469 ps
CPU time 11.35 seconds
Started Jun 21 06:29:52 PM PDT 24
Finished Jun 21 06:30:04 PM PDT 24
Peak memory 217620 kb
Host smart-a9f19e0a-f55b-4dc9-b9a9-89994e6c8709
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353910866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.353910866
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3320524335
Short name T239
Test name
Test status
Simulation time 29793400 ps
CPU time 1.49 seconds
Started Jun 21 06:29:47 PM PDT 24
Finished Jun 21 06:29:51 PM PDT 24
Peak memory 218348 kb
Host smart-e4129dba-b57f-4b42-b20d-bc7d441eb8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320524335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3320524335
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.2666660687
Short name T282
Test name
Test status
Simulation time 323018948 ps
CPU time 12.35 seconds
Started Jun 21 06:29:47 PM PDT 24
Finished Jun 21 06:30:01 PM PDT 24
Peak memory 218980 kb
Host smart-1b3ee28b-5447-403d-bd2c-f2bb84116f88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666660687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2666660687
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3722747639
Short name T662
Test name
Test status
Simulation time 313039976 ps
CPU time 10.82 seconds
Started Jun 21 06:29:45 PM PDT 24
Finished Jun 21 06:29:58 PM PDT 24
Peak memory 218484 kb
Host smart-d75eff00-f022-4c87-a2eb-85546cabad81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722747639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3722747639
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2562178367
Short name T301
Test name
Test status
Simulation time 1483416760 ps
CPU time 8.83 seconds
Started Jun 21 06:29:49 PM PDT 24
Finished Jun 21 06:29:59 PM PDT 24
Peak memory 218428 kb
Host smart-b04e2160-7ef6-4171-aa70-80e0c1e7913f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562178367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2562178367
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.3525175032
Short name T815
Test name
Test status
Simulation time 293532319 ps
CPU time 7.92 seconds
Started Jun 21 06:29:54 PM PDT 24
Finished Jun 21 06:30:03 PM PDT 24
Peak memory 224776 kb
Host smart-bd89a099-6fe3-4dc7-8a78-c1768e1b1794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525175032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3525175032
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.3301601762
Short name T144
Test name
Test status
Simulation time 163636724 ps
CPU time 1.53 seconds
Started Jun 21 06:30:03 PM PDT 24
Finished Jun 21 06:30:07 PM PDT 24
Peak memory 214072 kb
Host smart-6f73f4a0-c5d1-4e98-8cab-46b9bc53052a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301601762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3301601762
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.1442075817
Short name T354
Test name
Test status
Simulation time 330613121 ps
CPU time 24.99 seconds
Started Jun 21 06:29:49 PM PDT 24
Finished Jun 21 06:30:16 PM PDT 24
Peak memory 251048 kb
Host smart-65da3bb1-3ca2-458b-b2c9-1e83820b779e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442075817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1442075817
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1528580010
Short name T609
Test name
Test status
Simulation time 73853328 ps
CPU time 3.99 seconds
Started Jun 21 06:29:46 PM PDT 24
Finished Jun 21 06:29:52 PM PDT 24
Peak memory 226464 kb
Host smart-3109abbf-217b-437b-b8ca-60996388b9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528580010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1528580010
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2606567601
Short name T685
Test name
Test status
Simulation time 3338307325 ps
CPU time 130.75 seconds
Started Jun 21 06:29:48 PM PDT 24
Finished Jun 21 06:32:01 PM PDT 24
Peak memory 251096 kb
Host smart-28785536-087d-404e-b3c1-729569c0205a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606567601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2606567601
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.3423191513
Short name T113
Test name
Test status
Simulation time 32017235987 ps
CPU time 607.67 seconds
Started Jun 21 06:29:49 PM PDT 24
Finished Jun 21 06:39:59 PM PDT 24
Peak memory 475496 kb
Host smart-2e688a90-1107-4f07-85fc-6aa6119cbdaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3423191513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.3423191513
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.1394377521
Short name T734
Test name
Test status
Simulation time 30397513 ps
CPU time 0.91 seconds
Started Jun 21 06:29:55 PM PDT 24
Finished Jun 21 06:29:57 PM PDT 24
Peak memory 212020 kb
Host smart-f41c6199-fb0d-4e1e-981f-2647f0f66ae6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394377521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.1394377521
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.629479941
Short name T470
Test name
Test status
Simulation time 73674244 ps
CPU time 0.96 seconds
Started Jun 21 06:29:47 PM PDT 24
Finished Jun 21 06:29:50 PM PDT 24
Peak memory 208904 kb
Host smart-7c1c6475-b9b7-4696-950f-122383114ffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629479941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.629479941
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3879596400
Short name T774
Test name
Test status
Simulation time 1290909875 ps
CPU time 16.48 seconds
Started Jun 21 06:29:59 PM PDT 24
Finished Jun 21 06:30:18 PM PDT 24
Peak memory 218356 kb
Host smart-39e90cf3-abce-43a8-be36-0a5836cbc687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879596400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3879596400
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.1349753479
Short name T694
Test name
Test status
Simulation time 2529936003 ps
CPU time 8.26 seconds
Started Jun 21 06:29:47 PM PDT 24
Finished Jun 21 06:29:58 PM PDT 24
Peak memory 217496 kb
Host smart-b99e3e24-5d5f-44ee-8e72-4c6d5136df34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349753479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1349753479
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.1444000140
Short name T697
Test name
Test status
Simulation time 262001615 ps
CPU time 2.4 seconds
Started Jun 21 06:29:48 PM PDT 24
Finished Jun 21 06:29:52 PM PDT 24
Peak memory 218352 kb
Host smart-e073f888-6d81-4152-843a-0b16422d349f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444000140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.1444000140
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.2888586992
Short name T812
Test name
Test status
Simulation time 507404299 ps
CPU time 16.93 seconds
Started Jun 21 06:29:58 PM PDT 24
Finished Jun 21 06:30:17 PM PDT 24
Peak memory 219128 kb
Host smart-790d4a84-c10b-4b96-9a17-393eeb9b0bf0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888586992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.2888586992
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3161134218
Short name T421
Test name
Test status
Simulation time 4428018992 ps
CPU time 16.84 seconds
Started Jun 21 06:29:46 PM PDT 24
Finished Jun 21 06:30:05 PM PDT 24
Peak memory 219044 kb
Host smart-6188e230-8529-4d68-89ea-4d369f116c3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161134218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.3161134218
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1241042025
Short name T309
Test name
Test status
Simulation time 350858129 ps
CPU time 7.83 seconds
Started Jun 21 06:29:48 PM PDT 24
Finished Jun 21 06:29:58 PM PDT 24
Peak memory 218396 kb
Host smart-01e914a5-7e9c-4b99-90a2-0886fee430a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241042025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
1241042025
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2438852587
Short name T727
Test name
Test status
Simulation time 1337402558 ps
CPU time 8.85 seconds
Started Jun 21 06:29:52 PM PDT 24
Finished Jun 21 06:30:02 PM PDT 24
Peak memory 224816 kb
Host smart-0ec977a7-b70e-4ac2-b2f5-6b3ea7622cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438852587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2438852587
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1013204904
Short name T831
Test name
Test status
Simulation time 213606160 ps
CPU time 1.21 seconds
Started Jun 21 06:29:58 PM PDT 24
Finished Jun 21 06:30:01 PM PDT 24
Peak memory 217828 kb
Host smart-c4cb5c61-36a4-48a8-8738-892a1d62c53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013204904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1013204904
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.2557924870
Short name T707
Test name
Test status
Simulation time 965805048 ps
CPU time 31.78 seconds
Started Jun 21 06:29:48 PM PDT 24
Finished Jun 21 06:30:22 PM PDT 24
Peak memory 251096 kb
Host smart-bce915f8-7d0c-4f8d-8368-f1d2f8631920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557924870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.2557924870
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3013401561
Short name T450
Test name
Test status
Simulation time 58025021 ps
CPU time 3.41 seconds
Started Jun 21 06:29:59 PM PDT 24
Finished Jun 21 06:30:05 PM PDT 24
Peak memory 218436 kb
Host smart-c431a1a2-b5d1-4189-a171-606c0e83e894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013401561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3013401561
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.1264823487
Short name T270
Test name
Test status
Simulation time 52406735138 ps
CPU time 437.21 seconds
Started Jun 21 06:29:54 PM PDT 24
Finished Jun 21 06:37:12 PM PDT 24
Peak memory 356576 kb
Host smart-de562f34-b582-4c57-b679-d0fa66867863
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264823487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.1264823487
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1701437214
Short name T715
Test name
Test status
Simulation time 43503968 ps
CPU time 0.88 seconds
Started Jun 21 06:29:48 PM PDT 24
Finished Jun 21 06:29:51 PM PDT 24
Peak memory 211888 kb
Host smart-7e1a1fdf-e401-43e3-8e20-debf3293dfca
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701437214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.1701437214
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.72719533
Short name T793
Test name
Test status
Simulation time 13350430 ps
CPU time 1.06 seconds
Started Jun 21 06:29:55 PM PDT 24
Finished Jun 21 06:29:57 PM PDT 24
Peak memory 208896 kb
Host smart-f6929fc4-10d2-4c4a-9884-8de701663698
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72719533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.72719533
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2390772529
Short name T422
Test name
Test status
Simulation time 813361933 ps
CPU time 16.56 seconds
Started Jun 21 06:29:49 PM PDT 24
Finished Jun 21 06:30:08 PM PDT 24
Peak memory 218352 kb
Host smart-fd097bb6-73c3-4408-8382-ac1bea015bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390772529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2390772529
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.2016849852
Short name T686
Test name
Test status
Simulation time 2093314539 ps
CPU time 12.54 seconds
Started Jun 21 06:29:52 PM PDT 24
Finished Jun 21 06:30:06 PM PDT 24
Peak memory 217300 kb
Host smart-7a6db02e-3f66-44a4-a475-4e35f7517970
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016849852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.2016849852
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.4250090232
Short name T758
Test name
Test status
Simulation time 69894155 ps
CPU time 1.94 seconds
Started Jun 21 06:29:55 PM PDT 24
Finished Jun 21 06:29:59 PM PDT 24
Peak memory 222032 kb
Host smart-e823fd1e-b299-4121-a6a5-d9d904f0d775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250090232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.4250090232
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.518332665
Short name T290
Test name
Test status
Simulation time 1838683548 ps
CPU time 24.39 seconds
Started Jun 21 06:29:58 PM PDT 24
Finished Jun 21 06:30:24 PM PDT 24
Peak memory 226176 kb
Host smart-20d021d3-b026-475f-b227-57c92d67956b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518332665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.518332665
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.3854634769
Short name T55
Test name
Test status
Simulation time 517764698 ps
CPU time 10.13 seconds
Started Jun 21 06:29:47 PM PDT 24
Finished Jun 21 06:29:59 PM PDT 24
Peak memory 218404 kb
Host smart-2391291d-6770-42e7-a455-7eadbc2a7a19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854634769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.3854634769
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.4225506662
Short name T300
Test name
Test status
Simulation time 259048277 ps
CPU time 7.09 seconds
Started Jun 21 06:29:46 PM PDT 24
Finished Jun 21 06:29:55 PM PDT 24
Peak memory 218376 kb
Host smart-b9226c77-0e27-42a3-bf5e-828de8bffdb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225506662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
4225506662
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.2467551285
Short name T486
Test name
Test status
Simulation time 1974045001 ps
CPU time 10.57 seconds
Started Jun 21 06:29:47 PM PDT 24
Finished Jun 21 06:30:00 PM PDT 24
Peak memory 225636 kb
Host smart-8ff45b8b-5bc9-40b3-b50a-cafb21115702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467551285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.2467551285
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.3680648065
Short name T519
Test name
Test status
Simulation time 55715434 ps
CPU time 1.26 seconds
Started Jun 21 06:29:50 PM PDT 24
Finished Jun 21 06:29:53 PM PDT 24
Peak memory 217896 kb
Host smart-70a52179-ffed-44af-94f8-3df11489625e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680648065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3680648065
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1150626454
Short name T508
Test name
Test status
Simulation time 205801008 ps
CPU time 24.24 seconds
Started Jun 21 06:29:46 PM PDT 24
Finished Jun 21 06:30:13 PM PDT 24
Peak memory 251008 kb
Host smart-b97d2060-45dd-41f2-bd4d-29e3105021ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150626454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1150626454
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.431704853
Short name T380
Test name
Test status
Simulation time 60244766 ps
CPU time 7.81 seconds
Started Jun 21 06:29:50 PM PDT 24
Finished Jun 21 06:29:59 PM PDT 24
Peak memory 251016 kb
Host smart-3e99b8b9-1b37-4a5d-9943-7b8805836246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431704853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.431704853
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.1814843152
Short name T374
Test name
Test status
Simulation time 5367168836 ps
CPU time 63.14 seconds
Started Jun 21 06:30:02 PM PDT 24
Finished Jun 21 06:31:08 PM PDT 24
Peak memory 268412 kb
Host smart-0f95c09d-5efa-40c3-a5f6-06027390a14c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814843152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.1814843152
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1502600694
Short name T446
Test name
Test status
Simulation time 32825358 ps
CPU time 0.92 seconds
Started Jun 21 06:29:48 PM PDT 24
Finished Jun 21 06:29:51 PM PDT 24
Peak memory 211936 kb
Host smart-01c2f840-1674-4c10-8846-3b142476a800
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502600694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.1502600694
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.804444806
Short name T469
Test name
Test status
Simulation time 13193772 ps
CPU time 0.84 seconds
Started Jun 21 06:29:57 PM PDT 24
Finished Jun 21 06:30:00 PM PDT 24
Peak memory 208820 kb
Host smart-485a735f-fc21-496a-b3a9-81c8430b64c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804444806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.804444806
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.1297097248
Short name T442
Test name
Test status
Simulation time 500454527 ps
CPU time 13.81 seconds
Started Jun 21 06:29:54 PM PDT 24
Finished Jun 21 06:30:09 PM PDT 24
Peak memory 218360 kb
Host smart-2cd91857-4c63-431e-b99b-267bff679dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297097248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1297097248
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.301659310
Short name T5
Test name
Test status
Simulation time 573308701 ps
CPU time 6.8 seconds
Started Jun 21 06:30:04 PM PDT 24
Finished Jun 21 06:30:13 PM PDT 24
Peak memory 217196 kb
Host smart-7069571f-7be5-4595-8878-7b77953d8ce6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301659310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.301659310
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.3971969875
Short name T654
Test name
Test status
Simulation time 19399574 ps
CPU time 1.55 seconds
Started Jun 21 06:30:00 PM PDT 24
Finished Jun 21 06:30:04 PM PDT 24
Peak memory 218344 kb
Host smart-705605b6-0e65-484d-8ea9-b17e3107156a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971969875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.3971969875
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.2472758358
Short name T444
Test name
Test status
Simulation time 281357283 ps
CPU time 14.56 seconds
Started Jun 21 06:29:57 PM PDT 24
Finished Jun 21 06:30:13 PM PDT 24
Peak memory 218504 kb
Host smart-b731c214-ce9a-42ef-86ad-c5bee8b7c2ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472758358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2472758358
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.848051349
Short name T635
Test name
Test status
Simulation time 329476370 ps
CPU time 9.59 seconds
Started Jun 21 06:29:58 PM PDT 24
Finished Jun 21 06:30:09 PM PDT 24
Peak memory 218404 kb
Host smart-47118003-c263-4995-b7d4-a3f6d8a2794a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848051349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_di
gest.848051349
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1372029255
Short name T866
Test name
Test status
Simulation time 673496312 ps
CPU time 13.56 seconds
Started Jun 21 06:29:54 PM PDT 24
Finished Jun 21 06:30:09 PM PDT 24
Peak memory 226192 kb
Host smart-e6cdc4f9-b6e2-4963-b752-5db9a2a16317
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372029255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1372029255
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.860827160
Short name T390
Test name
Test status
Simulation time 9855344111 ps
CPU time 11.56 seconds
Started Jun 21 06:29:55 PM PDT 24
Finished Jun 21 06:30:09 PM PDT 24
Peak memory 226264 kb
Host smart-aa29be03-9c05-4bcb-8fce-8053708f516b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860827160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.860827160
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3178572774
Short name T313
Test name
Test status
Simulation time 82734527 ps
CPU time 2.44 seconds
Started Jun 21 06:30:04 PM PDT 24
Finished Jun 21 06:30:09 PM PDT 24
Peak memory 217076 kb
Host smart-849dca5f-9add-4ca6-a6e2-df4f7aba9fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178572774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3178572774
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.1485174281
Short name T372
Test name
Test status
Simulation time 426059572 ps
CPU time 27.05 seconds
Started Jun 21 06:29:56 PM PDT 24
Finished Jun 21 06:30:25 PM PDT 24
Peak memory 250976 kb
Host smart-e44f6ff4-9dc0-4476-9ebb-695c295049db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485174281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.1485174281
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.993632194
Short name T237
Test name
Test status
Simulation time 110019810 ps
CPU time 7.09 seconds
Started Jun 21 06:30:00 PM PDT 24
Finished Jun 21 06:30:09 PM PDT 24
Peak memory 247280 kb
Host smart-4f8b9615-0f07-44c0-8511-b8a71f41ee49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993632194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.993632194
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.2985943660
Short name T754
Test name
Test status
Simulation time 466582556 ps
CPU time 16.13 seconds
Started Jun 21 06:29:54 PM PDT 24
Finished Jun 21 06:30:12 PM PDT 24
Peak memory 218016 kb
Host smart-a2b4bec7-84d1-4256-be38-7860ee51f281
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985943660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.2985943660
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.3761888673
Short name T114
Test name
Test status
Simulation time 102438924820 ps
CPU time 2728.91 seconds
Started Jun 21 06:30:00 PM PDT 24
Finished Jun 21 07:15:31 PM PDT 24
Peak memory 1013900 kb
Host smart-11748aee-1228-4ff4-aaa2-7c460f398829
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3761888673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.3761888673
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2198220180
Short name T410
Test name
Test status
Simulation time 15837731 ps
CPU time 1.18 seconds
Started Jun 21 06:29:59 PM PDT 24
Finished Jun 21 06:30:03 PM PDT 24
Peak memory 211868 kb
Host smart-4e9efd9b-3da6-44e6-b5fb-40065704069a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198220180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2198220180
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1000645933
Short name T196
Test name
Test status
Simulation time 15468159 ps
CPU time 1.08 seconds
Started Jun 21 06:30:02 PM PDT 24
Finished Jun 21 06:30:06 PM PDT 24
Peak memory 208964 kb
Host smart-a7d4d541-cf86-4f0b-8d55-67a672b0d37e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000645933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1000645933
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.784637194
Short name T869
Test name
Test status
Simulation time 1225348899 ps
CPU time 12.85 seconds
Started Jun 21 06:29:56 PM PDT 24
Finished Jun 21 06:30:11 PM PDT 24
Peak memory 218364 kb
Host smart-df3b2b06-139a-4c5f-b81a-bd9a200dc4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784637194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.784637194
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1454776847
Short name T537
Test name
Test status
Simulation time 285028165 ps
CPU time 2.21 seconds
Started Jun 21 06:29:57 PM PDT 24
Finished Jun 21 06:30:01 PM PDT 24
Peak memory 217104 kb
Host smart-da594da6-eb29-41c0-bcae-bf3c8bf1be85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454776847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1454776847
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.2726871847
Short name T502
Test name
Test status
Simulation time 26781021 ps
CPU time 1.71 seconds
Started Jun 21 06:29:59 PM PDT 24
Finished Jun 21 06:30:02 PM PDT 24
Peak memory 218424 kb
Host smart-d9704b8a-ee13-493e-9b6d-8ad0c7cb08d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726871847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.2726871847
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.1392946908
Short name T558
Test name
Test status
Simulation time 200485024 ps
CPU time 11.15 seconds
Started Jun 21 06:29:59 PM PDT 24
Finished Jun 21 06:30:12 PM PDT 24
Peak memory 218456 kb
Host smart-55915eb6-b6dd-4ded-89cb-64f23e5b5d0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392946908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.1392946908
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3204364177
Short name T557
Test name
Test status
Simulation time 1744065189 ps
CPU time 16.64 seconds
Started Jun 21 06:29:55 PM PDT 24
Finished Jun 21 06:30:14 PM PDT 24
Peak memory 218332 kb
Host smart-52db5279-5e61-422c-a10e-870b320fffb2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204364177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.3204364177
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.4241865677
Short name T763
Test name
Test status
Simulation time 380066552 ps
CPU time 14.07 seconds
Started Jun 21 06:29:57 PM PDT 24
Finished Jun 21 06:30:12 PM PDT 24
Peak memory 226188 kb
Host smart-479f586a-48cb-4d1e-a325-4c29b247be37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241865677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
4241865677
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.4292886547
Short name T47
Test name
Test status
Simulation time 1125212964 ps
CPU time 9.52 seconds
Started Jun 21 06:29:58 PM PDT 24
Finished Jun 21 06:30:09 PM PDT 24
Peak memory 225356 kb
Host smart-1e102876-352c-42ed-8043-f10698ba2af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292886547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.4292886547
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3502190098
Short name T101
Test name
Test status
Simulation time 129474380 ps
CPU time 2.68 seconds
Started Jun 21 06:30:05 PM PDT 24
Finished Jun 21 06:30:10 PM PDT 24
Peak memory 217776 kb
Host smart-dfe88444-1313-434e-bacc-65c8f6ee8351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502190098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3502190098
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1898760339
Short name T327
Test name
Test status
Simulation time 918508732 ps
CPU time 21.58 seconds
Started Jun 21 06:30:04 PM PDT 24
Finished Jun 21 06:30:28 PM PDT 24
Peak memory 251056 kb
Host smart-30db6223-19ce-434f-8de4-588d0a0fa4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898760339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1898760339
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.3548129026
Short name T650
Test name
Test status
Simulation time 355182601 ps
CPU time 3.42 seconds
Started Jun 21 06:29:54 PM PDT 24
Finished Jun 21 06:29:59 PM PDT 24
Peak memory 226444 kb
Host smart-faaa4d27-5596-4f7a-9593-bffda21f47e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548129026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.3548129026
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.2033877297
Short name T234
Test name
Test status
Simulation time 525832706 ps
CPU time 12.29 seconds
Started Jun 21 06:29:59 PM PDT 24
Finished Jun 21 06:30:13 PM PDT 24
Peak memory 251016 kb
Host smart-1aeec6c9-9a58-4412-a628-b2d9ed8dee72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033877297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.2033877297
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1255876039
Short name T563
Test name
Test status
Simulation time 17169733 ps
CPU time 0.72 seconds
Started Jun 21 06:29:54 PM PDT 24
Finished Jun 21 06:29:56 PM PDT 24
Peak memory 207200 kb
Host smart-cf5baaff-1c17-40ce-bd76-7f05e7e17cff
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255876039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1255876039
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.1429361319
Short name T526
Test name
Test status
Simulation time 35484023 ps
CPU time 0.94 seconds
Started Jun 21 06:30:00 PM PDT 24
Finished Jun 21 06:30:03 PM PDT 24
Peak memory 208812 kb
Host smart-dbb8bd8d-df3d-4b87-9627-adbe5e2d7c9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429361319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.1429361319
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.1115648393
Short name T571
Test name
Test status
Simulation time 2426566865 ps
CPU time 8.08 seconds
Started Jun 21 06:29:58 PM PDT 24
Finished Jun 21 06:30:07 PM PDT 24
Peak memory 218320 kb
Host smart-c507b899-9d0c-44b3-93ef-4278ca6d3eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115648393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.1115648393
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.2528224877
Short name T709
Test name
Test status
Simulation time 351376722 ps
CPU time 7.9 seconds
Started Jun 21 06:29:55 PM PDT 24
Finished Jun 21 06:30:05 PM PDT 24
Peak memory 217472 kb
Host smart-95938d89-d9a0-402a-b483-fce3ff8b88a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528224877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.2528224877
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.390769922
Short name T768
Test name
Test status
Simulation time 470963195 ps
CPU time 3.89 seconds
Started Jun 21 06:29:59 PM PDT 24
Finished Jun 21 06:30:04 PM PDT 24
Peak memory 218336 kb
Host smart-1f1842fe-0775-45b6-ac2c-7dee0c0ddd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390769922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.390769922
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.2650234352
Short name T548
Test name
Test status
Simulation time 1379180539 ps
CPU time 11.54 seconds
Started Jun 21 06:29:59 PM PDT 24
Finished Jun 21 06:30:12 PM PDT 24
Peak memory 219108 kb
Host smart-9d12fb36-ea6e-4d7e-881d-3798b8aba8a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650234352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2650234352
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.3454506105
Short name T407
Test name
Test status
Simulation time 3975261602 ps
CPU time 22.3 seconds
Started Jun 21 06:30:03 PM PDT 24
Finished Jun 21 06:30:28 PM PDT 24
Peak memory 218408 kb
Host smart-1129f179-4c07-415a-ba74-c46b7b79afe3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454506105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.3454506105
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.152750350
Short name T665
Test name
Test status
Simulation time 2348755055 ps
CPU time 8.44 seconds
Started Jun 21 06:29:58 PM PDT 24
Finished Jun 21 06:30:08 PM PDT 24
Peak memory 226292 kb
Host smart-1a703bd0-d979-46ad-bc24-838b3e9cd71c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152750350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.152750350
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.3687279240
Short name T229
Test name
Test status
Simulation time 312732407 ps
CPU time 8.46 seconds
Started Jun 21 06:29:58 PM PDT 24
Finished Jun 21 06:30:08 PM PDT 24
Peak memory 225520 kb
Host smart-da1d6714-5594-4754-9049-2f5879416254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687279240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3687279240
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.2324405484
Short name T573
Test name
Test status
Simulation time 203212771 ps
CPU time 3 seconds
Started Jun 21 06:29:57 PM PDT 24
Finished Jun 21 06:30:01 PM PDT 24
Peak memory 217816 kb
Host smart-60037864-493a-46e3-8389-462fd95224d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324405484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2324405484
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.1425359295
Short name T833
Test name
Test status
Simulation time 238570357 ps
CPU time 25.68 seconds
Started Jun 21 06:29:53 PM PDT 24
Finished Jun 21 06:30:20 PM PDT 24
Peak memory 251048 kb
Host smart-dc08ea4c-a5c5-49a6-8d39-f21a08491fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425359295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1425359295
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.2272981562
Short name T247
Test name
Test status
Simulation time 408907962 ps
CPU time 4.04 seconds
Started Jun 21 06:30:03 PM PDT 24
Finished Jun 21 06:30:10 PM PDT 24
Peak memory 223024 kb
Host smart-ec09560b-d998-4cc8-812d-fd85f67596bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272981562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.2272981562
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.2613154940
Short name T841
Test name
Test status
Simulation time 5788895954 ps
CPU time 118.15 seconds
Started Jun 21 06:29:54 PM PDT 24
Finished Jun 21 06:31:53 PM PDT 24
Peak memory 275940 kb
Host smart-8d388b3c-eb6a-49ca-9f4d-f318663bba3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613154940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.2613154940
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.2832891397
Short name T626
Test name
Test status
Simulation time 46919761987 ps
CPU time 960.61 seconds
Started Jun 21 06:29:56 PM PDT 24
Finished Jun 21 06:45:59 PM PDT 24
Peak memory 372964 kb
Host smart-ad1f9b32-0237-4e1c-8aac-a1d4817b25ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2832891397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.2832891397
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3288337283
Short name T331
Test name
Test status
Simulation time 11893032 ps
CPU time 1.11 seconds
Started Jun 21 06:29:59 PM PDT 24
Finished Jun 21 06:30:03 PM PDT 24
Peak memory 211764 kb
Host smart-b4a5f4fb-c345-4fb7-83bf-458cd374e7e6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288337283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.3288337283
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1187648737
Short name T601
Test name
Test status
Simulation time 42622824 ps
CPU time 0.86 seconds
Started Jun 21 06:29:59 PM PDT 24
Finished Jun 21 06:30:03 PM PDT 24
Peak memory 208852 kb
Host smart-087f5b1a-4a53-4c7b-beb9-098b9fb297e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187648737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1187648737
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3556942145
Short name T156
Test name
Test status
Simulation time 1606473422 ps
CPU time 13.75 seconds
Started Jun 21 06:30:00 PM PDT 24
Finished Jun 21 06:30:16 PM PDT 24
Peak memory 218296 kb
Host smart-dccdfebc-3b5f-4345-8e00-6202eb3da2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556942145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3556942145
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1038395976
Short name T96
Test name
Test status
Simulation time 718232580 ps
CPU time 5.42 seconds
Started Jun 21 06:30:01 PM PDT 24
Finished Jun 21 06:30:10 PM PDT 24
Peak memory 217124 kb
Host smart-43c9928e-eb38-4990-976c-c0885be7fc7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038395976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1038395976
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2804405430
Short name T395
Test name
Test status
Simulation time 332599405 ps
CPU time 2.87 seconds
Started Jun 21 06:29:58 PM PDT 24
Finished Jun 21 06:30:03 PM PDT 24
Peak memory 218364 kb
Host smart-d473565a-2d9e-4074-8984-ce4ad13b57f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804405430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2804405430
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.3517050754
Short name T283
Test name
Test status
Simulation time 2106209986 ps
CPU time 20.17 seconds
Started Jun 21 06:29:58 PM PDT 24
Finished Jun 21 06:30:20 PM PDT 24
Peak memory 226216 kb
Host smart-8f4bdb70-4430-4a1a-8706-e3e85aa4f554
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517050754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3517050754
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1767115093
Short name T473
Test name
Test status
Simulation time 216149347 ps
CPU time 8.84 seconds
Started Jun 21 06:29:56 PM PDT 24
Finished Jun 21 06:30:06 PM PDT 24
Peak memory 218392 kb
Host smart-a25161a6-d670-487e-8dac-dcfcc2649abb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767115093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.1767115093
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.2211793083
Short name T445
Test name
Test status
Simulation time 1612698417 ps
CPU time 21.88 seconds
Started Jun 21 06:30:04 PM PDT 24
Finished Jun 21 06:30:29 PM PDT 24
Peak memory 225552 kb
Host smart-276e1831-64df-4156-a3f6-46e763147352
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211793083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
2211793083
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.78987279
Short name T368
Test name
Test status
Simulation time 1150856832 ps
CPU time 7.86 seconds
Started Jun 21 06:29:56 PM PDT 24
Finished Jun 21 06:30:05 PM PDT 24
Peak memory 224708 kb
Host smart-8c0cb18a-3dd5-4c26-b5d6-e350543a6a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78987279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.78987279
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.370292827
Short name T62
Test name
Test status
Simulation time 14280264 ps
CPU time 1.25 seconds
Started Jun 21 06:29:59 PM PDT 24
Finished Jun 21 06:30:03 PM PDT 24
Peak memory 212336 kb
Host smart-f065265c-b0d9-48fe-a84a-a39e1114389f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370292827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.370292827
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.3625096262
Short name T580
Test name
Test status
Simulation time 942705861 ps
CPU time 20.38 seconds
Started Jun 21 06:29:54 PM PDT 24
Finished Jun 21 06:30:16 PM PDT 24
Peak memory 251020 kb
Host smart-6b69caa0-ce51-4be2-b771-296fe0eb4616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625096262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3625096262
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.418859033
Short name T58
Test name
Test status
Simulation time 272178771 ps
CPU time 3.67 seconds
Started Jun 21 06:30:01 PM PDT 24
Finished Jun 21 06:30:07 PM PDT 24
Peak memory 222352 kb
Host smart-ddd4070f-84e2-409a-9be0-7fc0b7852798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418859033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.418859033
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3990876797
Short name T293
Test name
Test status
Simulation time 35492140990 ps
CPU time 237.91 seconds
Started Jun 21 06:30:00 PM PDT 24
Finished Jun 21 06:34:00 PM PDT 24
Peak memory 267420 kb
Host smart-f1915263-8011-4187-a852-21e30af575c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990876797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3990876797
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3904788642
Short name T500
Test name
Test status
Simulation time 35129316 ps
CPU time 0.9 seconds
Started Jun 21 06:29:58 PM PDT 24
Finished Jun 21 06:30:01 PM PDT 24
Peak memory 211944 kb
Host smart-b23d665c-75a7-4309-9cfa-b9fbdf723346
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904788642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3904788642
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.1266420933
Short name T154
Test name
Test status
Simulation time 15667678 ps
CPU time 1.08 seconds
Started Jun 21 06:29:56 PM PDT 24
Finished Jun 21 06:29:58 PM PDT 24
Peak memory 209012 kb
Host smart-788ac66a-c3dd-4845-86bd-4c5c63d54ff3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266420933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.1266420933
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.1478437469
Short name T726
Test name
Test status
Simulation time 461720126 ps
CPU time 18.99 seconds
Started Jun 21 06:30:01 PM PDT 24
Finished Jun 21 06:30:23 PM PDT 24
Peak memory 218300 kb
Host smart-96d872cc-1b62-4612-a7ce-f5414ad3c5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478437469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1478437469
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.3688420769
Short name T35
Test name
Test status
Simulation time 386703148 ps
CPU time 10.75 seconds
Started Jun 21 06:29:55 PM PDT 24
Finished Jun 21 06:30:08 PM PDT 24
Peak memory 217400 kb
Host smart-4bd754a6-0717-4935-b9e2-2528dc4afa7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688420769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.3688420769
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.4224559481
Short name T503
Test name
Test status
Simulation time 49935325 ps
CPU time 2.18 seconds
Started Jun 21 06:30:01 PM PDT 24
Finished Jun 21 06:30:07 PM PDT 24
Peak memory 222500 kb
Host smart-35216b07-81c0-4bae-a6b0-bd379b3f7489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224559481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.4224559481
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.3235598350
Short name T801
Test name
Test status
Simulation time 2645734096 ps
CPU time 13.72 seconds
Started Jun 21 06:30:02 PM PDT 24
Finished Jun 21 06:30:19 PM PDT 24
Peak memory 219400 kb
Host smart-50b49f30-5bce-4651-ab59-f42644e06a0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235598350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.3235598350
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1789422495
Short name T441
Test name
Test status
Simulation time 249911477 ps
CPU time 9.39 seconds
Started Jun 21 06:30:02 PM PDT 24
Finished Jun 21 06:30:15 PM PDT 24
Peak memory 218384 kb
Host smart-2c932a23-8060-442a-96fd-d8b9110296c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789422495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1789422495
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3562755008
Short name T289
Test name
Test status
Simulation time 1550813645 ps
CPU time 9.69 seconds
Started Jun 21 06:30:01 PM PDT 24
Finished Jun 21 06:30:13 PM PDT 24
Peak memory 218328 kb
Host smart-479f6976-2b9b-49b7-a0be-a88403798f7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562755008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3562755008
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.89250507
Short name T183
Test name
Test status
Simulation time 319439759 ps
CPU time 8.91 seconds
Started Jun 21 06:30:02 PM PDT 24
Finished Jun 21 06:30:14 PM PDT 24
Peak memory 218404 kb
Host smart-b12f9d1e-858e-44a5-b5b2-04a98c2311f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89250507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.89250507
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2117723927
Short name T431
Test name
Test status
Simulation time 48674738 ps
CPU time 1.45 seconds
Started Jun 21 06:30:03 PM PDT 24
Finished Jun 21 06:30:08 PM PDT 24
Peak memory 213992 kb
Host smart-9b0312c3-4b89-49d1-bb5b-1a7afc61024e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117723927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2117723927
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.370041466
Short name T84
Test name
Test status
Simulation time 209440518 ps
CPU time 21.19 seconds
Started Jun 21 06:30:02 PM PDT 24
Finished Jun 21 06:30:27 PM PDT 24
Peak memory 251024 kb
Host smart-820102e8-fd4d-444f-b217-3380ca77948c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370041466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.370041466
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.729125894
Short name T403
Test name
Test status
Simulation time 43853546 ps
CPU time 2.94 seconds
Started Jun 21 06:30:04 PM PDT 24
Finished Jun 21 06:30:10 PM PDT 24
Peak memory 226464 kb
Host smart-58dc9329-666f-4f01-a9ab-75fccff61abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729125894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.729125894
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.776124858
Short name T836
Test name
Test status
Simulation time 24631179984 ps
CPU time 416.42 seconds
Started Jun 21 06:30:04 PM PDT 24
Finished Jun 21 06:37:03 PM PDT 24
Peak memory 278976 kb
Host smart-894b6bd0-30e9-47fa-b312-242e5c619467
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776124858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.776124858
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2786283331
Short name T781
Test name
Test status
Simulation time 13386330 ps
CPU time 0.91 seconds
Started Jun 21 06:29:54 PM PDT 24
Finished Jun 21 06:29:57 PM PDT 24
Peak memory 211984 kb
Host smart-53b9e5fb-4f08-4639-a438-c48291d577e4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786283331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.2786283331
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.3616921229
Short name T74
Test name
Test status
Simulation time 29206326 ps
CPU time 0.89 seconds
Started Jun 21 06:28:55 PM PDT 24
Finished Jun 21 06:28:58 PM PDT 24
Peak memory 208852 kb
Host smart-ae11d549-cf2d-4310-9263-7a718b1d7cd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616921229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3616921229
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.390028701
Short name T398
Test name
Test status
Simulation time 22384750 ps
CPU time 0.82 seconds
Started Jun 21 06:29:00 PM PDT 24
Finished Jun 21 06:29:02 PM PDT 24
Peak memory 208968 kb
Host smart-c5f67d5b-b826-4cc0-99da-7191b2c7579c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390028701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.390028701
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2921894525
Short name T681
Test name
Test status
Simulation time 357935489 ps
CPU time 11.3 seconds
Started Jun 21 06:28:51 PM PDT 24
Finished Jun 21 06:29:03 PM PDT 24
Peak memory 218420 kb
Host smart-2d8e463b-f560-46d1-b983-47f682ff861d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921894525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2921894525
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.2644377377
Short name T452
Test name
Test status
Simulation time 340659571 ps
CPU time 9.33 seconds
Started Jun 21 06:28:56 PM PDT 24
Finished Jun 21 06:29:07 PM PDT 24
Peak memory 217496 kb
Host smart-0823b228-2fc9-423b-b503-ea73f384487e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644377377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.2644377377
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.1208838813
Short name T438
Test name
Test status
Simulation time 5271698928 ps
CPU time 67.89 seconds
Started Jun 21 06:29:03 PM PDT 24
Finished Jun 21 06:30:12 PM PDT 24
Peak memory 218776 kb
Host smart-a27a1630-a750-4d38-9e28-57a6af9f038c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208838813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.1208838813
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.3616352688
Short name T174
Test name
Test status
Simulation time 1390012140 ps
CPU time 8.81 seconds
Started Jun 21 06:28:54 PM PDT 24
Finished Jun 21 06:29:04 PM PDT 24
Peak memory 217872 kb
Host smart-a650e45e-2602-4ef8-8dfc-661d88b3c603
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616352688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.3
616352688
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1477085766
Short name T510
Test name
Test status
Simulation time 644691668 ps
CPU time 17.62 seconds
Started Jun 21 06:28:53 PM PDT 24
Finished Jun 21 06:29:12 PM PDT 24
Peak memory 218308 kb
Host smart-75be4ead-0548-4ace-b922-b39fb2d87272
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477085766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1477085766
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3639816095
Short name T78
Test name
Test status
Simulation time 4249842010 ps
CPU time 30.99 seconds
Started Jun 21 06:29:08 PM PDT 24
Finished Jun 21 06:29:42 PM PDT 24
Peak memory 217808 kb
Host smart-940dff1c-9d8f-4b42-bf11-d5cf15c7a69e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639816095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.3639816095
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2656272092
Short name T63
Test name
Test status
Simulation time 294830097 ps
CPU time 8.53 seconds
Started Jun 21 06:28:57 PM PDT 24
Finished Jun 21 06:29:08 PM PDT 24
Peak memory 217704 kb
Host smart-6d539dac-8bb7-482d-a47a-6278e3dc2c36
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656272092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2656272092
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1583122488
Short name T27
Test name
Test status
Simulation time 7859591562 ps
CPU time 69.57 seconds
Started Jun 21 06:28:54 PM PDT 24
Finished Jun 21 06:30:06 PM PDT 24
Peak memory 267408 kb
Host smart-c3760b4a-8282-460b-a777-64859848c164
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583122488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.1583122488
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.3850756519
Short name T644
Test name
Test status
Simulation time 881145065 ps
CPU time 25.25 seconds
Started Jun 21 06:28:57 PM PDT 24
Finished Jun 21 06:29:24 PM PDT 24
Peak memory 222980 kb
Host smart-29f3156c-2771-4fc1-b85b-67519bc6ec28
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850756519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.3850756519
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1057579716
Short name T40
Test name
Test status
Simulation time 139015029 ps
CPU time 2.37 seconds
Started Jun 21 06:28:54 PM PDT 24
Finished Jun 21 06:28:59 PM PDT 24
Peak memory 218348 kb
Host smart-8a7b9926-e956-4dd3-9ac2-318cef24718e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057579716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1057579716
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.2221273932
Short name T194
Test name
Test status
Simulation time 839602501 ps
CPU time 4.09 seconds
Started Jun 21 06:28:52 PM PDT 24
Finished Jun 21 06:28:57 PM PDT 24
Peak memory 217724 kb
Host smart-6694ae1b-090d-4e72-9764-84ed8bbbf42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221273932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.2221273932
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1344180312
Short name T100
Test name
Test status
Simulation time 116199600 ps
CPU time 21.84 seconds
Started Jun 21 06:28:52 PM PDT 24
Finished Jun 21 06:29:15 PM PDT 24
Peak memory 269168 kb
Host smart-e08d69f9-0461-4f41-a047-dfdff26e1998
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344180312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1344180312
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.3474050035
Short name T595
Test name
Test status
Simulation time 877589563 ps
CPU time 13.53 seconds
Started Jun 21 06:28:52 PM PDT 24
Finished Jun 21 06:29:07 PM PDT 24
Peak memory 219056 kb
Host smart-dee89607-f9e3-40cc-87f5-2cc4d6548562
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474050035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.3474050035
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3314296565
Short name T337
Test name
Test status
Simulation time 1572568237 ps
CPU time 8.6 seconds
Started Jun 21 06:28:53 PM PDT 24
Finished Jun 21 06:29:03 PM PDT 24
Peak memory 218388 kb
Host smart-d0865834-d4c7-43f0-9e21-041cc8d701fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314296565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.3314296565
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1519849037
Short name T264
Test name
Test status
Simulation time 1706645476 ps
CPU time 8.72 seconds
Started Jun 21 06:28:48 PM PDT 24
Finished Jun 21 06:28:58 PM PDT 24
Peak memory 218384 kb
Host smart-2f7b02bc-8c40-4f77-8983-45cfe05a5b0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519849037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
519849037
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.634690920
Short name T710
Test name
Test status
Simulation time 807677172 ps
CPU time 7.58 seconds
Started Jun 21 06:29:02 PM PDT 24
Finished Jun 21 06:29:11 PM PDT 24
Peak memory 225156 kb
Host smart-5a7af320-48ea-4bfb-b217-3af0d5562864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634690920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.634690920
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.3237475506
Short name T581
Test name
Test status
Simulation time 95600905 ps
CPU time 2.78 seconds
Started Jun 21 06:28:47 PM PDT 24
Finished Jun 21 06:28:51 PM PDT 24
Peak memory 217828 kb
Host smart-a56ed647-74fc-4886-9001-4b3a0905496a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237475506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3237475506
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3510638453
Short name T360
Test name
Test status
Simulation time 216020697 ps
CPU time 24.04 seconds
Started Jun 21 06:28:53 PM PDT 24
Finished Jun 21 06:29:19 PM PDT 24
Peak memory 251116 kb
Host smart-a296d2fa-256e-4e20-a99b-7dfe08dc0e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510638453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3510638453
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.489805207
Short name T656
Test name
Test status
Simulation time 49118893 ps
CPU time 3.25 seconds
Started Jun 21 06:28:53 PM PDT 24
Finished Jun 21 06:28:59 PM PDT 24
Peak memory 226480 kb
Host smart-59a8aad9-0d2b-4966-98bc-9fcbb6b64e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489805207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.489805207
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3545788989
Short name T69
Test name
Test status
Simulation time 30565040758 ps
CPU time 146.17 seconds
Started Jun 21 06:28:51 PM PDT 24
Finished Jun 21 06:31:18 PM PDT 24
Peak memory 251104 kb
Host smart-01b8a79f-63a4-4e71-9d7c-a44db569091d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545788989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3545788989
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.95296894
Short name T651
Test name
Test status
Simulation time 21129275 ps
CPU time 0.97 seconds
Started Jun 21 06:28:57 PM PDT 24
Finished Jun 21 06:29:00 PM PDT 24
Peak memory 211920 kb
Host smart-534719cd-ecf1-4a73-a8d7-b967139bcb11
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95296894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_volatile_unlock_smoke.95296894
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1479249356
Short name T759
Test name
Test status
Simulation time 12386701 ps
CPU time 0.87 seconds
Started Jun 21 06:30:09 PM PDT 24
Finished Jun 21 06:30:11 PM PDT 24
Peak memory 208804 kb
Host smart-914d3962-5026-4215-93b1-32af023bfd94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479249356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1479249356
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.721482298
Short name T794
Test name
Test status
Simulation time 1227057237 ps
CPU time 11.25 seconds
Started Jun 21 06:29:59 PM PDT 24
Finished Jun 21 06:30:12 PM PDT 24
Peak memory 218420 kb
Host smart-4854b7d6-56a0-4d17-a951-aa0791b36f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721482298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.721482298
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.2321028713
Short name T7
Test name
Test status
Simulation time 467053620 ps
CPU time 5.27 seconds
Started Jun 21 06:30:01 PM PDT 24
Finished Jun 21 06:30:10 PM PDT 24
Peak memory 217144 kb
Host smart-4b61e066-a3e8-4f9d-bec3-b0d18d0e0a9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321028713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.2321028713
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3267123135
Short name T724
Test name
Test status
Simulation time 192603289 ps
CPU time 4.93 seconds
Started Jun 21 06:30:04 PM PDT 24
Finished Jun 21 06:30:12 PM PDT 24
Peak memory 223004 kb
Host smart-e9b8b1e1-96aa-4ee7-8d79-204319b9be1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267123135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3267123135
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.2235615622
Short name T275
Test name
Test status
Simulation time 1850023451 ps
CPU time 18.41 seconds
Started Jun 21 06:30:02 PM PDT 24
Finished Jun 21 06:30:24 PM PDT 24
Peak memory 218404 kb
Host smart-1269c163-375e-4eec-807f-3b7769df7689
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235615622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.2235615622
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1827169854
Short name T433
Test name
Test status
Simulation time 405817923 ps
CPU time 15.83 seconds
Started Jun 21 06:30:04 PM PDT 24
Finished Jun 21 06:30:22 PM PDT 24
Peak memory 218392 kb
Host smart-8bf46651-cb61-412a-a280-804103b29933
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827169854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1827169854
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1382740690
Short name T857
Test name
Test status
Simulation time 173073343 ps
CPU time 7.44 seconds
Started Jun 21 06:30:05 PM PDT 24
Finished Jun 21 06:30:15 PM PDT 24
Peak memory 218464 kb
Host smart-a7918002-a7a6-4b7e-859b-f01257431841
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382740690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1382740690
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.709760185
Short name T396
Test name
Test status
Simulation time 335050830 ps
CPU time 6.04 seconds
Started Jun 21 06:30:04 PM PDT 24
Finished Jun 21 06:30:13 PM PDT 24
Peak memory 218440 kb
Host smart-7807951e-2262-43bf-bbfa-1da896349805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709760185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.709760185
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2652275381
Short name T67
Test name
Test status
Simulation time 361773570 ps
CPU time 6.02 seconds
Started Jun 21 06:30:02 PM PDT 24
Finished Jun 21 06:30:11 PM PDT 24
Peak memory 217808 kb
Host smart-592dd5cd-a191-4442-a43d-5f4cb02a945e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652275381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2652275381
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.4116989781
Short name T336
Test name
Test status
Simulation time 494978857 ps
CPU time 21.18 seconds
Started Jun 21 06:29:57 PM PDT 24
Finished Jun 21 06:30:19 PM PDT 24
Peak memory 251120 kb
Host smart-e922989e-47ef-40f9-948f-ab24159b8e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116989781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.4116989781
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3837580685
Short name T717
Test name
Test status
Simulation time 6052620218 ps
CPU time 70.07 seconds
Started Jun 21 06:30:11 PM PDT 24
Finished Jun 21 06:31:22 PM PDT 24
Peak memory 254368 kb
Host smart-6b3202c0-e4c4-4e55-9971-75a29b0f0ce6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837580685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3837580685
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3470029087
Short name T820
Test name
Test status
Simulation time 12502911 ps
CPU time 1.04 seconds
Started Jun 21 06:29:56 PM PDT 24
Finished Jun 21 06:29:59 PM PDT 24
Peak memory 211924 kb
Host smart-31addaa0-82b6-4458-b92f-99c029e59c00
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470029087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3470029087
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.2957987047
Short name T72
Test name
Test status
Simulation time 20756240 ps
CPU time 1.24 seconds
Started Jun 21 06:30:07 PM PDT 24
Finished Jun 21 06:30:10 PM PDT 24
Peak memory 208960 kb
Host smart-6e88a618-ec96-4314-92a0-784a8649d7e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957987047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.2957987047
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.378758796
Short name T647
Test name
Test status
Simulation time 120825469 ps
CPU time 3.87 seconds
Started Jun 21 06:30:02 PM PDT 24
Finished Jun 21 06:30:09 PM PDT 24
Peak memory 217120 kb
Host smart-b0f9aea7-d316-416d-a4aa-618f4d0411b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378758796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.378758796
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.2887363165
Short name T816
Test name
Test status
Simulation time 68880713 ps
CPU time 3.07 seconds
Started Jun 21 06:30:00 PM PDT 24
Finished Jun 21 06:30:06 PM PDT 24
Peak memory 218368 kb
Host smart-462537b6-1b64-46c6-8d91-6c1e9eb94290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887363165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.2887363165
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2543444482
Short name T383
Test name
Test status
Simulation time 1856620902 ps
CPU time 22.64 seconds
Started Jun 21 06:30:00 PM PDT 24
Finished Jun 21 06:30:25 PM PDT 24
Peak memory 226220 kb
Host smart-c7b0f664-9da6-40b2-beb6-394dbdba66e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543444482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2543444482
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2861832950
Short name T482
Test name
Test status
Simulation time 1016577562 ps
CPU time 18.98 seconds
Started Jun 21 06:30:01 PM PDT 24
Finished Jun 21 06:30:23 PM PDT 24
Peak memory 226172 kb
Host smart-2a8c9e6a-0cf6-4b4e-9f56-831c685ea5a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861832950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.2861832950
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.972037953
Short name T511
Test name
Test status
Simulation time 590530219 ps
CPU time 11.51 seconds
Started Jun 21 06:30:01 PM PDT 24
Finished Jun 21 06:30:16 PM PDT 24
Peak memory 218336 kb
Host smart-72753e7f-58ab-434d-9b3c-697079bb1a95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972037953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.972037953
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.4226170015
Short name T335
Test name
Test status
Simulation time 940185491 ps
CPU time 10.24 seconds
Started Jun 21 06:30:01 PM PDT 24
Finished Jun 21 06:30:14 PM PDT 24
Peak memory 226156 kb
Host smart-011b4825-c4da-42a3-b191-4a0f5742cf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226170015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.4226170015
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.4237859144
Short name T704
Test name
Test status
Simulation time 314032730 ps
CPU time 5.32 seconds
Started Jun 21 06:30:08 PM PDT 24
Finished Jun 21 06:30:15 PM PDT 24
Peak memory 217816 kb
Host smart-f89f204f-013a-4039-a5bb-d02a00302f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237859144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.4237859144
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.131974474
Short name T615
Test name
Test status
Simulation time 920061699 ps
CPU time 30.6 seconds
Started Jun 21 06:30:01 PM PDT 24
Finished Jun 21 06:30:34 PM PDT 24
Peak memory 251024 kb
Host smart-8508382c-c53c-4dc1-9f02-13220c618b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131974474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.131974474
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.4227047218
Short name T296
Test name
Test status
Simulation time 243063122 ps
CPU time 9.39 seconds
Started Jun 21 06:30:09 PM PDT 24
Finished Jun 21 06:30:20 PM PDT 24
Peak memory 251028 kb
Host smart-8332d061-c44f-40d5-8670-72fe3dfb2e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227047218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.4227047218
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.2589789644
Short name T21
Test name
Test status
Simulation time 3412748362 ps
CPU time 131.92 seconds
Started Jun 21 06:30:01 PM PDT 24
Finished Jun 21 06:32:16 PM PDT 24
Peak memory 269152 kb
Host smart-56534988-4f56-46a0-8611-3a91f131a2ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589789644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.2589789644
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1081919547
Short name T94
Test name
Test status
Simulation time 11804583 ps
CPU time 0.98 seconds
Started Jun 21 06:30:01 PM PDT 24
Finished Jun 21 06:30:05 PM PDT 24
Peak memory 211984 kb
Host smart-0c9c5c60-7043-4eba-97f2-206564114f4f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081919547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1081919547
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.2954267019
Short name T636
Test name
Test status
Simulation time 20955119 ps
CPU time 0.98 seconds
Started Jun 21 06:30:03 PM PDT 24
Finished Jun 21 06:30:07 PM PDT 24
Peak memory 209048 kb
Host smart-764904f5-1202-49a8-8589-be7649dbc18c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954267019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.2954267019
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.3368377792
Short name T506
Test name
Test status
Simulation time 567341691 ps
CPU time 10.97 seconds
Started Jun 21 06:30:07 PM PDT 24
Finished Jun 21 06:30:20 PM PDT 24
Peak memory 218348 kb
Host smart-5db7b19e-feff-4b26-8e31-53673881f607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368377792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3368377792
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.4226777130
Short name T460
Test name
Test status
Simulation time 12625569656 ps
CPU time 23.62 seconds
Started Jun 21 06:30:09 PM PDT 24
Finished Jun 21 06:30:33 PM PDT 24
Peak memory 217848 kb
Host smart-2db76076-16af-436d-956d-b32cb527535a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226777130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.4226777130
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3932258876
Short name T775
Test name
Test status
Simulation time 133970198 ps
CPU time 2.26 seconds
Started Jun 21 06:30:07 PM PDT 24
Finished Jun 21 06:30:11 PM PDT 24
Peak memory 218304 kb
Host smart-5198cb78-2bc4-48ae-ba6c-b36ca4037cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932258876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3932258876
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.2854487551
Short name T310
Test name
Test status
Simulation time 537785812 ps
CPU time 13.83 seconds
Started Jun 21 06:30:10 PM PDT 24
Finished Jun 21 06:30:25 PM PDT 24
Peak memory 218456 kb
Host smart-ccc278e2-22af-41cf-bb5b-b3ee138efb70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854487551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.2854487551
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.3101142546
Short name T504
Test name
Test status
Simulation time 354054299 ps
CPU time 14.04 seconds
Started Jun 21 06:30:06 PM PDT 24
Finished Jun 21 06:30:22 PM PDT 24
Peak memory 218344 kb
Host smart-243872eb-278b-4f6f-abe3-874448b2a616
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101142546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.3101142546
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.2801708094
Short name T860
Test name
Test status
Simulation time 1393651248 ps
CPU time 8.59 seconds
Started Jun 21 06:30:07 PM PDT 24
Finished Jun 21 06:30:17 PM PDT 24
Peak memory 218384 kb
Host smart-f3b7a167-a2ac-4a08-8143-9cbed677cdf2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801708094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
2801708094
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.519886241
Short name T845
Test name
Test status
Simulation time 635407653 ps
CPU time 7.19 seconds
Started Jun 21 06:30:01 PM PDT 24
Finished Jun 21 06:30:11 PM PDT 24
Peak memory 225104 kb
Host smart-05458227-5683-4d7b-85fb-7568a9ca46c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519886241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.519886241
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.2387239391
Short name T349
Test name
Test status
Simulation time 70425820 ps
CPU time 1.97 seconds
Started Jun 21 06:29:59 PM PDT 24
Finished Jun 21 06:30:03 PM PDT 24
Peak memory 214456 kb
Host smart-3a6f08cd-8f6e-4725-a03f-afe45827c295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387239391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2387239391
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3751436367
Short name T361
Test name
Test status
Simulation time 441492052 ps
CPU time 31.6 seconds
Started Jun 21 06:30:06 PM PDT 24
Finished Jun 21 06:30:40 PM PDT 24
Peak memory 251048 kb
Host smart-d33ba1cb-6545-42ad-bea0-5a984693599e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751436367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3751436367
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1002987412
Short name T166
Test name
Test status
Simulation time 74718439 ps
CPU time 6.75 seconds
Started Jun 21 06:30:05 PM PDT 24
Finished Jun 21 06:30:14 PM PDT 24
Peak memory 250520 kb
Host smart-102fa6ba-054e-435a-9347-e4f8f155251c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002987412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1002987412
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.2397054142
Short name T240
Test name
Test status
Simulation time 14518184109 ps
CPU time 72.48 seconds
Started Jun 21 06:30:00 PM PDT 24
Finished Jun 21 06:31:15 PM PDT 24
Peak memory 276940 kb
Host smart-ddf2e66a-bbc1-44d9-9655-63a72cfdc8aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397054142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.2397054142
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1761732718
Short name T579
Test name
Test status
Simulation time 22748869 ps
CPU time 1.01 seconds
Started Jun 21 06:30:00 PM PDT 24
Finished Jun 21 06:30:03 PM PDT 24
Peak memory 211888 kb
Host smart-f402ec69-bda2-4259-a7f3-2015aa1efe26
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761732718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1761732718
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3018123265
Short name T800
Test name
Test status
Simulation time 63646193 ps
CPU time 0.83 seconds
Started Jun 21 06:30:16 PM PDT 24
Finished Jun 21 06:30:19 PM PDT 24
Peak memory 209052 kb
Host smart-cb9d4b75-8ba6-4444-9165-98085493e1e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018123265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3018123265
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3953825674
Short name T576
Test name
Test status
Simulation time 5145427334 ps
CPU time 11.57 seconds
Started Jun 21 06:30:08 PM PDT 24
Finished Jun 21 06:30:21 PM PDT 24
Peak memory 218416 kb
Host smart-1870ebf9-1001-4d1e-8b40-962c1daa5f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953825674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3953825674
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.2150728272
Short name T703
Test name
Test status
Simulation time 2139195769 ps
CPU time 9.12 seconds
Started Jun 21 06:30:11 PM PDT 24
Finished Jun 21 06:30:21 PM PDT 24
Peak memory 216616 kb
Host smart-d19e709f-a764-4981-ad79-712fa9aff97a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150728272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.2150728272
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.172910858
Short name T373
Test name
Test status
Simulation time 80832123 ps
CPU time 2.51 seconds
Started Jun 21 06:30:01 PM PDT 24
Finished Jun 21 06:30:07 PM PDT 24
Peak memory 218312 kb
Host smart-ee0f6686-9ff0-4719-a19d-2d1dcf9348c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172910858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.172910858
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1768742280
Short name T419
Test name
Test status
Simulation time 1574260403 ps
CPU time 13.46 seconds
Started Jun 21 06:30:16 PM PDT 24
Finished Jun 21 06:30:31 PM PDT 24
Peak memory 226204 kb
Host smart-a8ee2471-7eb1-4b3a-8ee2-14296b28dbd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768742280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1768742280
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.4010540435
Short name T827
Test name
Test status
Simulation time 728366830 ps
CPU time 11.26 seconds
Started Jun 21 06:30:18 PM PDT 24
Finished Jun 21 06:30:32 PM PDT 24
Peak memory 218344 kb
Host smart-bd41e91e-6670-41bf-b813-e6e31fb56dd1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010540435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.4010540435
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3095142208
Short name T554
Test name
Test status
Simulation time 1747022286 ps
CPU time 7.94 seconds
Started Jun 21 06:30:11 PM PDT 24
Finished Jun 21 06:30:20 PM PDT 24
Peak memory 217380 kb
Host smart-57d738d4-3bc9-4e30-817b-705b57ebddec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095142208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3095142208
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.4062508690
Short name T865
Test name
Test status
Simulation time 543754476 ps
CPU time 9.28 seconds
Started Jun 21 06:30:04 PM PDT 24
Finished Jun 21 06:30:16 PM PDT 24
Peak memory 225784 kb
Host smart-5f7a4687-c653-44b0-9f06-b3d933f3c95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062508690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.4062508690
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.613402150
Short name T295
Test name
Test status
Simulation time 190479413 ps
CPU time 7.98 seconds
Started Jun 21 06:30:09 PM PDT 24
Finished Jun 21 06:30:18 PM PDT 24
Peak memory 217900 kb
Host smart-769ef332-e149-4124-b342-722156f1e71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613402150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.613402150
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2142261243
Short name T106
Test name
Test status
Simulation time 589320194 ps
CPU time 27.19 seconds
Started Jun 21 06:30:07 PM PDT 24
Finished Jun 21 06:30:35 PM PDT 24
Peak memory 251032 kb
Host smart-2321d3b0-731d-42ae-a1e3-780de7c62f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142261243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2142261243
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3466770738
Short name T92
Test name
Test status
Simulation time 237893828 ps
CPU time 7.11 seconds
Started Jun 21 06:30:11 PM PDT 24
Finished Jun 21 06:30:19 PM PDT 24
Peak memory 251048 kb
Host smart-141e8a68-1d99-41e0-9d5b-ca39028164f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466770738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3466770738
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.2202591415
Short name T718
Test name
Test status
Simulation time 20021387400 ps
CPU time 161.25 seconds
Started Jun 21 06:30:09 PM PDT 24
Finished Jun 21 06:32:52 PM PDT 24
Peak memory 251168 kb
Host smart-96bea387-c81f-4d72-aa02-5cb7b06061d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202591415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.2202591415
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2387280966
Short name T549
Test name
Test status
Simulation time 58442072 ps
CPU time 1.03 seconds
Started Jun 21 06:30:05 PM PDT 24
Finished Jun 21 06:30:08 PM PDT 24
Peak memory 213096 kb
Host smart-c9eedcf8-04f3-42ef-b1dc-8681f49bdeeb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387280966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.2387280966
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2474914086
Short name T672
Test name
Test status
Simulation time 31187701 ps
CPU time 1.06 seconds
Started Jun 21 06:30:11 PM PDT 24
Finished Jun 21 06:30:13 PM PDT 24
Peak memory 208952 kb
Host smart-b23d1410-17aa-42cf-864d-5a11b9a1fa16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474914086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2474914086
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.1940181798
Short name T578
Test name
Test status
Simulation time 470192172 ps
CPU time 16.8 seconds
Started Jun 21 06:30:20 PM PDT 24
Finished Jun 21 06:30:39 PM PDT 24
Peak memory 218420 kb
Host smart-81774acb-b91f-4ef9-95e3-3e2466a5fd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940181798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1940181798
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.3858385451
Short name T776
Test name
Test status
Simulation time 473975243 ps
CPU time 3.41 seconds
Started Jun 21 06:30:10 PM PDT 24
Finished Jun 21 06:30:15 PM PDT 24
Peak memory 217148 kb
Host smart-992182d1-bbaa-4b12-88a0-9218a7e8a699
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858385451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.3858385451
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.1664389068
Short name T476
Test name
Test status
Simulation time 155774182 ps
CPU time 1.99 seconds
Started Jun 21 06:30:16 PM PDT 24
Finished Jun 21 06:30:20 PM PDT 24
Peak memory 218348 kb
Host smart-d2bf2178-36b0-496b-844b-e55498f0e0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664389068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1664389068
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.1299444689
Short name T597
Test name
Test status
Simulation time 1262342755 ps
CPU time 18.4 seconds
Started Jun 21 06:30:19 PM PDT 24
Finished Jun 21 06:30:40 PM PDT 24
Peak memory 219068 kb
Host smart-06e309ad-5c54-4f35-97d4-4f6cd08d9a5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299444689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1299444689
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2776084121
Short name T762
Test name
Test status
Simulation time 1585939555 ps
CPU time 15.14 seconds
Started Jun 21 06:30:15 PM PDT 24
Finished Jun 21 06:30:33 PM PDT 24
Peak memory 218316 kb
Host smart-14889943-376d-4a57-8d49-db13fe6a626e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776084121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.2776084121
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3393417041
Short name T56
Test name
Test status
Simulation time 6419596184 ps
CPU time 10.71 seconds
Started Jun 21 06:30:15 PM PDT 24
Finished Jun 21 06:30:27 PM PDT 24
Peak memory 226356 kb
Host smart-7862ef79-5452-4c7f-b5f6-963a154ea240
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393417041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3393417041
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.867178373
Short name T854
Test name
Test status
Simulation time 1098635752 ps
CPU time 12.67 seconds
Started Jun 21 06:30:15 PM PDT 24
Finished Jun 21 06:30:36 PM PDT 24
Peak memory 218420 kb
Host smart-5dab631b-3b0a-4035-8490-45f9fdf8194e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867178373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.867178373
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.3753397258
Short name T712
Test name
Test status
Simulation time 514465980 ps
CPU time 3.62 seconds
Started Jun 21 06:30:11 PM PDT 24
Finished Jun 21 06:30:16 PM PDT 24
Peak memory 215196 kb
Host smart-06858cdd-d164-4037-b95b-875dbefc279f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753397258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3753397258
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1453097189
Short name T855
Test name
Test status
Simulation time 224076100 ps
CPU time 23.86 seconds
Started Jun 21 06:30:17 PM PDT 24
Finished Jun 21 06:30:43 PM PDT 24
Peak memory 251052 kb
Host smart-423a3386-cbf5-4294-8787-277cfa637512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453097189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1453097189
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.1822904563
Short name T38
Test name
Test status
Simulation time 477168337 ps
CPU time 9.95 seconds
Started Jun 21 06:30:18 PM PDT 24
Finished Jun 21 06:30:30 PM PDT 24
Peak memory 250976 kb
Host smart-c9888bed-e48a-4c0e-ade5-246339e20274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822904563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1822904563
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.2174182858
Short name T757
Test name
Test status
Simulation time 7499742921 ps
CPU time 51.27 seconds
Started Jun 21 06:30:15 PM PDT 24
Finished Jun 21 06:31:08 PM PDT 24
Peak memory 267868 kb
Host smart-67b16118-44aa-4f27-a0d6-3c0cd9ebf562
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174182858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.2174182858
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.654661755
Short name T588
Test name
Test status
Simulation time 40210159 ps
CPU time 0.82 seconds
Started Jun 21 06:30:19 PM PDT 24
Finished Jun 21 06:30:22 PM PDT 24
Peak memory 211792 kb
Host smart-71d292eb-f1d9-4461-9874-cf7072b787b9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654661755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ct
rl_volatile_unlock_smoke.654661755
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.3551112707
Short name T770
Test name
Test status
Simulation time 17391796 ps
CPU time 0.88 seconds
Started Jun 21 06:30:20 PM PDT 24
Finished Jun 21 06:30:23 PM PDT 24
Peak memory 208876 kb
Host smart-b77aed67-8461-4071-b303-4da13f0fa2a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551112707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3551112707
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3069913872
Short name T559
Test name
Test status
Simulation time 690790202 ps
CPU time 10.56 seconds
Started Jun 21 06:30:16 PM PDT 24
Finished Jun 21 06:30:29 PM PDT 24
Peak memory 218436 kb
Host smart-8591529a-d666-42e0-9f80-1ef10eff824a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069913872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3069913872
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.3558492887
Short name T499
Test name
Test status
Simulation time 3412263230 ps
CPU time 8.92 seconds
Started Jun 21 06:30:16 PM PDT 24
Finished Jun 21 06:30:27 PM PDT 24
Peak memory 217864 kb
Host smart-85281d78-4973-4600-9015-a221e0b12cd0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558492887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.3558492887
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.3964841138
Short name T642
Test name
Test status
Simulation time 50773639 ps
CPU time 2.8 seconds
Started Jun 21 06:30:06 PM PDT 24
Finished Jun 21 06:30:11 PM PDT 24
Peak memory 218364 kb
Host smart-9ff661bb-a0b8-410d-88ed-80496a278599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964841138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3964841138
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.591056100
Short name T746
Test name
Test status
Simulation time 1399647522 ps
CPU time 10.39 seconds
Started Jun 21 06:30:20 PM PDT 24
Finished Jun 21 06:30:33 PM PDT 24
Peak memory 226208 kb
Host smart-4d425b52-2c09-421d-9aea-03909afae81f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591056100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.591056100
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.2214849891
Short name T638
Test name
Test status
Simulation time 1086994112 ps
CPU time 14.39 seconds
Started Jun 21 06:30:10 PM PDT 24
Finished Jun 21 06:30:26 PM PDT 24
Peak memory 226204 kb
Host smart-604fc836-7ac8-4257-9b8a-96152d4398bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214849891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.2214849891
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.2786217154
Short name T722
Test name
Test status
Simulation time 1127691741 ps
CPU time 11.64 seconds
Started Jun 21 06:30:19 PM PDT 24
Finished Jun 21 06:30:33 PM PDT 24
Peak memory 218352 kb
Host smart-9d4bc703-d5e4-49d2-a24d-d3e6239a804b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786217154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
2786217154
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.2289850002
Short name T228
Test name
Test status
Simulation time 601974753 ps
CPU time 8 seconds
Started Jun 21 06:30:20 PM PDT 24
Finished Jun 21 06:30:31 PM PDT 24
Peak memory 225388 kb
Host smart-25038c53-10e4-466b-b5a5-4e3ab5e6eef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289850002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2289850002
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.1759654388
Short name T565
Test name
Test status
Simulation time 46704855 ps
CPU time 2.48 seconds
Started Jun 21 06:30:15 PM PDT 24
Finished Jun 21 06:30:20 PM PDT 24
Peak memory 217820 kb
Host smart-600ebe6b-e999-4b0f-a4c8-d6c163fd3516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759654388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1759654388
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.3695867478
Short name T392
Test name
Test status
Simulation time 1108242157 ps
CPU time 25.58 seconds
Started Jun 21 06:30:15 PM PDT 24
Finished Jun 21 06:30:42 PM PDT 24
Peak memory 251116 kb
Host smart-39487e7a-2e0d-4d07-9786-156a457a2981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695867478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3695867478
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.3180281817
Short name T379
Test name
Test status
Simulation time 67086186 ps
CPU time 6.6 seconds
Started Jun 21 06:30:09 PM PDT 24
Finished Jun 21 06:30:17 PM PDT 24
Peak memory 247056 kb
Host smart-938064bf-384d-4b73-9974-b091bfbd74b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180281817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.3180281817
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.1410217755
Short name T163
Test name
Test status
Simulation time 47973462757 ps
CPU time 188.18 seconds
Started Jun 21 06:30:15 PM PDT 24
Finished Jun 21 06:33:24 PM PDT 24
Peak memory 267600 kb
Host smart-293d4624-3379-4eaf-9710-99ad0d84242c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410217755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.1410217755
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2733817426
Short name T575
Test name
Test status
Simulation time 12602273 ps
CPU time 1.02 seconds
Started Jun 21 06:30:19 PM PDT 24
Finished Jun 21 06:30:22 PM PDT 24
Peak memory 211856 kb
Host smart-a005d791-803b-4295-93ea-0b4e9d2ea0fb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733817426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2733817426
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.2744658199
Short name T66
Test name
Test status
Simulation time 23320901 ps
CPU time 1.03 seconds
Started Jun 21 06:30:35 PM PDT 24
Finished Jun 21 06:30:38 PM PDT 24
Peak memory 208900 kb
Host smart-d5d5b3fc-b025-48ad-9de5-177586d1e253
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744658199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.2744658199
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.3732792169
Short name T299
Test name
Test status
Simulation time 1010034731 ps
CPU time 14.37 seconds
Started Jun 21 06:30:18 PM PDT 24
Finished Jun 21 06:30:35 PM PDT 24
Peak memory 218428 kb
Host smart-19be1e08-0ae8-419f-860a-1a25a14b36ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732792169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.3732792169
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3801579587
Short name T832
Test name
Test status
Simulation time 84968662 ps
CPU time 2.97 seconds
Started Jun 21 06:30:20 PM PDT 24
Finished Jun 21 06:30:25 PM PDT 24
Peak memory 217140 kb
Host smart-ab8a25a0-b630-4352-8f48-67f88e6fc139
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801579587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.3801579587
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.700275562
Short name T307
Test name
Test status
Simulation time 97152811 ps
CPU time 2.07 seconds
Started Jun 21 06:30:20 PM PDT 24
Finished Jun 21 06:30:24 PM PDT 24
Peak memory 218332 kb
Host smart-287467c8-003d-4e4f-8a3d-7a3722b3bb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700275562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.700275562
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.167138988
Short name T818
Test name
Test status
Simulation time 5114108278 ps
CPU time 13.22 seconds
Started Jun 21 06:30:17 PM PDT 24
Finished Jun 21 06:30:32 PM PDT 24
Peak memory 226252 kb
Host smart-509f5cb5-d426-416d-98a2-51a90dcb05ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167138988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.167138988
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3377384513
Short name T735
Test name
Test status
Simulation time 818116126 ps
CPU time 9.44 seconds
Started Jun 21 06:30:15 PM PDT 24
Finished Jun 21 06:30:26 PM PDT 24
Peak memory 218388 kb
Host smart-a4caf55b-42e4-4b89-a540-3d3c7eac4cab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377384513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.3377384513
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.1346267451
Short name T676
Test name
Test status
Simulation time 340986155 ps
CPU time 9.6 seconds
Started Jun 21 06:30:16 PM PDT 24
Finished Jun 21 06:30:27 PM PDT 24
Peak memory 218384 kb
Host smart-035a549c-5517-4669-adaf-ccfe1e28450b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346267451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
1346267451
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2291406969
Short name T529
Test name
Test status
Simulation time 51623423 ps
CPU time 4.03 seconds
Started Jun 21 06:30:20 PM PDT 24
Finished Jun 21 06:30:26 PM PDT 24
Peak memory 215208 kb
Host smart-61b44202-147c-4169-a400-a66f38749959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291406969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2291406969
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3026702633
Short name T257
Test name
Test status
Simulation time 229435345 ps
CPU time 23.3 seconds
Started Jun 21 06:30:16 PM PDT 24
Finished Jun 21 06:30:42 PM PDT 24
Peak memory 251076 kb
Host smart-37f0f56a-8f85-407c-8faf-1ab87fceacc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026702633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3026702633
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.2351817290
Short name T305
Test name
Test status
Simulation time 159006876 ps
CPU time 7.94 seconds
Started Jun 21 06:30:12 PM PDT 24
Finished Jun 21 06:30:21 PM PDT 24
Peak memory 243844 kb
Host smart-359e2451-dd61-43f2-ae4c-ba8acd95e9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351817290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2351817290
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.1391793762
Short name T326
Test name
Test status
Simulation time 6243132828 ps
CPU time 157.99 seconds
Started Jun 21 06:30:20 PM PDT 24
Finished Jun 21 06:33:01 PM PDT 24
Peak memory 251084 kb
Host smart-5a36bbb3-82e4-4915-9a78-3ce9bb2d9e64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391793762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.1391793762
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.1938352497
Short name T148
Test name
Test status
Simulation time 112082251306 ps
CPU time 849.94 seconds
Started Jun 21 06:30:17 PM PDT 24
Finished Jun 21 06:44:29 PM PDT 24
Peak memory 316692 kb
Host smart-fe86d389-d5e2-4ca5-8f91-9857f529cb75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1938352497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.1938352497
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.827590234
Short name T634
Test name
Test status
Simulation time 23221597 ps
CPU time 0.86 seconds
Started Jun 21 06:30:14 PM PDT 24
Finished Jun 21 06:30:16 PM PDT 24
Peak memory 212004 kb
Host smart-756b9837-3b12-46e3-85e2-dd8661b05522
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827590234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ct
rl_volatile_unlock_smoke.827590234
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3256204631
Short name T660
Test name
Test status
Simulation time 45247112 ps
CPU time 0.84 seconds
Started Jun 21 06:30:15 PM PDT 24
Finished Jun 21 06:30:17 PM PDT 24
Peak memory 208816 kb
Host smart-22dd3137-38e5-492e-892d-f27dbd8fa029
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256204631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3256204631
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.999213688
Short name T488
Test name
Test status
Simulation time 223681737 ps
CPU time 7.48 seconds
Started Jun 21 06:30:37 PM PDT 24
Finished Jun 21 06:30:47 PM PDT 24
Peak memory 218352 kb
Host smart-a11b7ae5-fc63-4811-9bd2-9901585491ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999213688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.999213688
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.1488201202
Short name T179
Test name
Test status
Simulation time 230787523 ps
CPU time 7.04 seconds
Started Jun 21 06:30:14 PM PDT 24
Finished Jun 21 06:30:22 PM PDT 24
Peak memory 217456 kb
Host smart-b3a6d836-34e8-4cce-9d2d-005eea96a396
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488201202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.1488201202
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.367572548
Short name T425
Test name
Test status
Simulation time 139966970 ps
CPU time 3.9 seconds
Started Jun 21 06:30:14 PM PDT 24
Finished Jun 21 06:30:19 PM PDT 24
Peak memory 222288 kb
Host smart-9787f319-6f4a-4893-a2b6-7bda52c198fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367572548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.367572548
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.552301571
Short name T535
Test name
Test status
Simulation time 1527867587 ps
CPU time 12.39 seconds
Started Jun 21 06:30:13 PM PDT 24
Finished Jun 21 06:30:27 PM PDT 24
Peak memory 219060 kb
Host smart-29ccdcf0-507d-4660-bcb4-69ccfa0f119c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552301571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.552301571
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.793595510
Short name T467
Test name
Test status
Simulation time 184729239 ps
CPU time 8.48 seconds
Started Jun 21 06:30:16 PM PDT 24
Finished Jun 21 06:30:27 PM PDT 24
Peak memory 226160 kb
Host smart-485d3659-3e66-419d-a9d7-621b2c767530
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793595510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_di
gest.793595510
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.1065022556
Short name T737
Test name
Test status
Simulation time 479859483 ps
CPU time 7.9 seconds
Started Jun 21 06:30:15 PM PDT 24
Finished Jun 21 06:30:26 PM PDT 24
Peak memory 218384 kb
Host smart-4ad59277-0111-4659-ac6f-790e1100f951
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065022556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
1065022556
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.386628988
Short name T566
Test name
Test status
Simulation time 711146110 ps
CPU time 12.99 seconds
Started Jun 21 06:30:36 PM PDT 24
Finished Jun 21 06:30:51 PM PDT 24
Peak memory 226220 kb
Host smart-38eab3a5-84ba-4643-ae3b-748a55f9d1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386628988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.386628988
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.3158899556
Short name T175
Test name
Test status
Simulation time 48306099 ps
CPU time 1.02 seconds
Started Jun 21 06:30:20 PM PDT 24
Finished Jun 21 06:30:23 PM PDT 24
Peak memory 217816 kb
Host smart-01640f3a-a13d-455c-a501-543939e072fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158899556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.3158899556
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3870524280
Short name T54
Test name
Test status
Simulation time 1004335741 ps
CPU time 31.11 seconds
Started Jun 21 06:30:18 PM PDT 24
Finished Jun 21 06:30:52 PM PDT 24
Peak memory 251120 kb
Host smart-b4fddacb-ce84-4ae6-ba66-756bded28685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870524280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3870524280
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.745207620
Short name T851
Test name
Test status
Simulation time 49294526 ps
CPU time 7.4 seconds
Started Jun 21 06:30:36 PM PDT 24
Finished Jun 21 06:30:46 PM PDT 24
Peak memory 251032 kb
Host smart-c89b32eb-82b5-4119-aa37-e50ff42e4fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745207620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.745207620
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.1828360328
Short name T569
Test name
Test status
Simulation time 6306261710 ps
CPU time 35.04 seconds
Started Jun 21 06:30:19 PM PDT 24
Finished Jun 21 06:30:56 PM PDT 24
Peak memory 245880 kb
Host smart-d88f1256-5b31-4ed0-8dcb-423d7cde6492
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828360328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.1828360328
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.3913758445
Short name T109
Test name
Test status
Simulation time 95936633736 ps
CPU time 839.77 seconds
Started Jun 21 06:30:14 PM PDT 24
Finished Jun 21 06:44:16 PM PDT 24
Peak memory 479880 kb
Host smart-9de532dd-4302-4a3d-9ece-ceaf4dac2ccf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3913758445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.3913758445
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.4222944514
Short name T343
Test name
Test status
Simulation time 18900921 ps
CPU time 1.06 seconds
Started Jun 21 06:30:16 PM PDT 24
Finished Jun 21 06:30:19 PM PDT 24
Peak memory 211892 kb
Host smart-fc5d9b35-c9e1-412c-9e49-3e7d1f47f1c0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222944514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.4222944514
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.1507698725
Short name T485
Test name
Test status
Simulation time 44097025 ps
CPU time 1.3 seconds
Started Jun 21 06:30:16 PM PDT 24
Finished Jun 21 06:30:20 PM PDT 24
Peak memory 208956 kb
Host smart-f5ce2f45-4f91-43af-9d90-a280c582aa30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507698725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1507698725
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2555986449
Short name T602
Test name
Test status
Simulation time 819646744 ps
CPU time 20.12 seconds
Started Jun 21 06:30:17 PM PDT 24
Finished Jun 21 06:30:39 PM PDT 24
Peak memory 218264 kb
Host smart-dad4a28d-e5c6-40ef-8c18-de2c55882ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555986449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2555986449
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1722177831
Short name T32
Test name
Test status
Simulation time 660661508 ps
CPU time 6.81 seconds
Started Jun 21 06:30:18 PM PDT 24
Finished Jun 21 06:30:27 PM PDT 24
Peak memory 217480 kb
Host smart-104c7744-c8d1-430a-848e-72a8f6792549
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722177831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.1722177831
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1707262450
Short name T276
Test name
Test status
Simulation time 749174176 ps
CPU time 3.18 seconds
Started Jun 21 06:30:15 PM PDT 24
Finished Jun 21 06:30:20 PM PDT 24
Peak memory 218380 kb
Host smart-db1211fd-5019-4056-a719-22767356957f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707262450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1707262450
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.833941124
Short name T583
Test name
Test status
Simulation time 272021283 ps
CPU time 9.35 seconds
Started Jun 21 06:30:40 PM PDT 24
Finished Jun 21 06:30:52 PM PDT 24
Peak memory 220108 kb
Host smart-5ff47859-7b66-4e9a-a354-36177c8b2138
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833941124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.833941124
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3601039061
Short name T497
Test name
Test status
Simulation time 1077267197 ps
CPU time 17.49 seconds
Started Jun 21 06:30:17 PM PDT 24
Finished Jun 21 06:30:37 PM PDT 24
Peak memory 226152 kb
Host smart-cb190a91-b2d5-4aab-84b8-21c3b7b46292
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601039061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.3601039061
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.2234138709
Short name T344
Test name
Test status
Simulation time 1493348387 ps
CPU time 8.3 seconds
Started Jun 21 06:30:20 PM PDT 24
Finished Jun 21 06:30:31 PM PDT 24
Peak memory 218376 kb
Host smart-8ff820be-6220-4a23-9b3c-8742c4c19bdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234138709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
2234138709
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.578197135
Short name T713
Test name
Test status
Simulation time 107628304 ps
CPU time 1.57 seconds
Started Jun 21 06:30:22 PM PDT 24
Finished Jun 21 06:30:26 PM PDT 24
Peak memory 214152 kb
Host smart-1b4b5542-691f-4606-b740-6ec8b2945e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578197135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.578197135
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3192136032
Short name T244
Test name
Test status
Simulation time 625558957 ps
CPU time 25.25 seconds
Started Jun 21 06:30:15 PM PDT 24
Finished Jun 21 06:30:42 PM PDT 24
Peak memory 251032 kb
Host smart-bd3d3bfd-c1ad-4116-b0af-c13655e81c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192136032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3192136032
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.1386384903
Short name T104
Test name
Test status
Simulation time 63202910 ps
CPU time 7.5 seconds
Started Jun 21 06:30:15 PM PDT 24
Finished Jun 21 06:30:24 PM PDT 24
Peak memory 250956 kb
Host smart-a0dda6b9-47c8-418b-829f-9c27c6f2c001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386384903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.1386384903
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.3220303414
Short name T561
Test name
Test status
Simulation time 29345554872 ps
CPU time 112.19 seconds
Started Jun 21 06:30:22 PM PDT 24
Finished Jun 21 06:32:17 PM PDT 24
Peak memory 274520 kb
Host smart-c5b706a6-fc09-4dae-91da-2921e0c0516c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3220303414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.3220303414
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2016800350
Short name T480
Test name
Test status
Simulation time 44575359 ps
CPU time 0.82 seconds
Started Jun 21 06:30:14 PM PDT 24
Finished Jun 21 06:30:16 PM PDT 24
Peak memory 212976 kb
Host smart-ea74b75f-f23f-4dc5-a648-8c34b479bbd8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016800350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.2016800350
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.4085959183
Short name T603
Test name
Test status
Simulation time 85907512 ps
CPU time 1.32 seconds
Started Jun 21 06:30:21 PM PDT 24
Finished Jun 21 06:30:25 PM PDT 24
Peak memory 208896 kb
Host smart-5cb7bf55-60b9-45ee-9407-fb9023b2d081
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085959183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.4085959183
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.1000399253
Short name T405
Test name
Test status
Simulation time 1521325348 ps
CPU time 8.82 seconds
Started Jun 21 06:30:27 PM PDT 24
Finished Jun 21 06:30:37 PM PDT 24
Peak memory 218368 kb
Host smart-809b9523-00c1-4cc7-b49d-396edbb012be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000399253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1000399253
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.44215587
Short name T423
Test name
Test status
Simulation time 1482433267 ps
CPU time 8.76 seconds
Started Jun 21 06:30:16 PM PDT 24
Finished Jun 21 06:30:27 PM PDT 24
Peak memory 217412 kb
Host smart-859bc713-c05c-4b2a-a8b7-05a58539cb50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44215587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.44215587
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.1357600357
Short name T306
Test name
Test status
Simulation time 288931284 ps
CPU time 3.38 seconds
Started Jun 21 06:30:14 PM PDT 24
Finished Jun 21 06:30:18 PM PDT 24
Peak memory 218344 kb
Host smart-c8acabd4-c9b2-4909-8aaa-5854b5555deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357600357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1357600357
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1231780392
Short name T748
Test name
Test status
Simulation time 1666962424 ps
CPU time 16.96 seconds
Started Jun 21 06:30:22 PM PDT 24
Finished Jun 21 06:30:42 PM PDT 24
Peak memory 225980 kb
Host smart-be9cf3b5-a569-4e68-936f-0c56028a4951
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231780392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1231780392
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.4258466621
Short name T248
Test name
Test status
Simulation time 282148954 ps
CPU time 13.27 seconds
Started Jun 21 06:30:24 PM PDT 24
Finished Jun 21 06:30:39 PM PDT 24
Peak memory 226200 kb
Host smart-4d2cdac2-6832-4bfa-bc3f-4fd2fbc12aba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258466621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.4258466621
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2985963599
Short name T358
Test name
Test status
Simulation time 1219906055 ps
CPU time 7.79 seconds
Started Jun 21 06:30:36 PM PDT 24
Finished Jun 21 06:30:45 PM PDT 24
Peak memory 218280 kb
Host smart-59105e65-69b3-4ca3-ac91-08efaa119189
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985963599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2985963599
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.2931722523
Short name T394
Test name
Test status
Simulation time 468555619 ps
CPU time 6.39 seconds
Started Jun 21 06:30:17 PM PDT 24
Finished Jun 21 06:30:31 PM PDT 24
Peak memory 224276 kb
Host smart-b0949a49-b03f-426e-a508-95785248f6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931722523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2931722523
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1758530441
Short name T83
Test name
Test status
Simulation time 52735621 ps
CPU time 1.59 seconds
Started Jun 21 06:30:37 PM PDT 24
Finished Jun 21 06:30:41 PM PDT 24
Peak memory 222140 kb
Host smart-b43fa868-a975-4de2-af21-5af542921378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758530441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1758530441
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.481170197
Short name T332
Test name
Test status
Simulation time 868432119 ps
CPU time 24.68 seconds
Started Jun 21 06:30:19 PM PDT 24
Finished Jun 21 06:30:46 PM PDT 24
Peak memory 251084 kb
Host smart-690a420d-d2a2-4989-b114-36d4779aeee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481170197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.481170197
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.1020796784
Short name T434
Test name
Test status
Simulation time 265355562 ps
CPU time 6.29 seconds
Started Jun 21 06:30:16 PM PDT 24
Finished Jun 21 06:30:25 PM PDT 24
Peak memory 246384 kb
Host smart-97b91336-2e75-4ab6-a1ed-c201a3d21acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020796784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.1020796784
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.3268048508
Short name T657
Test name
Test status
Simulation time 44698797294 ps
CPU time 273.14 seconds
Started Jun 21 06:30:29 PM PDT 24
Finished Jun 21 06:35:02 PM PDT 24
Peak memory 259456 kb
Host smart-df5ebe5a-3894-4aa0-8a1a-0632686dfa75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268048508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.3268048508
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.1910419920
Short name T159
Test name
Test status
Simulation time 539816155727 ps
CPU time 1477.62 seconds
Started Jun 21 06:30:27 PM PDT 24
Finished Jun 21 06:55:06 PM PDT 24
Peak memory 370292 kb
Host smart-125364ca-a919-47fa-802e-865e45b3f8e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1910419920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.1910419920
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.98649541
Short name T792
Test name
Test status
Simulation time 38215782 ps
CPU time 0.81 seconds
Started Jun 21 06:30:36 PM PDT 24
Finished Jun 21 06:30:40 PM PDT 24
Peak memory 212024 kb
Host smart-fa573339-ee65-467e-a16a-533582d84f4c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98649541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctr
l_volatile_unlock_smoke.98649541
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.3338653684
Short name T521
Test name
Test status
Simulation time 225363432 ps
CPU time 0.95 seconds
Started Jun 21 06:28:59 PM PDT 24
Finished Jun 21 06:29:01 PM PDT 24
Peak memory 208940 kb
Host smart-3f95c6fc-2c18-43e5-b0a2-e7dbf73e08ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338653684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3338653684
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.2006412556
Short name T544
Test name
Test status
Simulation time 450529840 ps
CPU time 14.15 seconds
Started Jun 21 06:28:58 PM PDT 24
Finished Jun 21 06:29:14 PM PDT 24
Peak memory 218412 kb
Host smart-9d0cc23b-ce19-4727-8d4c-147b9793d571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006412556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.2006412556
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1596202336
Short name T184
Test name
Test status
Simulation time 390541199 ps
CPU time 5.48 seconds
Started Jun 21 06:28:51 PM PDT 24
Finished Jun 21 06:28:58 PM PDT 24
Peak memory 217448 kb
Host smart-b1babd98-21e3-4746-991e-27bc3d86c330
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596202336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1596202336
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1707692174
Short name T377
Test name
Test status
Simulation time 1219653726 ps
CPU time 21.27 seconds
Started Jun 21 06:28:56 PM PDT 24
Finished Jun 21 06:29:19 PM PDT 24
Peak memory 225740 kb
Host smart-cc668a0b-3ac8-4f31-9813-7b3f1169e122
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707692174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1707692174
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2926034954
Short name T478
Test name
Test status
Simulation time 496561650 ps
CPU time 3.78 seconds
Started Jun 21 06:28:51 PM PDT 24
Finished Jun 21 06:28:56 PM PDT 24
Peak memory 217376 kb
Host smart-bb4d26e5-8eda-419f-b603-9782d3f2dc9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926034954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.2
926034954
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.38210212
Short name T265
Test name
Test status
Simulation time 278141125 ps
CPU time 9.79 seconds
Started Jun 21 06:28:54 PM PDT 24
Finished Jun 21 06:29:05 PM PDT 24
Peak memory 223344 kb
Host smart-60a2ea33-7122-48d0-ba97-8a227d0a4603
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38210212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_p
rog_failure.38210212
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2473448271
Short name T843
Test name
Test status
Simulation time 4170169554 ps
CPU time 18.48 seconds
Started Jun 21 06:29:12 PM PDT 24
Finished Jun 21 06:29:33 PM PDT 24
Peak memory 217808 kb
Host smart-ffa16201-3d46-489f-aae9-b9dd58aa412e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473448271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.2473448271
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.179511327
Short name T673
Test name
Test status
Simulation time 657234137 ps
CPU time 10.59 seconds
Started Jun 21 06:28:53 PM PDT 24
Finished Jun 21 06:29:06 PM PDT 24
Peak memory 217780 kb
Host smart-ff62b27c-281d-430e-bf04-c7809d6e5138
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179511327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.179511327
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3618759530
Short name T550
Test name
Test status
Simulation time 28346909625 ps
CPU time 62.03 seconds
Started Jun 21 06:28:54 PM PDT 24
Finished Jun 21 06:29:58 PM PDT 24
Peak memory 279956 kb
Host smart-d1af2000-2793-4674-91a0-9c651d8bcd0d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618759530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.3618759530
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1060377259
Short name T725
Test name
Test status
Simulation time 315215714 ps
CPU time 11.1 seconds
Started Jun 21 06:28:55 PM PDT 24
Finished Jun 21 06:29:08 PM PDT 24
Peak memory 247456 kb
Host smart-12e7a7c8-ca90-451d-9e20-44c462d95724
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060377259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1060377259
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.712578563
Short name T391
Test name
Test status
Simulation time 295216840 ps
CPU time 3.79 seconds
Started Jun 21 06:28:57 PM PDT 24
Finished Jun 21 06:29:03 PM PDT 24
Peak memory 218312 kb
Host smart-538cbbae-d402-4bf8-85e8-31dce2060ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712578563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.712578563
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1990653903
Short name T393
Test name
Test status
Simulation time 663194500 ps
CPU time 7.82 seconds
Started Jun 21 06:28:53 PM PDT 24
Finished Jun 21 06:29:03 PM PDT 24
Peak memory 217820 kb
Host smart-ed9e3d2e-f5e3-4bf6-a1c8-431c98ec5cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990653903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1990653903
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3304141278
Short name T87
Test name
Test status
Simulation time 449992380 ps
CPU time 24.58 seconds
Started Jun 21 06:29:12 PM PDT 24
Finished Jun 21 06:29:39 PM PDT 24
Peak memory 268608 kb
Host smart-4dc3dd57-3c78-4aab-b784-fa7ac649541b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304141278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3304141278
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.3067735650
Short name T517
Test name
Test status
Simulation time 1313814199 ps
CPU time 15.29 seconds
Started Jun 21 06:29:01 PM PDT 24
Finished Jun 21 06:29:18 PM PDT 24
Peak memory 226208 kb
Host smart-a5c8ae2f-ffd1-4697-9940-f3c96eb0e631
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067735650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.3067735650
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3090322538
Short name T669
Test name
Test status
Simulation time 887136810 ps
CPU time 11.94 seconds
Started Jun 21 06:28:58 PM PDT 24
Finished Jun 21 06:29:12 PM PDT 24
Peak memory 218276 kb
Host smart-eeab31f5-2ac5-4730-854d-e6677ab2d12a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090322538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.3090322538
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.3232202886
Short name T263
Test name
Test status
Simulation time 191930232 ps
CPU time 7.36 seconds
Started Jun 21 06:28:54 PM PDT 24
Finished Jun 21 06:29:04 PM PDT 24
Peak memory 218396 kb
Host smart-ec258bcf-fe06-4828-a01e-2701c21b19c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232202886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.3
232202886
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.4162964520
Short name T687
Test name
Test status
Simulation time 777835543 ps
CPU time 10.49 seconds
Started Jun 21 06:28:57 PM PDT 24
Finished Jun 21 06:29:10 PM PDT 24
Peak memory 225536 kb
Host smart-6a5a5381-7fe7-4c7f-ac64-5dd3cf45859c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162964520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.4162964520
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.2670527553
Short name T385
Test name
Test status
Simulation time 164339276 ps
CPU time 1.82 seconds
Started Jun 21 06:28:54 PM PDT 24
Finished Jun 21 06:28:58 PM PDT 24
Peak memory 217844 kb
Host smart-84c9bfdb-c7f2-4240-bba3-f29d22805725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670527553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.2670527553
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.3801596770
Short name T105
Test name
Test status
Simulation time 590247069 ps
CPU time 28.08 seconds
Started Jun 21 06:29:02 PM PDT 24
Finished Jun 21 06:29:32 PM PDT 24
Peak memory 251072 kb
Host smart-e4dcb221-ee69-4be2-9e6e-80c257710b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801596770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3801596770
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.2619767229
Short name T764
Test name
Test status
Simulation time 78051171 ps
CPU time 7.62 seconds
Started Jun 21 06:28:45 PM PDT 24
Finished Jun 21 06:28:54 PM PDT 24
Peak memory 250752 kb
Host smart-0452e7e4-8a65-4360-a312-1de2aa43c16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619767229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2619767229
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.1317417725
Short name T108
Test name
Test status
Simulation time 95359229999 ps
CPU time 151.57 seconds
Started Jun 21 06:28:55 PM PDT 24
Finished Jun 21 06:31:28 PM PDT 24
Peak memory 248212 kb
Host smart-ee5b56d6-72cb-4ecc-8a88-1f98cb5b35fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317417725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.1317417725
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.1188027201
Short name T140
Test name
Test status
Simulation time 36033715101 ps
CPU time 1361.31 seconds
Started Jun 21 06:28:54 PM PDT 24
Finished Jun 21 06:51:38 PM PDT 24
Peak memory 447836 kb
Host smart-4a6966c2-c4fe-459b-8e9a-78aa5223c6ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1188027201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.1188027201
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2055164329
Short name T489
Test name
Test status
Simulation time 16624316 ps
CPU time 0.93 seconds
Started Jun 21 06:28:54 PM PDT 24
Finished Jun 21 06:28:57 PM PDT 24
Peak memory 211884 kb
Host smart-233e5397-360e-49da-aa1b-ecc47e472461
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055164329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.2055164329
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.474258710
Short name T518
Test name
Test status
Simulation time 29470979 ps
CPU time 1.06 seconds
Started Jun 21 06:30:27 PM PDT 24
Finished Jun 21 06:30:29 PM PDT 24
Peak memory 208880 kb
Host smart-5eb42823-0cba-4bc6-a778-48afbd7f7544
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474258710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.474258710
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.610380539
Short name T346
Test name
Test status
Simulation time 281436501 ps
CPU time 10.86 seconds
Started Jun 21 06:30:21 PM PDT 24
Finished Jun 21 06:30:35 PM PDT 24
Peak memory 218336 kb
Host smart-fccd3c71-1311-449c-900c-4bc2da053b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610380539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.610380539
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.3221521234
Short name T413
Test name
Test status
Simulation time 269229417 ps
CPU time 4.35 seconds
Started Jun 21 06:30:33 PM PDT 24
Finished Jun 21 06:30:38 PM PDT 24
Peak memory 217312 kb
Host smart-f358b46d-c726-4836-a364-d42eab792730
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221521234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.3221521234
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.1318928379
Short name T173
Test name
Test status
Simulation time 23230907 ps
CPU time 1.63 seconds
Started Jun 21 06:30:37 PM PDT 24
Finished Jun 21 06:30:40 PM PDT 24
Peak memory 221904 kb
Host smart-3bf4f86b-ed5b-4985-9863-9ff562d2f4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318928379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1318928379
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1869877532
Short name T362
Test name
Test status
Simulation time 945136097 ps
CPU time 12.15 seconds
Started Jun 21 06:30:22 PM PDT 24
Finished Jun 21 06:30:37 PM PDT 24
Peak memory 226204 kb
Host smart-d28bee60-9c97-48c9-b18f-be56ec73d9ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869877532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1869877532
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2972786289
Short name T767
Test name
Test status
Simulation time 2601394445 ps
CPU time 8.92 seconds
Started Jun 21 06:30:25 PM PDT 24
Finished Jun 21 06:30:35 PM PDT 24
Peak memory 218456 kb
Host smart-ea5a484b-5b15-40bc-8b75-232cf6f71748
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972786289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2972786289
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.2608213557
Short name T771
Test name
Test status
Simulation time 3734564535 ps
CPU time 8.66 seconds
Started Jun 21 06:30:28 PM PDT 24
Finished Jun 21 06:30:38 PM PDT 24
Peak memory 226252 kb
Host smart-3103c90d-c33e-4537-9474-34177ead5b07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608213557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
2608213557
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.3211221604
Short name T714
Test name
Test status
Simulation time 612226363 ps
CPU time 12.32 seconds
Started Jun 21 06:30:28 PM PDT 24
Finished Jun 21 06:30:41 PM PDT 24
Peak memory 225276 kb
Host smart-4a02eef6-16e9-426d-a476-44a7acc7df95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211221604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3211221604
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.3125498432
Short name T322
Test name
Test status
Simulation time 114030364 ps
CPU time 3 seconds
Started Jun 21 06:30:21 PM PDT 24
Finished Jun 21 06:30:27 PM PDT 24
Peak memory 217856 kb
Host smart-152c5288-8994-4211-a4fa-e9c6004d0d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125498432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3125498432
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.2841274891
Short name T621
Test name
Test status
Simulation time 1234812374 ps
CPU time 34.15 seconds
Started Jun 21 06:30:30 PM PDT 24
Finished Jun 21 06:31:05 PM PDT 24
Peak memory 251020 kb
Host smart-98fb35b6-692b-4a9a-9bdc-3df5312733cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841274891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.2841274891
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2781995378
Short name T733
Test name
Test status
Simulation time 189542764 ps
CPU time 6.36 seconds
Started Jun 21 06:30:26 PM PDT 24
Finished Jun 21 06:30:34 PM PDT 24
Peak memory 250904 kb
Host smart-8b0a130a-2183-4160-b069-29912a2c567f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781995378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2781995378
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.133106981
Short name T81
Test name
Test status
Simulation time 1041481849 ps
CPU time 51.44 seconds
Started Jun 21 06:30:25 PM PDT 24
Finished Jun 21 06:31:17 PM PDT 24
Peak memory 251068 kb
Host smart-6b9bb354-8eba-4f10-9214-98ca0c4e7fac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133106981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.133106981
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.1932405847
Short name T142
Test name
Test status
Simulation time 361042401665 ps
CPU time 492.6 seconds
Started Jun 21 06:30:21 PM PDT 24
Finished Jun 21 06:38:36 PM PDT 24
Peak memory 546064 kb
Host smart-ae21d857-3bbc-4dda-950d-8a045f3bdd60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1932405847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.1932405847
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2928159057
Short name T233
Test name
Test status
Simulation time 21210210 ps
CPU time 0.93 seconds
Started Jun 21 06:30:35 PM PDT 24
Finished Jun 21 06:30:37 PM PDT 24
Peak memory 211972 kb
Host smart-334239f3-237f-4b15-b98c-7e4dfc468769
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928159057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.2928159057
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.1610199688
Short name T655
Test name
Test status
Simulation time 47384234 ps
CPU time 1 seconds
Started Jun 21 06:30:40 PM PDT 24
Finished Jun 21 06:30:44 PM PDT 24
Peak memory 208884 kb
Host smart-d46dca65-6c88-465f-ac22-842980fec5c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610199688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.1610199688
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.1024901644
Short name T274
Test name
Test status
Simulation time 1328830462 ps
CPU time 15.35 seconds
Started Jun 21 06:30:28 PM PDT 24
Finished Jun 21 06:30:44 PM PDT 24
Peak memory 218364 kb
Host smart-88679253-6b39-4a2f-b3ac-8582aff5d864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024901644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.1024901644
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3656515445
Short name T523
Test name
Test status
Simulation time 568269479 ps
CPU time 6.54 seconds
Started Jun 21 06:30:39 PM PDT 24
Finished Jun 21 06:30:48 PM PDT 24
Peak memory 217432 kb
Host smart-506f9a8e-6cc0-41e1-84e8-23b6f923d141
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656515445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.3656515445
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.858562807
Short name T370
Test name
Test status
Simulation time 79595925 ps
CPU time 2.31 seconds
Started Jun 21 06:30:21 PM PDT 24
Finished Jun 21 06:30:27 PM PDT 24
Peak memory 222652 kb
Host smart-59097503-6fdc-42f1-8fc7-426d25b12066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858562807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.858562807
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.810716019
Short name T632
Test name
Test status
Simulation time 493345645 ps
CPU time 13.89 seconds
Started Jun 21 06:30:26 PM PDT 24
Finished Jun 21 06:30:41 PM PDT 24
Peak memory 219056 kb
Host smart-52785b26-1104-4755-9781-77b7ce4f4bce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810716019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.810716019
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.4049661597
Short name T788
Test name
Test status
Simulation time 852560848 ps
CPU time 15.7 seconds
Started Jun 21 06:30:34 PM PDT 24
Finished Jun 21 06:30:51 PM PDT 24
Peak memory 218404 kb
Host smart-a44682e5-227e-495d-ae46-f53c61da3fdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049661597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.4049661597
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3569893840
Short name T837
Test name
Test status
Simulation time 373533233 ps
CPU time 14.44 seconds
Started Jun 21 06:30:21 PM PDT 24
Finished Jun 21 06:30:38 PM PDT 24
Peak memory 226136 kb
Host smart-70960d07-a9de-42de-acae-945281a7043f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569893840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3569893840
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.264182362
Short name T448
Test name
Test status
Simulation time 403423551 ps
CPU time 2.78 seconds
Started Jun 21 06:30:32 PM PDT 24
Finished Jun 21 06:30:36 PM PDT 24
Peak memory 214744 kb
Host smart-66034bcb-6990-44ee-9812-868612462848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264182362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.264182362
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.1384447118
Short name T400
Test name
Test status
Simulation time 250544641 ps
CPU time 28.84 seconds
Started Jun 21 06:30:21 PM PDT 24
Finished Jun 21 06:30:54 PM PDT 24
Peak memory 251032 kb
Host smart-e102adbe-7bfa-4948-a7f6-efc5b89fe261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384447118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1384447118
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3712602466
Short name T292
Test name
Test status
Simulation time 55913282 ps
CPU time 7.02 seconds
Started Jun 21 06:30:20 PM PDT 24
Finished Jun 21 06:30:30 PM PDT 24
Peak memory 251000 kb
Host smart-a2cace7d-b833-429b-b453-238ff89865e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712602466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3712602466
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.4151302261
Short name T755
Test name
Test status
Simulation time 2421159819 ps
CPU time 108.08 seconds
Started Jun 21 06:30:29 PM PDT 24
Finished Jun 21 06:32:17 PM PDT 24
Peak memory 273716 kb
Host smart-a27c04a6-d0bc-4bfe-821a-0e2e9651b0b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151302261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.4151302261
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1920371884
Short name T604
Test name
Test status
Simulation time 68799833 ps
CPU time 1.04 seconds
Started Jun 21 06:30:20 PM PDT 24
Finished Jun 21 06:30:24 PM PDT 24
Peak memory 217840 kb
Host smart-44751323-6f42-44f1-ad30-bdf40c57e5df
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920371884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1920371884
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.4180019867
Short name T187
Test name
Test status
Simulation time 17989130 ps
CPU time 1.15 seconds
Started Jun 21 06:30:37 PM PDT 24
Finished Jun 21 06:30:40 PM PDT 24
Peak memory 209036 kb
Host smart-b5a63363-a89d-4b1e-9665-f37542d90778
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180019867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.4180019867
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.707394933
Short name T436
Test name
Test status
Simulation time 239630388 ps
CPU time 10.92 seconds
Started Jun 21 06:30:37 PM PDT 24
Finished Jun 21 06:30:51 PM PDT 24
Peak memory 218352 kb
Host smart-8fcfae6e-6478-478f-87b4-dade019a10a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707394933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.707394933
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.2414854014
Short name T451
Test name
Test status
Simulation time 2439513421 ps
CPU time 7.49 seconds
Started Jun 21 06:30:37 PM PDT 24
Finished Jun 21 06:30:47 PM PDT 24
Peak memory 217712 kb
Host smart-b5b3e0c8-5581-4d49-a07b-7f21814d11f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414854014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.2414854014
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.3585940064
Short name T541
Test name
Test status
Simulation time 126993603 ps
CPU time 2.2 seconds
Started Jun 21 06:30:36 PM PDT 24
Finished Jun 21 06:30:40 PM PDT 24
Peak memory 218296 kb
Host smart-2db79e9e-a801-486b-becd-1ff7d648d7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585940064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.3585940064
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.2266694399
Short name T711
Test name
Test status
Simulation time 384879656 ps
CPU time 16.38 seconds
Started Jun 21 06:30:34 PM PDT 24
Finished Jun 21 06:30:51 PM PDT 24
Peak memory 219024 kb
Host smart-af6f6c10-17ed-4277-ae5f-0fc949629201
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266694399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.2266694399
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2725449175
Short name T266
Test name
Test status
Simulation time 849784378 ps
CPU time 8.84 seconds
Started Jun 21 06:30:37 PM PDT 24
Finished Jun 21 06:30:49 PM PDT 24
Peak memory 218340 kb
Host smart-bcb7c8e3-c753-4be7-9e4a-8577701c1cb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725449175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2725449175
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2083666481
Short name T468
Test name
Test status
Simulation time 325557439 ps
CPU time 9.32 seconds
Started Jun 21 06:30:39 PM PDT 24
Finished Jun 21 06:30:51 PM PDT 24
Peak memory 218400 kb
Host smart-a59cff14-8f03-4068-8267-e4b67b75c622
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083666481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
2083666481
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.576273837
Short name T386
Test name
Test status
Simulation time 971805397 ps
CPU time 11.4 seconds
Started Jun 21 06:30:28 PM PDT 24
Finished Jun 21 06:30:40 PM PDT 24
Peak memory 225244 kb
Host smart-a14dc996-3f7f-41b8-a33d-119a781559f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576273837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.576273837
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.3661763189
Short name T498
Test name
Test status
Simulation time 843946096 ps
CPU time 3.93 seconds
Started Jun 21 06:30:36 PM PDT 24
Finished Jun 21 06:30:41 PM PDT 24
Peak memory 217820 kb
Host smart-bd4bebbb-29e9-4e47-aa2e-6de4fbfc50e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661763189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.3661763189
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.1719778419
Short name T267
Test name
Test status
Simulation time 314388518 ps
CPU time 28.74 seconds
Started Jun 21 06:30:34 PM PDT 24
Finished Jun 21 06:31:03 PM PDT 24
Peak memory 251036 kb
Host smart-66ad902b-5284-4136-a244-18a49d600652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719778419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1719778419
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3882327660
Short name T493
Test name
Test status
Simulation time 229043359 ps
CPU time 3.7 seconds
Started Jun 21 06:30:37 PM PDT 24
Finished Jun 21 06:30:43 PM PDT 24
Peak memory 222528 kb
Host smart-07fd9966-06a7-4929-8f04-42d2518ce876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882327660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3882327660
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.1256584771
Short name T853
Test name
Test status
Simulation time 3001057812 ps
CPU time 43.9 seconds
Started Jun 21 06:30:37 PM PDT 24
Finished Jun 21 06:31:24 PM PDT 24
Peak memory 217892 kb
Host smart-49716740-5390-44d0-9d86-74fc18760d55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256584771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.1256584771
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.4070225610
Short name T840
Test name
Test status
Simulation time 15422011 ps
CPU time 0.95 seconds
Started Jun 21 06:30:35 PM PDT 24
Finished Jun 21 06:30:38 PM PDT 24
Peak memory 213108 kb
Host smart-0eba1fe6-c8e0-4049-8970-22b81e6b0db6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070225610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.4070225610
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.3629890876
Short name T829
Test name
Test status
Simulation time 17627490 ps
CPU time 0.88 seconds
Started Jun 21 06:30:38 PM PDT 24
Finished Jun 21 06:30:41 PM PDT 24
Peak memory 208800 kb
Host smart-779b7979-ab56-40c8-b180-ed59ac48eda5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629890876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.3629890876
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.3601241227
Short name T353
Test name
Test status
Simulation time 1257481845 ps
CPU time 11.37 seconds
Started Jun 21 06:30:40 PM PDT 24
Finished Jun 21 06:30:53 PM PDT 24
Peak memory 218308 kb
Host smart-b4811173-9d1a-4831-b32e-f1c1a45fd53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601241227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3601241227
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.1118290592
Short name T182
Test name
Test status
Simulation time 222295880 ps
CPU time 6.48 seconds
Started Jun 21 06:30:37 PM PDT 24
Finished Jun 21 06:30:46 PM PDT 24
Peak memory 217496 kb
Host smart-5e5d1997-5705-4fc5-8db9-2a619bd0ee99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118290592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.1118290592
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.1923583703
Short name T696
Test name
Test status
Simulation time 310080000 ps
CPU time 3.83 seconds
Started Jun 21 06:30:37 PM PDT 24
Finished Jun 21 06:30:43 PM PDT 24
Peak memory 218328 kb
Host smart-0664a361-647c-4983-bbdd-e21b26b845e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923583703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1923583703
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.1768405422
Short name T60
Test name
Test status
Simulation time 273112344 ps
CPU time 11.72 seconds
Started Jun 21 06:30:40 PM PDT 24
Finished Jun 21 06:30:55 PM PDT 24
Peak memory 218564 kb
Host smart-f94e6558-61f0-4acd-8164-de3c5af32edf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768405422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.1768405422
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1588345621
Short name T12
Test name
Test status
Simulation time 634794659 ps
CPU time 12.23 seconds
Started Jun 21 06:30:39 PM PDT 24
Finished Jun 21 06:30:54 PM PDT 24
Peak memory 218380 kb
Host smart-7f55e663-bcae-4963-a831-5a09ab18113f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588345621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.1588345621
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.3192926223
Short name T674
Test name
Test status
Simulation time 2761861070 ps
CPU time 13.5 seconds
Started Jun 21 06:30:37 PM PDT 24
Finished Jun 21 06:30:53 PM PDT 24
Peak memory 226252 kb
Host smart-7ae9d791-bf4f-47f8-8064-446c5f02f6ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192926223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
3192926223
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2892641074
Short name T742
Test name
Test status
Simulation time 180749101 ps
CPU time 6.86 seconds
Started Jun 21 06:30:29 PM PDT 24
Finished Jun 21 06:30:37 PM PDT 24
Peak memory 218408 kb
Host smart-93253a9c-abda-42d8-b178-36196d46508e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892641074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2892641074
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.3812481173
Short name T318
Test name
Test status
Simulation time 95651087 ps
CPU time 3.03 seconds
Started Jun 21 06:30:35 PM PDT 24
Finished Jun 21 06:30:39 PM PDT 24
Peak memory 217844 kb
Host smart-12ae0094-3ee0-4db8-97ed-43296fba8683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812481173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3812481173
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.2503550334
Short name T435
Test name
Test status
Simulation time 279296286 ps
CPU time 26.56 seconds
Started Jun 21 06:30:34 PM PDT 24
Finished Jun 21 06:31:02 PM PDT 24
Peak memory 251032 kb
Host smart-751b9b15-8747-4d1a-bf30-5b9d3f46947c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503550334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.2503550334
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.3187022907
Short name T366
Test name
Test status
Simulation time 266157192 ps
CPU time 7.16 seconds
Started Jun 21 06:30:40 PM PDT 24
Finished Jun 21 06:30:50 PM PDT 24
Peak memory 251012 kb
Host smart-72f4bb74-c9f7-45b1-91b2-2f4cb1f3a3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187022907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3187022907
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1084843293
Short name T107
Test name
Test status
Simulation time 11023984063 ps
CPU time 71.27 seconds
Started Jun 21 06:30:38 PM PDT 24
Finished Jun 21 06:31:52 PM PDT 24
Peak memory 247412 kb
Host smart-21bc59cc-c6e1-4560-8d83-db8dd56b1dfa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084843293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1084843293
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.566836945
Short name T844
Test name
Test status
Simulation time 23124406 ps
CPU time 0.88 seconds
Started Jun 21 06:30:41 PM PDT 24
Finished Jun 21 06:30:45 PM PDT 24
Peak memory 211916 kb
Host smart-2a7becf7-09eb-4297-aa47-6caca717f619
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566836945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ct
rl_volatile_unlock_smoke.566836945
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.3091887292
Short name T287
Test name
Test status
Simulation time 21255164 ps
CPU time 1.19 seconds
Started Jun 21 06:30:35 PM PDT 24
Finished Jun 21 06:30:37 PM PDT 24
Peak memory 208984 kb
Host smart-5930434e-85a6-4a2b-ad0d-c6c3876b42e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091887292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.3091887292
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2425498327
Short name T814
Test name
Test status
Simulation time 375744962 ps
CPU time 16.35 seconds
Started Jun 21 06:30:38 PM PDT 24
Finished Jun 21 06:30:57 PM PDT 24
Peak memory 218356 kb
Host smart-59c82e55-c5f5-487b-903f-4761141e2899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425498327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2425498327
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.499662403
Short name T388
Test name
Test status
Simulation time 2955260978 ps
CPU time 18.07 seconds
Started Jun 21 06:30:36 PM PDT 24
Finished Jun 21 06:30:56 PM PDT 24
Peak memory 217836 kb
Host smart-672209ab-aaae-4da8-90c7-99ca6e5e2cbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499662403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.499662403
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.268656263
Short name T330
Test name
Test status
Simulation time 56768054 ps
CPU time 1.6 seconds
Started Jun 21 06:30:35 PM PDT 24
Finished Jun 21 06:30:38 PM PDT 24
Peak memory 221724 kb
Host smart-f9bb8a1d-5230-4544-bb25-e735fb4da786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268656263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.268656263
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.4063114063
Short name T864
Test name
Test status
Simulation time 894753236 ps
CPU time 14.62 seconds
Started Jun 21 06:30:29 PM PDT 24
Finished Jun 21 06:30:45 PM PDT 24
Peak memory 219100 kb
Host smart-2cd91582-5ca6-47ec-ad14-052b931c319b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063114063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.4063114063
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2318330142
Short name T777
Test name
Test status
Simulation time 884685465 ps
CPU time 14.72 seconds
Started Jun 21 06:30:36 PM PDT 24
Finished Jun 21 06:30:53 PM PDT 24
Peak memory 218344 kb
Host smart-898dd3f4-25a8-46bb-8954-7cfd860baf89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318330142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2318330142
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1036647357
Short name T731
Test name
Test status
Simulation time 1129054426 ps
CPU time 8.16 seconds
Started Jun 21 06:30:32 PM PDT 24
Finished Jun 21 06:30:41 PM PDT 24
Peak memory 218360 kb
Host smart-1eb0ad64-6038-4ad5-b630-f6864cb55e12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036647357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1036647357
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.3716833491
Short name T91
Test name
Test status
Simulation time 2973529502 ps
CPU time 12.44 seconds
Started Jun 21 06:30:27 PM PDT 24
Finished Jun 21 06:30:40 PM PDT 24
Peak memory 218528 kb
Host smart-69a1f3a7-d9d5-4769-91de-5d300d30b43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716833491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.3716833491
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.2673828785
Short name T617
Test name
Test status
Simulation time 111409339 ps
CPU time 2.4 seconds
Started Jun 21 06:30:37 PM PDT 24
Finished Jun 21 06:30:42 PM PDT 24
Peak memory 217812 kb
Host smart-d47aae80-ca2a-43ef-ace7-db2bf76acb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673828785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2673828785
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3279061661
Short name T304
Test name
Test status
Simulation time 785772322 ps
CPU time 17.99 seconds
Started Jun 21 06:30:39 PM PDT 24
Finished Jun 21 06:30:59 PM PDT 24
Peak memory 251008 kb
Host smart-23e9dd2d-2a08-4f4a-9fda-61f0aca6d51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279061661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3279061661
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.1152140705
Short name T613
Test name
Test status
Simulation time 127184063 ps
CPU time 6.12 seconds
Started Jun 21 06:30:41 PM PDT 24
Finished Jun 21 06:30:50 PM PDT 24
Peak memory 247168 kb
Host smart-e81a31f4-201e-4983-8560-320825422e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152140705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.1152140705
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.3049753969
Short name T547
Test name
Test status
Simulation time 56014404840 ps
CPU time 340.71 seconds
Started Jun 21 06:30:40 PM PDT 24
Finished Jun 21 06:36:24 PM PDT 24
Peak memory 247908 kb
Host smart-a355cd80-715d-4e78-af0c-8768b53043f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049753969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.3049753969
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.3048367965
Short name T93
Test name
Test status
Simulation time 37665681376 ps
CPU time 1298.48 seconds
Started Jun 21 06:30:38 PM PDT 24
Finished Jun 21 06:52:19 PM PDT 24
Peak memory 528656 kb
Host smart-13329603-4375-4be9-b9c6-8f986bf1da08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3048367965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.3048367965
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3150157366
Short name T262
Test name
Test status
Simulation time 44070011 ps
CPU time 1.03 seconds
Started Jun 21 06:30:41 PM PDT 24
Finished Jun 21 06:30:44 PM PDT 24
Peak memory 211944 kb
Host smart-f3d8e958-e231-4491-ab21-9168d5bff73b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150157366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3150157366
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.1228877509
Short name T847
Test name
Test status
Simulation time 77053421 ps
CPU time 0.95 seconds
Started Jun 21 06:30:41 PM PDT 24
Finished Jun 21 06:30:45 PM PDT 24
Peak memory 209040 kb
Host smart-25528caa-a3f0-4ad1-a42e-2534cba5744e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228877509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.1228877509
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.3994738303
Short name T611
Test name
Test status
Simulation time 485822219 ps
CPU time 12.83 seconds
Started Jun 21 06:30:49 PM PDT 24
Finished Jun 21 06:31:03 PM PDT 24
Peak memory 218296 kb
Host smart-710b5fed-8feb-4d95-9c1d-c887f410e72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994738303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.3994738303
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.880982478
Short name T46
Test name
Test status
Simulation time 239369353 ps
CPU time 1.78 seconds
Started Jun 21 06:30:40 PM PDT 24
Finished Jun 21 06:30:45 PM PDT 24
Peak memory 217112 kb
Host smart-74a4a532-f812-42d2-9924-13faad9617e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880982478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.880982478
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2319475721
Short name T408
Test name
Test status
Simulation time 277909982 ps
CPU time 2.3 seconds
Started Jun 21 06:30:49 PM PDT 24
Finished Jun 21 06:30:53 PM PDT 24
Peak memory 222380 kb
Host smart-e4c83444-d1b2-425f-9a85-75efb9da9449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319475721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2319475721
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3333345636
Short name T661
Test name
Test status
Simulation time 365805419 ps
CPU time 10.92 seconds
Started Jun 21 06:30:43 PM PDT 24
Finished Jun 21 06:30:57 PM PDT 24
Peak memory 218364 kb
Host smart-a2493102-9ae5-46a9-96a9-e6cf29197d61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333345636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3333345636
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.4131445096
Short name T667
Test name
Test status
Simulation time 1224795698 ps
CPU time 12.97 seconds
Started Jun 21 06:30:48 PM PDT 24
Finished Jun 21 06:31:02 PM PDT 24
Peak memory 226148 kb
Host smart-90e48a74-3515-449d-844b-c9ad04a9e635
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131445096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
4131445096
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.4256947154
Short name T440
Test name
Test status
Simulation time 732037243 ps
CPU time 13.08 seconds
Started Jun 21 06:31:01 PM PDT 24
Finished Jun 21 06:31:15 PM PDT 24
Peak memory 226192 kb
Host smart-8a9492da-1164-4ae7-9e96-8bf5df066a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256947154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.4256947154
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.2831842158
Short name T808
Test name
Test status
Simulation time 19231170 ps
CPU time 1.73 seconds
Started Jun 21 06:30:37 PM PDT 24
Finished Jun 21 06:30:41 PM PDT 24
Peak memory 213972 kb
Host smart-b8f9f4a6-7538-4a4c-8e14-a82841c6cc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831842158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2831842158
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.4138758233
Short name T494
Test name
Test status
Simulation time 339847682 ps
CPU time 28.36 seconds
Started Jun 21 06:30:42 PM PDT 24
Finished Jun 21 06:31:13 PM PDT 24
Peak memory 251052 kb
Host smart-66c26d3d-6009-40f7-8b9a-f83b3a9a002c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138758233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.4138758233
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2793418834
Short name T381
Test name
Test status
Simulation time 148607928 ps
CPU time 6.47 seconds
Started Jun 21 06:30:43 PM PDT 24
Finished Jun 21 06:30:52 PM PDT 24
Peak memory 246568 kb
Host smart-3e88c058-6a95-418a-b1c2-15df37b60342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793418834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2793418834
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.71943435
Short name T572
Test name
Test status
Simulation time 49794484 ps
CPU time 0.93 seconds
Started Jun 21 06:30:46 PM PDT 24
Finished Jun 21 06:30:49 PM PDT 24
Peak memory 213028 kb
Host smart-11e87ae9-317a-4f40-b83f-1b85bf72761d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71943435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctr
l_volatile_unlock_smoke.71943435
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.4013759830
Short name T162
Test name
Test status
Simulation time 21700485 ps
CPU time 1.25 seconds
Started Jun 21 06:30:45 PM PDT 24
Finished Jun 21 06:30:48 PM PDT 24
Peak memory 208968 kb
Host smart-7a272c97-69c7-4843-8c10-ef35e38876d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013759830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.4013759830
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.3102734164
Short name T165
Test name
Test status
Simulation time 1188413020 ps
CPU time 8.79 seconds
Started Jun 21 06:30:40 PM PDT 24
Finished Jun 21 06:30:51 PM PDT 24
Peak memory 218396 kb
Host smart-68d6663b-add9-4043-934f-54f6824a61cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102734164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3102734164
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1367854072
Short name T37
Test name
Test status
Simulation time 713844622 ps
CPU time 1.68 seconds
Started Jun 21 06:30:38 PM PDT 24
Finished Jun 21 06:30:42 PM PDT 24
Peak memory 217160 kb
Host smart-8c789cb5-238c-46cd-bf27-02b55e07bdd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367854072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.1367854072
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.1580519819
Short name T415
Test name
Test status
Simulation time 108944343 ps
CPU time 1.46 seconds
Started Jun 21 06:30:43 PM PDT 24
Finished Jun 21 06:30:47 PM PDT 24
Peak memory 218320 kb
Host smart-11d480b6-6f49-4522-941c-a7be153fff7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580519819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1580519819
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.2146860512
Short name T185
Test name
Test status
Simulation time 188728914 ps
CPU time 8.27 seconds
Started Jun 21 06:30:46 PM PDT 24
Finished Jun 21 06:30:56 PM PDT 24
Peak memory 226192 kb
Host smart-1bf9dcaa-8c0c-420f-ac05-7a01ad7292af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146860512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.2146860512
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.2148102873
Short name T850
Test name
Test status
Simulation time 317303793 ps
CPU time 12.49 seconds
Started Jun 21 06:30:42 PM PDT 24
Finished Jun 21 06:30:57 PM PDT 24
Peak memory 218392 kb
Host smart-afb93269-7cdb-4721-8960-43c420b39249
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148102873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.2148102873
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3233132689
Short name T546
Test name
Test status
Simulation time 3807199614 ps
CPU time 12.2 seconds
Started Jun 21 06:30:48 PM PDT 24
Finished Jun 21 06:31:02 PM PDT 24
Peak memory 226248 kb
Host smart-d0d7bb83-01aa-44d3-a19c-0294c0951c89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233132689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3233132689
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.3126298670
Short name T53
Test name
Test status
Simulation time 3142141187 ps
CPU time 9.95 seconds
Started Jun 21 06:31:00 PM PDT 24
Finished Jun 21 06:31:11 PM PDT 24
Peak memory 226268 kb
Host smart-670cba22-17c0-479f-ba84-e43f175d4903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126298670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3126298670
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1122324086
Short name T695
Test name
Test status
Simulation time 74515596 ps
CPU time 3.42 seconds
Started Jun 21 06:30:46 PM PDT 24
Finished Jun 21 06:30:51 PM PDT 24
Peak memory 217812 kb
Host smart-a62e8d9b-94ee-4040-8108-eb72fa15a6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122324086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1122324086
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.385340312
Short name T98
Test name
Test status
Simulation time 155196624 ps
CPU time 26.79 seconds
Started Jun 21 06:30:41 PM PDT 24
Finished Jun 21 06:31:10 PM PDT 24
Peak memory 251024 kb
Host smart-30e8c326-0094-4278-bd80-9734049a82f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385340312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.385340312
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.1180614000
Short name T495
Test name
Test status
Simulation time 183816518 ps
CPU time 7.93 seconds
Started Jun 21 06:30:41 PM PDT 24
Finished Jun 21 06:30:52 PM PDT 24
Peak memory 250768 kb
Host smart-5c477987-e12a-4b25-aa8e-34073c6a6298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180614000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1180614000
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1501013363
Short name T753
Test name
Test status
Simulation time 4638883795 ps
CPU time 80.88 seconds
Started Jun 21 06:30:41 PM PDT 24
Finished Jun 21 06:32:04 PM PDT 24
Peak memory 246680 kb
Host smart-b74b0eff-3ffb-4a4f-9073-c08b431fe1be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501013363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1501013363
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3867750389
Short name T729
Test name
Test status
Simulation time 18815243 ps
CPU time 0.94 seconds
Started Jun 21 06:30:42 PM PDT 24
Finished Jun 21 06:30:45 PM PDT 24
Peak memory 211952 kb
Host smart-55117a7a-9b52-484f-96c8-114b3dba2a67
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867750389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3867750389
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.489914079
Short name T464
Test name
Test status
Simulation time 21988272 ps
CPU time 0.91 seconds
Started Jun 21 06:30:43 PM PDT 24
Finished Jun 21 06:30:46 PM PDT 24
Peak memory 208812 kb
Host smart-85d42053-4864-4311-b148-b100f4863172
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489914079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.489914079
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1903579768
Short name T42
Test name
Test status
Simulation time 1483961402 ps
CPU time 11.68 seconds
Started Jun 21 06:30:44 PM PDT 24
Finished Jun 21 06:30:58 PM PDT 24
Peak memory 218436 kb
Host smart-b14a04cd-a9ad-401f-870c-f8941aa1e43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903579768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1903579768
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3402376463
Short name T351
Test name
Test status
Simulation time 173417047 ps
CPU time 5.11 seconds
Started Jun 21 06:30:43 PM PDT 24
Finished Jun 21 06:30:51 PM PDT 24
Peak memory 217308 kb
Host smart-4fd05f0f-4989-438d-9ae2-9529d1ba2484
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402376463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3402376463
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2967263189
Short name T867
Test name
Test status
Simulation time 602388187 ps
CPU time 2.83 seconds
Started Jun 21 06:30:46 PM PDT 24
Finished Jun 21 06:30:51 PM PDT 24
Peak memory 218380 kb
Host smart-ade06c09-b560-4924-8bfe-8caa0a9e7b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967263189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2967263189
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.2802302153
Short name T44
Test name
Test status
Simulation time 910780845 ps
CPU time 12.42 seconds
Started Jun 21 06:30:42 PM PDT 24
Finished Jun 21 06:30:57 PM PDT 24
Peak memory 219056 kb
Host smart-177029e5-d4ed-4a72-9c54-66b87a6944fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802302153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.2802302153
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.2509902570
Short name T568
Test name
Test status
Simulation time 341671851 ps
CPU time 8.19 seconds
Started Jun 21 06:30:45 PM PDT 24
Finished Jun 21 06:30:56 PM PDT 24
Peak memory 226204 kb
Host smart-c75ea80d-aab3-43f1-bdb2-0b130a17ecae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509902570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.2509902570
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3727096284
Short name T449
Test name
Test status
Simulation time 830812788 ps
CPU time 7.51 seconds
Started Jun 21 06:30:42 PM PDT 24
Finished Jun 21 06:30:52 PM PDT 24
Peak memory 226192 kb
Host smart-1f525a9e-370f-417b-8c25-ec52d7a23d9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727096284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3727096284
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.1296074918
Short name T540
Test name
Test status
Simulation time 238550216 ps
CPU time 9.25 seconds
Started Jun 21 06:30:43 PM PDT 24
Finished Jun 21 06:30:55 PM PDT 24
Peak memory 226152 kb
Host smart-420c0d56-9ee8-43aa-a260-3c89dddc9021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296074918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.1296074918
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.524599144
Short name T779
Test name
Test status
Simulation time 134680656 ps
CPU time 3.49 seconds
Started Jun 21 06:30:50 PM PDT 24
Finished Jun 21 06:30:54 PM PDT 24
Peak memory 217816 kb
Host smart-5828eb3c-e837-48a1-a7cb-d2ea24590884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524599144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.524599144
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.643337904
Short name T721
Test name
Test status
Simulation time 542533870 ps
CPU time 21.24 seconds
Started Jun 21 06:30:43 PM PDT 24
Finished Jun 21 06:31:06 PM PDT 24
Peak memory 251048 kb
Host smart-f7321d40-d172-4c57-9245-b5c1b873b6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643337904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.643337904
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.1133634503
Short name T693
Test name
Test status
Simulation time 91718640 ps
CPU time 8.16 seconds
Started Jun 21 06:30:46 PM PDT 24
Finished Jun 21 06:30:56 PM PDT 24
Peak memory 250552 kb
Host smart-ae8e3348-3dff-4b9b-af4c-cd87a5330c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133634503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.1133634503
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.667921185
Short name T594
Test name
Test status
Simulation time 5049754418 ps
CPU time 124.85 seconds
Started Jun 21 06:30:48 PM PDT 24
Finished Jun 21 06:32:54 PM PDT 24
Peak memory 267484 kb
Host smart-7b4f4ba1-3bee-48c4-9fdb-910f107389ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667921185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.667921185
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.4047016937
Short name T143
Test name
Test status
Simulation time 34899585010 ps
CPU time 1027.56 seconds
Started Jun 21 06:30:49 PM PDT 24
Finished Jun 21 06:47:58 PM PDT 24
Peak memory 422208 kb
Host smart-6a46f969-4c73-430a-95c3-a7fcb4f32f52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4047016937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.4047016937
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.128538589
Short name T691
Test name
Test status
Simulation time 17064111 ps
CPU time 0.73 seconds
Started Jun 21 06:30:47 PM PDT 24
Finished Jun 21 06:30:49 PM PDT 24
Peak memory 207200 kb
Host smart-3253afe3-d8ea-45e2-8f32-108be382f881
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128538589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.128538589
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.902143949
Short name T838
Test name
Test status
Simulation time 18584037 ps
CPU time 0.93 seconds
Started Jun 21 06:30:43 PM PDT 24
Finished Jun 21 06:30:47 PM PDT 24
Peak memory 208964 kb
Host smart-e3fcb1ef-9c78-44c2-980a-9b17f8eb84b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902143949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.902143949
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.3031936212
Short name T745
Test name
Test status
Simulation time 745539301 ps
CPU time 25.87 seconds
Started Jun 21 06:30:43 PM PDT 24
Finished Jun 21 06:31:12 PM PDT 24
Peak memory 218352 kb
Host smart-230e4388-0515-4a38-ad23-09601347d232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031936212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3031936212
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.3182070727
Short name T645
Test name
Test status
Simulation time 1036986103 ps
CPU time 4.39 seconds
Started Jun 21 06:30:53 PM PDT 24
Finished Jun 21 06:30:59 PM PDT 24
Peak memory 217216 kb
Host smart-ac8283d2-24f1-4a1c-8331-172cc16cba9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182070727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.3182070727
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.3540006127
Short name T799
Test name
Test status
Simulation time 70002690 ps
CPU time 3.43 seconds
Started Jun 21 06:30:43 PM PDT 24
Finished Jun 21 06:30:49 PM PDT 24
Peak memory 218348 kb
Host smart-41bb09b0-17fd-41d5-8ff3-9e9ef10df22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540006127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3540006127
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.2602326868
Short name T728
Test name
Test status
Simulation time 1097287330 ps
CPU time 11.35 seconds
Started Jun 21 06:30:51 PM PDT 24
Finished Jun 21 06:31:04 PM PDT 24
Peak memory 218452 kb
Host smart-e9eae0ff-500c-498c-8401-563f19b85864
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602326868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2602326868
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.76663684
Short name T618
Test name
Test status
Simulation time 1175407439 ps
CPU time 20.91 seconds
Started Jun 21 06:30:52 PM PDT 24
Finished Jun 21 06:31:14 PM PDT 24
Peak memory 218388 kb
Host smart-a8822852-5908-47c9-8d12-fe4f0d993fdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76663684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_dig
est.76663684
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1840333898
Short name T57
Test name
Test status
Simulation time 1080044540 ps
CPU time 11.76 seconds
Started Jun 21 06:30:42 PM PDT 24
Finished Jun 21 06:30:56 PM PDT 24
Peak memory 218396 kb
Host smart-6a0106db-1933-44fb-806f-cdb72fa11793
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840333898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1840333898
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.864020091
Short name T49
Test name
Test status
Simulation time 261935794 ps
CPU time 6.94 seconds
Started Jun 21 06:30:40 PM PDT 24
Finished Jun 21 06:30:49 PM PDT 24
Peak memory 225144 kb
Host smart-6f974a55-275b-4c3a-9d9d-35af4b3d71e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864020091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.864020091
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.3085080867
Short name T348
Test name
Test status
Simulation time 52578378 ps
CPU time 2.64 seconds
Started Jun 21 06:30:45 PM PDT 24
Finished Jun 21 06:30:50 PM PDT 24
Peak memory 214784 kb
Host smart-890c25b4-bcf9-4671-aa70-159b822aeac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085080867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3085080867
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.798913325
Short name T612
Test name
Test status
Simulation time 223217979 ps
CPU time 14.69 seconds
Started Jun 21 06:30:47 PM PDT 24
Finished Jun 21 06:31:03 PM PDT 24
Peak memory 251020 kb
Host smart-ee167684-e429-41dd-ae63-086cd00ab4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798913325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.798913325
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.800588426
Short name T599
Test name
Test status
Simulation time 381659464 ps
CPU time 8.38 seconds
Started Jun 21 06:30:41 PM PDT 24
Finished Jun 21 06:30:52 PM PDT 24
Peak memory 247192 kb
Host smart-b479c6b6-2701-406e-90c0-64c3ea088596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800588426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.800588426
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.2901383007
Short name T732
Test name
Test status
Simulation time 8018806050 ps
CPU time 70.07 seconds
Started Jun 21 06:30:55 PM PDT 24
Finished Jun 21 06:32:06 PM PDT 24
Peak memory 251540 kb
Host smart-1fd5f9af-5332-432f-ac39-956a670236ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901383007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.2901383007
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3852063014
Short name T82
Test name
Test status
Simulation time 62531563 ps
CPU time 0.91 seconds
Started Jun 21 06:30:44 PM PDT 24
Finished Jun 21 06:30:47 PM PDT 24
Peak memory 213084 kb
Host smart-6d3899ea-5b86-4a27-b364-a7bdcabc4e6f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852063014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3852063014
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.3384675431
Short name T89
Test name
Test status
Simulation time 34075043 ps
CPU time 0.9 seconds
Started Jun 21 06:30:56 PM PDT 24
Finished Jun 21 06:30:58 PM PDT 24
Peak memory 208888 kb
Host smart-04f3d032-6363-4787-b9aa-0f4573798858
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384675431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3384675431
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2962712200
Short name T325
Test name
Test status
Simulation time 250948626 ps
CPU time 8.36 seconds
Started Jun 21 06:30:53 PM PDT 24
Finished Jun 21 06:31:03 PM PDT 24
Peak memory 218420 kb
Host smart-2f0097e1-336f-458b-aadb-d4e6f4365668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962712200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2962712200
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.535550729
Short name T169
Test name
Test status
Simulation time 323878857 ps
CPU time 4.44 seconds
Started Jun 21 06:30:47 PM PDT 24
Finished Jun 21 06:30:53 PM PDT 24
Peak memory 217172 kb
Host smart-714ec865-50c7-4cf2-8ca9-e6987776b5a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535550729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.535550729
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3024662230
Short name T321
Test name
Test status
Simulation time 299826115 ps
CPU time 3.01 seconds
Started Jun 21 06:30:54 PM PDT 24
Finished Jun 21 06:30:59 PM PDT 24
Peak memory 222788 kb
Host smart-94f0478d-1729-4323-afee-72443bc22130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024662230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3024662230
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.4142702573
Short name T528
Test name
Test status
Simulation time 2510017255 ps
CPU time 13.15 seconds
Started Jun 21 06:30:49 PM PDT 24
Finished Jun 21 06:31:03 PM PDT 24
Peak memory 226264 kb
Host smart-485886c4-abc1-44f5-aa23-0b45920b6740
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142702573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.4142702573
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.3648825334
Short name T591
Test name
Test status
Simulation time 2119629442 ps
CPU time 7.21 seconds
Started Jun 21 06:30:48 PM PDT 24
Finished Jun 21 06:30:56 PM PDT 24
Peak memory 218316 kb
Host smart-e45147ba-d4cb-4eda-99d0-431652775945
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648825334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.3648825334
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2913035605
Short name T329
Test name
Test status
Simulation time 1497017266 ps
CPU time 10.16 seconds
Started Jun 21 06:30:53 PM PDT 24
Finished Jun 21 06:31:05 PM PDT 24
Peak memory 226188 kb
Host smart-e816bfac-9ec0-4924-9414-6bf1c370a45d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913035605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2913035605
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.1694653318
Short name T479
Test name
Test status
Simulation time 1062873482 ps
CPU time 10.83 seconds
Started Jun 21 06:30:55 PM PDT 24
Finished Jun 21 06:31:07 PM PDT 24
Peak memory 218424 kb
Host smart-112f5335-ec45-4150-8529-82f74c4f9756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694653318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.1694653318
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.2793969734
Short name T364
Test name
Test status
Simulation time 267791730 ps
CPU time 14.28 seconds
Started Jun 21 06:30:46 PM PDT 24
Finished Jun 21 06:31:02 PM PDT 24
Peak memory 217808 kb
Host smart-d85ddad0-8ca7-4919-bd30-66dd33e39e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793969734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.2793969734
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.3905628
Short name T509
Test name
Test status
Simulation time 817030901 ps
CPU time 36.13 seconds
Started Jun 21 06:30:53 PM PDT 24
Finished Jun 21 06:31:31 PM PDT 24
Peak memory 251024 kb
Host smart-388f3d76-5934-4050-9404-4fa41c2f7e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3905628
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.3318586125
Short name T795
Test name
Test status
Simulation time 67199799 ps
CPU time 5.79 seconds
Started Jun 21 06:30:52 PM PDT 24
Finished Jun 21 06:30:59 PM PDT 24
Peak memory 247188 kb
Host smart-d8453645-c6f5-4b4c-8403-bfc7b3b4eee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318586125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3318586125
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.717164249
Short name T286
Test name
Test status
Simulation time 6420256171 ps
CPU time 109.11 seconds
Started Jun 21 06:30:57 PM PDT 24
Finished Jun 21 06:32:48 PM PDT 24
Peak memory 282188 kb
Host smart-98d9ad00-b8d5-412f-b6db-20b9b11e281c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717164249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.717164249
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3859065352
Short name T828
Test name
Test status
Simulation time 11624637 ps
CPU time 1.02 seconds
Started Jun 21 06:30:49 PM PDT 24
Finished Jun 21 06:30:51 PM PDT 24
Peak memory 211908 kb
Host smart-3e1c2220-a87f-4d7b-8b6e-cd07ee6f8758
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859065352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.3859065352
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.2608886215
Short name T699
Test name
Test status
Simulation time 86030481 ps
CPU time 1 seconds
Started Jun 21 06:29:08 PM PDT 24
Finished Jun 21 06:29:11 PM PDT 24
Peak memory 208900 kb
Host smart-7e7fb94a-c917-4f89-8766-ecf11f0f67d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608886215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.2608886215
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2307345144
Short name T378
Test name
Test status
Simulation time 84206363 ps
CPU time 0.91 seconds
Started Jun 21 06:29:09 PM PDT 24
Finished Jun 21 06:29:12 PM PDT 24
Peak memory 209096 kb
Host smart-c0f15e7a-e8ee-4da8-a2a0-1fdf520a2d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307345144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2307345144
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.2538193614
Short name T751
Test name
Test status
Simulation time 3727501202 ps
CPU time 13.56 seconds
Started Jun 21 06:29:00 PM PDT 24
Finished Jun 21 06:29:15 PM PDT 24
Peak memory 219116 kb
Host smart-2fcc7177-b95f-4fcd-b2e3-b3e22806e9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538193614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.2538193614
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3101648274
Short name T412
Test name
Test status
Simulation time 945145282 ps
CPU time 12.22 seconds
Started Jun 21 06:29:15 PM PDT 24
Finished Jun 21 06:29:28 PM PDT 24
Peak memory 217620 kb
Host smart-eb68ad63-7371-42a6-8715-909b9ce2f6a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101648274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3101648274
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1709123295
Short name T399
Test name
Test status
Simulation time 2128595541 ps
CPU time 38.55 seconds
Started Jun 21 06:29:07 PM PDT 24
Finished Jun 21 06:29:48 PM PDT 24
Peak memory 226152 kb
Host smart-50189145-149c-4312-a9bd-e939215f0220
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709123295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1709123295
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.1303657112
Short name T623
Test name
Test status
Simulation time 295439706 ps
CPU time 7.89 seconds
Started Jun 21 06:29:10 PM PDT 24
Finished Jun 21 06:29:21 PM PDT 24
Peak memory 217648 kb
Host smart-84406db8-b968-4206-839c-1463a3799ec7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303657112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.1
303657112
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.2011872468
Short name T245
Test name
Test status
Simulation time 804671596 ps
CPU time 23.04 seconds
Started Jun 21 06:29:06 PM PDT 24
Finished Jun 21 06:29:30 PM PDT 24
Peak memory 225648 kb
Host smart-d45d9361-1b7b-4f44-9800-bc0cdc0484d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011872468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.2011872468
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1185113314
Short name T462
Test name
Test status
Simulation time 1128067892 ps
CPU time 15.92 seconds
Started Jun 21 06:29:05 PM PDT 24
Finished Jun 21 06:29:21 PM PDT 24
Peak memory 217760 kb
Host smart-78840ecd-efb4-452e-b1a3-9de694544c6d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185113314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.1185113314
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.215550716
Short name T76
Test name
Test status
Simulation time 135776054 ps
CPU time 3.8 seconds
Started Jun 21 06:29:01 PM PDT 24
Finished Jun 21 06:29:07 PM PDT 24
Peak memory 217768 kb
Host smart-6fc69da6-84b1-4a06-a855-9abda99a27ff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215550716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.215550716
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.492733943
Short name T357
Test name
Test status
Simulation time 3061572331 ps
CPU time 60.84 seconds
Started Jun 21 06:29:01 PM PDT 24
Finished Jun 21 06:30:03 PM PDT 24
Peak memory 282724 kb
Host smart-70cb5b04-4a2b-4e78-9dde-56658bc32553
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492733943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_state_failure.492733943
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3103059412
Short name T250
Test name
Test status
Simulation time 1585509280 ps
CPU time 8.86 seconds
Started Jun 21 06:29:01 PM PDT 24
Finished Jun 21 06:29:12 PM PDT 24
Peak memory 226344 kb
Host smart-5ca17ad9-2841-4951-87d0-c25bf0accb53
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103059412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.3103059412
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.120690880
Short name T48
Test name
Test status
Simulation time 68584985 ps
CPU time 2.61 seconds
Started Jun 21 06:29:00 PM PDT 24
Finished Jun 21 06:29:03 PM PDT 24
Peak memory 218336 kb
Host smart-58b7a796-b290-49da-817a-397060ce1e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120690880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.120690880
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.4279065134
Short name T192
Test name
Test status
Simulation time 1505458182 ps
CPU time 8.43 seconds
Started Jun 21 06:28:59 PM PDT 24
Finished Jun 21 06:29:09 PM PDT 24
Peak memory 217796 kb
Host smart-c2f0c9b1-17f2-4f5f-8f89-542ef9fd3b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279065134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.4279065134
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.597570242
Short name T589
Test name
Test status
Simulation time 480615901 ps
CPU time 11.73 seconds
Started Jun 21 06:28:57 PM PDT 24
Finished Jun 21 06:29:10 PM PDT 24
Peak memory 226296 kb
Host smart-a73aecc8-ee05-44cd-9e74-1e280e99c7e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597570242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.597570242
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2992099259
Short name T545
Test name
Test status
Simulation time 1144469253 ps
CPU time 6.97 seconds
Started Jun 21 06:29:08 PM PDT 24
Finished Jun 21 06:29:17 PM PDT 24
Peak memory 218388 kb
Host smart-2f284003-6b15-422f-a3f4-a46e2aebb01b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992099259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.2992099259
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3190906300
Short name T842
Test name
Test status
Simulation time 288079470 ps
CPU time 10.68 seconds
Started Jun 21 06:29:06 PM PDT 24
Finished Jun 21 06:29:17 PM PDT 24
Peak memory 218384 kb
Host smart-d52c1110-fa9c-4b68-b48a-18a84454a499
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190906300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
190906300
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.3874181477
Short name T50
Test name
Test status
Simulation time 1365821029 ps
CPU time 10.5 seconds
Started Jun 21 06:28:52 PM PDT 24
Finished Jun 21 06:29:04 PM PDT 24
Peak memory 225144 kb
Host smart-937b1252-c72c-4e14-af67-cc03b1ff4da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874181477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.3874181477
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.71525990
Short name T414
Test name
Test status
Simulation time 28522695 ps
CPU time 1.91 seconds
Started Jun 21 06:28:55 PM PDT 24
Finished Jun 21 06:28:59 PM PDT 24
Peak memory 217768 kb
Host smart-fe0592a3-efdb-4a1d-8239-f5b6a368921f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71525990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.71525990
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.234989840
Short name T155
Test name
Test status
Simulation time 851993349 ps
CPU time 29.2 seconds
Started Jun 21 06:29:02 PM PDT 24
Finished Jun 21 06:29:33 PM PDT 24
Peak memory 251020 kb
Host smart-877ccb9e-3ccb-4e92-bcc6-ec0bfd1f350d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234989840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.234989840
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.4012105017
Short name T723
Test name
Test status
Simulation time 68379944 ps
CPU time 8.12 seconds
Started Jun 21 06:29:07 PM PDT 24
Finished Jun 21 06:29:17 PM PDT 24
Peak memory 250956 kb
Host smart-8ecf8a3f-73f4-49c0-9843-0ebce3da9e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012105017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.4012105017
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1411253878
Short name T20
Test name
Test status
Simulation time 44187998489 ps
CPU time 213.38 seconds
Started Jun 21 06:29:14 PM PDT 24
Finished Jun 21 06:32:49 PM PDT 24
Peak memory 422016 kb
Host smart-39699ee5-cde3-4482-a558-3b105d4cf279
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411253878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1411253878
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1589335164
Short name T648
Test name
Test status
Simulation time 35068504 ps
CPU time 0.85 seconds
Started Jun 21 06:28:57 PM PDT 24
Finished Jun 21 06:28:59 PM PDT 24
Peak memory 212028 kb
Host smart-4e459e85-5e8a-48a9-ad82-dff2e6a4fe79
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589335164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.1589335164
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.247437620
Short name T778
Test name
Test status
Simulation time 417583412 ps
CPU time 11.29 seconds
Started Jun 21 06:29:07 PM PDT 24
Finished Jun 21 06:29:20 PM PDT 24
Peak memory 218404 kb
Host smart-2b269270-2729-4eb1-8035-56d89cdce2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247437620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.247437620
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1905828335
Short name T531
Test name
Test status
Simulation time 680952259 ps
CPU time 4.01 seconds
Started Jun 21 06:28:56 PM PDT 24
Finished Jun 21 06:29:02 PM PDT 24
Peak memory 217400 kb
Host smart-20dd929d-402f-4e58-a1c9-35f1f999bde6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905828335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1905828335
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.2220349761
Short name T328
Test name
Test status
Simulation time 6947405868 ps
CPU time 27.02 seconds
Started Jun 21 06:29:00 PM PDT 24
Finished Jun 21 06:29:28 PM PDT 24
Peak memory 219168 kb
Host smart-1eff378d-520d-49c4-be49-0079df395738
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220349761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.2220349761
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1835491357
Short name T769
Test name
Test status
Simulation time 1197785550 ps
CPU time 8.57 seconds
Started Jun 21 06:29:01 PM PDT 24
Finished Jun 21 06:29:11 PM PDT 24
Peak memory 217872 kb
Host smart-0d3f51cb-2147-47fd-8ef2-3577d9a784ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835491357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
835491357
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.661319861
Short name T858
Test name
Test status
Simulation time 2647629812 ps
CPU time 8.41 seconds
Started Jun 21 06:29:01 PM PDT 24
Finished Jun 21 06:29:11 PM PDT 24
Peak memory 223728 kb
Host smart-f3a3dfb0-09c0-4d5b-bedd-318d66468ed4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661319861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
prog_failure.661319861
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1669264954
Short name T683
Test name
Test status
Simulation time 710803793 ps
CPU time 20.28 seconds
Started Jun 21 06:28:58 PM PDT 24
Finished Jun 21 06:29:20 PM PDT 24
Peak memory 217804 kb
Host smart-608c37aa-3616-43ab-b553-2b66069230fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669264954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1669264954
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.4004760971
Short name T856
Test name
Test status
Simulation time 539066708 ps
CPU time 2.39 seconds
Started Jun 21 06:28:58 PM PDT 24
Finished Jun 21 06:29:02 PM PDT 24
Peak memory 217748 kb
Host smart-016e0d8b-6eb7-4fdd-946a-5905cfd3abc7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004760971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
4004760971
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.3789127820
Short name T437
Test name
Test status
Simulation time 2581502764 ps
CPU time 94.03 seconds
Started Jun 21 06:29:07 PM PDT 24
Finished Jun 21 06:30:43 PM PDT 24
Peak memory 279816 kb
Host smart-069c47a7-c36e-4424-b8f1-21dc99e9f635
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789127820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.3789127820
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.445508924
Short name T99
Test name
Test status
Simulation time 1959263562 ps
CPU time 18.44 seconds
Started Jun 21 06:29:11 PM PDT 24
Finished Jun 21 06:29:33 PM PDT 24
Peak memory 247640 kb
Host smart-28fd383e-61fb-4b14-98fb-bffeda6399bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445508924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_state_post_trans.445508924
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3823443223
Short name T749
Test name
Test status
Simulation time 88139152 ps
CPU time 3.26 seconds
Started Jun 21 06:28:58 PM PDT 24
Finished Jun 21 06:29:03 PM PDT 24
Peak memory 222632 kb
Host smart-1f6de977-48f0-46c7-a967-a719370e317f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823443223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3823443223
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.1706018543
Short name T70
Test name
Test status
Simulation time 531433055 ps
CPU time 7.31 seconds
Started Jun 21 06:29:05 PM PDT 24
Finished Jun 21 06:29:14 PM PDT 24
Peak memory 217816 kb
Host smart-a41ba2cb-e741-4668-872f-ca00a31221c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706018543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1706018543
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.1765800444
Short name T796
Test name
Test status
Simulation time 4178408165 ps
CPU time 18.96 seconds
Started Jun 21 06:28:57 PM PDT 24
Finished Jun 21 06:29:17 PM PDT 24
Peak memory 218456 kb
Host smart-f8b24bcf-0a69-431d-8500-a68e5ee23707
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765800444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1765800444
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.999027253
Short name T483
Test name
Test status
Simulation time 437652443 ps
CPU time 8.71 seconds
Started Jun 21 06:29:08 PM PDT 24
Finished Jun 21 06:29:19 PM PDT 24
Peak memory 226216 kb
Host smart-991bc5b8-2d59-4768-9e3d-41f7b36a26c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999027253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dig
est.999027253
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3416935960
Short name T432
Test name
Test status
Simulation time 344974451 ps
CPU time 6.91 seconds
Started Jun 21 06:29:04 PM PDT 24
Finished Jun 21 06:29:12 PM PDT 24
Peak memory 218384 kb
Host smart-d6c48839-21fc-4af0-8afe-488beadfccc0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416935960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3
416935960
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.3550608636
Short name T51
Test name
Test status
Simulation time 1158112993 ps
CPU time 9.27 seconds
Started Jun 21 06:29:05 PM PDT 24
Finished Jun 21 06:29:15 PM PDT 24
Peak memory 226196 kb
Host smart-d1bedf2a-2d8f-4d0e-a4ae-575725c59f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550608636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3550608636
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.4146901386
Short name T641
Test name
Test status
Simulation time 441111157 ps
CPU time 3.74 seconds
Started Jun 21 06:29:05 PM PDT 24
Finished Jun 21 06:29:09 PM PDT 24
Peak memory 217824 kb
Host smart-aaabed87-d5b2-4821-bcb1-593fe05177f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146901386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.4146901386
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3219509955
Short name T459
Test name
Test status
Simulation time 460525876 ps
CPU time 24.8 seconds
Started Jun 21 06:29:06 PM PDT 24
Finished Jun 21 06:29:33 PM PDT 24
Peak memory 251052 kb
Host smart-a6c13fdc-a031-47bd-8258-a598857933ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219509955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3219509955
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.1401364407
Short name T677
Test name
Test status
Simulation time 80029201 ps
CPU time 8.2 seconds
Started Jun 21 06:28:54 PM PDT 24
Finished Jun 21 06:29:04 PM PDT 24
Peak memory 251024 kb
Host smart-2377490f-0486-4c98-b32f-fd1db14bbae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401364407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.1401364407
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.2216707508
Short name T542
Test name
Test status
Simulation time 4745816905 ps
CPU time 75.46 seconds
Started Jun 21 06:28:59 PM PDT 24
Finished Jun 21 06:30:16 PM PDT 24
Peak memory 251076 kb
Host smart-c4e23ec3-4268-4252-9456-5ba07df3b8d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216707508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.2216707508
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.3637660897
Short name T640
Test name
Test status
Simulation time 23579852183 ps
CPU time 417.39 seconds
Started Jun 21 06:29:01 PM PDT 24
Finished Jun 21 06:36:00 PM PDT 24
Peak memory 466748 kb
Host smart-76bd28fa-ef50-453f-a800-79064d73fffe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3637660897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.3637660897
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1071175785
Short name T570
Test name
Test status
Simulation time 11707620 ps
CPU time 1.01 seconds
Started Jun 21 06:28:56 PM PDT 24
Finished Jun 21 06:28:59 PM PDT 24
Peak memory 211888 kb
Host smart-a553cfe4-9f64-4bdd-a8a5-11f6e88df472
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071175785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.1071175785
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.449116096
Short name T607
Test name
Test status
Simulation time 45327559 ps
CPU time 0.95 seconds
Started Jun 21 06:29:09 PM PDT 24
Finished Jun 21 06:29:13 PM PDT 24
Peak memory 208956 kb
Host smart-b48bfb80-9ad2-4522-a5be-34b359c50a14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449116096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.449116096
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3107940885
Short name T68
Test name
Test status
Simulation time 35967890 ps
CPU time 0.81 seconds
Started Jun 21 06:29:00 PM PDT 24
Finished Jun 21 06:29:02 PM PDT 24
Peak memory 208964 kb
Host smart-07ef0586-431d-4baf-95a5-7f38a3e16894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107940885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3107940885
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1167995601
Short name T315
Test name
Test status
Simulation time 479884747 ps
CPU time 14.61 seconds
Started Jun 21 06:28:57 PM PDT 24
Finished Jun 21 06:29:14 PM PDT 24
Peak memory 218404 kb
Host smart-7c95ba68-d4af-44f0-bf22-fcf31e9329df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167995601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1167995601
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.3618713845
Short name T8
Test name
Test status
Simulation time 1689067553 ps
CPU time 10.55 seconds
Started Jun 21 06:29:01 PM PDT 24
Finished Jun 21 06:29:13 PM PDT 24
Peak memory 217576 kb
Host smart-97eaab57-6902-4b89-b877-03cd01b1cb5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618713845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.3618713845
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.3067068893
Short name T97
Test name
Test status
Simulation time 1309442218 ps
CPU time 41.89 seconds
Started Jun 21 06:28:57 PM PDT 24
Finished Jun 21 06:29:40 PM PDT 24
Peak memory 218316 kb
Host smart-450d6d61-e144-402d-8e90-3a56f414242b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067068893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.3067068893
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.371527880
Short name T3
Test name
Test status
Simulation time 255417603 ps
CPU time 2.13 seconds
Started Jun 21 06:29:00 PM PDT 24
Finished Jun 21 06:29:03 PM PDT 24
Peak memory 217892 kb
Host smart-83814866-5687-4734-a198-bc80baffb45c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371527880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.371527880
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1262520042
Short name T197
Test name
Test status
Simulation time 54030230 ps
CPU time 1.96 seconds
Started Jun 21 06:29:06 PM PDT 24
Finished Jun 21 06:29:08 PM PDT 24
Peak memory 221504 kb
Host smart-1bb69527-ef5b-44dd-9dc7-9330bd460590
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262520042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1262520042
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.316707548
Short name T839
Test name
Test status
Simulation time 970912675 ps
CPU time 27.33 seconds
Started Jun 21 06:28:58 PM PDT 24
Finished Jun 21 06:29:27 PM PDT 24
Peak memory 217716 kb
Host smart-1e72d58d-f47c-4737-bb7f-d57cd693f9e3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316707548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.316707548
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.4144143238
Short name T61
Test name
Test status
Simulation time 794336380 ps
CPU time 6.44 seconds
Started Jun 21 06:29:08 PM PDT 24
Finished Jun 21 06:29:17 PM PDT 24
Peak memory 217832 kb
Host smart-9c584655-9522-49bf-9a20-3f66220844a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144143238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
4144143238
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2691468648
Short name T369
Test name
Test status
Simulation time 1276153534 ps
CPU time 56.36 seconds
Started Jun 21 06:29:13 PM PDT 24
Finished Jun 21 06:30:12 PM PDT 24
Peak memory 267484 kb
Host smart-48bcaf25-9a7f-40c1-b1fb-6c7cdd0bec35
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691468648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2691468648
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.882591432
Short name T614
Test name
Test status
Simulation time 1835438587 ps
CPU time 31.64 seconds
Started Jun 21 06:29:21 PM PDT 24
Finished Jun 21 06:29:54 PM PDT 24
Peak memory 250792 kb
Host smart-6be64a2e-2934-4cd6-adc8-a377a06e4fc9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882591432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_state_post_trans.882591432
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1907345663
Short name T513
Test name
Test status
Simulation time 569600434 ps
CPU time 5.57 seconds
Started Jun 21 06:29:04 PM PDT 24
Finished Jun 21 06:29:11 PM PDT 24
Peak memory 218288 kb
Host smart-7a60d162-1fca-40c6-8a2c-81e51a277cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907345663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1907345663
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.2089290218
Short name T220
Test name
Test status
Simulation time 206295853 ps
CPU time 8.68 seconds
Started Jun 21 06:28:56 PM PDT 24
Finished Jun 21 06:29:07 PM PDT 24
Peak memory 217824 kb
Host smart-babc1f05-4c9e-4445-bb2a-b6a0734830ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089290218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.2089290218
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.3665372154
Short name T320
Test name
Test status
Simulation time 2480100853 ps
CPU time 14.34 seconds
Started Jun 21 06:29:00 PM PDT 24
Finished Jun 21 06:29:15 PM PDT 24
Peak memory 219192 kb
Host smart-290f1034-d8e6-4d52-8c53-2aad5b27966d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665372154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.3665372154
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3664522831
Short name T268
Test name
Test status
Simulation time 3096350103 ps
CPU time 14.79 seconds
Started Jun 21 06:29:08 PM PDT 24
Finished Jun 21 06:29:25 PM PDT 24
Peak memory 219184 kb
Host smart-6153b2cb-bb88-472e-b277-0b015e187666
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664522831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3664522831
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.302127081
Short name T679
Test name
Test status
Simulation time 308526919 ps
CPU time 11.52 seconds
Started Jun 21 06:28:59 PM PDT 24
Finished Jun 21 06:29:12 PM PDT 24
Peak memory 218324 kb
Host smart-9631e8b4-8e39-4a1f-b097-c4550a298db3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302127081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.302127081
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.1331386689
Short name T671
Test name
Test status
Simulation time 316260058 ps
CPU time 8.03 seconds
Started Jun 21 06:29:03 PM PDT 24
Finished Jun 21 06:29:13 PM PDT 24
Peak memory 226212 kb
Host smart-6efef670-4aa2-4c04-9f05-92e5763b5168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331386689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1331386689
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.974177637
Short name T80
Test name
Test status
Simulation time 28720236 ps
CPU time 1.03 seconds
Started Jun 21 06:29:06 PM PDT 24
Finished Jun 21 06:29:09 PM PDT 24
Peak memory 212068 kb
Host smart-330d8451-0879-4dc1-ad1a-f4c566f961cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974177637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.974177637
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1297682058
Short name T830
Test name
Test status
Simulation time 1105593391 ps
CPU time 23.95 seconds
Started Jun 21 06:28:58 PM PDT 24
Finished Jun 21 06:29:24 PM PDT 24
Peak memory 250980 kb
Host smart-67739373-fc0a-4f79-9150-e3914a1256b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297682058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1297682058
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.4281375600
Short name T637
Test name
Test status
Simulation time 183080874 ps
CPU time 6.77 seconds
Started Jun 21 06:29:02 PM PDT 24
Finished Jun 21 06:29:10 PM PDT 24
Peak memory 244536 kb
Host smart-e67b9d2e-018c-45f9-b6d3-c8bae99ebf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281375600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.4281375600
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.93772422
Short name T684
Test name
Test status
Simulation time 12521661559 ps
CPU time 429.55 seconds
Started Jun 21 06:29:01 PM PDT 24
Finished Jun 21 06:36:12 PM PDT 24
Peak memory 226224 kb
Host smart-ba02c103-6231-4d19-a2e3-f8812bdbe1b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93772422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.lc_ctrl_stress_all.93772422
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3664587545
Short name T786
Test name
Test status
Simulation time 15282169 ps
CPU time 1.12 seconds
Started Jun 21 06:29:01 PM PDT 24
Finished Jun 21 06:29:04 PM PDT 24
Peak memory 212988 kb
Host smart-1ee0a35a-f11f-437e-943f-4ed121e16d64
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664587545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.3664587545
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.2276739364
Short name T692
Test name
Test status
Simulation time 230071677 ps
CPU time 0.87 seconds
Started Jun 21 06:29:25 PM PDT 24
Finished Jun 21 06:29:27 PM PDT 24
Peak memory 208844 kb
Host smart-c175f93d-e93d-42df-9efd-45f5fe027ab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276739364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.2276739364
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.2665415425
Short name T222
Test name
Test status
Simulation time 18681311 ps
CPU time 0.98 seconds
Started Jun 21 06:29:01 PM PDT 24
Finished Jun 21 06:29:04 PM PDT 24
Peak memory 209068 kb
Host smart-957549aa-1444-4e94-a6a1-ea68f998142a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665415425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2665415425
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.2732328044
Short name T606
Test name
Test status
Simulation time 1680309235 ps
CPU time 12.75 seconds
Started Jun 21 06:29:06 PM PDT 24
Finished Jun 21 06:29:20 PM PDT 24
Peak memory 218332 kb
Host smart-cb9c2105-83a6-4fb3-adf5-aba0420d49ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732328044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.2732328044
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.3684755172
Short name T706
Test name
Test status
Simulation time 1023995384 ps
CPU time 6.74 seconds
Started Jun 21 06:29:08 PM PDT 24
Finished Jun 21 06:29:17 PM PDT 24
Peak memory 217428 kb
Host smart-83e9d34b-7d6e-44a3-b3dd-fdcb99519625
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684755172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3684755172
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1632794141
Short name T280
Test name
Test status
Simulation time 4186248339 ps
CPU time 54.02 seconds
Started Jun 21 06:29:09 PM PDT 24
Finished Jun 21 06:30:06 PM PDT 24
Peak memory 219048 kb
Host smart-68d1ce58-7f1b-409b-815e-cd2995ecd5b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632794141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1632794141
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.3822034112
Short name T848
Test name
Test status
Simulation time 853985832 ps
CPU time 3.34 seconds
Started Jun 21 06:29:02 PM PDT 24
Finished Jun 21 06:29:07 PM PDT 24
Peak memory 217384 kb
Host smart-d85d506d-4401-41ea-a06a-f6a9aae88edb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822034112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.3
822034112
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.416173694
Short name T411
Test name
Test status
Simulation time 4833677481 ps
CPU time 7.89 seconds
Started Jun 21 06:29:08 PM PDT 24
Finished Jun 21 06:29:18 PM PDT 24
Peak memory 223352 kb
Host smart-434f268c-1e6e-483e-8b7a-d1801419ee3b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416173694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
prog_failure.416173694
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.519800769
Short name T298
Test name
Test status
Simulation time 888845498 ps
CPU time 14.44 seconds
Started Jun 21 06:29:25 PM PDT 24
Finished Jun 21 06:29:41 PM PDT 24
Peak memory 217748 kb
Host smart-00b80c3c-b6ab-4935-89e6-1211d573d876
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519800769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_regwen_during_op.519800769
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.55029608
Short name T241
Test name
Test status
Simulation time 595153382 ps
CPU time 4.01 seconds
Started Jun 21 06:29:06 PM PDT 24
Finished Jun 21 06:29:11 PM PDT 24
Peak memory 217748 kb
Host smart-c629c1a4-f76e-4cae-9fc1-270ed3f97e12
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55029608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.55029608
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.1895515083
Short name T271
Test name
Test status
Simulation time 1240655926 ps
CPU time 34.47 seconds
Started Jun 21 06:29:16 PM PDT 24
Finished Jun 21 06:29:51 PM PDT 24
Peak memory 250948 kb
Host smart-30ecccdf-cec8-44ba-9cc6-f3a9528f3ce1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895515083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.1895515083
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.242477551
Short name T652
Test name
Test status
Simulation time 453877737 ps
CPU time 11.33 seconds
Started Jun 21 06:29:08 PM PDT 24
Finished Jun 21 06:29:21 PM PDT 24
Peak memory 250468 kb
Host smart-f3114a11-b3cc-411b-aece-0f943061bf51
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242477551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_state_post_trans.242477551
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.3751471244
Short name T817
Test name
Test status
Simulation time 144008732 ps
CPU time 3.74 seconds
Started Jun 21 06:29:06 PM PDT 24
Finished Jun 21 06:29:11 PM PDT 24
Peak memory 218340 kb
Host smart-fde9491e-b2e2-4d56-b750-95380c33d37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751471244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3751471244
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3873156854
Short name T198
Test name
Test status
Simulation time 413904867 ps
CPU time 6.49 seconds
Started Jun 21 06:29:08 PM PDT 24
Finished Jun 21 06:29:17 PM PDT 24
Peak memory 217824 kb
Host smart-e97f7e67-89be-45aa-bf39-9fec43bd8953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873156854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3873156854
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.4054792366
Short name T481
Test name
Test status
Simulation time 332124813 ps
CPU time 16.02 seconds
Started Jun 21 06:29:18 PM PDT 24
Finished Jun 21 06:29:35 PM PDT 24
Peak memory 220188 kb
Host smart-5e9926bd-3e98-429c-8cfd-04a0e1fb8753
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054792366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.4054792366
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2851238795
Short name T406
Test name
Test status
Simulation time 899507527 ps
CPU time 8.02 seconds
Started Jun 21 06:29:25 PM PDT 24
Finished Jun 21 06:29:35 PM PDT 24
Peak memory 226172 kb
Host smart-3a1b8f66-4156-46d8-bb70-062b42328a73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851238795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2851238795
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.2667546784
Short name T345
Test name
Test status
Simulation time 463068529 ps
CPU time 9.5 seconds
Started Jun 21 06:29:15 PM PDT 24
Finished Jun 21 06:29:31 PM PDT 24
Peak memory 218352 kb
Host smart-ecdfd22d-a676-46f7-b164-51d76011251c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667546784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.2
667546784
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.2187465918
Short name T365
Test name
Test status
Simulation time 288398741 ps
CPU time 12.1 seconds
Started Jun 21 06:29:11 PM PDT 24
Finished Jun 21 06:29:26 PM PDT 24
Peak memory 226208 kb
Host smart-f00f1afc-b4ed-4b29-94af-fcadb7cb8044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187465918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2187465918
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.1270355191
Short name T77
Test name
Test status
Simulation time 20596545 ps
CPU time 1.8 seconds
Started Jun 21 06:28:58 PM PDT 24
Finished Jun 21 06:29:02 PM PDT 24
Peak memory 214352 kb
Host smart-261bbef0-a0de-41a4-9f26-accf180bcbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270355191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.1270355191
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.2474655404
Short name T846
Test name
Test status
Simulation time 1127038094 ps
CPU time 22.42 seconds
Started Jun 21 06:29:08 PM PDT 24
Finished Jun 21 06:29:33 PM PDT 24
Peak memory 251028 kb
Host smart-ec91bbc8-772c-425f-ac85-54a257a5bc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474655404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2474655404
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.1958159416
Short name T700
Test name
Test status
Simulation time 67393950 ps
CPU time 2.83 seconds
Started Jun 21 06:29:08 PM PDT 24
Finished Jun 21 06:29:13 PM PDT 24
Peak memory 222376 kb
Host smart-eed99f2b-2e9e-4e68-a248-5bc6582ab0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958159416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.1958159416
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3214624008
Short name T73
Test name
Test status
Simulation time 8274531836 ps
CPU time 132.11 seconds
Started Jun 21 06:29:07 PM PDT 24
Finished Jun 21 06:31:21 PM PDT 24
Peak memory 226928 kb
Host smart-70fff3c1-a2a0-49b2-9c1c-3554352d5001
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214624008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3214624008
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3619481384
Short name T453
Test name
Test status
Simulation time 14721242 ps
CPU time 1.23 seconds
Started Jun 21 06:28:55 PM PDT 24
Finished Jun 21 06:28:58 PM PDT 24
Peak memory 213356 kb
Host smart-ea715cb8-ed83-4efb-a377-dc04689c24b8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619481384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3619481384
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.1065597127
Short name T145
Test name
Test status
Simulation time 26545977 ps
CPU time 1.03 seconds
Started Jun 21 06:29:07 PM PDT 24
Finished Jun 21 06:29:10 PM PDT 24
Peak memory 208952 kb
Host smart-9fd92c15-c28b-488d-9270-bc15758853f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065597127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.1065597127
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.1468575027
Short name T224
Test name
Test status
Simulation time 13815497 ps
CPU time 1 seconds
Started Jun 21 06:29:09 PM PDT 24
Finished Jun 21 06:29:13 PM PDT 24
Peak memory 209096 kb
Host smart-26d9ff4c-9d81-47c2-9331-9385eb43b9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468575027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1468575027
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.2478244008
Short name T664
Test name
Test status
Simulation time 326017474 ps
CPU time 16.26 seconds
Started Jun 21 06:29:24 PM PDT 24
Finished Jun 21 06:29:42 PM PDT 24
Peak memory 218336 kb
Host smart-11d749d2-a3bb-4203-a659-87aed2fe53e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478244008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.2478244008
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.1243988325
Short name T868
Test name
Test status
Simulation time 822169199 ps
CPU time 6.96 seconds
Started Jun 21 06:29:15 PM PDT 24
Finished Jun 21 06:29:23 PM PDT 24
Peak memory 217480 kb
Host smart-435efe82-e416-4676-b4c3-6218c75a1ca9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243988325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.1243988325
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.547042569
Short name T835
Test name
Test status
Simulation time 2168520661 ps
CPU time 31.84 seconds
Started Jun 21 06:29:17 PM PDT 24
Finished Jun 21 06:29:50 PM PDT 24
Peak memory 218388 kb
Host smart-eb3d1e3b-ccfa-4fba-9501-102a6cbbe830
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547042569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_err
ors.547042569
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2347352637
Short name T6
Test name
Test status
Simulation time 536842996 ps
CPU time 4.2 seconds
Started Jun 21 06:29:11 PM PDT 24
Finished Jun 21 06:29:18 PM PDT 24
Peak memory 217612 kb
Host smart-df264be7-b60c-49f3-ae4f-c9ce006857e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347352637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
347352637
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.3226898624
Short name T291
Test name
Test status
Simulation time 328866401 ps
CPU time 10.85 seconds
Started Jun 21 06:29:13 PM PDT 24
Finished Jun 21 06:29:26 PM PDT 24
Peak memory 218244 kb
Host smart-6a5c7cfb-2746-47e3-93f9-765c707e65fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226898624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.3226898624
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.318830952
Short name T803
Test name
Test status
Simulation time 1082283848 ps
CPU time 17.05 seconds
Started Jun 21 06:29:08 PM PDT 24
Finished Jun 21 06:29:27 PM PDT 24
Peak memory 217316 kb
Host smart-a03da0ef-c362-4727-b771-62fa2b114694
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318830952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_regwen_during_op.318830952
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2808448488
Short name T861
Test name
Test status
Simulation time 899906605 ps
CPU time 2.88 seconds
Started Jun 21 06:29:06 PM PDT 24
Finished Jun 21 06:29:10 PM PDT 24
Peak memory 217656 kb
Host smart-8152bbd2-34f3-49eb-8e42-50c7279a07db
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808448488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2808448488
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1183715477
Short name T314
Test name
Test status
Simulation time 7200258663 ps
CPU time 49.64 seconds
Started Jun 21 06:29:06 PM PDT 24
Finished Jun 21 06:29:57 PM PDT 24
Peak memory 254608 kb
Host smart-5491ce73-e1b3-4218-a1d8-4b9d275311b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183715477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.1183715477
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3447181020
Short name T789
Test name
Test status
Simulation time 1385066572 ps
CPU time 11.49 seconds
Started Jun 21 06:29:09 PM PDT 24
Finished Jun 21 06:29:23 PM PDT 24
Peak memory 250956 kb
Host smart-11b31e11-da4d-483e-8e4a-f19831e1b50f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447181020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.3447181020
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1703430075
Short name T782
Test name
Test status
Simulation time 52810970 ps
CPU time 2.33 seconds
Started Jun 21 06:29:05 PM PDT 24
Finished Jun 21 06:29:08 PM PDT 24
Peak memory 222504 kb
Host smart-f953fca0-0a07-47f0-b317-0bd4d315b588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703430075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1703430075
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.937081864
Short name T456
Test name
Test status
Simulation time 1143326968 ps
CPU time 10.33 seconds
Started Jun 21 06:29:04 PM PDT 24
Finished Jun 21 06:29:15 PM PDT 24
Peak memory 217852 kb
Host smart-451862c4-cc93-4894-b2c0-25f3f7463256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937081864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.937081864
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.939440927
Short name T273
Test name
Test status
Simulation time 337598307 ps
CPU time 13.41 seconds
Started Jun 21 06:28:59 PM PDT 24
Finished Jun 21 06:29:14 PM PDT 24
Peak memory 219088 kb
Host smart-40697fe9-1b69-4318-937e-e64f814fcfc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939440927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.939440927
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.905377831
Short name T24
Test name
Test status
Simulation time 797749158 ps
CPU time 16.05 seconds
Started Jun 21 06:28:59 PM PDT 24
Finished Jun 21 06:29:16 PM PDT 24
Peak memory 218348 kb
Host smart-de803de8-fb4b-4d2e-b7f9-f018021d5764
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905377831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dig
est.905377831
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1839200515
Short name T825
Test name
Test status
Simulation time 299892665 ps
CPU time 11.09 seconds
Started Jun 21 06:29:10 PM PDT 24
Finished Jun 21 06:29:24 PM PDT 24
Peak memory 218476 kb
Host smart-78bbd4cd-ce80-40f4-b619-5837d738391a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839200515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.1
839200515
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.2965606543
Short name T859
Test name
Test status
Simulation time 414776700 ps
CPU time 10.3 seconds
Started Jun 21 06:29:27 PM PDT 24
Finished Jun 21 06:29:39 PM PDT 24
Peak memory 218460 kb
Host smart-9d3ed377-4bab-4c60-b191-78d373c03e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965606543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2965606543
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1977101756
Short name T75
Test name
Test status
Simulation time 99406216 ps
CPU time 2.71 seconds
Started Jun 21 06:29:14 PM PDT 24
Finished Jun 21 06:29:18 PM PDT 24
Peak memory 217788 kb
Host smart-6bd611d8-3687-4c67-9c6e-7d60039eba91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977101756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1977101756
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.2564953808
Short name T802
Test name
Test status
Simulation time 265690470 ps
CPU time 22.91 seconds
Started Jun 21 06:29:09 PM PDT 24
Finished Jun 21 06:29:34 PM PDT 24
Peak memory 251028 kb
Host smart-0b0f8d99-3b09-4314-9c12-8baaae362907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564953808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2564953808
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.577692508
Short name T811
Test name
Test status
Simulation time 96784598 ps
CPU time 6.84 seconds
Started Jun 21 06:29:21 PM PDT 24
Finished Jun 21 06:29:30 PM PDT 24
Peak memory 250940 kb
Host smart-51df9156-3839-4ded-b3eb-dc750dcad7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577692508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.577692508
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.2447708431
Short name T592
Test name
Test status
Simulation time 4901225792 ps
CPU time 126.34 seconds
Started Jun 21 06:29:07 PM PDT 24
Finished Jun 21 06:31:14 PM PDT 24
Peak memory 283812 kb
Host smart-80dbf95d-760a-4079-af21-6b9ed2e61b64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447708431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.2447708431
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3689309178
Short name T530
Test name
Test status
Simulation time 85899154 ps
CPU time 0.83 seconds
Started Jun 21 06:29:07 PM PDT 24
Finished Jun 21 06:29:10 PM PDT 24
Peak memory 211996 kb
Host smart-04348476-31a4-4736-939d-55dbb2b309bc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689309178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.3689309178
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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