Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52479 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
344 |
auto[1] |
1794 |
1 |
|
|
T13 |
4 |
|
T15 |
6 |
|
T4 |
7 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53540 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
344 |
auto[1] |
733 |
1 |
|
|
T36 |
16 |
|
T19 |
22 |
|
T46 |
11 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52251 |
1 |
|
|
T1 |
78 |
|
T2 |
1 |
|
T3 |
301 |
auto[1] |
2022 |
1 |
|
|
T1 |
12 |
|
T3 |
43 |
|
T11 |
10 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52252 |
1 |
|
|
T1 |
77 |
|
T2 |
1 |
|
T3 |
307 |
auto[1] |
2021 |
1 |
|
|
T1 |
13 |
|
T3 |
37 |
|
T11 |
7 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52242 |
1 |
|
|
T1 |
82 |
|
T2 |
1 |
|
T3 |
305 |
auto[1] |
2031 |
1 |
|
|
T1 |
8 |
|
T3 |
39 |
|
T11 |
6 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
49326 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
332 |
no_err_inj |
4947 |
1 |
|
|
T3 |
12 |
|
T27 |
3 |
|
T38 |
6 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52497 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
344 |
auto[1] |
1776 |
1 |
|
|
T13 |
11 |
|
T15 |
4 |
|
T4 |
11 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53558 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
344 |
auto[1] |
715 |
1 |
|
|
T36 |
20 |
|
T19 |
15 |
|
T46 |
9 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38499 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
255 |
auto[1] |
15774 |
1 |
|
|
T3 |
89 |
|
T4 |
64 |
|
T5 |
12 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52233 |
1 |
|
|
T1 |
75 |
|
T2 |
1 |
|
T3 |
302 |
auto[1] |
2040 |
1 |
|
|
T1 |
15 |
|
T3 |
42 |
|
T11 |
12 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52243 |
1 |
|
|
T1 |
81 |
|
T2 |
1 |
|
T3 |
309 |
auto[1] |
2030 |
1 |
|
|
T1 |
9 |
|
T3 |
35 |
|
T11 |
2 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52301 |
1 |
|
|
T1 |
83 |
|
T2 |
1 |
|
T3 |
306 |
auto[1] |
1972 |
1 |
|
|
T1 |
7 |
|
T3 |
38 |
|
T11 |
3 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52590 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
344 |
auto[1] |
1683 |
1 |
|
|
T13 |
4 |
|
T15 |
5 |
|
T4 |
11 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51889 |
1 |
|
|
T1 |
90 |
|
T3 |
344 |
|
T11 |
57 |
auto[1] |
2384 |
1 |
|
|
T2 |
1 |
|
T10 |
4 |
|
T59 |
19 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53505 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
344 |
auto[1] |
768 |
1 |
|
|
T36 |
17 |
|
T19 |
14 |
|
T46 |
15 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53539 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
344 |
auto[1] |
734 |
1 |
|
|
T36 |
21 |
|
T19 |
18 |
|
T46 |
14 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53520 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
344 |
auto[1] |
753 |
1 |
|
|
T36 |
24 |
|
T19 |
18 |
|
T46 |
14 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51667 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
331 |
auto[1] |
2606 |
1 |
|
|
T3 |
13 |
|
T27 |
14 |
|
T38 |
12 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50632 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
344 |
auto[1] |
3641 |
1 |
|
|
T40 |
59 |
|
T42 |
53 |
|
T54 |
75 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52253 |
1 |
|
|
T1 |
85 |
|
T2 |
1 |
|
T3 |
310 |
auto[1] |
2020 |
1 |
|
|
T1 |
5 |
|
T3 |
34 |
|
T11 |
7 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52200 |
1 |
|
|
T1 |
82 |
|
T2 |
1 |
|
T3 |
307 |
auto[1] |
2073 |
1 |
|
|
T1 |
8 |
|
T3 |
37 |
|
T11 |
6 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52279 |
1 |
|
|
T1 |
77 |
|
T2 |
1 |
|
T3 |
317 |
auto[1] |
1994 |
1 |
|
|
T1 |
13 |
|
T3 |
27 |
|
T11 |
4 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52527 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
344 |
auto[1] |
1746 |
1 |
|
|
T13 |
10 |
|
T15 |
9 |
|
T4 |
6 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48908 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
344 |
auto[1] |
5365 |
1 |
|
|
T13 |
4 |
|
T15 |
6 |
|
T4 |
5 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50371 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
344 |
auto[1] |
3902 |
1 |
|
|
T12 |
74 |
|
T14 |
62 |
|
T22 |
96 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54273 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
344 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52610 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
344 |
auto[1] |
1663 |
1 |
|
|
T13 |
6 |
|
T15 |
4 |
|
T4 |
10 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52511 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
344 |
auto[1] |
1762 |
1 |
|
|
T13 |
8 |
|
T15 |
11 |
|
T4 |
6 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52569 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
344 |
auto[1] |
1704 |
1 |
|
|
T13 |
5 |
|
T15 |
5 |
|
T4 |
8 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
48025 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
325 |
auto[0] |
no_err_inj |
3642 |
1 |
|
|
T3 |
6 |
|
T63 |
10 |
|
T215 |
7 |
auto[1] |
err_inj |
1301 |
1 |
|
|
T3 |
7 |
|
T27 |
11 |
|
T38 |
6 |
auto[1] |
no_err_inj |
1305 |
1 |
|
|
T3 |
6 |
|
T27 |
3 |
|
T38 |
6 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49734 |
1 |
|
|
T1 |
82 |
|
T2 |
1 |
|
T3 |
295 |
auto[0] |
auto[1] |
1933 |
1 |
|
|
T1 |
8 |
|
T3 |
36 |
|
T11 |
6 |
auto[1] |
auto[0] |
2466 |
1 |
|
|
T3 |
12 |
|
T27 |
13 |
|
T38 |
11 |
auto[1] |
auto[1] |
140 |
1 |
|
|
T3 |
1 |
|
T27 |
1 |
|
T38 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49788 |
1 |
|
|
T1 |
81 |
|
T2 |
1 |
|
T3 |
297 |
auto[0] |
auto[1] |
1879 |
1 |
|
|
T1 |
9 |
|
T3 |
34 |
|
T11 |
2 |
auto[1] |
auto[0] |
2455 |
1 |
|
|
T3 |
12 |
|
T27 |
12 |
|
T38 |
12 |
auto[1] |
auto[1] |
151 |
1 |
|
|
T3 |
1 |
|
T27 |
2 |
|
T43 |
6 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49830 |
1 |
|
|
T1 |
77 |
|
T2 |
1 |
|
T3 |
305 |
auto[0] |
auto[1] |
1837 |
1 |
|
|
T1 |
13 |
|
T3 |
26 |
|
T11 |
4 |
auto[1] |
auto[0] |
2449 |
1 |
|
|
T3 |
12 |
|
T27 |
14 |
|
T38 |
10 |
auto[1] |
auto[1] |
157 |
1 |
|
|
T3 |
1 |
|
T38 |
2 |
|
T115 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49790 |
1 |
|
|
T1 |
77 |
|
T2 |
1 |
|
T3 |
294 |
auto[0] |
auto[1] |
1877 |
1 |
|
|
T1 |
13 |
|
T3 |
37 |
|
T11 |
7 |
auto[1] |
auto[0] |
2462 |
1 |
|
|
T3 |
13 |
|
T27 |
12 |
|
T38 |
11 |
auto[1] |
auto[1] |
144 |
1 |
|
|
T27 |
2 |
|
T38 |
1 |
|
T115 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49784 |
1 |
|
|
T1 |
82 |
|
T2 |
1 |
|
T3 |
293 |
auto[0] |
auto[1] |
1883 |
1 |
|
|
T1 |
8 |
|
T3 |
38 |
|
T11 |
6 |
auto[1] |
auto[0] |
2458 |
1 |
|
|
T3 |
12 |
|
T27 |
13 |
|
T38 |
12 |
auto[1] |
auto[1] |
148 |
1 |
|
|
T3 |
1 |
|
T27 |
1 |
|
T115 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49788 |
1 |
|
|
T1 |
78 |
|
T2 |
1 |
|
T3 |
289 |
auto[0] |
auto[1] |
1879 |
1 |
|
|
T1 |
12 |
|
T3 |
42 |
|
T11 |
10 |
auto[1] |
auto[0] |
2463 |
1 |
|
|
T3 |
12 |
|
T27 |
14 |
|
T38 |
12 |
auto[1] |
auto[1] |
143 |
1 |
|
|
T3 |
1 |
|
T115 |
2 |
|
T43 |
2 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37325 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
255 |
auto[0] |
auto[1] |
1174 |
1 |
|
|
T13 |
4 |
|
T15 |
6 |
|
T21 |
5 |
auto[1] |
auto[0] |
15154 |
1 |
|
|
T3 |
89 |
|
T4 |
57 |
|
T5 |
12 |
auto[1] |
auto[1] |
620 |
1 |
|
|
T4 |
7 |
|
T43 |
2 |
|
T45 |
8 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37347 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
255 |
auto[0] |
auto[1] |
1152 |
1 |
|
|
T13 |
11 |
|
T15 |
4 |
|
T21 |
8 |
auto[1] |
auto[0] |
15150 |
1 |
|
|
T3 |
89 |
|
T4 |
53 |
|
T5 |
12 |
auto[1] |
auto[1] |
624 |
1 |
|
|
T4 |
11 |
|
T43 |
2 |
|
T45 |
7 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37185 |
1 |
|
|
T1 |
90 |
|
T3 |
255 |
|
T11 |
57 |
auto[0] |
auto[1] |
1314 |
1 |
|
|
T2 |
1 |
|
T10 |
4 |
|
T59 |
19 |
auto[1] |
auto[0] |
14704 |
1 |
|
|
T3 |
89 |
|
T4 |
64 |
|
T24 |
79 |
auto[1] |
auto[1] |
1070 |
1 |
|
|
T5 |
12 |
|
T23 |
20 |
|
T17 |
77 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37448 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
255 |
auto[0] |
auto[1] |
1051 |
1 |
|
|
T13 |
4 |
|
T15 |
5 |
|
T21 |
9 |
auto[1] |
auto[0] |
15142 |
1 |
|
|
T3 |
89 |
|
T4 |
53 |
|
T5 |
12 |
auto[1] |
auto[1] |
632 |
1 |
|
|
T4 |
11 |
|
T43 |
1 |
|
T45 |
12 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33734 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
255 |
auto[0] |
auto[1] |
4765 |
1 |
|
|
T13 |
4 |
|
T15 |
6 |
|
T21 |
7 |
auto[1] |
auto[0] |
15174 |
1 |
|
|
T3 |
89 |
|
T4 |
59 |
|
T5 |
12 |
auto[1] |
auto[1] |
600 |
1 |
|
|
T4 |
5 |
|
T45 |
12 |
|
T17 |
23 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37312 |
1 |
|
|
T1 |
82 |
|
T2 |
1 |
|
T3 |
227 |
auto[0] |
auto[1] |
1187 |
1 |
|
|
T1 |
8 |
|
T3 |
28 |
|
T11 |
6 |
auto[1] |
auto[0] |
14888 |
1 |
|
|
T3 |
80 |
|
T4 |
64 |
|
T5 |
12 |
auto[1] |
auto[1] |
886 |
1 |
|
|
T3 |
9 |
|
T24 |
10 |
|
T25 |
4 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37350 |
1 |
|
|
T1 |
85 |
|
T2 |
1 |
|
T3 |
228 |
auto[0] |
auto[1] |
1149 |
1 |
|
|
T1 |
5 |
|
T3 |
27 |
|
T11 |
7 |
auto[1] |
auto[0] |
14903 |
1 |
|
|
T3 |
82 |
|
T4 |
64 |
|
T5 |
12 |
auto[1] |
auto[1] |
871 |
1 |
|
|
T3 |
7 |
|
T24 |
11 |
|
T25 |
8 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37298 |
1 |
|
|
T1 |
81 |
|
T2 |
1 |
|
T3 |
228 |
auto[0] |
auto[1] |
1201 |
1 |
|
|
T1 |
9 |
|
T3 |
27 |
|
T11 |
2 |
auto[1] |
auto[0] |
14945 |
1 |
|
|
T3 |
81 |
|
T4 |
64 |
|
T5 |
12 |
auto[1] |
auto[1] |
829 |
1 |
|
|
T3 |
8 |
|
T24 |
4 |
|
T25 |
2 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37295 |
1 |
|
|
T1 |
75 |
|
T2 |
1 |
|
T3 |
222 |
auto[0] |
auto[1] |
1204 |
1 |
|
|
T1 |
15 |
|
T3 |
33 |
|
T11 |
12 |
auto[1] |
auto[0] |
14938 |
1 |
|
|
T3 |
80 |
|
T4 |
64 |
|
T5 |
12 |
auto[1] |
auto[1] |
836 |
1 |
|
|
T3 |
9 |
|
T24 |
6 |
|
T25 |
7 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37361 |
1 |
|
|
T1 |
77 |
|
T2 |
1 |
|
T3 |
228 |
auto[0] |
auto[1] |
1138 |
1 |
|
|
T1 |
13 |
|
T3 |
27 |
|
T11 |
7 |
auto[1] |
auto[0] |
14891 |
1 |
|
|
T3 |
79 |
|
T4 |
64 |
|
T5 |
12 |
auto[1] |
auto[1] |
883 |
1 |
|
|
T3 |
10 |
|
T24 |
4 |
|
T25 |
10 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37342 |
1 |
|
|
T1 |
78 |
|
T2 |
1 |
|
T3 |
226 |
auto[0] |
auto[1] |
1157 |
1 |
|
|
T1 |
12 |
|
T3 |
29 |
|
T11 |
10 |
auto[1] |
auto[0] |
14909 |
1 |
|
|
T3 |
75 |
|
T4 |
64 |
|
T5 |
12 |
auto[1] |
auto[1] |
865 |
1 |
|
|
T3 |
14 |
|
T24 |
10 |
|
T25 |
7 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37411 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
255 |
auto[0] |
auto[1] |
1088 |
1 |
|
|
T13 |
5 |
|
T15 |
5 |
|
T21 |
10 |
auto[1] |
auto[0] |
15158 |
1 |
|
|
T3 |
89 |
|
T4 |
56 |
|
T5 |
12 |
auto[1] |
auto[1] |
616 |
1 |
|
|
T4 |
8 |
|
T45 |
18 |
|
T17 |
19 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37363 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
255 |
auto[0] |
auto[1] |
1136 |
1 |
|
|
T13 |
8 |
|
T15 |
11 |
|
T21 |
8 |
auto[1] |
auto[0] |
15148 |
1 |
|
|
T3 |
89 |
|
T4 |
58 |
|
T5 |
12 |
auto[1] |
auto[1] |
626 |
1 |
|
|
T4 |
6 |
|
T43 |
2 |
|
T45 |
8 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37009 |
1 |
|
|
T1 |
90 |
|
T2 |
1 |
|
T3 |
255 |
auto[0] |
auto[1] |
1490 |
1 |
|
|
T27 |
14 |
|
T38 |
12 |
|
T115 |
10 |
auto[1] |
auto[0] |
14658 |
1 |
|
|
T3 |
76 |
|
T4 |
64 |
|
T5 |
12 |
auto[1] |
auto[1] |
1116 |
1 |
|
|
T3 |
13 |
|
T43 |
27 |
|
T17 |
52 |