Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101410790

1

T1

25095

T2

1172

T3

344670

auto[1]

1425045

1

T1

3069

T3

13329

T10

297

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101396648

1

T1

24303

T2

1073

T3

344961

auto[1]

1439187

1

T1

3861

T2

99

T3

13038

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7621196	1			T1	12739		T2	144		T3	53905
auto[IdleSt]	22442941	1			T1	1290		T2	791		T3	22560
auto[ClkMuxSt]	35040	1			T2	1		T3	10		T10	4
auto[CntIncrSt]	34733	1			T2	1		T3	10		T10	4
auto[CntProgSt]	1550281	1			T2	12		T3	311		T10	8
auto[TransCheckSt]	26998	1			T3	10		T12	74		T13	41
auto[TokenHashSt]	36025756	1			T3	33985		T12	682		T13	684
auto[FlashRmaSt]	27618	1			T3	33		T12	20		T13	54
auto[TokenCheck0St]	12568	1			T3	10		T12	20		T13	16
auto[TokenCheck1St]	9300	1			T3	10		T12	5		T13	5
auto[TransProgSt]	374909	1			T3	384		T13	9		T15	10
auto[PostTransSt]	12723973	1			T2	78		T3	17304		T10	262
auto[ScrapSt]	122326	1			T3	174		T42	6		T43	1596
auto[EscalateSt]	7597377	1			T1	8858		T2	145		T3	72099
auto[InvalidSt]	14228699	1			T1	5268		T3	157159		T11	3685

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2120	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	14228699	1			T1	5268		T3	157159		T11	3685
EscalateSt	7597377	1			T1	8858		T2	145		T3	72099
ScrapSt	122326	1			T3	174		T42	6		T43	1596
PostTransSt	12723973	1			T2	78		T3	17304		T10	262
TransProgSt	374909	1			T3	384		T13	9		T15	10
TokenCheck1St	9300	1			T3	10		T12	5		T13	5
TokenCheck0St	12568	1			T3	10		T12	20		T13	16
FlashRmaSt	27618	1			T3	33		T12	20		T13	54
TokenHashSt	36025756	1			T3	33985		T12	682		T13	684
TransCheckSt	26998	1			T3	10		T12	74		T13	41
CntProgSt	1550281	1			T2	12		T3	311		T10	8
CntIncrSt	34733	1			T2	1		T3	10		T10	4
ClkMuxSt	35040	1			T2	1		T3	10		T10	4
IdleSt	22442941	1			T1	1290		T2	791		T3	22560
ResetSt	7621196	1			T1	12739		T2	144		T3	53905
arcs[ResetSt=>IdleSt]	54646	1			T1	84		T2	2		T3	312
arcs[IdleSt=>ScrapSt]	308	1			T3	2		T42	2		T43	4
arcs[IdleSt=>ClkMuxSt]	34784	1			T2	1		T3	10		T10	4
arcs[ClkMuxSt=>CntIncrSt]	34733	1			T2	1		T3	10		T10	4
arcs[CntIncrSt=>PostTransSt]	1762	1			T13	8		T15	11		T4	6
arcs[CntIncrSt=>CntProgSt]	32910	1			T2	1		T3	10		T10	4
arcs[CntProgSt=>PostTransSt]	4877	1			T2	1		T10	4		T13	3
arcs[CntProgSt=>TransCheckSt]	26998	1			T3	10		T12	74		T13	41
arcs[TransCheckSt=>PostTransSt]	3697	1			T12	43		T13	5		T14	26
arcs[TransCheckSt=>TokenHashSt]	23167	1			T3	10		T12	31		T13	36
arcs[TokenHashSt=>PostTransSt]	9797	1			T12	11		T13	20		T14	7
arcs[TokenHashSt=>FlashRmaSt]	12651	1			T3	10		T12	20		T13	16
arcs[FlashRmaSt=>TokenCheck0St]	12568	1			T3	10		T12	20		T13	16
arcs[TokenCheck0St=>PostTransSt]	3223	1			T12	15		T13	11		T14	17
arcs[TokenCheck0St=>TokenCheck1St]	9300	1			T3	10		T12	5		T13	5
arcs[TokenCheck1St=>PostTransSt]	662	1			T12	5		T14	12		T4	2
arcs[TransProgSt=>PostTransSt]	7806	1			T3	10		T13	5		T15	5
arcs[IdleSt=>EscalateSt]	171	1			T42	5		T54	5		T51	6
arcs[ClkMuxSt=>EscalateSt]	51	1			T40	3		T50	2		T51	2
arcs[CntIncrSt=>EscalateSt]	61	1			T40	1		T52	1		T53	1
arcs[CntProgSt=>EscalateSt]	1035	1			T40	24		T42	23		T54	8
arcs[TransCheckSt=>EscalateSt]	134	1			T40	1		T54	5		T55	2
arcs[TokenHashSt=>EscalateSt]	719	1			T40	9		T42	2		T43	2
arcs[FlashRmaSt=>EscalateSt]	83	1			T40	1		T54	2		T55	2
arcs[TokenCheck0St=>EscalateSt]	45	1			T40	1		T55	1		T50	1
arcs[TokenCheck1St=>EscalateSt]	142	1			T40	1		T42	1		T54	6
arcs[TransProgSt=>EscalateSt]	690	1			T40	12		T42	11		T54	9
arcs[PostTransSt=>EscalateSt]	5127	1			T2	1		T10	4		T13	4
arcs[InvalidSt=>EscalateSt]	14987	1			T1	70		T3	267		T11	50

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7621034	1			T1	12739		T2	144		T3	53905
auto[0]	auto[IdleSt]	22442828	1			T1	1290		T2	791		T3	22560
auto[0]	auto[ClkMuxSt]	35003	1			T2	1		T3	10		T10	4
auto[0]	auto[CntIncrSt]	34689	1			T2	1		T3	10		T10	4
auto[0]	auto[CntProgSt]	1549603	1			T2	12		T3	311		T10	8
auto[0]	auto[TransCheckSt]	26908	1			T3	10		T12	74		T13	41
auto[0]	auto[TokenHashSt]	36025271	1			T3	33985		T12	682		T13	684
auto[0]	auto[FlashRmaSt]	27560	1			T3	33		T12	20		T13	54
auto[0]	auto[TokenCheck0St]	12543	1			T3	10		T12	20		T13	16
auto[0]	auto[TokenCheck1St]	9205	1			T3	10		T12	5		T13	5
auto[0]	auto[TransProgSt]	374457	1			T3	384		T13	9		T15	10
auto[0]	auto[PostTransSt]	12721352	1			T2	78		T3	17304		T10	259
auto[0]	auto[ScrapSt]	122288	1			T3	174		T42	5		T43	1596
auto[0]	auto[EscalateSt]	6184648	1			T1	5820		T2	145		T3	58905
auto[0]	auto[InvalidSt]	14221281	1			T1	5237		T3	157024		T11	3659
auto[1]	auto[ResetSt]	162	1			T40	2		T42	4		T54	6
auto[1]	auto[IdleSt]	113	1			T42	2		T54	4		T51	3
auto[1]	auto[ClkMuxSt]	37	1			T40	1		T50	2		T51	1
auto[1]	auto[CntIncrSt]	44	1			T40	1		T53	1		T177	1
auto[1]	auto[CntProgSt]	678	1			T40	17		T42	17		T54	3
auto[1]	auto[TransCheckSt]	90	1			T40	1		T54	3		T55	1
auto[1]	auto[TokenHashSt]	485	1			T40	7		T42	1		T43	1
auto[1]	auto[FlashRmaSt]	58	1			T40	1		T54	2		T55	1
auto[1]	auto[TokenCheck0St]	25	1			T40	1		T50	1		T53	1
auto[1]	auto[TokenCheck1St]	95	1			T42	1		T54	4		T50	1
auto[1]	auto[TransProgSt]	452	1			T40	6		T42	10		T54	7
auto[1]	auto[PostTransSt]	2621	1			T10	3		T15	2		T4	5
auto[1]	auto[ScrapSt]	38	1			T42	1		T55	2		T51	1
auto[1]	auto[EscalateSt]	1412729	1			T1	3038		T3	13194		T10	294
auto[1]	auto[InvalidSt]	7418	1			T1	31		T3	135		T11	26

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7621033	1			T1	12739		T2	144		T3	53905
auto[0]	auto[IdleSt]	22442823	1			T1	1290		T2	791		T3	22560
auto[0]	auto[ClkMuxSt]	35010	1			T2	1		T3	10		T10	4
auto[0]	auto[CntIncrSt]	34699	1			T2	1		T3	10		T10	4
auto[0]	auto[CntProgSt]	1549577	1			T2	12		T3	311		T10	8
auto[0]	auto[TransCheckSt]	26916	1			T3	10		T12	74		T13	41
auto[0]	auto[TokenHashSt]	36025284	1			T3	33985		T12	682		T13	684
auto[0]	auto[FlashRmaSt]	27570	1			T3	33		T12	20		T13	54
auto[0]	auto[TokenCheck0St]	12540	1			T3	10		T12	20		T13	16
auto[0]	auto[TokenCheck1St]	9205	1			T3	10		T12	5		T13	5
auto[0]	auto[TransProgSt]	374439	1			T3	384		T13	9		T15	10
auto[0]	auto[PostTransSt]	12721388	1			T2	77		T3	17304		T10	261
auto[0]	auto[ScrapSt]	122285	1			T3	174		T42	4		T43	1596
auto[0]	auto[EscalateSt]	6170629	1			T1	5036		T2	47		T3	59193
auto[0]	auto[InvalidSt]	14221130	1			T1	5229		T3	157027		T11	3661
auto[1]	auto[ResetSt]	163	1			T40	2		T42	3		T54	5
auto[1]	auto[IdleSt]	118	1			T42	3		T54	4		T51	5
auto[1]	auto[ClkMuxSt]	30	1			T40	3		T50	1		T51	1
auto[1]	auto[CntIncrSt]	34	1			T52	1		T53	1		T177	1
auto[1]	auto[CntProgSt]	704	1			T40	12		T42	17		T54	7
auto[1]	auto[TransCheckSt]	82	1			T40	1		T54	2		T55	2
auto[1]	auto[TokenHashSt]	472	1			T40	5		T42	2		T43	1
auto[1]	auto[FlashRmaSt]	48	1			T55	2		T52	3		T173	2
auto[1]	auto[TokenCheck0St]	28	1			T55	1		T50	1		T51	1
auto[1]	auto[TokenCheck1St]	95	1			T40	1		T42	1		T54	3
auto[1]	auto[TransProgSt]	470	1			T40	9		T42	11		T54	6
auto[1]	auto[PostTransSt]	2585	1			T2	1		T10	1		T13	4
auto[1]	auto[ScrapSt]	41	1			T42	2		T55	1		T51	1
auto[1]	auto[EscalateSt]	1426748	1			T1	3822		T2	98		T3	12906
auto[1]	auto[InvalidSt]	7569	1			T1	39		T3	132		T11	24