Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102250082

1

T1

6805

T2

1674

T3

31387

auto[1]

1423372

1

T1

198

T3

1287

T4

1386

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102229389

1

T1

6508

T2

1674

T3

31189

auto[1]

1444065

1

T1

495

T3

1485

T4

1584

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7655856	1			T1	1426		T2	73		T3	6768
auto[IdleSt]	21696721	1			T1	1285		T2	1601		T3	7066
auto[ClkMuxSt]	36733	1			T1	4		T3	54		T4	60
auto[CntIncrSt]	36441	1			T1	4		T3	54		T4	60
auto[CntProgSt]	1749148	1			T1	22		T3	115		T4	17462
auto[TransCheckSt]	28233	1			T1	4		T3	41		T4	47
auto[TokenHashSt]	38494333	1			T1	516		T3	2552		T4	518
auto[FlashRmaSt]	29221	1			T1	4		T3	39		T4	139
auto[TokenCheck0St]	13039	1			T1	4		T3	30		T4	39
auto[TokenCheck1St]	9747	1			T1	4		T3	19		T4	25
auto[TransProgSt]	452165	1			T1	20		T3	52		T4	10579
auto[PostTransSt]	13035251	1			T1	1086		T3	9019		T4	10070
auto[ScrapSt]	188340	1			T5	738		T19	1280		T26	9
auto[EscalateSt]	7155942	1			T1	1734		T3	3919		T4	4163
auto[InvalidSt]	13090206	1			T1	890		T3	2946		T4	3470

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2078	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	13090206	1			T1	890		T3	2946		T4	3470
EscalateSt	7155942	1			T1	1734		T3	3919		T4	4163
ScrapSt	188340	1			T5	738		T19	1280		T26	9
PostTransSt	13035251	1			T1	1086		T3	9019		T4	10070
TransProgSt	452165	1			T1	20		T3	52		T4	10579
TokenCheck1St	9747	1			T1	4		T3	19		T4	25
TokenCheck0St	13039	1			T1	4		T3	30		T4	39
FlashRmaSt	29221	1			T1	4		T3	39		T4	139
TokenHashSt	38494333	1			T1	516		T3	2552		T4	518
TransCheckSt	28233	1			T1	4		T3	41		T4	47
CntProgSt	1749148	1			T1	22		T3	115		T4	17462
CntIncrSt	36441	1			T1	4		T3	54		T4	60
ClkMuxSt	36733	1			T1	4		T3	54		T4	60
IdleSt	21696721	1			T1	1285		T2	1601		T3	7066
ResetSt	7655856	1			T1	1426		T2	73		T3	6768
arcs[ResetSt=>IdleSt]	55787	1			T1	12		T2	1		T3	70
arcs[IdleSt=>ScrapSt]	284	1			T5	2		T19	1		T26	3
arcs[IdleSt=>ClkMuxSt]	36501	1			T1	4		T3	54		T4	60
arcs[ClkMuxSt=>CntIncrSt]	36441	1			T1	4		T3	54		T4	60
arcs[CntIncrSt=>PostTransSt]	2002	1			T14	9		T15	11		T16	12
arcs[CntIncrSt=>CntProgSt]	34372	1			T1	4		T3	54		T4	60
arcs[CntProgSt=>PostTransSt]	4928	1			T3	13		T4	13		T7	14
arcs[CntProgSt=>TransCheckSt]	28233	1			T1	4		T3	41		T4	47
arcs[TransCheckSt=>PostTransSt]	3737	1			T13	31		T14	11		T22	46
arcs[TransCheckSt=>TokenHashSt]	24416	1			T1	4		T3	41		T4	47
arcs[TokenHashSt=>PostTransSt]	10696	1			T3	11		T4	8		T13	8
arcs[TokenHashSt=>FlashRmaSt]	13129	1			T1	4		T3	30		T4	39
arcs[FlashRmaSt=>TokenCheck0St]	13039	1			T1	4		T3	30		T4	39
arcs[TokenCheck0St=>PostTransSt]	3272	1			T3	11		T4	14		T13	10
arcs[TokenCheck0St=>TokenCheck1St]	9747	1			T1	4		T3	19		T4	25
arcs[TokenCheck1St=>PostTransSt]	703	1			T4	3		T13	12		T21	1
arcs[TransProgSt=>PostTransSt]	8098	1			T1	4		T3	19		T4	22
arcs[IdleSt=>EscalateSt]	181	1			T26	3		T51	4		T53	9
arcs[ClkMuxSt=>EscalateSt]	60	1			T26	3		T50	1		T51	2
arcs[CntIncrSt=>EscalateSt]	67	1			T26	2		T50	1		T52	4
arcs[CntProgSt=>EscalateSt]	1211	1			T26	39		T50	24		T51	6
arcs[TransCheckSt=>EscalateSt]	80	1			T51	4		T53	1		T59	2
arcs[TokenHashSt=>EscalateSt]	591	1			T26	9		T50	5		T51	12
arcs[FlashRmaSt=>EscalateSt]	90	1			T26	2		T50	1		T51	1
arcs[TokenCheck0St=>EscalateSt]	20	1			T52	2		T57	1		T58	1
arcs[TokenCheck1St=>EscalateSt]	146	1			T26	7		T50	1		T51	6
arcs[TransProgSt=>EscalateSt]	800	1			T26	20		T50	16		T51	12
arcs[PostTransSt=>EscalateSt]	5144	1			T3	13		T4	13		T7	14
arcs[InvalidSt=>EscalateSt]	14626	1			T1	7		T3	15		T4	17

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7655692	1			T1	1426		T2	73		T3	6768
auto[0]	auto[IdleSt]	21696600	1			T1	1285		T2	1601		T3	7066
auto[0]	auto[ClkMuxSt]	36691	1			T1	4		T3	54		T4	60
auto[0]	auto[CntIncrSt]	36398	1			T1	4		T3	54		T4	60
auto[0]	auto[CntProgSt]	1748353	1			T1	22		T3	115		T4	17462
auto[0]	auto[TransCheckSt]	28182	1			T1	4		T3	41		T4	47
auto[0]	auto[TokenHashSt]	38493950	1			T1	516		T3	2552		T4	518
auto[0]	auto[FlashRmaSt]	29161	1			T1	4		T3	39		T4	139
auto[0]	auto[TokenCheck0St]	13024	1			T1	4		T3	30		T4	39
auto[0]	auto[TokenCheck1St]	9658	1			T1	4		T3	19		T4	25
auto[0]	auto[TransProgSt]	451628	1			T1	20		T3	52		T4	10579
auto[0]	auto[PostTransSt]	13032682	1			T1	1086		T3	9015		T4	10063
auto[0]	auto[ScrapSt]	188288	1			T5	738		T19	1280		T26	6
auto[0]	auto[EscalateSt]	5744800	1			T1	1538		T3	2645		T4	2791
auto[0]	auto[InvalidSt]	13082897	1			T1	888		T3	2937		T4	3463
auto[1]	auto[ResetSt]	164	1			T26	5		T50	6		T51	3
auto[1]	auto[IdleSt]	121	1			T26	2		T51	1		T53	4
auto[1]	auto[ClkMuxSt]	42	1			T26	3		T50	1		T51	2
auto[1]	auto[CntIncrSt]	43	1			T26	1		T50	1		T52	2
auto[1]	auto[CntProgSt]	795	1			T26	22		T50	18		T51	3
auto[1]	auto[TransCheckSt]	51	1			T51	3		T59	1		T213	1
auto[1]	auto[TokenHashSt]	383	1			T26	7		T50	2		T51	9
auto[1]	auto[FlashRmaSt]	60	1			T50	1		T51	1		T214	1
auto[1]	auto[TokenCheck0St]	15	1			T57	1		T58	1		T213	1
auto[1]	auto[TokenCheck1St]	89	1			T26	5		T50	1		T51	2
auto[1]	auto[TransProgSt]	537	1			T26	10		T50	12		T51	10
auto[1]	auto[PostTransSt]	2569	1			T3	4		T4	7		T7	5
auto[1]	auto[ScrapSt]	52	1			T26	3		T52	2		T214	1
auto[1]	auto[EscalateSt]	1411142	1			T1	196		T3	1274		T4	1372
auto[1]	auto[InvalidSt]	7309	1			T1	2		T3	9		T4	7

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7655677	1			T1	1426		T2	73		T3	6768
auto[0]	auto[IdleSt]	21696591	1			T1	1285		T2	1601		T3	7066
auto[0]	auto[ClkMuxSt]	36698	1			T1	4		T3	54		T4	60
auto[0]	auto[CntIncrSt]	36395	1			T1	4		T3	54		T4	60
auto[0]	auto[CntProgSt]	1748342	1			T1	22		T3	115		T4	17462
auto[0]	auto[TransCheckSt]	28179	1			T1	4		T3	41		T4	47
auto[0]	auto[TokenHashSt]	38493948	1			T1	516		T3	2552		T4	518
auto[0]	auto[FlashRmaSt]	29155	1			T1	4		T3	39		T4	139
auto[0]	auto[TokenCheck0St]	13028	1			T1	4		T3	30		T4	39
auto[0]	auto[TokenCheck1St]	9641	1			T1	4		T3	19		T4	25
auto[0]	auto[TransProgSt]	451626	1			T1	20		T3	52		T4	10579
auto[0]	auto[PostTransSt]	13032610	1			T1	1086		T3	9010		T4	10064
auto[0]	auto[ScrapSt]	188289	1			T5	738		T19	1280		T26	7
auto[0]	auto[EscalateSt]	5724243	1			T1	1244		T3	2449		T4	2595
auto[0]	auto[InvalidSt]	13082889	1			T1	885		T3	2940		T4	3460
auto[1]	auto[ResetSt]	179	1			T26	5		T50	3		T51	5
auto[1]	auto[IdleSt]	130	1			T26	3		T51	3		T53	8
auto[1]	auto[ClkMuxSt]	35	1			T53	1		T59	2		T215	1
auto[1]	auto[CntIncrSt]	46	1			T26	2		T50	1		T52	3
auto[1]	auto[CntProgSt]	806	1			T26	32		T50	17		T51	4
auto[1]	auto[TransCheckSt]	54	1			T51	3		T53	1		T59	1
auto[1]	auto[TokenHashSt]	385	1			T26	6		T50	4		T51	6
auto[1]	auto[FlashRmaSt]	66	1			T26	2		T51	1		T214	1
auto[1]	auto[TokenCheck0St]	11	1			T52	2		T213	1		T216	1
auto[1]	auto[TokenCheck1St]	106	1			T26	5		T50	1		T51	5
auto[1]	auto[TransProgSt]	539	1			T26	15		T50	9		T51	5
auto[1]	auto[PostTransSt]	2641	1			T3	9		T4	6		T7	9
auto[1]	auto[ScrapSt]	51	1			T26	2		T51	1		T52	1
auto[1]	auto[EscalateSt]	1431699	1			T1	490		T3	1470		T4	1568
auto[1]	auto[InvalidSt]	7317	1			T1	5		T3	6		T4	10