Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56573 |
1 |
|
|
T2 |
73 |
|
T3 |
1149 |
|
T4 |
89 |
auto[1] |
2102 |
1 |
|
|
T3 |
35 |
|
T9 |
6 |
|
T15 |
5 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57876 |
1 |
|
|
T2 |
59 |
|
T3 |
1184 |
|
T4 |
89 |
auto[1] |
799 |
1 |
|
|
T2 |
14 |
|
T42 |
13 |
|
T61 |
19 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56496 |
1 |
|
|
T2 |
73 |
|
T3 |
1129 |
|
T4 |
76 |
auto[1] |
2179 |
1 |
|
|
T3 |
55 |
|
T4 |
13 |
|
T14 |
10 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56579 |
1 |
|
|
T2 |
73 |
|
T3 |
1103 |
|
T4 |
80 |
auto[1] |
2096 |
1 |
|
|
T3 |
81 |
|
T4 |
9 |
|
T14 |
15 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56470 |
1 |
|
|
T2 |
73 |
|
T3 |
1119 |
|
T4 |
75 |
auto[1] |
2205 |
1 |
|
|
T3 |
65 |
|
T4 |
14 |
|
T14 |
11 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
53384 |
1 |
|
|
T2 |
73 |
|
T3 |
962 |
|
T4 |
89 |
no_err_inj |
5291 |
1 |
|
|
T3 |
222 |
|
T10 |
10 |
|
T14 |
18 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56530 |
1 |
|
|
T2 |
73 |
|
T3 |
1144 |
|
T4 |
89 |
auto[1] |
2145 |
1 |
|
|
T3 |
40 |
|
T9 |
10 |
|
T15 |
7 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57957 |
1 |
|
|
T2 |
61 |
|
T3 |
1184 |
|
T4 |
89 |
auto[1] |
718 |
1 |
|
|
T2 |
12 |
|
T42 |
14 |
|
T61 |
14 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40680 |
1 |
|
|
T2 |
73 |
|
T3 |
402 |
|
T11 |
75 |
auto[1] |
17995 |
1 |
|
|
T3 |
782 |
|
T4 |
89 |
|
T9 |
70 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56477 |
1 |
|
|
T2 |
73 |
|
T3 |
1116 |
|
T4 |
79 |
auto[1] |
2198 |
1 |
|
|
T3 |
68 |
|
T4 |
10 |
|
T14 |
9 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56632 |
1 |
|
|
T2 |
73 |
|
T3 |
1126 |
|
T4 |
81 |
auto[1] |
2043 |
1 |
|
|
T3 |
58 |
|
T4 |
8 |
|
T14 |
7 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56573 |
1 |
|
|
T2 |
73 |
|
T3 |
1130 |
|
T4 |
83 |
auto[1] |
2102 |
1 |
|
|
T3 |
54 |
|
T4 |
6 |
|
T14 |
11 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56626 |
1 |
|
|
T2 |
73 |
|
T3 |
1135 |
|
T4 |
89 |
auto[1] |
2049 |
1 |
|
|
T3 |
49 |
|
T9 |
7 |
|
T15 |
10 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56030 |
1 |
|
|
T2 |
73 |
|
T3 |
1110 |
|
T4 |
89 |
auto[1] |
2645 |
1 |
|
|
T3 |
74 |
|
T21 |
5 |
|
T15 |
51 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57943 |
1 |
|
|
T2 |
53 |
|
T3 |
1184 |
|
T4 |
89 |
auto[1] |
732 |
1 |
|
|
T2 |
20 |
|
T42 |
19 |
|
T61 |
10 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57970 |
1 |
|
|
T2 |
64 |
|
T3 |
1184 |
|
T4 |
89 |
auto[1] |
705 |
1 |
|
|
T2 |
9 |
|
T42 |
14 |
|
T61 |
8 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57909 |
1 |
|
|
T2 |
55 |
|
T3 |
1184 |
|
T4 |
89 |
auto[1] |
766 |
1 |
|
|
T2 |
18 |
|
T42 |
12 |
|
T61 |
14 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55858 |
1 |
|
|
T2 |
73 |
|
T3 |
1119 |
|
T4 |
89 |
auto[1] |
2817 |
1 |
|
|
T3 |
65 |
|
T14 |
12 |
|
T15 |
22 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54938 |
1 |
|
|
T2 |
73 |
|
T3 |
1184 |
|
T4 |
89 |
auto[1] |
3737 |
1 |
|
|
T20 |
78 |
|
T46 |
81 |
|
T31 |
58 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56523 |
1 |
|
|
T2 |
73 |
|
T3 |
1124 |
|
T4 |
81 |
auto[1] |
2152 |
1 |
|
|
T3 |
60 |
|
T4 |
8 |
|
T14 |
10 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56587 |
1 |
|
|
T2 |
73 |
|
T3 |
1124 |
|
T4 |
76 |
auto[1] |
2088 |
1 |
|
|
T3 |
60 |
|
T4 |
13 |
|
T14 |
12 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56527 |
1 |
|
|
T2 |
73 |
|
T3 |
1125 |
|
T4 |
81 |
auto[1] |
2148 |
1 |
|
|
T3 |
59 |
|
T4 |
8 |
|
T14 |
6 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56620 |
1 |
|
|
T2 |
73 |
|
T3 |
1151 |
|
T4 |
89 |
auto[1] |
2055 |
1 |
|
|
T3 |
33 |
|
T9 |
5 |
|
T15 |
5 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52872 |
1 |
|
|
T2 |
73 |
|
T3 |
1130 |
|
T4 |
89 |
auto[1] |
5803 |
1 |
|
|
T3 |
54 |
|
T9 |
7 |
|
T11 |
75 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54913 |
1 |
|
|
T2 |
73 |
|
T3 |
1184 |
|
T4 |
89 |
auto[1] |
3762 |
1 |
|
|
T34 |
68 |
|
T59 |
87 |
|
T60 |
84 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58675 |
1 |
|
|
T2 |
73 |
|
T3 |
1184 |
|
T4 |
89 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56593 |
1 |
|
|
T2 |
73 |
|
T3 |
1145 |
|
T4 |
89 |
auto[1] |
2082 |
1 |
|
|
T3 |
39 |
|
T9 |
13 |
|
T15 |
6 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56659 |
1 |
|
|
T2 |
73 |
|
T3 |
1151 |
|
T4 |
89 |
auto[1] |
2016 |
1 |
|
|
T3 |
33 |
|
T9 |
10 |
|
T15 |
8 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56618 |
1 |
|
|
T2 |
73 |
|
T3 |
1139 |
|
T4 |
89 |
auto[1] |
2057 |
1 |
|
|
T3 |
45 |
|
T9 |
12 |
|
T15 |
4 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
52011 |
1 |
|
|
T2 |
73 |
|
T3 |
929 |
|
T4 |
89 |
auto[0] |
no_err_inj |
3847 |
1 |
|
|
T3 |
190 |
|
T10 |
10 |
|
T14 |
10 |
auto[1] |
err_inj |
1373 |
1 |
|
|
T3 |
33 |
|
T14 |
4 |
|
T15 |
9 |
auto[1] |
no_err_inj |
1444 |
1 |
|
|
T3 |
32 |
|
T14 |
8 |
|
T15 |
13 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
53933 |
1 |
|
|
T2 |
73 |
|
T3 |
1061 |
|
T4 |
76 |
auto[0] |
auto[1] |
1925 |
1 |
|
|
T3 |
58 |
|
T4 |
13 |
|
T14 |
10 |
auto[1] |
auto[0] |
2654 |
1 |
|
|
T3 |
63 |
|
T14 |
10 |
|
T15 |
22 |
auto[1] |
auto[1] |
163 |
1 |
|
|
T3 |
2 |
|
T14 |
2 |
|
T80 |
3 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
53950 |
1 |
|
|
T2 |
73 |
|
T3 |
1063 |
|
T4 |
81 |
auto[0] |
auto[1] |
1908 |
1 |
|
|
T3 |
56 |
|
T4 |
8 |
|
T14 |
7 |
auto[1] |
auto[0] |
2682 |
1 |
|
|
T3 |
63 |
|
T14 |
12 |
|
T15 |
22 |
auto[1] |
auto[1] |
135 |
1 |
|
|
T3 |
2 |
|
T80 |
4 |
|
T197 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
53859 |
1 |
|
|
T2 |
73 |
|
T3 |
1064 |
|
T4 |
81 |
auto[0] |
auto[1] |
1999 |
1 |
|
|
T3 |
55 |
|
T4 |
8 |
|
T14 |
6 |
auto[1] |
auto[0] |
2668 |
1 |
|
|
T3 |
61 |
|
T14 |
12 |
|
T15 |
20 |
auto[1] |
auto[1] |
149 |
1 |
|
|
T3 |
4 |
|
T15 |
2 |
|
T37 |
2 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
53903 |
1 |
|
|
T2 |
73 |
|
T3 |
1046 |
|
T4 |
80 |
auto[0] |
auto[1] |
1955 |
1 |
|
|
T3 |
73 |
|
T4 |
9 |
|
T14 |
15 |
auto[1] |
auto[0] |
2676 |
1 |
|
|
T3 |
57 |
|
T14 |
12 |
|
T15 |
21 |
auto[1] |
auto[1] |
141 |
1 |
|
|
T3 |
8 |
|
T15 |
1 |
|
T80 |
4 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
53827 |
1 |
|
|
T2 |
73 |
|
T3 |
1056 |
|
T4 |
75 |
auto[0] |
auto[1] |
2031 |
1 |
|
|
T3 |
63 |
|
T4 |
14 |
|
T14 |
11 |
auto[1] |
auto[0] |
2643 |
1 |
|
|
T3 |
63 |
|
T14 |
12 |
|
T15 |
22 |
auto[1] |
auto[1] |
174 |
1 |
|
|
T3 |
2 |
|
T37 |
1 |
|
T80 |
5 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
53831 |
1 |
|
|
T2 |
73 |
|
T3 |
1069 |
|
T4 |
76 |
auto[0] |
auto[1] |
2027 |
1 |
|
|
T3 |
50 |
|
T4 |
13 |
|
T14 |
10 |
auto[1] |
auto[0] |
2665 |
1 |
|
|
T3 |
60 |
|
T14 |
12 |
|
T15 |
20 |
auto[1] |
auto[1] |
152 |
1 |
|
|
T3 |
5 |
|
T15 |
2 |
|
T37 |
2 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39422 |
1 |
|
|
T2 |
73 |
|
T3 |
389 |
|
T11 |
75 |
auto[0] |
auto[1] |
1258 |
1 |
|
|
T3 |
13 |
|
T15 |
5 |
|
T18 |
12 |
auto[1] |
auto[0] |
17151 |
1 |
|
|
T3 |
760 |
|
T4 |
89 |
|
T9 |
64 |
auto[1] |
auto[1] |
844 |
1 |
|
|
T3 |
22 |
|
T9 |
6 |
|
T17 |
5 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39393 |
1 |
|
|
T2 |
73 |
|
T3 |
389 |
|
T11 |
75 |
auto[0] |
auto[1] |
1287 |
1 |
|
|
T3 |
13 |
|
T15 |
7 |
|
T18 |
6 |
auto[1] |
auto[0] |
17137 |
1 |
|
|
T3 |
755 |
|
T4 |
89 |
|
T9 |
60 |
auto[1] |
auto[1] |
858 |
1 |
|
|
T3 |
27 |
|
T9 |
10 |
|
T17 |
8 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39299 |
1 |
|
|
T2 |
73 |
|
T3 |
361 |
|
T11 |
75 |
auto[0] |
auto[1] |
1381 |
1 |
|
|
T3 |
41 |
|
T21 |
5 |
|
T64 |
10 |
auto[1] |
auto[0] |
16731 |
1 |
|
|
T3 |
749 |
|
T4 |
89 |
|
T9 |
70 |
auto[1] |
auto[1] |
1264 |
1 |
|
|
T3 |
33 |
|
T15 |
51 |
|
T18 |
8 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39434 |
1 |
|
|
T2 |
73 |
|
T3 |
375 |
|
T11 |
75 |
auto[0] |
auto[1] |
1246 |
1 |
|
|
T3 |
27 |
|
T15 |
10 |
|
T18 |
12 |
auto[1] |
auto[0] |
17192 |
1 |
|
|
T3 |
760 |
|
T4 |
89 |
|
T9 |
63 |
auto[1] |
auto[1] |
803 |
1 |
|
|
T3 |
22 |
|
T9 |
7 |
|
T17 |
11 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35724 |
1 |
|
|
T2 |
73 |
|
T3 |
383 |
|
T14 |
10 |
auto[0] |
auto[1] |
4956 |
1 |
|
|
T3 |
19 |
|
T11 |
75 |
|
T15 |
6 |
auto[1] |
auto[0] |
17148 |
1 |
|
|
T3 |
747 |
|
T4 |
89 |
|
T9 |
63 |
auto[1] |
auto[1] |
847 |
1 |
|
|
T3 |
35 |
|
T9 |
7 |
|
T17 |
11 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39427 |
1 |
|
|
T2 |
73 |
|
T3 |
394 |
|
T11 |
75 |
auto[0] |
auto[1] |
1253 |
1 |
|
|
T3 |
8 |
|
T22 |
11 |
|
T15 |
12 |
auto[1] |
auto[0] |
17160 |
1 |
|
|
T3 |
730 |
|
T4 |
76 |
|
T9 |
70 |
auto[1] |
auto[1] |
835 |
1 |
|
|
T3 |
52 |
|
T4 |
13 |
|
T14 |
12 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39346 |
1 |
|
|
T2 |
73 |
|
T3 |
386 |
|
T11 |
75 |
auto[0] |
auto[1] |
1334 |
1 |
|
|
T3 |
16 |
|
T22 |
7 |
|
T15 |
23 |
auto[1] |
auto[0] |
17177 |
1 |
|
|
T3 |
738 |
|
T4 |
81 |
|
T9 |
70 |
auto[1] |
auto[1] |
818 |
1 |
|
|
T3 |
44 |
|
T4 |
8 |
|
T14 |
10 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39387 |
1 |
|
|
T2 |
73 |
|
T3 |
386 |
|
T11 |
75 |
auto[0] |
auto[1] |
1293 |
1 |
|
|
T3 |
16 |
|
T22 |
5 |
|
T15 |
25 |
auto[1] |
auto[0] |
17245 |
1 |
|
|
T3 |
740 |
|
T4 |
81 |
|
T9 |
70 |
auto[1] |
auto[1] |
750 |
1 |
|
|
T3 |
42 |
|
T4 |
8 |
|
T14 |
7 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39415 |
1 |
|
|
T2 |
73 |
|
T3 |
389 |
|
T11 |
75 |
auto[0] |
auto[1] |
1265 |
1 |
|
|
T3 |
13 |
|
T22 |
8 |
|
T15 |
15 |
auto[1] |
auto[0] |
17062 |
1 |
|
|
T3 |
727 |
|
T4 |
79 |
|
T9 |
70 |
auto[1] |
auto[1] |
933 |
1 |
|
|
T3 |
55 |
|
T4 |
10 |
|
T14 |
9 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39417 |
1 |
|
|
T2 |
73 |
|
T3 |
382 |
|
T11 |
75 |
auto[0] |
auto[1] |
1263 |
1 |
|
|
T3 |
20 |
|
T22 |
12 |
|
T15 |
15 |
auto[1] |
auto[0] |
17162 |
1 |
|
|
T3 |
721 |
|
T4 |
80 |
|
T9 |
70 |
auto[1] |
auto[1] |
833 |
1 |
|
|
T3 |
61 |
|
T4 |
9 |
|
T14 |
15 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39376 |
1 |
|
|
T2 |
73 |
|
T3 |
394 |
|
T11 |
75 |
auto[0] |
auto[1] |
1304 |
1 |
|
|
T3 |
8 |
|
T22 |
14 |
|
T15 |
20 |
auto[1] |
auto[0] |
17120 |
1 |
|
|
T3 |
735 |
|
T4 |
76 |
|
T9 |
70 |
auto[1] |
auto[1] |
875 |
1 |
|
|
T3 |
47 |
|
T4 |
13 |
|
T14 |
10 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39430 |
1 |
|
|
T2 |
73 |
|
T3 |
384 |
|
T11 |
75 |
auto[0] |
auto[1] |
1250 |
1 |
|
|
T3 |
18 |
|
T15 |
4 |
|
T18 |
18 |
auto[1] |
auto[0] |
17188 |
1 |
|
|
T3 |
755 |
|
T4 |
89 |
|
T9 |
58 |
auto[1] |
auto[1] |
807 |
1 |
|
|
T3 |
27 |
|
T9 |
12 |
|
T17 |
4 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39498 |
1 |
|
|
T2 |
73 |
|
T3 |
389 |
|
T11 |
75 |
auto[0] |
auto[1] |
1182 |
1 |
|
|
T3 |
13 |
|
T15 |
8 |
|
T18 |
10 |
auto[1] |
auto[0] |
17161 |
1 |
|
|
T3 |
762 |
|
T4 |
89 |
|
T9 |
60 |
auto[1] |
auto[1] |
834 |
1 |
|
|
T3 |
20 |
|
T9 |
10 |
|
T17 |
6 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
39045 |
1 |
|
|
T2 |
73 |
|
T3 |
370 |
|
T11 |
75 |
auto[0] |
auto[1] |
1635 |
1 |
|
|
T3 |
32 |
|
T80 |
64 |
|
T198 |
14 |
auto[1] |
auto[0] |
16813 |
1 |
|
|
T3 |
749 |
|
T4 |
89 |
|
T9 |
70 |
auto[1] |
auto[1] |
1182 |
1 |
|
|
T3 |
33 |
|
T14 |
12 |
|
T15 |
22 |