Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
99.19 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv



Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 1 63 98.44
Crosses 60 0 60 100.00


Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
esc_scrap_state0_i_cp 2 0 2 100.00 100 1 1 2
esc_scrap_state1_i_cp 2 0 2 100.00 100 1 1 2
fsm_state_q 15 0 15 100.00 100 1 1 0
fsm_state_q_cp 45 1 44 97.78 100 1 1 0


Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
scrap_state0_xp 30 0 30 100.00 100 1 1 0
scrap_state1_xp 30 0 30 100.00 100 1 1 0


Summary for Variable esc_scrap_state0_i_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for esc_scrap_state0_i_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 113489946 1 T1 79989 T2 34495 T3 467820
auto[1] 1507855 1 T2 693 T3 27208 T4 3724



Summary for Variable esc_scrap_state1_i_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for esc_scrap_state1_i_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 113490008 1 T1 79989 T2 33604 T3 467788
auto[1] 1507793 1 T2 1584 T3 27527 T4 3626



Summary for Variable fsm_state_q

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 15 0 15 100.00


Automatically Generated Bins for fsm_state_q

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[ResetSt] 7798875 1 T1 108 T2 7734 T3 214540
auto[IdleSt] 23729837 1 T1 79881 T2 8068 T3 498018
auto[ClkMuxSt] 38434 1 T2 64 T3 638 T9 70
auto[CntIncrSt] 38150 1 T2 64 T3 619 T9 70
auto[CntProgSt] 2024376 1 T2 682 T3 203080 T9 1099
auto[TransCheckSt] 29479 1 T2 50 T3 477 T9 54
auto[TokenHashSt] 47321491 1 T2 2239 T3 255989 T9 3253
auto[FlashRmaSt] 29672 1 T2 70 T3 611 T9 22
auto[TokenCheck0St] 13446 1 T2 39 T3 304 T9 17
auto[TokenCheck1St] 9910 1 T2 27 T3 265 T9 7
auto[TransProgSt] 594123 1 T2 372 T3 99212 T9 138
auto[PostTransSt] 14133660 1 T2 10744 T3 300139 T9 54036
auto[ScrapSt] 175584 1 T3 4900 T10 309 T14 175
auto[EscalateSt] 7268304 1 T2 3366 T3 230471 T4 52528
auto[InvalidSt] 11790336 1 T2 1669 T3 592189 T4 191395



Summary for Variable fsm_state_q_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 45 1 44 97.78


User Defined Bins for fsm_state_q_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
arcs[TokenCheck1St=>TokenCheck1St] 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
IllegalEncoding 2124 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
InvalidSt 11790336 1 T2 1669 T3 592189 T4 191395
EscalateSt 7268304 1 T2 3366 T3 230471 T4 52528
ScrapSt 175584 1 T3 4900 T10 309 T14 175
PostTransSt 14133660 1 T2 10744 T3 300139 T9 54036
TransProgSt 594123 1 T2 372 T3 99212 T9 138
TokenCheck1St 9910 1 T2 27 T3 265 T9 7
TokenCheck0St 13446 1 T2 39 T3 304 T9 17
FlashRmaSt 29672 1 T2 70 T3 611 T9 22
TokenHashSt 47321491 1 T2 2239 T3 255989 T9 3253
TransCheckSt 29479 1 T2 50 T3 477 T9 54
CntProgSt 2024376 1 T2 682 T3 203080 T9 1099
CntIncrSt 38150 1 T2 64 T3 619 T9 70
ClkMuxSt 38434 1 T2 64 T3 638 T9 70
IdleSt 23729837 1 T1 79881 T2 8068 T3 498018
ResetSt 7798875 1 T1 108 T2 7734 T3 214540
arcs[ResetSt=>IdleSt] 58860 1 T1 1 T2 74 T3 1166
arcs[IdleSt=>ScrapSt] 290 1 T3 12 T10 1 T14 2
arcs[IdleSt=>ClkMuxSt] 38210 1 T2 64 T3 619 T9 70
arcs[ClkMuxSt=>CntIncrSt] 38150 1 T2 64 T3 619 T9 70
arcs[CntIncrSt=>PostTransSt] 2016 1 T3 33 T9 10 T15 8
arcs[CntIncrSt=>CntProgSt] 36053 1 T2 64 T3 586 T9 60
arcs[CntProgSt=>PostTransSt] 5496 1 T2 14 T3 109 T9 6
arcs[CntProgSt=>TransCheckSt] 29479 1 T2 50 T3 477 T9 54
arcs[TransCheckSt=>PostTransSt] 3974 1 T3 45 T9 12 T15 4
arcs[TransCheckSt=>TokenHashSt] 25387 1 T2 50 T3 432 T9 42
arcs[TokenHashSt=>PostTransSt] 11119 1 T2 11 T3 128 T9 25
arcs[TokenHashSt=>FlashRmaSt] 13548 1 T2 39 T3 304 T9 17
arcs[FlashRmaSt=>TokenCheck0St] 13446 1 T2 39 T3 304 T9 17
arcs[TokenCheck0St=>PostTransSt] 3511 1 T2 12 T3 39 T9 10
arcs[TokenCheck0St=>TokenCheck1St] 9910 1 T2 27 T3 265 T9 7
arcs[TokenCheck1St=>PostTransSt] 664 1 T15 1 T23 3 T18 4
arcs[TransProgSt=>PostTransSt] 8370 1 T2 27 T3 265 T9 7
arcs[IdleSt=>EscalateSt] 167 1 T47 4 T48 3 T50 8
arcs[ClkMuxSt=>EscalateSt] 60 1 T46 2 T47 2 T48 3
arcs[CntIncrSt=>EscalateSt] 81 1 T20 1 T46 2 T49 3
arcs[CntProgSt=>EscalateSt] 1078 1 T20 33 T46 33 T31 16
arcs[TransCheckSt=>EscalateSt] 118 1 T54 3 T50 9 T55 1
arcs[TokenHashSt=>EscalateSt] 720 1 T20 10 T46 11 T31 9
arcs[FlashRmaSt=>EscalateSt] 102 1 T20 4 T46 5 T31 2
arcs[TokenCheck0St=>EscalateSt] 25 1 T31 1 T49 1 T53 2
arcs[TokenCheck1St=>EscalateSt] 134 1 T20 2 T46 4 T31 2
arcs[TransProgSt=>EscalateSt] 742 1 T20 20 T46 17 T31 24
arcs[PostTransSt=>EscalateSt] 5748 1 T2 14 T3 109 T9 6
arcs[InvalidSt=>EscalateSt] 15683 1 T2 9 T3 448 T4 75



Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 30 0 30 100.00


Automatically Generated Cross Bins for scrap_state0_xp

Bins
esc_scrap_state0_i_cpfsm_state_qCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[ResetSt] 7798701 1 T1 108 T2 7734 T3 214540
auto[0] auto[IdleSt] 23729715 1 T1 79881 T2 8068 T3 498018
auto[0] auto[ClkMuxSt] 38401 1 T2 64 T3 638 T9 70
auto[0] auto[CntIncrSt] 38105 1 T2 64 T3 619 T9 70
auto[0] auto[CntProgSt] 2023640 1 T2 682 T3 203080 T9 1099
auto[0] auto[TransCheckSt] 29394 1 T2 50 T3 477 T9 54
auto[0] auto[TokenHashSt] 47321016 1 T2 2239 T3 255989 T9 3253
auto[0] auto[FlashRmaSt] 29601 1 T2 70 T3 611 T9 22
auto[0] auto[TokenCheck0St] 13428 1 T2 39 T3 304 T9 17
auto[0] auto[TokenCheck1St] 9819 1 T2 27 T3 265 T9 7
auto[0] auto[TransProgSt] 593625 1 T2 372 T3 99212 T9 138
auto[0] auto[PostTransSt] 14130726 1 T2 10739 T3 300090 T9 54033
auto[0] auto[ScrapSt] 175545 1 T3 4900 T10 309 T14 175
auto[0] auto[EscalateSt] 5773564 1 T2 2680 T3 203540 T4 48842
auto[0] auto[InvalidSt] 11782542 1 T2 1667 T3 591961 T4 191357
auto[1] auto[ResetSt] 174 1 T20 4 T46 2 T31 2
auto[1] auto[IdleSt] 122 1 T47 3 T48 1 T50 6
auto[1] auto[ClkMuxSt] 33 1 T46 1 T47 2 T48 2
auto[1] auto[CntIncrSt] 45 1 T20 1 T46 1 T49 3
auto[1] auto[CntProgSt] 736 1 T20 22 T46 26 T31 9
auto[1] auto[TransCheckSt] 85 1 T54 3 T50 6 T53 3
auto[1] auto[TokenHashSt] 475 1 T20 6 T46 8 T31 5
auto[1] auto[FlashRmaSt] 71 1 T20 3 T46 2 T31 2
auto[1] auto[TokenCheck0St] 18 1 T49 1 T53 1 T157 1
auto[1] auto[TokenCheck1St] 91 1 T20 2 T46 3 T31 2
auto[1] auto[TransProgSt] 498 1 T20 13 T46 11 T31 17
auto[1] auto[PostTransSt] 2934 1 T2 5 T3 49 T9 3
auto[1] auto[ScrapSt] 39 1 T20 1 T46 2 T49 2
auto[1] auto[EscalateSt] 1494740 1 T2 686 T3 26931 T4 3686
auto[1] auto[InvalidSt] 7794 1 T2 2 T3 228 T4 38



Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 30 0 30 100.00


Automatically Generated Cross Bins for scrap_state1_xp

Bins
esc_scrap_state1_i_cpfsm_state_qCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[ResetSt] 7798714 1 T1 108 T2 7734 T3 214540
auto[0] auto[IdleSt] 23729730 1 T1 79881 T2 8068 T3 498018
auto[0] auto[ClkMuxSt] 38396 1 T2 64 T3 638 T9 70
auto[0] auto[CntIncrSt] 38092 1 T2 64 T3 619 T9 70
auto[0] auto[CntProgSt] 2023650 1 T2 682 T3 203080 T9 1099
auto[0] auto[TransCheckSt] 29403 1 T2 50 T3 477 T9 54
auto[0] auto[TokenHashSt] 47321011 1 T2 2239 T3 255989 T9 3253
auto[0] auto[FlashRmaSt] 29604 1 T2 70 T3 611 T9 22
auto[0] auto[TokenCheck0St] 13428 1 T2 39 T3 304 T9 17
auto[0] auto[TokenCheck1St] 9824 1 T2 27 T3 265 T9 7
auto[0] auto[TransProgSt] 593614 1 T2 372 T3 99212 T9 138
auto[0] auto[PostTransSt] 14130773 1 T2 10735 T3 300079 T9 54033
auto[0] auto[ScrapSt] 175553 1 T3 4900 T10 309 T14 175
auto[0] auto[EscalateSt] 5773645 1 T2 1798 T3 203224 T4 48939
auto[0] auto[InvalidSt] 11782447 1 T2 1662 T3 591969 T4 191358
auto[1] auto[ResetSt] 161 1 T20 4 T46 1 T31 2
auto[1] auto[IdleSt] 107 1 T47 2 T48 3 T50 7
auto[1] auto[ClkMuxSt] 38 1 T46 1 T48 1 T55 1
auto[1] auto[CntIncrSt] 58 1 T20 1 T46 1 T49 3
auto[1] auto[CntProgSt] 726 1 T20 24 T46 20 T31 11
auto[1] auto[TransCheckSt] 76 1 T54 3 T50 6 T55 1
auto[1] auto[TokenHashSt] 480 1 T20 4 T46 7 T31 7
auto[1] auto[FlashRmaSt] 68 1 T20 3 T46 5 T31 1
auto[1] auto[TokenCheck0St] 18 1 T31 1 T53 1 T157 1
auto[1] auto[TokenCheck1St] 86 1 T20 1 T46 3 T31 1
auto[1] auto[TransProgSt] 509 1 T20 15 T46 11 T31 17
auto[1] auto[PostTransSt] 2887 1 T2 9 T3 60 T9 3
auto[1] auto[ScrapSt] 31 1 T20 1 T46 1 T54 1
auto[1] auto[EscalateSt] 1494659 1 T2 1568 T3 27247 T4 3589
auto[1] auto[InvalidSt] 7889 1 T2 7 T3 220 T4 37

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