Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53349 |
1 |
|
|
T1 |
193 |
|
T2 |
1 |
|
T3 |
13 |
auto[1] |
1916 |
1 |
|
|
T14 |
21 |
|
T15 |
12 |
|
T16 |
11 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54526 |
1 |
|
|
T1 |
193 |
|
T2 |
1 |
|
T3 |
13 |
auto[1] |
739 |
1 |
|
|
T21 |
8 |
|
T47 |
8 |
|
T18 |
21 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53207 |
1 |
|
|
T1 |
170 |
|
T2 |
1 |
|
T3 |
12 |
auto[1] |
2058 |
1 |
|
|
T1 |
23 |
|
T3 |
1 |
|
T4 |
8 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53212 |
1 |
|
|
T1 |
178 |
|
T2 |
1 |
|
T3 |
13 |
auto[1] |
2053 |
1 |
|
|
T1 |
15 |
|
T4 |
15 |
|
T6 |
8 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53201 |
1 |
|
|
T1 |
176 |
|
T2 |
1 |
|
T3 |
12 |
auto[1] |
2064 |
1 |
|
|
T1 |
17 |
|
T3 |
1 |
|
T4 |
11 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
50428 |
1 |
|
|
T1 |
162 |
|
T3 |
5 |
|
T4 |
80 |
no_err_inj |
4837 |
1 |
|
|
T1 |
31 |
|
T2 |
1 |
|
T3 |
8 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53460 |
1 |
|
|
T1 |
193 |
|
T2 |
1 |
|
T3 |
13 |
auto[1] |
1805 |
1 |
|
|
T14 |
15 |
|
T15 |
14 |
|
T16 |
11 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54523 |
1 |
|
|
T1 |
193 |
|
T2 |
1 |
|
T3 |
13 |
auto[1] |
742 |
1 |
|
|
T21 |
12 |
|
T47 |
10 |
|
T18 |
22 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38149 |
1 |
|
|
T1 |
109 |
|
T2 |
1 |
|
T3 |
13 |
auto[1] |
17116 |
1 |
|
|
T1 |
84 |
|
T5 |
15 |
|
T6 |
87 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53221 |
1 |
|
|
T1 |
174 |
|
T2 |
1 |
|
T3 |
12 |
auto[1] |
2044 |
1 |
|
|
T1 |
19 |
|
T3 |
1 |
|
T4 |
5 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53188 |
1 |
|
|
T1 |
171 |
|
T2 |
1 |
|
T3 |
13 |
auto[1] |
2077 |
1 |
|
|
T1 |
22 |
|
T4 |
8 |
|
T6 |
8 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53281 |
1 |
|
|
T1 |
179 |
|
T2 |
1 |
|
T3 |
13 |
auto[1] |
1984 |
1 |
|
|
T1 |
14 |
|
T4 |
7 |
|
T6 |
11 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53500 |
1 |
|
|
T1 |
193 |
|
T2 |
1 |
|
T3 |
13 |
auto[1] |
1765 |
1 |
|
|
T14 |
15 |
|
T15 |
18 |
|
T16 |
8 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52844 |
1 |
|
|
T1 |
193 |
|
T2 |
1 |
|
T3 |
13 |
auto[1] |
2421 |
1 |
|
|
T20 |
8 |
|
T14 |
22 |
|
T59 |
5 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54475 |
1 |
|
|
T1 |
193 |
|
T2 |
1 |
|
T3 |
13 |
auto[1] |
790 |
1 |
|
|
T21 |
19 |
|
T47 |
14 |
|
T18 |
18 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54535 |
1 |
|
|
T1 |
193 |
|
T2 |
1 |
|
T3 |
13 |
auto[1] |
730 |
1 |
|
|
T21 |
11 |
|
T47 |
17 |
|
T18 |
15 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54552 |
1 |
|
|
T1 |
193 |
|
T2 |
1 |
|
T3 |
13 |
auto[1] |
713 |
1 |
|
|
T21 |
13 |
|
T47 |
9 |
|
T18 |
19 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52488 |
1 |
|
|
T1 |
182 |
|
T2 |
1 |
|
T4 |
80 |
auto[1] |
2777 |
1 |
|
|
T1 |
11 |
|
T3 |
13 |
|
T14 |
65 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51399 |
1 |
|
|
T1 |
193 |
|
T2 |
1 |
|
T3 |
13 |
auto[1] |
3866 |
1 |
|
|
T22 |
87 |
|
T26 |
85 |
|
T27 |
79 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53219 |
1 |
|
|
T1 |
174 |
|
T2 |
1 |
|
T3 |
13 |
auto[1] |
2046 |
1 |
|
|
T1 |
19 |
|
T4 |
7 |
|
T6 |
10 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53276 |
1 |
|
|
T1 |
173 |
|
T2 |
1 |
|
T3 |
12 |
auto[1] |
1989 |
1 |
|
|
T1 |
20 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53268 |
1 |
|
|
T1 |
180 |
|
T2 |
1 |
|
T3 |
12 |
auto[1] |
1997 |
1 |
|
|
T1 |
13 |
|
T3 |
1 |
|
T4 |
6 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53398 |
1 |
|
|
T1 |
193 |
|
T2 |
1 |
|
T3 |
13 |
auto[1] |
1867 |
1 |
|
|
T14 |
18 |
|
T15 |
7 |
|
T16 |
5 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49702 |
1 |
|
|
T1 |
193 |
|
T2 |
1 |
|
T3 |
13 |
auto[1] |
5563 |
1 |
|
|
T14 |
18 |
|
T24 |
79 |
|
T15 |
9 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51488 |
1 |
|
|
T1 |
193 |
|
T2 |
1 |
|
T3 |
13 |
auto[1] |
3777 |
1 |
|
|
T28 |
78 |
|
T60 |
72 |
|
T61 |
53 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55265 |
1 |
|
|
T1 |
193 |
|
T2 |
1 |
|
T3 |
13 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53428 |
1 |
|
|
T1 |
193 |
|
T2 |
1 |
|
T3 |
13 |
auto[1] |
1837 |
1 |
|
|
T14 |
18 |
|
T15 |
10 |
|
T16 |
18 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53441 |
1 |
|
|
T1 |
193 |
|
T2 |
1 |
|
T3 |
13 |
auto[1] |
1824 |
1 |
|
|
T14 |
16 |
|
T15 |
11 |
|
T16 |
10 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53504 |
1 |
|
|
T1 |
193 |
|
T2 |
1 |
|
T3 |
13 |
auto[1] |
1761 |
1 |
|
|
T14 |
17 |
|
T15 |
7 |
|
T16 |
11 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
49073 |
1 |
|
|
T1 |
157 |
|
T4 |
80 |
|
T6 |
87 |
auto[0] |
no_err_inj |
3415 |
1 |
|
|
T1 |
25 |
|
T2 |
1 |
|
T5 |
15 |
auto[1] |
err_inj |
1355 |
1 |
|
|
T1 |
5 |
|
T3 |
5 |
|
T14 |
38 |
auto[1] |
no_err_inj |
1422 |
1 |
|
|
T1 |
6 |
|
T3 |
8 |
|
T14 |
27 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50646 |
1 |
|
|
T1 |
162 |
|
T2 |
1 |
|
T4 |
67 |
auto[0] |
auto[1] |
1842 |
1 |
|
|
T1 |
20 |
|
T4 |
13 |
|
T6 |
8 |
auto[1] |
auto[0] |
2630 |
1 |
|
|
T1 |
11 |
|
T3 |
12 |
|
T14 |
58 |
auto[1] |
auto[1] |
147 |
1 |
|
|
T3 |
1 |
|
T14 |
7 |
|
T197 |
2 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50563 |
1 |
|
|
T1 |
161 |
|
T2 |
1 |
|
T4 |
72 |
auto[0] |
auto[1] |
1925 |
1 |
|
|
T1 |
21 |
|
T4 |
8 |
|
T6 |
8 |
auto[1] |
auto[0] |
2625 |
1 |
|
|
T1 |
10 |
|
T3 |
13 |
|
T14 |
63 |
auto[1] |
auto[1] |
152 |
1 |
|
|
T1 |
1 |
|
T14 |
2 |
|
T87 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50631 |
1 |
|
|
T1 |
171 |
|
T2 |
1 |
|
T4 |
74 |
auto[0] |
auto[1] |
1857 |
1 |
|
|
T1 |
11 |
|
T4 |
6 |
|
T6 |
12 |
auto[1] |
auto[0] |
2637 |
1 |
|
|
T1 |
9 |
|
T3 |
12 |
|
T14 |
63 |
auto[1] |
auto[1] |
140 |
1 |
|
|
T1 |
2 |
|
T3 |
1 |
|
T14 |
2 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50582 |
1 |
|
|
T1 |
167 |
|
T2 |
1 |
|
T4 |
65 |
auto[0] |
auto[1] |
1906 |
1 |
|
|
T1 |
15 |
|
T4 |
15 |
|
T6 |
8 |
auto[1] |
auto[0] |
2630 |
1 |
|
|
T1 |
11 |
|
T3 |
13 |
|
T14 |
58 |
auto[1] |
auto[1] |
147 |
1 |
|
|
T14 |
7 |
|
T91 |
1 |
|
T197 |
2 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50577 |
1 |
|
|
T1 |
166 |
|
T2 |
1 |
|
T4 |
69 |
auto[0] |
auto[1] |
1911 |
1 |
|
|
T1 |
16 |
|
T4 |
11 |
|
T6 |
9 |
auto[1] |
auto[0] |
2624 |
1 |
|
|
T1 |
10 |
|
T3 |
12 |
|
T14 |
58 |
auto[1] |
auto[1] |
153 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T14 |
7 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50584 |
1 |
|
|
T1 |
160 |
|
T2 |
1 |
|
T4 |
72 |
auto[0] |
auto[1] |
1904 |
1 |
|
|
T1 |
22 |
|
T4 |
8 |
|
T6 |
10 |
auto[1] |
auto[0] |
2623 |
1 |
|
|
T1 |
10 |
|
T3 |
12 |
|
T14 |
61 |
auto[1] |
auto[1] |
154 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T14 |
4 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37125 |
1 |
|
|
T1 |
109 |
|
T2 |
1 |
|
T3 |
13 |
auto[0] |
auto[1] |
1024 |
1 |
|
|
T15 |
12 |
|
T16 |
11 |
|
T17 |
12 |
auto[1] |
auto[0] |
16224 |
1 |
|
|
T1 |
84 |
|
T5 |
15 |
|
T6 |
87 |
auto[1] |
auto[1] |
892 |
1 |
|
|
T14 |
21 |
|
T17 |
17 |
|
T88 |
7 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37146 |
1 |
|
|
T1 |
109 |
|
T2 |
1 |
|
T3 |
13 |
auto[0] |
auto[1] |
1003 |
1 |
|
|
T15 |
14 |
|
T16 |
11 |
|
T17 |
8 |
auto[1] |
auto[0] |
16314 |
1 |
|
|
T1 |
84 |
|
T5 |
15 |
|
T6 |
87 |
auto[1] |
auto[1] |
802 |
1 |
|
|
T14 |
15 |
|
T17 |
17 |
|
T88 |
14 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36806 |
1 |
|
|
T1 |
109 |
|
T2 |
1 |
|
T3 |
13 |
auto[0] |
auto[1] |
1343 |
1 |
|
|
T20 |
8 |
|
T14 |
17 |
|
T59 |
5 |
auto[1] |
auto[0] |
16038 |
1 |
|
|
T1 |
84 |
|
T5 |
15 |
|
T6 |
87 |
auto[1] |
auto[1] |
1078 |
1 |
|
|
T14 |
5 |
|
T35 |
9 |
|
T17 |
27 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37178 |
1 |
|
|
T1 |
109 |
|
T2 |
1 |
|
T3 |
13 |
auto[0] |
auto[1] |
971 |
1 |
|
|
T15 |
18 |
|
T16 |
8 |
|
T17 |
9 |
auto[1] |
auto[0] |
16322 |
1 |
|
|
T1 |
84 |
|
T5 |
15 |
|
T6 |
87 |
auto[1] |
auto[1] |
794 |
1 |
|
|
T14 |
15 |
|
T17 |
16 |
|
T88 |
20 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33402 |
1 |
|
|
T1 |
109 |
|
T2 |
1 |
|
T3 |
13 |
auto[0] |
auto[1] |
4747 |
1 |
|
|
T24 |
79 |
|
T15 |
9 |
|
T16 |
9 |
auto[1] |
auto[0] |
16300 |
1 |
|
|
T1 |
84 |
|
T5 |
15 |
|
T6 |
87 |
auto[1] |
auto[1] |
816 |
1 |
|
|
T14 |
18 |
|
T17 |
14 |
|
T88 |
12 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36928 |
1 |
|
|
T1 |
97 |
|
T2 |
1 |
|
T3 |
12 |
auto[0] |
auto[1] |
1221 |
1 |
|
|
T1 |
12 |
|
T3 |
1 |
|
T4 |
13 |
auto[1] |
auto[0] |
16348 |
1 |
|
|
T1 |
76 |
|
T5 |
15 |
|
T6 |
79 |
auto[1] |
auto[1] |
768 |
1 |
|
|
T1 |
8 |
|
T6 |
8 |
|
T14 |
4 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36919 |
1 |
|
|
T1 |
99 |
|
T2 |
1 |
|
T3 |
13 |
auto[0] |
auto[1] |
1230 |
1 |
|
|
T1 |
10 |
|
T4 |
7 |
|
T31 |
5 |
auto[1] |
auto[0] |
16300 |
1 |
|
|
T1 |
75 |
|
T5 |
15 |
|
T6 |
77 |
auto[1] |
auto[1] |
816 |
1 |
|
|
T1 |
9 |
|
T6 |
10 |
|
T14 |
2 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36904 |
1 |
|
|
T1 |
97 |
|
T2 |
1 |
|
T3 |
13 |
auto[0] |
auto[1] |
1245 |
1 |
|
|
T1 |
12 |
|
T4 |
8 |
|
T31 |
9 |
auto[1] |
auto[0] |
16284 |
1 |
|
|
T1 |
74 |
|
T5 |
15 |
|
T6 |
79 |
auto[1] |
auto[1] |
832 |
1 |
|
|
T1 |
10 |
|
T6 |
8 |
|
T14 |
2 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36939 |
1 |
|
|
T1 |
97 |
|
T2 |
1 |
|
T3 |
12 |
auto[0] |
auto[1] |
1210 |
1 |
|
|
T1 |
12 |
|
T3 |
1 |
|
T4 |
5 |
auto[1] |
auto[0] |
16282 |
1 |
|
|
T1 |
77 |
|
T5 |
15 |
|
T6 |
76 |
auto[1] |
auto[1] |
834 |
1 |
|
|
T1 |
7 |
|
T6 |
11 |
|
T14 |
2 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36907 |
1 |
|
|
T1 |
102 |
|
T2 |
1 |
|
T3 |
13 |
auto[0] |
auto[1] |
1242 |
1 |
|
|
T1 |
7 |
|
T4 |
15 |
|
T31 |
14 |
auto[1] |
auto[0] |
16305 |
1 |
|
|
T1 |
76 |
|
T5 |
15 |
|
T6 |
79 |
auto[1] |
auto[1] |
811 |
1 |
|
|
T1 |
8 |
|
T6 |
8 |
|
T14 |
6 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36893 |
1 |
|
|
T1 |
96 |
|
T2 |
1 |
|
T3 |
12 |
auto[0] |
auto[1] |
1256 |
1 |
|
|
T1 |
13 |
|
T3 |
1 |
|
T4 |
8 |
auto[1] |
auto[0] |
16314 |
1 |
|
|
T1 |
74 |
|
T5 |
15 |
|
T6 |
77 |
auto[1] |
auto[1] |
802 |
1 |
|
|
T1 |
10 |
|
T6 |
10 |
|
T14 |
3 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37195 |
1 |
|
|
T1 |
109 |
|
T2 |
1 |
|
T3 |
13 |
auto[0] |
auto[1] |
954 |
1 |
|
|
T15 |
7 |
|
T16 |
11 |
|
T17 |
2 |
auto[1] |
auto[0] |
16309 |
1 |
|
|
T1 |
84 |
|
T5 |
15 |
|
T6 |
87 |
auto[1] |
auto[1] |
807 |
1 |
|
|
T14 |
17 |
|
T17 |
23 |
|
T88 |
17 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37160 |
1 |
|
|
T1 |
109 |
|
T2 |
1 |
|
T3 |
13 |
auto[0] |
auto[1] |
989 |
1 |
|
|
T15 |
11 |
|
T16 |
10 |
|
T17 |
10 |
auto[1] |
auto[0] |
16281 |
1 |
|
|
T1 |
84 |
|
T5 |
15 |
|
T6 |
87 |
auto[1] |
auto[1] |
835 |
1 |
|
|
T14 |
16 |
|
T17 |
15 |
|
T88 |
8 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36588 |
1 |
|
|
T1 |
109 |
|
T2 |
1 |
|
T4 |
80 |
auto[0] |
auto[1] |
1561 |
1 |
|
|
T3 |
13 |
|
T14 |
15 |
|
T87 |
12 |
auto[1] |
auto[0] |
15900 |
1 |
|
|
T1 |
73 |
|
T5 |
15 |
|
T6 |
87 |
auto[1] |
auto[1] |
1216 |
1 |
|
|
T1 |
11 |
|
T14 |
50 |
|
T17 |
14 |