Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101393330

1

T1

416539

T2

1204

T3

5379

auto[1]

1465727

1

T1

7394

T3

297

T4

2277

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101365854

1

T1

418024

T2

1204

T3

5577

auto[1]

1493203

1

T1

5909

T3

99

T4

4356

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7349933	1			T1	22401		T2	91		T3	1237
auto[IdleSt]	22268205	1			T1	28612		T2	195		T3	861
auto[ClkMuxSt]	35715	1			T1	31		T2	1		T3	8
auto[CntIncrSt]	35510	1			T1	31		T2	1		T3	8
auto[CntProgSt]	1316199	1			T1	791		T2	2		T3	562
auto[TransCheckSt]	27475	1			T1	31		T2	1		T3	8
auto[TokenHashSt]	40097953	1			T1	239492		T2	124		T3	190
auto[FlashRmaSt]	27934	1			T1	77		T2	1		T3	8
auto[TokenCheck0St]	12677	1			T1	31		T2	1		T3	8
auto[TokenCheck1St]	9367	1			T1	31		T2	1		T3	8
auto[TransProgSt]	281597	1			T1	964		T2	2		T3	352
auto[PostTransSt]	13173984	1			T1	14014		T2	784		T3	1418
auto[ScrapSt]	160901	1			T5	281		T22	3		T26	6
auto[EscalateSt]	6938166	1			T1	35760		T3	687		T4	9343
auto[InvalidSt]	11121282	1			T1	81645		T3	321		T4	9371

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2159	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11121282	1			T1	81645		T3	321		T4	9371
EscalateSt	6938166	1			T1	35760		T3	687		T4	9343
ScrapSt	160901	1			T5	281		T22	3		T26	6
PostTransSt	13173984	1			T1	14014		T2	784		T3	1418
TransProgSt	281597	1			T1	964		T2	2		T3	352
TokenCheck1St	9367	1			T1	31		T2	1		T3	8
TokenCheck0St	12677	1			T1	31		T2	1		T3	8
FlashRmaSt	27934	1			T1	77		T2	1		T3	8
TokenHashSt	40097953	1			T1	239492		T2	124		T3	190
TransCheckSt	27475	1			T1	31		T2	1		T3	8
CntProgSt	1316199	1			T1	791		T2	2		T3	562
CntIncrSt	35510	1			T1	31		T2	1		T3	8
ClkMuxSt	35715	1			T1	31		T2	1		T3	8
IdleSt	22268205	1			T1	28612		T2	195		T3	861
ResetSt	7349933	1			T1	22401		T2	91		T3	1237
arcs[ResetSt=>IdleSt]	55460	1			T1	183		T2	1		T3	14
arcs[IdleSt=>ScrapSt]	327	1			T5	1		T22	1		T26	2
arcs[IdleSt=>ClkMuxSt]	35571	1			T1	31		T2	1		T3	8
arcs[ClkMuxSt=>CntIncrSt]	35510	1			T1	31		T2	1		T3	8
arcs[CntIncrSt=>PostTransSt]	1825	1			T14	16		T15	11		T16	10
arcs[CntIncrSt=>CntProgSt]	33627	1			T1	31		T2	1		T3	8
arcs[CntProgSt=>PostTransSt]	5027	1			T20	8		T21	8		T14	42
arcs[CntProgSt=>TransCheckSt]	27475	1			T1	31		T2	1		T3	8
arcs[TransCheckSt=>PostTransSt]	3615	1			T28	32		T14	17		T15	7
arcs[TransCheckSt=>TokenHashSt]	23751	1			T1	31		T2	1		T3	8
arcs[TokenHashSt=>PostTransSt]	10284	1			T21	5		T28	13		T14	54
arcs[TokenHashSt=>FlashRmaSt]	12763	1			T1	31		T2	1		T3	8
arcs[FlashRmaSt=>TokenCheck0St]	12677	1			T1	31		T2	1		T3	8
arcs[TokenCheck0St=>PostTransSt]	3284	1			T21	10		T28	24		T14	13
arcs[TokenCheck0St=>TokenCheck1St]	9367	1			T1	31		T2	1		T3	8
arcs[TokenCheck1St=>PostTransSt]	651	1			T21	2		T28	9		T14	2
arcs[TransProgSt=>PostTransSt]	7799	1			T1	31		T2	1		T3	8
arcs[IdleSt=>EscalateSt]	227	1			T22	7		T27	7		T45	11
arcs[ClkMuxSt=>EscalateSt]	61	1			T22	2		T26	1		T29	2
arcs[CntIncrSt=>EscalateSt]	58	1			T26	2		T29	1		T45	3
arcs[CntProgSt=>EscalateSt]	1125	1			T22	31		T26	11		T27	20
arcs[TransCheckSt=>EscalateSt]	109	1			T26	8		T29	1		T45	4
arcs[TokenHashSt=>EscalateSt]	704	1			T22	10		T26	34		T27	8
arcs[FlashRmaSt=>EscalateSt]	86	1			T22	3		T27	1		T29	4
arcs[TokenCheck0St=>EscalateSt]	26	1			T26	1		T27	1		T29	1
arcs[TokenCheck1St=>EscalateSt]	155	1			T22	1		T26	2		T27	7
arcs[TransProgSt=>EscalateSt]	762	1			T22	19		T26	5		T27	21
arcs[PostTransSt=>EscalateSt]	5302	1			T20	8		T21	8		T22	1
arcs[InvalidSt=>EscalateSt]	15071	1			T1	135		T3	4		T4	67

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7349758	1			T1	22401		T2	91		T3	1237
auto[0]	auto[IdleSt]	22268050	1			T1	28612		T2	195		T3	861
auto[0]	auto[ClkMuxSt]	35677	1			T1	31		T2	1		T3	8
auto[0]	auto[CntIncrSt]	35469	1			T1	31		T2	1		T3	8
auto[0]	auto[CntProgSt]	1315491	1			T1	791		T2	2		T3	562
auto[0]	auto[TransCheckSt]	27405	1			T1	31		T2	1		T3	8
auto[0]	auto[TokenHashSt]	40097497	1			T1	239492		T2	124		T3	190
auto[0]	auto[FlashRmaSt]	27880	1			T1	77		T2	1		T3	8
auto[0]	auto[TokenCheck0St]	12663	1			T1	31		T2	1		T3	8
auto[0]	auto[TokenCheck1St]	9261	1			T1	31		T2	1		T3	8
auto[0]	auto[TransProgSt]	281096	1			T1	964		T2	2		T3	352
auto[0]	auto[PostTransSt]	13171336	1			T1	14014		T2	784		T3	1418
auto[0]	auto[ScrapSt]	160852	1			T5	281		T22	2		T26	4
auto[0]	auto[EscalateSt]	5484996	1			T1	28441		T3	393		T4	7089
auto[0]	auto[InvalidSt]	11113740	1			T1	81570		T3	318		T4	9348
auto[1]	auto[ResetSt]	175	1			T22	6		T26	3		T27	6
auto[1]	auto[IdleSt]	155	1			T22	5		T27	4		T45	9
auto[1]	auto[ClkMuxSt]	38	1			T22	1		T45	2		T194	2
auto[1]	auto[CntIncrSt]	41	1			T26	2		T29	1		T45	2
auto[1]	auto[CntProgSt]	708	1			T22	17		T26	10		T27	10
auto[1]	auto[TransCheckSt]	70	1			T26	5		T45	2		T194	1
auto[1]	auto[TokenHashSt]	456	1			T22	10		T26	21		T27	5
auto[1]	auto[FlashRmaSt]	54	1			T22	1		T27	1		T29	3
auto[1]	auto[TokenCheck0St]	14	1			T27	1		T194	1		T96	1
auto[1]	auto[TokenCheck1St]	106	1			T26	2		T27	5		T29	2
auto[1]	auto[TransProgSt]	501	1			T22	15		T26	4		T27	15
auto[1]	auto[PostTransSt]	2648	1			T20	4		T21	6		T26	9
auto[1]	auto[ScrapSt]	49	1			T22	1		T26	2		T27	1
auto[1]	auto[EscalateSt]	1453170	1			T1	7319		T3	294		T4	2254
auto[1]	auto[InvalidSt]	7542	1			T1	75		T3	3		T4	23

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7349746	1			T1	22401		T2	91		T3	1237
auto[0]	auto[IdleSt]	22268059	1			T1	28612		T2	195		T3	861
auto[0]	auto[ClkMuxSt]	35674	1			T1	31		T2	1		T3	8
auto[0]	auto[CntIncrSt]	35478	1			T1	31		T2	1		T3	8
auto[0]	auto[CntProgSt]	1315412	1			T1	791		T2	2		T3	562
auto[0]	auto[TransCheckSt]	27400	1			T1	31		T2	1		T3	8
auto[0]	auto[TokenHashSt]	40097497	1			T1	239492		T2	124		T3	190
auto[0]	auto[FlashRmaSt]	27874	1			T1	77		T2	1		T3	8
auto[0]	auto[TokenCheck0St]	12658	1			T1	31		T2	1		T3	8
auto[0]	auto[TokenCheck1St]	9259	1			T1	31		T2	1		T3	8
auto[0]	auto[TransProgSt]	281094	1			T1	964		T2	2		T3	352
auto[0]	auto[PostTransSt]	13171256	1			T1	14014		T2	784		T3	1418
auto[0]	auto[ScrapSt]	160857	1			T5	281		T22	3		T26	4
auto[0]	auto[EscalateSt]	5457678	1			T1	29911		T3	589		T4	5031
auto[0]	auto[InvalidSt]	11113753	1			T1	81585		T3	320		T4	9327
auto[1]	auto[ResetSt]	187	1			T22	9		T26	2		T27	8
auto[1]	auto[IdleSt]	146	1			T22	5		T27	5		T45	5
auto[1]	auto[ClkMuxSt]	41	1			T22	2		T26	1		T29	2
auto[1]	auto[CntIncrSt]	32	1			T45	3		T195	1		T196	1
auto[1]	auto[CntProgSt]	787	1			T22	22		T26	7		T27	14
auto[1]	auto[TransCheckSt]	75	1			T26	6		T29	1		T45	3
auto[1]	auto[TokenHashSt]	456	1			T22	7		T26	24		T27	5
auto[1]	auto[FlashRmaSt]	60	1			T22	3		T27	1		T29	4
auto[1]	auto[TokenCheck0St]	19	1			T26	1		T27	1		T29	1
auto[1]	auto[TokenCheck1St]	108	1			T22	1		T26	2		T27	5
auto[1]	auto[TransProgSt]	503	1			T22	10		T26	4		T27	11
auto[1]	auto[PostTransSt]	2728	1			T20	4		T21	2		T22	1
auto[1]	auto[ScrapSt]	44	1			T26	2		T27	2		T29	1
auto[1]	auto[EscalateSt]	1480488	1			T1	5849		T3	98		T4	4312
auto[1]	auto[InvalidSt]	7529	1			T1	60		T3	1		T4	44