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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.87 97.92 95.84 93.38 97.62 98.52 98.51 96.29


Total test records in report: 999
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T810 /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3664714910 Jun 25 06:29:04 PM PDT 24 Jun 25 06:29:08 PM PDT 24 64383250 ps
T811 /workspace/coverage/default/17.lc_ctrl_jtag_errors.2178448838 Jun 25 06:27:55 PM PDT 24 Jun 25 06:28:38 PM PDT 24 10833217287 ps
T812 /workspace/coverage/default/35.lc_ctrl_state_failure.2578555361 Jun 25 06:29:11 PM PDT 24 Jun 25 06:29:40 PM PDT 24 1003234018 ps
T813 /workspace/coverage/default/1.lc_ctrl_sec_token_mux.4128418153 Jun 25 06:26:25 PM PDT 24 Jun 25 06:26:36 PM PDT 24 447033618 ps
T814 /workspace/coverage/default/43.lc_ctrl_errors.3990571109 Jun 25 06:29:35 PM PDT 24 Jun 25 06:29:54 PM PDT 24 323625504 ps
T815 /workspace/coverage/default/45.lc_ctrl_alert_test.2563282216 Jun 25 06:29:46 PM PDT 24 Jun 25 06:29:48 PM PDT 24 52782931 ps
T816 /workspace/coverage/default/42.lc_ctrl_prog_failure.2095766749 Jun 25 06:29:35 PM PDT 24 Jun 25 06:29:40 PM PDT 24 432213116 ps
T817 /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1378235217 Jun 25 06:26:17 PM PDT 24 Jun 25 06:26:20 PM PDT 24 76029052 ps
T818 /workspace/coverage/default/37.lc_ctrl_stress_all.3742793472 Jun 25 06:29:22 PM PDT 24 Jun 25 06:31:55 PM PDT 24 6247244405 ps
T819 /workspace/coverage/default/4.lc_ctrl_jtag_priority.2661728849 Jun 25 06:26:48 PM PDT 24 Jun 25 06:26:58 PM PDT 24 458610026 ps
T820 /workspace/coverage/default/18.lc_ctrl_sec_token_digest.4272370738 Jun 25 06:28:04 PM PDT 24 Jun 25 06:28:16 PM PDT 24 564770396 ps
T821 /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.1587957861 Jun 25 06:27:57 PM PDT 24 Jun 25 06:28:02 PM PDT 24 1089161909 ps
T822 /workspace/coverage/default/1.lc_ctrl_stress_all.248023683 Jun 25 06:26:25 PM PDT 24 Jun 25 06:29:00 PM PDT 24 4565041739 ps
T823 /workspace/coverage/default/0.lc_ctrl_prog_failure.1052266684 Jun 25 06:26:08 PM PDT 24 Jun 25 06:26:11 PM PDT 24 44728386 ps
T824 /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.4220595041 Jun 25 06:28:05 PM PDT 24 Jun 25 06:28:09 PM PDT 24 13834301 ps
T825 /workspace/coverage/default/43.lc_ctrl_sec_mubi.2303864933 Jun 25 06:29:35 PM PDT 24 Jun 25 06:29:48 PM PDT 24 294889326 ps
T826 /workspace/coverage/default/45.lc_ctrl_errors.3264901355 Jun 25 06:29:44 PM PDT 24 Jun 25 06:30:02 PM PDT 24 1318194026 ps
T827 /workspace/coverage/default/8.lc_ctrl_regwen_during_op.2539769598 Jun 25 06:26:55 PM PDT 24 Jun 25 06:27:10 PM PDT 24 1132902859 ps
T828 /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2779833727 Jun 25 06:28:21 PM PDT 24 Jun 25 06:28:31 PM PDT 24 398353051 ps
T829 /workspace/coverage/default/6.lc_ctrl_errors.4040966650 Jun 25 06:26:43 PM PDT 24 Jun 25 06:26:58 PM PDT 24 540948481 ps
T830 /workspace/coverage/default/19.lc_ctrl_jtag_errors.2018045129 Jun 25 06:28:12 PM PDT 24 Jun 25 06:29:04 PM PDT 24 1623613376 ps
T55 /workspace/coverage/default/0.lc_ctrl_sec_cm.1482859172 Jun 25 06:26:16 PM PDT 24 Jun 25 06:26:41 PM PDT 24 434127869 ps
T831 /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.4248199778 Jun 25 06:27:31 PM PDT 24 Jun 25 06:27:34 PM PDT 24 46581307 ps
T832 /workspace/coverage/default/36.lc_ctrl_state_post_trans.436879968 Jun 25 06:29:16 PM PDT 24 Jun 25 06:29:26 PM PDT 24 164520760 ps
T833 /workspace/coverage/default/19.lc_ctrl_errors.2518011602 Jun 25 06:28:06 PM PDT 24 Jun 25 06:28:24 PM PDT 24 720090626 ps
T834 /workspace/coverage/default/45.lc_ctrl_sec_token_mux.1809787382 Jun 25 06:29:44 PM PDT 24 Jun 25 06:29:54 PM PDT 24 675933078 ps
T835 /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.4072524833 Jun 25 06:28:45 PM PDT 24 Jun 25 06:28:47 PM PDT 24 27646663 ps
T836 /workspace/coverage/default/23.lc_ctrl_state_failure.3138957106 Jun 25 06:28:29 PM PDT 24 Jun 25 06:28:54 PM PDT 24 479779784 ps
T837 /workspace/coverage/default/41.lc_ctrl_prog_failure.1794162363 Jun 25 06:29:30 PM PDT 24 Jun 25 06:29:37 PM PDT 24 75933957 ps
T838 /workspace/coverage/default/32.lc_ctrl_sec_mubi.2373345144 Jun 25 06:28:59 PM PDT 24 Jun 25 06:29:16 PM PDT 24 698328040 ps
T839 /workspace/coverage/default/9.lc_ctrl_jtag_errors.1713894932 Jun 25 06:27:09 PM PDT 24 Jun 25 06:27:52 PM PDT 24 8810730224 ps
T840 /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.712910968 Jun 25 06:29:30 PM PDT 24 Jun 25 06:29:34 PM PDT 24 169008617 ps
T841 /workspace/coverage/default/39.lc_ctrl_jtag_access.159346723 Jun 25 06:29:22 PM PDT 24 Jun 25 06:29:31 PM PDT 24 11678445239 ps
T842 /workspace/coverage/default/3.lc_ctrl_state_failure.2634875634 Jun 25 06:26:36 PM PDT 24 Jun 25 06:27:08 PM PDT 24 602571265 ps
T843 /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3108039852 Jun 25 06:27:31 PM PDT 24 Jun 25 06:27:59 PM PDT 24 1218052624 ps
T844 /workspace/coverage/default/30.lc_ctrl_stress_all.2417917990 Jun 25 06:28:49 PM PDT 24 Jun 25 06:30:08 PM PDT 24 3756725551 ps
T845 /workspace/coverage/default/5.lc_ctrl_jtag_access.2252527131 Jun 25 06:26:46 PM PDT 24 Jun 25 06:27:01 PM PDT 24 346870132 ps
T846 /workspace/coverage/default/23.lc_ctrl_stress_all.553214102 Jun 25 06:28:28 PM PDT 24 Jun 25 06:31:34 PM PDT 24 5247610716 ps
T847 /workspace/coverage/default/30.lc_ctrl_smoke.999714939 Jun 25 06:28:49 PM PDT 24 Jun 25 06:28:57 PM PDT 24 772069623 ps
T848 /workspace/coverage/default/9.lc_ctrl_jtag_priority.3243091185 Jun 25 06:27:10 PM PDT 24 Jun 25 06:27:27 PM PDT 24 15028980577 ps
T849 /workspace/coverage/default/33.lc_ctrl_errors.3218478766 Jun 25 06:29:00 PM PDT 24 Jun 25 06:29:16 PM PDT 24 515808742 ps
T850 /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3327791818 Jun 25 06:27:43 PM PDT 24 Jun 25 06:27:58 PM PDT 24 2240193860 ps
T851 /workspace/coverage/default/31.lc_ctrl_errors.817306307 Jun 25 06:28:50 PM PDT 24 Jun 25 06:29:05 PM PDT 24 764502284 ps
T852 /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2857491264 Jun 25 06:26:38 PM PDT 24 Jun 25 06:26:56 PM PDT 24 967281591 ps
T853 /workspace/coverage/default/33.lc_ctrl_state_failure.80824204 Jun 25 06:28:59 PM PDT 24 Jun 25 06:29:27 PM PDT 24 593428098 ps
T854 /workspace/coverage/default/49.lc_ctrl_sec_token_digest.907955949 Jun 25 06:29:58 PM PDT 24 Jun 25 06:30:07 PM PDT 24 435435544 ps
T855 /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1633825450 Jun 25 06:28:36 PM PDT 24 Jun 25 06:28:39 PM PDT 24 33574254 ps
T856 /workspace/coverage/default/14.lc_ctrl_stress_all.1882274070 Jun 25 06:27:43 PM PDT 24 Jun 25 06:30:14 PM PDT 24 7373101225 ps
T857 /workspace/coverage/default/10.lc_ctrl_jtag_access.340018168 Jun 25 06:27:18 PM PDT 24 Jun 25 06:27:27 PM PDT 24 487861143 ps
T858 /workspace/coverage/default/23.lc_ctrl_prog_failure.1739142478 Jun 25 06:28:27 PM PDT 24 Jun 25 06:28:33 PM PDT 24 50137623 ps
T859 /workspace/coverage/default/5.lc_ctrl_sec_mubi.3853239231 Jun 25 06:26:42 PM PDT 24 Jun 25 06:27:02 PM PDT 24 254059430 ps
T860 /workspace/coverage/default/4.lc_ctrl_prog_failure.1403002547 Jun 25 06:26:37 PM PDT 24 Jun 25 06:26:46 PM PDT 24 577909824 ps
T861 /workspace/coverage/default/38.lc_ctrl_smoke.522129197 Jun 25 06:29:20 PM PDT 24 Jun 25 06:29:24 PM PDT 24 775773494 ps
T862 /workspace/coverage/default/22.lc_ctrl_smoke.1985143423 Jun 25 06:28:21 PM PDT 24 Jun 25 06:28:28 PM PDT 24 612894063 ps
T863 /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.937189237 Jun 25 06:27:57 PM PDT 24 Jun 25 06:27:59 PM PDT 24 14558663 ps
T864 /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1285285953 Jun 25 06:27:46 PM PDT 24 Jun 25 06:27:59 PM PDT 24 337731937 ps
T865 /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1062699697 Jun 25 06:29:06 PM PDT 24 Jun 25 06:29:09 PM PDT 24 14871164 ps
T866 /workspace/coverage/default/35.lc_ctrl_prog_failure.4127661191 Jun 25 06:29:11 PM PDT 24 Jun 25 06:29:14 PM PDT 24 143782656 ps
T867 /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.537813217 Jun 25 06:29:00 PM PDT 24 Jun 25 06:36:22 PM PDT 24 13130057199 ps
T868 /workspace/coverage/default/20.lc_ctrl_sec_token_mux.665749050 Jun 25 06:28:12 PM PDT 24 Jun 25 06:28:27 PM PDT 24 1101843254 ps
T869 /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.953549152 Jun 25 06:26:49 PM PDT 24 Jun 25 06:27:24 PM PDT 24 3414201620 ps
T870 /workspace/coverage/default/42.lc_ctrl_jtag_access.1102388378 Jun 25 06:29:34 PM PDT 24 Jun 25 06:29:39 PM PDT 24 82544289 ps
T871 /workspace/coverage/default/9.lc_ctrl_sec_mubi.1452908417 Jun 25 06:27:18 PM PDT 24 Jun 25 06:27:34 PM PDT 24 6896576128 ps
T872 /workspace/coverage/default/19.lc_ctrl_sec_token_mux.3173988176 Jun 25 06:28:05 PM PDT 24 Jun 25 06:28:15 PM PDT 24 1024242259 ps
T103 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3039812531 Jun 25 06:25:56 PM PDT 24 Jun 25 06:26:01 PM PDT 24 112129335 ps
T112 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1175302436 Jun 25 06:25:53 PM PDT 24 Jun 25 06:25:55 PM PDT 24 16851520 ps
T113 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3194583243 Jun 25 06:25:54 PM PDT 24 Jun 25 06:25:56 PM PDT 24 20614946 ps
T106 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3173022570 Jun 25 06:25:47 PM PDT 24 Jun 25 06:25:53 PM PDT 24 371338514 ps
T140 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2146775556 Jun 25 06:25:41 PM PDT 24 Jun 25 06:26:11 PM PDT 24 1236843959 ps
T107 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3159424199 Jun 25 06:25:53 PM PDT 24 Jun 25 06:25:56 PM PDT 24 137282521 ps
T137 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.377836939 Jun 25 06:25:18 PM PDT 24 Jun 25 06:25:20 PM PDT 24 14621607 ps
T186 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.4119109921 Jun 25 06:25:46 PM PDT 24 Jun 25 06:25:59 PM PDT 24 2022828492 ps
T114 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.90067352 Jun 25 06:26:03 PM PDT 24 Jun 25 06:26:06 PM PDT 24 144705669 ps
T146 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.183572867 Jun 25 06:25:54 PM PDT 24 Jun 25 06:25:58 PM PDT 24 53245346 ps
T179 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2322699245 Jun 25 06:26:10 PM PDT 24 Jun 25 06:26:13 PM PDT 24 38660457 ps
T187 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1978077595 Jun 25 06:25:59 PM PDT 24 Jun 25 06:26:14 PM PDT 24 4937872280 ps
T104 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2582719878 Jun 25 06:25:53 PM PDT 24 Jun 25 06:26:00 PM PDT 24 190086926 ps
T105 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1263186023 Jun 25 06:26:02 PM PDT 24 Jun 25 06:26:06 PM PDT 24 89056107 ps
T115 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3945935523 Jun 25 06:25:52 PM PDT 24 Jun 25 06:25:55 PM PDT 24 52467572 ps
T108 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.540270979 Jun 25 06:25:55 PM PDT 24 Jun 25 06:26:02 PM PDT 24 117390135 ps
T873 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3668662158 Jun 25 06:25:34 PM PDT 24 Jun 25 06:25:36 PM PDT 24 455198508 ps
T121 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2285337848 Jun 25 06:26:02 PM PDT 24 Jun 25 06:26:05 PM PDT 24 35821987 ps
T147 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.89822362 Jun 25 06:25:35 PM PDT 24 Jun 25 06:25:37 PM PDT 24 24044202 ps
T874 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1267020386 Jun 25 06:25:45 PM PDT 24 Jun 25 06:26:24 PM PDT 24 1787200307 ps
T109 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3891886261 Jun 25 06:25:39 PM PDT 24 Jun 25 06:25:44 PM PDT 24 210498861 ps
T180 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2071543782 Jun 25 06:26:03 PM PDT 24 Jun 25 06:26:07 PM PDT 24 47422940 ps
T138 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.416715048 Jun 25 06:25:47 PM PDT 24 Jun 25 06:25:51 PM PDT 24 68072759 ps
T139 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3785846055 Jun 25 06:25:40 PM PDT 24 Jun 25 06:25:55 PM PDT 24 588751780 ps
T875 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3107466645 Jun 25 06:26:09 PM PDT 24 Jun 25 06:26:12 PM PDT 24 107660861 ps
T181 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.359406467 Jun 25 06:26:02 PM PDT 24 Jun 25 06:26:06 PM PDT 24 39988448 ps
T876 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.752708822 Jun 25 06:25:45 PM PDT 24 Jun 25 06:25:57 PM PDT 24 973557109 ps
T877 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.4280198588 Jun 25 06:26:02 PM PDT 24 Jun 25 06:26:06 PM PDT 24 28797998 ps
T182 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.136773385 Jun 25 06:25:54 PM PDT 24 Jun 25 06:25:57 PM PDT 24 48144721 ps
T878 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1736938054 Jun 25 06:25:24 PM PDT 24 Jun 25 06:25:27 PM PDT 24 160112883 ps
T110 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1129876169 Jun 25 06:25:45 PM PDT 24 Jun 25 06:25:49 PM PDT 24 63140124 ps
T183 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.805056417 Jun 25 06:25:47 PM PDT 24 Jun 25 06:25:51 PM PDT 24 201436014 ps
T111 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.709156021 Jun 25 06:26:00 PM PDT 24 Jun 25 06:26:04 PM PDT 24 47747096 ps
T117 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3008077492 Jun 25 06:25:46 PM PDT 24 Jun 25 06:25:53 PM PDT 24 114301701 ps
T184 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1360490943 Jun 25 06:25:54 PM PDT 24 Jun 25 06:25:58 PM PDT 24 25695735 ps
T185 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1413194802 Jun 25 06:25:47 PM PDT 24 Jun 25 06:25:51 PM PDT 24 187336155 ps
T879 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1574698626 Jun 25 06:25:38 PM PDT 24 Jun 25 06:25:40 PM PDT 24 45653752 ps
T880 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1868554841 Jun 25 06:25:16 PM PDT 24 Jun 25 06:25:18 PM PDT 24 88688702 ps
T881 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1323095170 Jun 25 06:25:47 PM PDT 24 Jun 25 06:25:50 PM PDT 24 18904663 ps
T882 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3739182174 Jun 25 06:25:30 PM PDT 24 Jun 25 06:25:33 PM PDT 24 45743610 ps
T170 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3042952714 Jun 25 06:25:41 PM PDT 24 Jun 25 06:25:43 PM PDT 24 23822231 ps
T116 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2619527423 Jun 25 06:26:02 PM PDT 24 Jun 25 06:26:07 PM PDT 24 125231848 ps
T883 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2833679911 Jun 25 06:25:48 PM PDT 24 Jun 25 06:25:52 PM PDT 24 17437735 ps
T884 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3214495677 Jun 25 06:25:16 PM PDT 24 Jun 25 06:25:20 PM PDT 24 48066991 ps
T885 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2437038464 Jun 25 06:25:53 PM PDT 24 Jun 25 06:25:57 PM PDT 24 350485151 ps
T886 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3987989390 Jun 25 06:25:55 PM PDT 24 Jun 25 06:25:58 PM PDT 24 61032060 ps
T125 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.682929413 Jun 25 06:25:55 PM PDT 24 Jun 25 06:26:01 PM PDT 24 232159334 ps
T171 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.4218682504 Jun 25 06:25:27 PM PDT 24 Jun 25 06:25:29 PM PDT 24 20982336 ps
T887 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.982956632 Jun 25 06:25:45 PM PDT 24 Jun 25 06:25:47 PM PDT 24 46698382 ps
T888 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3531760505 Jun 25 06:25:47 PM PDT 24 Jun 25 06:25:51 PM PDT 24 33503579 ps
T889 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2198956584 Jun 25 06:25:16 PM PDT 24 Jun 25 06:25:19 PM PDT 24 104679132 ps
T890 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.810929521 Jun 25 06:25:47 PM PDT 24 Jun 25 06:25:53 PM PDT 24 74330952 ps
T172 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3782752123 Jun 25 06:25:46 PM PDT 24 Jun 25 06:25:48 PM PDT 24 23453877 ps
T173 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.854293307 Jun 25 06:25:41 PM PDT 24 Jun 25 06:25:43 PM PDT 24 24652138 ps
T891 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2866436437 Jun 25 06:25:49 PM PDT 24 Jun 25 06:25:53 PM PDT 24 20135856 ps
T174 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.262671642 Jun 25 06:25:46 PM PDT 24 Jun 25 06:25:48 PM PDT 24 15643890 ps
T892 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.4280609325 Jun 25 06:25:13 PM PDT 24 Jun 25 06:25:17 PM PDT 24 280278211 ps
T124 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2965200284 Jun 25 06:26:01 PM PDT 24 Jun 25 06:26:07 PM PDT 24 652667940 ps
T893 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2140306801 Jun 25 06:25:31 PM PDT 24 Jun 25 06:25:34 PM PDT 24 269900893 ps
T123 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3141128055 Jun 25 06:25:40 PM PDT 24 Jun 25 06:25:43 PM PDT 24 19732431 ps
T120 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.8962444 Jun 25 06:26:00 PM PDT 24 Jun 25 06:26:07 PM PDT 24 183579234 ps
T894 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1760057702 Jun 25 06:25:40 PM PDT 24 Jun 25 06:25:42 PM PDT 24 97042824 ps
T136 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3866844723 Jun 25 06:25:49 PM PDT 24 Jun 25 06:25:54 PM PDT 24 312094743 ps
T895 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2412306514 Jun 25 06:25:26 PM PDT 24 Jun 25 06:25:30 PM PDT 24 217500854 ps
T896 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2473271145 Jun 25 06:25:34 PM PDT 24 Jun 25 06:25:50 PM PDT 24 10346764499 ps
T897 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.4231369269 Jun 25 06:25:09 PM PDT 24 Jun 25 06:25:13 PM PDT 24 298566094 ps
T898 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1231121324 Jun 25 06:25:58 PM PDT 24 Jun 25 06:26:01 PM PDT 24 82109588 ps
T899 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2624031592 Jun 25 06:25:27 PM PDT 24 Jun 25 06:25:31 PM PDT 24 814061827 ps
T900 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2530849980 Jun 25 06:25:47 PM PDT 24 Jun 25 06:25:54 PM PDT 24 371638510 ps
T175 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2232179827 Jun 25 06:26:09 PM PDT 24 Jun 25 06:26:12 PM PDT 24 14873112 ps
T901 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2993325339 Jun 25 06:25:47 PM PDT 24 Jun 25 06:25:51 PM PDT 24 66201688 ps
T902 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3741609149 Jun 25 06:26:01 PM PDT 24 Jun 25 06:26:05 PM PDT 24 69807967 ps
T903 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2890515449 Jun 25 06:25:56 PM PDT 24 Jun 25 06:26:02 PM PDT 24 3303147739 ps
T904 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.421858217 Jun 25 06:26:08 PM PDT 24 Jun 25 06:26:10 PM PDT 24 27719989 ps
T905 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.4269336311 Jun 25 06:25:07 PM PDT 24 Jun 25 06:25:11 PM PDT 24 117795679 ps
T906 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.211026811 Jun 25 06:25:39 PM PDT 24 Jun 25 06:25:41 PM PDT 24 16848983 ps
T907 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1643209627 Jun 25 06:25:45 PM PDT 24 Jun 25 06:25:47 PM PDT 24 17187136 ps
T132 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.4064093566 Jun 25 06:25:55 PM PDT 24 Jun 25 06:25:59 PM PDT 24 48825078 ps
T908 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.364524963 Jun 25 06:25:54 PM PDT 24 Jun 25 06:25:57 PM PDT 24 569513514 ps
T909 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4238260391 Jun 25 06:26:07 PM PDT 24 Jun 25 06:26:12 PM PDT 24 43389994 ps
T910 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4186584401 Jun 25 06:25:23 PM PDT 24 Jun 25 06:25:26 PM PDT 24 80407523 ps
T911 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1121068914 Jun 25 06:25:26 PM PDT 24 Jun 25 06:26:01 PM PDT 24 3024343606 ps
T912 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1299907471 Jun 25 06:25:17 PM PDT 24 Jun 25 06:25:22 PM PDT 24 979829073 ps
T913 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1712029193 Jun 25 06:25:47 PM PDT 24 Jun 25 06:25:50 PM PDT 24 36578298 ps
T914 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.285411138 Jun 25 06:25:55 PM PDT 24 Jun 25 06:26:03 PM PDT 24 1169872652 ps
T915 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2674012453 Jun 25 06:25:55 PM PDT 24 Jun 25 06:25:58 PM PDT 24 70580586 ps
T916 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3601291761 Jun 25 06:25:49 PM PDT 24 Jun 25 06:25:57 PM PDT 24 2393990305 ps
T917 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3254874130 Jun 25 06:25:15 PM PDT 24 Jun 25 06:25:18 PM PDT 24 87320411 ps
T918 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.754331865 Jun 25 06:25:46 PM PDT 24 Jun 25 06:25:48 PM PDT 24 24612704 ps
T919 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2383793546 Jun 25 06:25:54 PM PDT 24 Jun 25 06:25:57 PM PDT 24 77449349 ps
T920 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.792684092 Jun 25 06:25:56 PM PDT 24 Jun 25 06:26:01 PM PDT 24 105720559 ps
T921 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2667263544 Jun 25 06:26:08 PM PDT 24 Jun 25 06:26:11 PM PDT 24 51833055 ps
T922 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2443602079 Jun 25 06:25:59 PM PDT 24 Jun 25 06:26:02 PM PDT 24 14893613 ps
T923 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1587406941 Jun 25 06:25:09 PM PDT 24 Jun 25 06:25:25 PM PDT 24 6985803806 ps
T924 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2037066232 Jun 25 06:26:03 PM PDT 24 Jun 25 06:26:07 PM PDT 24 27030074 ps
T925 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1547332915 Jun 25 06:25:54 PM PDT 24 Jun 25 06:25:57 PM PDT 24 27577210 ps
T926 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.181749794 Jun 25 06:25:47 PM PDT 24 Jun 25 06:25:51 PM PDT 24 37156337 ps
T927 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.123663107 Jun 25 06:25:46 PM PDT 24 Jun 25 06:25:49 PM PDT 24 126269676 ps
T928 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.230993025 Jun 25 06:25:24 PM PDT 24 Jun 25 06:25:26 PM PDT 24 36899917 ps
T929 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2092349635 Jun 25 06:25:59 PM PDT 24 Jun 25 06:26:05 PM PDT 24 144748684 ps
T930 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.4214930847 Jun 25 06:25:38 PM PDT 24 Jun 25 06:25:40 PM PDT 24 29279860 ps
T135 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2231385065 Jun 25 06:25:39 PM PDT 24 Jun 25 06:25:43 PM PDT 24 50104374 ps
T931 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1406578820 Jun 25 06:26:00 PM PDT 24 Jun 25 06:26:04 PM PDT 24 17454257 ps
T932 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1289013790 Jun 25 06:26:01 PM PDT 24 Jun 25 06:26:05 PM PDT 24 55962346 ps
T933 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3780261577 Jun 25 06:25:47 PM PDT 24 Jun 25 06:25:51 PM PDT 24 88184498 ps
T934 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2235031925 Jun 25 06:25:25 PM PDT 24 Jun 25 06:25:28 PM PDT 24 39873166 ps
T935 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2511467308 Jun 25 06:25:58 PM PDT 24 Jun 25 06:26:01 PM PDT 24 110008287 ps
T936 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.835929873 Jun 25 06:26:01 PM PDT 24 Jun 25 06:26:05 PM PDT 24 48257608 ps
T118 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.453298577 Jun 25 06:26:03 PM PDT 24 Jun 25 06:26:09 PM PDT 24 418536216 ps
T937 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.419274723 Jun 25 06:25:41 PM PDT 24 Jun 25 06:25:46 PM PDT 24 219165401 ps
T133 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1254388149 Jun 25 06:25:58 PM PDT 24 Jun 25 06:26:02 PM PDT 24 231684619 ps
T938 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3988734279 Jun 25 06:25:54 PM PDT 24 Jun 25 06:25:59 PM PDT 24 29888501 ps
T939 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2633347902 Jun 25 06:25:59 PM PDT 24 Jun 25 06:26:02 PM PDT 24 32133516 ps
T940 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3609711583 Jun 25 06:25:16 PM PDT 24 Jun 25 06:25:19 PM PDT 24 22562387 ps
T941 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3244914212 Jun 25 06:25:24 PM PDT 24 Jun 25 06:25:25 PM PDT 24 27477061 ps
T942 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.983620897 Jun 25 06:25:42 PM PDT 24 Jun 25 06:25:45 PM PDT 24 299610235 ps
T943 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.183163115 Jun 25 06:25:50 PM PDT 24 Jun 25 06:25:55 PM PDT 24 385446529 ps
T944 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3308904049 Jun 25 06:25:59 PM PDT 24 Jun 25 06:26:03 PM PDT 24 185241889 ps
T945 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3935476485 Jun 25 06:25:55 PM PDT 24 Jun 25 06:26:21 PM PDT 24 2069900215 ps
T130 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1709547062 Jun 25 06:26:02 PM PDT 24 Jun 25 06:26:07 PM PDT 24 120190602 ps
T946 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2106153877 Jun 25 06:25:47 PM PDT 24 Jun 25 06:25:52 PM PDT 24 50344467 ps
T947 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3330168971 Jun 25 06:25:54 PM PDT 24 Jun 25 06:25:58 PM PDT 24 370657078 ps
T948 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.150995847 Jun 25 06:25:47 PM PDT 24 Jun 25 06:25:52 PM PDT 24 65818696 ps
T949 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2820392507 Jun 25 06:25:26 PM PDT 24 Jun 25 06:25:37 PM PDT 24 1724379476 ps
T950 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.912723628 Jun 25 06:26:01 PM PDT 24 Jun 25 06:26:05 PM PDT 24 138243504 ps
T951 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3412942 Jun 25 06:25:40 PM PDT 24 Jun 25 06:25:43 PM PDT 24 50924543 ps
T952 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2228114297 Jun 25 06:25:46 PM PDT 24 Jun 25 06:25:59 PM PDT 24 1246761139 ps
T953 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2151904859 Jun 25 06:25:46 PM PDT 24 Jun 25 06:25:57 PM PDT 24 1981709549 ps
T954 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2310326662 Jun 25 06:25:55 PM PDT 24 Jun 25 06:25:58 PM PDT 24 24113279 ps
T127 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3371408165 Jun 25 06:25:54 PM PDT 24 Jun 25 06:25:58 PM PDT 24 60602417 ps
T955 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1546544778 Jun 25 06:25:47 PM PDT 24 Jun 25 06:25:52 PM PDT 24 72024492 ps
T956 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.733928963 Jun 25 06:25:47 PM PDT 24 Jun 25 06:25:51 PM PDT 24 344777018 ps
T957 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3783887050 Jun 25 06:25:58 PM PDT 24 Jun 25 06:26:01 PM PDT 24 50099938 ps
T958 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3237861339 Jun 25 06:25:07 PM PDT 24 Jun 25 06:25:18 PM PDT 24 3552354857 ps
T959 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.916290171 Jun 25 06:25:25 PM PDT 24 Jun 25 06:25:27 PM PDT 24 81495543 ps
T131 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3903857754 Jun 25 06:26:07 PM PDT 24 Jun 25 06:26:13 PM PDT 24 461309489 ps
T960 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.4167483979 Jun 25 06:25:46 PM PDT 24 Jun 25 06:25:48 PM PDT 24 82779672 ps
T961 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.768042266 Jun 25 06:25:57 PM PDT 24 Jun 25 06:26:01 PM PDT 24 61530021 ps
T962 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2363104787 Jun 25 06:25:48 PM PDT 24 Jun 25 06:25:52 PM PDT 24 25618012 ps
T176 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.535225824 Jun 25 06:26:08 PM PDT 24 Jun 25 06:26:10 PM PDT 24 45691266 ps
T963 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3570137850 Jun 25 06:25:48 PM PDT 24 Jun 25 06:25:52 PM PDT 24 79556522 ps
T964 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2026733462 Jun 25 06:26:02 PM PDT 24 Jun 25 06:26:05 PM PDT 24 23930418 ps
T965 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2579234898 Jun 25 06:25:38 PM PDT 24 Jun 25 06:25:42 PM PDT 24 485471036 ps
T966 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1037762211 Jun 25 06:25:47 PM PDT 24 Jun 25 06:25:53 PM PDT 24 2578978627 ps
T967 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4210328987 Jun 25 06:25:55 PM PDT 24 Jun 25 06:25:58 PM PDT 24 156860006 ps
T968 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2162675418 Jun 25 06:25:57 PM PDT 24 Jun 25 06:26:00 PM PDT 24 62750406 ps
T969 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.377843045 Jun 25 06:25:33 PM PDT 24 Jun 25 06:25:40 PM PDT 24 1175318010 ps
T128 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3658363167 Jun 25 06:25:57 PM PDT 24 Jun 25 06:26:01 PM PDT 24 48673237 ps
T970 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1700578319 Jun 25 06:26:09 PM PDT 24 Jun 25 06:26:11 PM PDT 24 22266301 ps
T971 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1072457687 Jun 25 06:26:02 PM PDT 24 Jun 25 06:26:06 PM PDT 24 72390542 ps
T972 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4174028303 Jun 25 06:25:55 PM PDT 24 Jun 25 06:25:59 PM PDT 24 30024825 ps
T973 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2439123756 Jun 25 06:26:01 PM PDT 24 Jun 25 06:26:04 PM PDT 24 55762620 ps
T974 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1657727896 Jun 25 06:25:56 PM PDT 24 Jun 25 06:26:00 PM PDT 24 21605988 ps
T975 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.856129335 Jun 25 06:25:55 PM PDT 24 Jun 25 06:25:58 PM PDT 24 475274558 ps
T119 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2843831837 Jun 25 06:25:15 PM PDT 24 Jun 25 06:25:21 PM PDT 24 229601024 ps
T976 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3622496056 Jun 25 06:25:50 PM PDT 24 Jun 25 06:25:54 PM PDT 24 122184710 ps
T177 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3840196881 Jun 25 06:25:38 PM PDT 24 Jun 25 06:25:40 PM PDT 24 13688053 ps
T977 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2670501417 Jun 25 06:25:46 PM PDT 24 Jun 25 06:25:49 PM PDT 24 86220066 ps
T978 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3857601610 Jun 25 06:26:09 PM PDT 24 Jun 25 06:26:13 PM PDT 24 100154311 ps
T979 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3279280545 Jun 25 06:25:16 PM PDT 24 Jun 25 06:25:19 PM PDT 24 75598904 ps
T134 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3800796076 Jun 25 06:26:01 PM PDT 24 Jun 25 06:26:07 PM PDT 24 115895842 ps
T980 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1362361150 Jun 25 06:25:40 PM PDT 24 Jun 25 06:25:43 PM PDT 24 40556521 ps
T981 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3320979629 Jun 25 06:25:47 PM PDT 24 Jun 25 06:25:51 PM PDT 24 116434539 ps
T982 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3547323404 Jun 25 06:25:26 PM PDT 24 Jun 25 06:25:30 PM PDT 24 340737574 ps
T983 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.371499995 Jun 25 06:25:39 PM PDT 24 Jun 25 06:25:41 PM PDT 24 43143786 ps
T984 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3752896251 Jun 25 06:25:54 PM PDT 24 Jun 25 06:25:57 PM PDT 24 22762081 ps
T985 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.123310063 Jun 25 06:26:00 PM PDT 24 Jun 25 06:26:04 PM PDT 24 64791677 ps
T986 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1639823499 Jun 25 06:25:41 PM PDT 24 Jun 25 06:25:43 PM PDT 24 23458742 ps
T987 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2493608359 Jun 25 06:25:15 PM PDT 24 Jun 25 06:25:18 PM PDT 24 257524526 ps
T988 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3896151495 Jun 25 06:25:26 PM PDT 24 Jun 25 06:25:28 PM PDT 24 93977477 ps
T989 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3915606784 Jun 25 06:25:38 PM PDT 24 Jun 25 06:25:41 PM PDT 24 120812540 ps
T990 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3160237843 Jun 25 06:25:40 PM PDT 24 Jun 25 06:25:44 PM PDT 24 355414113 ps
T991 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.627402748 Jun 25 06:25:26 PM PDT 24 Jun 25 06:25:28 PM PDT 24 106464226 ps
T992 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.545064635 Jun 25 06:25:48 PM PDT 24 Jun 25 06:25:51 PM PDT 24 101184763 ps
T993 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2622504857 Jun 25 06:25:42 PM PDT 24 Jun 25 06:25:44 PM PDT 24 16829046 ps
T994 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2417875050 Jun 25 06:25:59 PM PDT 24 Jun 25 06:26:03 PM PDT 24 26880793 ps
T995 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2456919682 Jun 25 06:25:40 PM PDT 24 Jun 25 06:25:45 PM PDT 24 129548246 ps
T129 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1289924644 Jun 25 06:26:09 PM PDT 24 Jun 25 06:26:13 PM PDT 24 55439750 ps
T178 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3942789769 Jun 25 06:25:38 PM PDT 24 Jun 25 06:25:40 PM PDT 24 66128464 ps
T996 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1052962410 Jun 25 06:26:01 PM PDT 24 Jun 25 06:26:05 PM PDT 24 36026940 ps
T122 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.97231534 Jun 25 06:26:09 PM PDT 24 Jun 25 06:26:13 PM PDT 24 70334361 ps
T997 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.799205514 Jun 25 06:25:22 PM PDT 24 Jun 25 06:25:24 PM PDT 24 35539076 ps
T998 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.602716335 Jun 25 06:25:54 PM PDT 24 Jun 25 06:25:56 PM PDT 24 13978987 ps
T999 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3616492662 Jun 25 06:25:50 PM PDT 24 Jun 25 06:25:55 PM PDT 24 120319353 ps
T126 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2162808087 Jun 25 06:25:25 PM PDT 24 Jun 25 06:25:28 PM PDT 24 222510950 ps

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.3603352997
Short name T1
Test name
Test status
Simulation time 4239350925 ps
CPU time 111.99 seconds
Started Jun 25 06:26:49 PM PDT 24
Finished Jun 25 06:28:47 PM PDT 24
Peak memory 276356 kb
Host smart-47d09970-8422-4905-a5a8-63ef09272617
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603352997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.3603352997
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.2915536238
Short name T14
Test name
Test status
Simulation time 5166128608 ps
CPU time 181.92 seconds
Started Jun 25 06:28:59 PM PDT 24
Finished Jun 25 06:32:03 PM PDT 24
Peak memory 274328 kb
Host smart-001dcc6a-b9ed-43ee-b869-40fa84b45ef1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2915536238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.2915536238
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.1462670308
Short name T45
Test name
Test status
Simulation time 634496087 ps
CPU time 11.45 seconds
Started Jun 25 06:29:29 PM PDT 24
Finished Jun 25 06:29:43 PM PDT 24
Peak memory 218488 kb
Host smart-c368405c-8e52-4ea3-93b4-9868dfea273a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462670308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.1462670308
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.4154667014
Short name T21
Test name
Test status
Simulation time 1248111309 ps
CPU time 9.47 seconds
Started Jun 25 06:29:23 PM PDT 24
Finished Jun 25 06:29:34 PM PDT 24
Peak memory 226240 kb
Host smart-82374bad-2e5a-40d3-ae82-950f565fd6e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154667014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.4154667014
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2582719878
Short name T104
Test name
Test status
Simulation time 190086926 ps
CPU time 5.76 seconds
Started Jun 25 06:25:53 PM PDT 24
Finished Jun 25 06:26:00 PM PDT 24
Peak memory 217696 kb
Host smart-888a0242-96f0-47e1-aa12-3c33497d3bf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258271
9878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2582719878
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.1906562786
Short name T49
Test name
Test status
Simulation time 23422209568 ps
CPU time 519.88 seconds
Started Jun 25 06:29:35 PM PDT 24
Finished Jun 25 06:38:17 PM PDT 24
Peak memory 332416 kb
Host smart-e375321b-392c-4164-89f4-f8366ba420e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1906562786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.1906562786
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.1482859172
Short name T55
Test name
Test status
Simulation time 434127869 ps
CPU time 23.6 seconds
Started Jun 25 06:26:16 PM PDT 24
Finished Jun 25 06:26:41 PM PDT 24
Peak memory 268340 kb
Host smart-e0bbc48c-a2c0-429d-9a3f-bba586d680f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482859172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.1482859172
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.3398900028
Short name T28
Test name
Test status
Simulation time 238265239 ps
CPU time 10.09 seconds
Started Jun 25 06:26:43 PM PDT 24
Finished Jun 25 06:26:59 PM PDT 24
Peak memory 226468 kb
Host smart-97d8d011-1714-4bbe-8611-d3664f6824bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398900028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.3
398900028
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3891886261
Short name T109
Test name
Test status
Simulation time 210498861 ps
CPU time 4.17 seconds
Started Jun 25 06:25:39 PM PDT 24
Finished Jun 25 06:25:44 PM PDT 24
Peak memory 217560 kb
Host smart-d9e87608-39cd-4b3a-b8e5-e4e8feab02d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891886261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.3891886261
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.2751790692
Short name T11
Test name
Test status
Simulation time 18034101 ps
CPU time 1.07 seconds
Started Jun 25 06:28:23 PM PDT 24
Finished Jun 25 06:28:25 PM PDT 24
Peak memory 209156 kb
Host smart-5d5ad338-c5f1-42d8-a635-0b4c57a19d16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751790692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2751790692
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.301699217
Short name T57
Test name
Test status
Simulation time 44640106453 ps
CPU time 401.3 seconds
Started Jun 25 06:27:51 PM PDT 24
Finished Jun 25 06:34:34 PM PDT 24
Peak memory 278252 kb
Host smart-bf9e72f7-8d06-4c4d-82f9-c4d12b01aa68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301699217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.301699217
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.228310730
Short name T9
Test name
Test status
Simulation time 2063921926 ps
CPU time 5.58 seconds
Started Jun 25 06:27:45 PM PDT 24
Finished Jun 25 06:27:53 PM PDT 24
Peak memory 217332 kb
Host smart-23cee51e-02bf-4a13-af47-f348c42f2f6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228310730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.228310730
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.4218682504
Short name T171
Test name
Test status
Simulation time 20982336 ps
CPU time 0.99 seconds
Started Jun 25 06:25:27 PM PDT 24
Finished Jun 25 06:25:29 PM PDT 24
Peak memory 209304 kb
Host smart-a82f4347-7931-4001-b7bb-81fbed183848
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218682504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.4218682504
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.1480212113
Short name T100
Test name
Test status
Simulation time 46173428090 ps
CPU time 1568.54 seconds
Started Jun 25 06:26:50 PM PDT 24
Finished Jun 25 06:53:06 PM PDT 24
Peak memory 373156 kb
Host smart-fd40b7ce-f9cd-44cc-822d-96d7b0c2a160
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1480212113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.1480212113
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.453298577
Short name T118
Test name
Test status
Simulation time 418536216 ps
CPU time 3.06 seconds
Started Jun 25 06:26:03 PM PDT 24
Finished Jun 25 06:26:09 PM PDT 24
Peak memory 222664 kb
Host smart-f753481c-1d8f-423a-b085-5c147ac4a581
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453298577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_
err.453298577
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.540270979
Short name T108
Test name
Test status
Simulation time 117390135 ps
CPU time 4.65 seconds
Started Jun 25 06:25:55 PM PDT 24
Finished Jun 25 06:26:02 PM PDT 24
Peak memory 217472 kb
Host smart-b7008b31-983d-4981-a83d-389671ce9ce7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540270979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.540270979
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2191432616
Short name T27
Test name
Test status
Simulation time 491619164 ps
CPU time 17.38 seconds
Started Jun 25 06:29:35 PM PDT 24
Finished Jun 25 06:29:54 PM PDT 24
Peak memory 218504 kb
Host smart-ced221e0-5a00-4287-94e3-1b742d63fc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191432616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2191432616
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.4064093566
Short name T132
Test name
Test status
Simulation time 48825078 ps
CPU time 1.97 seconds
Started Jun 25 06:25:55 PM PDT 24
Finished Jun 25 06:25:59 PM PDT 24
Peak memory 222192 kb
Host smart-b59f9df4-b8de-4e9f-8e1b-d5f3ffdf3532
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064093566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.4064093566
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2843831837
Short name T119
Test name
Test status
Simulation time 229601024 ps
CPU time 4.12 seconds
Started Jun 25 06:25:15 PM PDT 24
Finished Jun 25 06:25:21 PM PDT 24
Peak memory 217544 kb
Host smart-543070fd-9ed4-4641-ad94-90caaaa242eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843831837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.2843831837
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3658363167
Short name T128
Test name
Test status
Simulation time 48673237 ps
CPU time 2.53 seconds
Started Jun 25 06:25:57 PM PDT 24
Finished Jun 25 06:26:01 PM PDT 24
Peak memory 222208 kb
Host smart-e72ff2d8-9fcb-4966-bb34-1b1a31bddb6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658363167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3658363167
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.377836939
Short name T137
Test name
Test status
Simulation time 14621607 ps
CPU time 0.96 seconds
Started Jun 25 06:25:18 PM PDT 24
Finished Jun 25 06:25:20 PM PDT 24
Peak memory 209192 kb
Host smart-7d250fe2-4d01-499d-8412-33f93c22aa86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377836939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.377836939
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3401150598
Short name T44
Test name
Test status
Simulation time 27745599 ps
CPU time 0.75 seconds
Started Jun 25 06:26:42 PM PDT 24
Finished Jun 25 06:26:49 PM PDT 24
Peak memory 209184 kb
Host smart-4fc83207-27d7-4608-9b28-f859db5103d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401150598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3401150598
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2640033021
Short name T25
Test name
Test status
Simulation time 38430779 ps
CPU time 1.02 seconds
Started Jun 25 06:28:12 PM PDT 24
Finished Jun 25 06:28:16 PM PDT 24
Peak memory 213244 kb
Host smart-c9c0208e-c054-430c-8721-a5734c128e28
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640033021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.2640033021
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2092349635
Short name T929
Test name
Test status
Simulation time 144748684 ps
CPU time 3.43 seconds
Started Jun 25 06:25:59 PM PDT 24
Finished Jun 25 06:26:05 PM PDT 24
Peak memory 217500 kb
Host smart-32f093f9-fd63-400c-9e62-321ce0e09c33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092349635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2092349635
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.682929413
Short name T125
Test name
Test status
Simulation time 232159334 ps
CPU time 4.05 seconds
Started Jun 25 06:25:55 PM PDT 24
Finished Jun 25 06:26:01 PM PDT 24
Peak memory 217640 kb
Host smart-4028cd46-b198-4f1c-a877-176c3d948976
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682929413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.682929413
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.1195259406
Short name T47
Test name
Test status
Simulation time 371335091 ps
CPU time 10.43 seconds
Started Jun 25 06:27:32 PM PDT 24
Finished Jun 25 06:27:44 PM PDT 24
Peak memory 226224 kb
Host smart-ccef1c5e-cd7d-436f-9220-be6662931411
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195259406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.1195259406
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1153903595
Short name T192
Test name
Test status
Simulation time 19045054 ps
CPU time 0.81 seconds
Started Jun 25 06:26:25 PM PDT 24
Finished Jun 25 06:26:29 PM PDT 24
Peak memory 209244 kb
Host smart-22959f9d-b520-4dcb-9d10-b03e34d6b813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153903595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1153903595
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.1739070342
Short name T191
Test name
Test status
Simulation time 14163609 ps
CPU time 0.89 seconds
Started Jun 25 06:27:00 PM PDT 24
Finished Jun 25 06:27:04 PM PDT 24
Peak memory 208992 kb
Host smart-6921452b-31f7-46c2-99f5-18e6ece6e21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739070342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.1739070342
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.1713887777
Short name T193
Test name
Test status
Simulation time 34022180 ps
CPU time 0.83 seconds
Started Jun 25 06:27:17 PM PDT 24
Finished Jun 25 06:27:19 PM PDT 24
Peak memory 209048 kb
Host smart-b4550f10-6632-4c54-889f-b5bf70846866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713887777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1713887777
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.2388169911
Short name T31
Test name
Test status
Simulation time 332796273 ps
CPU time 26.95 seconds
Started Jun 25 06:28:42 PM PDT 24
Finished Jun 25 06:29:11 PM PDT 24
Peak memory 251132 kb
Host smart-c3434bff-8776-474b-83c1-c2d1dc9c4a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388169911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2388169911
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3371408165
Short name T127
Test name
Test status
Simulation time 60602417 ps
CPU time 2.72 seconds
Started Jun 25 06:25:54 PM PDT 24
Finished Jun 25 06:25:58 PM PDT 24
Peak memory 217564 kb
Host smart-31812f0d-24ba-4d25-92f1-fc260d60ba42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371408165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3371408165
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.97231534
Short name T122
Test name
Test status
Simulation time 70334361 ps
CPU time 1.99 seconds
Started Jun 25 06:26:09 PM PDT 24
Finished Jun 25 06:26:13 PM PDT 24
Peak memory 221932 kb
Host smart-f72ea30d-a19e-4bb9-9c0f-413bf53f3334
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97231534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_e
rr.97231534
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1709547062
Short name T130
Test name
Test status
Simulation time 120190602 ps
CPU time 1.97 seconds
Started Jun 25 06:26:02 PM PDT 24
Finished Jun 25 06:26:07 PM PDT 24
Peak memory 221736 kb
Host smart-5fbb77e6-5cc2-480f-8a8c-4dcf02a3c5cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709547062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1709547062
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3800796076
Short name T134
Test name
Test status
Simulation time 115895842 ps
CPU time 3.05 seconds
Started Jun 25 06:26:01 PM PDT 24
Finished Jun 25 06:26:07 PM PDT 24
Peak memory 222340 kb
Host smart-f96f946d-f79e-4868-a7f8-033b637c38ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800796076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.3800796076
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.3044421961
Short name T52
Test name
Test status
Simulation time 754082875 ps
CPU time 17.51 seconds
Started Jun 25 06:29:30 PM PDT 24
Finished Jun 25 06:29:50 PM PDT 24
Peak memory 226244 kb
Host smart-cdbb1323-9512-4ede-be28-ceff333c3d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044421961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.3044421961
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.2908606807
Short name T51
Test name
Test status
Simulation time 72340795325 ps
CPU time 758.38 seconds
Started Jun 25 06:29:29 PM PDT 24
Finished Jun 25 06:42:10 PM PDT 24
Peak memory 422276 kb
Host smart-20195297-d6c5-427d-a446-351476618a32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2908606807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.2908606807
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.4107286053
Short name T4
Test name
Test status
Simulation time 278975417 ps
CPU time 25.34 seconds
Started Jun 25 06:26:15 PM PDT 24
Finished Jun 25 06:26:41 PM PDT 24
Peak memory 251132 kb
Host smart-bcd9cba6-6e06-41b1-8196-9ab27dbaa2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107286053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.4107286053
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.4112180952
Short name T22
Test name
Test status
Simulation time 5290314177 ps
CPU time 13.75 seconds
Started Jun 25 06:27:17 PM PDT 24
Finished Jun 25 06:27:32 PM PDT 24
Peak memory 218552 kb
Host smart-7a409143-7a71-4a7c-a60d-788c756eb174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112180952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.4112180952
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2493608359
Short name T987
Test name
Test status
Simulation time 257524526 ps
CPU time 1.05 seconds
Started Jun 25 06:25:15 PM PDT 24
Finished Jun 25 06:25:18 PM PDT 24
Peak memory 209300 kb
Host smart-958da69f-8be1-4781-aad2-ad52798f3766
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493608359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.2493608359
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3896151495
Short name T988
Test name
Test status
Simulation time 93977477 ps
CPU time 1.52 seconds
Started Jun 25 06:25:26 PM PDT 24
Finished Jun 25 06:25:28 PM PDT 24
Peak memory 208572 kb
Host smart-aaa0aa14-d1f6-4675-99aa-c6fedff6a351
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896151495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3896151495
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3609711583
Short name T940
Test name
Test status
Simulation time 22562387 ps
CPU time 1.42 seconds
Started Jun 25 06:25:16 PM PDT 24
Finished Jun 25 06:25:19 PM PDT 24
Peak memory 217900 kb
Host smart-7dfeb6c9-ece3-460f-acbc-8243fdf24e5a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609711583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.3609711583
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3254874130
Short name T917
Test name
Test status
Simulation time 87320411 ps
CPU time 1.7 seconds
Started Jun 25 06:25:15 PM PDT 24
Finished Jun 25 06:25:18 PM PDT 24
Peak memory 219304 kb
Host smart-1f846f6e-62c5-4558-91cd-c9b32aec1b5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254874130 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3254874130
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1868554841
Short name T880
Test name
Test status
Simulation time 88688702 ps
CPU time 1.01 seconds
Started Jun 25 06:25:16 PM PDT 24
Finished Jun 25 06:25:18 PM PDT 24
Peak memory 208676 kb
Host smart-7025c2b6-50de-4f7b-b58c-8593626072ab
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868554841 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1868554841
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3237861339
Short name T958
Test name
Test status
Simulation time 3552354857 ps
CPU time 8.17 seconds
Started Jun 25 06:25:07 PM PDT 24
Finished Jun 25 06:25:18 PM PDT 24
Peak memory 209160 kb
Host smart-ce5acda1-64c4-4f81-aab3-5a2019c3b76c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237861339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.3237861339
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1587406941
Short name T923
Test name
Test status
Simulation time 6985803806 ps
CPU time 13.95 seconds
Started Jun 25 06:25:09 PM PDT 24
Finished Jun 25 06:25:25 PM PDT 24
Peak memory 209304 kb
Host smart-6020bc4f-2cef-4994-a2f2-317358cf5e1b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587406941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1587406941
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.4280609325
Short name T892
Test name
Test status
Simulation time 280278211 ps
CPU time 2.05 seconds
Started Jun 25 06:25:13 PM PDT 24
Finished Jun 25 06:25:17 PM PDT 24
Peak memory 210848 kb
Host smart-fca3c70e-369a-4b27-9285-0bc222c0a333
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280609325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.4280609325
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1299907471
Short name T912
Test name
Test status
Simulation time 979829073 ps
CPU time 3.2 seconds
Started Jun 25 06:25:17 PM PDT 24
Finished Jun 25 06:25:22 PM PDT 24
Peak memory 218652 kb
Host smart-bea7af92-8d50-4259-99bd-ef37f0357da7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129990
7471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1299907471
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.4231369269
Short name T897
Test name
Test status
Simulation time 298566094 ps
CPU time 1.47 seconds
Started Jun 25 06:25:09 PM PDT 24
Finished Jun 25 06:25:13 PM PDT 24
Peak memory 209176 kb
Host smart-37003996-b624-4f3e-8d4d-4634785e3408
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231369269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.4231369269
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.4269336311
Short name T905
Test name
Test status
Simulation time 117795679 ps
CPU time 1.09 seconds
Started Jun 25 06:25:07 PM PDT 24
Finished Jun 25 06:25:11 PM PDT 24
Peak memory 209352 kb
Host smart-99ef1bf9-dd7e-4c70-bede-b78afaed691f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269336311 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.4269336311
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2198956584
Short name T889
Test name
Test status
Simulation time 104679132 ps
CPU time 1.16 seconds
Started Jun 25 06:25:16 PM PDT 24
Finished Jun 25 06:25:19 PM PDT 24
Peak memory 209476 kb
Host smart-29c6135e-8242-4c6b-823f-da65b16d1c52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198956584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.2198956584
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.627402748
Short name T991
Test name
Test status
Simulation time 106464226 ps
CPU time 1.83 seconds
Started Jun 25 06:25:26 PM PDT 24
Finished Jun 25 06:25:28 PM PDT 24
Peak memory 216800 kb
Host smart-619773e1-284f-4c56-9d81-ead34852034f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627402748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.627402748
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2412306514
Short name T895
Test name
Test status
Simulation time 217500854 ps
CPU time 3.05 seconds
Started Jun 25 06:25:26 PM PDT 24
Finished Jun 25 06:25:30 PM PDT 24
Peak memory 208952 kb
Host smart-8e4ed6b0-e407-4eed-9839-08afa41a7778
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412306514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2412306514
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.799205514
Short name T997
Test name
Test status
Simulation time 35539076 ps
CPU time 1.04 seconds
Started Jun 25 06:25:22 PM PDT 24
Finished Jun 25 06:25:24 PM PDT 24
Peak memory 211484 kb
Host smart-9b272af4-49b7-4fc4-ae50-4938723982aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799205514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset
.799205514
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1736938054
Short name T878
Test name
Test status
Simulation time 160112883 ps
CPU time 1.88 seconds
Started Jun 25 06:25:24 PM PDT 24
Finished Jun 25 06:25:27 PM PDT 24
Peak memory 217704 kb
Host smart-ded29261-1a98-4d9f-82bc-e89654a96c5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736938054 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1736938054
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3244914212
Short name T941
Test name
Test status
Simulation time 27477061 ps
CPU time 0.78 seconds
Started Jun 25 06:25:24 PM PDT 24
Finished Jun 25 06:25:25 PM PDT 24
Peak memory 208328 kb
Host smart-3b2a8f75-8d23-41f4-a365-617279ee9545
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244914212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.3244914212
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.916290171
Short name T959
Test name
Test status
Simulation time 81495543 ps
CPU time 1.07 seconds
Started Jun 25 06:25:25 PM PDT 24
Finished Jun 25 06:25:27 PM PDT 24
Peak memory 209164 kb
Host smart-e7333e08-d990-440b-88b3-5e2df2c00f40
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916290171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.916290171
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2820392507
Short name T949
Test name
Test status
Simulation time 1724379476 ps
CPU time 9.61 seconds
Started Jun 25 06:25:26 PM PDT 24
Finished Jun 25 06:25:37 PM PDT 24
Peak memory 217072 kb
Host smart-f230c943-d4ce-442e-89df-f163a75adb63
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820392507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2820392507
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1121068914
Short name T911
Test name
Test status
Simulation time 3024343606 ps
CPU time 34.17 seconds
Started Jun 25 06:25:26 PM PDT 24
Finished Jun 25 06:26:01 PM PDT 24
Peak memory 209196 kb
Host smart-6c510a12-fd7b-454b-a77e-1f480e095237
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121068914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1121068914
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3547323404
Short name T982
Test name
Test status
Simulation time 340737574 ps
CPU time 2.7 seconds
Started Jun 25 06:25:26 PM PDT 24
Finished Jun 25 06:25:30 PM PDT 24
Peak memory 217428 kb
Host smart-2cacd7f8-4f72-40dc-ad60-eeccef4c0e3c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547323404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.3547323404
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2624031592
Short name T899
Test name
Test status
Simulation time 814061827 ps
CPU time 3.02 seconds
Started Jun 25 06:25:27 PM PDT 24
Finished Jun 25 06:25:31 PM PDT 24
Peak memory 218640 kb
Host smart-8276ab38-4e63-40c8-b058-c349530a2716
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262403
1592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2624031592
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3279280545
Short name T979
Test name
Test status
Simulation time 75598904 ps
CPU time 1.5 seconds
Started Jun 25 06:25:16 PM PDT 24
Finished Jun 25 06:25:19 PM PDT 24
Peak memory 217244 kb
Host smart-4dc3954d-0636-4079-ae4e-2377453ef748
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279280545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.3279280545
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3214495677
Short name T884
Test name
Test status
Simulation time 48066991 ps
CPU time 2.01 seconds
Started Jun 25 06:25:16 PM PDT 24
Finished Jun 25 06:25:20 PM PDT 24
Peak memory 211396 kb
Host smart-d541111f-e55e-4ec2-a109-1b2652748df2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214495677 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.3214495677
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.230993025
Short name T928
Test name
Test status
Simulation time 36899917 ps
CPU time 1.49 seconds
Started Jun 25 06:25:24 PM PDT 24
Finished Jun 25 06:25:26 PM PDT 24
Peak memory 209356 kb
Host smart-261c13a4-0816-49cc-8ef2-e23b0a7f3af5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230993025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.230993025
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2235031925
Short name T934
Test name
Test status
Simulation time 39873166 ps
CPU time 2.62 seconds
Started Jun 25 06:25:25 PM PDT 24
Finished Jun 25 06:25:28 PM PDT 24
Peak memory 218524 kb
Host smart-4cd69c24-a616-4e32-b130-9a4814e66b83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235031925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.2235031925
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2162808087
Short name T126
Test name
Test status
Simulation time 222510950 ps
CPU time 2.58 seconds
Started Jun 25 06:25:25 PM PDT 24
Finished Jun 25 06:25:28 PM PDT 24
Peak memory 217556 kb
Host smart-214e91dd-cb15-4c0b-b23a-fd2879487512
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162808087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2162808087
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2633347902
Short name T939
Test name
Test status
Simulation time 32133516 ps
CPU time 1.31 seconds
Started Jun 25 06:25:59 PM PDT 24
Finished Jun 25 06:26:02 PM PDT 24
Peak memory 217628 kb
Host smart-8d2a1b9a-0116-49e2-a487-9ac0b37def7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633347902 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2633347902
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2383793546
Short name T919
Test name
Test status
Simulation time 77449349 ps
CPU time 0.88 seconds
Started Jun 25 06:25:54 PM PDT 24
Finished Jun 25 06:25:57 PM PDT 24
Peak memory 209180 kb
Host smart-e963913e-d2d2-4253-9713-af94d580830c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383793546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2383793546
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3752896251
Short name T984
Test name
Test status
Simulation time 22762081 ps
CPU time 1.5 seconds
Started Jun 25 06:25:54 PM PDT 24
Finished Jun 25 06:25:57 PM PDT 24
Peak memory 209396 kb
Host smart-d02d6f14-f1cb-4046-bfc1-c0a982f71ff3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752896251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3752896251
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2310326662
Short name T954
Test name
Test status
Simulation time 24113279 ps
CPU time 1.14 seconds
Started Jun 25 06:25:55 PM PDT 24
Finished Jun 25 06:25:58 PM PDT 24
Peak memory 217692 kb
Host smart-ab51490a-394f-4b87-8656-831a88c197ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310326662 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.2310326662
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.602716335
Short name T998
Test name
Test status
Simulation time 13978987 ps
CPU time 1 seconds
Started Jun 25 06:25:54 PM PDT 24
Finished Jun 25 06:25:56 PM PDT 24
Peak memory 209304 kb
Host smart-cee56329-6ca0-43e9-87e7-c86df81cbf5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602716335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.602716335
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2511467308
Short name T935
Test name
Test status
Simulation time 110008287 ps
CPU time 1.41 seconds
Started Jun 25 06:25:58 PM PDT 24
Finished Jun 25 06:26:01 PM PDT 24
Peak memory 211384 kb
Host smart-4aa60177-ca20-47d8-8632-e3f3c9a24b53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511467308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.2511467308
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3308904049
Short name T944
Test name
Test status
Simulation time 185241889 ps
CPU time 2.07 seconds
Started Jun 25 06:25:59 PM PDT 24
Finished Jun 25 06:26:03 PM PDT 24
Peak memory 218944 kb
Host smart-a19553cc-a6f8-44a7-b92f-b4f236e29dad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308904049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3308904049
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2285337848
Short name T121
Test name
Test status
Simulation time 35821987 ps
CPU time 1.04 seconds
Started Jun 25 06:26:02 PM PDT 24
Finished Jun 25 06:26:05 PM PDT 24
Peak memory 217612 kb
Host smart-0049d138-47ba-4705-a40f-a1ff0f0e7f9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285337848 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2285337848
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1175302436
Short name T112
Test name
Test status
Simulation time 16851520 ps
CPU time 0.96 seconds
Started Jun 25 06:25:53 PM PDT 24
Finished Jun 25 06:25:55 PM PDT 24
Peak memory 209296 kb
Host smart-ca92ecfc-4246-417c-8aee-b9b14696bccd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175302436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1175302436
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.912723628
Short name T950
Test name
Test status
Simulation time 138243504 ps
CPU time 1.74 seconds
Started Jun 25 06:26:01 PM PDT 24
Finished Jun 25 06:26:05 PM PDT 24
Peak memory 211424 kb
Host smart-4f3d18d0-8f5c-42cc-9469-6dc1d0ec0067
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912723628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_same_csr_outstanding.912723628
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4174028303
Short name T972
Test name
Test status
Simulation time 30024825 ps
CPU time 1.89 seconds
Started Jun 25 06:25:55 PM PDT 24
Finished Jun 25 06:25:59 PM PDT 24
Peak memory 217660 kb
Host smart-cb41b98b-118d-4c6a-815f-4fa5408a844f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174028303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.4174028303
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.709156021
Short name T111
Test name
Test status
Simulation time 47747096 ps
CPU time 2.41 seconds
Started Jun 25 06:26:00 PM PDT 24
Finished Jun 25 06:26:04 PM PDT 24
Peak memory 217684 kb
Host smart-7a48308d-4ffd-49f0-99b8-f4a8161680c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709156021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_
err.709156021
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1052962410
Short name T996
Test name
Test status
Simulation time 36026940 ps
CPU time 1.42 seconds
Started Jun 25 06:26:01 PM PDT 24
Finished Jun 25 06:26:05 PM PDT 24
Peak memory 217752 kb
Host smart-c234c408-d0c4-4f5d-b7a9-f8078d0bc64e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052962410 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1052962410
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.123310063
Short name T985
Test name
Test status
Simulation time 64791677 ps
CPU time 1 seconds
Started Jun 25 06:26:00 PM PDT 24
Finished Jun 25 06:26:04 PM PDT 24
Peak memory 209288 kb
Host smart-25454181-4dde-409e-ae48-d3f8905dc558
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123310063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.123310063
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2417875050
Short name T994
Test name
Test status
Simulation time 26880793 ps
CPU time 1.08 seconds
Started Jun 25 06:25:59 PM PDT 24
Finished Jun 25 06:26:03 PM PDT 24
Peak memory 209292 kb
Host smart-432bb8bc-3487-41be-ad2a-902cb6cfca58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417875050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2417875050
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3741609149
Short name T902
Test name
Test status
Simulation time 69807967 ps
CPU time 1.07 seconds
Started Jun 25 06:26:01 PM PDT 24
Finished Jun 25 06:26:05 PM PDT 24
Peak memory 217608 kb
Host smart-b25add9f-123a-40b1-b426-794a094c0461
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741609149 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.3741609149
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2071543782
Short name T180
Test name
Test status
Simulation time 47422940 ps
CPU time 0.9 seconds
Started Jun 25 06:26:03 PM PDT 24
Finished Jun 25 06:26:07 PM PDT 24
Peak memory 209300 kb
Host smart-9c248803-76e3-45ac-bb40-46bcfa577a97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071543782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2071543782
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2037066232
Short name T924
Test name
Test status
Simulation time 27030074 ps
CPU time 1.14 seconds
Started Jun 25 06:26:03 PM PDT 24
Finished Jun 25 06:26:07 PM PDT 24
Peak memory 209356 kb
Host smart-d173835d-7b19-4a88-952d-371bb477d095
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037066232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2037066232
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4238260391
Short name T909
Test name
Test status
Simulation time 43389994 ps
CPU time 3.02 seconds
Started Jun 25 06:26:07 PM PDT 24
Finished Jun 25 06:26:12 PM PDT 24
Peak memory 217520 kb
Host smart-36b89366-5469-48bb-8cf3-61e6fc94cb69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238260391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.4238260391
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1289924644
Short name T129
Test name
Test status
Simulation time 55439750 ps
CPU time 2.46 seconds
Started Jun 25 06:26:09 PM PDT 24
Finished Jun 25 06:26:13 PM PDT 24
Peak memory 221620 kb
Host smart-ca56f1aa-9118-4601-bc80-d9a5741e31de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289924644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1289924644
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2026733462
Short name T964
Test name
Test status
Simulation time 23930418 ps
CPU time 1.18 seconds
Started Jun 25 06:26:02 PM PDT 24
Finished Jun 25 06:26:05 PM PDT 24
Peak memory 217568 kb
Host smart-158cac9e-5f1f-4f6d-bf47-b18cbdbf83f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026733462 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2026733462
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.421858217
Short name T904
Test name
Test status
Simulation time 27719989 ps
CPU time 0.91 seconds
Started Jun 25 06:26:08 PM PDT 24
Finished Jun 25 06:26:10 PM PDT 24
Peak memory 209284 kb
Host smart-2a141e88-aef9-4222-bac4-eed1a773f35b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421858217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.421858217
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1406578820
Short name T931
Test name
Test status
Simulation time 17454257 ps
CPU time 1.22 seconds
Started Jun 25 06:26:00 PM PDT 24
Finished Jun 25 06:26:04 PM PDT 24
Peak memory 209368 kb
Host smart-71f10bb1-c243-4ee4-9ef2-28b6b0e2f179
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406578820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.1406578820
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1263186023
Short name T105
Test name
Test status
Simulation time 89056107 ps
CPU time 1.71 seconds
Started Jun 25 06:26:02 PM PDT 24
Finished Jun 25 06:26:06 PM PDT 24
Peak memory 218596 kb
Host smart-bfd6a46a-54b5-4d56-88e7-778add0642b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263186023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1263186023
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2965200284
Short name T124
Test name
Test status
Simulation time 652667940 ps
CPU time 2.53 seconds
Started Jun 25 06:26:01 PM PDT 24
Finished Jun 25 06:26:07 PM PDT 24
Peak memory 217640 kb
Host smart-a0cd403a-3fb1-4cab-a1b5-88c449e69a9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965200284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2965200284
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.4280198588
Short name T877
Test name
Test status
Simulation time 28797998 ps
CPU time 1.3 seconds
Started Jun 25 06:26:02 PM PDT 24
Finished Jun 25 06:26:06 PM PDT 24
Peak memory 217784 kb
Host smart-1dde5b7a-551e-4e1e-8e02-dbf85bf3cd0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280198588 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.4280198588
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2439123756
Short name T973
Test name
Test status
Simulation time 55762620 ps
CPU time 0.89 seconds
Started Jun 25 06:26:01 PM PDT 24
Finished Jun 25 06:26:04 PM PDT 24
Peak memory 209288 kb
Host smart-4c071932-1d23-481a-b446-70350fe7084d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439123756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.2439123756
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.835929873
Short name T936
Test name
Test status
Simulation time 48257608 ps
CPU time 0.99 seconds
Started Jun 25 06:26:01 PM PDT 24
Finished Jun 25 06:26:05 PM PDT 24
Peak memory 209456 kb
Host smart-616e53ab-0a4c-44c5-852f-985f1eb3c024
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835929873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_same_csr_outstanding.835929873
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.8962444
Short name T120
Test name
Test status
Simulation time 183579234 ps
CPU time 3.94 seconds
Started Jun 25 06:26:00 PM PDT 24
Finished Jun 25 06:26:07 PM PDT 24
Peak memory 217508 kb
Host smart-3a946e5d-debb-4a8e-b1f1-e72e2bfc4d51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8962444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.8962444
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.90067352
Short name T114
Test name
Test status
Simulation time 144705669 ps
CPU time 1.39 seconds
Started Jun 25 06:26:03 PM PDT 24
Finished Jun 25 06:26:06 PM PDT 24
Peak memory 219728 kb
Host smart-5acc9b45-7f95-473e-8687-3d300c75a839
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90067352 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.90067352
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1289013790
Short name T932
Test name
Test status
Simulation time 55962346 ps
CPU time 1.01 seconds
Started Jun 25 06:26:01 PM PDT 24
Finished Jun 25 06:26:05 PM PDT 24
Peak memory 209284 kb
Host smart-2fafdf62-5c12-4dec-b376-7787d2d3d56a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289013790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1289013790
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.359406467
Short name T181
Test name
Test status
Simulation time 39988448 ps
CPU time 1.77 seconds
Started Jun 25 06:26:02 PM PDT 24
Finished Jun 25 06:26:06 PM PDT 24
Peak memory 217564 kb
Host smart-5bf3c4d5-52b1-4e28-b95f-dc17202ac557
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359406467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_same_csr_outstanding.359406467
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1072457687
Short name T971
Test name
Test status
Simulation time 72390542 ps
CPU time 1.46 seconds
Started Jun 25 06:26:02 PM PDT 24
Finished Jun 25 06:26:06 PM PDT 24
Peak memory 218396 kb
Host smart-8a242db4-4c94-4687-b3bd-069a0c53be0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072457687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.1072457687
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3857601610
Short name T978
Test name
Test status
Simulation time 100154311 ps
CPU time 1.77 seconds
Started Jun 25 06:26:09 PM PDT 24
Finished Jun 25 06:26:13 PM PDT 24
Peak memory 217584 kb
Host smart-fe1779f1-1c40-47ee-bfd8-9c9b10cbe974
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857601610 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.3857601610
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.535225824
Short name T176
Test name
Test status
Simulation time 45691266 ps
CPU time 0.86 seconds
Started Jun 25 06:26:08 PM PDT 24
Finished Jun 25 06:26:10 PM PDT 24
Peak memory 209168 kb
Host smart-e8e2cf72-f312-4d92-b66a-08ab57e2b304
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535225824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.535225824
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2322699245
Short name T179
Test name
Test status
Simulation time 38660457 ps
CPU time 1.55 seconds
Started Jun 25 06:26:10 PM PDT 24
Finished Jun 25 06:26:13 PM PDT 24
Peak memory 211484 kb
Host smart-3293d05a-ddf7-43e6-9d3e-56d6fca0eec1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322699245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.2322699245
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2619527423
Short name T116
Test name
Test status
Simulation time 125231848 ps
CPU time 2.43 seconds
Started Jun 25 06:26:02 PM PDT 24
Finished Jun 25 06:26:07 PM PDT 24
Peak memory 217500 kb
Host smart-c5a394ab-8917-47e2-b586-341f1897e569
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619527423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.2619527423
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3107466645
Short name T875
Test name
Test status
Simulation time 107660861 ps
CPU time 1.12 seconds
Started Jun 25 06:26:09 PM PDT 24
Finished Jun 25 06:26:12 PM PDT 24
Peak memory 218632 kb
Host smart-17a9ce22-8dd6-4bb2-b4c4-d89ff3b2c442
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107466645 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3107466645
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2232179827
Short name T175
Test name
Test status
Simulation time 14873112 ps
CPU time 0.9 seconds
Started Jun 25 06:26:09 PM PDT 24
Finished Jun 25 06:26:12 PM PDT 24
Peak memory 209300 kb
Host smart-651c8a8d-bbda-4622-8bae-ad0525e6ce06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232179827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2232179827
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1700578319
Short name T970
Test name
Test status
Simulation time 22266301 ps
CPU time 1.15 seconds
Started Jun 25 06:26:09 PM PDT 24
Finished Jun 25 06:26:11 PM PDT 24
Peak memory 209372 kb
Host smart-20a321a6-5886-4816-abfb-ca759ff9253a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700578319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.1700578319
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2667263544
Short name T921
Test name
Test status
Simulation time 51833055 ps
CPU time 1.91 seconds
Started Jun 25 06:26:08 PM PDT 24
Finished Jun 25 06:26:11 PM PDT 24
Peak memory 217500 kb
Host smart-3cda9e2b-dd0b-4c38-9b91-42976c6f1215
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667263544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2667263544
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3903857754
Short name T131
Test name
Test status
Simulation time 461309489 ps
CPU time 4.05 seconds
Started Jun 25 06:26:07 PM PDT 24
Finished Jun 25 06:26:13 PM PDT 24
Peak memory 217624 kb
Host smart-bc86bc82-5bb3-49eb-b86a-1fdd48c49c43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903857754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.3903857754
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3042952714
Short name T170
Test name
Test status
Simulation time 23822231 ps
CPU time 1.11 seconds
Started Jun 25 06:25:41 PM PDT 24
Finished Jun 25 06:25:43 PM PDT 24
Peak memory 209288 kb
Host smart-033efa1b-98fc-4425-b3a4-752ae3e7159c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042952714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.3042952714
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1362361150
Short name T980
Test name
Test status
Simulation time 40556521 ps
CPU time 1.89 seconds
Started Jun 25 06:25:40 PM PDT 24
Finished Jun 25 06:25:43 PM PDT 24
Peak memory 209316 kb
Host smart-5c729d5e-b49d-4876-9a33-a1c3b92f0228
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362361150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.1362361150
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2622504857
Short name T993
Test name
Test status
Simulation time 16829046 ps
CPU time 1.26 seconds
Started Jun 25 06:25:42 PM PDT 24
Finished Jun 25 06:25:44 PM PDT 24
Peak memory 211368 kb
Host smart-b3bec514-900b-42bf-84ed-a79ef9608ddc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622504857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.2622504857
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.4214930847
Short name T930
Test name
Test status
Simulation time 29279860 ps
CPU time 1.08 seconds
Started Jun 25 06:25:38 PM PDT 24
Finished Jun 25 06:25:40 PM PDT 24
Peak memory 217540 kb
Host smart-597513c5-f1f0-414c-a900-3a72dbdab506
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214930847 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.4214930847
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3840196881
Short name T177
Test name
Test status
Simulation time 13688053 ps
CPU time 1.09 seconds
Started Jun 25 06:25:38 PM PDT 24
Finished Jun 25 06:25:40 PM PDT 24
Peak memory 209008 kb
Host smart-1cdc2847-dba4-4f8b-8e2e-e2a59568f01b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840196881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3840196881
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3739182174
Short name T882
Test name
Test status
Simulation time 45743610 ps
CPU time 1.81 seconds
Started Jun 25 06:25:30 PM PDT 24
Finished Jun 25 06:25:33 PM PDT 24
Peak memory 209196 kb
Host smart-ff0a2c49-b42b-4951-b031-d39ab5b60d18
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739182174 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3739182174
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.377843045
Short name T969
Test name
Test status
Simulation time 1175318010 ps
CPU time 6.75 seconds
Started Jun 25 06:25:33 PM PDT 24
Finished Jun 25 06:25:40 PM PDT 24
Peak memory 208928 kb
Host smart-a909cfbf-9738-446d-9289-3d53d958d11d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377843045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.377843045
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2473271145
Short name T896
Test name
Test status
Simulation time 10346764499 ps
CPU time 15.08 seconds
Started Jun 25 06:25:34 PM PDT 24
Finished Jun 25 06:25:50 PM PDT 24
Peak memory 209280 kb
Host smart-d37187c0-37c3-4c1d-9324-9cc0df4ffc21
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473271145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.2473271145
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4186584401
Short name T910
Test name
Test status
Simulation time 80407523 ps
CPU time 1.85 seconds
Started Jun 25 06:25:23 PM PDT 24
Finished Jun 25 06:25:26 PM PDT 24
Peak memory 217444 kb
Host smart-a73bd79b-6a70-472c-a3d5-e1c7d7254eef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186584401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.4186584401
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2140306801
Short name T893
Test name
Test status
Simulation time 269900893 ps
CPU time 2.07 seconds
Started Jun 25 06:25:31 PM PDT 24
Finished Jun 25 06:25:34 PM PDT 24
Peak memory 217560 kb
Host smart-3b9703fb-bb0e-4a54-982a-f6d271a32971
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214030
6801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2140306801
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3668662158
Short name T873
Test name
Test status
Simulation time 455198508 ps
CPU time 1.44 seconds
Started Jun 25 06:25:34 PM PDT 24
Finished Jun 25 06:25:36 PM PDT 24
Peak memory 209116 kb
Host smart-02cc290b-a0b0-4628-984e-300dcb7ca09c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668662158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3668662158
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.89822362
Short name T147
Test name
Test status
Simulation time 24044202 ps
CPU time 1.05 seconds
Started Jun 25 06:25:35 PM PDT 24
Finished Jun 25 06:25:37 PM PDT 24
Peak memory 217620 kb
Host smart-91eaed15-7c9b-41ef-81cb-f644392629e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89822362 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.89822362
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.211026811
Short name T906
Test name
Test status
Simulation time 16848983 ps
CPU time 1.01 seconds
Started Jun 25 06:25:39 PM PDT 24
Finished Jun 25 06:25:41 PM PDT 24
Peak memory 209480 kb
Host smart-8fd26d09-c462-4aae-bd63-069cf60aae9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211026811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
same_csr_outstanding.211026811
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.983620897
Short name T942
Test name
Test status
Simulation time 299610235 ps
CPU time 2.42 seconds
Started Jun 25 06:25:42 PM PDT 24
Finished Jun 25 06:25:45 PM PDT 24
Peak memory 217496 kb
Host smart-9362d391-3c71-48e2-b081-284858e9bf9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983620897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.983620897
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2231385065
Short name T135
Test name
Test status
Simulation time 50104374 ps
CPU time 2.04 seconds
Started Jun 25 06:25:39 PM PDT 24
Finished Jun 25 06:25:43 PM PDT 24
Peak memory 221848 kb
Host smart-521e2fcd-e7d3-4151-974d-256bf1e3e28d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231385065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2231385065
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.854293307
Short name T173
Test name
Test status
Simulation time 24652138 ps
CPU time 1.46 seconds
Started Jun 25 06:25:41 PM PDT 24
Finished Jun 25 06:25:43 PM PDT 24
Peak memory 217472 kb
Host smart-8452ff3d-e403-4c61-8f6f-e8ba38b2e279
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854293307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing
.854293307
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3412942
Short name T951
Test name
Test status
Simulation time 50924543 ps
CPU time 1.86 seconds
Started Jun 25 06:25:40 PM PDT 24
Finished Jun 25 06:25:43 PM PDT 24
Peak memory 209268 kb
Host smart-1f5dff8a-4fd2-438c-824c-003d69fa5e8a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bash.3412942
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3942789769
Short name T178
Test name
Test status
Simulation time 66128464 ps
CPU time 1.07 seconds
Started Jun 25 06:25:38 PM PDT 24
Finished Jun 25 06:25:40 PM PDT 24
Peak memory 209832 kb
Host smart-5f92e716-e936-4efa-a20e-5b33d0c8eb07
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942789769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3942789769
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3141128055
Short name T123
Test name
Test status
Simulation time 19732431 ps
CPU time 1.32 seconds
Started Jun 25 06:25:40 PM PDT 24
Finished Jun 25 06:25:43 PM PDT 24
Peak memory 217872 kb
Host smart-84e5e071-973b-4a4e-bd53-520c765ab276
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141128055 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3141128055
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.371499995
Short name T983
Test name
Test status
Simulation time 43143786 ps
CPU time 0.87 seconds
Started Jun 25 06:25:39 PM PDT 24
Finished Jun 25 06:25:41 PM PDT 24
Peak memory 209332 kb
Host smart-950a4bee-da58-45e2-a70c-7443154b9a40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371499995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.371499995
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1760057702
Short name T894
Test name
Test status
Simulation time 97042824 ps
CPU time 1.22 seconds
Started Jun 25 06:25:40 PM PDT 24
Finished Jun 25 06:25:42 PM PDT 24
Peak memory 209208 kb
Host smart-73aa5f3c-4a6d-4d45-abfe-0bc1490af633
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760057702 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.1760057702
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3785846055
Short name T139
Test name
Test status
Simulation time 588751780 ps
CPU time 13.92 seconds
Started Jun 25 06:25:40 PM PDT 24
Finished Jun 25 06:25:55 PM PDT 24
Peak memory 209028 kb
Host smart-4bc4921c-a55c-43fe-89ad-6d4f94f6282d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785846055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3785846055
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2146775556
Short name T140
Test name
Test status
Simulation time 1236843959 ps
CPU time 29.42 seconds
Started Jun 25 06:25:41 PM PDT 24
Finished Jun 25 06:26:11 PM PDT 24
Peak memory 209076 kb
Host smart-35546839-b33e-4f37-8d09-170779269bc5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146775556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.2146775556
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3915606784
Short name T989
Test name
Test status
Simulation time 120812540 ps
CPU time 2.02 seconds
Started Jun 25 06:25:38 PM PDT 24
Finished Jun 25 06:25:41 PM PDT 24
Peak memory 217384 kb
Host smart-c2f8b52b-3d83-41ab-bfd1-f07c99800bfd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915606784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3915606784
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3160237843
Short name T990
Test name
Test status
Simulation time 355414113 ps
CPU time 2.73 seconds
Started Jun 25 06:25:40 PM PDT 24
Finished Jun 25 06:25:44 PM PDT 24
Peak memory 219236 kb
Host smart-c690633d-739d-4287-a3d2-12cfc8d20e29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316023
7843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3160237843
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2456919682
Short name T995
Test name
Test status
Simulation time 129548246 ps
CPU time 3.57 seconds
Started Jun 25 06:25:40 PM PDT 24
Finished Jun 25 06:25:45 PM PDT 24
Peak memory 209240 kb
Host smart-542eb537-a61d-4a74-9018-621c8cfd10d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456919682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2456919682
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1639823499
Short name T986
Test name
Test status
Simulation time 23458742 ps
CPU time 1.2 seconds
Started Jun 25 06:25:41 PM PDT 24
Finished Jun 25 06:25:43 PM PDT 24
Peak memory 217624 kb
Host smart-5d31cb27-637f-492c-8a3e-9c1b535c7d15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639823499 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1639823499
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1574698626
Short name T879
Test name
Test status
Simulation time 45653752 ps
CPU time 1.92 seconds
Started Jun 25 06:25:38 PM PDT 24
Finished Jun 25 06:25:40 PM PDT 24
Peak memory 211240 kb
Host smart-2f701352-6fd6-4827-816a-865ba0b19451
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574698626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.1574698626
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.419274723
Short name T937
Test name
Test status
Simulation time 219165401 ps
CPU time 4.09 seconds
Started Jun 25 06:25:41 PM PDT 24
Finished Jun 25 06:25:46 PM PDT 24
Peak memory 217328 kb
Host smart-9f0ee46a-843e-41d7-8c31-205cdb8216fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419274723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.419274723
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2866436437
Short name T891
Test name
Test status
Simulation time 20135856 ps
CPU time 1.4 seconds
Started Jun 25 06:25:49 PM PDT 24
Finished Jun 25 06:25:53 PM PDT 24
Peak memory 207852 kb
Host smart-949f5a9b-d684-493e-ad3e-b74c53975277
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866436437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2866436437
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.183163115
Short name T943
Test name
Test status
Simulation time 385446529 ps
CPU time 3.05 seconds
Started Jun 25 06:25:50 PM PDT 24
Finished Jun 25 06:25:55 PM PDT 24
Peak memory 209288 kb
Host smart-0fac301f-d8fb-45c2-9e17-c591d0a82b3f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183163115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash
.183163115
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.4167483979
Short name T960
Test name
Test status
Simulation time 82779672 ps
CPU time 0.95 seconds
Started Jun 25 06:25:46 PM PDT 24
Finished Jun 25 06:25:48 PM PDT 24
Peak memory 209712 kb
Host smart-55efbdd4-0578-45d1-ac6b-6fff4843b15f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167483979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.4167483979
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2833679911
Short name T883
Test name
Test status
Simulation time 17437735 ps
CPU time 1.21 seconds
Started Jun 25 06:25:48 PM PDT 24
Finished Jun 25 06:25:52 PM PDT 24
Peak memory 217740 kb
Host smart-d4eb4e1b-c35a-405d-a019-e879a8abd53c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833679911 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.2833679911
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1712029193
Short name T913
Test name
Test status
Simulation time 36578298 ps
CPU time 0.88 seconds
Started Jun 25 06:25:47 PM PDT 24
Finished Jun 25 06:25:50 PM PDT 24
Peak memory 209072 kb
Host smart-f042ce85-a73f-451b-99cb-773650b72e81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712029193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.1712029193
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3320979629
Short name T981
Test name
Test status
Simulation time 116434539 ps
CPU time 1.26 seconds
Started Jun 25 06:25:47 PM PDT 24
Finished Jun 25 06:25:51 PM PDT 24
Peak memory 208628 kb
Host smart-b6377a22-5de7-43ae-be1d-225241d60995
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320979629 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3320979629
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3601291761
Short name T916
Test name
Test status
Simulation time 2393990305 ps
CPU time 5.98 seconds
Started Jun 25 06:25:49 PM PDT 24
Finished Jun 25 06:25:57 PM PDT 24
Peak memory 209168 kb
Host smart-a66e8aeb-5eab-4734-b235-eca7fb88e07f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601291761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3601291761
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.4119109921
Short name T186
Test name
Test status
Simulation time 2022828492 ps
CPU time 12.76 seconds
Started Jun 25 06:25:46 PM PDT 24
Finished Jun 25 06:25:59 PM PDT 24
Peak memory 209204 kb
Host smart-cfaa4d9e-a4b0-4d85-b114-d17f54a53e48
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119109921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.4119109921
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2579234898
Short name T965
Test name
Test status
Simulation time 485471036 ps
CPU time 3.47 seconds
Started Jun 25 06:25:38 PM PDT 24
Finished Jun 25 06:25:42 PM PDT 24
Peak memory 217428 kb
Host smart-dd53bde2-9462-44f2-a231-3550887a6c09
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579234898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2579234898
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1546544778
Short name T955
Test name
Test status
Simulation time 72024492 ps
CPU time 2.62 seconds
Started Jun 25 06:25:47 PM PDT 24
Finished Jun 25 06:25:52 PM PDT 24
Peak memory 218448 kb
Host smart-14280363-a8b9-4342-a295-e9c5af27f252
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154654
4778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1546544778
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3570137850
Short name T963
Test name
Test status
Simulation time 79556522 ps
CPU time 1.69 seconds
Started Jun 25 06:25:48 PM PDT 24
Finished Jun 25 06:25:52 PM PDT 24
Peak memory 217284 kb
Host smart-9c7b61ab-3134-4b29-a8ac-c09ac4816456
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570137850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.3570137850
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1643209627
Short name T907
Test name
Test status
Simulation time 17187136 ps
CPU time 1.02 seconds
Started Jun 25 06:25:45 PM PDT 24
Finished Jun 25 06:25:47 PM PDT 24
Peak memory 209296 kb
Host smart-f9a850bc-4464-4692-b4e3-2ffb8e7181e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643209627 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1643209627
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.982956632
Short name T887
Test name
Test status
Simulation time 46698382 ps
CPU time 1.06 seconds
Started Jun 25 06:25:45 PM PDT 24
Finished Jun 25 06:25:47 PM PDT 24
Peak memory 209224 kb
Host smart-e281d7a3-b5f8-4bb0-9fde-08e0a9a54993
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982956632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
same_csr_outstanding.982956632
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2106153877
Short name T946
Test name
Test status
Simulation time 50344467 ps
CPU time 2.12 seconds
Started Jun 25 06:25:47 PM PDT 24
Finished Jun 25 06:25:52 PM PDT 24
Peak memory 217612 kb
Host smart-065ea597-e74c-47bf-a028-2a1e7d1c660f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106153877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2106153877
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3866844723
Short name T136
Test name
Test status
Simulation time 312094743 ps
CPU time 2.12 seconds
Started Jun 25 06:25:49 PM PDT 24
Finished Jun 25 06:25:54 PM PDT 24
Peak memory 220640 kb
Host smart-07b6745f-f82c-4c4f-a806-c5dd20d5caf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866844723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.3866844723
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.754331865
Short name T918
Test name
Test status
Simulation time 24612704 ps
CPU time 1.53 seconds
Started Jun 25 06:25:46 PM PDT 24
Finished Jun 25 06:25:48 PM PDT 24
Peak memory 221480 kb
Host smart-0ac5ea0d-2000-4034-81d8-d16d8916f560
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754331865 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.754331865
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.262671642
Short name T174
Test name
Test status
Simulation time 15643890 ps
CPU time 1.1 seconds
Started Jun 25 06:25:46 PM PDT 24
Finished Jun 25 06:25:48 PM PDT 24
Peak memory 209304 kb
Host smart-ea433a5f-7468-48d4-9ee9-35475533eb9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262671642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.262671642
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2670501417
Short name T977
Test name
Test status
Simulation time 86220066 ps
CPU time 0.82 seconds
Started Jun 25 06:25:46 PM PDT 24
Finished Jun 25 06:25:49 PM PDT 24
Peak memory 208448 kb
Host smart-de1cf66e-5f93-4ffa-ae75-0ee078cbb019
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670501417 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2670501417
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2530849980
Short name T900
Test name
Test status
Simulation time 371638510 ps
CPU time 4.89 seconds
Started Jun 25 06:25:47 PM PDT 24
Finished Jun 25 06:25:54 PM PDT 24
Peak memory 217080 kb
Host smart-6636d676-e683-4e07-aa2b-08897de915dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530849980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2530849980
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1267020386
Short name T874
Test name
Test status
Simulation time 1787200307 ps
CPU time 38.93 seconds
Started Jun 25 06:25:45 PM PDT 24
Finished Jun 25 06:26:24 PM PDT 24
Peak memory 208948 kb
Host smart-458d6dab-7d62-4141-b9c3-b279199b6211
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267020386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1267020386
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.416715048
Short name T138
Test name
Test status
Simulation time 68072759 ps
CPU time 1.53 seconds
Started Jun 25 06:25:47 PM PDT 24
Finished Jun 25 06:25:51 PM PDT 24
Peak memory 217308 kb
Host smart-99ee7c5a-bd12-4f1d-81a4-b152617f6a1e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416715048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.416715048
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3622496056
Short name T976
Test name
Test status
Simulation time 122184710 ps
CPU time 2.15 seconds
Started Jun 25 06:25:50 PM PDT 24
Finished Jun 25 06:25:54 PM PDT 24
Peak memory 217644 kb
Host smart-30aba2cd-b30e-4316-938a-69d4f5172447
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362249
6056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3622496056
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3531760505
Short name T888
Test name
Test status
Simulation time 33503579 ps
CPU time 1.1 seconds
Started Jun 25 06:25:47 PM PDT 24
Finished Jun 25 06:25:51 PM PDT 24
Peak memory 209160 kb
Host smart-d9b0a0f6-13fc-4415-8359-eaf0de3b8bdf
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531760505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3531760505
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.181749794
Short name T926
Test name
Test status
Simulation time 37156337 ps
CPU time 1.51 seconds
Started Jun 25 06:25:47 PM PDT 24
Finished Jun 25 06:25:51 PM PDT 24
Peak memory 209372 kb
Host smart-7509e75f-cc43-4639-9995-ba3c19e92c81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181749794 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.181749794
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1413194802
Short name T185
Test name
Test status
Simulation time 187336155 ps
CPU time 1.17 seconds
Started Jun 25 06:25:47 PM PDT 24
Finished Jun 25 06:25:51 PM PDT 24
Peak memory 209360 kb
Host smart-6acbeb89-3dc7-4782-b3c9-c1016a4488ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413194802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.1413194802
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.733928963
Short name T956
Test name
Test status
Simulation time 344777018 ps
CPU time 1.91 seconds
Started Jun 25 06:25:47 PM PDT 24
Finished Jun 25 06:25:51 PM PDT 24
Peak memory 217480 kb
Host smart-43c3941e-f7d1-43d7-8fc5-957da0eca154
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733928963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.733928963
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3008077492
Short name T117
Test name
Test status
Simulation time 114301701 ps
CPU time 4.25 seconds
Started Jun 25 06:25:46 PM PDT 24
Finished Jun 25 06:25:53 PM PDT 24
Peak memory 217644 kb
Host smart-7edb2510-f327-4420-81f2-3d1b4892d4e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008077492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.3008077492
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2363104787
Short name T962
Test name
Test status
Simulation time 25618012 ps
CPU time 1.51 seconds
Started Jun 25 06:25:48 PM PDT 24
Finished Jun 25 06:25:52 PM PDT 24
Peak memory 217704 kb
Host smart-21e57720-e7a3-4633-affd-ddaff2277af7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363104787 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2363104787
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3782752123
Short name T172
Test name
Test status
Simulation time 23453877 ps
CPU time 0.85 seconds
Started Jun 25 06:25:46 PM PDT 24
Finished Jun 25 06:25:48 PM PDT 24
Peak memory 209096 kb
Host smart-943e1f7e-2b4a-41f4-b8e8-69cb087798bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782752123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3782752123
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.545064635
Short name T992
Test name
Test status
Simulation time 101184763 ps
CPU time 0.9 seconds
Started Jun 25 06:25:48 PM PDT 24
Finished Jun 25 06:25:51 PM PDT 24
Peak memory 209140 kb
Host smart-b7c1b136-7a7b-4425-86b5-55aca3d23180
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545064635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.lc_ctrl_jtag_alert_test.545064635
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1037762211
Short name T966
Test name
Test status
Simulation time 2578978627 ps
CPU time 4.21 seconds
Started Jun 25 06:25:47 PM PDT 24
Finished Jun 25 06:25:53 PM PDT 24
Peak memory 209176 kb
Host smart-ef5315bf-642e-4047-8b50-7b5b359f19d2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037762211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1037762211
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2228114297
Short name T952
Test name
Test status
Simulation time 1246761139 ps
CPU time 12.06 seconds
Started Jun 25 06:25:46 PM PDT 24
Finished Jun 25 06:25:59 PM PDT 24
Peak memory 209248 kb
Host smart-072b0879-49b2-432e-b88f-725399cd1bd7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228114297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.2228114297
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.123663107
Short name T927
Test name
Test status
Simulation time 126269676 ps
CPU time 1.45 seconds
Started Jun 25 06:25:46 PM PDT 24
Finished Jun 25 06:25:49 PM PDT 24
Peak memory 210628 kb
Host smart-55ae727a-0ab1-4792-916a-23661ae3b5c3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123663107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.123663107
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3173022570
Short name T106
Test name
Test status
Simulation time 371338514 ps
CPU time 3.62 seconds
Started Jun 25 06:25:47 PM PDT 24
Finished Jun 25 06:25:53 PM PDT 24
Peak memory 218640 kb
Host smart-1c93e433-f747-402d-a7cc-5da57d1ce9bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317302
2570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3173022570
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.150995847
Short name T948
Test name
Test status
Simulation time 65818696 ps
CPU time 2.24 seconds
Started Jun 25 06:25:47 PM PDT 24
Finished Jun 25 06:25:52 PM PDT 24
Peak memory 208516 kb
Host smart-e29a67e8-f192-4c7b-915a-7b99201fa1ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150995847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.150995847
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1323095170
Short name T881
Test name
Test status
Simulation time 18904663 ps
CPU time 1.25 seconds
Started Jun 25 06:25:47 PM PDT 24
Finished Jun 25 06:25:50 PM PDT 24
Peak memory 217584 kb
Host smart-270c9814-0c80-42a7-ba55-5ab067146262
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323095170 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1323095170
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3780261577
Short name T933
Test name
Test status
Simulation time 88184498 ps
CPU time 1.05 seconds
Started Jun 25 06:25:47 PM PDT 24
Finished Jun 25 06:25:51 PM PDT 24
Peak memory 209340 kb
Host smart-d3e51f17-f45e-49fe-aa9e-018ea991cb89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780261577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.3780261577
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.810929521
Short name T890
Test name
Test status
Simulation time 74330952 ps
CPU time 2.83 seconds
Started Jun 25 06:25:47 PM PDT 24
Finished Jun 25 06:25:53 PM PDT 24
Peak memory 217440 kb
Host smart-2dc0e6f6-04db-4d93-ab9d-999f3e95984f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810929521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.810929521
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1129876169
Short name T110
Test name
Test status
Simulation time 63140124 ps
CPU time 2.64 seconds
Started Jun 25 06:25:45 PM PDT 24
Finished Jun 25 06:25:49 PM PDT 24
Peak memory 217636 kb
Host smart-776fab70-3535-44a1-8e3d-b6c46e428a1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129876169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.1129876169
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3988734279
Short name T938
Test name
Test status
Simulation time 29888501 ps
CPU time 2.25 seconds
Started Jun 25 06:25:54 PM PDT 24
Finished Jun 25 06:25:59 PM PDT 24
Peak memory 217616 kb
Host smart-9dcb2bf7-9e13-4309-841f-435318a64f1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988734279 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3988734279
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3194583243
Short name T113
Test name
Test status
Simulation time 20614946 ps
CPU time 0.88 seconds
Started Jun 25 06:25:54 PM PDT 24
Finished Jun 25 06:25:56 PM PDT 24
Peak memory 209056 kb
Host smart-661c93a2-3f82-4436-a3ed-101896b2f041
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194583243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.3194583243
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.768042266
Short name T961
Test name
Test status
Simulation time 61530021 ps
CPU time 1.33 seconds
Started Jun 25 06:25:57 PM PDT 24
Finished Jun 25 06:26:01 PM PDT 24
Peak memory 208628 kb
Host smart-7fa513b4-999c-409d-8a62-685511c45603
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768042266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.lc_ctrl_jtag_alert_test.768042266
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2151904859
Short name T953
Test name
Test status
Simulation time 1981709549 ps
CPU time 8.38 seconds
Started Jun 25 06:25:46 PM PDT 24
Finished Jun 25 06:25:57 PM PDT 24
Peak memory 208824 kb
Host smart-e18155c9-1d5d-403f-9973-ed10992d9124
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151904859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2151904859
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.752708822
Short name T876
Test name
Test status
Simulation time 973557109 ps
CPU time 10.69 seconds
Started Jun 25 06:25:45 PM PDT 24
Finished Jun 25 06:25:57 PM PDT 24
Peak memory 209304 kb
Host smart-163cd4dc-da8d-45cd-9a01-0a4957f39e56
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752708822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.752708822
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3616492662
Short name T999
Test name
Test status
Simulation time 120319353 ps
CPU time 2.99 seconds
Started Jun 25 06:25:50 PM PDT 24
Finished Jun 25 06:25:55 PM PDT 24
Peak memory 217428 kb
Host smart-033b4079-8117-4280-90dc-a60fd5896cc9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616492662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3616492662
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3159424199
Short name T107
Test name
Test status
Simulation time 137282521 ps
CPU time 1.44 seconds
Started Jun 25 06:25:53 PM PDT 24
Finished Jun 25 06:25:56 PM PDT 24
Peak memory 218628 kb
Host smart-fa8406fa-e0dc-41c9-8179-f6e174642235
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315942
4199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3159424199
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2993325339
Short name T901
Test name
Test status
Simulation time 66201688 ps
CPU time 1.61 seconds
Started Jun 25 06:25:47 PM PDT 24
Finished Jun 25 06:25:51 PM PDT 24
Peak memory 216512 kb
Host smart-221bd051-f0ac-4834-be8f-eb3f5c908892
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993325339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2993325339
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.805056417
Short name T183
Test name
Test status
Simulation time 201436014 ps
CPU time 2.06 seconds
Started Jun 25 06:25:47 PM PDT 24
Finished Jun 25 06:25:51 PM PDT 24
Peak memory 209368 kb
Host smart-f63ec969-ec43-4c02-bbb5-280ea7653549
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805056417 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.805056417
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.136773385
Short name T182
Test name
Test status
Simulation time 48144721 ps
CPU time 2.05 seconds
Started Jun 25 06:25:54 PM PDT 24
Finished Jun 25 06:25:57 PM PDT 24
Peak memory 209356 kb
Host smart-ca84eeba-06e5-48d8-b6b5-8c8ed8f14393
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136773385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
same_csr_outstanding.136773385
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.792684092
Short name T920
Test name
Test status
Simulation time 105720559 ps
CPU time 2.5 seconds
Started Jun 25 06:25:56 PM PDT 24
Finished Jun 25 06:26:01 PM PDT 24
Peak memory 217524 kb
Host smart-26ba34d8-b34a-4840-8ecb-c72e6e6e9686
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792684092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.792684092
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3783887050
Short name T957
Test name
Test status
Simulation time 50099938 ps
CPU time 1.14 seconds
Started Jun 25 06:25:58 PM PDT 24
Finished Jun 25 06:26:01 PM PDT 24
Peak memory 217612 kb
Host smart-8e48c445-10bb-47d4-830f-f3c6e2387dfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783887050 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3783887050
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2443602079
Short name T922
Test name
Test status
Simulation time 14893613 ps
CPU time 0.9 seconds
Started Jun 25 06:25:59 PM PDT 24
Finished Jun 25 06:26:02 PM PDT 24
Peak memory 209300 kb
Host smart-85ccd51b-086f-4ee9-9e5f-9ac52dd16606
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443602079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2443602079
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1657727896
Short name T974
Test name
Test status
Simulation time 21605988 ps
CPU time 0.9 seconds
Started Jun 25 06:25:56 PM PDT 24
Finished Jun 25 06:26:00 PM PDT 24
Peak memory 208624 kb
Host smart-4af30eaa-cd3e-4851-a7bb-1c7285a08990
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657727896 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.1657727896
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.285411138
Short name T914
Test name
Test status
Simulation time 1169872652 ps
CPU time 6.25 seconds
Started Jun 25 06:25:55 PM PDT 24
Finished Jun 25 06:26:03 PM PDT 24
Peak memory 217076 kb
Host smart-bb7ebc3b-fc41-4293-afdb-a2594b4550a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285411138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.285411138
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3935476485
Short name T945
Test name
Test status
Simulation time 2069900215 ps
CPU time 23.94 seconds
Started Jun 25 06:25:55 PM PDT 24
Finished Jun 25 06:26:21 PM PDT 24
Peak memory 208996 kb
Host smart-3b6c3d33-77be-4b94-b353-84e7be522cf0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935476485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3935476485
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.856129335
Short name T975
Test name
Test status
Simulation time 475274558 ps
CPU time 1.41 seconds
Started Jun 25 06:25:55 PM PDT 24
Finished Jun 25 06:25:58 PM PDT 24
Peak memory 210700 kb
Host smart-2f5654eb-6d4f-480f-8623-1117b18ce71e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856129335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.856129335
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2437038464
Short name T885
Test name
Test status
Simulation time 350485151 ps
CPU time 3.11 seconds
Started Jun 25 06:25:53 PM PDT 24
Finished Jun 25 06:25:57 PM PDT 24
Peak memory 217372 kb
Host smart-c8e4b9f3-9192-4c71-ada8-d99a962fdb5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437038464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.2437038464
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1547332915
Short name T925
Test name
Test status
Simulation time 27577210 ps
CPU time 0.99 seconds
Started Jun 25 06:25:54 PM PDT 24
Finished Jun 25 06:25:57 PM PDT 24
Peak memory 209368 kb
Host smart-c28a8986-a6bf-4137-a07a-ac21da2aa847
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547332915 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.1547332915
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3987989390
Short name T886
Test name
Test status
Simulation time 61032060 ps
CPU time 1.35 seconds
Started Jun 25 06:25:55 PM PDT 24
Finished Jun 25 06:25:58 PM PDT 24
Peak memory 209332 kb
Host smart-70245d24-3a81-4b10-bf8e-1cdc24b360d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987989390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.3987989390
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3039812531
Short name T103
Test name
Test status
Simulation time 112129335 ps
CPU time 2.93 seconds
Started Jun 25 06:25:56 PM PDT 24
Finished Jun 25 06:26:01 PM PDT 24
Peak memory 217664 kb
Host smart-a6c6175a-60a3-409b-944c-105d3455cb21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039812531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3039812531
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.183572867
Short name T146
Test name
Test status
Simulation time 53245346 ps
CPU time 1.6 seconds
Started Jun 25 06:25:54 PM PDT 24
Finished Jun 25 06:25:58 PM PDT 24
Peak memory 217632 kb
Host smart-0756c834-1183-4ee7-9da4-64843c796aa0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183572867 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.183572867
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2162675418
Short name T968
Test name
Test status
Simulation time 62750406 ps
CPU time 0.85 seconds
Started Jun 25 06:25:57 PM PDT 24
Finished Jun 25 06:26:00 PM PDT 24
Peak memory 209176 kb
Host smart-c38446dc-6575-4efb-98ed-3313c4ef0143
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162675418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.2162675418
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2674012453
Short name T915
Test name
Test status
Simulation time 70580586 ps
CPU time 0.89 seconds
Started Jun 25 06:25:55 PM PDT 24
Finished Jun 25 06:25:58 PM PDT 24
Peak memory 208632 kb
Host smart-9793950f-9319-4290-8e69-6023742c6406
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674012453 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2674012453
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2890515449
Short name T903
Test name
Test status
Simulation time 3303147739 ps
CPU time 3.98 seconds
Started Jun 25 06:25:56 PM PDT 24
Finished Jun 25 06:26:02 PM PDT 24
Peak memory 209160 kb
Host smart-d24e7089-457c-4960-a1f9-420454f6377d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890515449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2890515449
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1978077595
Short name T187
Test name
Test status
Simulation time 4937872280 ps
CPU time 12.56 seconds
Started Jun 25 06:25:59 PM PDT 24
Finished Jun 25 06:26:14 PM PDT 24
Peak memory 209200 kb
Host smart-06aeec43-ca8a-4c55-94eb-207b7d911d4c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978077595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1978077595
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1231121324
Short name T898
Test name
Test status
Simulation time 82109588 ps
CPU time 1.43 seconds
Started Jun 25 06:25:58 PM PDT 24
Finished Jun 25 06:26:01 PM PDT 24
Peak memory 210636 kb
Host smart-d893eebb-9509-449e-87c2-d55a60f75055
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231121324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.1231121324
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3330168971
Short name T947
Test name
Test status
Simulation time 370657078 ps
CPU time 2.79 seconds
Started Jun 25 06:25:54 PM PDT 24
Finished Jun 25 06:25:58 PM PDT 24
Peak memory 217892 kb
Host smart-c4f1e061-34a0-4b48-962e-a4f49d3f79d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333016
8971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3330168971
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.364524963
Short name T908
Test name
Test status
Simulation time 569513514 ps
CPU time 1.35 seconds
Started Jun 25 06:25:54 PM PDT 24
Finished Jun 25 06:25:57 PM PDT 24
Peak memory 217228 kb
Host smart-36fef4cc-af65-4df9-b93f-07e3bd3f27c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364524963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.364524963
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1360490943
Short name T184
Test name
Test status
Simulation time 25695735 ps
CPU time 1.35 seconds
Started Jun 25 06:25:54 PM PDT 24
Finished Jun 25 06:25:58 PM PDT 24
Peak memory 209300 kb
Host smart-919d8450-1fd1-4f26-8206-6570ba5baf30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360490943 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1360490943
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4210328987
Short name T967
Test name
Test status
Simulation time 156860006 ps
CPU time 1.05 seconds
Started Jun 25 06:25:55 PM PDT 24
Finished Jun 25 06:25:58 PM PDT 24
Peak memory 209364 kb
Host smart-39ee412e-cd38-4c5a-8e0d-8e92a9d7521c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210328987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.4210328987
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3945935523
Short name T115
Test name
Test status
Simulation time 52467572 ps
CPU time 1.35 seconds
Started Jun 25 06:25:52 PM PDT 24
Finished Jun 25 06:25:55 PM PDT 24
Peak memory 217524 kb
Host smart-5c25bbd9-caf9-4f61-ab2e-634118ad442d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945935523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.3945935523
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1254388149
Short name T133
Test name
Test status
Simulation time 231684619 ps
CPU time 3.08 seconds
Started Jun 25 06:25:58 PM PDT 24
Finished Jun 25 06:26:02 PM PDT 24
Peak memory 222420 kb
Host smart-fcd50c74-22b4-4d84-a5cc-31e5107b9ec6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254388149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.1254388149
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.2846093380
Short name T237
Test name
Test status
Simulation time 18597491 ps
CPU time 0.95 seconds
Started Jun 25 06:26:15 PM PDT 24
Finished Jun 25 06:26:17 PM PDT 24
Peak memory 209396 kb
Host smart-37133d9a-a272-490e-a619-8d765aa02f1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846093380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2846093380
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.684895654
Short name T673
Test name
Test status
Simulation time 32298970 ps
CPU time 0.81 seconds
Started Jun 25 06:26:09 PM PDT 24
Finished Jun 25 06:26:11 PM PDT 24
Peak memory 209200 kb
Host smart-2ae9aa84-af0a-49c0-8e14-197c2705e64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684895654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.684895654
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.3732880310
Short name T210
Test name
Test status
Simulation time 792328083 ps
CPU time 10.81 seconds
Started Jun 25 06:26:10 PM PDT 24
Finished Jun 25 06:26:22 PM PDT 24
Peak memory 218416 kb
Host smart-01e0f9ac-b454-42ed-9b3b-1420cefbb934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732880310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.3732880310
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2236199070
Short name T345
Test name
Test status
Simulation time 1110753950 ps
CPU time 1.54 seconds
Started Jun 25 06:26:16 PM PDT 24
Finished Jun 25 06:26:19 PM PDT 24
Peak memory 217348 kb
Host smart-f9cb8bdd-65bf-4095-bf41-277bec6ea5b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236199070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2236199070
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3309791554
Short name T591
Test name
Test status
Simulation time 9352706514 ps
CPU time 25.9 seconds
Started Jun 25 06:26:08 PM PDT 24
Finished Jun 25 06:26:35 PM PDT 24
Peak memory 218476 kb
Host smart-31756a8c-8290-406b-955a-160d8e658ab6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309791554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3309791554
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.2797435386
Short name T755
Test name
Test status
Simulation time 403676525 ps
CPU time 10.46 seconds
Started Jun 25 06:26:16 PM PDT 24
Finished Jun 25 06:26:28 PM PDT 24
Peak memory 217740 kb
Host smart-30309c2c-b274-490f-9aaf-ff5fd15080d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797435386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.2
797435386
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3766822359
Short name T479
Test name
Test status
Simulation time 2740342838 ps
CPU time 12.75 seconds
Started Jun 25 06:26:07 PM PDT 24
Finished Jun 25 06:26:21 PM PDT 24
Peak memory 218588 kb
Host smart-82b200f4-5d01-4850-adad-8ebd4fcf93d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766822359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3766822359
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2553143674
Short name T77
Test name
Test status
Simulation time 950610044 ps
CPU time 24.88 seconds
Started Jun 25 06:26:14 PM PDT 24
Finished Jun 25 06:26:40 PM PDT 24
Peak memory 217900 kb
Host smart-58dec0a2-aeff-4ddc-ba75-619271f0570b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553143674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.2553143674
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.959919167
Short name T357
Test name
Test status
Simulation time 94607868 ps
CPU time 2.15 seconds
Started Jun 25 06:26:09 PM PDT 24
Finished Jun 25 06:26:13 PM PDT 24
Peak memory 217932 kb
Host smart-77a947f9-53f8-4062-9462-103930b82407
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959919167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.959919167
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.2605040775
Short name T542
Test name
Test status
Simulation time 1382665324 ps
CPU time 40.37 seconds
Started Jun 25 06:26:09 PM PDT 24
Finished Jun 25 06:26:51 PM PDT 24
Peak memory 251140 kb
Host smart-b380887e-d111-41af-9ef2-0bbadfc09eec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605040775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.2605040775
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1263671309
Short name T363
Test name
Test status
Simulation time 490507915 ps
CPU time 16.91 seconds
Started Jun 25 06:26:09 PM PDT 24
Finished Jun 25 06:26:27 PM PDT 24
Peak memory 226596 kb
Host smart-46747be9-19a5-4c4b-b696-88a941767ce3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263671309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.1263671309
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1052266684
Short name T823
Test name
Test status
Simulation time 44728386 ps
CPU time 2.29 seconds
Started Jun 25 06:26:08 PM PDT 24
Finished Jun 25 06:26:11 PM PDT 24
Peak memory 218424 kb
Host smart-8244c905-33f7-4df5-9e76-2da88aabf792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052266684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1052266684
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.531538704
Short name T805
Test name
Test status
Simulation time 205410705 ps
CPU time 5.26 seconds
Started Jun 25 06:26:09 PM PDT 24
Finished Jun 25 06:26:16 PM PDT 24
Peak memory 214700 kb
Host smart-f1181a61-f808-4449-bced-10a382957c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531538704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.531538704
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.2650565111
Short name T692
Test name
Test status
Simulation time 648202748 ps
CPU time 11.45 seconds
Started Jun 25 06:26:16 PM PDT 24
Finished Jun 25 06:26:29 PM PDT 24
Peak memory 226228 kb
Host smart-568bee70-f185-4d4e-bc28-ad98479da9b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650565111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2650565111
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3555846746
Short name T502
Test name
Test status
Simulation time 242895251 ps
CPU time 11.32 seconds
Started Jun 25 06:26:18 PM PDT 24
Finished Jun 25 06:26:30 PM PDT 24
Peak memory 218312 kb
Host smart-3b982adb-c006-4636-8ebc-4a69de5b3d82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555846746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.3555846746
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.4135565148
Short name T609
Test name
Test status
Simulation time 740565976 ps
CPU time 9.04 seconds
Started Jun 25 06:26:16 PM PDT 24
Finished Jun 25 06:26:26 PM PDT 24
Peak memory 218424 kb
Host smart-2badef5a-f2f7-438c-81c7-4c0a8e987e91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135565148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.4
135565148
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.3732878504
Short name T516
Test name
Test status
Simulation time 996663934 ps
CPU time 10.89 seconds
Started Jun 25 06:26:08 PM PDT 24
Finished Jun 25 06:26:20 PM PDT 24
Peak memory 218484 kb
Host smart-5a4483a2-cc6e-4e75-a76f-2f9fc4528f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732878504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3732878504
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.2184792658
Short name T495
Test name
Test status
Simulation time 53902653 ps
CPU time 3.6 seconds
Started Jun 25 06:26:08 PM PDT 24
Finished Jun 25 06:26:13 PM PDT 24
Peak memory 217912 kb
Host smart-a198a294-85f2-49c3-b0c9-1ac330ab5604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184792658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2184792658
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.2801298792
Short name T462
Test name
Test status
Simulation time 1472195549 ps
CPU time 21.79 seconds
Started Jun 25 06:26:10 PM PDT 24
Finished Jun 25 06:26:34 PM PDT 24
Peak memory 251096 kb
Host smart-7efeb90e-ed53-4ecb-8757-d9929a811f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801298792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2801298792
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2182681597
Short name T367
Test name
Test status
Simulation time 263011318 ps
CPU time 8.17 seconds
Started Jun 25 06:26:09 PM PDT 24
Finished Jun 25 06:26:19 PM PDT 24
Peak memory 251100 kb
Host smart-fa55d8af-50b4-470c-9907-565bdd3261c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182681597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2182681597
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.2172547171
Short name T521
Test name
Test status
Simulation time 13229369722 ps
CPU time 214.66 seconds
Started Jun 25 06:26:15 PM PDT 24
Finished Jun 25 06:29:50 PM PDT 24
Peak memory 260132 kb
Host smart-9d13797d-b91c-4908-8e7c-a4c34133a07a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172547171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.2172547171
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2311178451
Short name T490
Test name
Test status
Simulation time 13009014 ps
CPU time 1.11 seconds
Started Jun 25 06:26:09 PM PDT 24
Finished Jun 25 06:26:12 PM PDT 24
Peak memory 211956 kb
Host smart-174dd95c-c0d1-43c5-b830-4d878bb749c2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311178451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.2311178451
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1946581903
Short name T698
Test name
Test status
Simulation time 18310242 ps
CPU time 0.91 seconds
Started Jun 25 06:26:28 PM PDT 24
Finished Jun 25 06:26:31 PM PDT 24
Peak memory 209120 kb
Host smart-28ab9040-e093-40a1-b755-ed061e2c1c53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946581903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1946581903
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.474630096
Short name T798
Test name
Test status
Simulation time 41951738 ps
CPU time 0.83 seconds
Started Jun 25 06:26:25 PM PDT 24
Finished Jun 25 06:26:28 PM PDT 24
Peak memory 209160 kb
Host smart-a7ec70d3-ea5c-4e7b-adc3-310f9b0af211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474630096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.474630096
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.226590287
Short name T203
Test name
Test status
Simulation time 196226404 ps
CPU time 8.6 seconds
Started Jun 25 06:26:17 PM PDT 24
Finished Jun 25 06:26:27 PM PDT 24
Peak memory 218556 kb
Host smart-51794825-a707-4ff7-b928-7201a9af62c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226590287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.226590287
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.935170715
Short name T160
Test name
Test status
Simulation time 411963395 ps
CPU time 1.85 seconds
Started Jun 25 06:26:24 PM PDT 24
Finished Jun 25 06:26:27 PM PDT 24
Peak memory 217252 kb
Host smart-e8688e29-4a28-4608-b450-098a6dab6f5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935170715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.935170715
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.3103102084
Short name T300
Test name
Test status
Simulation time 1725452381 ps
CPU time 48.53 seconds
Started Jun 25 06:26:26 PM PDT 24
Finished Jun 25 06:27:17 PM PDT 24
Peak memory 218452 kb
Host smart-8be70f28-5263-4550-b9f1-72155a39ffb7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103102084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.3103102084
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.1597408948
Short name T541
Test name
Test status
Simulation time 591505090 ps
CPU time 5.74 seconds
Started Jun 25 06:26:25 PM PDT 24
Finished Jun 25 06:26:34 PM PDT 24
Peak memory 217880 kb
Host smart-cc0085e4-14be-4fb0-b4b2-19c15283f6b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597408948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.1
597408948
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.961416052
Short name T387
Test name
Test status
Simulation time 656325483 ps
CPU time 5.89 seconds
Started Jun 25 06:26:25 PM PDT 24
Finished Jun 25 06:26:34 PM PDT 24
Peak memory 218412 kb
Host smart-cd0246c0-5dde-41fc-9f93-44088f2a1226
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961416052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
prog_failure.961416052
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.4238175185
Short name T287
Test name
Test status
Simulation time 2334265033 ps
CPU time 18.83 seconds
Started Jun 25 06:26:25 PM PDT 24
Finished Jun 25 06:26:46 PM PDT 24
Peak memory 217964 kb
Host smart-1f294ce6-8c04-4950-849e-4d7229579982
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238175185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.4238175185
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3861391064
Short name T383
Test name
Test status
Simulation time 163262606 ps
CPU time 2.77 seconds
Started Jun 25 06:26:25 PM PDT 24
Finished Jun 25 06:26:30 PM PDT 24
Peak memory 217908 kb
Host smart-72e6f530-9a34-4aa2-8057-9cae35c7412d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861391064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3861391064
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.908652258
Short name T365
Test name
Test status
Simulation time 2051293778 ps
CPU time 41.43 seconds
Started Jun 25 06:26:25 PM PDT 24
Finished Jun 25 06:27:08 PM PDT 24
Peak memory 267508 kb
Host smart-468ebf34-e737-4d40-b1ea-5fbfdf379f29
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908652258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.908652258
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.965852442
Short name T784
Test name
Test status
Simulation time 464752847 ps
CPU time 17.05 seconds
Started Jun 25 06:26:25 PM PDT 24
Finished Jun 25 06:26:44 PM PDT 24
Peak memory 246572 kb
Host smart-c031eadb-ea55-4a56-ab99-4441f72fe1d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965852442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_state_post_trans.965852442
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.472881628
Short name T284
Test name
Test status
Simulation time 14497987 ps
CPU time 1.47 seconds
Started Jun 25 06:26:17 PM PDT 24
Finished Jun 25 06:26:20 PM PDT 24
Peak memory 221856 kb
Host smart-d7f486a9-3e68-46f8-a312-2aa70ddb8f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472881628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.472881628
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.1771609068
Short name T82
Test name
Test status
Simulation time 265803730 ps
CPU time 10.73 seconds
Started Jun 25 06:26:25 PM PDT 24
Finished Jun 25 06:26:38 PM PDT 24
Peak memory 214248 kb
Host smart-f1884718-d712-4393-94f6-da290a0b9c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771609068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.1771609068
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.700772344
Short name T54
Test name
Test status
Simulation time 223133525 ps
CPU time 38.18 seconds
Started Jun 25 06:26:28 PM PDT 24
Finished Jun 25 06:27:08 PM PDT 24
Peak memory 282268 kb
Host smart-968283ed-d742-411b-9b47-c2733d97c5dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700772344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.700772344
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.3084418376
Short name T622
Test name
Test status
Simulation time 318841453 ps
CPU time 10.19 seconds
Started Jun 25 06:26:25 PM PDT 24
Finished Jun 25 06:26:38 PM PDT 24
Peak memory 219080 kb
Host smart-bbcdccb7-a193-4b8d-8d0d-ee5cc64b5c31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084418376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.3084418376
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.2273441205
Short name T364
Test name
Test status
Simulation time 900046792 ps
CPU time 9.41 seconds
Started Jun 25 06:26:27 PM PDT 24
Finished Jun 25 06:26:39 PM PDT 24
Peak memory 218448 kb
Host smart-92c92854-ac34-4fc9-974d-128e8dba3509
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273441205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.2273441205
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.4128418153
Short name T813
Test name
Test status
Simulation time 447033618 ps
CPU time 8.97 seconds
Started Jun 25 06:26:25 PM PDT 24
Finished Jun 25 06:26:36 PM PDT 24
Peak memory 218328 kb
Host smart-9c4e2b87-2c38-46f6-b5af-b0902b691b27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128418153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.4
128418153
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.1776519058
Short name T292
Test name
Test status
Simulation time 2478630396 ps
CPU time 16.78 seconds
Started Jun 25 06:26:26 PM PDT 24
Finished Jun 25 06:26:45 PM PDT 24
Peak memory 218568 kb
Host smart-2f9da898-001c-4f08-a78d-f69085214e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776519058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.1776519058
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.1962734978
Short name T278
Test name
Test status
Simulation time 18475688 ps
CPU time 1.52 seconds
Started Jun 25 06:26:16 PM PDT 24
Finished Jun 25 06:26:18 PM PDT 24
Peak memory 217912 kb
Host smart-2f31c340-be9d-47a1-bfff-1bcb309cd924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962734978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1962734978
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.2876617223
Short name T700
Test name
Test status
Simulation time 77409030 ps
CPU time 6.86 seconds
Started Jun 25 06:26:17 PM PDT 24
Finished Jun 25 06:26:25 PM PDT 24
Peak memory 250800 kb
Host smart-dd0782d9-1c60-4709-9225-3ad087ca191b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876617223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2876617223
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.248023683
Short name T822
Test name
Test status
Simulation time 4565041739 ps
CPU time 151.94 seconds
Started Jun 25 06:26:25 PM PDT 24
Finished Jun 25 06:29:00 PM PDT 24
Peak memory 246560 kb
Host smart-d4752d03-90ef-49b0-af5f-9c52f3d246b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248023683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.248023683
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1378235217
Short name T817
Test name
Test status
Simulation time 76029052 ps
CPU time 1.04 seconds
Started Jun 25 06:26:17 PM PDT 24
Finished Jun 25 06:26:20 PM PDT 24
Peak memory 212036 kb
Host smart-a761a490-d642-4fd5-b288-77d237f7f4de
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378235217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1378235217
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.1881357524
Short name T438
Test name
Test status
Simulation time 18786448 ps
CPU time 0.95 seconds
Started Jun 25 06:27:25 PM PDT 24
Finished Jun 25 06:27:27 PM PDT 24
Peak memory 209164 kb
Host smart-221008ea-e784-4a91-867a-b62f8f3c8afc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881357524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.1881357524
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.2115817294
Short name T411
Test name
Test status
Simulation time 456689236 ps
CPU time 10.74 seconds
Started Jun 25 06:27:16 PM PDT 24
Finished Jun 25 06:27:27 PM PDT 24
Peak memory 218332 kb
Host smart-6763954d-00e4-4097-b573-ac3453ac0a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115817294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.2115817294
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.340018168
Short name T857
Test name
Test status
Simulation time 487861143 ps
CPU time 8.15 seconds
Started Jun 25 06:27:18 PM PDT 24
Finished Jun 25 06:27:27 PM PDT 24
Peak memory 217288 kb
Host smart-a57c4892-af6b-4558-a5c8-b9222f08fcd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340018168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.340018168
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.3050229869
Short name T310
Test name
Test status
Simulation time 2030594557 ps
CPU time 32.66 seconds
Started Jun 25 06:27:17 PM PDT 24
Finished Jun 25 06:27:51 PM PDT 24
Peak memory 226228 kb
Host smart-2a51ed5f-68ca-4088-955a-bd2ffb0e2831
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050229869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.3050229869
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.563121319
Short name T583
Test name
Test status
Simulation time 1546028986 ps
CPU time 11.29 seconds
Started Jun 25 06:27:17 PM PDT 24
Finished Jun 25 06:27:30 PM PDT 24
Peak memory 218416 kb
Host smart-3fbb3a5d-d761-4142-b17d-11ea3841cfb1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563121319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag
_prog_failure.563121319
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.137507381
Short name T80
Test name
Test status
Simulation time 1739150783 ps
CPU time 9.65 seconds
Started Jun 25 06:27:16 PM PDT 24
Finished Jun 25 06:27:26 PM PDT 24
Peak memory 217896 kb
Host smart-8dedcee8-d80e-4795-ab30-9575447ce38e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137507381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke.
137507381
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1391557563
Short name T669
Test name
Test status
Simulation time 16556620717 ps
CPU time 42.67 seconds
Started Jun 25 06:27:20 PM PDT 24
Finished Jun 25 06:28:04 PM PDT 24
Peak memory 275756 kb
Host smart-145391ce-b730-49dc-8bbc-fb21f79c853a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391557563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1391557563
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.1859653684
Short name T569
Test name
Test status
Simulation time 3565193492 ps
CPU time 10.27 seconds
Started Jun 25 06:27:17 PM PDT 24
Finished Jun 25 06:27:28 PM PDT 24
Peak memory 223776 kb
Host smart-114dd6a8-ad67-44b3-af94-e8fa48dbf657
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859653684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.1859653684
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2330513334
Short name T206
Test name
Test status
Simulation time 45790648 ps
CPU time 1.39 seconds
Started Jun 25 06:27:15 PM PDT 24
Finished Jun 25 06:27:18 PM PDT 24
Peak memory 218420 kb
Host smart-56289eb9-fd53-48e0-90ad-7238f217554b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330513334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2330513334
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.2399018322
Short name T422
Test name
Test status
Simulation time 450752442 ps
CPU time 13.98 seconds
Started Jun 25 06:27:24 PM PDT 24
Finished Jun 25 06:27:40 PM PDT 24
Peak memory 218436 kb
Host smart-7f5fa285-ace4-41bb-8bd9-6c8f717822df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399018322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.2399018322
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.2419454447
Short name T538
Test name
Test status
Simulation time 3952779154 ps
CPU time 14.44 seconds
Started Jun 25 06:27:23 PM PDT 24
Finished Jun 25 06:27:38 PM PDT 24
Peak memory 218496 kb
Host smart-e675d33c-8e97-4ddc-9470-c983ce70e57c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419454447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.2419454447
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1262823943
Short name T540
Test name
Test status
Simulation time 4322819807 ps
CPU time 10.43 seconds
Started Jun 25 06:27:25 PM PDT 24
Finished Jun 25 06:27:37 PM PDT 24
Peak memory 218468 kb
Host smart-99eddd61-6197-4c55-9627-bed67ce0c1cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262823943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1262823943
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3938891332
Short name T68
Test name
Test status
Simulation time 87408494 ps
CPU time 5.03 seconds
Started Jun 25 06:27:17 PM PDT 24
Finished Jun 25 06:27:23 PM PDT 24
Peak memory 217856 kb
Host smart-c72fdf60-a49f-4ff4-bc38-b323beaac87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938891332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3938891332
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.3985550097
Short name T435
Test name
Test status
Simulation time 5461540897 ps
CPU time 36.97 seconds
Started Jun 25 06:27:18 PM PDT 24
Finished Jun 25 06:27:56 PM PDT 24
Peak memory 251176 kb
Host smart-7c4e6d17-7acc-4ad3-9fe2-a41b2808cc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985550097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.3985550097
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.3247854652
Short name T703
Test name
Test status
Simulation time 162832682 ps
CPU time 8.68 seconds
Started Jun 25 06:27:20 PM PDT 24
Finished Jun 25 06:27:30 PM PDT 24
Peak memory 250964 kb
Host smart-fda328a1-c57b-446f-a497-9305667c98ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247854652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3247854652
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.565648401
Short name T764
Test name
Test status
Simulation time 47318291823 ps
CPU time 119.04 seconds
Started Jun 25 06:27:25 PM PDT 24
Finished Jun 25 06:29:26 PM PDT 24
Peak memory 283924 kb
Host smart-bf2b8ba6-eb94-4bbc-9539-3816746ee190
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565648401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.565648401
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2192713512
Short name T421
Test name
Test status
Simulation time 12409401 ps
CPU time 0.86 seconds
Started Jun 25 06:27:17 PM PDT 24
Finished Jun 25 06:27:19 PM PDT 24
Peak memory 212076 kb
Host smart-963f205a-f08b-44be-b5ea-57f65b0a6783
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192713512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.2192713512
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.1416447093
Short name T781
Test name
Test status
Simulation time 83472765 ps
CPU time 0.97 seconds
Started Jun 25 06:27:31 PM PDT 24
Finished Jun 25 06:27:34 PM PDT 24
Peak memory 209248 kb
Host smart-109da61f-4141-4c64-98e8-e60f2125e570
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416447093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.1416447093
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2080254182
Short name T347
Test name
Test status
Simulation time 1080118553 ps
CPU time 9.75 seconds
Started Jun 25 06:27:24 PM PDT 24
Finished Jun 25 06:27:36 PM PDT 24
Peak memory 226244 kb
Host smart-8382ef88-736e-471a-9f9b-54559a381fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080254182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2080254182
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.454179338
Short name T437
Test name
Test status
Simulation time 939739825 ps
CPU time 10.76 seconds
Started Jun 25 06:27:31 PM PDT 24
Finished Jun 25 06:27:43 PM PDT 24
Peak memory 217596 kb
Host smart-720f0121-de0f-4a55-baab-e648daf70544
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454179338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.454179338
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.4128319527
Short name T632
Test name
Test status
Simulation time 10639756310 ps
CPU time 71.12 seconds
Started Jun 25 06:27:23 PM PDT 24
Finished Jun 25 06:28:35 PM PDT 24
Peak memory 219124 kb
Host smart-0d1961ea-11e3-4491-842b-5d3887461845
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128319527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.4128319527
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.3229452307
Short name T280
Test name
Test status
Simulation time 301981299 ps
CPU time 10.66 seconds
Started Jun 25 06:27:25 PM PDT 24
Finished Jun 25 06:27:37 PM PDT 24
Peak memory 218424 kb
Host smart-d03177ce-e3fc-4867-90f3-24eb61e6d658
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229452307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.3229452307
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2696556980
Short name T589
Test name
Test status
Simulation time 3287047508 ps
CPU time 5.51 seconds
Started Jun 25 06:27:23 PM PDT 24
Finished Jun 25 06:27:29 PM PDT 24
Peak memory 217968 kb
Host smart-a6703632-3b59-49a3-9f1a-06d56395cdea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696556980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2696556980
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.1638204987
Short name T458
Test name
Test status
Simulation time 4761234357 ps
CPU time 41.1 seconds
Started Jun 25 06:27:24 PM PDT 24
Finished Jun 25 06:28:07 PM PDT 24
Peak memory 251176 kb
Host smart-eceec44f-c36c-49a9-ac09-f25e8b4373eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638204987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.1638204987
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.4256313645
Short name T384
Test name
Test status
Simulation time 1715796963 ps
CPU time 13.4 seconds
Started Jun 25 06:27:22 PM PDT 24
Finished Jun 25 06:27:36 PM PDT 24
Peak memory 251108 kb
Host smart-ef1e945f-485c-40f7-823e-bac340c55f89
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256313645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.4256313645
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.1447233891
Short name T445
Test name
Test status
Simulation time 89625389 ps
CPU time 3.9 seconds
Started Jun 25 06:27:24 PM PDT 24
Finished Jun 25 06:27:30 PM PDT 24
Peak memory 218412 kb
Host smart-9a233426-5025-4bbe-bd8d-4e7b0b5fc720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447233891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1447233891
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.272088292
Short name T366
Test name
Test status
Simulation time 687762048 ps
CPU time 19.83 seconds
Started Jun 25 06:27:28 PM PDT 24
Finished Jun 25 06:27:49 PM PDT 24
Peak memory 218512 kb
Host smart-5c4521be-79a4-4c5e-a12f-b7580f0283c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272088292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_di
gest.272088292
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1334410553
Short name T424
Test name
Test status
Simulation time 371242200 ps
CPU time 8.85 seconds
Started Jun 25 06:27:30 PM PDT 24
Finished Jun 25 06:27:40 PM PDT 24
Peak memory 226236 kb
Host smart-b795129e-2940-4e94-bb52-8c49c40956fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334410553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
1334410553
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.3198369835
Short name T524
Test name
Test status
Simulation time 1878451657 ps
CPU time 10.4 seconds
Started Jun 25 06:27:24 PM PDT 24
Finished Jun 25 06:27:36 PM PDT 24
Peak memory 218512 kb
Host smart-e33f8939-8782-4668-abb4-1a6b08634d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198369835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.3198369835
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.3620149846
Short name T460
Test name
Test status
Simulation time 17377578 ps
CPU time 1.3 seconds
Started Jun 25 06:27:23 PM PDT 24
Finished Jun 25 06:27:25 PM PDT 24
Peak memory 214064 kb
Host smart-0bcc7e85-ab71-44f1-8b50-a04517f18839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620149846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3620149846
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1816850435
Short name T662
Test name
Test status
Simulation time 651293262 ps
CPU time 20.13 seconds
Started Jun 25 06:27:22 PM PDT 24
Finished Jun 25 06:27:43 PM PDT 24
Peak memory 244936 kb
Host smart-cfc42feb-2cd4-4ed2-819e-5ef92f34b806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816850435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1816850435
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.4263149622
Short name T270
Test name
Test status
Simulation time 65084653 ps
CPU time 6.68 seconds
Started Jun 25 06:27:23 PM PDT 24
Finished Jun 25 06:27:32 PM PDT 24
Peak memory 247200 kb
Host smart-49395e81-cd7f-4840-86a0-e70c5cebdd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263149622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.4263149622
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.3421471654
Short name T256
Test name
Test status
Simulation time 1971316636 ps
CPU time 52.36 seconds
Started Jun 25 06:27:31 PM PDT 24
Finished Jun 25 06:28:25 PM PDT 24
Peak memory 248040 kb
Host smart-84781456-0737-41e2-b42f-5dd017fe44ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421471654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.3421471654
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.4181512416
Short name T238
Test name
Test status
Simulation time 18623975 ps
CPU time 0.85 seconds
Started Jun 25 06:27:24 PM PDT 24
Finished Jun 25 06:27:26 PM PDT 24
Peak memory 212136 kb
Host smart-0ea6eb59-ac6d-45ae-9247-a882f0d0364f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181512416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.4181512416
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.1172214002
Short name T286
Test name
Test status
Simulation time 16063986 ps
CPU time 0.91 seconds
Started Jun 25 06:27:29 PM PDT 24
Finished Jun 25 06:27:31 PM PDT 24
Peak memory 208956 kb
Host smart-20b64c01-491a-4d3c-af87-c5ddf51598cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172214002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.1172214002
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.3760055053
Short name T276
Test name
Test status
Simulation time 265979422 ps
CPU time 12.12 seconds
Started Jun 25 06:27:31 PM PDT 24
Finished Jun 25 06:27:45 PM PDT 24
Peak memory 226248 kb
Host smart-d464a332-d044-4e35-827e-900f14556e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760055053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3760055053
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.3649315151
Short name T792
Test name
Test status
Simulation time 3383669892 ps
CPU time 14.22 seconds
Started Jun 25 06:27:30 PM PDT 24
Finished Jun 25 06:27:46 PM PDT 24
Peak memory 217892 kb
Host smart-d7995a0c-cfc1-4119-a029-23ed8c7fbcee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649315151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3649315151
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.4238164154
Short name T230
Test name
Test status
Simulation time 28027591128 ps
CPU time 87.89 seconds
Started Jun 25 06:27:30 PM PDT 24
Finished Jun 25 06:29:00 PM PDT 24
Peak memory 219060 kb
Host smart-98a1eeb4-88a9-4d0c-af79-9e921a369274
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238164154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.4238164154
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1809036745
Short name T370
Test name
Test status
Simulation time 3983771378 ps
CPU time 26.79 seconds
Started Jun 25 06:27:32 PM PDT 24
Finished Jun 25 06:28:00 PM PDT 24
Peak memory 219068 kb
Host smart-b958c99d-31ee-447a-af07-5d421b1d336b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809036745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1809036745
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3124575058
Short name T325
Test name
Test status
Simulation time 851006191 ps
CPU time 12.02 seconds
Started Jun 25 06:27:33 PM PDT 24
Finished Jun 25 06:27:47 PM PDT 24
Peak memory 217904 kb
Host smart-e3a45afe-fdba-41b9-b7d2-708c7a88c8a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124575058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.3124575058
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3632365438
Short name T404
Test name
Test status
Simulation time 3673816578 ps
CPU time 44.9 seconds
Started Jun 25 06:27:32 PM PDT 24
Finished Jun 25 06:28:19 PM PDT 24
Peak memory 276108 kb
Host smart-4661f9fc-442c-4c01-ad7e-8d250e54a494
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632365438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3632365438
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3108039852
Short name T843
Test name
Test status
Simulation time 1218052624 ps
CPU time 25.98 seconds
Started Jun 25 06:27:31 PM PDT 24
Finished Jun 25 06:27:59 PM PDT 24
Peak memory 250972 kb
Host smart-745f1dd9-759f-4c55-8a20-df292c4c3409
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108039852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3108039852
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.2653053048
Short name T748
Test name
Test status
Simulation time 142968407 ps
CPU time 3.97 seconds
Started Jun 25 06:27:29 PM PDT 24
Finished Jun 25 06:27:34 PM PDT 24
Peak memory 222932 kb
Host smart-6bbce54c-60bf-489e-af5e-2e71f50d8538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653053048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2653053048
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2727363663
Short name T308
Test name
Test status
Simulation time 353864073 ps
CPU time 9.15 seconds
Started Jun 25 06:27:31 PM PDT 24
Finished Jun 25 06:27:41 PM PDT 24
Peak memory 226232 kb
Host smart-768306af-f2c4-4f21-91ff-f4da38a3531e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727363663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2727363663
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2173963811
Short name T330
Test name
Test status
Simulation time 302289788 ps
CPU time 12.84 seconds
Started Jun 25 06:27:31 PM PDT 24
Finished Jun 25 06:27:46 PM PDT 24
Peak memory 218532 kb
Host smart-f37e7f54-92dc-48b6-a6c7-ba0c67a4a887
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173963811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.2173963811
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.2970631416
Short name T93
Test name
Test status
Simulation time 3245528422 ps
CPU time 10.19 seconds
Started Jun 25 06:27:32 PM PDT 24
Finished Jun 25 06:27:45 PM PDT 24
Peak memory 219144 kb
Host smart-55d8a165-6371-49cb-ba9a-daaf4868fa85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970631416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
2970631416
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.137133009
Short name T604
Test name
Test status
Simulation time 1382041684 ps
CPU time 10.14 seconds
Started Jun 25 06:27:33 PM PDT 24
Finished Jun 25 06:27:45 PM PDT 24
Peak memory 218496 kb
Host smart-a212f90b-7ae7-40ba-ac1b-42c459d8ca35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137133009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.137133009
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.79591400
Short name T294
Test name
Test status
Simulation time 15955699 ps
CPU time 1.08 seconds
Started Jun 25 06:27:31 PM PDT 24
Finished Jun 25 06:27:33 PM PDT 24
Peak memory 218032 kb
Host smart-fb459dee-b911-476f-bb79-6f23b89701fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79591400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.79591400
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2946575619
Short name T381
Test name
Test status
Simulation time 351777568 ps
CPU time 30.92 seconds
Started Jun 25 06:27:34 PM PDT 24
Finished Jun 25 06:28:07 PM PDT 24
Peak memory 251096 kb
Host smart-acb579b2-0739-487e-8ca6-6a48b706105f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946575619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2946575619
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.623956885
Short name T584
Test name
Test status
Simulation time 258406431 ps
CPU time 5.95 seconds
Started Jun 25 06:27:30 PM PDT 24
Finished Jun 25 06:27:38 PM PDT 24
Peak memory 244688 kb
Host smart-a08cbaea-4763-49ae-9c1e-e8708c8c3417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623956885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.623956885
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.1335500936
Short name T641
Test name
Test status
Simulation time 25895991738 ps
CPU time 192.44 seconds
Started Jun 25 06:27:31 PM PDT 24
Finished Jun 25 06:30:46 PM PDT 24
Peak memory 276212 kb
Host smart-e830570c-0493-409e-aa66-5f5017d7d9bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335500936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.1335500936
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.934749185
Short name T536
Test name
Test status
Simulation time 80478588588 ps
CPU time 722.73 seconds
Started Jun 25 06:27:30 PM PDT 24
Finished Jun 25 06:39:34 PM PDT 24
Peak memory 300344 kb
Host smart-08e5788d-b082-498b-b8ca-0b33399a3d20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=934749185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.934749185
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1216858281
Short name T260
Test name
Test status
Simulation time 17005426 ps
CPU time 0.92 seconds
Started Jun 25 06:27:31 PM PDT 24
Finished Jun 25 06:27:34 PM PDT 24
Peak memory 217924 kb
Host smart-b4cf9752-3416-466e-a37c-d2917401e4e8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216858281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.1216858281
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3459184682
Short name T265
Test name
Test status
Simulation time 13149334 ps
CPU time 0.84 seconds
Started Jun 25 06:27:39 PM PDT 24
Finished Jun 25 06:27:42 PM PDT 24
Peak memory 209004 kb
Host smart-1982fa49-3187-46c7-8d59-e0a170f4a6b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459184682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3459184682
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.607324608
Short name T620
Test name
Test status
Simulation time 401258502 ps
CPU time 15.93 seconds
Started Jun 25 06:27:37 PM PDT 24
Finished Jun 25 06:27:54 PM PDT 24
Peak memory 218420 kb
Host smart-0e967154-3aad-45e1-88d5-e797f99367b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607324608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.607324608
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.2457315580
Short name T675
Test name
Test status
Simulation time 1271894557 ps
CPU time 8.93 seconds
Started Jun 25 06:27:41 PM PDT 24
Finished Jun 25 06:27:52 PM PDT 24
Peak memory 217688 kb
Host smart-0110e186-01a7-4716-abc8-946490e7e7cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457315580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.2457315580
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.3563485132
Short name T503
Test name
Test status
Simulation time 18219574493 ps
CPU time 116.8 seconds
Started Jun 25 06:27:38 PM PDT 24
Finished Jun 25 06:29:37 PM PDT 24
Peak memory 220448 kb
Host smart-271ce297-9aaf-4404-8881-ddc8683b44af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563485132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.3563485132
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.3913202340
Short name T359
Test name
Test status
Simulation time 2321939906 ps
CPU time 8.42 seconds
Started Jun 25 06:27:37 PM PDT 24
Finished Jun 25 06:27:47 PM PDT 24
Peak memory 218396 kb
Host smart-bb7f1f47-2638-4a06-ae69-7f35e5e37b57
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913202340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.3913202340
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2702996384
Short name T257
Test name
Test status
Simulation time 2187015042 ps
CPU time 7.56 seconds
Started Jun 25 06:27:40 PM PDT 24
Finished Jun 25 06:27:49 PM PDT 24
Peak memory 217960 kb
Host smart-b745a606-21a2-490d-9052-9270a334a43f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702996384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2702996384
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.4171692027
Short name T102
Test name
Test status
Simulation time 5237157571 ps
CPU time 52.16 seconds
Started Jun 25 06:27:39 PM PDT 24
Finished Jun 25 06:28:33 PM PDT 24
Peak memory 283900 kb
Host smart-ba17b5b6-9767-4d14-ad49-c1333bbf96b1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171692027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.4171692027
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.905691428
Short name T348
Test name
Test status
Simulation time 807962987 ps
CPU time 12.84 seconds
Started Jun 25 06:27:40 PM PDT 24
Finished Jun 25 06:27:55 PM PDT 24
Peak memory 251100 kb
Host smart-c0ea38ff-a297-47f3-87e8-2fe9e60c66a8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905691428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_
jtag_state_post_trans.905691428
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.3826070638
Short name T694
Test name
Test status
Simulation time 391992182 ps
CPU time 3.17 seconds
Started Jun 25 06:27:41 PM PDT 24
Finished Jun 25 06:27:45 PM PDT 24
Peak memory 218440 kb
Host smart-85b53266-0b7c-4194-a3a2-53ea803c2d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826070638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3826070638
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.2331029564
Short name T670
Test name
Test status
Simulation time 306247329 ps
CPU time 12.02 seconds
Started Jun 25 06:27:41 PM PDT 24
Finished Jun 25 06:27:55 PM PDT 24
Peak memory 226348 kb
Host smart-f91b4998-4010-411a-9092-d8e4273e0e33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331029564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.2331029564
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.961089992
Short name T333
Test name
Test status
Simulation time 411073929 ps
CPU time 11.54 seconds
Started Jun 25 06:27:38 PM PDT 24
Finished Jun 25 06:27:51 PM PDT 24
Peak memory 218456 kb
Host smart-bdbc7d8d-618c-459b-bfa9-8f5e6076481b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961089992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di
gest.961089992
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.3085097315
Short name T645
Test name
Test status
Simulation time 1423448295 ps
CPU time 14 seconds
Started Jun 25 06:27:37 PM PDT 24
Finished Jun 25 06:27:53 PM PDT 24
Peak memory 218408 kb
Host smart-909eb864-461c-4637-be0f-e0c28d69a114
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085097315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
3085097315
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.889145927
Short name T261
Test name
Test status
Simulation time 295267529 ps
CPU time 7.41 seconds
Started Jun 25 06:27:38 PM PDT 24
Finished Jun 25 06:27:47 PM PDT 24
Peak memory 218488 kb
Host smart-7a742c94-fa7e-417e-a08c-4894f6dca4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889145927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.889145927
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.701255862
Short name T582
Test name
Test status
Simulation time 41263190 ps
CPU time 2.56 seconds
Started Jun 25 06:27:34 PM PDT 24
Finished Jun 25 06:27:38 PM PDT 24
Peak memory 223068 kb
Host smart-7b1b7989-0fe0-44fc-a7ca-5fbe3502d4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701255862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.701255862
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.3191395593
Short name T86
Test name
Test status
Simulation time 296445194 ps
CPU time 14.89 seconds
Started Jun 25 06:27:32 PM PDT 24
Finished Jun 25 06:27:49 PM PDT 24
Peak memory 250836 kb
Host smart-e3238657-a72f-45e1-ac9d-4e4d3612e782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191395593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.3191395593
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.2463716122
Short name T253
Test name
Test status
Simulation time 125762207 ps
CPU time 6.93 seconds
Started Jun 25 06:27:40 PM PDT 24
Finished Jun 25 06:27:48 PM PDT 24
Peak memory 246928 kb
Host smart-d6346144-9a56-43e3-9dfb-9aaccfca1f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463716122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2463716122
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.1220630310
Short name T619
Test name
Test status
Simulation time 16505546436 ps
CPU time 127.82 seconds
Started Jun 25 06:27:38 PM PDT 24
Finished Jun 25 06:29:48 PM PDT 24
Peak memory 283896 kb
Host smart-3506db77-dc0e-4880-81f8-4422147d5744
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220630310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.1220630310
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.4248199778
Short name T831
Test name
Test status
Simulation time 46581307 ps
CPU time 0.9 seconds
Started Jun 25 06:27:31 PM PDT 24
Finished Jun 25 06:27:34 PM PDT 24
Peak memory 213212 kb
Host smart-ae17d2a2-d1b9-4413-b252-084a53bc3e0c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248199778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.4248199778
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.4156347982
Short name T719
Test name
Test status
Simulation time 32924052 ps
CPU time 1.18 seconds
Started Jun 25 06:27:44 PM PDT 24
Finished Jun 25 06:27:46 PM PDT 24
Peak memory 209284 kb
Host smart-07e02ddf-7f1e-4a16-8981-613b9e026d3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156347982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.4156347982
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.3629350785
Short name T319
Test name
Test status
Simulation time 1121783546 ps
CPU time 10.33 seconds
Started Jun 25 06:27:37 PM PDT 24
Finished Jun 25 06:27:49 PM PDT 24
Peak memory 218432 kb
Host smart-f2223f76-6b53-453a-b168-14928a588628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629350785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3629350785
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.3392750931
Short name T634
Test name
Test status
Simulation time 1324764976 ps
CPU time 45.77 seconds
Started Jun 25 06:27:41 PM PDT 24
Finished Jun 25 06:28:28 PM PDT 24
Peak memory 218420 kb
Host smart-7c0091d6-d873-41ea-a38c-e3768e38c5a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392750931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.3392750931
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1670610383
Short name T342
Test name
Test status
Simulation time 383017084 ps
CPU time 7.27 seconds
Started Jun 25 06:27:38 PM PDT 24
Finished Jun 25 06:27:47 PM PDT 24
Peak memory 218396 kb
Host smart-314bdded-7cb1-4427-afe7-405c1f1db8f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670610383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.1670610383
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1733666598
Short name T565
Test name
Test status
Simulation time 314678525 ps
CPU time 1.98 seconds
Started Jun 25 06:27:39 PM PDT 24
Finished Jun 25 06:27:42 PM PDT 24
Peak memory 217896 kb
Host smart-18cc553a-1f48-41cd-ba94-908550d84bdc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733666598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1733666598
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.1379835909
Short name T274
Test name
Test status
Simulation time 2403136174 ps
CPU time 79.64 seconds
Started Jun 25 06:27:39 PM PDT 24
Finished Jun 25 06:29:00 PM PDT 24
Peak memory 276920 kb
Host smart-c3ec9caf-a432-4fef-87e3-53a2ca7860e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379835909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.1379835909
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.4235055818
Short name T320
Test name
Test status
Simulation time 3983338731 ps
CPU time 20.77 seconds
Started Jun 25 06:27:40 PM PDT 24
Finished Jun 25 06:28:03 PM PDT 24
Peak memory 251200 kb
Host smart-654b7308-4d8a-46f5-ab32-8a5749028875
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235055818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.4235055818
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.557978224
Short name T691
Test name
Test status
Simulation time 77214417 ps
CPU time 1.9 seconds
Started Jun 25 06:27:39 PM PDT 24
Finished Jun 25 06:27:43 PM PDT 24
Peak memory 222324 kb
Host smart-d76b9e1e-f088-4dc1-bdfd-39276561ed37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557978224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.557978224
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.2970913313
Short name T369
Test name
Test status
Simulation time 1124090912 ps
CPU time 8.99 seconds
Started Jun 25 06:27:44 PM PDT 24
Finished Jun 25 06:27:56 PM PDT 24
Peak memory 218332 kb
Host smart-65c7c55e-e191-493c-93e2-b22d356441d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970913313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2970913313
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1071626199
Short name T573
Test name
Test status
Simulation time 567401423 ps
CPU time 11.4 seconds
Started Jun 25 06:27:49 PM PDT 24
Finished Jun 25 06:28:03 PM PDT 24
Peak memory 218460 kb
Host smart-d317c55b-0949-4a55-94e1-336ab5af6237
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071626199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.1071626199
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1586457379
Short name T61
Test name
Test status
Simulation time 1729869629 ps
CPU time 6.09 seconds
Started Jun 25 06:27:49 PM PDT 24
Finished Jun 25 06:27:56 PM PDT 24
Peak memory 225060 kb
Host smart-9f1ae3a2-deac-4427-b2a4-bb4a1c7916c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586457379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
1586457379
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.3069587272
Short name T247
Test name
Test status
Simulation time 244399532 ps
CPU time 6.13 seconds
Started Jun 25 06:27:40 PM PDT 24
Finished Jun 25 06:27:47 PM PDT 24
Peak memory 218488 kb
Host smart-41ae21ce-c69d-4988-8415-03fa54044ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069587272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.3069587272
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3942065508
Short name T487
Test name
Test status
Simulation time 157252095 ps
CPU time 2.65 seconds
Started Jun 25 06:27:41 PM PDT 24
Finished Jun 25 06:27:45 PM PDT 24
Peak memory 214776 kb
Host smart-ea977223-940c-442e-8f88-08c686215e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942065508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3942065508
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.3243237376
Short name T408
Test name
Test status
Simulation time 3427063969 ps
CPU time 27.74 seconds
Started Jun 25 06:27:41 PM PDT 24
Finished Jun 25 06:28:10 PM PDT 24
Peak memory 251164 kb
Host smart-b86cd78b-3dc9-4f1d-81ca-27777ac093ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243237376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3243237376
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.3854210555
Short name T636
Test name
Test status
Simulation time 75850689 ps
CPU time 6.9 seconds
Started Jun 25 06:27:38 PM PDT 24
Finished Jun 25 06:27:47 PM PDT 24
Peak memory 247108 kb
Host smart-d3e04402-f10f-4d29-8d31-3f2a6ae87de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854210555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3854210555
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.1882274070
Short name T856
Test name
Test status
Simulation time 7373101225 ps
CPU time 149.54 seconds
Started Jun 25 06:27:43 PM PDT 24
Finished Jun 25 06:30:14 PM PDT 24
Peak memory 277016 kb
Host smart-06af9f5a-67de-4bb0-be2d-31433db324d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882274070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.1882274070
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2486388833
Short name T736
Test name
Test status
Simulation time 17905609 ps
CPU time 0.99 seconds
Started Jun 25 06:27:38 PM PDT 24
Finished Jun 25 06:27:41 PM PDT 24
Peak memory 212104 kb
Host smart-fd26cc8b-3854-4b38-a864-c54ed75349c0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486388833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.2486388833
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3307480480
Short name T578
Test name
Test status
Simulation time 51029097 ps
CPU time 1.02 seconds
Started Jun 25 06:27:45 PM PDT 24
Finished Jun 25 06:27:48 PM PDT 24
Peak memory 209256 kb
Host smart-02169f8e-ee59-49bc-ad62-89ab66464529
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307480480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3307480480
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.3247290761
Short name T701
Test name
Test status
Simulation time 168232471 ps
CPU time 5.3 seconds
Started Jun 25 06:27:46 PM PDT 24
Finished Jun 25 06:27:53 PM PDT 24
Peak memory 217448 kb
Host smart-42415c7b-7abe-4aad-b8f0-0e1d67eeff4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247290761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.3247290761
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.553835841
Short name T773
Test name
Test status
Simulation time 778699861 ps
CPU time 6.84 seconds
Started Jun 25 06:27:48 PM PDT 24
Finished Jun 25 06:27:56 PM PDT 24
Peak memory 218444 kb
Host smart-1e52d1e0-a74b-42e1-aa11-e8b04f0e2458
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553835841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.553835841
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1353895025
Short name T474
Test name
Test status
Simulation time 812823040 ps
CPU time 1.77 seconds
Started Jun 25 06:27:46 PM PDT 24
Finished Jun 25 06:27:50 PM PDT 24
Peak memory 218024 kb
Host smart-032da13c-a583-49d3-9551-ff3671d00e96
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353895025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1353895025
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1599683590
Short name T734
Test name
Test status
Simulation time 6372245813 ps
CPU time 37.94 seconds
Started Jun 25 06:27:50 PM PDT 24
Finished Jun 25 06:28:30 PM PDT 24
Peak memory 283952 kb
Host smart-55869d15-6438-498c-bb40-9952f4996491
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599683590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.1599683590
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1323713188
Short name T766
Test name
Test status
Simulation time 615747257 ps
CPU time 23.98 seconds
Started Jun 25 06:27:50 PM PDT 24
Finished Jun 25 06:28:17 PM PDT 24
Peak memory 251124 kb
Host smart-4fac0cd1-43ed-43fc-aef3-ba24b5d922d7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323713188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.1323713188
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2193694817
Short name T221
Test name
Test status
Simulation time 70865563 ps
CPU time 2.16 seconds
Started Jun 25 06:27:46 PM PDT 24
Finished Jun 25 06:27:50 PM PDT 24
Peak memory 222428 kb
Host smart-8770fcb9-f7b9-4c3c-994c-b23390392327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193694817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2193694817
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.1112861007
Short name T553
Test name
Test status
Simulation time 275047332 ps
CPU time 14.61 seconds
Started Jun 25 06:27:44 PM PDT 24
Finished Jun 25 06:28:01 PM PDT 24
Peak memory 226228 kb
Host smart-0948d6cd-9608-45fc-a820-51ec29788c79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112861007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1112861007
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.3721111672
Short name T371
Test name
Test status
Simulation time 1695913663 ps
CPU time 12.36 seconds
Started Jun 25 06:27:44 PM PDT 24
Finished Jun 25 06:27:58 PM PDT 24
Peak memory 218436 kb
Host smart-2fc85616-de90-4f6b-931c-e296faa86648
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721111672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.3721111672
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1285285953
Short name T864
Test name
Test status
Simulation time 337731937 ps
CPU time 11.5 seconds
Started Jun 25 06:27:46 PM PDT 24
Finished Jun 25 06:27:59 PM PDT 24
Peak memory 218424 kb
Host smart-0c329af4-03ff-469c-8d7f-f4bea41e8db9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285285953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1285285953
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.4033176468
Short name T793
Test name
Test status
Simulation time 244555856 ps
CPU time 8.32 seconds
Started Jun 25 06:27:48 PM PDT 24
Finished Jun 25 06:27:58 PM PDT 24
Peak memory 218500 kb
Host smart-cd8d8166-fa35-4fd2-937f-db6252943c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033176468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.4033176468
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.869004333
Short name T545
Test name
Test status
Simulation time 36771495 ps
CPU time 1.98 seconds
Started Jun 25 06:27:44 PM PDT 24
Finished Jun 25 06:27:48 PM PDT 24
Peak memory 223448 kb
Host smart-1b9b0f43-b24b-4a47-b50e-64dc2ceffa11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869004333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.869004333
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.3489245308
Short name T322
Test name
Test status
Simulation time 1005792871 ps
CPU time 31.09 seconds
Started Jun 25 06:27:45 PM PDT 24
Finished Jun 25 06:28:18 PM PDT 24
Peak memory 251060 kb
Host smart-994b17f2-7fd3-42d9-afee-ee3382c2085f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489245308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3489245308
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.2709079276
Short name T271
Test name
Test status
Simulation time 249872203 ps
CPU time 7.1 seconds
Started Jun 25 06:27:43 PM PDT 24
Finished Jun 25 06:27:52 PM PDT 24
Peak memory 251108 kb
Host smart-68521ea0-d911-4835-a406-29a02a31360b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709079276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.2709079276
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3417464641
Short name T523
Test name
Test status
Simulation time 6333701010 ps
CPU time 118.79 seconds
Started Jun 25 06:27:44 PM PDT 24
Finished Jun 25 06:29:45 PM PDT 24
Peak memory 283936 kb
Host smart-4854561d-0ffe-4814-8c72-45cb8757e96c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417464641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3417464641
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3333248102
Short name T711
Test name
Test status
Simulation time 30966735 ps
CPU time 1 seconds
Started Jun 25 06:27:46 PM PDT 24
Finished Jun 25 06:27:49 PM PDT 24
Peak memory 212084 kb
Host smart-3cc5e175-04c6-4723-ae4e-cbbeff8abf48
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333248102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.3333248102
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2935874440
Short name T74
Test name
Test status
Simulation time 66065212 ps
CPU time 1.07 seconds
Started Jun 25 06:27:52 PM PDT 24
Finished Jun 25 06:27:55 PM PDT 24
Peak memory 209180 kb
Host smart-26d9a5c7-d0ab-4b13-87a0-23fa81df7a2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935874440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2935874440
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.412579837
Short name T656
Test name
Test status
Simulation time 1187319757 ps
CPU time 9.59 seconds
Started Jun 25 06:27:44 PM PDT 24
Finished Jun 25 06:27:56 PM PDT 24
Peak memory 218444 kb
Host smart-63e08347-5d46-44ee-bc3c-e15075daa732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412579837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.412579837
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1591577888
Short name T42
Test name
Test status
Simulation time 3525780020 ps
CPU time 6.88 seconds
Started Jun 25 06:27:55 PM PDT 24
Finished Jun 25 06:28:03 PM PDT 24
Peak memory 217968 kb
Host smart-a4a5e994-1993-475e-acf3-fa29fce12565
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591577888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.1591577888
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.2022681967
Short name T611
Test name
Test status
Simulation time 7590512974 ps
CPU time 92.85 seconds
Started Jun 25 06:27:46 PM PDT 24
Finished Jun 25 06:29:21 PM PDT 24
Peak memory 220168 kb
Host smart-f7a45825-eadf-4d52-b14c-a872c413e81f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022681967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.2022681967
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1626810779
Short name T242
Test name
Test status
Simulation time 1871347783 ps
CPU time 7.06 seconds
Started Jun 25 06:27:45 PM PDT 24
Finished Jun 25 06:27:54 PM PDT 24
Peak memory 223388 kb
Host smart-473b9353-82e3-4bd2-926a-31d7f6c86a28
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626810779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1626810779
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.1225121881
Short name T84
Test name
Test status
Simulation time 382705263 ps
CPU time 6.13 seconds
Started Jun 25 06:27:44 PM PDT 24
Finished Jun 25 06:27:52 PM PDT 24
Peak memory 218012 kb
Host smart-289778e5-f416-48aa-bc5d-032544042b8b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225121881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.1225121881
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2641804584
Short name T493
Test name
Test status
Simulation time 11368825300 ps
CPU time 83.3 seconds
Started Jun 25 06:27:50 PM PDT 24
Finished Jun 25 06:29:16 PM PDT 24
Peak memory 268020 kb
Host smart-0cf10a89-8b62-44f3-9d47-42651de5fdaf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641804584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2641804584
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3327791818
Short name T850
Test name
Test status
Simulation time 2240193860 ps
CPU time 13.64 seconds
Started Jun 25 06:27:43 PM PDT 24
Finished Jun 25 06:27:58 PM PDT 24
Peak memory 250672 kb
Host smart-d0c67c11-e69b-4689-9295-3ace4ec28760
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327791818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3327791818
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.3428028855
Short name T687
Test name
Test status
Simulation time 96852913 ps
CPU time 1.99 seconds
Started Jun 25 06:27:44 PM PDT 24
Finished Jun 25 06:27:47 PM PDT 24
Peak memory 218432 kb
Host smart-ebaaf6e0-5b0f-4bba-9442-3a81fd1da12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428028855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.3428028855
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1969863790
Short name T198
Test name
Test status
Simulation time 1699794579 ps
CPU time 14.3 seconds
Started Jun 25 06:27:51 PM PDT 24
Finished Jun 25 06:28:07 PM PDT 24
Peak memory 220144 kb
Host smart-c1c98d94-784b-4805-87d7-109bb22f9831
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969863790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1969863790
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.3608647680
Short name T605
Test name
Test status
Simulation time 1194304908 ps
CPU time 13.42 seconds
Started Jun 25 06:27:52 PM PDT 24
Finished Jun 25 06:28:07 PM PDT 24
Peak memory 218420 kb
Host smart-e13a1d40-72f6-4722-9175-1c5fe9825e8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608647680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.3608647680
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3517908416
Short name T329
Test name
Test status
Simulation time 405236792 ps
CPU time 9.86 seconds
Started Jun 25 06:27:54 PM PDT 24
Finished Jun 25 06:28:06 PM PDT 24
Peak memory 218416 kb
Host smart-108a1b1e-2f3a-40f4-9a7b-403c8867a7c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517908416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
3517908416
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.2316598150
Short name T464
Test name
Test status
Simulation time 559819967 ps
CPU time 9.85 seconds
Started Jun 25 06:27:48 PM PDT 24
Finished Jun 25 06:28:00 PM PDT 24
Peak memory 218572 kb
Host smart-cb88bf79-5340-46c3-bf25-a0b6cc5612c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316598150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2316598150
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.1991622072
Short name T444
Test name
Test status
Simulation time 28271371 ps
CPU time 2.35 seconds
Started Jun 25 06:27:50 PM PDT 24
Finished Jun 25 06:27:54 PM PDT 24
Peak memory 214628 kb
Host smart-e53877dd-a4a2-47e2-8803-c0deca894ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991622072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.1991622072
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.4109549430
Short name T721
Test name
Test status
Simulation time 747323082 ps
CPU time 26.21 seconds
Started Jun 25 06:27:46 PM PDT 24
Finished Jun 25 06:28:15 PM PDT 24
Peak memory 251112 kb
Host smart-1f0f8d2f-924e-405e-bca7-3ead8391cae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109549430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.4109549430
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.778958148
Short name T535
Test name
Test status
Simulation time 1526362322 ps
CPU time 10.6 seconds
Started Jun 25 06:27:46 PM PDT 24
Finished Jun 25 06:27:59 PM PDT 24
Peak memory 251112 kb
Host smart-de31d506-f567-48f8-813c-01ef69a9f78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778958148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.778958148
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.525146065
Short name T50
Test name
Test status
Simulation time 255033267425 ps
CPU time 549.12 seconds
Started Jun 25 06:27:52 PM PDT 24
Finished Jun 25 06:37:03 PM PDT 24
Peak memory 497040 kb
Host smart-cd9171e2-06d8-4cbb-879b-be63386a9262
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=525146065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.525146065
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3144341
Short name T433
Test name
Test status
Simulation time 11791982 ps
CPU time 0.88 seconds
Started Jun 25 06:27:46 PM PDT 24
Finished Jun 25 06:27:49 PM PDT 24
Peak memory 211920 kb
Host smart-20c94527-8400-4534-a5ee-0e11c255ef80
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vola
tile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_volatile_unlock_smoke.3144341
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.2822033525
Short name T303
Test name
Test status
Simulation time 28344017 ps
CPU time 1.21 seconds
Started Jun 25 06:27:59 PM PDT 24
Finished Jun 25 06:28:02 PM PDT 24
Peak memory 209176 kb
Host smart-982ef904-1617-4b1e-acfb-f7c8919a9156
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822033525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2822033525
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.572846613
Short name T394
Test name
Test status
Simulation time 310324532 ps
CPU time 10.01 seconds
Started Jun 25 06:27:55 PM PDT 24
Finished Jun 25 06:28:06 PM PDT 24
Peak memory 226264 kb
Host smart-982ed241-73a6-4aa4-8393-bc5db6d5f15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572846613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.572846613
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.130817564
Short name T167
Test name
Test status
Simulation time 280840182 ps
CPU time 4.38 seconds
Started Jun 25 06:27:52 PM PDT 24
Finished Jun 25 06:27:58 PM PDT 24
Peak memory 217740 kb
Host smart-3c468000-0889-489b-b1ef-8c30377f69a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130817564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.130817564
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.2178448838
Short name T811
Test name
Test status
Simulation time 10833217287 ps
CPU time 41.34 seconds
Started Jun 25 06:27:55 PM PDT 24
Finished Jun 25 06:28:38 PM PDT 24
Peak memory 219168 kb
Host smart-bfdc89d1-3a57-4292-9678-41d62bbe5d3f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178448838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.2178448838
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3630552903
Short name T760
Test name
Test status
Simulation time 564131741 ps
CPU time 8.98 seconds
Started Jun 25 06:27:54 PM PDT 24
Finished Jun 25 06:28:04 PM PDT 24
Peak memory 218416 kb
Host smart-766fab16-8c33-42c8-b723-11f9d842ac16
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630552903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.3630552903
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.3394735863
Short name T66
Test name
Test status
Simulation time 2504673827 ps
CPU time 4.4 seconds
Started Jun 25 06:27:54 PM PDT 24
Finished Jun 25 06:28:00 PM PDT 24
Peak memory 217992 kb
Host smart-8b315838-811f-4e7b-bf1c-0975ca1adbb6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394735863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.3394735863
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1304460257
Short name T388
Test name
Test status
Simulation time 4849011926 ps
CPU time 42.84 seconds
Started Jun 25 06:27:55 PM PDT 24
Finished Jun 25 06:28:39 PM PDT 24
Peak memory 258856 kb
Host smart-e3eb8360-c552-4fc4-9234-db6b829d345f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304460257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.1304460257
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1859582808
Short name T655
Test name
Test status
Simulation time 2358867356 ps
CPU time 23.68 seconds
Started Jun 25 06:27:53 PM PDT 24
Finished Jun 25 06:28:18 PM PDT 24
Peak memory 251164 kb
Host smart-e1644e57-1370-4243-8044-39134c6c536a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859582808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.1859582808
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2202414331
Short name T339
Test name
Test status
Simulation time 242820690 ps
CPU time 3.41 seconds
Started Jun 25 06:28:00 PM PDT 24
Finished Jun 25 06:28:05 PM PDT 24
Peak memory 218316 kb
Host smart-882bf086-4a7a-4d82-8429-1849ddb78372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202414331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2202414331
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.926501527
Short name T486
Test name
Test status
Simulation time 3508072734 ps
CPU time 11.62 seconds
Started Jun 25 06:28:01 PM PDT 24
Finished Jun 25 06:28:14 PM PDT 24
Peak memory 226260 kb
Host smart-6127f29f-1f17-41e0-8248-e185f94e27c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926501527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.926501527
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3437491482
Short name T380
Test name
Test status
Simulation time 1296158415 ps
CPU time 9.53 seconds
Started Jun 25 06:27:59 PM PDT 24
Finished Jun 25 06:28:11 PM PDT 24
Peak memory 218448 kb
Host smart-beeac049-52dc-4fea-875b-9898f2b0c623
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437491482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.3437491482
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2991401856
Short name T327
Test name
Test status
Simulation time 345638477 ps
CPU time 11.55 seconds
Started Jun 25 06:28:03 PM PDT 24
Finished Jun 25 06:28:16 PM PDT 24
Peak memory 218420 kb
Host smart-ce080e49-8cb6-4cde-97c2-8c6fc26d8100
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991401856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2991401856
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.1818934606
Short name T642
Test name
Test status
Simulation time 280697867 ps
CPU time 8.42 seconds
Started Jun 25 06:27:51 PM PDT 24
Finished Jun 25 06:28:02 PM PDT 24
Peak memory 218720 kb
Host smart-79837636-bcec-4142-8c22-dbeee79b7c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818934606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.1818934606
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2852908166
Short name T62
Test name
Test status
Simulation time 454154817 ps
CPU time 5.1 seconds
Started Jun 25 06:27:53 PM PDT 24
Finished Jun 25 06:27:59 PM PDT 24
Peak memory 217908 kb
Host smart-8e7cae5e-3b6b-46be-a481-84460bc58ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852908166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2852908166
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.1669215109
Short name T767
Test name
Test status
Simulation time 309605848 ps
CPU time 34.94 seconds
Started Jun 25 06:27:52 PM PDT 24
Finished Jun 25 06:28:28 PM PDT 24
Peak memory 251116 kb
Host smart-ea402889-6bee-410a-a128-c7c254b3da29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669215109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1669215109
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.1168475936
Short name T94
Test name
Test status
Simulation time 116101009 ps
CPU time 7.12 seconds
Started Jun 25 06:27:52 PM PDT 24
Finished Jun 25 06:28:01 PM PDT 24
Peak memory 247596 kb
Host smart-d07b4721-5726-4da1-a43f-454153cd25bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168475936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.1168475936
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.585499129
Short name T159
Test name
Test status
Simulation time 10028662821 ps
CPU time 152.33 seconds
Started Jun 25 06:27:59 PM PDT 24
Finished Jun 25 06:30:34 PM PDT 24
Peak memory 283916 kb
Host smart-856aee45-3f82-4972-9c7b-5ad137cb88f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585499129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.585499129
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.2062134678
Short name T145
Test name
Test status
Simulation time 18583718031 ps
CPU time 463.22 seconds
Started Jun 25 06:28:04 PM PDT 24
Finished Jun 25 06:35:48 PM PDT 24
Peak memory 496936 kb
Host smart-962baed5-3aad-44b0-8c19-dd9d9d555d91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2062134678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.2062134678
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.402051281
Short name T218
Test name
Test status
Simulation time 22271183 ps
CPU time 0.89 seconds
Started Jun 25 06:27:50 PM PDT 24
Finished Jun 25 06:27:54 PM PDT 24
Peak memory 213080 kb
Host smart-1d9b3dea-8b1f-488f-bc3b-d012370589b4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402051281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.402051281
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3199484076
Short name T272
Test name
Test status
Simulation time 48772682 ps
CPU time 0.95 seconds
Started Jun 25 06:28:00 PM PDT 24
Finished Jun 25 06:28:03 PM PDT 24
Peak memory 209164 kb
Host smart-e313453b-9df0-44ac-9c4e-275a254034ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199484076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3199484076
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.916854313
Short name T628
Test name
Test status
Simulation time 8282186841 ps
CPU time 18.77 seconds
Started Jun 25 06:27:58 PM PDT 24
Finished Jun 25 06:28:18 PM PDT 24
Peak memory 218432 kb
Host smart-f2f6b594-4c1b-4777-8eef-2599a994341a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916854313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.916854313
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.4023197877
Short name T466
Test name
Test status
Simulation time 714150566 ps
CPU time 4.03 seconds
Started Jun 25 06:27:58 PM PDT 24
Finished Jun 25 06:28:04 PM PDT 24
Peak memory 217356 kb
Host smart-c56d333d-a0cd-4932-a7b8-265c749575b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023197877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.4023197877
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1694186950
Short name T450
Test name
Test status
Simulation time 10215911156 ps
CPU time 36.51 seconds
Started Jun 25 06:27:58 PM PDT 24
Finished Jun 25 06:28:36 PM PDT 24
Peak memory 226224 kb
Host smart-10931f83-33cc-48be-bf2d-648c8a16f336
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694186950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1694186950
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.1587957861
Short name T821
Test name
Test status
Simulation time 1089161909 ps
CPU time 3.78 seconds
Started Jun 25 06:27:57 PM PDT 24
Finished Jun 25 06:28:02 PM PDT 24
Peak memory 218400 kb
Host smart-c990b4fe-6ddc-43bf-829c-0dec4343f68f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587957861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.1587957861
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.27664537
Short name T563
Test name
Test status
Simulation time 946642171 ps
CPU time 12.76 seconds
Started Jun 25 06:27:58 PM PDT 24
Finished Jun 25 06:28:12 PM PDT 24
Peak memory 217900 kb
Host smart-5c2485a3-03f5-4539-97b0-2f89eaa2ed4c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27664537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.27664537
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.547106875
Short name T552
Test name
Test status
Simulation time 2694100964 ps
CPU time 51.85 seconds
Started Jun 25 06:27:58 PM PDT 24
Finished Jun 25 06:28:52 PM PDT 24
Peak memory 267496 kb
Host smart-55df3d13-ae44-477e-9584-db533a75db1e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547106875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_state_failure.547106875
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3196825720
Short name T304
Test name
Test status
Simulation time 1132723288 ps
CPU time 15.54 seconds
Started Jun 25 06:27:58 PM PDT 24
Finished Jun 25 06:28:15 PM PDT 24
Peak memory 251128 kb
Host smart-c855b630-fdc8-4be0-8826-cb7fb9b44b9c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196825720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.3196825720
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.2760829455
Short name T379
Test name
Test status
Simulation time 101262660 ps
CPU time 4.64 seconds
Started Jun 25 06:28:00 PM PDT 24
Finished Jun 25 06:28:06 PM PDT 24
Peak memory 222824 kb
Host smart-d0f87035-b19e-4751-a1ad-3eef44c453a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760829455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2760829455
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.1204255490
Short name T432
Test name
Test status
Simulation time 1493187704 ps
CPU time 15.73 seconds
Started Jun 25 06:28:00 PM PDT 24
Finished Jun 25 06:28:17 PM PDT 24
Peak memory 226236 kb
Host smart-ed289b7f-481a-49de-bd0d-70f755a95306
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204255490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1204255490
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.4272370738
Short name T820
Test name
Test status
Simulation time 564770396 ps
CPU time 10.27 seconds
Started Jun 25 06:28:04 PM PDT 24
Finished Jun 25 06:28:16 PM PDT 24
Peak memory 218408 kb
Host smart-c3bd9788-2cc8-42db-aaa3-3a622ceccdf7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272370738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.4272370738
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1802056987
Short name T314
Test name
Test status
Simulation time 546780228 ps
CPU time 7.27 seconds
Started Jun 25 06:27:58 PM PDT 24
Finished Jun 25 06:28:07 PM PDT 24
Peak memory 218416 kb
Host smart-d111bfee-8e7e-4d4e-934a-2f170bd2a46f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802056987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1802056987
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.3506618296
Short name T769
Test name
Test status
Simulation time 1618907872 ps
CPU time 14.26 seconds
Started Jun 25 06:27:58 PM PDT 24
Finished Jun 25 06:28:14 PM PDT 24
Peak memory 218556 kb
Host smart-2d20cb38-9bbb-4eb4-b297-cabaec8b0e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506618296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3506618296
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.1110654631
Short name T71
Test name
Test status
Simulation time 192290135 ps
CPU time 5.82 seconds
Started Jun 25 06:27:57 PM PDT 24
Finished Jun 25 06:28:04 PM PDT 24
Peak memory 217904 kb
Host smart-e3f10724-ff2a-47a0-9b77-8998546e09bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110654631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1110654631
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.3432734334
Short name T577
Test name
Test status
Simulation time 513591453 ps
CPU time 24.98 seconds
Started Jun 25 06:28:09 PM PDT 24
Finished Jun 25 06:28:35 PM PDT 24
Peak memory 251040 kb
Host smart-5f3998d7-713c-41cc-bfea-bc66752edcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432734334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.3432734334
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2799346087
Short name T453
Test name
Test status
Simulation time 309304247 ps
CPU time 9.13 seconds
Started Jun 25 06:28:04 PM PDT 24
Finished Jun 25 06:28:14 PM PDT 24
Peak memory 250972 kb
Host smart-89d3aa31-df6f-4d4b-b61a-b6a4df835dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799346087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2799346087
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.3673542520
Short name T443
Test name
Test status
Simulation time 47316124841 ps
CPU time 81.16 seconds
Started Jun 25 06:28:00 PM PDT 24
Finished Jun 25 06:29:23 PM PDT 24
Peak memory 278232 kb
Host smart-a62b4e4d-b866-49d0-b140-ccd68977bd7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673542520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.3673542520
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.937189237
Short name T863
Test name
Test status
Simulation time 14558663 ps
CPU time 0.9 seconds
Started Jun 25 06:27:57 PM PDT 24
Finished Jun 25 06:27:59 PM PDT 24
Peak memory 211968 kb
Host smart-4a410960-7ac0-460a-8371-3e7f8df62ff3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937189237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.937189237
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.682717920
Short name T693
Test name
Test status
Simulation time 55537606 ps
CPU time 1.1 seconds
Started Jun 25 06:28:04 PM PDT 24
Finished Jun 25 06:28:07 PM PDT 24
Peak memory 209052 kb
Host smart-2ff807a5-e27d-4462-8e98-849f1f9d071b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682717920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.682717920
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2518011602
Short name T833
Test name
Test status
Simulation time 720090626 ps
CPU time 16.15 seconds
Started Jun 25 06:28:06 PM PDT 24
Finished Jun 25 06:28:24 PM PDT 24
Peak memory 218444 kb
Host smart-8e8d9711-d589-430b-abd0-6af3bb48a6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518011602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2518011602
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.3145855441
Short name T763
Test name
Test status
Simulation time 478752413 ps
CPU time 5.99 seconds
Started Jun 25 06:28:11 PM PDT 24
Finished Jun 25 06:28:19 PM PDT 24
Peak memory 217484 kb
Host smart-6bf36427-76a0-4f49-adc6-544b65393dcc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145855441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.3145855441
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2018045129
Short name T830
Test name
Test status
Simulation time 1623613376 ps
CPU time 48.27 seconds
Started Jun 25 06:28:12 PM PDT 24
Finished Jun 25 06:29:04 PM PDT 24
Peak memory 219052 kb
Host smart-b1bd8940-3747-44ef-97d3-85ed1857d63e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018045129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2018045129
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2892149359
Short name T513
Test name
Test status
Simulation time 506813996 ps
CPU time 3.86 seconds
Started Jun 25 06:28:10 PM PDT 24
Finished Jun 25 06:28:14 PM PDT 24
Peak memory 221980 kb
Host smart-99130bc4-a704-4c0b-82e7-483725117b8b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892149359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.2892149359
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.4042326421
Short name T343
Test name
Test status
Simulation time 529153680 ps
CPU time 8.21 seconds
Started Jun 25 06:28:05 PM PDT 24
Finished Jun 25 06:28:16 PM PDT 24
Peak memory 217892 kb
Host smart-869809cc-ef62-4804-8275-2455f2a51a67
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042326421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.4042326421
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3532376526
Short name T6
Test name
Test status
Simulation time 2424433391 ps
CPU time 58.13 seconds
Started Jun 25 06:28:06 PM PDT 24
Finished Jun 25 06:29:06 PM PDT 24
Peak memory 267560 kb
Host smart-4d9e0e11-05f1-4c1d-bb43-a6de571cd739
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532376526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3532376526
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.3342655494
Short name T723
Test name
Test status
Simulation time 3703413397 ps
CPU time 18.43 seconds
Started Jun 25 06:28:05 PM PDT 24
Finished Jun 25 06:28:25 PM PDT 24
Peak memory 251140 kb
Host smart-6ed0a5be-7679-49d8-ba06-b34402bc8270
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342655494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.3342655494
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.2960026563
Short name T409
Test name
Test status
Simulation time 64843512 ps
CPU time 1.72 seconds
Started Jun 25 06:28:11 PM PDT 24
Finished Jun 25 06:28:15 PM PDT 24
Peak memory 218412 kb
Host smart-b2d8af6e-2ae3-4fa9-99af-ddd73a1ae0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960026563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.2960026563
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.2299111955
Short name T212
Test name
Test status
Simulation time 426563034 ps
CPU time 13.02 seconds
Started Jun 25 06:28:05 PM PDT 24
Finished Jun 25 06:28:20 PM PDT 24
Peak memory 226220 kb
Host smart-98d3af2a-8f6d-4018-8aa2-e9cb120ddb5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299111955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.2299111955
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3199962426
Short name T374
Test name
Test status
Simulation time 1495268194 ps
CPU time 10.89 seconds
Started Jun 25 06:28:13 PM PDT 24
Finished Jun 25 06:28:27 PM PDT 24
Peak memory 218424 kb
Host smart-4af03b26-4639-40a2-b599-5e62a24d5d2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199962426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.3199962426
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.3173988176
Short name T872
Test name
Test status
Simulation time 1024242259 ps
CPU time 8 seconds
Started Jun 25 06:28:05 PM PDT 24
Finished Jun 25 06:28:15 PM PDT 24
Peak memory 218416 kb
Host smart-101ef828-787e-4c59-94e1-cb7e5823341f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173988176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
3173988176
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.575858941
Short name T610
Test name
Test status
Simulation time 296376075 ps
CPU time 12.91 seconds
Started Jun 25 06:28:05 PM PDT 24
Finished Jun 25 06:28:21 PM PDT 24
Peak memory 226248 kb
Host smart-62594d2e-13bf-43fb-bc26-acc39b475804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575858941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.575858941
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.2329893394
Short name T227
Test name
Test status
Simulation time 24769458 ps
CPU time 2 seconds
Started Jun 25 06:28:09 PM PDT 24
Finished Jun 25 06:28:12 PM PDT 24
Peak memory 217896 kb
Host smart-ed816a70-1433-4c19-b084-91a389655a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329893394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2329893394
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1978334073
Short name T612
Test name
Test status
Simulation time 336207627 ps
CPU time 28.66 seconds
Started Jun 25 06:28:04 PM PDT 24
Finished Jun 25 06:28:35 PM PDT 24
Peak memory 251196 kb
Host smart-9b5443be-6fcb-4f25-a6bb-7a23f4e3fd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978334073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1978334073
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2485616158
Short name T561
Test name
Test status
Simulation time 221209257 ps
CPU time 6.16 seconds
Started Jun 25 06:28:05 PM PDT 24
Finished Jun 25 06:28:14 PM PDT 24
Peak memory 246788 kb
Host smart-d7b7aa78-16a6-4338-b57c-61e304b39a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485616158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2485616158
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.4155732318
Short name T631
Test name
Test status
Simulation time 55483669303 ps
CPU time 350.13 seconds
Started Jun 25 06:28:09 PM PDT 24
Finished Jun 25 06:34:00 PM PDT 24
Peak memory 271876 kb
Host smart-26b28f0b-0f78-4541-93c1-af4e1af96bab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155732318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.4155732318
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.63960867
Short name T91
Test name
Test status
Simulation time 10470691690 ps
CPU time 361.35 seconds
Started Jun 25 06:28:05 PM PDT 24
Finished Jun 25 06:34:08 PM PDT 24
Peak memory 405124 kb
Host smart-c7a6be43-8f76-4fdb-acd6-ed8a49a1a115
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=63960867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.63960867
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.4220595041
Short name T824
Test name
Test status
Simulation time 13834301 ps
CPU time 1.07 seconds
Started Jun 25 06:28:05 PM PDT 24
Finished Jun 25 06:28:09 PM PDT 24
Peak memory 212096 kb
Host smart-3a195877-ab6d-4705-9b7b-f0b1e16fa863
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220595041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.4220595041
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.2335807953
Short name T282
Test name
Test status
Simulation time 17919753 ps
CPU time 0.92 seconds
Started Jun 25 06:26:37 PM PDT 24
Finished Jun 25 06:26:43 PM PDT 24
Peak memory 209152 kb
Host smart-f8b33b72-f53e-445a-89dd-7cd1c59c17db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335807953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2335807953
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.989800599
Short name T326
Test name
Test status
Simulation time 224914309 ps
CPU time 11.17 seconds
Started Jun 25 06:26:26 PM PDT 24
Finished Jun 25 06:26:40 PM PDT 24
Peak memory 226228 kb
Host smart-6bd31b75-b929-49e1-8294-9b3fbc2dc106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989800599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.989800599
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.2770972477
Short name T531
Test name
Test status
Simulation time 528038217 ps
CPU time 7.71 seconds
Started Jun 25 06:26:36 PM PDT 24
Finished Jun 25 06:26:47 PM PDT 24
Peak memory 216912 kb
Host smart-9d920f7c-8c90-4cd3-9418-e62a17950d85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770972477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.2770972477
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1019838357
Short name T593
Test name
Test status
Simulation time 2623345371 ps
CPU time 64.76 seconds
Started Jun 25 06:26:36 PM PDT 24
Finished Jun 25 06:27:44 PM PDT 24
Peak memory 218616 kb
Host smart-b9a1a179-257d-4db0-a9ff-bcad77b1cac3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019838357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1019838357
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.2754288573
Short name T775
Test name
Test status
Simulation time 389097273 ps
CPU time 4.9 seconds
Started Jun 25 06:26:35 PM PDT 24
Finished Jun 25 06:26:42 PM PDT 24
Peak memory 218004 kb
Host smart-2d5950cf-d2c3-4016-9d74-a9eca8ebf088
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754288573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.2
754288573
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2796906497
Short name T259
Test name
Test status
Simulation time 3031067113 ps
CPU time 19.9 seconds
Started Jun 25 06:26:37 PM PDT 24
Finished Jun 25 06:27:02 PM PDT 24
Peak memory 223904 kb
Host smart-443e5131-3eda-4074-8e3e-e58fb7c64656
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796906497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2796906497
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2039655797
Short name T714
Test name
Test status
Simulation time 2967953451 ps
CPU time 23.71 seconds
Started Jun 25 06:26:37 PM PDT 24
Finished Jun 25 06:27:07 PM PDT 24
Peak memory 217976 kb
Host smart-06bb89ce-459e-4635-ab97-11dccb605241
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039655797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.2039655797
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.3510318458
Short name T499
Test name
Test status
Simulation time 316296462 ps
CPU time 5.22 seconds
Started Jun 25 06:26:26 PM PDT 24
Finished Jun 25 06:26:34 PM PDT 24
Peak memory 217956 kb
Host smart-8a39d269-7434-4c7e-9909-b011f468bfa7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510318458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
3510318458
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2643787859
Short name T624
Test name
Test status
Simulation time 10008949943 ps
CPU time 43.17 seconds
Started Jun 25 06:26:36 PM PDT 24
Finished Jun 25 06:27:24 PM PDT 24
Peak memory 267680 kb
Host smart-dbb2ac4d-0df2-4fe9-9c5e-434b09c00c0d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643787859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.2643787859
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2706165402
Short name T209
Test name
Test status
Simulation time 4560477126 ps
CPU time 19.66 seconds
Started Jun 25 06:26:35 PM PDT 24
Finished Jun 25 06:26:58 PM PDT 24
Peak memory 251184 kb
Host smart-b89652c7-34d2-4fb8-a21e-d8126bfc0a7c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706165402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.2706165402
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3902258391
Short name T354
Test name
Test status
Simulation time 92875389 ps
CPU time 3.04 seconds
Started Jun 25 06:26:27 PM PDT 24
Finished Jun 25 06:26:32 PM PDT 24
Peak memory 218400 kb
Host smart-5b57db32-d90e-4ccc-879f-6d2b22a628ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902258391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3902258391
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.735894002
Short name T323
Test name
Test status
Simulation time 279765589 ps
CPU time 18.84 seconds
Started Jun 25 06:26:30 PM PDT 24
Finished Jun 25 06:26:50 PM PDT 24
Peak memory 214812 kb
Host smart-43a7a221-b655-45e6-bfc6-0d8377637ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735894002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.735894002
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3480879599
Short name T53
Test name
Test status
Simulation time 229506786 ps
CPU time 38.71 seconds
Started Jun 25 06:26:37 PM PDT 24
Finished Jun 25 06:27:20 PM PDT 24
Peak memory 281928 kb
Host smart-1d0fc44a-1ba6-4f4b-b302-466c3bdaec32
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480879599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3480879599
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.4249778296
Short name T288
Test name
Test status
Simulation time 278548851 ps
CPU time 11.56 seconds
Started Jun 25 06:26:36 PM PDT 24
Finished Jun 25 06:26:52 PM PDT 24
Peak memory 226232 kb
Host smart-2ca3fb47-8d98-4c43-9c30-e900afed06be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249778296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.4249778296
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3167670359
Short name T211
Test name
Test status
Simulation time 1128135864 ps
CPU time 24.36 seconds
Started Jun 25 06:26:36 PM PDT 24
Finished Jun 25 06:27:04 PM PDT 24
Peak memory 218448 kb
Host smart-8fc6a4a3-57be-4831-a062-cdc2673b4a0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167670359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.3167670359
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.4138104633
Short name T296
Test name
Test status
Simulation time 1111781882 ps
CPU time 10.2 seconds
Started Jun 25 06:26:35 PM PDT 24
Finished Jun 25 06:26:48 PM PDT 24
Peak memory 218456 kb
Host smart-efc855af-2a7b-45ae-93fd-cf744b8ec0f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138104633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.4
138104633
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.2449245962
Short name T696
Test name
Test status
Simulation time 424832104 ps
CPU time 11.51 seconds
Started Jun 25 06:26:24 PM PDT 24
Finished Jun 25 06:26:37 PM PDT 24
Peak memory 218468 kb
Host smart-ce31d0fc-5752-484e-9d72-b9dbc35c1b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449245962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2449245962
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.2169137583
Short name T324
Test name
Test status
Simulation time 224276186 ps
CPU time 3.82 seconds
Started Jun 25 06:26:25 PM PDT 24
Finished Jun 25 06:26:31 PM PDT 24
Peak memory 217928 kb
Host smart-208cd82a-7e3f-40fe-91f9-42e2ce9c28eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169137583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.2169137583
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.573520939
Short name T530
Test name
Test status
Simulation time 248770165 ps
CPU time 25.57 seconds
Started Jun 25 06:26:25 PM PDT 24
Finished Jun 25 06:26:53 PM PDT 24
Peak memory 251208 kb
Host smart-01319673-34e2-4961-a037-be8d3af5e451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573520939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.573520939
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.2849368066
Short name T560
Test name
Test status
Simulation time 195242004 ps
CPU time 7.13 seconds
Started Jun 25 06:26:26 PM PDT 24
Finished Jun 25 06:26:36 PM PDT 24
Peak memory 251116 kb
Host smart-478bfd78-6ad9-4a88-af6a-45455fb7e25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849368066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2849368066
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3274105076
Short name T488
Test name
Test status
Simulation time 14221239 ps
CPU time 0.97 seconds
Started Jun 25 06:26:25 PM PDT 24
Finished Jun 25 06:26:28 PM PDT 24
Peak memory 212012 kb
Host smart-f51a4563-108d-4c8d-a009-7f49d723aa68
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274105076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.3274105076
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.4215292662
Short name T386
Test name
Test status
Simulation time 17837396 ps
CPU time 0.95 seconds
Started Jun 25 06:28:14 PM PDT 24
Finished Jun 25 06:28:18 PM PDT 24
Peak memory 209172 kb
Host smart-f184ef0a-0836-40fd-b6ff-356969d9864b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215292662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.4215292662
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.591239648
Short name T681
Test name
Test status
Simulation time 6295675016 ps
CPU time 13.68 seconds
Started Jun 25 06:28:04 PM PDT 24
Finished Jun 25 06:28:20 PM PDT 24
Peak memory 218504 kb
Host smart-720dd448-9c50-4806-bac7-81a58ef3ae86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591239648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.591239648
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.2746018000
Short name T780
Test name
Test status
Simulation time 8857034486 ps
CPU time 7.89 seconds
Started Jun 25 06:28:05 PM PDT 24
Finished Jun 25 06:28:15 PM PDT 24
Peak memory 217952 kb
Host smart-54a38bf7-d45a-4fde-a251-2127862f53a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746018000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.2746018000
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.1567262996
Short name T332
Test name
Test status
Simulation time 67571399 ps
CPU time 3.63 seconds
Started Jun 25 06:28:05 PM PDT 24
Finished Jun 25 06:28:11 PM PDT 24
Peak memory 222740 kb
Host smart-f6f03306-72a9-42a7-bbd2-d2560fe91f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567262996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1567262996
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.2945981722
Short name T391
Test name
Test status
Simulation time 312478765 ps
CPU time 11.12 seconds
Started Jun 25 06:28:12 PM PDT 24
Finished Jun 25 06:28:26 PM PDT 24
Peak memory 226228 kb
Host smart-daf34160-498c-4d25-bcba-12fb8a80e88a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945981722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2945981722
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.51001025
Short name T497
Test name
Test status
Simulation time 471470004 ps
CPU time 18.12 seconds
Started Jun 25 06:28:14 PM PDT 24
Finished Jun 25 06:28:35 PM PDT 24
Peak memory 218508 kb
Host smart-e211c81e-0dca-4e72-96f4-ba8aef1a9449
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51001025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_dig
est.51001025
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.665749050
Short name T868
Test name
Test status
Simulation time 1101843254 ps
CPU time 11.88 seconds
Started Jun 25 06:28:12 PM PDT 24
Finished Jun 25 06:28:27 PM PDT 24
Peak memory 218452 kb
Host smart-1027c988-d566-495f-9090-fae2f1fd81f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665749050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.665749050
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.1643914155
Short name T520
Test name
Test status
Simulation time 800316031 ps
CPU time 11.22 seconds
Started Jun 25 06:28:10 PM PDT 24
Finished Jun 25 06:28:24 PM PDT 24
Peak memory 218552 kb
Host smart-9696258e-6674-4315-b671-8297deec459b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643914155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1643914155
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1974851164
Short name T447
Test name
Test status
Simulation time 202499301 ps
CPU time 2.79 seconds
Started Jun 25 06:28:05 PM PDT 24
Finished Jun 25 06:28:10 PM PDT 24
Peak memory 217900 kb
Host smart-442b1c1b-f7a9-473f-9125-582876d5e493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974851164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1974851164
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.2733311914
Short name T298
Test name
Test status
Simulation time 318924499 ps
CPU time 26.13 seconds
Started Jun 25 06:28:06 PM PDT 24
Finished Jun 25 06:28:34 PM PDT 24
Peak memory 251112 kb
Host smart-ccf1c4f0-145d-4814-b88b-873a3e17a196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733311914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2733311914
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.3098764826
Short name T731
Test name
Test status
Simulation time 87225479 ps
CPU time 8.28 seconds
Started Jun 25 06:28:06 PM PDT 24
Finished Jun 25 06:28:16 PM PDT 24
Peak memory 251120 kb
Host smart-2c584e4e-c747-4922-a862-9e1df5540fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098764826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.3098764826
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1525236666
Short name T418
Test name
Test status
Simulation time 2736749213 ps
CPU time 95.32 seconds
Started Jun 25 06:28:13 PM PDT 24
Finished Jun 25 06:29:52 PM PDT 24
Peak memory 267536 kb
Host smart-bde3ca51-ab49-4c0a-903d-ee3390fe9578
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525236666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.1525236666
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1861690017
Short name T213
Test name
Test status
Simulation time 14162407 ps
CPU time 0.94 seconds
Started Jun 25 06:28:07 PM PDT 24
Finished Jun 25 06:28:10 PM PDT 24
Peak memory 213152 kb
Host smart-28b9f6fe-2cb9-4ec3-8149-d3a985045386
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861690017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1861690017
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.3067345819
Short name T15
Test name
Test status
Simulation time 877352144 ps
CPU time 16.18 seconds
Started Jun 25 06:28:17 PM PDT 24
Finished Jun 25 06:28:35 PM PDT 24
Peak memory 218324 kb
Host smart-8831abb7-6662-4ba6-afb7-d6b3568aaadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067345819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.3067345819
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.423373202
Short name T423
Test name
Test status
Simulation time 446639535 ps
CPU time 3.18 seconds
Started Jun 25 06:28:12 PM PDT 24
Finished Jun 25 06:28:19 PM PDT 24
Peak memory 217348 kb
Host smart-ad9891a7-a091-4bfb-bea8-17452a62a685
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423373202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.423373202
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.615663577
Short name T395
Test name
Test status
Simulation time 44385587 ps
CPU time 2.19 seconds
Started Jun 25 06:28:18 PM PDT 24
Finished Jun 25 06:28:22 PM PDT 24
Peak memory 218308 kb
Host smart-392ad3b4-9a17-4e43-b9b5-bea6146ca7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615663577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.615663577
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.2307193273
Short name T99
Test name
Test status
Simulation time 600126166 ps
CPU time 16.51 seconds
Started Jun 25 06:28:15 PM PDT 24
Finished Jun 25 06:28:34 PM PDT 24
Peak memory 226220 kb
Host smart-a7620184-80bb-4c2c-9789-3e346b345eed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307193273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.2307193273
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.3757299048
Short name T461
Test name
Test status
Simulation time 484119425 ps
CPU time 9.33 seconds
Started Jun 25 06:28:15 PM PDT 24
Finished Jun 25 06:28:27 PM PDT 24
Peak memory 218536 kb
Host smart-19caa841-5435-4dc5-bc88-78e1d4e53b88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757299048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.3757299048
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3334280330
Short name T482
Test name
Test status
Simulation time 1350132822 ps
CPU time 10.51 seconds
Started Jun 25 06:28:12 PM PDT 24
Finished Jun 25 06:28:26 PM PDT 24
Peak memory 218412 kb
Host smart-cadf7f2c-fad9-462a-8508-b44f4d5af526
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334280330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3334280330
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.1841970973
Short name T572
Test name
Test status
Simulation time 1376022326 ps
CPU time 12.24 seconds
Started Jun 25 06:28:17 PM PDT 24
Finished Jun 25 06:28:32 PM PDT 24
Peak memory 218384 kb
Host smart-94cb6de1-8eb3-416e-870f-41407bfaffc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841970973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1841970973
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1532430636
Short name T23
Test name
Test status
Simulation time 437258592 ps
CPU time 13.08 seconds
Started Jun 25 06:28:12 PM PDT 24
Finished Jun 25 06:28:28 PM PDT 24
Peak memory 217852 kb
Host smart-15607446-b19f-4eb4-88b7-0d140bbdab45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532430636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1532430636
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.2720120326
Short name T608
Test name
Test status
Simulation time 586019683 ps
CPU time 26.42 seconds
Started Jun 25 06:28:12 PM PDT 24
Finished Jun 25 06:28:42 PM PDT 24
Peak memory 251124 kb
Host smart-236286fd-a4a4-44a9-87e2-4137a860f25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720120326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2720120326
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.1535926218
Short name T214
Test name
Test status
Simulation time 444986594 ps
CPU time 8.17 seconds
Started Jun 25 06:28:15 PM PDT 24
Finished Jun 25 06:28:26 PM PDT 24
Peak memory 251136 kb
Host smart-f8f31a48-21d4-48c1-8496-f669933c2610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535926218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1535926218
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.923394487
Short name T574
Test name
Test status
Simulation time 9791803400 ps
CPU time 69.91 seconds
Started Jun 25 06:28:13 PM PDT 24
Finished Jun 25 06:29:27 PM PDT 24
Peak memory 251020 kb
Host smart-5dc292f7-06c5-4c6e-b3e2-618b7ea75e80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923394487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.923394487
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.1608795583
Short name T56
Test name
Test status
Simulation time 190354801501 ps
CPU time 854.75 seconds
Started Jun 25 06:28:20 PM PDT 24
Finished Jun 25 06:42:36 PM PDT 24
Peak memory 333196 kb
Host smart-acfe0f13-a716-4d63-873e-d35816ccf4b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1608795583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.1608795583
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2479256298
Short name T680
Test name
Test status
Simulation time 30613060 ps
CPU time 1.1 seconds
Started Jun 25 06:28:20 PM PDT 24
Finished Jun 25 06:28:22 PM PDT 24
Peak memory 209240 kb
Host smart-fb21b5d7-22d1-4d19-9c79-a077d8209486
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479256298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2479256298
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.3149224241
Short name T737
Test name
Test status
Simulation time 283930427 ps
CPU time 15.21 seconds
Started Jun 25 06:28:22 PM PDT 24
Finished Jun 25 06:28:39 PM PDT 24
Peak memory 226232 kb
Host smart-f233d12e-c2bd-4319-886b-993395edf972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149224241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3149224241
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.4099223945
Short name T427
Test name
Test status
Simulation time 169598381 ps
CPU time 2.6 seconds
Started Jun 25 06:28:20 PM PDT 24
Finished Jun 25 06:28:23 PM PDT 24
Peak memory 217296 kb
Host smart-faa3b51a-c9ca-44ed-a5d2-53aaf724f8fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099223945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.4099223945
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2780189180
Short name T356
Test name
Test status
Simulation time 309788442 ps
CPU time 3.34 seconds
Started Jun 25 06:28:20 PM PDT 24
Finished Jun 25 06:28:25 PM PDT 24
Peak memory 222776 kb
Host smart-25b05833-1b82-4ec6-ad33-5624a3be4c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780189180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2780189180
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.2399472726
Short name T469
Test name
Test status
Simulation time 2998607325 ps
CPU time 17.71 seconds
Started Jun 25 06:28:19 PM PDT 24
Finished Jun 25 06:28:38 PM PDT 24
Peak memory 226292 kb
Host smart-cc409f0b-f4d0-44c8-a65c-4d03b6ce399c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399472726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2399472726
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.1549784312
Short name T528
Test name
Test status
Simulation time 2210257416 ps
CPU time 15.26 seconds
Started Jun 25 06:28:20 PM PDT 24
Finished Jun 25 06:28:36 PM PDT 24
Peak memory 218508 kb
Host smart-094711f4-1dd5-4a6e-92ba-459a034de58c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549784312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.1549784312
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2779833727
Short name T828
Test name
Test status
Simulation time 398353051 ps
CPU time 8.47 seconds
Started Jun 25 06:28:21 PM PDT 24
Finished Jun 25 06:28:31 PM PDT 24
Peak memory 218412 kb
Host smart-cb2d3215-01c6-4380-a712-41e669d5953b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779833727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2779833727
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.396584787
Short name T500
Test name
Test status
Simulation time 1181527877 ps
CPU time 11.95 seconds
Started Jun 25 06:28:23 PM PDT 24
Finished Jun 25 06:28:36 PM PDT 24
Peak memory 218556 kb
Host smart-efdc3e34-617d-4d47-b738-3573a5f2b521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396584787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.396584787
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.1985143423
Short name T862
Test name
Test status
Simulation time 612894063 ps
CPU time 5.07 seconds
Started Jun 25 06:28:21 PM PDT 24
Finished Jun 25 06:28:28 PM PDT 24
Peak memory 217992 kb
Host smart-d4c34034-df77-44fc-9773-566d386fba25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985143423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1985143423
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.4071234976
Short name T201
Test name
Test status
Simulation time 3221135269 ps
CPU time 32.95 seconds
Started Jun 25 06:28:20 PM PDT 24
Finished Jun 25 06:28:55 PM PDT 24
Peak memory 251080 kb
Host smart-ebbd5f5a-0373-4359-b175-4e72d6bdf8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071234976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.4071234976
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.2586267081
Short name T231
Test name
Test status
Simulation time 123558345 ps
CPU time 7.17 seconds
Started Jun 25 06:28:20 PM PDT 24
Finished Jun 25 06:28:28 PM PDT 24
Peak memory 251116 kb
Host smart-fad632e2-271c-49ed-ace4-1309e47bae00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586267081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.2586267081
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1003096183
Short name T83
Test name
Test status
Simulation time 11915669797 ps
CPU time 91.03 seconds
Started Jun 25 06:28:21 PM PDT 24
Finished Jun 25 06:29:53 PM PDT 24
Peak memory 251204 kb
Host smart-28a4afe2-27d6-49b9-bda0-b70d36ff0d90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003096183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.1003096183
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.4095061475
Short name T161
Test name
Test status
Simulation time 28801833927 ps
CPU time 1079.88 seconds
Started Jun 25 06:28:23 PM PDT 24
Finished Jun 25 06:46:24 PM PDT 24
Peak memory 497032 kb
Host smart-c9631642-cc00-4a1a-93e2-b6f8433db1f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4095061475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.4095061475
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.1380461172
Short name T728
Test name
Test status
Simulation time 13300195 ps
CPU time 0.92 seconds
Started Jun 25 06:28:21 PM PDT 24
Finished Jun 25 06:28:23 PM PDT 24
Peak memory 212144 kb
Host smart-d2e09927-5e31-4fc1-8ee0-3f7a7a5bb8c0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380461172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.1380461172
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.3949319992
Short name T585
Test name
Test status
Simulation time 66086667 ps
CPU time 0.91 seconds
Started Jun 25 06:28:31 PM PDT 24
Finished Jun 25 06:28:34 PM PDT 24
Peak memory 209180 kb
Host smart-0854065e-a9f4-4d22-9491-c0acd45ded02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949319992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3949319992
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3341216680
Short name T95
Test name
Test status
Simulation time 174652746 ps
CPU time 8.92 seconds
Started Jun 25 06:28:29 PM PDT 24
Finished Jun 25 06:28:41 PM PDT 24
Peak memory 226236 kb
Host smart-8b415af1-e9eb-48a1-bdb8-b1cfc29224c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341216680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3341216680
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.4031352779
Short name T599
Test name
Test status
Simulation time 237122837 ps
CPU time 4.33 seconds
Started Jun 25 06:28:30 PM PDT 24
Finished Jun 25 06:28:37 PM PDT 24
Peak memory 217272 kb
Host smart-28b334fe-5cac-4372-b17f-86e4e2ba9424
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031352779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.4031352779
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.1739142478
Short name T858
Test name
Test status
Simulation time 50137623 ps
CPU time 2.58 seconds
Started Jun 25 06:28:27 PM PDT 24
Finished Jun 25 06:28:33 PM PDT 24
Peak memory 218348 kb
Host smart-d4e4229e-e836-403c-8a45-6ba1e015a078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739142478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.1739142478
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.644526599
Short name T559
Test name
Test status
Simulation time 439753933 ps
CPU time 9.33 seconds
Started Jun 25 06:28:29 PM PDT 24
Finished Jun 25 06:28:41 PM PDT 24
Peak memory 226244 kb
Host smart-3481a354-ee63-4cb5-9b0e-b27d1cd7f26a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644526599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.644526599
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1715628086
Short name T800
Test name
Test status
Simulation time 2531387563 ps
CPU time 14.79 seconds
Started Jun 25 06:28:28 PM PDT 24
Finished Jun 25 06:28:45 PM PDT 24
Peak memory 219260 kb
Host smart-ad40dbf5-3bc6-4017-abcc-c5f6ea6440f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715628086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.1715628086
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2198429737
Short name T60
Test name
Test status
Simulation time 925284693 ps
CPU time 10.11 seconds
Started Jun 25 06:28:27 PM PDT 24
Finished Jun 25 06:28:39 PM PDT 24
Peak memory 218448 kb
Host smart-d709996d-6cc7-40a7-b6f4-c1d3d97542b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198429737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2198429737
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.3921147243
Short name T442
Test name
Test status
Simulation time 295576269 ps
CPU time 11.65 seconds
Started Jun 25 06:28:29 PM PDT 24
Finished Jun 25 06:28:43 PM PDT 24
Peak memory 218488 kb
Host smart-5028a318-2ee1-413d-85b9-536c43f6a1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921147243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3921147243
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1891722850
Short name T581
Test name
Test status
Simulation time 37939773 ps
CPU time 1.56 seconds
Started Jun 25 06:28:21 PM PDT 24
Finished Jun 25 06:28:24 PM PDT 24
Peak memory 223152 kb
Host smart-92a43645-7fc7-494e-8dcf-1e639462696d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891722850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1891722850
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.3138957106
Short name T836
Test name
Test status
Simulation time 479779784 ps
CPU time 22.51 seconds
Started Jun 25 06:28:29 PM PDT 24
Finished Jun 25 06:28:54 PM PDT 24
Peak memory 251120 kb
Host smart-27741748-c458-4a96-a60c-51f4d6423211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138957106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3138957106
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.483289736
Short name T92
Test name
Test status
Simulation time 283473383 ps
CPU time 6.36 seconds
Started Jun 25 06:28:29 PM PDT 24
Finished Jun 25 06:28:38 PM PDT 24
Peak memory 250528 kb
Host smart-b8f8fbab-ccdb-4815-a4fc-cf51f89f89c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483289736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.483289736
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.553214102
Short name T846
Test name
Test status
Simulation time 5247610716 ps
CPU time 183.3 seconds
Started Jun 25 06:28:28 PM PDT 24
Finished Jun 25 06:31:34 PM PDT 24
Peak memory 277768 kb
Host smart-cfe8250e-8019-4d37-a61e-76e189d6b8c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553214102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.553214102
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.2867378526
Short name T17
Test name
Test status
Simulation time 29196745950 ps
CPU time 474.36 seconds
Started Jun 25 06:28:28 PM PDT 24
Finished Jun 25 06:36:26 PM PDT 24
Peak memory 300396 kb
Host smart-8ba23961-03e3-4d85-9ab1-7b6dcaf7240c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2867378526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.2867378526
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1871666151
Short name T592
Test name
Test status
Simulation time 13171130 ps
CPU time 0.92 seconds
Started Jun 25 06:28:21 PM PDT 24
Finished Jun 25 06:28:23 PM PDT 24
Peak memory 212080 kb
Host smart-87181f74-ec83-4e5f-8056-af5e92e1d8bb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871666151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.1871666151
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.56426606
Short name T664
Test name
Test status
Simulation time 13658777 ps
CPU time 0.85 seconds
Started Jun 25 06:28:27 PM PDT 24
Finished Jun 25 06:28:31 PM PDT 24
Peak memory 208988 kb
Host smart-0accbe69-11b0-4650-bf3c-33b24a1b9e14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56426606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.56426606
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.3588751996
Short name T163
Test name
Test status
Simulation time 1129212434 ps
CPU time 23.86 seconds
Started Jun 25 06:28:31 PM PDT 24
Finished Jun 25 06:28:57 PM PDT 24
Peak memory 218444 kb
Host smart-49a4b16c-4b16-44c2-b510-ab275ad39a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588751996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3588751996
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.2773444625
Short name T400
Test name
Test status
Simulation time 1461684428 ps
CPU time 7.45 seconds
Started Jun 25 06:28:27 PM PDT 24
Finished Jun 25 06:28:37 PM PDT 24
Peak memory 217600 kb
Host smart-47ae5437-0a2b-4b1d-842b-e08122de81b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773444625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.2773444625
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.895244720
Short name T595
Test name
Test status
Simulation time 33910721 ps
CPU time 2.12 seconds
Started Jun 25 06:28:26 PM PDT 24
Finished Jun 25 06:28:30 PM PDT 24
Peak memory 222288 kb
Host smart-5fb65b1f-476e-46e8-a789-0a815d987d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895244720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.895244720
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.589316738
Short name T788
Test name
Test status
Simulation time 221524452 ps
CPU time 10.43 seconds
Started Jun 25 06:28:27 PM PDT 24
Finished Jun 25 06:28:40 PM PDT 24
Peak memory 218440 kb
Host smart-2671b0af-598b-45cd-92b0-8f3a4d352bef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589316738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.589316738
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.501760205
Short name T451
Test name
Test status
Simulation time 437409374 ps
CPU time 12.32 seconds
Started Jun 25 06:28:28 PM PDT 24
Finished Jun 25 06:28:43 PM PDT 24
Peak memory 218440 kb
Host smart-15d3cdd6-256b-427b-b49a-affb57c0f859
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501760205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_di
gest.501760205
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3810556673
Short name T229
Test name
Test status
Simulation time 2256725978 ps
CPU time 9.01 seconds
Started Jun 25 06:28:29 PM PDT 24
Finished Jun 25 06:28:41 PM PDT 24
Peak memory 218380 kb
Host smart-c5b59c30-f05d-4f54-ba73-eea4e62bffef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810556673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3810556673
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3796713599
Short name T407
Test name
Test status
Simulation time 1167221991 ps
CPU time 9.63 seconds
Started Jun 25 06:28:29 PM PDT 24
Finished Jun 25 06:28:41 PM PDT 24
Peak memory 218480 kb
Host smart-1feeb6f0-57ed-47a2-92c7-8add7d3cc921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796713599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3796713599
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.1706668372
Short name T312
Test name
Test status
Simulation time 76546510 ps
CPU time 3.09 seconds
Started Jun 25 06:28:27 PM PDT 24
Finished Jun 25 06:28:33 PM PDT 24
Peak memory 215092 kb
Host smart-47f0276e-6046-4ef0-8e3e-0a936c9504c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706668372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1706668372
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.217867914
Short name T684
Test name
Test status
Simulation time 286747923 ps
CPU time 26.35 seconds
Started Jun 25 06:28:27 PM PDT 24
Finished Jun 25 06:28:56 PM PDT 24
Peak memory 251100 kb
Host smart-ace850e4-abe3-4f4b-be5e-dcf3819d2053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217867914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.217867914
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.2881246106
Short name T707
Test name
Test status
Simulation time 70475596 ps
CPU time 7.26 seconds
Started Jun 25 06:28:28 PM PDT 24
Finished Jun 25 06:28:38 PM PDT 24
Peak memory 248588 kb
Host smart-94fb2ab1-15c2-49e1-be1a-40984d54f5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881246106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.2881246106
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.1071356160
Short name T197
Test name
Test status
Simulation time 3504221001 ps
CPU time 53.18 seconds
Started Jun 25 06:28:29 PM PDT 24
Finished Jun 25 06:29:25 PM PDT 24
Peak memory 269624 kb
Host smart-c2681980-6f25-4ed1-ace2-fbbcbd8eece9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071356160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.1071356160
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.1920132048
Short name T749
Test name
Test status
Simulation time 41982159500 ps
CPU time 199.21 seconds
Started Jun 25 06:28:30 PM PDT 24
Finished Jun 25 06:31:52 PM PDT 24
Peak memory 254416 kb
Host smart-811e5194-45e0-4d33-93d8-f9fad819b934
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1920132048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.1920132048
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2275665491
Short name T275
Test name
Test status
Simulation time 15648382 ps
CPU time 1.06 seconds
Started Jun 25 06:28:28 PM PDT 24
Finished Jun 25 06:28:32 PM PDT 24
Peak memory 212116 kb
Host smart-2951ebf7-e54d-4aca-bebc-0811cb10bbfe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275665491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.2275665491
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.3583199809
Short name T72
Test name
Test status
Simulation time 62288176 ps
CPU time 1.11 seconds
Started Jun 25 06:28:35 PM PDT 24
Finished Jun 25 06:28:38 PM PDT 24
Peak memory 209192 kb
Host smart-7b7765d4-0fc7-429b-b8ec-16a2b5e0f3db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583199809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3583199809
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.62363808
Short name T689
Test name
Test status
Simulation time 618671787 ps
CPU time 8.03 seconds
Started Jun 25 06:28:30 PM PDT 24
Finished Jun 25 06:28:40 PM PDT 24
Peak memory 218456 kb
Host smart-6781b920-84d7-4878-ad37-7481d0deef1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62363808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.62363808
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.1528763663
Short name T41
Test name
Test status
Simulation time 396029423 ps
CPU time 10.42 seconds
Started Jun 25 06:28:28 PM PDT 24
Finished Jun 25 06:28:42 PM PDT 24
Peak memory 217560 kb
Host smart-c3046b37-a7ef-4012-a770-fce8624fd450
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528763663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.1528763663
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.934109447
Short name T567
Test name
Test status
Simulation time 57536355 ps
CPU time 2.71 seconds
Started Jun 25 06:28:29 PM PDT 24
Finished Jun 25 06:28:35 PM PDT 24
Peak memory 218404 kb
Host smart-488ab3c8-4b42-4254-9c23-12c4c068db25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934109447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.934109447
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.3059865604
Short name T349
Test name
Test status
Simulation time 248570944 ps
CPU time 8.4 seconds
Started Jun 25 06:28:29 PM PDT 24
Finished Jun 25 06:28:40 PM PDT 24
Peak memory 226296 kb
Host smart-2173dfb0-6275-4bf1-b13d-c1fa06b03f7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059865604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.3059865604
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2906163796
Short name T285
Test name
Test status
Simulation time 699971341 ps
CPU time 14.25 seconds
Started Jun 25 06:28:28 PM PDT 24
Finished Jun 25 06:28:45 PM PDT 24
Peak memory 218516 kb
Host smart-779f1a8c-922c-48ba-902e-9397d7310c7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906163796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2906163796
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.556971606
Short name T556
Test name
Test status
Simulation time 2653154541 ps
CPU time 13.59 seconds
Started Jun 25 06:28:28 PM PDT 24
Finished Jun 25 06:28:44 PM PDT 24
Peak memory 218508 kb
Host smart-a50fada4-ecc1-465f-b2f9-55f5e69dd385
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556971606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.556971606
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1937834035
Short name T372
Test name
Test status
Simulation time 711415499 ps
CPU time 13.57 seconds
Started Jun 25 06:28:28 PM PDT 24
Finished Jun 25 06:28:44 PM PDT 24
Peak memory 218488 kb
Host smart-0b94f939-bdaa-4215-80c4-82a03454d1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937834035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1937834035
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.1461903938
Short name T739
Test name
Test status
Simulation time 608453092 ps
CPU time 3.49 seconds
Started Jun 25 06:28:27 PM PDT 24
Finished Jun 25 06:28:34 PM PDT 24
Peak memory 217940 kb
Host smart-1a96129c-f533-4e2f-8db4-6c2e5b58c7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461903938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.1461903938
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3181063713
Short name T534
Test name
Test status
Simulation time 355343114 ps
CPU time 19.55 seconds
Started Jun 25 06:28:28 PM PDT 24
Finished Jun 25 06:28:50 PM PDT 24
Peak memory 246328 kb
Host smart-2c72dfd0-65bb-431d-913f-bbf54a4d78e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181063713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3181063713
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.9986757
Short name T791
Test name
Test status
Simulation time 163764427 ps
CPU time 10.59 seconds
Started Jun 25 06:28:27 PM PDT 24
Finished Jun 25 06:28:40 PM PDT 24
Peak memory 251072 kb
Host smart-fffccaf2-27bd-4523-b664-d3fb45a3756e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9986757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.9986757
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.4206565958
Short name T373
Test name
Test status
Simulation time 14374852816 ps
CPU time 73.78 seconds
Started Jun 25 06:28:36 PM PDT 24
Finished Jun 25 06:29:53 PM PDT 24
Peak memory 251172 kb
Host smart-2b41bec3-16c6-4597-9ed8-b2935f60c727
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206565958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.4206565958
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.377369947
Short name T715
Test name
Test status
Simulation time 14254803 ps
CPU time 1.03 seconds
Started Jun 25 06:28:29 PM PDT 24
Finished Jun 25 06:28:33 PM PDT 24
Peak memory 213164 kb
Host smart-30481a9a-0c8f-4db5-aee2-cf51919a361b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377369947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ct
rl_volatile_unlock_smoke.377369947
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1003194877
Short name T70
Test name
Test status
Simulation time 27147527 ps
CPU time 0.98 seconds
Started Jun 25 06:28:36 PM PDT 24
Finished Jun 25 06:28:39 PM PDT 24
Peak memory 209132 kb
Host smart-6fae1574-3953-41d8-ae12-beb9d0e65e9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003194877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1003194877
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.885274281
Short name T150
Test name
Test status
Simulation time 1495887435 ps
CPU time 11.61 seconds
Started Jun 25 06:28:38 PM PDT 24
Finished Jun 25 06:28:52 PM PDT 24
Peak memory 226236 kb
Host smart-4b6e5113-a11f-4d66-90fe-686b30422a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885274281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.885274281
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.739732000
Short name T39
Test name
Test status
Simulation time 1823008026 ps
CPU time 10.96 seconds
Started Jun 25 06:28:41 PM PDT 24
Finished Jun 25 06:28:53 PM PDT 24
Peak memory 217592 kb
Host smart-a10c40c5-c066-4ec0-9c30-48dc413b03a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739732000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.739732000
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.577427332
Short name T415
Test name
Test status
Simulation time 83778136 ps
CPU time 2.97 seconds
Started Jun 25 06:28:36 PM PDT 24
Finished Jun 25 06:28:41 PM PDT 24
Peak memory 222568 kb
Host smart-ce5b3296-9d3a-4c24-b8dc-6c3ddc56125b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577427332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.577427332
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.4036555729
Short name T507
Test name
Test status
Simulation time 393972594 ps
CPU time 13.51 seconds
Started Jun 25 06:28:34 PM PDT 24
Finished Jun 25 06:28:49 PM PDT 24
Peak memory 219152 kb
Host smart-85d5c126-777b-4edd-be98-9761023fdcbd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036555729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.4036555729
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.275561483
Short name T155
Test name
Test status
Simulation time 1497288295 ps
CPU time 9.18 seconds
Started Jun 25 06:28:41 PM PDT 24
Finished Jun 25 06:28:52 PM PDT 24
Peak memory 218452 kb
Host smart-2fc75da9-5c14-4074-a953-fc650f685a45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275561483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_di
gest.275561483
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3288927764
Short name T544
Test name
Test status
Simulation time 2002374602 ps
CPU time 20.43 seconds
Started Jun 25 06:28:35 PM PDT 24
Finished Jun 25 06:28:57 PM PDT 24
Peak memory 218412 kb
Host smart-f56a6a2c-ed0c-4c27-b62a-52cad11ef36f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288927764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3288927764
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.53759844
Short name T785
Test name
Test status
Simulation time 569045967 ps
CPU time 14.22 seconds
Started Jun 25 06:28:35 PM PDT 24
Finished Jun 25 06:28:51 PM PDT 24
Peak memory 218396 kb
Host smart-25621d18-40e3-4352-a9d7-5d9c39e1185b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53759844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.53759844
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3852431960
Short name T311
Test name
Test status
Simulation time 53520687 ps
CPU time 1.71 seconds
Started Jun 25 06:28:34 PM PDT 24
Finished Jun 25 06:28:38 PM PDT 24
Peak memory 214244 kb
Host smart-cd153d9e-71b6-495e-afaa-8c7828e93e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852431960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3852431960
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1188584394
Short name T463
Test name
Test status
Simulation time 346923355 ps
CPU time 23.73 seconds
Started Jun 25 06:28:38 PM PDT 24
Finished Jun 25 06:29:04 PM PDT 24
Peak memory 251124 kb
Host smart-24d9f2e0-f0a5-44a4-9b29-52ac0df9fd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188584394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1188584394
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.2140004553
Short name T537
Test name
Test status
Simulation time 58396902 ps
CPU time 7.98 seconds
Started Jun 25 06:28:35 PM PDT 24
Finished Jun 25 06:28:44 PM PDT 24
Peak memory 251240 kb
Host smart-a590861b-c54b-459a-8590-5cc1182ce2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140004553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.2140004553
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.143352681
Short name T804
Test name
Test status
Simulation time 7735942385 ps
CPU time 306.82 seconds
Started Jun 25 06:28:41 PM PDT 24
Finished Jun 25 06:33:49 PM PDT 24
Peak memory 496896 kb
Host smart-ca37d79e-534f-4d5a-8f06-b797adb7ca1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143352681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.143352681
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1633825450
Short name T855
Test name
Test status
Simulation time 33574254 ps
CPU time 0.81 seconds
Started Jun 25 06:28:36 PM PDT 24
Finished Jun 25 06:28:39 PM PDT 24
Peak memory 212068 kb
Host smart-d6a9f251-d05a-4e18-ac5a-9be94d37d192
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633825450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1633825450
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.1649975520
Short name T511
Test name
Test status
Simulation time 80419692 ps
CPU time 0.95 seconds
Started Jun 25 06:28:43 PM PDT 24
Finished Jun 25 06:28:46 PM PDT 24
Peak memory 209220 kb
Host smart-505c9245-64f3-4941-8c03-c853429829e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649975520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.1649975520
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.1628591096
Short name T786
Test name
Test status
Simulation time 1903747501 ps
CPU time 12.59 seconds
Started Jun 25 06:28:34 PM PDT 24
Finished Jun 25 06:28:48 PM PDT 24
Peak memory 218420 kb
Host smart-f786935a-a251-40b3-bcb7-342728d0fbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628591096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.1628591096
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.638633420
Short name T489
Test name
Test status
Simulation time 601798581 ps
CPU time 2.34 seconds
Started Jun 25 06:28:37 PM PDT 24
Finished Jun 25 06:28:42 PM PDT 24
Peak memory 217328 kb
Host smart-203ac4dd-1e2e-4d13-8517-7c6a82aa380c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638633420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.638633420
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.8790094
Short name T291
Test name
Test status
Simulation time 59234636 ps
CPU time 2.45 seconds
Started Jun 25 06:28:42 PM PDT 24
Finished Jun 25 06:28:46 PM PDT 24
Peak memory 222332 kb
Host smart-59f76663-c323-4070-9076-e567ac2606c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8790094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.8790094
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.4040600244
Short name T606
Test name
Test status
Simulation time 418233798 ps
CPU time 18.87 seconds
Started Jun 25 06:28:35 PM PDT 24
Finished Jun 25 06:28:56 PM PDT 24
Peak memory 226260 kb
Host smart-5f885836-083f-4a48-add0-dd150186a49f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040600244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.4040600244
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.4097698356
Short name T410
Test name
Test status
Simulation time 715787056 ps
CPU time 14.95 seconds
Started Jun 25 06:28:37 PM PDT 24
Finished Jun 25 06:28:54 PM PDT 24
Peak memory 218460 kb
Host smart-bda4b469-7b52-461b-a22c-012b14e47a86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097698356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.4097698356
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1300185098
Short name T588
Test name
Test status
Simulation time 202720591 ps
CPU time 6.22 seconds
Started Jun 25 06:28:41 PM PDT 24
Finished Jun 25 06:28:49 PM PDT 24
Peak memory 218424 kb
Host smart-0b4d7ba4-ddfe-472f-a461-1a3edd12626b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300185098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1300185098
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.1975548407
Short name T551
Test name
Test status
Simulation time 1381478859 ps
CPU time 10.18 seconds
Started Jun 25 06:28:36 PM PDT 24
Finished Jun 25 06:28:49 PM PDT 24
Peak memory 218572 kb
Host smart-78f8405a-6c57-4fbf-a14e-5179cec85ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975548407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1975548407
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.770154811
Short name T795
Test name
Test status
Simulation time 43240455 ps
CPU time 3.1 seconds
Started Jun 25 06:28:36 PM PDT 24
Finished Jun 25 06:28:42 PM PDT 24
Peak memory 214988 kb
Host smart-4fb37d46-fec3-43ef-a625-1d487f43380d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770154811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.770154811
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3850359963
Short name T200
Test name
Test status
Simulation time 182508823 ps
CPU time 16.11 seconds
Started Jun 25 06:28:36 PM PDT 24
Finished Jun 25 06:28:55 PM PDT 24
Peak memory 251120 kb
Host smart-8a0c4fd8-df98-424d-8a3a-bb11a32b77a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850359963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3850359963
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.1049422216
Short name T555
Test name
Test status
Simulation time 73694531 ps
CPU time 6.73 seconds
Started Jun 25 06:28:35 PM PDT 24
Finished Jun 25 06:28:44 PM PDT 24
Peak memory 250696 kb
Host smart-dac1f25d-05cc-4d39-8131-6f2b75122d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049422216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1049422216
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.4285540303
Short name T58
Test name
Test status
Simulation time 10143225900 ps
CPU time 382.8 seconds
Started Jun 25 06:28:42 PM PDT 24
Finished Jun 25 06:35:06 PM PDT 24
Peak memory 270192 kb
Host smart-84e51da4-33da-47c2-ba36-c5760b661fdf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285540303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.4285540303
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.3065813465
Short name T725
Test name
Test status
Simulation time 42478280064 ps
CPU time 205.96 seconds
Started Jun 25 06:28:44 PM PDT 24
Finished Jun 25 06:32:11 PM PDT 24
Peak memory 276756 kb
Host smart-8b9410d6-c9a2-4993-a199-056a1746921f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3065813465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.3065813465
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1534055338
Short name T190
Test name
Test status
Simulation time 37912315 ps
CPU time 0.87 seconds
Started Jun 25 06:28:36 PM PDT 24
Finished Jun 25 06:28:40 PM PDT 24
Peak memory 213124 kb
Host smart-7a7ab96b-ca94-43e9-8695-9ab2a2f92975
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534055338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.1534055338
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.2266365742
Short name T43
Test name
Test status
Simulation time 23774269 ps
CPU time 1.21 seconds
Started Jun 25 06:28:42 PM PDT 24
Finished Jun 25 06:28:44 PM PDT 24
Peak memory 209468 kb
Host smart-6383e6fc-ea90-4367-962d-88df0fe684d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266365742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.2266365742
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.101042243
Short name T262
Test name
Test status
Simulation time 554546751 ps
CPU time 11.52 seconds
Started Jun 25 06:28:43 PM PDT 24
Finished Jun 25 06:28:55 PM PDT 24
Peak memory 218348 kb
Host smart-f2a6b881-3017-47c3-8dad-ce50ee6d2639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101042243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.101042243
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1313415008
Short name T671
Test name
Test status
Simulation time 418400661 ps
CPU time 5.71 seconds
Started Jun 25 06:28:43 PM PDT 24
Finished Jun 25 06:28:50 PM PDT 24
Peak memory 217348 kb
Host smart-61104aa9-4bcc-44ee-a916-4716f5cb933e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313415008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1313415008
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2080330064
Short name T267
Test name
Test status
Simulation time 141043092 ps
CPU time 3.94 seconds
Started Jun 25 06:28:44 PM PDT 24
Finished Jun 25 06:28:50 PM PDT 24
Peak memory 218340 kb
Host smart-02b0ede6-f133-4622-9464-71b2d46fdb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080330064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2080330064
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.3291940828
Short name T208
Test name
Test status
Simulation time 523533796 ps
CPU time 14.86 seconds
Started Jun 25 06:28:43 PM PDT 24
Finished Jun 25 06:28:59 PM PDT 24
Peak memory 226252 kb
Host smart-470eed99-6cdf-4ecc-9926-6c7babea2670
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291940828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3291940828
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1219909505
Short name T24
Test name
Test status
Simulation time 3301425778 ps
CPU time 14.09 seconds
Started Jun 25 06:28:51 PM PDT 24
Finished Jun 25 06:29:07 PM PDT 24
Peak memory 219092 kb
Host smart-d21b9e4f-1a1b-4d55-88ae-04f2ae49ec49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219909505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.1219909505
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3727849345
Short name T549
Test name
Test status
Simulation time 426565493 ps
CPU time 9.23 seconds
Started Jun 25 06:28:41 PM PDT 24
Finished Jun 25 06:28:51 PM PDT 24
Peak memory 218424 kb
Host smart-7d1cb55a-4aa5-4bb8-adf9-c50497127286
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727849345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3727849345
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2972536596
Short name T195
Test name
Test status
Simulation time 1073699024 ps
CPU time 7.47 seconds
Started Jun 25 06:28:41 PM PDT 24
Finished Jun 25 06:28:50 PM PDT 24
Peak memory 218556 kb
Host smart-bb3b4f99-defe-4323-81ee-c001417a8816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972536596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2972536596
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2971843340
Short name T672
Test name
Test status
Simulation time 220938802 ps
CPU time 3.21 seconds
Started Jun 25 06:28:40 PM PDT 24
Finished Jun 25 06:28:45 PM PDT 24
Peak memory 223000 kb
Host smart-f02fd9d5-269e-416e-bdd4-3ec6177168c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971843340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2971843340
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.2358070260
Short name T639
Test name
Test status
Simulation time 543611284 ps
CPU time 20.16 seconds
Started Jun 25 06:28:43 PM PDT 24
Finished Jun 25 06:29:05 PM PDT 24
Peak memory 251056 kb
Host smart-9e4b09e6-bf5f-4b11-8aa8-a649e35f3b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358070260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2358070260
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.1886914070
Short name T232
Test name
Test status
Simulation time 563536601 ps
CPU time 6.05 seconds
Started Jun 25 06:28:44 PM PDT 24
Finished Jun 25 06:28:51 PM PDT 24
Peak memory 226540 kb
Host smart-93460864-4323-4650-b1b8-ef99fdc2bd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886914070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.1886914070
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.1970569401
Short name T596
Test name
Test status
Simulation time 7558022919 ps
CPU time 147.82 seconds
Started Jun 25 06:28:50 PM PDT 24
Finished Jun 25 06:31:20 PM PDT 24
Peak memory 251012 kb
Host smart-ca31720a-cc08-457d-aadd-e04030dc10d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970569401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.1970569401
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1191555873
Short name T222
Test name
Test status
Simulation time 14882484 ps
CPU time 0.93 seconds
Started Jun 25 06:28:43 PM PDT 24
Finished Jun 25 06:28:46 PM PDT 24
Peak memory 212136 kb
Host smart-3dfc3740-108b-45b3-8d17-161f8bd3eae8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191555873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1191555873
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.2678268230
Short name T273
Test name
Test status
Simulation time 50794613 ps
CPU time 0.86 seconds
Started Jun 25 06:28:43 PM PDT 24
Finished Jun 25 06:28:46 PM PDT 24
Peak memory 208944 kb
Host smart-74d1125c-e5f2-4296-b93a-316d62a8978f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678268230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2678268230
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3785764131
Short name T484
Test name
Test status
Simulation time 261826360 ps
CPU time 13.22 seconds
Started Jun 25 06:28:41 PM PDT 24
Finished Jun 25 06:28:56 PM PDT 24
Peak memory 226296 kb
Host smart-b3799486-b09f-4975-a68d-af8bc6ce3bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785764131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3785764131
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.4275853328
Short name T38
Test name
Test status
Simulation time 814264073 ps
CPU time 5.68 seconds
Started Jun 25 06:28:41 PM PDT 24
Finished Jun 25 06:28:48 PM PDT 24
Peak memory 218004 kb
Host smart-5fa5793c-af1d-40d8-8137-bb334b308fee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275853328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.4275853328
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.1678315184
Short name T753
Test name
Test status
Simulation time 37492756 ps
CPU time 2 seconds
Started Jun 25 06:28:42 PM PDT 24
Finished Jun 25 06:28:46 PM PDT 24
Peak memory 218448 kb
Host smart-79958e31-1f50-47e8-b21b-291ea46cf70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678315184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1678315184
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.3273462140
Short name T770
Test name
Test status
Simulation time 443989941 ps
CPU time 13.25 seconds
Started Jun 25 06:28:44 PM PDT 24
Finished Jun 25 06:28:59 PM PDT 24
Peak memory 226228 kb
Host smart-c2cd3e36-5f00-4dc3-b4c8-a93ca3d590b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273462140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.3273462140
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.54152716
Short name T337
Test name
Test status
Simulation time 606306255 ps
CPU time 13.9 seconds
Started Jun 25 06:28:42 PM PDT 24
Finished Jun 25 06:28:57 PM PDT 24
Peak memory 218376 kb
Host smart-5b39233a-2541-4789-ab78-d435cb8fb86d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54152716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_dig
est.54152716
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.539504691
Short name T459
Test name
Test status
Simulation time 518645829 ps
CPU time 7.77 seconds
Started Jun 25 06:28:44 PM PDT 24
Finished Jun 25 06:28:53 PM PDT 24
Peak memory 218420 kb
Host smart-4f8ec8f4-0a4a-41f2-8d6b-b992ebe24b84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539504691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.539504691
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.593267130
Short name T674
Test name
Test status
Simulation time 201422094 ps
CPU time 8.71 seconds
Started Jun 25 06:28:42 PM PDT 24
Finished Jun 25 06:28:52 PM PDT 24
Peak memory 218460 kb
Host smart-02d70058-265f-4922-8c1e-1475808ddc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593267130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.593267130
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.89997757
Short name T806
Test name
Test status
Simulation time 49051480 ps
CPU time 3.42 seconds
Started Jun 25 06:28:45 PM PDT 24
Finished Jun 25 06:28:50 PM PDT 24
Peak memory 215196 kb
Host smart-936f54bb-85e1-4e1a-ac85-bfacee17fe9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89997757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.89997757
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.663967929
Short name T515
Test name
Test status
Simulation time 153645432 ps
CPU time 3.14 seconds
Started Jun 25 06:28:42 PM PDT 24
Finished Jun 25 06:28:46 PM PDT 24
Peak memory 222656 kb
Host smart-eae28adf-4019-402f-a478-6f337e988357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663967929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.663967929
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.2262409762
Short name T472
Test name
Test status
Simulation time 5645259117 ps
CPU time 37.81 seconds
Started Jun 25 06:28:43 PM PDT 24
Finished Jun 25 06:29:23 PM PDT 24
Peak memory 251160 kb
Host smart-5b7d4ce6-2a16-477f-bf29-065295738dbd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262409762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.2262409762
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.3721872024
Short name T188
Test name
Test status
Simulation time 40962654050 ps
CPU time 268.84 seconds
Started Jun 25 06:28:50 PM PDT 24
Finished Jun 25 06:33:21 PM PDT 24
Peak memory 343432 kb
Host smart-cdb17691-53de-4441-ae27-70bc3112d78a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3721872024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.3721872024
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2765378210
Short name T751
Test name
Test status
Simulation time 43281962 ps
CPU time 0.88 seconds
Started Jun 25 06:28:44 PM PDT 24
Finished Jun 25 06:28:47 PM PDT 24
Peak memory 213152 kb
Host smart-75149a4e-0984-44e8-999e-205d5015a9d7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765378210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.2765378210
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1567833630
Short name T547
Test name
Test status
Simulation time 24977881 ps
CPU time 1.38 seconds
Started Jun 25 06:26:37 PM PDT 24
Finished Jun 25 06:26:44 PM PDT 24
Peak memory 209224 kb
Host smart-95e6ec43-76fd-4bd0-a1e5-5abccea34744
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567833630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1567833630
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.2642180074
Short name T378
Test name
Test status
Simulation time 35163477 ps
CPU time 0.88 seconds
Started Jun 25 06:26:37 PM PDT 24
Finished Jun 25 06:26:42 PM PDT 24
Peak memory 209220 kb
Host smart-2ececb66-efb8-42fe-b47b-5e38ae68d794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642180074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2642180074
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.285629292
Short name T635
Test name
Test status
Simulation time 2732154745 ps
CPU time 17.36 seconds
Started Jun 25 06:26:38 PM PDT 24
Finished Jun 25 06:27:02 PM PDT 24
Peak memory 226304 kb
Host smart-85a5fd27-7743-47d6-9ce6-794c4f8e25ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285629292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.285629292
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.2307896367
Short name T601
Test name
Test status
Simulation time 738304961 ps
CPU time 2.61 seconds
Started Jun 25 06:26:37 PM PDT 24
Finished Jun 25 06:26:44 PM PDT 24
Peak memory 217280 kb
Host smart-4a085acb-f35a-45a1-86f6-d68ab5d07074
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307896367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.2307896367
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.2415565345
Short name T344
Test name
Test status
Simulation time 1673119171 ps
CPU time 31.02 seconds
Started Jun 25 06:26:37 PM PDT 24
Finished Jun 25 06:27:12 PM PDT 24
Peak memory 218432 kb
Host smart-b5f2543e-7f32-48ff-99c0-3ea88dfc367a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415565345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.2415565345
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.1376253344
Short name T416
Test name
Test status
Simulation time 2728919824 ps
CPU time 6.24 seconds
Started Jun 25 06:26:36 PM PDT 24
Finished Jun 25 06:26:45 PM PDT 24
Peak memory 218004 kb
Host smart-d144b4c9-f5f8-4015-b989-0595d667cc3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376253344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.1
376253344
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.2144720304
Short name T97
Test name
Test status
Simulation time 613799025 ps
CPU time 3.03 seconds
Started Jun 25 06:26:35 PM PDT 24
Finished Jun 25 06:26:42 PM PDT 24
Peak memory 221888 kb
Host smart-de186123-f536-4bef-ba28-81f481d6004a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144720304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.2144720304
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2857491264
Short name T852
Test name
Test status
Simulation time 967281591 ps
CPU time 11.77 seconds
Started Jun 25 06:26:38 PM PDT 24
Finished Jun 25 06:26:56 PM PDT 24
Peak memory 217904 kb
Host smart-dd60a384-b77b-4f0e-85e3-80406cd9f7b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857491264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2857491264
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.3521545076
Short name T762
Test name
Test status
Simulation time 361030397 ps
CPU time 10.64 seconds
Started Jun 25 06:26:39 PM PDT 24
Finished Jun 25 06:26:57 PM PDT 24
Peak memory 217908 kb
Host smart-42accaea-26e3-4c67-9da4-5d2e445ac035
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521545076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
3521545076
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2731091393
Short name T514
Test name
Test status
Simulation time 9292910170 ps
CPU time 86.65 seconds
Started Jun 25 06:26:36 PM PDT 24
Finished Jun 25 06:28:06 PM PDT 24
Peak memory 283856 kb
Host smart-8237d31a-bd7d-4165-ab98-def6c5045c2a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731091393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2731091393
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.303066384
Short name T579
Test name
Test status
Simulation time 1147152999 ps
CPU time 10.47 seconds
Started Jun 25 06:26:39 PM PDT 24
Finished Jun 25 06:26:57 PM PDT 24
Peak memory 224284 kb
Host smart-29353e90-4bd1-4f9c-9f95-51157a6164ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303066384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.303066384
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1663622493
Short name T783
Test name
Test status
Simulation time 85782765 ps
CPU time 2.15 seconds
Started Jun 25 06:26:36 PM PDT 24
Finished Jun 25 06:26:43 PM PDT 24
Peak memory 222384 kb
Host smart-72aa1ee5-3ddd-4c2a-a9fe-22d296e45436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663622493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1663622493
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.2169092123
Short name T682
Test name
Test status
Simulation time 469388853 ps
CPU time 26.03 seconds
Started Jun 25 06:26:36 PM PDT 24
Finished Jun 25 06:27:07 PM PDT 24
Peak memory 217920 kb
Host smart-e2a7c426-7b0b-4c40-b13d-5c366c5157c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169092123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.2169092123
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1848205999
Short name T89
Test name
Test status
Simulation time 561886380 ps
CPU time 27.3 seconds
Started Jun 25 06:26:47 PM PDT 24
Finished Jun 25 06:27:21 PM PDT 24
Peak memory 282252 kb
Host smart-da62e1f0-5b7f-449e-a31f-3a8aa6dc0bb0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848205999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1848205999
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.4214830418
Short name T529
Test name
Test status
Simulation time 2484414557 ps
CPU time 14.62 seconds
Started Jun 25 06:26:36 PM PDT 24
Finished Jun 25 06:26:55 PM PDT 24
Peak memory 226284 kb
Host smart-426fa948-5555-46a3-86ff-b822db538f52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214830418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.4214830418
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.1472091955
Short name T733
Test name
Test status
Simulation time 722594224 ps
CPU time 11.47 seconds
Started Jun 25 06:26:36 PM PDT 24
Finished Jun 25 06:26:51 PM PDT 24
Peak memory 218524 kb
Host smart-18473c3a-aaef-495a-ad5f-421b518855a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472091955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.1472091955
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.2187540436
Short name T527
Test name
Test status
Simulation time 1913216439 ps
CPU time 9.58 seconds
Started Jun 25 06:26:37 PM PDT 24
Finished Jun 25 06:26:51 PM PDT 24
Peak memory 218436 kb
Host smart-8ce66d44-7d19-4ee3-a54c-38a4ef6a0a62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187540436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.2
187540436
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.1941614221
Short name T26
Test name
Test status
Simulation time 2170927959 ps
CPU time 9.02 seconds
Started Jun 25 06:26:37 PM PDT 24
Finished Jun 25 06:26:52 PM PDT 24
Peak memory 218612 kb
Host smart-546f63c5-19df-4462-b060-521265658b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941614221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1941614221
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.431782006
Short name T76
Test name
Test status
Simulation time 307998338 ps
CPU time 2.66 seconds
Started Jun 25 06:26:37 PM PDT 24
Finished Jun 25 06:26:45 PM PDT 24
Peak memory 217916 kb
Host smart-506aac4d-fb00-47b2-be45-f20654a7951a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431782006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.431782006
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.2634875634
Short name T842
Test name
Test status
Simulation time 602571265 ps
CPU time 28.15 seconds
Started Jun 25 06:26:36 PM PDT 24
Finished Jun 25 06:27:08 PM PDT 24
Peak memory 251032 kb
Host smart-ef8e3680-518c-4ce1-a33a-461c8df03ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634875634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2634875634
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1886526220
Short name T778
Test name
Test status
Simulation time 222992885 ps
CPU time 7.78 seconds
Started Jun 25 06:26:36 PM PDT 24
Finished Jun 25 06:26:47 PM PDT 24
Peak memory 251044 kb
Host smart-e02d2c0a-1d12-4696-b12d-ea8a3e425c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886526220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1886526220
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.2328249292
Short name T340
Test name
Test status
Simulation time 71558838167 ps
CPU time 68.9 seconds
Started Jun 25 06:26:37 PM PDT 24
Finished Jun 25 06:27:50 PM PDT 24
Peak memory 275292 kb
Host smart-801ae64c-e28c-4db5-b208-98ff13c135cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328249292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.2328249292
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.1133116436
Short name T143
Test name
Test status
Simulation time 103617375745 ps
CPU time 534.52 seconds
Started Jun 25 06:26:36 PM PDT 24
Finished Jun 25 06:35:35 PM PDT 24
Peak memory 406028 kb
Host smart-7472cfa3-4a23-4bf4-988d-6cc181d0dd9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1133116436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.1133116436
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.4180243099
Short name T713
Test name
Test status
Simulation time 17114048 ps
CPU time 0.9 seconds
Started Jun 25 06:26:35 PM PDT 24
Finished Jun 25 06:26:40 PM PDT 24
Peak memory 212124 kb
Host smart-d75f9ec1-6171-4c5f-8cd4-ef6c19b45154
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180243099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.4180243099
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1236366847
Short name T465
Test name
Test status
Simulation time 13251377 ps
CPU time 0.88 seconds
Started Jun 25 06:28:53 PM PDT 24
Finished Jun 25 06:28:55 PM PDT 24
Peak memory 208904 kb
Host smart-caf274df-76ce-42bd-a73a-b4c90861dbbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236366847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1236366847
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.1790281838
Short name T750
Test name
Test status
Simulation time 2726288879 ps
CPU time 12.19 seconds
Started Jun 25 06:28:50 PM PDT 24
Finished Jun 25 06:29:05 PM PDT 24
Peak memory 219092 kb
Host smart-3c790fc4-a75f-4e69-b173-9e77e016cd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790281838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1790281838
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.3761527594
Short name T653
Test name
Test status
Simulation time 268581373 ps
CPU time 1.95 seconds
Started Jun 25 06:28:51 PM PDT 24
Finished Jun 25 06:28:55 PM PDT 24
Peak memory 217368 kb
Host smart-49c3443c-3b37-4b47-ac6c-ad7cdbef7302
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761527594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.3761527594
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.2432076064
Short name T654
Test name
Test status
Simulation time 30461303 ps
CPU time 1.7 seconds
Started Jun 25 06:28:51 PM PDT 24
Finished Jun 25 06:28:54 PM PDT 24
Peak memory 221904 kb
Host smart-880ce47a-0aaf-406e-8d34-16fee2b6d4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432076064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.2432076064
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.76277114
Short name T637
Test name
Test status
Simulation time 3578529010 ps
CPU time 19.44 seconds
Started Jun 25 06:28:51 PM PDT 24
Finished Jun 25 06:29:12 PM PDT 24
Peak memory 226300 kb
Host smart-78f363a7-cf15-410c-80ed-dd35977ffa7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76277114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.76277114
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.3610826527
Short name T803
Test name
Test status
Simulation time 338816111 ps
CPU time 10.72 seconds
Started Jun 25 06:28:50 PM PDT 24
Finished Jun 25 06:29:03 PM PDT 24
Peak memory 218460 kb
Host smart-00a7b212-7b0b-4991-b5fa-c507efb7fcbd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610826527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.3610826527
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.2313655581
Short name T481
Test name
Test status
Simulation time 163756077 ps
CPU time 5.98 seconds
Started Jun 25 06:28:50 PM PDT 24
Finished Jun 25 06:28:58 PM PDT 24
Peak memory 218428 kb
Host smart-f0464b1c-9764-415c-ab6d-099ad8913e61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313655581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
2313655581
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.3475614794
Short name T512
Test name
Test status
Simulation time 878285107 ps
CPU time 10.49 seconds
Started Jun 25 06:28:50 PM PDT 24
Finished Jun 25 06:29:03 PM PDT 24
Peak memory 218480 kb
Host smart-9e970c46-a758-4ac1-8921-f34ec7dd4b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475614794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3475614794
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.999714939
Short name T847
Test name
Test status
Simulation time 772069623 ps
CPU time 6.67 seconds
Started Jun 25 06:28:49 PM PDT 24
Finished Jun 25 06:28:57 PM PDT 24
Peak memory 217864 kb
Host smart-76720c95-b1fc-4efa-9cf4-9da7af469547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999714939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.999714939
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.721851437
Short name T353
Test name
Test status
Simulation time 858601280 ps
CPU time 23.03 seconds
Started Jun 25 06:28:52 PM PDT 24
Finished Jun 25 06:29:17 PM PDT 24
Peak memory 251112 kb
Host smart-f3c37f1f-d0d7-416e-a074-c12ab7c22dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721851437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.721851437
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.955191032
Short name T224
Test name
Test status
Simulation time 245500806 ps
CPU time 3.72 seconds
Started Jun 25 06:28:50 PM PDT 24
Finished Jun 25 06:28:56 PM PDT 24
Peak memory 225792 kb
Host smart-2f156586-3f28-487e-ba49-3996733b81d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955191032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.955191032
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.2417917990
Short name T844
Test name
Test status
Simulation time 3756725551 ps
CPU time 76.93 seconds
Started Jun 25 06:28:49 PM PDT 24
Finished Jun 25 06:30:08 PM PDT 24
Peak memory 268216 kb
Host smart-790a3728-ddce-4623-b5b4-331bed1bc4c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417917990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.2417917990
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.4278592402
Short name T153
Test name
Test status
Simulation time 82441782113 ps
CPU time 493.45 seconds
Started Jun 25 06:28:49 PM PDT 24
Finished Jun 25 06:37:05 PM PDT 24
Peak memory 333132 kb
Host smart-a8d67c94-9f7e-42bc-95aa-011c075e1391
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4278592402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.4278592402
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.4072524833
Short name T835
Test name
Test status
Simulation time 27646663 ps
CPU time 0.95 seconds
Started Jun 25 06:28:45 PM PDT 24
Finished Jun 25 06:28:47 PM PDT 24
Peak memory 212012 kb
Host smart-11650b96-7a92-447c-85fb-824dd1a14a37
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072524833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.4072524833
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3597353255
Short name T10
Test name
Test status
Simulation time 11210443 ps
CPU time 1 seconds
Started Jun 25 06:29:00 PM PDT 24
Finished Jun 25 06:29:03 PM PDT 24
Peak memory 209164 kb
Host smart-5ea568f0-755c-4b14-866d-d6b00023cff6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597353255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3597353255
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.817306307
Short name T851
Test name
Test status
Simulation time 764502284 ps
CPU time 12.78 seconds
Started Jun 25 06:28:50 PM PDT 24
Finished Jun 25 06:29:05 PM PDT 24
Peak memory 218416 kb
Host smart-10141c08-aca8-4ee6-ad79-22750bf99ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817306307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.817306307
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.34599554
Short name T548
Test name
Test status
Simulation time 367887344 ps
CPU time 4.01 seconds
Started Jun 25 06:28:53 PM PDT 24
Finished Jun 25 06:28:58 PM PDT 24
Peak memory 217012 kb
Host smart-59d4315f-a4b0-4630-a51e-7e09e9f1585d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34599554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.34599554
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.2864673198
Short name T492
Test name
Test status
Simulation time 173912927 ps
CPU time 2.6 seconds
Started Jun 25 06:28:49 PM PDT 24
Finished Jun 25 06:28:54 PM PDT 24
Peak memory 222388 kb
Host smart-18bf1798-18ba-484d-8dfb-d2d6932a7738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864673198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.2864673198
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.3627546815
Short name T390
Test name
Test status
Simulation time 1688600568 ps
CPU time 12.11 seconds
Started Jun 25 06:28:58 PM PDT 24
Finished Jun 25 06:29:12 PM PDT 24
Peak memory 219084 kb
Host smart-f5d50e17-5576-4849-8e6a-c26f33fb1b3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627546815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.3627546815
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2542076094
Short name T543
Test name
Test status
Simulation time 342631831 ps
CPU time 14.8 seconds
Started Jun 25 06:28:58 PM PDT 24
Finished Jun 25 06:29:15 PM PDT 24
Peak memory 218440 kb
Host smart-99742ed2-94b3-4311-b9b3-2ca2076a667f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542076094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.2542076094
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2713599075
Short name T414
Test name
Test status
Simulation time 1212109190 ps
CPU time 11.1 seconds
Started Jun 25 06:28:58 PM PDT 24
Finished Jun 25 06:29:11 PM PDT 24
Peak memory 218420 kb
Host smart-a90212ad-5c79-4a65-9882-b616ee86dc6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713599075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
2713599075
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.542818458
Short name T412
Test name
Test status
Simulation time 1325390608 ps
CPU time 13.32 seconds
Started Jun 25 06:28:49 PM PDT 24
Finished Jun 25 06:29:04 PM PDT 24
Peak memory 218468 kb
Host smart-e50a591b-72e2-412b-b945-82699ddfe48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542818458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.542818458
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3757530798
Short name T2
Test name
Test status
Simulation time 50259075 ps
CPU time 0.98 seconds
Started Jun 25 06:28:50 PM PDT 24
Finished Jun 25 06:28:53 PM PDT 24
Peak memory 217928 kb
Host smart-b9131e9d-2d73-4385-b42c-ed226a9fbe07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757530798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3757530798
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.915016086
Short name T647
Test name
Test status
Simulation time 727256855 ps
CPU time 22.95 seconds
Started Jun 25 06:28:50 PM PDT 24
Finished Jun 25 06:29:15 PM PDT 24
Peak memory 251116 kb
Host smart-a0e96a45-b48d-4bcb-a5e3-f465dedf0132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915016086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.915016086
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.448235903
Short name T557
Test name
Test status
Simulation time 68385282 ps
CPU time 3 seconds
Started Jun 25 06:28:50 PM PDT 24
Finished Jun 25 06:28:55 PM PDT 24
Peak memory 224496 kb
Host smart-6e61e4eb-39d7-4f6a-a4de-424463567af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448235903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.448235903
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3039950274
Short name T562
Test name
Test status
Simulation time 2793046847 ps
CPU time 66.71 seconds
Started Jun 25 06:28:58 PM PDT 24
Finished Jun 25 06:30:08 PM PDT 24
Peak memory 276276 kb
Host smart-6067878f-cc67-4557-adcf-220e4b708b8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039950274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3039950274
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.537813217
Short name T867
Test name
Test status
Simulation time 13130057199 ps
CPU time 439.6 seconds
Started Jun 25 06:29:00 PM PDT 24
Finished Jun 25 06:36:22 PM PDT 24
Peak memory 278332 kb
Host smart-9aebdb06-5e94-4afc-9b93-f406f998f503
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=537813217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.537813217
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2962772546
Short name T189
Test name
Test status
Simulation time 11039661 ps
CPU time 0.83 seconds
Started Jun 25 06:28:49 PM PDT 24
Finished Jun 25 06:28:51 PM PDT 24
Peak memory 211984 kb
Host smart-046fd774-f8c6-443c-a5af-3f1aa9d06f0d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962772546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2962772546
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.264647684
Short name T790
Test name
Test status
Simulation time 37223070 ps
CPU time 1 seconds
Started Jun 25 06:28:59 PM PDT 24
Finished Jun 25 06:29:03 PM PDT 24
Peak memory 209164 kb
Host smart-3551e15e-a0c2-450c-a7a2-d28f16af7754
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264647684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.264647684
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.295745016
Short name T782
Test name
Test status
Simulation time 6731236496 ps
CPU time 11.18 seconds
Started Jun 25 06:29:01 PM PDT 24
Finished Jun 25 06:29:14 PM PDT 24
Peak memory 218668 kb
Host smart-95eb7cf0-9b86-4372-b6aa-fb2cf68ab591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295745016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.295745016
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.3641834906
Short name T787
Test name
Test status
Simulation time 592649461 ps
CPU time 7.14 seconds
Started Jun 25 06:29:01 PM PDT 24
Finished Jun 25 06:29:10 PM PDT 24
Peak memory 217348 kb
Host smart-a79bdd65-1f8e-43d9-8323-6358556aa9f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641834906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.3641834906
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.2797735927
Short name T441
Test name
Test status
Simulation time 552807267 ps
CPU time 3.46 seconds
Started Jun 25 06:28:59 PM PDT 24
Finished Jun 25 06:29:05 PM PDT 24
Peak memory 218408 kb
Host smart-1a647fe8-99d0-4349-b23a-0e1ccdd1cb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797735927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.2797735927
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.2373345144
Short name T838
Test name
Test status
Simulation time 698328040 ps
CPU time 14.44 seconds
Started Jun 25 06:28:59 PM PDT 24
Finished Jun 25 06:29:16 PM PDT 24
Peak memory 226224 kb
Host smart-c1cf66a7-57a0-41b2-a0bf-cc3f58351c29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373345144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.2373345144
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.1727521910
Short name T525
Test name
Test status
Simulation time 313666300 ps
CPU time 10.7 seconds
Started Jun 25 06:29:00 PM PDT 24
Finished Jun 25 06:29:13 PM PDT 24
Peak memory 218436 kb
Host smart-2ead0341-1e9c-43bd-8544-deb6403674ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727521910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.1727521910
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.434336437
Short name T598
Test name
Test status
Simulation time 531587305 ps
CPU time 17.69 seconds
Started Jun 25 06:29:01 PM PDT 24
Finished Jun 25 06:29:21 PM PDT 24
Peak memory 218412 kb
Host smart-0a4da589-ced8-4ec5-8fe2-d6605ef832a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434336437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.434336437
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.4282926352
Short name T550
Test name
Test status
Simulation time 442913897 ps
CPU time 15.86 seconds
Started Jun 25 06:29:02 PM PDT 24
Finished Jun 25 06:29:19 PM PDT 24
Peak memory 218488 kb
Host smart-56439f11-365f-47a1-a204-af2b53f5ce25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282926352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.4282926352
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.2591359963
Short name T75
Test name
Test status
Simulation time 101763254 ps
CPU time 3.52 seconds
Started Jun 25 06:28:58 PM PDT 24
Finished Jun 25 06:29:04 PM PDT 24
Peak memory 218032 kb
Host smart-fe8d985f-42b0-4e8b-8ab7-7ca813de317b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591359963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2591359963
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.538161675
Short name T777
Test name
Test status
Simulation time 1520319757 ps
CPU time 30.18 seconds
Started Jun 25 06:28:58 PM PDT 24
Finished Jun 25 06:29:30 PM PDT 24
Peak memory 251184 kb
Host smart-c282c3ed-94d1-4e6b-b290-ab55aaa804cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538161675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.538161675
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1145988265
Short name T87
Test name
Test status
Simulation time 73862105 ps
CPU time 6.49 seconds
Started Jun 25 06:29:03 PM PDT 24
Finished Jun 25 06:29:11 PM PDT 24
Peak memory 245120 kb
Host smart-27c90b56-0021-48fa-81a3-461d20d29317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145988265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1145988265
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.123060175
Short name T166
Test name
Test status
Simulation time 72713989388 ps
CPU time 342.58 seconds
Started Jun 25 06:29:03 PM PDT 24
Finished Jun 25 06:34:47 PM PDT 24
Peak memory 251284 kb
Host smart-2753d128-dc97-45a4-9802-a3feaef9d2b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123060175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.123060175
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.695053867
Short name T346
Test name
Test status
Simulation time 61798633 ps
CPU time 0.85 seconds
Started Jun 25 06:28:58 PM PDT 24
Finished Jun 25 06:29:01 PM PDT 24
Peak memory 212112 kb
Host smart-5b28b8c2-f274-4b10-927f-844ab930f609
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695053867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ct
rl_volatile_unlock_smoke.695053867
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3722989960
Short name T807
Test name
Test status
Simulation time 27048892 ps
CPU time 1.03 seconds
Started Jun 25 06:29:05 PM PDT 24
Finished Jun 25 06:29:08 PM PDT 24
Peak memory 209156 kb
Host smart-d42e2841-3cbe-4f36-aa0c-b1b92f7f2c3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722989960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3722989960
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3218478766
Short name T849
Test name
Test status
Simulation time 515808742 ps
CPU time 13.69 seconds
Started Jun 25 06:29:00 PM PDT 24
Finished Jun 25 06:29:16 PM PDT 24
Peak memory 218428 kb
Host smart-df362647-9edb-41c2-9c20-6e215de7f984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218478766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3218478766
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3647929980
Short name T420
Test name
Test status
Simulation time 110623951 ps
CPU time 1.98 seconds
Started Jun 25 06:29:00 PM PDT 24
Finished Jun 25 06:29:04 PM PDT 24
Peak memory 217372 kb
Host smart-86251517-f3ac-4764-843e-186a18386dd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647929980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3647929980
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2453074541
Short name T382
Test name
Test status
Simulation time 92955283 ps
CPU time 2.39 seconds
Started Jun 25 06:28:58 PM PDT 24
Finished Jun 25 06:29:03 PM PDT 24
Peak memory 222548 kb
Host smart-9c7d1be8-162c-41b8-8dfa-345059aaff1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453074541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2453074541
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1018195250
Short name T18
Test name
Test status
Simulation time 785448001 ps
CPU time 16.06 seconds
Started Jun 25 06:28:58 PM PDT 24
Finished Jun 25 06:29:16 PM PDT 24
Peak memory 219108 kb
Host smart-53646e6b-c167-487e-9047-9741433f74f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018195250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1018195250
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1465332945
Short name T318
Test name
Test status
Simulation time 2904527854 ps
CPU time 9.66 seconds
Started Jun 25 06:28:58 PM PDT 24
Finished Jun 25 06:29:10 PM PDT 24
Peak memory 218536 kb
Host smart-618c5ee6-fd63-411c-9b95-57d45b65a37c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465332945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.1465332945
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.4174383722
Short name T649
Test name
Test status
Simulation time 627618421 ps
CPU time 7.34 seconds
Started Jun 25 06:29:01 PM PDT 24
Finished Jun 25 06:29:10 PM PDT 24
Peak memory 218412 kb
Host smart-639556d7-392b-4045-b2fb-21f53ea505f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174383722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
4174383722
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.3639134610
Short name T483
Test name
Test status
Simulation time 2390044853 ps
CPU time 10.92 seconds
Started Jun 25 06:29:02 PM PDT 24
Finished Jun 25 06:29:14 PM PDT 24
Peak memory 218544 kb
Host smart-448f357b-0c2f-4a97-bbbf-67cfa5aa0172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639134610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3639134610
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.1261253874
Short name T254
Test name
Test status
Simulation time 68392019 ps
CPU time 1.96 seconds
Started Jun 25 06:29:00 PM PDT 24
Finished Jun 25 06:29:05 PM PDT 24
Peak memory 217988 kb
Host smart-d8593d7e-3c8e-460d-bb4c-2cf38250a733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261253874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1261253874
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.80824204
Short name T853
Test name
Test status
Simulation time 593428098 ps
CPU time 26.11 seconds
Started Jun 25 06:28:59 PM PDT 24
Finished Jun 25 06:29:27 PM PDT 24
Peak memory 245408 kb
Host smart-23eae4f2-af56-4f3c-8773-3a0a1039588c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80824204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.80824204
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1248790081
Short name T377
Test name
Test status
Simulation time 255072620 ps
CPU time 9.68 seconds
Started Jun 25 06:28:59 PM PDT 24
Finished Jun 25 06:29:11 PM PDT 24
Peak memory 251096 kb
Host smart-8100650d-2470-4728-a5e7-f088b8ad62c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248790081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1248790081
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.3520809470
Short name T627
Test name
Test status
Simulation time 83648651584 ps
CPU time 152.81 seconds
Started Jun 25 06:29:10 PM PDT 24
Finished Jun 25 06:31:44 PM PDT 24
Peak memory 422148 kb
Host smart-89993bf2-0a26-4028-a17f-929e3ffe17cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520809470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.3520809470
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1980574589
Short name T709
Test name
Test status
Simulation time 30152960 ps
CPU time 0.88 seconds
Started Jun 25 06:28:59 PM PDT 24
Finished Jun 25 06:29:02 PM PDT 24
Peak memory 208600 kb
Host smart-f2a40086-a67f-4a67-ab46-695840a8de46
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980574589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.1980574589
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2009385535
Short name T397
Test name
Test status
Simulation time 37075906 ps
CPU time 0.92 seconds
Started Jun 25 06:29:07 PM PDT 24
Finished Jun 25 06:29:10 PM PDT 24
Peak memory 209172 kb
Host smart-25ca82e2-c718-469f-8bc9-a111a710f12b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009385535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2009385535
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2406975025
Short name T219
Test name
Test status
Simulation time 1081945528 ps
CPU time 10.18 seconds
Started Jun 25 06:29:11 PM PDT 24
Finished Jun 25 06:29:23 PM PDT 24
Peak memory 226180 kb
Host smart-b8f13bce-9177-4ddd-8484-1cbf09a671f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406975025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2406975025
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.4070676345
Short name T659
Test name
Test status
Simulation time 1760447382 ps
CPU time 18.53 seconds
Started Jun 25 06:29:06 PM PDT 24
Finished Jun 25 06:29:26 PM PDT 24
Peak memory 217584 kb
Host smart-af92ecf0-cc70-4853-86d8-f2a561965e68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070676345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.4070676345
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.2407743789
Short name T402
Test name
Test status
Simulation time 634451398 ps
CPU time 2.99 seconds
Started Jun 25 06:29:09 PM PDT 24
Finished Jun 25 06:29:14 PM PDT 24
Peak memory 218432 kb
Host smart-540c95e8-262b-4d51-bea3-22436259d652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407743789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2407743789
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.4154346692
Short name T352
Test name
Test status
Simulation time 553963259 ps
CPU time 12.04 seconds
Started Jun 25 06:29:05 PM PDT 24
Finished Jun 25 06:29:19 PM PDT 24
Peak memory 226344 kb
Host smart-4073dc16-827c-4ae9-bd1b-701f9ad4a6dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154346692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.4154346692
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2747718435
Short name T546
Test name
Test status
Simulation time 1134931110 ps
CPU time 12.83 seconds
Started Jun 25 06:29:05 PM PDT 24
Finished Jun 25 06:29:20 PM PDT 24
Peak memory 218456 kb
Host smart-4d56cc25-8c43-4cf7-af09-39c16c6bb903
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747718435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.2747718435
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3124890244
Short name T336
Test name
Test status
Simulation time 467357562 ps
CPU time 14.83 seconds
Started Jun 25 06:29:07 PM PDT 24
Finished Jun 25 06:29:24 PM PDT 24
Peak memory 218440 kb
Host smart-1efdafc2-767b-41ff-a7cd-b9945930908f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124890244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3124890244
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.3260373892
Short name T809
Test name
Test status
Simulation time 251636534 ps
CPU time 7.34 seconds
Started Jun 25 06:29:09 PM PDT 24
Finished Jun 25 06:29:18 PM PDT 24
Peak memory 218480 kb
Host smart-c0b984b0-af48-4d9b-bb45-2b02b91cc07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260373892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3260373892
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.38420225
Short name T405
Test name
Test status
Simulation time 195546952 ps
CPU time 3.28 seconds
Started Jun 25 06:29:09 PM PDT 24
Finished Jun 25 06:29:15 PM PDT 24
Peak memory 217956 kb
Host smart-6f25d122-b062-4501-9493-fa44847658a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38420225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.38420225
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.3758241739
Short name T712
Test name
Test status
Simulation time 188618052 ps
CPU time 21.52 seconds
Started Jun 25 06:29:05 PM PDT 24
Finished Jun 25 06:29:29 PM PDT 24
Peak memory 251116 kb
Host smart-7e811102-0ed9-490a-ae08-e12d6831178d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758241739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.3758241739
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2108135774
Short name T470
Test name
Test status
Simulation time 75766637 ps
CPU time 6.49 seconds
Started Jun 25 06:29:09 PM PDT 24
Finished Jun 25 06:29:17 PM PDT 24
Peak memory 250612 kb
Host smart-78768dc6-c143-49de-9d65-9279fcf7c56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108135774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2108135774
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.2877534497
Short name T436
Test name
Test status
Simulation time 29077913353 ps
CPU time 221.34 seconds
Started Jun 25 06:29:10 PM PDT 24
Finished Jun 25 06:32:53 PM PDT 24
Peak memory 267564 kb
Host smart-27f84a3e-5b29-4346-914e-cc9fd219fb0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877534497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.2877534497
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1062699697
Short name T865
Test name
Test status
Simulation time 14871164 ps
CPU time 1 seconds
Started Jun 25 06:29:06 PM PDT 24
Finished Jun 25 06:29:09 PM PDT 24
Peak memory 212136 kb
Host smart-edbb496a-e08e-4e62-8714-60462caf723c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062699697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1062699697
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.3517389433
Short name T164
Test name
Test status
Simulation time 20683154 ps
CPU time 0.91 seconds
Started Jun 25 06:29:13 PM PDT 24
Finished Jun 25 06:29:16 PM PDT 24
Peak memory 209236 kb
Host smart-8597ecb1-e25b-4298-aa9e-fb4793c6f68e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517389433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3517389433
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3120560163
Short name T476
Test name
Test status
Simulation time 1026899070 ps
CPU time 9.81 seconds
Started Jun 25 06:29:06 PM PDT 24
Finished Jun 25 06:29:18 PM PDT 24
Peak memory 218436 kb
Host smart-df0717c8-04d9-4361-9431-6662fdeb4470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120560163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3120560163
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2889685511
Short name T718
Test name
Test status
Simulation time 1329363434 ps
CPU time 16.44 seconds
Started Jun 25 06:29:15 PM PDT 24
Finished Jun 25 06:29:34 PM PDT 24
Peak memory 217288 kb
Host smart-a5a3afe6-1778-4bb3-9369-0a3bcda4ca5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889685511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2889685511
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.4127661191
Short name T866
Test name
Test status
Simulation time 143782656 ps
CPU time 1.67 seconds
Started Jun 25 06:29:11 PM PDT 24
Finished Jun 25 06:29:14 PM PDT 24
Peak memory 218148 kb
Host smart-5e2646cd-718c-49a3-bbbb-cc9ed43ebe71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127661191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.4127661191
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.4150757433
Short name T249
Test name
Test status
Simulation time 280773336 ps
CPU time 9.44 seconds
Started Jun 25 06:29:13 PM PDT 24
Finished Jun 25 06:29:24 PM PDT 24
Peak memory 219040 kb
Host smart-7d333d20-f7a6-402d-8fdf-6c48270c8f92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150757433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.4150757433
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.2386875890
Short name T597
Test name
Test status
Simulation time 817290325 ps
CPU time 9.07 seconds
Started Jun 25 06:29:13 PM PDT 24
Finished Jun 25 06:29:24 PM PDT 24
Peak memory 218468 kb
Host smart-e3ab6e29-15f1-4ca8-8022-29d224c4c57d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386875890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.2386875890
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.207676585
Short name T594
Test name
Test status
Simulation time 1359721883 ps
CPU time 8.48 seconds
Started Jun 25 06:29:14 PM PDT 24
Finished Jun 25 06:29:25 PM PDT 24
Peak memory 218440 kb
Host smart-e3272631-9c36-4ddb-9a50-afff9eb4fd0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207676585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.207676585
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.2179832944
Short name T758
Test name
Test status
Simulation time 664837579 ps
CPU time 7.55 seconds
Started Jun 25 06:29:06 PM PDT 24
Finished Jun 25 06:29:16 PM PDT 24
Peak memory 218476 kb
Host smart-c5d4e5dc-6515-4f77-9d96-572260f06803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179832944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2179832944
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.2640194151
Short name T468
Test name
Test status
Simulation time 223178371 ps
CPU time 1.96 seconds
Started Jun 25 06:29:06 PM PDT 24
Finished Jun 25 06:29:10 PM PDT 24
Peak memory 214668 kb
Host smart-bd43bdee-505c-45fb-a737-007d3a816be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640194151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.2640194151
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.2578555361
Short name T812
Test name
Test status
Simulation time 1003234018 ps
CPU time 28.11 seconds
Started Jun 25 06:29:11 PM PDT 24
Finished Jun 25 06:29:40 PM PDT 24
Peak memory 250876 kb
Host smart-1d1a3843-e9e0-4c01-897b-b2ebbce41d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578555361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.2578555361
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.493370882
Short name T245
Test name
Test status
Simulation time 191811708 ps
CPU time 7.6 seconds
Started Jun 25 06:29:07 PM PDT 24
Finished Jun 25 06:29:16 PM PDT 24
Peak memory 251120 kb
Host smart-f625057a-0966-4352-ae5d-c16785d4e4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493370882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.493370882
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2519887099
Short name T801
Test name
Test status
Simulation time 16721004527 ps
CPU time 147.57 seconds
Started Jun 25 06:29:14 PM PDT 24
Finished Jun 25 06:31:43 PM PDT 24
Peak memory 251164 kb
Host smart-587c23f8-85a8-46d5-8aa3-926274c55083
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519887099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2519887099
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3664714910
Short name T810
Test name
Test status
Simulation time 64383250 ps
CPU time 1.15 seconds
Started Jun 25 06:29:04 PM PDT 24
Finished Jun 25 06:29:08 PM PDT 24
Peak memory 217900 kb
Host smart-7053da7c-e023-43bc-afea-21e980beee20
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664714910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.3664714910
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.514297157
Short name T679
Test name
Test status
Simulation time 26825577 ps
CPU time 1.04 seconds
Started Jun 25 06:29:13 PM PDT 24
Finished Jun 25 06:29:15 PM PDT 24
Peak memory 209140 kb
Host smart-e395d8a9-be4b-4365-bdb0-7902a1467d00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514297157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.514297157
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.3577287210
Short name T46
Test name
Test status
Simulation time 3291705442 ps
CPU time 14.73 seconds
Started Jun 25 06:29:15 PM PDT 24
Finished Jun 25 06:29:32 PM PDT 24
Peak memory 219136 kb
Host smart-f4e13228-6344-412f-939a-897fa232d6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577287210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.3577287210
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.2771147003
Short name T726
Test name
Test status
Simulation time 386049276 ps
CPU time 5.03 seconds
Started Jun 25 06:29:13 PM PDT 24
Finished Jun 25 06:29:20 PM PDT 24
Peak memory 217416 kb
Host smart-30a30960-cb54-4ab9-952a-90759879c848
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771147003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.2771147003
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.1162326627
Short name T485
Test name
Test status
Simulation time 851424453 ps
CPU time 3.27 seconds
Started Jun 25 06:29:14 PM PDT 24
Finished Jun 25 06:29:20 PM PDT 24
Peak memory 218352 kb
Host smart-b8985280-9eea-42c7-a3ef-74cb0a374a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162326627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1162326627
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.971218122
Short name T48
Test name
Test status
Simulation time 1106888464 ps
CPU time 13.79 seconds
Started Jun 25 06:29:14 PM PDT 24
Finished Jun 25 06:29:30 PM PDT 24
Peak memory 226228 kb
Host smart-de8f08c0-c78c-4a54-ae8e-2055b23326d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971218122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.971218122
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.2106117655
Short name T430
Test name
Test status
Simulation time 694501995 ps
CPU time 12.42 seconds
Started Jun 25 06:29:16 PM PDT 24
Finished Jun 25 06:29:30 PM PDT 24
Peak memory 218460 kb
Host smart-abd462c3-722f-4fda-b3d8-4fd45b9737b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106117655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.2106117655
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3731010021
Short name T729
Test name
Test status
Simulation time 723472153 ps
CPU time 14.62 seconds
Started Jun 25 06:29:14 PM PDT 24
Finished Jun 25 06:29:31 PM PDT 24
Peak memory 218436 kb
Host smart-30be7b8f-4c1e-4623-b36e-d3bacc5548e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731010021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3731010021
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.896899239
Short name T509
Test name
Test status
Simulation time 1691051181 ps
CPU time 9.5 seconds
Started Jun 25 06:29:15 PM PDT 24
Finished Jun 25 06:29:26 PM PDT 24
Peak memory 218484 kb
Host smart-d2c388dd-e636-4423-9f2a-e63038f2fc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896899239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.896899239
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.763261703
Short name T360
Test name
Test status
Simulation time 31124730 ps
CPU time 1.8 seconds
Started Jun 25 06:29:13 PM PDT 24
Finished Jun 25 06:29:17 PM PDT 24
Peak memory 217908 kb
Host smart-fb87cccf-2d6d-4064-8861-08bf5066899a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763261703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.763261703
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3169902494
Short name T215
Test name
Test status
Simulation time 264947105 ps
CPU time 26.76 seconds
Started Jun 25 06:29:12 PM PDT 24
Finished Jun 25 06:29:40 PM PDT 24
Peak memory 251128 kb
Host smart-ef7f3a7f-a541-4298-bbbc-be487c85ff67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169902494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3169902494
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.436879968
Short name T832
Test name
Test status
Simulation time 164520760 ps
CPU time 8.16 seconds
Started Jun 25 06:29:16 PM PDT 24
Finished Jun 25 06:29:26 PM PDT 24
Peak memory 251100 kb
Host smart-6655356a-3758-4c8b-b0f5-a8d270b78bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436879968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.436879968
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.3431668218
Short name T101
Test name
Test status
Simulation time 74088917935 ps
CPU time 624.91 seconds
Started Jun 25 06:29:13 PM PDT 24
Finished Jun 25 06:39:40 PM PDT 24
Peak memory 257524 kb
Host smart-68b83ecf-3714-47bc-bfe5-c08f56e52fa3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431668218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.3431668218
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.2470902985
Short name T661
Test name
Test status
Simulation time 115442620682 ps
CPU time 471.19 seconds
Started Jun 25 06:29:14 PM PDT 24
Finished Jun 25 06:37:07 PM PDT 24
Peak memory 287556 kb
Host smart-de37d675-488d-4ad0-b265-917c6b624319
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2470902985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.2470902985
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2268835811
Short name T223
Test name
Test status
Simulation time 12951334 ps
CPU time 0.86 seconds
Started Jun 25 06:29:13 PM PDT 24
Finished Jun 25 06:29:15 PM PDT 24
Peak memory 212064 kb
Host smart-e87a7fc5-4be6-42a6-b6c7-dcbc1f3e0bd3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268835811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.2268835811
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3345570200
Short name T571
Test name
Test status
Simulation time 128656658 ps
CPU time 1.13 seconds
Started Jun 25 06:29:23 PM PDT 24
Finished Jun 25 06:29:27 PM PDT 24
Peak memory 209160 kb
Host smart-62468f9e-4811-477a-a0e9-4c74c892ea2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345570200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3345570200
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2554877561
Short name T705
Test name
Test status
Simulation time 458954344 ps
CPU time 9.3 seconds
Started Jun 25 06:29:21 PM PDT 24
Finished Jun 25 06:29:32 PM PDT 24
Peak memory 218368 kb
Host smart-bd0b3559-a947-4ce2-bb12-fd5e3b2ab54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554877561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2554877561
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.2768797756
Short name T7
Test name
Test status
Simulation time 1838489364 ps
CPU time 8.64 seconds
Started Jun 25 06:29:21 PM PDT 24
Finished Jun 25 06:29:31 PM PDT 24
Peak memory 217436 kb
Host smart-b397749a-1e98-428c-83dd-5dfda3177f13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768797756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.2768797756
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2314588392
Short name T629
Test name
Test status
Simulation time 86212081 ps
CPU time 4.31 seconds
Started Jun 25 06:29:13 PM PDT 24
Finished Jun 25 06:29:19 PM PDT 24
Peak memory 218440 kb
Host smart-b6474a22-15ee-470d-8826-3ce94a4ebe23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314588392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2314588392
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.1672985476
Short name T480
Test name
Test status
Simulation time 284309146 ps
CPU time 12.37 seconds
Started Jun 25 06:29:21 PM PDT 24
Finished Jun 25 06:29:35 PM PDT 24
Peak memory 219096 kb
Host smart-beaa07f8-c3a1-44cb-b979-eb18e578de3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672985476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.1672985476
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.1438296037
Short name T695
Test name
Test status
Simulation time 809000643 ps
CPU time 8.58 seconds
Started Jun 25 06:29:21 PM PDT 24
Finished Jun 25 06:29:30 PM PDT 24
Peak memory 218452 kb
Host smart-899a7d56-6340-4938-81fb-1c683a0d6fe5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438296037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.1438296037
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.1231558394
Short name T716
Test name
Test status
Simulation time 1011830804 ps
CPU time 10.78 seconds
Started Jun 25 06:29:25 PM PDT 24
Finished Jun 25 06:29:38 PM PDT 24
Peak memory 218416 kb
Host smart-9660281c-2eda-4ad3-b5c1-076c75253b6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231558394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
1231558394
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.3151866665
Short name T660
Test name
Test status
Simulation time 2237925337 ps
CPU time 11.72 seconds
Started Jun 25 06:29:25 PM PDT 24
Finished Jun 25 06:29:39 PM PDT 24
Peak memory 218612 kb
Host smart-3d24493d-9a11-4158-959d-7a601aa0b2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151866665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3151866665
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.517983085
Short name T403
Test name
Test status
Simulation time 26897600 ps
CPU time 1.87 seconds
Started Jun 25 06:29:13 PM PDT 24
Finished Jun 25 06:29:17 PM PDT 24
Peak memory 217916 kb
Host smart-4365add5-f8bc-4685-a245-b22eebc97721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517983085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.517983085
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1025190767
Short name T506
Test name
Test status
Simulation time 985749797 ps
CPU time 23.83 seconds
Started Jun 25 06:29:14 PM PDT 24
Finished Jun 25 06:29:40 PM PDT 24
Peak memory 251052 kb
Host smart-b33b2f2f-0905-4ca4-a42d-daf574ddbee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025190767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1025190767
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.2960071298
Short name T666
Test name
Test status
Simulation time 49308574 ps
CPU time 3.18 seconds
Started Jun 25 06:29:13 PM PDT 24
Finished Jun 25 06:29:18 PM PDT 24
Peak memory 222680 kb
Host smart-e7a5c8a4-557b-43dd-97e9-1f3115f1a56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960071298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.2960071298
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.3742793472
Short name T818
Test name
Test status
Simulation time 6247244405 ps
CPU time 150.86 seconds
Started Jun 25 06:29:22 PM PDT 24
Finished Jun 25 06:31:55 PM PDT 24
Peak memory 279164 kb
Host smart-a6a76d48-a9cb-46dd-9572-36675c96224d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742793472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.3742793472
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3459780976
Short name T575
Test name
Test status
Simulation time 93396297 ps
CPU time 0.96 seconds
Started Jun 25 06:29:14 PM PDT 24
Finished Jun 25 06:29:17 PM PDT 24
Peak memory 213160 kb
Host smart-bbbaf626-68bb-49b3-8419-104f80c3c642
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459780976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3459780976
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.847488345
Short name T251
Test name
Test status
Simulation time 16117459 ps
CPU time 1.1 seconds
Started Jun 25 06:29:22 PM PDT 24
Finished Jun 25 06:29:26 PM PDT 24
Peak memory 209180 kb
Host smart-6160969b-847e-444c-b98d-72da9b9b8101
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847488345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.847488345
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2198004352
Short name T154
Test name
Test status
Simulation time 339479723 ps
CPU time 7.85 seconds
Started Jun 25 06:29:21 PM PDT 24
Finished Jun 25 06:29:30 PM PDT 24
Peak memory 218536 kb
Host smart-f6679786-18e5-4014-a3b7-8e87947ac31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198004352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2198004352
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.678236704
Short name T434
Test name
Test status
Simulation time 11864629061 ps
CPU time 6.46 seconds
Started Jun 25 06:29:22 PM PDT 24
Finished Jun 25 06:29:31 PM PDT 24
Peak memory 217948 kb
Host smart-c6f598b2-1d91-4fba-b472-85fce901c7ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678236704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.678236704
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.4163742221
Short name T309
Test name
Test status
Simulation time 952219418 ps
CPU time 3.2 seconds
Started Jun 25 06:29:23 PM PDT 24
Finished Jun 25 06:29:29 PM PDT 24
Peak memory 218344 kb
Host smart-4e306d61-b26a-44f7-a378-677336a2a2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163742221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.4163742221
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2329780243
Short name T467
Test name
Test status
Simulation time 437921886 ps
CPU time 16.59 seconds
Started Jun 25 06:29:24 PM PDT 24
Finished Jun 25 06:29:43 PM PDT 24
Peak memory 218460 kb
Host smart-3637029b-aee5-46db-aa44-19770fab1a3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329780243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.2329780243
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.428895401
Short name T313
Test name
Test status
Simulation time 333526794 ps
CPU time 9.35 seconds
Started Jun 25 06:29:23 PM PDT 24
Finished Jun 25 06:29:34 PM PDT 24
Peak memory 218420 kb
Host smart-208c61b4-f1bc-4732-895d-04114042aa20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428895401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.428895401
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2581852673
Short name T29
Test name
Test status
Simulation time 210929908 ps
CPU time 9.08 seconds
Started Jun 25 06:29:20 PM PDT 24
Finished Jun 25 06:29:30 PM PDT 24
Peak memory 218488 kb
Host smart-bd5f2ba5-cc87-4511-92cd-ef2ab10fe700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581852673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2581852673
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.522129197
Short name T861
Test name
Test status
Simulation time 775773494 ps
CPU time 3.16 seconds
Started Jun 25 06:29:20 PM PDT 24
Finished Jun 25 06:29:24 PM PDT 24
Peak memory 217932 kb
Host smart-5b6e15ce-5846-44b7-877f-c85ad69e3450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522129197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.522129197
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3587370972
Short name T338
Test name
Test status
Simulation time 360373384 ps
CPU time 32.58 seconds
Started Jun 25 06:29:21 PM PDT 24
Finished Jun 25 06:29:55 PM PDT 24
Peak memory 251248 kb
Host smart-5fc1792b-c7b7-497e-a003-869843688710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587370972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3587370972
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.193145006
Short name T526
Test name
Test status
Simulation time 568097254 ps
CPU time 8.57 seconds
Started Jun 25 06:29:19 PM PDT 24
Finished Jun 25 06:29:29 PM PDT 24
Peak memory 244828 kb
Host smart-a2649646-142d-4bf4-9a5d-ef05520c7833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193145006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.193145006
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.500233431
Short name T440
Test name
Test status
Simulation time 11259966680 ps
CPU time 412.07 seconds
Started Jun 25 06:29:21 PM PDT 24
Finished Jun 25 06:36:16 PM PDT 24
Peak memory 272384 kb
Host smart-d12ba0e6-c044-40cb-a504-d3c7a2c1e805
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500233431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.500233431
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2178060836
Short name T724
Test name
Test status
Simulation time 17124620 ps
CPU time 0.87 seconds
Started Jun 25 06:29:24 PM PDT 24
Finished Jun 25 06:29:28 PM PDT 24
Peak memory 212088 kb
Host smart-ab34eb53-e09c-4f24-b0ba-d674bbacaa4a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178060836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.2178060836
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.197850131
Short name T207
Test name
Test status
Simulation time 36148646 ps
CPU time 1.17 seconds
Started Jun 25 06:29:29 PM PDT 24
Finished Jun 25 06:29:33 PM PDT 24
Peak memory 209160 kb
Host smart-70b6d1ea-8933-427f-b207-f5d2b27da7f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197850131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.197850131
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.1619422397
Short name T738
Test name
Test status
Simulation time 405446536 ps
CPU time 13.8 seconds
Started Jun 25 06:29:20 PM PDT 24
Finished Jun 25 06:29:35 PM PDT 24
Peak memory 226232 kb
Host smart-40b702c0-1c6b-41d3-abec-34415bbdd644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619422397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1619422397
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.159346723
Short name T841
Test name
Test status
Simulation time 11678445239 ps
CPU time 6.77 seconds
Started Jun 25 06:29:22 PM PDT 24
Finished Jun 25 06:29:31 PM PDT 24
Peak memory 217948 kb
Host smart-dad7e09a-7311-422d-9a8f-9adbba0c0360
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159346723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.159346723
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.1728743820
Short name T796
Test name
Test status
Simulation time 62250242 ps
CPU time 1.55 seconds
Started Jun 25 06:29:23 PM PDT 24
Finished Jun 25 06:29:27 PM PDT 24
Peak memory 218392 kb
Host smart-b2b97f73-f848-4025-9022-698181996219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728743820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1728743820
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.554551624
Short name T393
Test name
Test status
Simulation time 433897984 ps
CPU time 13.43 seconds
Started Jun 25 06:29:22 PM PDT 24
Finished Jun 25 06:29:38 PM PDT 24
Peak memory 226172 kb
Host smart-1ac70c57-4191-468f-8afd-08998d8974c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554551624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.554551624
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.307770981
Short name T580
Test name
Test status
Simulation time 2425298648 ps
CPU time 19.1 seconds
Started Jun 25 06:29:21 PM PDT 24
Finished Jun 25 06:29:42 PM PDT 24
Peak memory 219148 kb
Host smart-c4eccdb5-d535-498d-8ce4-a0f5a419dec9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307770981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.307770981
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2805302513
Short name T355
Test name
Test status
Simulation time 6217746278 ps
CPU time 15.64 seconds
Started Jun 25 06:29:21 PM PDT 24
Finished Jun 25 06:29:39 PM PDT 24
Peak memory 218480 kb
Host smart-11da80de-23be-42e3-b04c-323228677b57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805302513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2805302513
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.1725361620
Short name T699
Test name
Test status
Simulation time 735612769 ps
CPU time 8.36 seconds
Started Jun 25 06:29:23 PM PDT 24
Finished Jun 25 06:29:34 PM PDT 24
Peak memory 218520 kb
Host smart-0a625f94-759d-4acf-9f32-8d4d01227057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725361620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.1725361620
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.3511873427
Short name T162
Test name
Test status
Simulation time 16207400 ps
CPU time 1.47 seconds
Started Jun 25 06:29:23 PM PDT 24
Finished Jun 25 06:29:27 PM PDT 24
Peak memory 213932 kb
Host smart-1b26818f-522a-47c7-850d-a01b881d2db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511873427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3511873427
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.407100352
Short name T205
Test name
Test status
Simulation time 1565648141 ps
CPU time 31.68 seconds
Started Jun 25 06:29:25 PM PDT 24
Finished Jun 25 06:29:59 PM PDT 24
Peak memory 247876 kb
Host smart-698e2d09-0560-4afe-b0a6-7aecb76ad0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407100352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.407100352
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.968360650
Short name T498
Test name
Test status
Simulation time 287190171 ps
CPU time 3.56 seconds
Started Jun 25 06:29:23 PM PDT 24
Finished Jun 25 06:29:29 PM PDT 24
Peak memory 218420 kb
Host smart-06435b75-92d6-4ca8-ae6f-0bc09c0413dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968360650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.968360650
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.4054609823
Short name T768
Test name
Test status
Simulation time 17770476939 ps
CPU time 228.53 seconds
Started Jun 25 06:29:22 PM PDT 24
Finished Jun 25 06:33:13 PM PDT 24
Peak memory 283724 kb
Host smart-1d5848a7-c289-4144-916e-b75510070cf3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054609823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.4054609823
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1268997738
Short name T351
Test name
Test status
Simulation time 16417258 ps
CPU time 0.94 seconds
Started Jun 25 06:29:23 PM PDT 24
Finished Jun 25 06:29:26 PM PDT 24
Peak memory 213188 kb
Host smart-fa68390b-eb5d-49bf-afb3-c8eb67fc5c3c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268997738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1268997738
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.1417300178
Short name T508
Test name
Test status
Simulation time 90245605 ps
CPU time 0.89 seconds
Started Jun 25 06:26:48 PM PDT 24
Finished Jun 25 06:26:56 PM PDT 24
Peak memory 209072 kb
Host smart-8d2c4326-76a3-4f76-8c61-c99ca571b11d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417300178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.1417300178
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.2259450302
Short name T735
Test name
Test status
Simulation time 1437569570 ps
CPU time 16.54 seconds
Started Jun 25 06:26:36 PM PDT 24
Finished Jun 25 06:26:56 PM PDT 24
Peak memory 218412 kb
Host smart-ca608a94-ca8e-45e0-b619-7621dd88a5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259450302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.2259450302
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.3182596942
Short name T34
Test name
Test status
Simulation time 275619314 ps
CPU time 2.41 seconds
Started Jun 25 06:26:44 PM PDT 24
Finished Jun 25 06:26:52 PM PDT 24
Peak memory 217344 kb
Host smart-59eed3fa-28cb-4d99-ba19-f2d337ce96b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182596942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3182596942
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.2295290503
Short name T376
Test name
Test status
Simulation time 11583074148 ps
CPU time 27.28 seconds
Started Jun 25 06:26:42 PM PDT 24
Finished Jun 25 06:27:16 PM PDT 24
Peak memory 226300 kb
Host smart-e833b13e-a7a6-4c25-9208-c27e4f877808
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295290503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.2295290503
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2661728849
Short name T819
Test name
Test status
Simulation time 458610026 ps
CPU time 3.7 seconds
Started Jun 25 06:26:48 PM PDT 24
Finished Jun 25 06:26:58 PM PDT 24
Peak memory 217492 kb
Host smart-5e629f57-53b4-48db-8db2-19790e81503a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661728849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.2
661728849
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.694269516
Short name T35
Test name
Test status
Simulation time 185335537 ps
CPU time 6.73 seconds
Started Jun 25 06:26:47 PM PDT 24
Finished Jun 25 06:26:58 PM PDT 24
Peak memory 218392 kb
Host smart-3e491621-125a-43f8-bd55-9c37abe15804
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694269516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.694269516
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.953549152
Short name T869
Test name
Test status
Simulation time 3414201620 ps
CPU time 28.08 seconds
Started Jun 25 06:26:49 PM PDT 24
Finished Jun 25 06:27:24 PM PDT 24
Peak memory 217164 kb
Host smart-66d1fac2-eca0-431d-9c39-3db0e3810bff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953549152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_regwen_during_op.953549152
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.3127192909
Short name T5
Test name
Test status
Simulation time 259679715 ps
CPU time 4.7 seconds
Started Jun 25 06:26:47 PM PDT 24
Finished Jun 25 06:26:57 PM PDT 24
Peak memory 217916 kb
Host smart-b2a40f97-9179-4047-a067-42f74dc27207
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127192909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
3127192909
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3790037806
Short name T752
Test name
Test status
Simulation time 2188069043 ps
CPU time 78.05 seconds
Started Jun 25 06:26:43 PM PDT 24
Finished Jun 25 06:28:07 PM PDT 24
Peak memory 268636 kb
Host smart-27c11a0a-7044-467a-b044-a033b859aa11
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790037806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.3790037806
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1227010656
Short name T335
Test name
Test status
Simulation time 388447649 ps
CPU time 14.48 seconds
Started Jun 25 06:26:47 PM PDT 24
Finished Jun 25 06:27:06 PM PDT 24
Peak memory 251124 kb
Host smart-70561a71-49e4-4758-bcb9-f53367c9089b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227010656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1227010656
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.1403002547
Short name T860
Test name
Test status
Simulation time 577909824 ps
CPU time 4.08 seconds
Started Jun 25 06:26:37 PM PDT 24
Finished Jun 25 06:26:46 PM PDT 24
Peak memory 222540 kb
Host smart-9f128ce3-302d-4fec-81aa-a1baa5d8902c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403002547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.1403002547
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1810585861
Short name T67
Test name
Test status
Simulation time 271851902 ps
CPU time 16.21 seconds
Started Jun 25 06:26:43 PM PDT 24
Finished Jun 25 06:27:05 PM PDT 24
Peak memory 214968 kb
Host smart-70811982-3744-43bd-aea1-450e0afb513b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810585861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1810585861
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.2804657916
Short name T90
Test name
Test status
Simulation time 979715332 ps
CPU time 35.13 seconds
Started Jun 25 06:26:51 PM PDT 24
Finished Jun 25 06:27:33 PM PDT 24
Peak memory 269756 kb
Host smart-8ecc1ef1-9e8c-4d95-91d3-469b8ea496a7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804657916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2804657916
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.515370785
Short name T586
Test name
Test status
Simulation time 352475945 ps
CPU time 11.18 seconds
Started Jun 25 06:26:47 PM PDT 24
Finished Jun 25 06:27:03 PM PDT 24
Peak memory 226276 kb
Host smart-2c8e9a6b-a7a5-44fa-9d7e-897d17945ad2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515370785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.515370785
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.162146964
Short name T419
Test name
Test status
Simulation time 413630009 ps
CPU time 14.99 seconds
Started Jun 25 06:26:43 PM PDT 24
Finished Jun 25 06:27:04 PM PDT 24
Peak memory 218460 kb
Host smart-aca82d52-6ef7-44f8-8580-e3be75b7c72c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162146964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_dig
est.162146964
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.504294253
Short name T564
Test name
Test status
Simulation time 2426888626 ps
CPU time 11.54 seconds
Started Jun 25 06:26:39 PM PDT 24
Finished Jun 25 06:26:58 PM PDT 24
Peak memory 218548 kb
Host smart-7e49f187-b55a-4627-98ab-963adb12617e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504294253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.504294253
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3807408249
Short name T156
Test name
Test status
Simulation time 56546117 ps
CPU time 2.1 seconds
Started Jun 25 06:26:36 PM PDT 24
Finished Jun 25 06:26:41 PM PDT 24
Peak memory 217908 kb
Host smart-400d5cfd-4399-4e10-b25d-cbbd26f1f3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807408249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3807408249
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.659205010
Short name T361
Test name
Test status
Simulation time 1101654835 ps
CPU time 32.55 seconds
Started Jun 25 06:26:36 PM PDT 24
Finished Jun 25 06:27:13 PM PDT 24
Peak memory 251140 kb
Host smart-bd030c5a-3f7a-43dd-9c38-2a9519ee7a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659205010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.659205010
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3602534783
Short name T533
Test name
Test status
Simulation time 140070841 ps
CPU time 6.52 seconds
Started Jun 25 06:26:35 PM PDT 24
Finished Jun 25 06:26:45 PM PDT 24
Peak memory 250952 kb
Host smart-b1a12e9b-9128-4e44-9fc8-64eff87d56c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602534783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3602534783
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1249921460
Short name T663
Test name
Test status
Simulation time 37249854 ps
CPU time 0.97 seconds
Started Jun 25 06:26:37 PM PDT 24
Finished Jun 25 06:26:43 PM PDT 24
Peak memory 212188 kb
Host smart-eb3c755f-93f0-4ea1-b639-a8e2839c8438
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249921460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.1249921460
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.1910461676
Short name T240
Test name
Test status
Simulation time 60864382 ps
CPU time 1.53 seconds
Started Jun 25 06:29:29 PM PDT 24
Finished Jun 25 06:29:33 PM PDT 24
Peak memory 209168 kb
Host smart-d3a9516f-99f1-4861-98a8-9a870930cac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910461676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1910461676
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1942112530
Short name T301
Test name
Test status
Simulation time 73757491 ps
CPU time 1.31 seconds
Started Jun 25 06:29:28 PM PDT 24
Finished Jun 25 06:29:31 PM PDT 24
Peak memory 217420 kb
Host smart-18939245-3415-44b5-a37d-81abe4e06659
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942112530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1942112530
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3154356039
Short name T668
Test name
Test status
Simulation time 144896946 ps
CPU time 2.04 seconds
Started Jun 25 06:29:31 PM PDT 24
Finished Jun 25 06:29:36 PM PDT 24
Peak memory 222664 kb
Host smart-57af771c-a01f-4feb-8780-45011df44852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154356039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3154356039
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.956796318
Short name T771
Test name
Test status
Simulation time 1128510514 ps
CPU time 12.75 seconds
Started Jun 25 06:29:29 PM PDT 24
Finished Jun 25 06:29:44 PM PDT 24
Peak memory 226228 kb
Host smart-f026609e-9200-46db-9f1e-1dab9979a874
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956796318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.956796318
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2020051945
Short name T652
Test name
Test status
Simulation time 391786895 ps
CPU time 7.09 seconds
Started Jun 25 06:29:28 PM PDT 24
Finished Jun 25 06:29:38 PM PDT 24
Peak memory 218444 kb
Host smart-92810839-950c-4959-b726-ff2595c95f68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020051945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2020051945
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1008506753
Short name T607
Test name
Test status
Simulation time 210058173 ps
CPU time 9.49 seconds
Started Jun 25 06:29:30 PM PDT 24
Finished Jun 25 06:29:42 PM PDT 24
Peak memory 226264 kb
Host smart-f125d7de-30cf-46f7-b2ac-fd52abcc005d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008506753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1008506753
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.3552842166
Short name T417
Test name
Test status
Simulation time 359575465 ps
CPU time 8.64 seconds
Started Jun 25 06:29:28 PM PDT 24
Finished Jun 25 06:29:38 PM PDT 24
Peak memory 218484 kb
Host smart-9603a977-9da4-4b3c-baef-387eedf1083e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552842166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3552842166
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.4156387241
Short name T13
Test name
Test status
Simulation time 47811269 ps
CPU time 1.13 seconds
Started Jun 25 06:29:29 PM PDT 24
Finished Jun 25 06:29:33 PM PDT 24
Peak memory 212268 kb
Host smart-50398768-e4dc-4532-8e3c-c83e1c78de20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156387241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.4156387241
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.1506820510
Short name T802
Test name
Test status
Simulation time 785641318 ps
CPU time 18.96 seconds
Started Jun 25 06:29:27 PM PDT 24
Finished Jun 25 06:29:48 PM PDT 24
Peak memory 251352 kb
Host smart-d1cf046d-bd76-4656-94e7-6afd3ca0e0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506820510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.1506820510
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2894418396
Short name T496
Test name
Test status
Simulation time 57858715 ps
CPU time 7.14 seconds
Started Jun 25 06:29:27 PM PDT 24
Finished Jun 25 06:29:36 PM PDT 24
Peak memory 248668 kb
Host smart-4922fe2b-e756-42a7-b716-c90712fb008f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894418396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2894418396
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.799317972
Short name T754
Test name
Test status
Simulation time 19312617497 ps
CPU time 102.25 seconds
Started Jun 25 06:29:32 PM PDT 24
Finished Jun 25 06:31:17 PM PDT 24
Peak memory 283936 kb
Host smart-62aadfff-a186-43f2-8cec-c6c3e0fe163d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799317972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.799317972
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.447585045
Short name T475
Test name
Test status
Simulation time 13119012 ps
CPU time 1.03 seconds
Started Jun 25 06:29:32 PM PDT 24
Finished Jun 25 06:29:35 PM PDT 24
Peak memory 212204 kb
Host smart-4e1d3d00-969a-4227-be29-7dfcc4fd92af
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447585045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ct
rl_volatile_unlock_smoke.447585045
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2998292891
Short name T688
Test name
Test status
Simulation time 70866326 ps
CPU time 0.97 seconds
Started Jun 25 06:29:27 PM PDT 24
Finished Jun 25 06:29:30 PM PDT 24
Peak memory 209192 kb
Host smart-8b6ee261-cbce-47db-bd17-75374c8922b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998292891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2998292891
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2015851845
Short name T625
Test name
Test status
Simulation time 588393249 ps
CPU time 13.31 seconds
Started Jun 25 06:29:29 PM PDT 24
Finished Jun 25 06:29:46 PM PDT 24
Peak memory 218448 kb
Host smart-e9bb2ac7-80aa-437f-98fc-c537ddb792df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015851845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2015851845
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2427036566
Short name T36
Test name
Test status
Simulation time 6481843352 ps
CPU time 6.24 seconds
Started Jun 25 06:29:28 PM PDT 24
Finished Jun 25 06:29:36 PM PDT 24
Peak memory 218060 kb
Host smart-46c01946-11df-45bd-bed0-864bc139d436
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427036566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.2427036566
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.1794162363
Short name T837
Test name
Test status
Simulation time 75933957 ps
CPU time 3.47 seconds
Started Jun 25 06:29:30 PM PDT 24
Finished Jun 25 06:29:37 PM PDT 24
Peak memory 218356 kb
Host smart-58ee59d7-86f3-4042-a3d5-d1df933b66fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794162363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.1794162363
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.1904518112
Short name T697
Test name
Test status
Simulation time 699464299 ps
CPU time 15.92 seconds
Started Jun 25 06:29:28 PM PDT 24
Finished Jun 25 06:29:46 PM PDT 24
Peak memory 219264 kb
Host smart-2f2c57e9-f0bd-4a0b-ae6e-e9e6ef8a7d62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904518112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1904518112
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2366111360
Short name T289
Test name
Test status
Simulation time 3167474336 ps
CPU time 20.93 seconds
Started Jun 25 06:29:30 PM PDT 24
Finished Jun 25 06:29:54 PM PDT 24
Peak memory 218584 kb
Host smart-03983747-a2c0-4d22-a018-3b8d0fd13ef7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366111360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2366111360
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.1113273503
Short name T258
Test name
Test status
Simulation time 1291334756 ps
CPU time 12.51 seconds
Started Jun 25 06:29:28 PM PDT 24
Finished Jun 25 06:29:42 PM PDT 24
Peak memory 218444 kb
Host smart-fe1e1533-3819-4392-9af9-e276f4425ae9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113273503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
1113273503
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.3252973005
Short name T85
Test name
Test status
Simulation time 59693325 ps
CPU time 3.99 seconds
Started Jun 25 06:29:29 PM PDT 24
Finished Jun 25 06:29:36 PM PDT 24
Peak memory 217908 kb
Host smart-cd769b8d-ae4d-4782-91a1-6fb7850ec418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252973005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.3252973005
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.1623561712
Short name T566
Test name
Test status
Simulation time 1334638503 ps
CPU time 36.87 seconds
Started Jun 25 06:29:30 PM PDT 24
Finished Jun 25 06:30:10 PM PDT 24
Peak memory 251120 kb
Host smart-b3823cf4-ec80-4bd3-bfae-73c6204a2e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623561712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1623561712
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3522614150
Short name T519
Test name
Test status
Simulation time 58898834 ps
CPU time 6.76 seconds
Started Jun 25 06:29:30 PM PDT 24
Finished Jun 25 06:29:40 PM PDT 24
Peak memory 247572 kb
Host smart-f562cb7b-97bc-479a-8416-88ab0cd92dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522614150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3522614150
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1233256595
Short name T73
Test name
Test status
Simulation time 13372000864 ps
CPU time 381.29 seconds
Started Jun 25 06:29:28 PM PDT 24
Finished Jun 25 06:35:53 PM PDT 24
Peak memory 252452 kb
Host smart-66ae3115-a75d-4e12-adbd-64f4976adb5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233256595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1233256595
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.712910968
Short name T840
Test name
Test status
Simulation time 169008617 ps
CPU time 0.93 seconds
Started Jun 25 06:29:30 PM PDT 24
Finished Jun 25 06:29:34 PM PDT 24
Peak memory 213392 kb
Host smart-6ef57b0b-5b00-418a-9b3b-e50c38b46c68
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712910968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ct
rl_volatile_unlock_smoke.712910968
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1946139319
Short name T281
Test name
Test status
Simulation time 46672478 ps
CPU time 1.01 seconds
Started Jun 25 06:29:35 PM PDT 24
Finished Jun 25 06:29:39 PM PDT 24
Peak memory 209112 kb
Host smart-becb47e7-b35a-473e-87ab-621b87ef1380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946139319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1946139319
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3414596649
Short name T317
Test name
Test status
Simulation time 313009442 ps
CPU time 13.03 seconds
Started Jun 25 06:29:36 PM PDT 24
Finished Jun 25 06:29:52 PM PDT 24
Peak memory 226232 kb
Host smart-a89382db-d52b-422d-94de-52c5e51a5bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414596649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3414596649
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.1102388378
Short name T870
Test name
Test status
Simulation time 82544289 ps
CPU time 2.89 seconds
Started Jun 25 06:29:34 PM PDT 24
Finished Jun 25 06:29:39 PM PDT 24
Peak memory 217404 kb
Host smart-ffdef614-0e47-4f7a-a794-0ce003a6f4ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102388378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.1102388378
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2095766749
Short name T816
Test name
Test status
Simulation time 432213116 ps
CPU time 2.74 seconds
Started Jun 25 06:29:35 PM PDT 24
Finished Jun 25 06:29:40 PM PDT 24
Peak memory 218408 kb
Host smart-75af6dfa-b622-4527-a2ba-a02923401aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095766749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2095766749
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.785962616
Short name T449
Test name
Test status
Simulation time 915940862 ps
CPU time 14.86 seconds
Started Jun 25 06:29:36 PM PDT 24
Finished Jun 25 06:29:54 PM PDT 24
Peak memory 226248 kb
Host smart-3a7f7fd5-86bc-40f5-847d-cfc91acf42e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785962616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.785962616
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.4058700984
Short name T761
Test name
Test status
Simulation time 2437978626 ps
CPU time 10.64 seconds
Started Jun 25 06:29:36 PM PDT 24
Finished Jun 25 06:29:49 PM PDT 24
Peak memory 218520 kb
Host smart-c61e0e14-d7f0-44de-85b4-fdf912dbfbd1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058700984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.4058700984
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.149668589
Short name T235
Test name
Test status
Simulation time 513805779 ps
CPU time 8.58 seconds
Started Jun 25 06:29:36 PM PDT 24
Finished Jun 25 06:29:47 PM PDT 24
Peak memory 226236 kb
Host smart-d668f2a2-f468-4973-88b2-1670ddb344ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149668589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.149668589
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.2227800581
Short name T717
Test name
Test status
Simulation time 360890021 ps
CPU time 9.12 seconds
Started Jun 25 06:29:37 PM PDT 24
Finished Jun 25 06:29:49 PM PDT 24
Peak memory 218564 kb
Host smart-c5d8b47f-266e-476e-8b32-e7b3db7ac5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227800581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2227800581
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.4012787320
Short name T69
Test name
Test status
Simulation time 165441550 ps
CPU time 2.93 seconds
Started Jun 25 06:29:30 PM PDT 24
Finished Jun 25 06:29:36 PM PDT 24
Peak memory 214616 kb
Host smart-ce9f107a-97c0-4faf-b9e0-e17b6822dfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012787320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.4012787320
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.1816572186
Short name T32
Test name
Test status
Simulation time 219610180 ps
CPU time 26.12 seconds
Started Jun 25 06:29:35 PM PDT 24
Finished Jun 25 06:30:04 PM PDT 24
Peak memory 251100 kb
Host smart-46f1193d-9641-4434-b5a4-46c231216d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816572186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1816572186
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.2055332136
Short name T431
Test name
Test status
Simulation time 100279606 ps
CPU time 7.49 seconds
Started Jun 25 06:29:35 PM PDT 24
Finished Jun 25 06:29:46 PM PDT 24
Peak memory 251100 kb
Host smart-5548dc39-34f5-4df4-ab64-399eca7499df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055332136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2055332136
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.3957904663
Short name T78
Test name
Test status
Simulation time 28624737540 ps
CPU time 112.31 seconds
Started Jun 25 06:29:34 PM PDT 24
Finished Jun 25 06:31:29 PM PDT 24
Peak memory 246960 kb
Host smart-06cfd6bc-2a6c-4232-bf30-d8d5cc463eea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957904663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.3957904663
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2990530244
Short name T334
Test name
Test status
Simulation time 37699389 ps
CPU time 0.86 seconds
Started Jun 25 06:29:29 PM PDT 24
Finished Jun 25 06:29:33 PM PDT 24
Peak memory 212092 kb
Host smart-7cf89d89-f4ec-41cd-9931-81a2f9f304e6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990530244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2990530244
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.4275280280
Short name T293
Test name
Test status
Simulation time 43678827 ps
CPU time 1.23 seconds
Started Jun 25 06:29:35 PM PDT 24
Finished Jun 25 06:29:38 PM PDT 24
Peak memory 209240 kb
Host smart-09e2c2b0-1180-4020-97ac-3a48f8916b90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275280280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.4275280280
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.3990571109
Short name T814
Test name
Test status
Simulation time 323625504 ps
CPU time 15.78 seconds
Started Jun 25 06:29:35 PM PDT 24
Finished Jun 25 06:29:54 PM PDT 24
Peak memory 218420 kb
Host smart-e58a4c35-0dcd-41f3-b323-9f2623d50b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990571109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3990571109
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.4042831280
Short name T644
Test name
Test status
Simulation time 192022994 ps
CPU time 5.67 seconds
Started Jun 25 06:29:35 PM PDT 24
Finished Jun 25 06:29:44 PM PDT 24
Peak memory 217560 kb
Host smart-10e68826-825d-4628-ae18-4f3b6d1c8966
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042831280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.4042831280
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.233277365
Short name T640
Test name
Test status
Simulation time 554414334 ps
CPU time 3.44 seconds
Started Jun 25 06:29:35 PM PDT 24
Finished Jun 25 06:29:40 PM PDT 24
Peak memory 218404 kb
Host smart-079b43fe-00a6-45c2-8d03-79b48e59690b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233277365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.233277365
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.2303864933
Short name T825
Test name
Test status
Simulation time 294889326 ps
CPU time 10.7 seconds
Started Jun 25 06:29:35 PM PDT 24
Finished Jun 25 06:29:48 PM PDT 24
Peak memory 226248 kb
Host smart-7861eda6-ad6b-4cce-8340-d7028d842630
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303864933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2303864933
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.147084063
Short name T633
Test name
Test status
Simulation time 287877443 ps
CPU time 11.32 seconds
Started Jun 25 06:29:34 PM PDT 24
Finished Jun 25 06:29:47 PM PDT 24
Peak memory 218452 kb
Host smart-24f2a107-4f14-4930-86fb-7e0f6f36b5d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147084063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_di
gest.147084063
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2047166883
Short name T720
Test name
Test status
Simulation time 6083334919 ps
CPU time 11.9 seconds
Started Jun 25 06:29:37 PM PDT 24
Finished Jun 25 06:29:51 PM PDT 24
Peak memory 218428 kb
Host smart-dde6d906-d70c-4839-9a65-c7ce41839795
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047166883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2047166883
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.2019105142
Short name T64
Test name
Test status
Simulation time 29647934 ps
CPU time 1.91 seconds
Started Jun 25 06:29:37 PM PDT 24
Finished Jun 25 06:29:42 PM PDT 24
Peak memory 217904 kb
Host smart-18fb0379-bc8f-4719-a83d-203720644d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019105142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.2019105142
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.1588244886
Short name T532
Test name
Test status
Simulation time 291266596 ps
CPU time 27.43 seconds
Started Jun 25 06:29:35 PM PDT 24
Finished Jun 25 06:30:05 PM PDT 24
Peak memory 251112 kb
Host smart-c77e2802-acdd-47d9-b12b-df641fe49684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588244886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.1588244886
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.3814490008
Short name T478
Test name
Test status
Simulation time 191157968 ps
CPU time 6.72 seconds
Started Jun 25 06:29:34 PM PDT 24
Finished Jun 25 06:29:42 PM PDT 24
Peak memory 247352 kb
Host smart-54b8dcfc-9ebb-4199-8d5d-8475be7abff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814490008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3814490008
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.542916635
Short name T757
Test name
Test status
Simulation time 7906501802 ps
CPU time 179.91 seconds
Started Jun 25 06:29:37 PM PDT 24
Finished Jun 25 06:32:39 PM PDT 24
Peak memory 278172 kb
Host smart-31115161-729e-4128-8db8-72e775bfb50f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542916635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.542916635
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2311710040
Short name T446
Test name
Test status
Simulation time 24206006 ps
CPU time 1.03 seconds
Started Jun 25 06:29:35 PM PDT 24
Finished Jun 25 06:29:39 PM PDT 24
Peak memory 213156 kb
Host smart-10195066-8b58-4021-9a40-45c9fb804d75
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311710040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.2311710040
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1136990188
Short name T789
Test name
Test status
Simulation time 15913815 ps
CPU time 1.08 seconds
Started Jun 25 06:29:45 PM PDT 24
Finished Jun 25 06:29:47 PM PDT 24
Peak memory 209088 kb
Host smart-929f53d9-3ee0-4545-a8b8-d81698ba4983
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136990188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1136990188
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.4001409324
Short name T477
Test name
Test status
Simulation time 4431975971 ps
CPU time 10.7 seconds
Started Jun 25 06:29:43 PM PDT 24
Finished Jun 25 06:29:55 PM PDT 24
Peak memory 218560 kb
Host smart-4bac4cbe-b34b-47e6-9be8-15f043c57cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001409324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.4001409324
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.404316391
Short name T617
Test name
Test status
Simulation time 924931467 ps
CPU time 3.57 seconds
Started Jun 25 06:29:48 PM PDT 24
Finished Jun 25 06:29:52 PM PDT 24
Peak memory 217428 kb
Host smart-5265c01d-d8cb-408c-b9df-93b3dffca58c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404316391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.404316391
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2569532498
Short name T722
Test name
Test status
Simulation time 360842640 ps
CPU time 3.21 seconds
Started Jun 25 06:29:44 PM PDT 24
Finished Jun 25 06:29:49 PM PDT 24
Peak memory 222816 kb
Host smart-b426e44c-ee7a-4d25-8a86-974fa590787d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569532498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2569532498
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.3885186122
Short name T255
Test name
Test status
Simulation time 819637588 ps
CPU time 16.83 seconds
Started Jun 25 06:29:42 PM PDT 24
Finished Jun 25 06:30:00 PM PDT 24
Peak memory 219096 kb
Host smart-16524247-1c03-4dc9-9768-0b139864aaf5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885186122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3885186122
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.1681557317
Short name T745
Test name
Test status
Simulation time 966209147 ps
CPU time 8.03 seconds
Started Jun 25 06:29:43 PM PDT 24
Finished Jun 25 06:29:52 PM PDT 24
Peak memory 218400 kb
Host smart-91227a2d-fc69-4ebc-bd8b-e9eedb0b0d09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681557317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.1681557317
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1481465600
Short name T613
Test name
Test status
Simulation time 608051714 ps
CPU time 11.42 seconds
Started Jun 25 06:29:43 PM PDT 24
Finished Jun 25 06:29:56 PM PDT 24
Peak memory 218416 kb
Host smart-5d9b4233-1069-460c-aaab-a610b6732521
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481465600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1481465600
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2672961263
Short name T196
Test name
Test status
Simulation time 274954137 ps
CPU time 7.85 seconds
Started Jun 25 06:29:43 PM PDT 24
Finished Jun 25 06:29:53 PM PDT 24
Peak memory 218556 kb
Host smart-45f6619b-72a2-47c5-94ae-6904e337d799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672961263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2672961263
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.2043278127
Short name T491
Test name
Test status
Simulation time 340682908 ps
CPU time 2.11 seconds
Started Jun 25 06:29:37 PM PDT 24
Finished Jun 25 06:29:42 PM PDT 24
Peak memory 214500 kb
Host smart-5f2ff456-c00c-4bfa-890a-edfc6a330568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043278127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2043278127
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.1046968855
Short name T428
Test name
Test status
Simulation time 148633930 ps
CPU time 18.59 seconds
Started Jun 25 06:29:36 PM PDT 24
Finished Jun 25 06:29:58 PM PDT 24
Peak memory 251092 kb
Host smart-67c0ff4f-412c-426d-9deb-ac0ca2324e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046968855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.1046968855
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.1366801365
Short name T268
Test name
Test status
Simulation time 69873514 ps
CPU time 7.19 seconds
Started Jun 25 06:29:48 PM PDT 24
Finished Jun 25 06:29:56 PM PDT 24
Peak memory 247436 kb
Host smart-99764b98-740c-4b21-8993-6715d59a50cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366801365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.1366801365
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.245132479
Short name T341
Test name
Test status
Simulation time 4093284248 ps
CPU time 136.28 seconds
Started Jun 25 06:29:44 PM PDT 24
Finished Jun 25 06:32:01 PM PDT 24
Peak memory 276352 kb
Host smart-2ceaa57d-6d62-4454-8964-f6d1002739d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245132479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.245132479
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.4214281001
Short name T144
Test name
Test status
Simulation time 14617147337 ps
CPU time 197.07 seconds
Started Jun 25 06:29:44 PM PDT 24
Finished Jun 25 06:33:02 PM PDT 24
Peak memory 282100 kb
Host smart-8e518bf6-eccf-4d8b-b5aa-906c51c15740
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4214281001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.4214281001
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3538210142
Short name T98
Test name
Test status
Simulation time 24922082 ps
CPU time 0.91 seconds
Started Jun 25 06:29:34 PM PDT 24
Finished Jun 25 06:29:37 PM PDT 24
Peak memory 213040 kb
Host smart-ad59968c-cf61-489e-bcc3-75873cb30424
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538210142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3538210142
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.2563282216
Short name T815
Test name
Test status
Simulation time 52782931 ps
CPU time 0.81 seconds
Started Jun 25 06:29:46 PM PDT 24
Finished Jun 25 06:29:48 PM PDT 24
Peak memory 208920 kb
Host smart-57a0f7f7-74d9-40f2-ba1e-8979a5b27b83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563282216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2563282216
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.3264901355
Short name T826
Test name
Test status
Simulation time 1318194026 ps
CPU time 16.86 seconds
Started Jun 25 06:29:44 PM PDT 24
Finished Jun 25 06:30:02 PM PDT 24
Peak memory 218424 kb
Host smart-6c5e4992-430f-4792-9ca7-16794012adf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264901355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.3264901355
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.3900968646
Short name T539
Test name
Test status
Simulation time 484469395 ps
CPU time 7.37 seconds
Started Jun 25 06:29:43 PM PDT 24
Finished Jun 25 06:29:51 PM PDT 24
Peak memory 217516 kb
Host smart-f02cdac6-bd5f-45fc-aea3-ac3c39162390
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900968646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3900968646
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.4103406342
Short name T456
Test name
Test status
Simulation time 123446767 ps
CPU time 1.98 seconds
Started Jun 25 06:29:42 PM PDT 24
Finished Jun 25 06:29:45 PM PDT 24
Peak memory 222204 kb
Host smart-89a2364f-c4b3-4fc2-86ec-4e1bdf7acbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103406342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.4103406342
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.2901995150
Short name T471
Test name
Test status
Simulation time 1219689764 ps
CPU time 12.82 seconds
Started Jun 25 06:29:44 PM PDT 24
Finished Jun 25 06:29:58 PM PDT 24
Peak memory 226232 kb
Host smart-d9f243aa-43de-427d-91cb-a7c1d6f1615c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901995150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.2901995150
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3525624204
Short name T220
Test name
Test status
Simulation time 2874600963 ps
CPU time 25.15 seconds
Started Jun 25 06:29:46 PM PDT 24
Finished Jun 25 06:30:12 PM PDT 24
Peak memory 219260 kb
Host smart-79d18304-0b60-4e4b-a268-e2dc25105400
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525624204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3525624204
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.1809787382
Short name T834
Test name
Test status
Simulation time 675933078 ps
CPU time 8.66 seconds
Started Jun 25 06:29:44 PM PDT 24
Finished Jun 25 06:29:54 PM PDT 24
Peak memory 226224 kb
Host smart-32f05a4e-d7af-401b-9e59-90004ad78b32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809787382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
1809787382
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.922001912
Short name T797
Test name
Test status
Simulation time 688455543 ps
CPU time 8.38 seconds
Started Jun 25 06:29:46 PM PDT 24
Finished Jun 25 06:29:56 PM PDT 24
Peak memory 218440 kb
Host smart-d331fb6b-b4b0-4f62-b54a-8bd3f10006bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922001912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.922001912
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.561255968
Short name T244
Test name
Test status
Simulation time 71005990 ps
CPU time 3.7 seconds
Started Jun 25 06:29:46 PM PDT 24
Finished Jun 25 06:29:51 PM PDT 24
Peak memory 217936 kb
Host smart-b2ed9c83-781d-4486-a594-b663574c51d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561255968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.561255968
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1711683982
Short name T779
Test name
Test status
Simulation time 757145519 ps
CPU time 20.17 seconds
Started Jun 25 06:29:45 PM PDT 24
Finished Jun 25 06:30:07 PM PDT 24
Peak memory 251108 kb
Host smart-8401f571-90cf-4c8a-a211-3aaecf4b3bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711683982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1711683982
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2819135948
Short name T501
Test name
Test status
Simulation time 508278138 ps
CPU time 3.99 seconds
Started Jun 25 06:29:44 PM PDT 24
Finished Jun 25 06:29:49 PM PDT 24
Peak memory 222960 kb
Host smart-36807ebb-17cb-4c30-b692-d361b8494d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819135948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2819135948
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.1744231736
Short name T362
Test name
Test status
Simulation time 15324385739 ps
CPU time 152.34 seconds
Started Jun 25 06:29:43 PM PDT 24
Finished Jun 25 06:32:17 PM PDT 24
Peak memory 421968 kb
Host smart-881371c7-82a2-48f8-849e-ddedec9c2272
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744231736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.1744231736
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1914459399
Short name T590
Test name
Test status
Simulation time 36708319 ps
CPU time 0.86 seconds
Started Jun 25 06:29:44 PM PDT 24
Finished Jun 25 06:29:46 PM PDT 24
Peak memory 208824 kb
Host smart-2e03449a-e807-4f3a-9a2c-993322eaad6a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914459399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1914459399
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.4160166416
Short name T618
Test name
Test status
Simulation time 50218852 ps
CPU time 1.04 seconds
Started Jun 25 06:29:51 PM PDT 24
Finished Jun 25 06:29:54 PM PDT 24
Peak memory 209152 kb
Host smart-e13e47dd-a3e8-4439-bccf-80ae882755f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160166416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.4160166416
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.6178868
Short name T16
Test name
Test status
Simulation time 3235517620 ps
CPU time 14.56 seconds
Started Jun 25 06:29:53 PM PDT 24
Finished Jun 25 06:30:10 PM PDT 24
Peak memory 219128 kb
Host smart-78bb9670-3d2a-4c91-a053-75b16fcf899f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6178868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.6178868
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.4273725130
Short name T8
Test name
Test status
Simulation time 2432122395 ps
CPU time 13.19 seconds
Started Jun 25 06:29:51 PM PDT 24
Finished Jun 25 06:30:06 PM PDT 24
Peak memory 217884 kb
Host smart-127a76e6-6c66-406a-ab1a-237ed54c6a4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273725130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.4273725130
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.2392996941
Short name T651
Test name
Test status
Simulation time 96918167 ps
CPU time 2.15 seconds
Started Jun 25 06:29:50 PM PDT 24
Finished Jun 25 06:29:54 PM PDT 24
Peak memory 218420 kb
Host smart-6d47e06e-6a24-4f55-a7d4-93eb860c8f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392996941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2392996941
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.217611651
Short name T676
Test name
Test status
Simulation time 336963066 ps
CPU time 9.87 seconds
Started Jun 25 06:29:51 PM PDT 24
Finished Jun 25 06:30:03 PM PDT 24
Peak memory 219100 kb
Host smart-cfd6c21a-549d-4750-ba83-39fb5dadf655
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217611651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.217611651
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.2405541614
Short name T704
Test name
Test status
Simulation time 777953702 ps
CPU time 9.16 seconds
Started Jun 25 06:29:54 PM PDT 24
Finished Jun 25 06:30:05 PM PDT 24
Peak memory 218532 kb
Host smart-ed985fc1-01d1-4d7d-8c5c-126d670d3266
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405541614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.2405541614
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3349126338
Short name T759
Test name
Test status
Simulation time 1145922770 ps
CPU time 7.34 seconds
Started Jun 25 06:29:51 PM PDT 24
Finished Jun 25 06:30:00 PM PDT 24
Peak memory 218500 kb
Host smart-d745def6-1304-465c-a505-ad86b069f717
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349126338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3349126338
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.912821315
Short name T776
Test name
Test status
Simulation time 423736023 ps
CPU time 11.89 seconds
Started Jun 25 06:29:51 PM PDT 24
Finished Jun 25 06:30:05 PM PDT 24
Peak memory 218488 kb
Host smart-09475052-a7f3-432a-927f-1048c40fb8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912821315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.912821315
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1644664773
Short name T290
Test name
Test status
Simulation time 74151312 ps
CPU time 3 seconds
Started Jun 25 06:29:52 PM PDT 24
Finished Jun 25 06:29:57 PM PDT 24
Peak memory 215108 kb
Host smart-d76178ee-9a14-4138-9f1c-121e0e581595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644664773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1644664773
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.540779678
Short name T741
Test name
Test status
Simulation time 319112477 ps
CPU time 32.69 seconds
Started Jun 25 06:29:50 PM PDT 24
Finished Jun 25 06:30:25 PM PDT 24
Peak memory 251116 kb
Host smart-688d099a-ee87-41f1-a066-7a380b5db111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540779678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.540779678
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2896498958
Short name T614
Test name
Test status
Simulation time 73189023 ps
CPU time 8.12 seconds
Started Jun 25 06:29:51 PM PDT 24
Finished Jun 25 06:30:01 PM PDT 24
Peak memory 251148 kb
Host smart-c0e59092-a84a-44c7-939f-a24ed6901861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896498958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2896498958
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.329487317
Short name T392
Test name
Test status
Simulation time 19677982508 ps
CPU time 201.56 seconds
Started Jun 25 06:29:50 PM PDT 24
Finished Jun 25 06:33:13 PM PDT 24
Peak memory 278948 kb
Host smart-39794a0e-7c3d-47c3-ba6b-8bb316429b0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329487317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.329487317
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3866710961
Short name T638
Test name
Test status
Simulation time 14117809 ps
CPU time 1.08 seconds
Started Jun 25 06:29:55 PM PDT 24
Finished Jun 25 06:29:57 PM PDT 24
Peak memory 212136 kb
Host smart-f9d4a363-798d-45dc-ba9d-1f8a3f970908
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866710961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3866710961
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.76078894
Short name T226
Test name
Test status
Simulation time 63965433 ps
CPU time 1.01 seconds
Started Jun 25 06:30:00 PM PDT 24
Finished Jun 25 06:30:03 PM PDT 24
Peak memory 209172 kb
Host smart-cdcf29ae-4d3c-44a6-a400-b97b6a84a3b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76078894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.76078894
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.2372589569
Short name T158
Test name
Test status
Simulation time 385534365 ps
CPU time 12.09 seconds
Started Jun 25 06:29:49 PM PDT 24
Finished Jun 25 06:30:03 PM PDT 24
Peak memory 218368 kb
Host smart-d0f02ecf-7e44-49a7-bad1-ce9545ec1023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372589569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.2372589569
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.1134645788
Short name T37
Test name
Test status
Simulation time 1754900170 ps
CPU time 7.71 seconds
Started Jun 25 06:29:55 PM PDT 24
Finished Jun 25 06:30:04 PM PDT 24
Peak memory 217828 kb
Host smart-2521b342-0d19-4937-97a8-cb01e3e6fc7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134645788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.1134645788
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.1030291999
Short name T297
Test name
Test status
Simulation time 219200347 ps
CPU time 2.04 seconds
Started Jun 25 06:29:50 PM PDT 24
Finished Jun 25 06:29:54 PM PDT 24
Peak memory 218388 kb
Host smart-475bbf08-3537-4273-8273-f0fdf5772e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030291999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1030291999
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.3607997034
Short name T615
Test name
Test status
Simulation time 261049577 ps
CPU time 8.13 seconds
Started Jun 25 06:29:50 PM PDT 24
Finished Jun 25 06:30:00 PM PDT 24
Peak memory 219084 kb
Host smart-e147d37b-1edc-4fd2-a701-fdd4ad30de48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607997034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3607997034
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.363815571
Short name T678
Test name
Test status
Simulation time 2610610699 ps
CPU time 12.66 seconds
Started Jun 25 06:29:58 PM PDT 24
Finished Jun 25 06:30:12 PM PDT 24
Peak memory 218508 kb
Host smart-df9bed9a-c6d8-4bc1-bd29-9afb66a04a17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363815571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di
gest.363815571
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3180180444
Short name T217
Test name
Test status
Simulation time 1478632854 ps
CPU time 9.9 seconds
Started Jun 25 06:29:59 PM PDT 24
Finished Jun 25 06:30:10 PM PDT 24
Peak memory 218428 kb
Host smart-15c2db62-0649-4bd1-886a-e4c949ad1363
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180180444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3180180444
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.1807744798
Short name T626
Test name
Test status
Simulation time 477529568 ps
CPU time 11.23 seconds
Started Jun 25 06:29:52 PM PDT 24
Finished Jun 25 06:30:06 PM PDT 24
Peak memory 226288 kb
Host smart-a177b491-81bc-45f2-bf40-c1210a8ce0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807744798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.1807744798
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.1978678551
Short name T266
Test name
Test status
Simulation time 106080166 ps
CPU time 2.08 seconds
Started Jun 25 06:29:52 PM PDT 24
Finished Jun 25 06:29:56 PM PDT 24
Peak memory 217928 kb
Host smart-814ea4e7-1d95-495a-a6db-ecbd8f5bf702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978678551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.1978678551
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3329961483
Short name T623
Test name
Test status
Simulation time 585974513 ps
CPU time 29.9 seconds
Started Jun 25 06:29:52 PM PDT 24
Finished Jun 25 06:30:24 PM PDT 24
Peak memory 251140 kb
Host smart-f434f276-e712-468d-9bd8-c3a0c216d708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329961483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3329961483
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.166409987
Short name T747
Test name
Test status
Simulation time 909503165 ps
CPU time 7.36 seconds
Started Jun 25 06:29:51 PM PDT 24
Finished Jun 25 06:30:00 PM PDT 24
Peak memory 251148 kb
Host smart-d19fa0a0-80be-4f1c-8045-7d17057489bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166409987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.166409987
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.326631683
Short name T576
Test name
Test status
Simulation time 15649677940 ps
CPU time 102.26 seconds
Started Jun 25 06:30:04 PM PDT 24
Finished Jun 25 06:31:48 PM PDT 24
Peak memory 276396 kb
Host smart-be9f0144-e418-4a7f-90c1-6a2b0236efc6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326631683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.326631683
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2624814405
Short name T765
Test name
Test status
Simulation time 24309646 ps
CPU time 1.02 seconds
Started Jun 25 06:29:51 PM PDT 24
Finished Jun 25 06:29:54 PM PDT 24
Peak memory 212084 kb
Host smart-edf63ee8-f771-4946-9143-f4b6704b571e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624814405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2624814405
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1691288145
Short name T413
Test name
Test status
Simulation time 62082373 ps
CPU time 0.9 seconds
Started Jun 25 06:30:02 PM PDT 24
Finished Jun 25 06:30:04 PM PDT 24
Peak memory 209128 kb
Host smart-ac414ad8-26fd-434a-bebe-1ce47efc0f27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691288145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1691288145
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.2316629772
Short name T799
Test name
Test status
Simulation time 3081185652 ps
CPU time 21.53 seconds
Started Jun 25 06:30:03 PM PDT 24
Finished Jun 25 06:30:27 PM PDT 24
Peak memory 219164 kb
Host smart-5fc860f4-c333-4a52-9d0b-44627ef641f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316629772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.2316629772
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.1990490377
Short name T772
Test name
Test status
Simulation time 1640754418 ps
CPU time 3.08 seconds
Started Jun 25 06:29:58 PM PDT 24
Finished Jun 25 06:30:02 PM PDT 24
Peak memory 217524 kb
Host smart-04afde58-2991-49bb-8e12-cd37fd8ac6bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990490377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.1990490377
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.52827588
Short name T621
Test name
Test status
Simulation time 54656378 ps
CPU time 2.99 seconds
Started Jun 25 06:29:59 PM PDT 24
Finished Jun 25 06:30:04 PM PDT 24
Peak memory 222640 kb
Host smart-4100122d-8ee9-401b-99dc-26724dd4ec89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52827588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.52827588
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.57414809
Short name T706
Test name
Test status
Simulation time 241576892 ps
CPU time 10.81 seconds
Started Jun 25 06:29:58 PM PDT 24
Finished Jun 25 06:30:11 PM PDT 24
Peak memory 226164 kb
Host smart-4664040d-ab91-435a-ade0-44b7f6c0429f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57414809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.57414809
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3476784768
Short name T246
Test name
Test status
Simulation time 5764442481 ps
CPU time 10.51 seconds
Started Jun 25 06:29:58 PM PDT 24
Finished Jun 25 06:30:10 PM PDT 24
Peak memory 218496 kb
Host smart-6e62fdad-3fb1-40ab-9e49-ba3169b98732
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476784768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.3476784768
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.109543153
Short name T299
Test name
Test status
Simulation time 1784484653 ps
CPU time 13.56 seconds
Started Jun 25 06:30:00 PM PDT 24
Finished Jun 25 06:30:15 PM PDT 24
Peak memory 218428 kb
Host smart-09d447fc-c819-455e-8563-9d5ed28f970b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109543153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.109543153
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.3733673829
Short name T216
Test name
Test status
Simulation time 367695172 ps
CPU time 14 seconds
Started Jun 25 06:30:00 PM PDT 24
Finished Jun 25 06:30:16 PM PDT 24
Peak memory 218504 kb
Host smart-49a50e23-bc07-4b4a-9df5-de8fda31f9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733673829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3733673829
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.1232683192
Short name T204
Test name
Test status
Simulation time 45659948 ps
CPU time 2.14 seconds
Started Jun 25 06:30:00 PM PDT 24
Finished Jun 25 06:30:05 PM PDT 24
Peak memory 214472 kb
Host smart-f1595bc5-684e-41fb-b646-e0c70fb60b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232683192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1232683192
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.4155572590
Short name T302
Test name
Test status
Simulation time 272127395 ps
CPU time 25.3 seconds
Started Jun 25 06:30:03 PM PDT 24
Finished Jun 25 06:30:30 PM PDT 24
Peak memory 251116 kb
Host smart-b850f163-6c2e-4fde-94c2-7ff3c9381bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155572590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.4155572590
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.621722029
Short name T389
Test name
Test status
Simulation time 1285928036 ps
CPU time 6.87 seconds
Started Jun 25 06:30:02 PM PDT 24
Finished Jun 25 06:30:10 PM PDT 24
Peak memory 247128 kb
Host smart-c8c57bbe-964b-483d-8189-76b6722da0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621722029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.621722029
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.2069449971
Short name T279
Test name
Test status
Simulation time 30914899361 ps
CPU time 140.29 seconds
Started Jun 25 06:30:01 PM PDT 24
Finished Jun 25 06:32:24 PM PDT 24
Peak memory 251040 kb
Host smart-71832c5d-c787-48fd-9e04-34288b5e4d9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069449971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.2069449971
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.3526926496
Short name T152
Test name
Test status
Simulation time 53150102872 ps
CPU time 613.36 seconds
Started Jun 25 06:29:59 PM PDT 24
Finished Jun 25 06:40:14 PM PDT 24
Peak memory 497144 kb
Host smart-d3ce30a9-ff96-4efa-8fc3-5579b332afc7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3526926496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.3526926496
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3058123460
Short name T518
Test name
Test status
Simulation time 19292693 ps
CPU time 0.82 seconds
Started Jun 25 06:29:59 PM PDT 24
Finished Jun 25 06:30:01 PM PDT 24
Peak memory 212148 kb
Host smart-8f2c6f71-6b30-46d6-a772-10c678f9443f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058123460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3058123460
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.379595175
Short name T708
Test name
Test status
Simulation time 97223254 ps
CPU time 1.08 seconds
Started Jun 25 06:30:05 PM PDT 24
Finished Jun 25 06:30:07 PM PDT 24
Peak memory 209192 kb
Host smart-1b34eee1-cacb-4c0b-a607-8cf8f61673f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379595175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.379595175
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2951003854
Short name T457
Test name
Test status
Simulation time 1546509341 ps
CPU time 12.79 seconds
Started Jun 25 06:30:00 PM PDT 24
Finished Jun 25 06:30:15 PM PDT 24
Peak memory 226228 kb
Host smart-e4e2ea56-8bae-4d6c-aed4-a53e04aabf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951003854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2951003854
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.552100248
Short name T33
Test name
Test status
Simulation time 128114663 ps
CPU time 1.24 seconds
Started Jun 25 06:30:00 PM PDT 24
Finished Jun 25 06:30:04 PM PDT 24
Peak memory 217352 kb
Host smart-4b212fc4-ce31-479f-b3be-559d1b3c4e16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552100248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.552100248
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.2901300127
Short name T148
Test name
Test status
Simulation time 35044955 ps
CPU time 1.79 seconds
Started Jun 25 06:29:59 PM PDT 24
Finished Jun 25 06:30:03 PM PDT 24
Peak memory 218432 kb
Host smart-995f12da-d116-47f6-a576-5d303a0cf77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901300127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.2901300127
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.1420733309
Short name T19
Test name
Test status
Simulation time 1455630439 ps
CPU time 17.74 seconds
Started Jun 25 06:29:58 PM PDT 24
Finished Jun 25 06:30:17 PM PDT 24
Peak memory 219184 kb
Host smart-37bf0396-a3b1-4108-b0e6-f71d3e6a4a5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420733309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.1420733309
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.907955949
Short name T854
Test name
Test status
Simulation time 435435544 ps
CPU time 7.82 seconds
Started Jun 25 06:29:58 PM PDT 24
Finished Jun 25 06:30:07 PM PDT 24
Peak memory 218560 kb
Host smart-d01d1098-6c9f-4dca-ac69-a68870f614d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907955949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_di
gest.907955949
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.304069111
Short name T558
Test name
Test status
Simulation time 391278098 ps
CPU time 10.17 seconds
Started Jun 25 06:30:02 PM PDT 24
Finished Jun 25 06:30:14 PM PDT 24
Peak memory 218428 kb
Host smart-47ce9ff2-2246-4d00-8acf-1dc85f379d07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304069111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.304069111
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.1476586939
Short name T603
Test name
Test status
Simulation time 1000865345 ps
CPU time 11.16 seconds
Started Jun 25 06:30:00 PM PDT 24
Finished Jun 25 06:30:14 PM PDT 24
Peak memory 218556 kb
Host smart-9322565f-c3e0-43d7-9b45-14cc8f920af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476586939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.1476586939
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.4166604119
Short name T602
Test name
Test status
Simulation time 29035507 ps
CPU time 2.32 seconds
Started Jun 25 06:29:59 PM PDT 24
Finished Jun 25 06:30:04 PM PDT 24
Peak memory 214712 kb
Host smart-dd1f30bd-dd8c-4821-846d-f6035e706195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166604119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.4166604119
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.80170775
Short name T228
Test name
Test status
Simulation time 1144122579 ps
CPU time 31.87 seconds
Started Jun 25 06:30:03 PM PDT 24
Finished Jun 25 06:30:37 PM PDT 24
Peak memory 251116 kb
Host smart-de7b28dd-b72c-4458-b02a-c2f9c2dc7c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80170775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.80170775
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.3979580184
Short name T568
Test name
Test status
Simulation time 72810230 ps
CPU time 7.18 seconds
Started Jun 25 06:29:59 PM PDT 24
Finished Jun 25 06:30:08 PM PDT 24
Peak memory 250540 kb
Host smart-b8992ef1-bc8d-4303-a510-cf43752b78d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979580184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3979580184
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3793680096
Short name T710
Test name
Test status
Simulation time 11531092930 ps
CPU time 177.88 seconds
Started Jun 25 06:30:08 PM PDT 24
Finished Jun 25 06:33:07 PM PDT 24
Peak memory 226284 kb
Host smart-b3affc82-98d6-47ca-8fdd-b313e4e3ad0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793680096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3793680096
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.2221570522
Short name T141
Test name
Test status
Simulation time 12490951840 ps
CPU time 484.1 seconds
Started Jun 25 06:30:09 PM PDT 24
Finished Jun 25 06:38:15 PM PDT 24
Peak memory 284056 kb
Host smart-af9b1be4-2b39-47d9-bf1e-c6cb4a60d119
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2221570522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.2221570522
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2292752329
Short name T743
Test name
Test status
Simulation time 78740674 ps
CPU time 0.98 seconds
Started Jun 25 06:29:59 PM PDT 24
Finished Jun 25 06:30:02 PM PDT 24
Peak memory 212104 kb
Host smart-5b0664df-b33c-4fa7-8e88-8384e757f902
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292752329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.2292752329
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.486080466
Short name T454
Test name
Test status
Simulation time 89876186 ps
CPU time 1.29 seconds
Started Jun 25 06:26:49 PM PDT 24
Finished Jun 25 06:26:58 PM PDT 24
Peak memory 208388 kb
Host smart-44196269-c986-4909-8b6e-a02dc46b032c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486080466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.486080466
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.823497987
Short name T151
Test name
Test status
Simulation time 33768869 ps
CPU time 0.8 seconds
Started Jun 25 06:26:42 PM PDT 24
Finished Jun 25 06:26:49 PM PDT 24
Peak memory 209176 kb
Host smart-c7cb5edf-e667-4143-8219-45c9a9bf8414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823497987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.823497987
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.2171340821
Short name T243
Test name
Test status
Simulation time 220316750 ps
CPU time 10.76 seconds
Started Jun 25 06:26:43 PM PDT 24
Finished Jun 25 06:27:00 PM PDT 24
Peak memory 218440 kb
Host smart-1ddc1d25-043d-4b49-953a-eedba1dc9b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171340821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.2171340821
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2252527131
Short name T845
Test name
Test status
Simulation time 346870132 ps
CPU time 9.51 seconds
Started Jun 25 06:26:46 PM PDT 24
Finished Jun 25 06:27:01 PM PDT 24
Peak memory 217820 kb
Host smart-46476645-037e-4c20-a632-c497c7f278c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252527131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2252527131
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.968631849
Short name T315
Test name
Test status
Simulation time 11543712636 ps
CPU time 36.24 seconds
Started Jun 25 06:26:44 PM PDT 24
Finished Jun 25 06:27:26 PM PDT 24
Peak memory 226308 kb
Host smart-0c644993-1ae4-4a33-b303-39f0147dec0d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968631849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.968631849
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.3828842786
Short name T630
Test name
Test status
Simulation time 1321460629 ps
CPU time 12.15 seconds
Started Jun 25 06:26:49 PM PDT 24
Finished Jun 25 06:27:09 PM PDT 24
Peak memory 217672 kb
Host smart-f849ccbb-9be8-492f-b9e3-b24360e7dff5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828842786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.3
828842786
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.319554651
Short name T149
Test name
Test status
Simulation time 1821470119 ps
CPU time 12.45 seconds
Started Jun 25 06:26:43 PM PDT 24
Finished Jun 25 06:27:01 PM PDT 24
Peak memory 219092 kb
Host smart-9634f055-8149-4a3b-9674-22a5fdbd880a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319554651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
prog_failure.319554651
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1428834146
Short name T554
Test name
Test status
Simulation time 1199379524 ps
CPU time 16.88 seconds
Started Jun 25 06:26:49 PM PDT 24
Finished Jun 25 06:27:13 PM PDT 24
Peak memory 217916 kb
Host smart-f34f8962-d7c9-41a1-9402-f796580e34cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428834146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.1428834146
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1621378016
Short name T328
Test name
Test status
Simulation time 143227681 ps
CPU time 3.1 seconds
Started Jun 25 06:26:46 PM PDT 24
Finished Jun 25 06:26:54 PM PDT 24
Peak memory 218032 kb
Host smart-68c49f4a-2a2c-4fd0-b625-459c5532062a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621378016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1621378016
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2739632898
Short name T494
Test name
Test status
Simulation time 1832963910 ps
CPU time 55.68 seconds
Started Jun 25 06:26:46 PM PDT 24
Finished Jun 25 06:27:46 PM PDT 24
Peak memory 268212 kb
Host smart-14772d84-dc67-4329-be80-25807f576f28
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739632898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2739632898
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.4071946896
Short name T225
Test name
Test status
Simulation time 356003567 ps
CPU time 10.46 seconds
Started Jun 25 06:26:49 PM PDT 24
Finished Jun 25 06:27:06 PM PDT 24
Peak memory 243068 kb
Host smart-3facc069-8793-49a8-8b3d-d74ee6320c66
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071946896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.4071946896
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.652517253
Short name T20
Test name
Test status
Simulation time 40741578 ps
CPU time 2.57 seconds
Started Jun 25 06:26:48 PM PDT 24
Finished Jun 25 06:26:57 PM PDT 24
Peak memory 218364 kb
Host smart-edabf9de-42ce-4f18-a2fd-0df14b1b2ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652517253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.652517253
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.4270828532
Short name T30
Test name
Test status
Simulation time 387628990 ps
CPU time 22.51 seconds
Started Jun 25 06:26:43 PM PDT 24
Finished Jun 25 06:27:11 PM PDT 24
Peak memory 217924 kb
Host smart-8b99b599-8020-4244-97eb-47c0fb152e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270828532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.4270828532
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.3853239231
Short name T859
Test name
Test status
Simulation time 254059430 ps
CPU time 13.82 seconds
Started Jun 25 06:26:42 PM PDT 24
Finished Jun 25 06:27:02 PM PDT 24
Peak memory 218424 kb
Host smart-8641aa87-d107-40fc-8bff-f1ecf16a956a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853239231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.3853239231
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2782342787
Short name T794
Test name
Test status
Simulation time 309167463 ps
CPU time 13.93 seconds
Started Jun 25 06:26:42 PM PDT 24
Finished Jun 25 06:27:02 PM PDT 24
Peak memory 218440 kb
Host smart-ca491143-c5d9-4a53-9ca5-ebd4c1e08ccc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782342787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.2782342787
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.1676631794
Short name T401
Test name
Test status
Simulation time 1565810703 ps
CPU time 9.28 seconds
Started Jun 25 06:26:42 PM PDT 24
Finished Jun 25 06:26:57 PM PDT 24
Peak memory 226164 kb
Host smart-f0c30757-5f8e-47da-b117-a51ca3e87501
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676631794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.1
676631794
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.4265734023
Short name T233
Test name
Test status
Simulation time 3164089551 ps
CPU time 13.44 seconds
Started Jun 25 06:26:47 PM PDT 24
Finished Jun 25 06:27:06 PM PDT 24
Peak memory 218504 kb
Host smart-dd8ce822-ef20-4079-9c82-94fc776160e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265734023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.4265734023
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2926701005
Short name T732
Test name
Test status
Simulation time 231247274 ps
CPU time 2.47 seconds
Started Jun 25 06:26:45 PM PDT 24
Finished Jun 25 06:26:53 PM PDT 24
Peak memory 214508 kb
Host smart-bbbf8a03-d8c5-4669-87d4-c72fde088dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926701005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2926701005
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.2450399451
Short name T385
Test name
Test status
Simulation time 251600242 ps
CPU time 26.45 seconds
Started Jun 25 06:26:47 PM PDT 24
Finished Jun 25 06:27:19 PM PDT 24
Peak memory 251068 kb
Host smart-7b89c887-798d-47ab-ad3a-2153ce09efde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450399451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.2450399451
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.3743275714
Short name T505
Test name
Test status
Simulation time 60953417 ps
CPU time 12.59 seconds
Started Jun 25 06:26:48 PM PDT 24
Finished Jun 25 06:27:07 PM PDT 24
Peak memory 251236 kb
Host smart-d1d1b789-4dc1-41e1-9734-8901ad197a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743275714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.3743275714
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.2670024834
Short name T406
Test name
Test status
Simulation time 6815412037 ps
CPU time 223.97 seconds
Started Jun 25 06:26:43 PM PDT 24
Finished Jun 25 06:30:33 PM PDT 24
Peak memory 251156 kb
Host smart-1a08b30f-515f-4c7a-9546-2ed0651e0537
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670024834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.2670024834
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.3716844664
Short name T165
Test name
Test status
Simulation time 106552617269 ps
CPU time 916.54 seconds
Started Jun 25 06:26:47 PM PDT 24
Finished Jun 25 06:42:09 PM PDT 24
Peak memory 284156 kb
Host smart-3c5173af-8d1c-44a2-b970-2eb903a47422
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3716844664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.3716844664
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1232858413
Short name T455
Test name
Test status
Simulation time 36417297 ps
CPU time 0.96 seconds
Started Jun 25 06:26:47 PM PDT 24
Finished Jun 25 06:26:54 PM PDT 24
Peak memory 212000 kb
Host smart-32d107e1-d470-41b7-859a-f2c08cfb825b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232858413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.1232858413
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.2179407055
Short name T12
Test name
Test status
Simulation time 92885729 ps
CPU time 0.92 seconds
Started Jun 25 06:26:48 PM PDT 24
Finished Jun 25 06:26:55 PM PDT 24
Peak memory 209220 kb
Host smart-ac516cd4-f2e8-4a22-bb35-af55e8df84f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179407055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2179407055
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.877026720
Short name T683
Test name
Test status
Simulation time 52920553 ps
CPU time 0.83 seconds
Started Jun 25 06:26:43 PM PDT 24
Finished Jun 25 06:26:50 PM PDT 24
Peak memory 209144 kb
Host smart-2b17d00c-ae65-4fd4-9d5e-c9c0cba516b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877026720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.877026720
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.4040966650
Short name T829
Test name
Test status
Simulation time 540948481 ps
CPU time 9.25 seconds
Started Jun 25 06:26:43 PM PDT 24
Finished Jun 25 06:26:58 PM PDT 24
Peak memory 218396 kb
Host smart-83dd4f55-4a3a-4c03-bc28-b713b784c963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040966650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.4040966650
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1787903387
Short name T168
Test name
Test status
Simulation time 295377273 ps
CPU time 8.06 seconds
Started Jun 25 06:26:47 PM PDT 24
Finished Jun 25 06:27:01 PM PDT 24
Peak memory 217324 kb
Host smart-ccd93476-016b-4b18-a6b4-5d85c16c188d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787903387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1787903387
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.3004583185
Short name T648
Test name
Test status
Simulation time 2052610862 ps
CPU time 61.84 seconds
Started Jun 25 06:26:48 PM PDT 24
Finished Jun 25 06:27:56 PM PDT 24
Peak memory 218412 kb
Host smart-ed3f3bbc-259f-46e6-bce4-dd3698a9b226
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004583185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.3004583185
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.2373602549
Short name T63
Test name
Test status
Simulation time 6184749506 ps
CPU time 5.97 seconds
Started Jun 25 06:26:51 PM PDT 24
Finished Jun 25 06:27:04 PM PDT 24
Peak memory 217928 kb
Host smart-a9906f64-b220-4258-85a2-d080b9f04cf1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373602549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.2
373602549
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3889024086
Short name T263
Test name
Test status
Simulation time 61706607 ps
CPU time 2.6 seconds
Started Jun 25 06:26:43 PM PDT 24
Finished Jun 25 06:26:51 PM PDT 24
Peak memory 221668 kb
Host smart-f3d7a427-1426-44ff-9085-a93df369cfa9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889024086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.3889024086
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3010621291
Short name T756
Test name
Test status
Simulation time 4133414105 ps
CPU time 17.27 seconds
Started Jun 25 06:26:44 PM PDT 24
Finished Jun 25 06:27:06 PM PDT 24
Peak memory 217972 kb
Host smart-6de3fe21-1660-4456-ba5b-83282b1871ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010621291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.3010621291
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.765817791
Short name T677
Test name
Test status
Simulation time 2295954638 ps
CPU time 7.93 seconds
Started Jun 25 06:26:52 PM PDT 24
Finished Jun 25 06:27:07 PM PDT 24
Peak memory 217912 kb
Host smart-7e6e6d48-c040-4aa9-bad3-b156c8f84f97
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765817791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.765817791
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2788494151
Short name T439
Test name
Test status
Simulation time 6886906950 ps
CPU time 125.79 seconds
Started Jun 25 06:26:48 PM PDT 24
Finished Jun 25 06:29:00 PM PDT 24
Peak memory 283872 kb
Host smart-59df4495-fbf3-42df-80f2-e1e4df2f8bd1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788494151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.2788494151
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1513329565
Short name T157
Test name
Test status
Simulation time 1567154106 ps
CPU time 27.13 seconds
Started Jun 25 06:26:45 PM PDT 24
Finished Jun 25 06:27:17 PM PDT 24
Peak memory 247536 kb
Host smart-4a1068cf-8d8f-486b-ac21-3a9e2c64df79
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513329565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1513329565
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.2982759470
Short name T730
Test name
Test status
Simulation time 122801594 ps
CPU time 2.74 seconds
Started Jun 25 06:26:42 PM PDT 24
Finished Jun 25 06:26:51 PM PDT 24
Peak memory 218476 kb
Host smart-84748415-78ed-4330-8a99-f31a58c0e550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982759470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.2982759470
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3980389096
Short name T686
Test name
Test status
Simulation time 336315079 ps
CPU time 13.12 seconds
Started Jun 25 06:26:47 PM PDT 24
Finished Jun 25 06:27:05 PM PDT 24
Peak memory 214952 kb
Host smart-cea354d7-c601-4843-909c-dbc749915c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980389096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3980389096
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.988619093
Short name T504
Test name
Test status
Simulation time 1182620835 ps
CPU time 14.99 seconds
Started Jun 25 06:26:51 PM PDT 24
Finished Jun 25 06:27:13 PM PDT 24
Peak memory 226108 kb
Host smart-785f9ea8-c4e9-4596-ad0c-060db04859d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988619093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.988619093
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.3284889925
Short name T646
Test name
Test status
Simulation time 1491322933 ps
CPU time 14.22 seconds
Started Jun 25 06:26:47 PM PDT 24
Finished Jun 25 06:27:08 PM PDT 24
Peak memory 218476 kb
Host smart-40b5f67c-090c-4af8-9862-bc5859f15f28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284889925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.3284889925
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2168605841
Short name T399
Test name
Test status
Simulation time 1106360639 ps
CPU time 10.46 seconds
Started Jun 25 06:26:49 PM PDT 24
Finished Jun 25 06:27:06 PM PDT 24
Peak memory 218468 kb
Host smart-e3f321bd-bf1b-4e27-9196-bb0a2a7c6826
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168605841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
168605841
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.3197101257
Short name T473
Test name
Test status
Simulation time 674984861 ps
CPU time 7.95 seconds
Started Jun 25 06:26:52 PM PDT 24
Finished Jun 25 06:27:07 PM PDT 24
Peak memory 218440 kb
Host smart-3bab1b62-7709-4143-bbd8-b928df554089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197101257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3197101257
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.4097805689
Short name T241
Test name
Test status
Simulation time 86248077 ps
CPU time 2.05 seconds
Started Jun 25 06:26:46 PM PDT 24
Finished Jun 25 06:26:53 PM PDT 24
Peak memory 214544 kb
Host smart-683b4f80-f4fa-4cc6-860e-e3d6d91818ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097805689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.4097805689
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3282726289
Short name T307
Test name
Test status
Simulation time 423400898 ps
CPU time 28.45 seconds
Started Jun 25 06:26:42 PM PDT 24
Finished Jun 25 06:27:17 PM PDT 24
Peak memory 251116 kb
Host smart-7bc97c5e-f050-4467-9a61-24f95bf371e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282726289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3282726289
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3514845853
Short name T199
Test name
Test status
Simulation time 67224018 ps
CPU time 8.72 seconds
Started Jun 25 06:26:48 PM PDT 24
Finished Jun 25 06:27:03 PM PDT 24
Peak memory 251116 kb
Host smart-79f46913-a6a7-49a7-880e-a2e3ffd2528a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514845853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3514845853
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.3932683544
Short name T650
Test name
Test status
Simulation time 4074521305 ps
CPU time 47.33 seconds
Started Jun 25 06:26:48 PM PDT 24
Finished Jun 25 06:27:42 PM PDT 24
Peak memory 251000 kb
Host smart-c799c3d1-896e-4658-9f90-943d6dc3bd1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932683544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.3932683544
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.2255752791
Short name T142
Test name
Test status
Simulation time 80860442739 ps
CPU time 419.42 seconds
Started Jun 25 06:26:51 PM PDT 24
Finished Jun 25 06:33:58 PM PDT 24
Peak memory 333188 kb
Host smart-a887020e-e127-4954-b647-43f44e1215e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2255752791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.2255752791
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1866868113
Short name T283
Test name
Test status
Simulation time 50119993 ps
CPU time 1 seconds
Started Jun 25 06:26:47 PM PDT 24
Finished Jun 25 06:26:54 PM PDT 24
Peak memory 212040 kb
Host smart-91702df6-33a9-4fa1-a095-a81fcf76bf85
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866868113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.1866868113
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.3011068073
Short name T368
Test name
Test status
Simulation time 44467812 ps
CPU time 0.93 seconds
Started Jun 25 06:26:51 PM PDT 24
Finished Jun 25 06:26:59 PM PDT 24
Peak memory 209124 kb
Host smart-75e3bc42-7b8a-412c-bdc3-8816817d0c7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011068073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.3011068073
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3447257958
Short name T517
Test name
Test status
Simulation time 17852339 ps
CPU time 0.79 seconds
Started Jun 25 06:26:50 PM PDT 24
Finished Jun 25 06:26:58 PM PDT 24
Peak memory 209168 kb
Host smart-7ca7ce2b-438b-4f6a-8935-b89c471fc097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447257958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3447257958
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.980149116
Short name T358
Test name
Test status
Simulation time 480152781 ps
CPU time 20.72 seconds
Started Jun 25 06:26:58 PM PDT 24
Finished Jun 25 06:27:23 PM PDT 24
Peak memory 218428 kb
Host smart-ebc7e6a6-5790-4efd-ae84-5b35ff0bb514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980149116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.980149116
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.3050390868
Short name T169
Test name
Test status
Simulation time 871663945 ps
CPU time 8.66 seconds
Started Jun 25 06:26:49 PM PDT 24
Finished Jun 25 06:27:05 PM PDT 24
Peak memory 217744 kb
Host smart-d38b4945-f181-43b3-963a-45cbac3ccb5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050390868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.3050390868
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2165409565
Short name T88
Test name
Test status
Simulation time 1854981971 ps
CPU time 59.42 seconds
Started Jun 25 06:26:49 PM PDT 24
Finished Jun 25 06:27:56 PM PDT 24
Peak memory 226356 kb
Host smart-f5db6d9d-6bfa-4fb6-9dca-181d1795799a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165409565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2165409565
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1180345143
Short name T774
Test name
Test status
Simulation time 5223150321 ps
CPU time 11.81 seconds
Started Jun 25 06:26:56 PM PDT 24
Finished Jun 25 06:27:14 PM PDT 24
Peak memory 219064 kb
Host smart-5e41dc3f-d601-4b60-aec3-909e648014a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180345143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1180345143
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2566083826
Short name T570
Test name
Test status
Simulation time 1152595334 ps
CPU time 17.9 seconds
Started Jun 25 06:26:49 PM PDT 24
Finished Jun 25 06:27:14 PM PDT 24
Peak memory 217920 kb
Host smart-bc5c88be-422c-4924-a57c-eb39ab872897
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566083826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.2566083826
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.4017826096
Short name T587
Test name
Test status
Simulation time 4665421636 ps
CPU time 15.04 seconds
Started Jun 25 06:26:50 PM PDT 24
Finished Jun 25 06:27:12 PM PDT 24
Peak memory 217936 kb
Host smart-ce122d3b-f74d-4599-ad19-ff1811e68e19
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017826096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
4017826096
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.3738059250
Short name T742
Test name
Test status
Simulation time 1886832607 ps
CPU time 65.66 seconds
Started Jun 25 06:26:50 PM PDT 24
Finished Jun 25 06:28:03 PM PDT 24
Peak memory 267516 kb
Host smart-9c54b047-3efd-41ed-aee0-abf7cb541b77
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738059250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.3738059250
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.4196083563
Short name T269
Test name
Test status
Simulation time 7170424395 ps
CPU time 8.51 seconds
Started Jun 25 06:26:51 PM PDT 24
Finished Jun 25 06:27:07 PM PDT 24
Peak memory 226588 kb
Host smart-d4b85e5d-6a08-4185-8438-c480568b8efa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196083563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.4196083563
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1015640111
Short name T59
Test name
Test status
Simulation time 337851839 ps
CPU time 1.95 seconds
Started Jun 25 06:26:45 PM PDT 24
Finished Jun 25 06:26:51 PM PDT 24
Peak memory 222404 kb
Host smart-248dd227-e913-4d7d-b739-699cc3620173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015640111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1015640111
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.4188340789
Short name T331
Test name
Test status
Simulation time 279828638 ps
CPU time 17.06 seconds
Started Jun 25 06:26:56 PM PDT 24
Finished Jun 25 06:27:19 PM PDT 24
Peak memory 214836 kb
Host smart-3fadc8ce-ede5-43fc-b91d-dd407510da9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188340789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.4188340789
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.360855642
Short name T398
Test name
Test status
Simulation time 229607980 ps
CPU time 8.54 seconds
Started Jun 25 06:26:48 PM PDT 24
Finished Jun 25 06:27:03 PM PDT 24
Peak memory 218440 kb
Host smart-7a382d84-c86a-4f0a-a2f6-38a9096dbd15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360855642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.360855642
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.248867219
Short name T808
Test name
Test status
Simulation time 722441403 ps
CPU time 11.5 seconds
Started Jun 25 06:26:50 PM PDT 24
Finished Jun 25 06:27:09 PM PDT 24
Peak memory 218448 kb
Host smart-c85d5c89-7b78-4086-99c2-3208abc11011
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248867219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dig
est.248867219
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2952498034
Short name T643
Test name
Test status
Simulation time 587723851 ps
CPU time 7.33 seconds
Started Jun 25 06:26:58 PM PDT 24
Finished Jun 25 06:27:10 PM PDT 24
Peak memory 226236 kb
Host smart-d846d72a-6c95-4944-81b0-258e120934d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952498034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2
952498034
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.1469237919
Short name T194
Test name
Test status
Simulation time 2199682181 ps
CPU time 8.67 seconds
Started Jun 25 06:26:50 PM PDT 24
Finished Jun 25 06:27:06 PM PDT 24
Peak memory 218552 kb
Host smart-2ea9be83-78b8-43be-a3f2-36919b0c5e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469237919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1469237919
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2518973551
Short name T79
Test name
Test status
Simulation time 81072468 ps
CPU time 2.67 seconds
Started Jun 25 06:26:46 PM PDT 24
Finished Jun 25 06:26:53 PM PDT 24
Peak memory 223036 kb
Host smart-c6a28980-b421-4785-ac25-df6b002f7089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518973551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2518973551
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1726195664
Short name T658
Test name
Test status
Simulation time 890954829 ps
CPU time 26.68 seconds
Started Jun 25 06:26:48 PM PDT 24
Finished Jun 25 06:27:21 PM PDT 24
Peak memory 251108 kb
Host smart-ef45353d-e803-433d-946b-92a4ef4b8800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726195664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1726195664
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1748433991
Short name T3
Test name
Test status
Simulation time 118262483 ps
CPU time 7.17 seconds
Started Jun 25 06:26:44 PM PDT 24
Finished Jun 25 06:26:56 PM PDT 24
Peak memory 250636 kb
Host smart-55e9feb1-1c6e-4e30-9941-34227da98eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748433991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1748433991
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.1740498114
Short name T690
Test name
Test status
Simulation time 3487127094 ps
CPU time 44.59 seconds
Started Jun 25 06:26:57 PM PDT 24
Finished Jun 25 06:27:46 PM PDT 24
Peak memory 251048 kb
Host smart-d2d643ad-661e-40d9-8bf1-9a53b4807f3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740498114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.1740498114
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3261991294
Short name T448
Test name
Test status
Simulation time 47045153 ps
CPU time 0.91 seconds
Started Jun 25 06:26:47 PM PDT 24
Finished Jun 25 06:26:53 PM PDT 24
Peak memory 212064 kb
Host smart-fb363f44-a5ca-4cff-ac34-c1a681183dab
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261991294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.3261991294
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.2566809819
Short name T321
Test name
Test status
Simulation time 102004922 ps
CPU time 1.33 seconds
Started Jun 25 06:27:04 PM PDT 24
Finished Jun 25 06:27:07 PM PDT 24
Peak memory 209220 kb
Host smart-bf962dfe-718b-489b-8d26-57049a0f01b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566809819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.2566809819
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.3578870321
Short name T396
Test name
Test status
Simulation time 1734537704 ps
CPU time 14.1 seconds
Started Jun 25 06:26:57 PM PDT 24
Finished Jun 25 06:27:17 PM PDT 24
Peak memory 226248 kb
Host smart-65d346b9-5b84-429a-8e1d-f785ad6bb0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578870321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3578870321
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.188576713
Short name T426
Test name
Test status
Simulation time 2021692028 ps
CPU time 3.7 seconds
Started Jun 25 06:26:58 PM PDT 24
Finished Jun 25 06:27:06 PM PDT 24
Peak memory 217440 kb
Host smart-b1e455ca-de08-4695-ae4c-0763eed9c179
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188576713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.188576713
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.3720507368
Short name T306
Test name
Test status
Simulation time 1829039091 ps
CPU time 29.44 seconds
Started Jun 25 06:26:59 PM PDT 24
Finished Jun 25 06:27:32 PM PDT 24
Peak memory 218412 kb
Host smart-9353663d-df8e-461b-9b58-72702deebb87
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720507368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.3720507368
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.292755655
Short name T685
Test name
Test status
Simulation time 1058354277 ps
CPU time 3.88 seconds
Started Jun 25 06:27:08 PM PDT 24
Finished Jun 25 06:27:13 PM PDT 24
Peak memory 217640 kb
Host smart-18fea030-9bac-408a-9b18-22b1fa7b61a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292755655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.292755655
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3041893179
Short name T702
Test name
Test status
Simulation time 3429189922 ps
CPU time 6.94 seconds
Started Jun 25 06:26:59 PM PDT 24
Finished Jun 25 06:27:10 PM PDT 24
Peak memory 223912 kb
Host smart-12b339ee-d7de-4381-bfd4-677e5039c45f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041893179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3041893179
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.159269884
Short name T81
Test name
Test status
Simulation time 2466310640 ps
CPU time 17.54 seconds
Started Jun 25 06:27:05 PM PDT 24
Finished Jun 25 06:27:24 PM PDT 24
Peak memory 217824 kb
Host smart-b84ca8f8-c788-4cfa-a506-5e41fefc9ae6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159269884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_regwen_during_op.159269884
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2793936007
Short name T252
Test name
Test status
Simulation time 434394875 ps
CPU time 7.29 seconds
Started Jun 25 06:26:56 PM PDT 24
Finished Jun 25 06:27:09 PM PDT 24
Peak memory 217904 kb
Host smart-025c2f32-0413-4ea4-8400-6a91af90cf47
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793936007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2793936007
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3365709565
Short name T600
Test name
Test status
Simulation time 1669164278 ps
CPU time 36.68 seconds
Started Jun 25 06:26:58 PM PDT 24
Finished Jun 25 06:27:39 PM PDT 24
Peak memory 267556 kb
Host smart-4c1b6afb-0b5f-41dd-8a74-1b6db8ac7102
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365709565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.3365709565
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1869951385
Short name T665
Test name
Test status
Simulation time 1623970278 ps
CPU time 12.48 seconds
Started Jun 25 06:26:57 PM PDT 24
Finished Jun 25 06:27:15 PM PDT 24
Peak memory 244452 kb
Host smart-d1a8f614-d24f-41ed-be8c-6884c60ec6cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869951385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.1869951385
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.4213028164
Short name T236
Test name
Test status
Simulation time 261699069 ps
CPU time 5.86 seconds
Started Jun 25 06:27:00 PM PDT 24
Finished Jun 25 06:27:09 PM PDT 24
Peak memory 223064 kb
Host smart-471445fb-449c-4a99-96c9-d70d90aa12c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213028164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.4213028164
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.2539769598
Short name T827
Test name
Test status
Simulation time 1132902859 ps
CPU time 8.5 seconds
Started Jun 25 06:26:55 PM PDT 24
Finished Jun 25 06:27:10 PM PDT 24
Peak memory 214844 kb
Host smart-a26c3ea9-e55a-4bf2-b9c4-2e897434bf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539769598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2539769598
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.53985788
Short name T234
Test name
Test status
Simulation time 422623426 ps
CPU time 13.33 seconds
Started Jun 25 06:27:05 PM PDT 24
Finished Jun 25 06:27:20 PM PDT 24
Peak memory 226100 kb
Host smart-c5758517-9e10-419d-8bda-0e0230777d33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53985788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.53985788
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.3129369378
Short name T248
Test name
Test status
Simulation time 6182033228 ps
CPU time 12.28 seconds
Started Jun 25 06:27:04 PM PDT 24
Finished Jun 25 06:27:18 PM PDT 24
Peak memory 218564 kb
Host smart-b55a316d-ffb1-4daf-8d04-5df6509e9a25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129369378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.3129369378
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.1311406644
Short name T375
Test name
Test status
Simulation time 504272264 ps
CPU time 16.92 seconds
Started Jun 25 06:27:03 PM PDT 24
Finished Jun 25 06:27:22 PM PDT 24
Peak memory 225584 kb
Host smart-715affe2-ca1f-4a97-a7e6-935b8ec61cc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311406644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.1
311406644
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.1237544550
Short name T96
Test name
Test status
Simulation time 3222345201 ps
CPU time 10.43 seconds
Started Jun 25 06:26:56 PM PDT 24
Finished Jun 25 06:27:12 PM PDT 24
Peak memory 218852 kb
Host smart-e8b2605a-d716-440f-ada1-e0b6a3922231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237544550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.1237544550
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.957494178
Short name T277
Test name
Test status
Simulation time 191917854 ps
CPU time 3.17 seconds
Started Jun 25 06:26:49 PM PDT 24
Finished Jun 25 06:26:59 PM PDT 24
Peak memory 217916 kb
Host smart-f0fc229d-1ca5-4518-b516-b3c4d35b9a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957494178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.957494178
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.1305934912
Short name T452
Test name
Test status
Simulation time 599923891 ps
CPU time 31.02 seconds
Started Jun 25 06:26:51 PM PDT 24
Finished Jun 25 06:27:29 PM PDT 24
Peak memory 251056 kb
Host smart-03e6d5e1-9612-46aa-9b7d-c190522ed3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305934912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.1305934912
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.864995927
Short name T250
Test name
Test status
Simulation time 76999178 ps
CPU time 3.19 seconds
Started Jun 25 06:26:59 PM PDT 24
Finished Jun 25 06:27:06 PM PDT 24
Peak memory 226548 kb
Host smart-83ae3afb-3eb2-444f-b833-eb68d312ba00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864995927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.864995927
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.515816285
Short name T616
Test name
Test status
Simulation time 3837890669 ps
CPU time 31.43 seconds
Started Jun 25 06:27:04 PM PDT 24
Finished Jun 25 06:27:37 PM PDT 24
Peak memory 227440 kb
Host smart-8fa20acb-cf17-401d-b89b-ded0c4f9bd57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515816285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.515816285
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2118660214
Short name T264
Test name
Test status
Simulation time 41242491 ps
CPU time 0.97 seconds
Started Jun 25 06:26:50 PM PDT 24
Finished Jun 25 06:26:58 PM PDT 24
Peak memory 212180 kb
Host smart-06ddb114-680b-4e82-8904-f2fca50304c4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118660214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.2118660214
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.1248146097
Short name T305
Test name
Test status
Simulation time 157651243 ps
CPU time 0.85 seconds
Started Jun 25 06:27:17 PM PDT 24
Finished Jun 25 06:27:19 PM PDT 24
Peak memory 209120 kb
Host smart-99be831c-ba95-4527-a30a-b7cc90e06971
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248146097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.1248146097
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.997241123
Short name T727
Test name
Test status
Simulation time 241147519 ps
CPU time 9.58 seconds
Started Jun 25 06:27:04 PM PDT 24
Finished Jun 25 06:27:15 PM PDT 24
Peak memory 218432 kb
Host smart-f8f7f2a0-c118-471b-b95a-69f46d19be95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997241123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.997241123
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.47499309
Short name T40
Test name
Test status
Simulation time 1327118291 ps
CPU time 9.78 seconds
Started Jun 25 06:27:09 PM PDT 24
Finished Jun 25 06:27:20 PM PDT 24
Peak memory 217360 kb
Host smart-283ecd12-1feb-449f-be99-7c85aba1761b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47499309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.47499309
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1713894932
Short name T839
Test name
Test status
Simulation time 8810730224 ps
CPU time 41.1 seconds
Started Jun 25 06:27:09 PM PDT 24
Finished Jun 25 06:27:52 PM PDT 24
Peak memory 218480 kb
Host smart-e2a9c8c5-5670-47ef-a514-4264057704c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713894932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1713894932
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.3243091185
Short name T848
Test name
Test status
Simulation time 15028980577 ps
CPU time 15.5 seconds
Started Jun 25 06:27:10 PM PDT 24
Finished Jun 25 06:27:27 PM PDT 24
Peak memory 218012 kb
Host smart-1e7594ef-6ca8-464d-adea-f359f85867c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243091185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.3
243091185
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1670586188
Short name T746
Test name
Test status
Simulation time 805488002 ps
CPU time 12.56 seconds
Started Jun 25 06:27:10 PM PDT 24
Finished Jun 25 06:27:24 PM PDT 24
Peak memory 218396 kb
Host smart-2d172858-84b2-4caf-9500-bff6b6de6c27
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670586188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.1670586188
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1616371857
Short name T429
Test name
Test status
Simulation time 809085674 ps
CPU time 13.67 seconds
Started Jun 25 06:27:10 PM PDT 24
Finished Jun 25 06:27:25 PM PDT 24
Peak memory 217924 kb
Host smart-a94c9db7-4afa-4bde-9210-61c92d6f6b49
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616371857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.1616371857
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.1976227697
Short name T667
Test name
Test status
Simulation time 286355559 ps
CPU time 4.52 seconds
Started Jun 25 06:27:10 PM PDT 24
Finished Jun 25 06:27:16 PM PDT 24
Peak memory 217936 kb
Host smart-027b66b4-20aa-4d04-8558-2c9aef2fbb15
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976227697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
1976227697
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1373670203
Short name T510
Test name
Test status
Simulation time 3226634473 ps
CPU time 80.47 seconds
Started Jun 25 06:27:10 PM PDT 24
Finished Jun 25 06:28:32 PM PDT 24
Peak memory 277388 kb
Host smart-e9db57cf-d8ad-470a-8f12-f57471748c52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373670203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.1373670203
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1017550443
Short name T657
Test name
Test status
Simulation time 854425810 ps
CPU time 8.77 seconds
Started Jun 25 06:27:12 PM PDT 24
Finished Jun 25 06:27:21 PM PDT 24
Peak memory 223152 kb
Host smart-49b5fa25-ff22-4a66-b290-48cf901d9417
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017550443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1017550443
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1454616882
Short name T425
Test name
Test status
Simulation time 43030531 ps
CPU time 2.83 seconds
Started Jun 25 06:27:11 PM PDT 24
Finished Jun 25 06:27:15 PM PDT 24
Peak memory 222500 kb
Host smart-02f4c44c-b8f0-4d4e-b6f1-96004a201c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454616882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1454616882
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.2954669349
Short name T65
Test name
Test status
Simulation time 1471113106 ps
CPU time 10.65 seconds
Started Jun 25 06:27:05 PM PDT 24
Finished Jun 25 06:27:17 PM PDT 24
Peak memory 214956 kb
Host smart-dfbc6d78-fd00-40dc-a204-3b0fd7ba868a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954669349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2954669349
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1452908417
Short name T871
Test name
Test status
Simulation time 6896576128 ps
CPU time 15.24 seconds
Started Jun 25 06:27:18 PM PDT 24
Finished Jun 25 06:27:34 PM PDT 24
Peak memory 226184 kb
Host smart-c1c356c4-d1a9-49e9-b6c7-4bda23a1d381
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452908417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1452908417
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2425284572
Short name T316
Test name
Test status
Simulation time 828633697 ps
CPU time 17.81 seconds
Started Jun 25 06:27:10 PM PDT 24
Finished Jun 25 06:27:29 PM PDT 24
Peak memory 218440 kb
Host smart-d843a17f-ee30-4ae3-aa05-55689819f804
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425284572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2425284572
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2512321453
Short name T350
Test name
Test status
Simulation time 446390443 ps
CPU time 12.16 seconds
Started Jun 25 06:27:17 PM PDT 24
Finished Jun 25 06:27:31 PM PDT 24
Peak memory 226132 kb
Host smart-824a9c68-e8ac-46d9-ad20-611f199945f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512321453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
512321453
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.398420331
Short name T295
Test name
Test status
Simulation time 180875709 ps
CPU time 5.65 seconds
Started Jun 25 06:27:04 PM PDT 24
Finished Jun 25 06:27:11 PM PDT 24
Peak memory 218492 kb
Host smart-34e0b719-4949-4216-9c25-ac69900aef3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398420331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.398420331
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.4264658648
Short name T522
Test name
Test status
Simulation time 548469114 ps
CPU time 3.75 seconds
Started Jun 25 06:27:13 PM PDT 24
Finished Jun 25 06:27:18 PM PDT 24
Peak memory 217780 kb
Host smart-28183b00-8182-4b4a-80ec-f09bea1aef33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264658648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.4264658648
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.322254109
Short name T202
Test name
Test status
Simulation time 290939560 ps
CPU time 29.21 seconds
Started Jun 25 06:27:13 PM PDT 24
Finished Jun 25 06:27:43 PM PDT 24
Peak memory 250972 kb
Host smart-1302cb3b-2d4a-441b-bf1d-2e8abf4dd7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322254109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.322254109
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.3913968359
Short name T740
Test name
Test status
Simulation time 61486752 ps
CPU time 7.08 seconds
Started Jun 25 06:27:04 PM PDT 24
Finished Jun 25 06:27:12 PM PDT 24
Peak memory 251024 kb
Host smart-974f09ec-006f-4499-8153-2e6f6b39d75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913968359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3913968359
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.1433320800
Short name T744
Test name
Test status
Simulation time 23359540967 ps
CPU time 186.75 seconds
Started Jun 25 06:27:11 PM PDT 24
Finished Jun 25 06:30:19 PM PDT 24
Peak memory 278808 kb
Host smart-af765205-707b-4af9-b985-d9c4f4a67f42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433320800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.1433320800
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.562302001
Short name T239
Test name
Test status
Simulation time 59707984 ps
CPU time 1.02 seconds
Started Jun 25 06:27:03 PM PDT 24
Finished Jun 25 06:27:06 PM PDT 24
Peak memory 213124 kb
Host smart-cb23d781-9ac3-4667-bd5d-b19972139d28
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562302001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr
l_volatile_unlock_smoke.562302001
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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