Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46492 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T3 |
3 |
auto[1] |
1600 |
1 |
|
|
T5 |
7 |
|
T14 |
13 |
|
T15 |
30 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47340 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T3 |
3 |
auto[1] |
752 |
1 |
|
|
T25 |
22 |
|
T38 |
12 |
|
T66 |
12 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46547 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T3 |
3 |
auto[1] |
1545 |
1 |
|
|
T10 |
1 |
|
T4 |
2 |
|
T15 |
27 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46468 |
1 |
|
|
T1 |
15 |
|
T2 |
11 |
|
T3 |
3 |
auto[1] |
1624 |
1 |
|
|
T2 |
1 |
|
T4 |
1 |
|
T15 |
25 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46508 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T3 |
3 |
auto[1] |
1584 |
1 |
|
|
T2 |
3 |
|
T15 |
28 |
|
T45 |
9 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
43509 |
1 |
|
|
T1 |
15 |
|
T2 |
7 |
|
T3 |
3 |
no_err_inj |
4583 |
1 |
|
|
T2 |
5 |
|
T10 |
11 |
|
T4 |
6 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46478 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T3 |
3 |
auto[1] |
1614 |
1 |
|
|
T5 |
7 |
|
T14 |
18 |
|
T15 |
37 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47350 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T3 |
3 |
auto[1] |
742 |
1 |
|
|
T25 |
15 |
|
T38 |
11 |
|
T66 |
11 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
34486 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T10 |
15 |
auto[1] |
13606 |
1 |
|
|
T3 |
3 |
|
T4 |
11 |
|
T5 |
67 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46579 |
1 |
|
|
T1 |
15 |
|
T2 |
10 |
|
T3 |
3 |
auto[1] |
1513 |
1 |
|
|
T2 |
2 |
|
T4 |
1 |
|
T15 |
24 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46487 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T3 |
3 |
auto[1] |
1605 |
1 |
|
|
T15 |
17 |
|
T45 |
9 |
|
T65 |
6 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46465 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T3 |
3 |
auto[1] |
1627 |
1 |
|
|
T10 |
1 |
|
T15 |
25 |
|
T45 |
15 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46555 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T3 |
3 |
auto[1] |
1537 |
1 |
|
|
T5 |
9 |
|
T14 |
8 |
|
T15 |
32 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46191 |
1 |
|
|
T2 |
12 |
|
T10 |
15 |
|
T4 |
11 |
auto[1] |
1901 |
1 |
|
|
T1 |
15 |
|
T3 |
3 |
|
T15 |
10 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47335 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T3 |
3 |
auto[1] |
757 |
1 |
|
|
T25 |
14 |
|
T38 |
13 |
|
T66 |
19 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47370 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T3 |
3 |
auto[1] |
722 |
1 |
|
|
T25 |
8 |
|
T38 |
8 |
|
T66 |
12 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47339 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T3 |
3 |
auto[1] |
753 |
1 |
|
|
T25 |
20 |
|
T38 |
10 |
|
T66 |
12 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
45626 |
1 |
|
|
T1 |
15 |
|
T3 |
3 |
|
T5 |
67 |
auto[1] |
2466 |
1 |
|
|
T2 |
12 |
|
T10 |
15 |
|
T4 |
11 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
44435 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T3 |
3 |
auto[1] |
3657 |
1 |
|
|
T23 |
80 |
|
T54 |
83 |
|
T56 |
81 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46553 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T3 |
3 |
auto[1] |
1539 |
1 |
|
|
T15 |
37 |
|
T45 |
4 |
|
T65 |
7 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46590 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T3 |
3 |
auto[1] |
1502 |
1 |
|
|
T10 |
1 |
|
T4 |
1 |
|
T15 |
26 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46511 |
1 |
|
|
T1 |
15 |
|
T2 |
11 |
|
T3 |
3 |
auto[1] |
1581 |
1 |
|
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
27 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46496 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T3 |
3 |
auto[1] |
1596 |
1 |
|
|
T5 |
9 |
|
T14 |
8 |
|
T15 |
45 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
42896 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T3 |
3 |
auto[1] |
5196 |
1 |
|
|
T5 |
5 |
|
T14 |
10 |
|
T15 |
39 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
44146 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T3 |
3 |
auto[1] |
3946 |
1 |
|
|
T21 |
96 |
|
T40 |
85 |
|
T18 |
77 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48092 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T3 |
3 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46538 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T3 |
3 |
auto[1] |
1554 |
1 |
|
|
T5 |
7 |
|
T14 |
6 |
|
T15 |
31 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46546 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T3 |
3 |
auto[1] |
1546 |
1 |
|
|
T5 |
12 |
|
T14 |
6 |
|
T15 |
29 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46576 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T3 |
3 |
auto[1] |
1516 |
1 |
|
|
T5 |
11 |
|
T14 |
6 |
|
T15 |
29 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
42277 |
1 |
|
|
T1 |
15 |
|
T3 |
3 |
|
T5 |
67 |
auto[0] |
no_err_inj |
3349 |
1 |
|
|
T19 |
11 |
|
T20 |
7 |
|
T15 |
102 |
auto[1] |
err_inj |
1232 |
1 |
|
|
T2 |
7 |
|
T10 |
4 |
|
T4 |
5 |
auto[1] |
no_err_inj |
1234 |
1 |
|
|
T2 |
5 |
|
T10 |
11 |
|
T4 |
6 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
44248 |
1 |
|
|
T1 |
15 |
|
T3 |
3 |
|
T5 |
67 |
auto[0] |
auto[1] |
1378 |
1 |
|
|
T15 |
26 |
|
T45 |
3 |
|
T65 |
7 |
auto[1] |
auto[0] |
2342 |
1 |
|
|
T2 |
12 |
|
T10 |
14 |
|
T4 |
10 |
auto[1] |
auto[1] |
124 |
1 |
|
|
T10 |
1 |
|
T4 |
1 |
|
T27 |
2 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
44157 |
1 |
|
|
T1 |
15 |
|
T3 |
3 |
|
T5 |
67 |
auto[0] |
auto[1] |
1469 |
1 |
|
|
T15 |
16 |
|
T45 |
9 |
|
T65 |
6 |
auto[1] |
auto[0] |
2330 |
1 |
|
|
T2 |
12 |
|
T10 |
15 |
|
T4 |
11 |
auto[1] |
auto[1] |
136 |
1 |
|
|
T15 |
1 |
|
T27 |
2 |
|
T29 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
44179 |
1 |
|
|
T1 |
15 |
|
T3 |
3 |
|
T5 |
67 |
auto[0] |
auto[1] |
1447 |
1 |
|
|
T15 |
24 |
|
T45 |
7 |
|
T65 |
5 |
auto[1] |
auto[0] |
2332 |
1 |
|
|
T2 |
11 |
|
T10 |
14 |
|
T4 |
11 |
auto[1] |
auto[1] |
134 |
1 |
|
|
T2 |
1 |
|
T10 |
1 |
|
T15 |
3 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
44120 |
1 |
|
|
T1 |
15 |
|
T3 |
3 |
|
T5 |
67 |
auto[0] |
auto[1] |
1506 |
1 |
|
|
T15 |
23 |
|
T45 |
14 |
|
T65 |
11 |
auto[1] |
auto[0] |
2348 |
1 |
|
|
T2 |
11 |
|
T10 |
15 |
|
T4 |
10 |
auto[1] |
auto[1] |
118 |
1 |
|
|
T2 |
1 |
|
T4 |
1 |
|
T15 |
2 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
44185 |
1 |
|
|
T1 |
15 |
|
T3 |
3 |
|
T5 |
67 |
auto[0] |
auto[1] |
1441 |
1 |
|
|
T15 |
27 |
|
T45 |
9 |
|
T65 |
10 |
auto[1] |
auto[0] |
2323 |
1 |
|
|
T2 |
9 |
|
T10 |
15 |
|
T4 |
11 |
auto[1] |
auto[1] |
143 |
1 |
|
|
T2 |
3 |
|
T15 |
1 |
|
T27 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
44224 |
1 |
|
|
T1 |
15 |
|
T3 |
3 |
|
T5 |
67 |
auto[0] |
auto[1] |
1402 |
1 |
|
|
T15 |
26 |
|
T45 |
2 |
|
T65 |
9 |
auto[1] |
auto[0] |
2323 |
1 |
|
|
T2 |
12 |
|
T10 |
14 |
|
T4 |
9 |
auto[1] |
auto[1] |
143 |
1 |
|
|
T10 |
1 |
|
T4 |
2 |
|
T15 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33556 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T10 |
15 |
auto[0] |
auto[1] |
930 |
1 |
|
|
T14 |
13 |
|
T15 |
13 |
|
T216 |
10 |
auto[1] |
auto[0] |
12936 |
1 |
|
|
T3 |
3 |
|
T4 |
11 |
|
T5 |
60 |
auto[1] |
auto[1] |
670 |
1 |
|
|
T5 |
7 |
|
T15 |
17 |
|
T93 |
7 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33536 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T10 |
15 |
auto[0] |
auto[1] |
950 |
1 |
|
|
T14 |
18 |
|
T15 |
9 |
|
T216 |
15 |
auto[1] |
auto[0] |
12942 |
1 |
|
|
T3 |
3 |
|
T4 |
11 |
|
T5 |
60 |
auto[1] |
auto[1] |
664 |
1 |
|
|
T5 |
7 |
|
T15 |
28 |
|
T93 |
6 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33293 |
1 |
|
|
T2 |
12 |
|
T10 |
15 |
|
T19 |
11 |
auto[0] |
auto[1] |
1193 |
1 |
|
|
T1 |
15 |
|
T15 |
10 |
|
T217 |
20 |
auto[1] |
auto[0] |
12898 |
1 |
|
|
T4 |
11 |
|
T5 |
67 |
|
T20 |
7 |
auto[1] |
auto[1] |
708 |
1 |
|
|
T3 |
3 |
|
T28 |
11 |
|
T218 |
1 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33588 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T10 |
15 |
auto[0] |
auto[1] |
898 |
1 |
|
|
T14 |
8 |
|
T15 |
7 |
|
T216 |
6 |
auto[1] |
auto[0] |
12967 |
1 |
|
|
T3 |
3 |
|
T4 |
11 |
|
T5 |
58 |
auto[1] |
auto[1] |
639 |
1 |
|
|
T5 |
9 |
|
T15 |
25 |
|
T93 |
3 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
29921 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T10 |
15 |
auto[0] |
auto[1] |
4565 |
1 |
|
|
T14 |
10 |
|
T15 |
11 |
|
T39 |
94 |
auto[1] |
auto[0] |
12975 |
1 |
|
|
T3 |
3 |
|
T4 |
11 |
|
T5 |
62 |
auto[1] |
auto[1] |
631 |
1 |
|
|
T5 |
5 |
|
T15 |
28 |
|
T93 |
5 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33566 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T10 |
14 |
auto[0] |
auto[1] |
920 |
1 |
|
|
T10 |
1 |
|
T15 |
7 |
|
T45 |
3 |
auto[1] |
auto[0] |
13024 |
1 |
|
|
T3 |
3 |
|
T4 |
10 |
|
T5 |
67 |
auto[1] |
auto[1] |
582 |
1 |
|
|
T4 |
1 |
|
T15 |
19 |
|
T37 |
9 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33570 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T10 |
15 |
auto[0] |
auto[1] |
916 |
1 |
|
|
T15 |
12 |
|
T45 |
4 |
|
T65 |
7 |
auto[1] |
auto[0] |
12983 |
1 |
|
|
T3 |
3 |
|
T4 |
11 |
|
T5 |
67 |
auto[1] |
auto[1] |
623 |
1 |
|
|
T15 |
25 |
|
T37 |
10 |
|
T41 |
2 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33521 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T10 |
15 |
auto[0] |
auto[1] |
965 |
1 |
|
|
T15 |
8 |
|
T45 |
9 |
|
T65 |
6 |
auto[1] |
auto[0] |
12966 |
1 |
|
|
T3 |
3 |
|
T4 |
11 |
|
T5 |
67 |
auto[1] |
auto[1] |
640 |
1 |
|
|
T15 |
9 |
|
T37 |
8 |
|
T41 |
1 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33572 |
1 |
|
|
T1 |
15 |
|
T2 |
10 |
|
T10 |
15 |
auto[0] |
auto[1] |
914 |
1 |
|
|
T2 |
2 |
|
T15 |
9 |
|
T45 |
4 |
auto[1] |
auto[0] |
13007 |
1 |
|
|
T3 |
3 |
|
T4 |
10 |
|
T5 |
67 |
auto[1] |
auto[1] |
599 |
1 |
|
|
T4 |
1 |
|
T15 |
15 |
|
T37 |
5 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33500 |
1 |
|
|
T1 |
15 |
|
T2 |
11 |
|
T10 |
15 |
auto[0] |
auto[1] |
986 |
1 |
|
|
T2 |
1 |
|
T15 |
9 |
|
T45 |
14 |
auto[1] |
auto[0] |
12968 |
1 |
|
|
T3 |
3 |
|
T4 |
10 |
|
T5 |
67 |
auto[1] |
auto[1] |
638 |
1 |
|
|
T4 |
1 |
|
T15 |
16 |
|
T37 |
11 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33569 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T10 |
14 |
auto[0] |
auto[1] |
917 |
1 |
|
|
T10 |
1 |
|
T15 |
17 |
|
T45 |
2 |
auto[1] |
auto[0] |
12978 |
1 |
|
|
T3 |
3 |
|
T4 |
9 |
|
T5 |
67 |
auto[1] |
auto[1] |
628 |
1 |
|
|
T4 |
2 |
|
T15 |
10 |
|
T37 |
9 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33604 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T10 |
15 |
auto[0] |
auto[1] |
882 |
1 |
|
|
T14 |
6 |
|
T15 |
13 |
|
T216 |
13 |
auto[1] |
auto[0] |
12972 |
1 |
|
|
T3 |
3 |
|
T4 |
11 |
|
T5 |
56 |
auto[1] |
auto[1] |
634 |
1 |
|
|
T5 |
11 |
|
T15 |
16 |
|
T93 |
8 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33570 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T10 |
15 |
auto[0] |
auto[1] |
916 |
1 |
|
|
T14 |
6 |
|
T15 |
9 |
|
T216 |
7 |
auto[1] |
auto[0] |
12976 |
1 |
|
|
T3 |
3 |
|
T4 |
11 |
|
T5 |
55 |
auto[1] |
auto[1] |
630 |
1 |
|
|
T5 |
12 |
|
T15 |
20 |
|
T93 |
6 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32991 |
1 |
|
|
T1 |
15 |
|
T19 |
11 |
|
T14 |
75 |
auto[0] |
auto[1] |
1495 |
1 |
|
|
T2 |
12 |
|
T10 |
15 |
|
T15 |
11 |
auto[1] |
auto[0] |
12635 |
1 |
|
|
T3 |
3 |
|
T5 |
67 |
|
T20 |
7 |
auto[1] |
auto[1] |
971 |
1 |
|
|
T4 |
11 |
|
T15 |
11 |
|
T41 |
13 |