Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94487218

1

T1

6269

T2

4516

T3

8506

auto[1]

1235600

1

T1

891

T2

396

T3

98

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94473640

1

T1

6566

T2

4714

T3

8408

auto[1]

1249178

1

T1

594

T2

198

T3

196

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6326110	1			T1	1548		T2	1174		T3	328
auto[IdleSt]	19081701	1			T1	1838		T2	912		T3	5570
auto[ClkMuxSt]	32850	1			T1	15		T2	5		T3	3
auto[CntIncrSt]	32589	1			T1	15		T2	5		T3	3
auto[CntProgSt]	1537300	1			T1	661		T2	114		T3	174
auto[TransCheckSt]	25665	1			T2	5		T10	11		T4	6
auto[TokenHashSt]	41711566	1			T2	56		T10	258		T4	103
auto[FlashRmaSt]	26719	1			T2	24		T10	11		T4	6
auto[TokenCheck0St]	11980	1			T2	5		T10	11		T4	6
auto[TokenCheck1St]	8867	1			T2	5		T10	11		T4	6
auto[TransProgSt]	337569	1			T2	168		T10	198		T4	286
auto[PostTransSt]	11534779	1			T1	1067		T2	849		T3	1411
auto[ScrapSt]	143334	1			T19	15		T20	2634		T15	5632
auto[EscalateSt]	5674224	1			T1	2016		T2	1086		T3	1115
auto[InvalidSt]	9235869	1			T2	504		T10	328		T4	10343

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1696	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	9235869	1			T2	504		T10	328		T4	10343
EscalateSt	5674224	1			T1	2016		T2	1086		T3	1115
ScrapSt	143334	1			T19	15		T20	2634		T15	5632
PostTransSt	11534779	1			T1	1067		T2	849		T3	1411
TransProgSt	337569	1			T2	168		T10	198		T4	286
TokenCheck1St	8867	1			T2	5		T10	11		T4	6
TokenCheck0St	11980	1			T2	5		T10	11		T4	6
FlashRmaSt	26719	1			T2	24		T10	11		T4	6
TokenHashSt	41711566	1			T2	56		T10	258		T4	103
TransCheckSt	25665	1			T2	5		T10	11		T4	6
CntProgSt	1537300	1			T1	661		T2	114		T3	174
CntIncrSt	32589	1			T1	15		T2	5		T3	3
ClkMuxSt	32850	1			T1	15		T2	5		T3	3
IdleSt	19081701	1			T1	1838		T2	912		T3	5570
ResetSt	6326110	1			T1	1548		T2	1174		T3	328
arcs[ResetSt=>IdleSt]	48548	1			T1	16		T2	13		T3	4
arcs[IdleSt=>ScrapSt]	283	1			T19	1		T20	1		T15	8
arcs[IdleSt=>ClkMuxSt]	32646	1			T1	15		T2	5		T3	3
arcs[ClkMuxSt=>CntIncrSt]	32589	1			T1	15		T2	5		T3	3
arcs[CntIncrSt=>PostTransSt]	1547	1			T5	12		T14	6		T15	29
arcs[CntIncrSt=>CntProgSt]	30977	1			T1	15		T2	5		T3	3
arcs[CntProgSt=>PostTransSt]	4203	1			T1	15		T3	3		T5	6
arcs[CntProgSt=>TransCheckSt]	25665	1			T2	5		T10	11		T4	6
arcs[TransCheckSt=>PostTransSt]	3499	1			T5	11		T14	6		T21	53
arcs[TransCheckSt=>TokenHashSt]	22048	1			T2	5		T10	11		T4	6
arcs[TokenHashSt=>PostTransSt]	9338	1			T12	1		T5	21		T14	24
arcs[TokenHashSt=>FlashRmaSt]	12081	1			T2	5		T10	11		T4	6
arcs[FlashRmaSt=>TokenCheck0St]	11980	1			T2	5		T10	11		T4	6
arcs[TokenCheck0St=>PostTransSt]	3087	1			T5	6		T14	16		T21	19
arcs[TokenCheck0St=>TokenCheck1St]	8867	1			T2	5		T10	11		T4	6
arcs[TokenCheck1St=>PostTransSt]	668	1			T5	1		T14	2		T21	16
arcs[TransProgSt=>PostTransSt]	7326	1			T2	5		T10	11		T4	6
arcs[IdleSt=>EscalateSt]	216	1			T23	10		T54	7		T58	8
arcs[ClkMuxSt=>EscalateSt]	57	1			T23	3		T54	1		T55	1
arcs[CntIncrSt=>EscalateSt]	65	1			T23	1		T54	3		T56	3
arcs[CntProgSt=>EscalateSt]	1109	1			T23	24		T54	30		T56	41
arcs[TransCheckSt=>EscalateSt]	118	1			T23	1		T57	11		T58	1
arcs[TokenHashSt=>EscalateSt]	629	1			T23	13		T54	10		T56	12
arcs[FlashRmaSt=>EscalateSt]	101	1			T23	2		T56	1		T57	5
arcs[TokenCheck0St=>EscalateSt]	26	1			T23	1		T55	1		T60	1
arcs[TokenCheck1St=>EscalateSt]	136	1			T23	2		T54	2		T55	2
arcs[TransProgSt=>EscalateSt]	737	1			T23	17		T54	17		T56	16
arcs[PostTransSt=>EscalateSt]	4430	1			T1	15		T3	3		T5	7
arcs[InvalidSt=>EscalateSt]	11642	1			T2	6		T10	2		T4	5

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6325958	1			T1	1548		T2	1174		T3	328
auto[0]	auto[IdleSt]	19081552	1			T1	1838		T2	912		T3	5570
auto[0]	auto[ClkMuxSt]	32811	1			T1	15		T2	5		T3	3
auto[0]	auto[CntIncrSt]	32546	1			T1	15		T2	5		T3	3
auto[0]	auto[CntProgSt]	1536586	1			T1	661		T2	114		T3	174
auto[0]	auto[TransCheckSt]	25593	1			T2	5		T10	11		T4	6
auto[0]	auto[TokenHashSt]	41711151	1			T2	56		T10	258		T4	103
auto[0]	auto[FlashRmaSt]	26646	1			T2	24		T10	11		T4	6
auto[0]	auto[TokenCheck0St]	11962	1			T2	5		T10	11		T4	6
auto[0]	auto[TokenCheck1St]	8774	1			T2	5		T10	11		T4	6
auto[0]	auto[TransProgSt]	337074	1			T2	168		T10	198		T4	286
auto[0]	auto[PostTransSt]	11532538	1			T1	1058		T2	849		T3	1410
auto[0]	auto[ScrapSt]	143298	1			T19	15		T20	2634		T15	5632
auto[0]	auto[EscalateSt]	4448944	1			T1	1134		T2	694		T3	1018
auto[0]	auto[InvalidSt]	9230089	1			T2	500		T10	327		T4	10338
auto[1]	auto[ResetSt]	152	1			T23	2		T54	7		T56	5
auto[1]	auto[IdleSt]	149	1			T23	8		T54	6		T58	5
auto[1]	auto[ClkMuxSt]	39	1			T23	3		T54	1		T214	1
auto[1]	auto[CntIncrSt]	43	1			T54	3		T56	3		T57	2
auto[1]	auto[CntProgSt]	714	1			T23	17		T54	19		T56	27
auto[1]	auto[TransCheckSt]	72	1			T23	1		T57	8		T58	1
auto[1]	auto[TokenHashSt]	415	1			T23	10		T54	6		T56	11
auto[1]	auto[FlashRmaSt]	73	1			T23	2		T56	1		T57	4
auto[1]	auto[TokenCheck0St]	18	1			T23	1		T60	1		T215	1
auto[1]	auto[TokenCheck1St]	93	1			T23	2		T54	1		T55	1
auto[1]	auto[TransProgSt]	495	1			T23	8		T54	15		T56	13
auto[1]	auto[PostTransSt]	2241	1			T1	9		T3	1		T5	4
auto[1]	auto[ScrapSt]	36	1			T54	1		T56	1		T55	1
auto[1]	auto[EscalateSt]	1225280	1			T1	882		T2	392		T3	97
auto[1]	auto[InvalidSt]	5780	1			T2	4		T10	1		T4	5

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6325952	1			T1	1548		T2	1174		T3	328
auto[0]	auto[IdleSt]	19081566	1			T1	1838		T2	912		T3	5570
auto[0]	auto[ClkMuxSt]	32808	1			T1	15		T2	5		T3	3
auto[0]	auto[CntIncrSt]	32541	1			T1	15		T2	5		T3	3
auto[0]	auto[CntProgSt]	1536560	1			T1	661		T2	114		T3	174
auto[0]	auto[TransCheckSt]	25579	1			T2	5		T10	11		T4	6
auto[0]	auto[TokenHashSt]	41711145	1			T2	56		T10	258		T4	103
auto[0]	auto[FlashRmaSt]	26654	1			T2	24		T10	11		T4	6
auto[0]	auto[TokenCheck0St]	11961	1			T2	5		T10	11		T4	6
auto[0]	auto[TokenCheck1St]	8776	1			T2	5		T10	11		T4	6
auto[0]	auto[TransProgSt]	337088	1			T2	168		T10	198		T4	286
auto[0]	auto[PostTransSt]	11532528	1			T1	1061		T2	849		T3	1409
auto[0]	auto[ScrapSt]	143296	1			T19	15		T20	2634		T15	5632
auto[0]	auto[EscalateSt]	4435483	1			T1	1428		T2	890		T3	921
auto[0]	auto[InvalidSt]	9230007	1			T2	502		T10	327		T4	10343
auto[1]	auto[ResetSt]	158	1			T23	2		T54	6		T56	4
auto[1]	auto[IdleSt]	135	1			T23	5		T54	3		T58	8
auto[1]	auto[ClkMuxSt]	42	1			T23	1		T55	1		T57	1
auto[1]	auto[CntIncrSt]	48	1			T23	1		T54	2		T56	3
auto[1]	auto[CntProgSt]	740	1			T23	17		T54	21		T56	23
auto[1]	auto[TransCheckSt]	86	1			T23	1		T57	9		T58	1
auto[1]	auto[TokenHashSt]	421	1			T23	8		T54	4		T56	8
auto[1]	auto[FlashRmaSt]	65	1			T23	1		T57	4		T58	1
auto[1]	auto[TokenCheck0St]	19	1			T55	1		T215	2		T164	1
auto[1]	auto[TokenCheck1St]	91	1			T23	1		T54	2		T55	2
auto[1]	auto[TransProgSt]	481	1			T23	11		T54	8		T56	8
auto[1]	auto[PostTransSt]	2251	1			T1	6		T3	2		T5	3
auto[1]	auto[ScrapSt]	38	1			T54	2		T56	1		T57	2
auto[1]	auto[EscalateSt]	1238741	1			T1	588		T2	196		T3	194
auto[1]	auto[InvalidSt]	5862	1			T2	2		T10	1		T15	87