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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.18 97.92 95.84 93.38 100.00 98.31 98.51 96.29


Total test records in report: 997
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T812 /workspace/coverage/default/25.lc_ctrl_prog_failure.4120899073 Jun 26 06:55:05 PM PDT 24 Jun 26 06:55:10 PM PDT 24 150301028 ps
T813 /workspace/coverage/default/42.lc_ctrl_errors.2530813838 Jun 26 06:56:37 PM PDT 24 Jun 26 06:56:47 PM PDT 24 254492803 ps
T814 /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.1066745232 Jun 26 06:52:38 PM PDT 24 Jun 26 06:52:55 PM PDT 24 1416613875 ps
T815 /workspace/coverage/default/13.lc_ctrl_smoke.1467140133 Jun 26 06:53:47 PM PDT 24 Jun 26 06:53:52 PM PDT 24 287976541 ps
T816 /workspace/coverage/default/49.lc_ctrl_sec_mubi.676390432 Jun 26 06:57:19 PM PDT 24 Jun 26 06:57:30 PM PDT 24 849160112 ps
T817 /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2613390752 Jun 26 06:51:50 PM PDT 24 Jun 26 06:51:54 PM PDT 24 14456695 ps
T818 /workspace/coverage/default/14.lc_ctrl_sec_token_digest.2087173772 Jun 26 06:53:54 PM PDT 24 Jun 26 06:54:11 PM PDT 24 2285170253 ps
T819 /workspace/coverage/default/18.lc_ctrl_jtag_smoke.4276642501 Jun 26 06:54:16 PM PDT 24 Jun 26 06:54:22 PM PDT 24 970869085 ps
T820 /workspace/coverage/default/29.lc_ctrl_state_post_trans.2387804283 Jun 26 06:55:23 PM PDT 24 Jun 26 06:55:32 PM PDT 24 567324248 ps
T821 /workspace/coverage/default/2.lc_ctrl_alert_test.656505918 Jun 26 06:52:04 PM PDT 24 Jun 26 06:52:07 PM PDT 24 144190889 ps
T822 /workspace/coverage/default/46.lc_ctrl_stress_all.1516279232 Jun 26 06:57:04 PM PDT 24 Jun 26 07:06:50 PM PDT 24 97072554479 ps
T823 /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.220015079 Jun 26 06:54:04 PM PDT 24 Jun 26 06:54:18 PM PDT 24 3276238453 ps
T824 /workspace/coverage/default/33.lc_ctrl_stress_all.2056257886 Jun 26 06:55:51 PM PDT 24 Jun 26 06:59:40 PM PDT 24 26447988268 ps
T825 /workspace/coverage/default/32.lc_ctrl_sec_mubi.3496762909 Jun 26 06:55:36 PM PDT 24 Jun 26 06:55:56 PM PDT 24 464843833 ps
T826 /workspace/coverage/default/32.lc_ctrl_jtag_access.3139030796 Jun 26 06:55:40 PM PDT 24 Jun 26 06:55:43 PM PDT 24 187868077 ps
T827 /workspace/coverage/default/21.lc_ctrl_sec_mubi.3760611112 Jun 26 06:54:40 PM PDT 24 Jun 26 06:54:54 PM PDT 24 1149568739 ps
T828 /workspace/coverage/default/4.lc_ctrl_security_escalation.2118973478 Jun 26 06:52:28 PM PDT 24 Jun 26 06:52:39 PM PDT 24 173471569 ps
T829 /workspace/coverage/default/24.lc_ctrl_sec_mubi.3403020827 Jun 26 06:54:54 PM PDT 24 Jun 26 06:55:06 PM PDT 24 266777352 ps
T830 /workspace/coverage/default/5.lc_ctrl_state_failure.3059955225 Jun 26 06:52:27 PM PDT 24 Jun 26 06:52:54 PM PDT 24 282763348 ps
T831 /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2679958833 Jun 26 06:52:28 PM PDT 24 Jun 26 06:52:46 PM PDT 24 368880377 ps
T832 /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3800055788 Jun 26 06:52:52 PM PDT 24 Jun 26 06:52:54 PM PDT 24 14217840 ps
T833 /workspace/coverage/default/45.lc_ctrl_sec_token_mux.4205197713 Jun 26 06:57:06 PM PDT 24 Jun 26 06:57:19 PM PDT 24 474350893 ps
T834 /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.226839604 Jun 26 06:53:32 PM PDT 24 Jun 26 06:58:50 PM PDT 24 66342238075 ps
T835 /workspace/coverage/default/47.lc_ctrl_security_escalation.815973466 Jun 26 06:57:05 PM PDT 24 Jun 26 06:57:20 PM PDT 24 1683514611 ps
T836 /workspace/coverage/default/36.lc_ctrl_state_post_trans.3879648852 Jun 26 06:56:04 PM PDT 24 Jun 26 06:56:12 PM PDT 24 160769349 ps
T837 /workspace/coverage/default/40.lc_ctrl_state_failure.2897380556 Jun 26 06:56:23 PM PDT 24 Jun 26 06:56:36 PM PDT 24 1338780948 ps
T838 /workspace/coverage/default/2.lc_ctrl_prog_failure.3256161587 Jun 26 06:52:08 PM PDT 24 Jun 26 06:52:12 PM PDT 24 61782176 ps
T839 /workspace/coverage/default/6.lc_ctrl_sec_token_digest.3132249528 Jun 26 06:52:50 PM PDT 24 Jun 26 06:52:59 PM PDT 24 957168548 ps
T840 /workspace/coverage/default/20.lc_ctrl_state_post_trans.44376300 Jun 26 06:54:45 PM PDT 24 Jun 26 06:54:55 PM PDT 24 64612746 ps
T841 /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3888780343 Jun 26 06:51:49 PM PDT 24 Jun 26 06:52:20 PM PDT 24 4415038834 ps
T842 /workspace/coverage/default/14.lc_ctrl_state_failure.1797325581 Jun 26 06:53:54 PM PDT 24 Jun 26 06:54:24 PM PDT 24 855717042 ps
T843 /workspace/coverage/default/2.lc_ctrl_smoke.2212576328 Jun 26 06:52:02 PM PDT 24 Jun 26 06:52:05 PM PDT 24 83090135 ps
T844 /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.588142318 Jun 26 06:52:39 PM PDT 24 Jun 26 06:52:41 PM PDT 24 30174522 ps
T845 /workspace/coverage/default/0.lc_ctrl_jtag_smoke.4013352016 Jun 26 06:51:26 PM PDT 24 Jun 26 06:51:37 PM PDT 24 1324194877 ps
T846 /workspace/coverage/default/38.lc_ctrl_prog_failure.3539363847 Jun 26 06:56:15 PM PDT 24 Jun 26 06:56:22 PM PDT 24 122331779 ps
T847 /workspace/coverage/default/12.lc_ctrl_sec_token_digest.930042921 Jun 26 06:53:42 PM PDT 24 Jun 26 06:53:57 PM PDT 24 701587779 ps
T848 /workspace/coverage/default/22.lc_ctrl_alert_test.993111883 Jun 26 06:54:55 PM PDT 24 Jun 26 06:54:58 PM PDT 24 116127852 ps
T849 /workspace/coverage/default/21.lc_ctrl_sec_token_mux.4205538336 Jun 26 06:54:41 PM PDT 24 Jun 26 06:54:55 PM PDT 24 1359134583 ps
T850 /workspace/coverage/default/10.lc_ctrl_state_post_trans.4078102730 Jun 26 06:53:33 PM PDT 24 Jun 26 06:53:42 PM PDT 24 118169988 ps
T851 /workspace/coverage/default/16.lc_ctrl_errors.3519111074 Jun 26 06:54:04 PM PDT 24 Jun 26 06:54:18 PM PDT 24 1033042244 ps
T852 /workspace/coverage/default/8.lc_ctrl_prog_failure.2679922609 Jun 26 06:53:01 PM PDT 24 Jun 26 06:53:04 PM PDT 24 147209973 ps
T853 /workspace/coverage/default/7.lc_ctrl_sec_token_mux.3630690808 Jun 26 06:53:02 PM PDT 24 Jun 26 06:53:20 PM PDT 24 2176697237 ps
T854 /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3514405737 Jun 26 06:55:25 PM PDT 24 Jun 26 06:55:28 PM PDT 24 42447963 ps
T855 /workspace/coverage/default/0.lc_ctrl_state_post_trans.2261055401 Jun 26 06:51:26 PM PDT 24 Jun 26 06:51:36 PM PDT 24 77937268 ps
T856 /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2475009312 Jun 26 06:51:48 PM PDT 24 Jun 26 06:51:59 PM PDT 24 1532837075 ps
T857 /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1484073247 Jun 26 06:52:26 PM PDT 24 Jun 26 06:52:35 PM PDT 24 876789074 ps
T858 /workspace/coverage/default/49.lc_ctrl_alert_test.2718550202 Jun 26 06:57:21 PM PDT 24 Jun 26 06:57:24 PM PDT 24 20692394 ps
T859 /workspace/coverage/default/2.lc_ctrl_security_escalation.1870330147 Jun 26 06:52:04 PM PDT 24 Jun 26 06:52:16 PM PDT 24 339854240 ps
T860 /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1125799068 Jun 26 06:55:25 PM PDT 24 Jun 26 06:55:38 PM PDT 24 4356949002 ps
T861 /workspace/coverage/default/1.lc_ctrl_smoke.4230201121 Jun 26 06:51:48 PM PDT 24 Jun 26 06:51:52 PM PDT 24 20866132 ps
T862 /workspace/coverage/default/7.lc_ctrl_jtag_priority.1813604826 Jun 26 06:53:01 PM PDT 24 Jun 26 06:53:05 PM PDT 24 128779605 ps
T863 /workspace/coverage/default/19.lc_ctrl_smoke.3412901188 Jun 26 06:54:29 PM PDT 24 Jun 26 06:54:32 PM PDT 24 40186924 ps
T864 /workspace/coverage/default/3.lc_ctrl_prog_failure.4124061138 Jun 26 06:52:07 PM PDT 24 Jun 26 06:52:11 PM PDT 24 41056423 ps
T865 /workspace/coverage/default/31.lc_ctrl_jtag_access.2503333390 Jun 26 06:55:38 PM PDT 24 Jun 26 06:55:42 PM PDT 24 178234258 ps
T866 /workspace/coverage/default/0.lc_ctrl_jtag_access.1368340978 Jun 26 06:51:49 PM PDT 24 Jun 26 06:51:56 PM PDT 24 130372087 ps
T867 /workspace/coverage/default/28.lc_ctrl_sec_mubi.4213916339 Jun 26 06:55:25 PM PDT 24 Jun 26 06:55:44 PM PDT 24 319288111 ps
T868 /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3867519821 Jun 26 06:57:04 PM PDT 24 Jun 26 06:57:21 PM PDT 24 686250095 ps
T869 /workspace/coverage/default/46.lc_ctrl_smoke.2726533329 Jun 26 06:57:06 PM PDT 24 Jun 26 06:57:12 PM PDT 24 89210597 ps
T870 /workspace/coverage/default/11.lc_ctrl_jtag_errors.4261041626 Jun 26 06:53:35 PM PDT 24 Jun 26 06:54:06 PM PDT 24 7343448181 ps
T871 /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3701409383 Jun 26 06:53:42 PM PDT 24 Jun 26 06:53:57 PM PDT 24 262550776 ps
T872 /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2871668222 Jun 26 06:52:50 PM PDT 24 Jun 26 06:53:12 PM PDT 24 8862242208 ps
T873 /workspace/coverage/default/9.lc_ctrl_sec_token_digest.504771152 Jun 26 06:53:16 PM PDT 24 Jun 26 06:53:31 PM PDT 24 2297540845 ps
T113 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2689280547 Jun 26 06:38:41 PM PDT 24 Jun 26 06:38:53 PM PDT 24 96310153 ps
T127 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4161580075 Jun 26 06:38:13 PM PDT 24 Jun 26 06:38:21 PM PDT 24 167221401 ps
T148 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2944962045 Jun 26 06:38:45 PM PDT 24 Jun 26 06:38:56 PM PDT 24 46741330 ps
T116 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2629523034 Jun 26 06:38:26 PM PDT 24 Jun 26 06:38:33 PM PDT 24 273366964 ps
T121 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3250032763 Jun 26 06:38:39 PM PDT 24 Jun 26 06:38:51 PM PDT 24 57222138 ps
T114 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3226593590 Jun 26 06:38:29 PM PDT 24 Jun 26 06:38:38 PM PDT 24 156236202 ps
T149 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1080747114 Jun 26 06:38:12 PM PDT 24 Jun 26 06:38:23 PM PDT 24 356356913 ps
T145 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3416749215 Jun 26 06:38:24 PM PDT 24 Jun 26 06:38:30 PM PDT 24 160139511 ps
T874 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.683493226 Jun 26 06:38:32 PM PDT 24 Jun 26 06:38:59 PM PDT 24 695740784 ps
T118 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1756746607 Jun 26 06:38:42 PM PDT 24 Jun 26 06:38:53 PM PDT 24 98826140 ps
T875 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3102033820 Jun 26 06:38:33 PM PDT 24 Jun 26 06:38:45 PM PDT 24 186165803 ps
T876 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4088421272 Jun 26 06:38:16 PM PDT 24 Jun 26 06:38:28 PM PDT 24 493256821 ps
T877 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1196084599 Jun 26 06:38:25 PM PDT 24 Jun 26 06:38:30 PM PDT 24 14978425 ps
T194 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2896649601 Jun 26 06:38:13 PM PDT 24 Jun 26 06:38:21 PM PDT 24 54553955 ps
T115 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.249426325 Jun 26 06:38:39 PM PDT 24 Jun 26 06:38:53 PM PDT 24 370239080 ps
T146 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1870687709 Jun 26 06:38:27 PM PDT 24 Jun 26 06:38:35 PM PDT 24 247293589 ps
T119 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.175888658 Jun 26 06:38:36 PM PDT 24 Jun 26 06:38:47 PM PDT 24 94793405 ps
T147 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1281287861 Jun 26 06:38:30 PM PDT 24 Jun 26 06:38:40 PM PDT 24 64373753 ps
T878 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.649046003 Jun 26 06:38:15 PM PDT 24 Jun 26 06:38:37 PM PDT 24 4670029539 ps
T174 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.98593651 Jun 26 06:38:11 PM PDT 24 Jun 26 06:38:16 PM PDT 24 183450548 ps
T117 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1849526384 Jun 26 06:38:33 PM PDT 24 Jun 26 06:38:46 PM PDT 24 122464588 ps
T120 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1493019798 Jun 26 06:38:49 PM PDT 24 Jun 26 06:39:01 PM PDT 24 89720067 ps
T136 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2107668804 Jun 26 06:38:13 PM PDT 24 Jun 26 06:38:21 PM PDT 24 109174973 ps
T175 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1360577676 Jun 26 06:38:50 PM PDT 24 Jun 26 06:39:00 PM PDT 24 107803107 ps
T176 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1559621516 Jun 26 06:38:33 PM PDT 24 Jun 26 06:38:43 PM PDT 24 357863320 ps
T879 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.460188826 Jun 26 06:38:11 PM PDT 24 Jun 26 06:38:17 PM PDT 24 85125807 ps
T140 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2211946670 Jun 26 06:38:41 PM PDT 24 Jun 26 06:38:53 PM PDT 24 107441394 ps
T880 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.180137175 Jun 26 06:38:38 PM PDT 24 Jun 26 06:38:49 PM PDT 24 25798358 ps
T881 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.4264438123 Jun 26 06:38:39 PM PDT 24 Jun 26 06:38:51 PM PDT 24 100610268 ps
T125 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3866653365 Jun 26 06:40:06 PM PDT 24 Jun 26 06:40:08 PM PDT 24 192875338 ps
T882 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1403060849 Jun 26 06:38:28 PM PDT 24 Jun 26 06:38:36 PM PDT 24 131347274 ps
T203 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3357894524 Jun 26 06:38:38 PM PDT 24 Jun 26 06:38:48 PM PDT 24 34917732 ps
T883 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2031183946 Jun 26 06:38:28 PM PDT 24 Jun 26 06:38:35 PM PDT 24 12987046 ps
T159 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1791226586 Jun 26 06:38:13 PM PDT 24 Jun 26 06:38:21 PM PDT 24 47840673 ps
T134 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3464681164 Jun 26 06:38:32 PM PDT 24 Jun 26 06:38:42 PM PDT 24 133879923 ps
T132 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3200611053 Jun 26 06:38:14 PM PDT 24 Jun 26 06:38:25 PM PDT 24 477117539 ps
T884 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.4171291120 Jun 26 06:38:30 PM PDT 24 Jun 26 06:38:45 PM PDT 24 1387527915 ps
T122 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2187027763 Jun 26 06:38:25 PM PDT 24 Jun 26 06:38:33 PM PDT 24 345621265 ps
T160 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3626162267 Jun 26 06:38:14 PM PDT 24 Jun 26 06:38:22 PM PDT 24 88955807 ps
T885 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.917568526 Jun 26 06:38:30 PM PDT 24 Jun 26 06:38:39 PM PDT 24 241696661 ps
T886 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.431891541 Jun 26 06:38:27 PM PDT 24 Jun 26 06:38:34 PM PDT 24 19342548 ps
T138 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2556340975 Jun 26 06:38:38 PM PDT 24 Jun 26 06:38:52 PM PDT 24 182468840 ps
T204 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2151901407 Jun 26 06:38:12 PM PDT 24 Jun 26 06:38:17 PM PDT 24 43244958 ps
T143 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.297220679 Jun 26 06:38:38 PM PDT 24 Jun 26 06:38:51 PM PDT 24 447737584 ps
T205 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1837362339 Jun 26 06:38:38 PM PDT 24 Jun 26 06:38:50 PM PDT 24 16518396 ps
T130 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1639973123 Jun 26 06:38:37 PM PDT 24 Jun 26 06:38:51 PM PDT 24 120159770 ps
T887 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.868867740 Jun 26 06:38:26 PM PDT 24 Jun 26 06:38:33 PM PDT 24 57734094 ps
T888 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3033854401 Jun 26 06:38:28 PM PDT 24 Jun 26 06:38:36 PM PDT 24 64935316 ps
T206 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3219829845 Jun 26 06:38:16 PM PDT 24 Jun 26 06:38:24 PM PDT 24 159576636 ps
T126 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3860412699 Jun 26 06:38:13 PM PDT 24 Jun 26 06:38:21 PM PDT 24 123467398 ps
T207 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3667425561 Jun 26 06:38:38 PM PDT 24 Jun 26 06:38:50 PM PDT 24 47807149 ps
T889 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.313557005 Jun 26 06:38:13 PM PDT 24 Jun 26 06:38:22 PM PDT 24 335468709 ps
T208 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.224682164 Jun 26 06:38:25 PM PDT 24 Jun 26 06:38:31 PM PDT 24 72210393 ps
T890 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3823163437 Jun 26 06:38:28 PM PDT 24 Jun 26 06:38:42 PM PDT 24 263370600 ps
T891 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3816836462 Jun 26 06:38:16 PM PDT 24 Jun 26 06:38:24 PM PDT 24 214650208 ps
T892 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1718978156 Jun 26 06:39:02 PM PDT 24 Jun 26 06:39:10 PM PDT 24 24246404 ps
T144 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2947014719 Jun 26 06:38:26 PM PDT 24 Jun 26 06:38:34 PM PDT 24 49269605 ps
T161 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.4203707230 Jun 26 06:38:32 PM PDT 24 Jun 26 06:38:42 PM PDT 24 177834571 ps
T195 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2717047862 Jun 26 06:38:25 PM PDT 24 Jun 26 06:38:31 PM PDT 24 36147368 ps
T209 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.812165570 Jun 26 06:38:11 PM PDT 24 Jun 26 06:38:16 PM PDT 24 85595099 ps
T893 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1877667634 Jun 26 06:38:37 PM PDT 24 Jun 26 06:38:48 PM PDT 24 14547203 ps
T894 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.513436942 Jun 26 06:38:28 PM PDT 24 Jun 26 06:38:36 PM PDT 24 88074239 ps
T123 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2494274168 Jun 26 06:38:13 PM PDT 24 Jun 26 06:38:21 PM PDT 24 61446888 ps
T162 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.972521104 Jun 26 06:38:11 PM PDT 24 Jun 26 06:38:14 PM PDT 24 17219563 ps
T895 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2135940244 Jun 26 06:38:37 PM PDT 24 Jun 26 06:38:51 PM PDT 24 90894516 ps
T896 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.20082153 Jun 26 06:38:50 PM PDT 24 Jun 26 06:38:59 PM PDT 24 49356285 ps
T897 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3713218453 Jun 26 06:38:12 PM PDT 24 Jun 26 06:38:20 PM PDT 24 406330524 ps
T898 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1891696801 Jun 26 06:38:17 PM PDT 24 Jun 26 06:38:26 PM PDT 24 1242837490 ps
T899 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2151012598 Jun 26 06:38:39 PM PDT 24 Jun 26 06:38:51 PM PDT 24 19612290 ps
T900 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2764964957 Jun 26 06:38:17 PM PDT 24 Jun 26 06:38:25 PM PDT 24 98374534 ps
T901 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.4021606865 Jun 26 06:38:33 PM PDT 24 Jun 26 06:38:42 PM PDT 24 15316126 ps
T902 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1286692029 Jun 26 06:38:26 PM PDT 24 Jun 26 06:38:32 PM PDT 24 57604169 ps
T903 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3346153514 Jun 26 06:38:27 PM PDT 24 Jun 26 06:38:34 PM PDT 24 223800805 ps
T163 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.396965755 Jun 26 06:38:10 PM PDT 24 Jun 26 06:38:15 PM PDT 24 433750363 ps
T904 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4093313467 Jun 26 06:38:13 PM PDT 24 Jun 26 06:38:21 PM PDT 24 27189380 ps
T905 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.529022002 Jun 26 06:38:39 PM PDT 24 Jun 26 06:38:50 PM PDT 24 49714402 ps
T196 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3992321002 Jun 26 06:39:16 PM PDT 24 Jun 26 06:39:22 PM PDT 24 14833317 ps
T906 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.357677820 Jun 26 06:38:12 PM PDT 24 Jun 26 06:38:19 PM PDT 24 115998610 ps
T907 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3717055416 Jun 26 06:38:30 PM PDT 24 Jun 26 06:38:56 PM PDT 24 1031787326 ps
T908 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3492403220 Jun 26 06:38:12 PM PDT 24 Jun 26 06:38:21 PM PDT 24 380420982 ps
T909 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.118596675 Jun 26 06:38:27 PM PDT 24 Jun 26 06:38:35 PM PDT 24 62491009 ps
T910 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2609284243 Jun 26 06:38:27 PM PDT 24 Jun 26 06:38:34 PM PDT 24 14577992 ps
T911 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1432434612 Jun 26 06:38:37 PM PDT 24 Jun 26 06:38:48 PM PDT 24 71822914 ps
T912 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.167998861 Jun 26 06:38:38 PM PDT 24 Jun 26 06:38:49 PM PDT 24 24805484 ps
T913 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.185086942 Jun 26 06:38:28 PM PDT 24 Jun 26 06:38:46 PM PDT 24 1662168168 ps
T914 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1487359563 Jun 26 06:38:29 PM PDT 24 Jun 26 06:38:41 PM PDT 24 443592675 ps
T915 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.216416702 Jun 26 06:38:16 PM PDT 24 Jun 26 06:38:24 PM PDT 24 56184347 ps
T197 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.4099830265 Jun 26 06:38:11 PM PDT 24 Jun 26 06:38:16 PM PDT 24 13003086 ps
T916 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2756693939 Jun 26 06:38:32 PM PDT 24 Jun 26 06:38:44 PM PDT 24 568266872 ps
T198 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1021267308 Jun 26 06:38:13 PM PDT 24 Jun 26 06:38:21 PM PDT 24 91962666 ps
T917 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1937729523 Jun 26 06:38:11 PM PDT 24 Jun 26 06:38:18 PM PDT 24 597728067 ps
T918 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.4182625983 Jun 26 06:38:29 PM PDT 24 Jun 26 06:38:38 PM PDT 24 151659749 ps
T199 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.365459933 Jun 26 06:38:49 PM PDT 24 Jun 26 06:38:59 PM PDT 24 47245334 ps
T919 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2050125844 Jun 26 06:38:29 PM PDT 24 Jun 26 06:38:42 PM PDT 24 1465406397 ps
T920 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2089281110 Jun 26 06:38:13 PM PDT 24 Jun 26 06:38:21 PM PDT 24 31466035 ps
T921 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.979786307 Jun 26 06:38:30 PM PDT 24 Jun 26 06:38:39 PM PDT 24 81525506 ps
T922 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1217354062 Jun 26 06:38:27 PM PDT 24 Jun 26 06:38:36 PM PDT 24 1248271581 ps
T923 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1491824518 Jun 26 06:38:13 PM PDT 24 Jun 26 06:38:22 PM PDT 24 371407366 ps
T924 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1757575241 Jun 26 06:38:32 PM PDT 24 Jun 26 06:38:41 PM PDT 24 22523578 ps
T925 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3082400120 Jun 26 06:38:37 PM PDT 24 Jun 26 06:38:48 PM PDT 24 36442317 ps
T926 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1883205026 Jun 26 06:38:13 PM PDT 24 Jun 26 06:38:21 PM PDT 24 41284456 ps
T927 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1800384088 Jun 26 06:38:30 PM PDT 24 Jun 26 06:38:40 PM PDT 24 95589914 ps
T928 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1386719721 Jun 26 06:38:40 PM PDT 24 Jun 26 06:38:51 PM PDT 24 16084110 ps
T929 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.83061078 Jun 26 06:38:37 PM PDT 24 Jun 26 06:38:48 PM PDT 24 15711474 ps
T930 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1723037828 Jun 26 06:38:42 PM PDT 24 Jun 26 06:38:54 PM PDT 24 141850844 ps
T931 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.375376939 Jun 26 06:38:12 PM PDT 24 Jun 26 06:38:20 PM PDT 24 259173535 ps
T932 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1646276954 Jun 26 06:38:39 PM PDT 24 Jun 26 06:38:50 PM PDT 24 16954932 ps
T933 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3277156957 Jun 26 06:38:10 PM PDT 24 Jun 26 06:38:14 PM PDT 24 283787295 ps
T934 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.414363935 Jun 26 06:38:14 PM PDT 24 Jun 26 06:38:22 PM PDT 24 145111474 ps
T935 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.220739519 Jun 26 06:39:03 PM PDT 24 Jun 26 06:39:12 PM PDT 24 40690576 ps
T936 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3388866919 Jun 26 06:38:27 PM PDT 24 Jun 26 06:38:34 PM PDT 24 59378850 ps
T937 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.728523680 Jun 26 06:38:29 PM PDT 24 Jun 26 06:38:37 PM PDT 24 143546395 ps
T938 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3996057218 Jun 26 06:38:28 PM PDT 24 Jun 26 06:38:35 PM PDT 24 182587163 ps
T939 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.835208064 Jun 26 06:38:32 PM PDT 24 Jun 26 06:38:58 PM PDT 24 969029752 ps
T940 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.753425387 Jun 26 06:38:11 PM PDT 24 Jun 26 06:38:16 PM PDT 24 36889095 ps
T941 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.97953120 Jun 26 06:38:39 PM PDT 24 Jun 26 06:38:51 PM PDT 24 510207143 ps
T942 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3503325229 Jun 26 06:38:47 PM PDT 24 Jun 26 06:38:58 PM PDT 24 290393412 ps
T200 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1205567320 Jun 26 06:38:51 PM PDT 24 Jun 26 06:39:01 PM PDT 24 55135940 ps
T943 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3990128971 Jun 26 06:38:26 PM PDT 24 Jun 26 06:38:33 PM PDT 24 694154524 ps
T944 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2120854989 Jun 26 06:38:34 PM PDT 24 Jun 26 06:38:45 PM PDT 24 110488898 ps
T945 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3406065347 Jun 26 06:38:42 PM PDT 24 Jun 26 06:38:53 PM PDT 24 11717508 ps
T201 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4170498741 Jun 26 06:38:34 PM PDT 24 Jun 26 06:38:44 PM PDT 24 59959364 ps
T946 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2756219639 Jun 26 06:38:15 PM PDT 24 Jun 26 06:38:24 PM PDT 24 153231685 ps
T947 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2991299101 Jun 26 06:38:10 PM PDT 24 Jun 26 06:38:30 PM PDT 24 3458079914 ps
T139 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.710929816 Jun 26 06:38:40 PM PDT 24 Jun 26 06:38:53 PM PDT 24 241135053 ps
T948 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2713705876 Jun 26 06:38:38 PM PDT 24 Jun 26 06:38:49 PM PDT 24 240978194 ps
T141 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1374622998 Jun 26 06:38:49 PM PDT 24 Jun 26 06:38:59 PM PDT 24 333013318 ps
T949 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1314788822 Jun 26 06:38:39 PM PDT 24 Jun 26 06:38:52 PM PDT 24 595220978 ps
T950 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.852378638 Jun 26 06:38:28 PM PDT 24 Jun 26 06:38:35 PM PDT 24 76255127 ps
T951 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1510827438 Jun 26 06:38:05 PM PDT 24 Jun 26 06:38:08 PM PDT 24 60189772 ps
T952 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.190736287 Jun 26 06:38:32 PM PDT 24 Jun 26 06:38:42 PM PDT 24 263755917 ps
T953 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2397371143 Jun 26 06:38:14 PM PDT 24 Jun 26 06:38:23 PM PDT 24 28501671 ps
T142 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2207687584 Jun 26 06:38:33 PM PDT 24 Jun 26 06:38:45 PM PDT 24 51897416 ps
T954 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3125071404 Jun 26 06:38:14 PM PDT 24 Jun 26 06:38:23 PM PDT 24 144322287 ps
T955 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1583397249 Jun 26 06:38:13 PM PDT 24 Jun 26 06:38:24 PM PDT 24 1096366693 ps
T956 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.529704522 Jun 26 06:38:30 PM PDT 24 Jun 26 06:38:39 PM PDT 24 99268664 ps
T957 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2938006696 Jun 26 06:38:12 PM PDT 24 Jun 26 06:38:17 PM PDT 24 176786766 ps
T958 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1272528676 Jun 26 06:38:50 PM PDT 24 Jun 26 06:38:59 PM PDT 24 18579792 ps
T959 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.720823903 Jun 26 06:38:42 PM PDT 24 Jun 26 06:38:52 PM PDT 24 16421637 ps
T960 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.253151809 Jun 26 06:38:39 PM PDT 24 Jun 26 06:38:51 PM PDT 24 49449401 ps
T961 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1676590319 Jun 26 06:38:11 PM PDT 24 Jun 26 06:38:17 PM PDT 24 149586318 ps
T962 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1724887674 Jun 26 06:38:39 PM PDT 24 Jun 26 06:38:52 PM PDT 24 211998675 ps
T963 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3212766806 Jun 26 06:38:28 PM PDT 24 Jun 26 06:38:36 PM PDT 24 49319667 ps
T964 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2200355022 Jun 26 06:38:11 PM PDT 24 Jun 26 06:38:16 PM PDT 24 578491681 ps
T965 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4209544611 Jun 26 06:38:27 PM PDT 24 Jun 26 06:38:39 PM PDT 24 957395860 ps
T966 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1587664371 Jun 26 06:38:49 PM PDT 24 Jun 26 06:39:00 PM PDT 24 106558203 ps
T967 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.311138575 Jun 26 06:38:49 PM PDT 24 Jun 26 06:38:59 PM PDT 24 24587232 ps
T968 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.602647360 Jun 26 06:38:41 PM PDT 24 Jun 26 06:38:51 PM PDT 24 70705423 ps
T969 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.744055437 Jun 26 06:38:32 PM PDT 24 Jun 26 06:38:42 PM PDT 24 86904070 ps
T124 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.711438024 Jun 26 06:38:42 PM PDT 24 Jun 26 06:38:54 PM PDT 24 217517084 ps
T970 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3329177999 Jun 26 06:38:28 PM PDT 24 Jun 26 06:38:37 PM PDT 24 181865459 ps
T133 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3293203812 Jun 26 06:38:17 PM PDT 24 Jun 26 06:38:26 PM PDT 24 59678502 ps
T971 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3415240142 Jun 26 06:38:13 PM PDT 24 Jun 26 06:38:24 PM PDT 24 368419389 ps
T137 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3827735753 Jun 26 06:38:11 PM PDT 24 Jun 26 06:38:18 PM PDT 24 289757279 ps
T972 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1363760994 Jun 26 06:38:26 PM PDT 24 Jun 26 06:38:34 PM PDT 24 63745092 ps
T973 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2576121906 Jun 26 06:38:38 PM PDT 24 Jun 26 06:38:50 PM PDT 24 50149706 ps
T974 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1945940235 Jun 26 06:38:42 PM PDT 24 Jun 26 06:38:53 PM PDT 24 34456438 ps
T975 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3266777055 Jun 26 06:38:30 PM PDT 24 Jun 26 06:38:39 PM PDT 24 62559350 ps
T976 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1090792461 Jun 26 06:38:28 PM PDT 24 Jun 26 06:38:36 PM PDT 24 121898849 ps
T977 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.682702841 Jun 26 06:38:39 PM PDT 24 Jun 26 06:38:51 PM PDT 24 55464132 ps
T978 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3443028288 Jun 26 06:38:34 PM PDT 24 Jun 26 06:38:48 PM PDT 24 1543399784 ps
T131 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.980738777 Jun 26 06:38:13 PM PDT 24 Jun 26 06:38:21 PM PDT 24 105194763 ps
T979 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2143274840 Jun 26 06:38:16 PM PDT 24 Jun 26 06:38:24 PM PDT 24 49618722 ps
T980 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3298990197 Jun 26 06:38:17 PM PDT 24 Jun 26 06:38:24 PM PDT 24 126950922 ps
T981 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1247584887 Jun 26 06:38:27 PM PDT 24 Jun 26 06:38:35 PM PDT 24 28624594 ps
T982 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3390897012 Jun 26 06:38:38 PM PDT 24 Jun 26 06:38:50 PM PDT 24 106802405 ps
T983 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1863711033 Jun 26 06:38:27 PM PDT 24 Jun 26 06:38:34 PM PDT 24 181158632 ps
T984 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1218805530 Jun 26 06:38:13 PM PDT 24 Jun 26 06:38:22 PM PDT 24 192673950 ps
T985 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2852811349 Jun 26 06:38:32 PM PDT 24 Jun 26 06:38:50 PM PDT 24 1085399860 ps
T128 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2668582496 Jun 26 06:38:27 PM PDT 24 Jun 26 06:38:36 PM PDT 24 171548980 ps
T986 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3458851893 Jun 26 06:38:50 PM PDT 24 Jun 26 06:38:59 PM PDT 24 25169521 ps
T987 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3168311476 Jun 26 06:38:30 PM PDT 24 Jun 26 06:38:40 PM PDT 24 163290424 ps
T988 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1882703516 Jun 26 06:38:02 PM PDT 24 Jun 26 06:38:06 PM PDT 24 35653867 ps
T129 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.674541951 Jun 26 06:38:49 PM PDT 24 Jun 26 06:39:00 PM PDT 24 69491053 ps
T989 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4117239985 Jun 26 06:38:30 PM PDT 24 Jun 26 06:38:43 PM PDT 24 356319332 ps
T990 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2066978324 Jun 26 06:38:32 PM PDT 24 Jun 26 06:38:42 PM PDT 24 20274581 ps
T991 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.653489096 Jun 26 06:38:28 PM PDT 24 Jun 26 06:38:37 PM PDT 24 46379163 ps
T202 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1799609844 Jun 26 06:38:27 PM PDT 24 Jun 26 06:38:34 PM PDT 24 23479617 ps
T992 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1592436499 Jun 26 06:38:13 PM PDT 24 Jun 26 06:38:20 PM PDT 24 131048139 ps
T993 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2203743160 Jun 26 06:38:14 PM PDT 24 Jun 26 06:38:28 PM PDT 24 826435159 ps
T994 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2916948981 Jun 26 06:38:12 PM PDT 24 Jun 26 06:38:17 PM PDT 24 145042779 ps
T995 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3439864396 Jun 26 06:38:27 PM PDT 24 Jun 26 06:38:34 PM PDT 24 19062461 ps
T996 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2011270412 Jun 26 06:38:32 PM PDT 24 Jun 26 06:38:43 PM PDT 24 179380887 ps
T135 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.760384609 Jun 26 06:38:33 PM PDT 24 Jun 26 06:38:43 PM PDT 24 126514057 ps
T997 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3227357352 Jun 26 06:38:34 PM PDT 24 Jun 26 06:38:44 PM PDT 24 87926741 ps

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.3098818737
Short name T5
Test name
Test status
Simulation time 4831911389 ps
CPU time 38.25 seconds
Started Jun 26 06:53:54 PM PDT 24
Finished Jun 26 06:54:35 PM PDT 24
Peak memory 226320 kb
Host smart-c6a12aea-0fcd-4eaf-bbf3-fa4359ec5449
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098818737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.3098818737
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.2092829889
Short name T15
Test name
Test status
Simulation time 113464482826 ps
CPU time 635.22 seconds
Started Jun 26 06:51:51 PM PDT 24
Finished Jun 26 07:02:28 PM PDT 24
Peak memory 284176 kb
Host smart-89c0f0b2-e5cf-4387-a2e9-e6e57b8df63e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2092829889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.2092829889
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.174467060
Short name T23
Test name
Test status
Simulation time 417350989 ps
CPU time 10.58 seconds
Started Jun 26 06:53:16 PM PDT 24
Finished Jun 26 06:53:28 PM PDT 24
Peak memory 218776 kb
Host smart-10ffae12-8e51-4c82-bc14-894661555a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174467060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.174467060
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.3822660833
Short name T11
Test name
Test status
Simulation time 15645402 ps
CPU time 1.06 seconds
Started Jun 26 06:56:36 PM PDT 24
Finished Jun 26 06:56:39 PM PDT 24
Peak memory 209180 kb
Host smart-a1502c63-73de-4bd0-9414-661868f2765c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822660833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.3822660833
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.1846858255
Short name T25
Test name
Test status
Simulation time 276253420 ps
CPU time 12.17 seconds
Started Jun 26 06:53:29 PM PDT 24
Finished Jun 26 06:53:44 PM PDT 24
Peak memory 219308 kb
Host smart-45c5b385-1d43-4afe-8e6d-0adc48f643fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846858255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.1846858255
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.4254174206
Short name T55
Test name
Test status
Simulation time 336421160 ps
CPU time 8.85 seconds
Started Jun 26 06:57:04 PM PDT 24
Finished Jun 26 06:57:17 PM PDT 24
Peak memory 218620 kb
Host smart-20a093fe-fd16-4fb1-bf80-ffca58b29b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254174206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.4254174206
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.644411754
Short name T52
Test name
Test status
Simulation time 108604336754 ps
CPU time 1181.78 seconds
Started Jun 26 06:53:42 PM PDT 24
Finished Jun 26 07:13:26 PM PDT 24
Peak memory 333340 kb
Host smart-18f0712d-0d08-45ee-a92c-c3b19aabdc35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=644411754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.644411754
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.1786770942
Short name T59
Test name
Test status
Simulation time 201368183 ps
CPU time 45.74 seconds
Started Jun 26 06:52:26 PM PDT 24
Finished Jun 26 06:53:13 PM PDT 24
Peak memory 282240 kb
Host smart-4e1b0c05-70b4-475d-9c05-0d17a4f025f4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786770942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1786770942
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2629523034
Short name T116
Test name
Test status
Simulation time 273366964 ps
CPU time 1.69 seconds
Started Jun 26 06:38:26 PM PDT 24
Finished Jun 26 06:38:33 PM PDT 24
Peak memory 222692 kb
Host smart-165f3de5-6be6-44cd-b80b-5ba549a4e3a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262952
3034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2629523034
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.136331146
Short name T21
Test name
Test status
Simulation time 820194703 ps
CPU time 12.6 seconds
Started Jun 26 06:52:44 PM PDT 24
Finished Jun 26 06:52:58 PM PDT 24
Peak memory 218388 kb
Host smart-9b7f5c76-69cd-491f-8028-9d310c63f7e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136331146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.136331146
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.249426325
Short name T115
Test name
Test status
Simulation time 370239080 ps
CPU time 3.63 seconds
Started Jun 26 06:38:39 PM PDT 24
Finished Jun 26 06:38:53 PM PDT 24
Peak memory 217448 kb
Host smart-6f6df3a9-77fe-4c9f-acba-2a6dc3727172
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249426325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.249426325
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.2573265395
Short name T30
Test name
Test status
Simulation time 1066849677 ps
CPU time 6.63 seconds
Started Jun 26 06:53:27 PM PDT 24
Finished Jun 26 06:53:34 PM PDT 24
Peak memory 217616 kb
Host smart-dbae0b1c-4a23-4dae-a729-0d2a167fa381
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573265395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.2573265395
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3458294048
Short name T172
Test name
Test status
Simulation time 327627425 ps
CPU time 9.01 seconds
Started Jun 26 06:56:36 PM PDT 24
Finished Jun 26 06:56:46 PM PDT 24
Peak memory 218644 kb
Host smart-d62cff8e-9606-4eda-b6ab-bfc18ed84f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458294048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3458294048
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.1978720842
Short name T279
Test name
Test status
Simulation time 13344519415 ps
CPU time 233.14 seconds
Started Jun 26 06:53:32 PM PDT 24
Finished Jun 26 06:57:27 PM PDT 24
Peak memory 419184 kb
Host smart-8cb95237-48b2-403b-b51e-ae53061dbc18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978720842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.1978720842
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.396965755
Short name T163
Test name
Test status
Simulation time 433750363 ps
CPU time 2.76 seconds
Started Jun 26 06:38:10 PM PDT 24
Finished Jun 26 06:38:15 PM PDT 24
Peak memory 209264 kb
Host smart-538b11b9-0664-4c4f-bf5a-ade1799a7865
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396965755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash
.396965755
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.710929816
Short name T139
Test name
Test status
Simulation time 241135053 ps
CPU time 2.7 seconds
Started Jun 26 06:38:40 PM PDT 24
Finished Jun 26 06:38:53 PM PDT 24
Peak memory 222012 kb
Host smart-55dd844c-1b3a-4635-a71b-2fcfa0c4d228
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710929816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_
err.710929816
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.1840267809
Short name T54
Test name
Test status
Simulation time 1520443013 ps
CPU time 13.49 seconds
Started Jun 26 06:54:41 PM PDT 24
Finished Jun 26 06:54:56 PM PDT 24
Peak memory 218716 kb
Host smart-79ffcb79-6fed-40c6-9a24-c3ebbfa5597b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840267809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1840267809
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.2444679454
Short name T224
Test name
Test status
Simulation time 2405253334 ps
CPU time 51.27 seconds
Started Jun 26 06:54:30 PM PDT 24
Finished Jun 26 06:55:24 PM PDT 24
Peak memory 267808 kb
Host smart-05e2894f-b7f8-4891-ab83-3d594f1ffef3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444679454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.2444679454
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.4250177835
Short name T48
Test name
Test status
Simulation time 586214213 ps
CPU time 11.7 seconds
Started Jun 26 06:53:43 PM PDT 24
Finished Jun 26 06:53:56 PM PDT 24
Peak memory 226208 kb
Host smart-fa150bcd-d0bc-4b27-b4c7-eba3a3328e93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250177835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.4250177835
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1314788822
Short name T949
Test name
Test status
Simulation time 595220978 ps
CPU time 2.46 seconds
Started Jun 26 06:38:39 PM PDT 24
Finished Jun 26 06:38:52 PM PDT 24
Peak memory 217740 kb
Host smart-281e9c3b-201a-4bb8-b733-78f2a034b9e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314788822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1314788822
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.591679080
Short name T27
Test name
Test status
Simulation time 3044595559 ps
CPU time 61.09 seconds
Started Jun 26 06:54:17 PM PDT 24
Finished Jun 26 06:55:20 PM PDT 24
Peak memory 249808 kb
Host smart-887db613-8d6f-4e35-9ca8-3e932bc5b3a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591679080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.591679080
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2187027763
Short name T122
Test name
Test status
Simulation time 345621265 ps
CPU time 2.95 seconds
Started Jun 26 06:38:25 PM PDT 24
Finished Jun 26 06:38:33 PM PDT 24
Peak memory 222628 kb
Host smart-91cf0cc1-8625-4d30-9f2e-80131a29613a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187027763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.2187027763
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.760384609
Short name T135
Test name
Test status
Simulation time 126514057 ps
CPU time 1.92 seconds
Started Jun 26 06:38:33 PM PDT 24
Finished Jun 26 06:38:43 PM PDT 24
Peak memory 221980 kb
Host smart-55081c14-940f-4c58-8c77-2fa5c73412e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760384609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_e
rr.760384609
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.980738777
Short name T131
Test name
Test status
Simulation time 105194763 ps
CPU time 2.34 seconds
Started Jun 26 06:38:13 PM PDT 24
Finished Jun 26 06:38:21 PM PDT 24
Peak memory 221960 kb
Host smart-08464ecf-aab2-4fc7-a873-71cb8db12398
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980738777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_e
rr.980738777
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3416749215
Short name T145
Test name
Test status
Simulation time 160139511 ps
CPU time 2.04 seconds
Started Jun 26 06:38:24 PM PDT 24
Finished Jun 26 06:38:30 PM PDT 24
Peak memory 210656 kb
Host smart-e2de8f58-e44b-4d2f-b054-aaed0d4f6d11
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416749215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3416749215
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3219829845
Short name T206
Test name
Test status
Simulation time 159576636 ps
CPU time 0.88 seconds
Started Jun 26 06:38:16 PM PDT 24
Finished Jun 26 06:38:24 PM PDT 24
Peak memory 209304 kb
Host smart-0f32eccd-a957-4722-a23a-aa6b31838d9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219829845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3219829845
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.4099830265
Short name T197
Test name
Test status
Simulation time 13003086 ps
CPU time 0.95 seconds
Started Jun 26 06:38:11 PM PDT 24
Finished Jun 26 06:38:16 PM PDT 24
Peak memory 209776 kb
Host smart-4f092548-95d7-410e-a2bb-ab31035bdfaa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099830265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.4099830265
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.105174756
Short name T12
Test name
Test status
Simulation time 27048038 ps
CPU time 0.9 seconds
Started Jun 26 06:57:06 PM PDT 24
Finished Jun 26 06:57:11 PM PDT 24
Peak memory 212192 kb
Host smart-cd5e501d-52d5-4de2-9244-aa031a457f67
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105174756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ct
rl_volatile_unlock_smoke.105174756
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1374622998
Short name T141
Test name
Test status
Simulation time 333013318 ps
CPU time 1.69 seconds
Started Jun 26 06:38:49 PM PDT 24
Finished Jun 26 06:38:59 PM PDT 24
Peak memory 222100 kb
Host smart-dfb81a34-87ba-4709-b30a-b6351b583e2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374622998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1374622998
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2207687584
Short name T142
Test name
Test status
Simulation time 51897416 ps
CPU time 2.46 seconds
Started Jun 26 06:38:33 PM PDT 24
Finished Jun 26 06:38:45 PM PDT 24
Peak memory 217652 kb
Host smart-c0f2f384-57a3-4841-9321-21a225449540
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207687584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.2207687584
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.2696338588
Short name T53
Test name
Test status
Simulation time 22323301601 ps
CPU time 580.73 seconds
Started Jun 26 06:54:54 PM PDT 24
Finished Jun 26 07:04:36 PM PDT 24
Peak memory 284064 kb
Host smart-2604eca4-bc32-4fc6-830b-d2db56794418
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2696338588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.2696338588
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.669186541
Short name T213
Test name
Test status
Simulation time 116452628 ps
CPU time 0.76 seconds
Started Jun 26 06:51:50 PM PDT 24
Finished Jun 26 06:51:53 PM PDT 24
Peak memory 209176 kb
Host smart-412a8b56-cd57-499a-8d49-4d938521fd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669186541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.669186541
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1368004626
Short name T211
Test name
Test status
Simulation time 10501727 ps
CPU time 0.91 seconds
Started Jun 26 06:52:27 PM PDT 24
Finished Jun 26 06:52:30 PM PDT 24
Peak memory 209212 kb
Host smart-96af2019-205d-46a0-8215-79db9d956acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368004626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1368004626
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.1029227795
Short name T212
Test name
Test status
Simulation time 120735166 ps
CPU time 0.85 seconds
Started Jun 26 06:53:03 PM PDT 24
Finished Jun 26 06:53:06 PM PDT 24
Peak memory 209228 kb
Host smart-22ec12ce-969d-4d3e-bdc7-55537701d48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029227795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.1029227795
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.1901991204
Short name T155
Test name
Test status
Simulation time 11895279 ps
CPU time 0.99 seconds
Started Jun 26 06:53:17 PM PDT 24
Finished Jun 26 06:53:20 PM PDT 24
Peak memory 209228 kb
Host smart-4d379cfa-65a8-423d-a26d-2cfa7894637d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901991204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1901991204
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.297220679
Short name T143
Test name
Test status
Simulation time 447737584 ps
CPU time 2.72 seconds
Started Jun 26 06:38:38 PM PDT 24
Finished Jun 26 06:38:51 PM PDT 24
Peak memory 222012 kb
Host smart-0223d128-b978-4e2f-aeb0-0fc87c0477f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297220679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_
err.297220679
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3293203812
Short name T133
Test name
Test status
Simulation time 59678502 ps
CPU time 2.6 seconds
Started Jun 26 06:38:17 PM PDT 24
Finished Jun 26 06:38:26 PM PDT 24
Peak memory 217552 kb
Host smart-86e03096-06eb-42ee-9d61-bf3c6813f9eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293203812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.3293203812
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2668582496
Short name T128
Test name
Test status
Simulation time 171548980 ps
CPU time 2.21 seconds
Started Jun 26 06:38:27 PM PDT 24
Finished Jun 26 06:38:36 PM PDT 24
Peak memory 221880 kb
Host smart-cf5a0be0-068e-4a2e-80b2-3b32ea34e291
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668582496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.2668582496
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3226593590
Short name T114
Test name
Test status
Simulation time 156236202 ps
CPU time 1.92 seconds
Started Jun 26 06:38:29 PM PDT 24
Finished Jun 26 06:38:38 PM PDT 24
Peak memory 221848 kb
Host smart-bef2aa1c-50c4-4531-862e-480d3b7949c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226593590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3226593590
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.170774471
Short name T37
Test name
Test status
Simulation time 4943284247 ps
CPU time 50.84 seconds
Started Jun 26 06:54:28 PM PDT 24
Finished Jun 26 06:55:21 PM PDT 24
Peak memory 267828 kb
Host smart-1d621460-f2ed-4c97-9c7a-9e2710b1c2c2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170774471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_state_failure.170774471
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2756219639
Short name T946
Test name
Test status
Simulation time 153231685 ps
CPU time 1.77 seconds
Started Jun 26 06:38:15 PM PDT 24
Finished Jun 26 06:38:24 PM PDT 24
Peak memory 209424 kb
Host smart-a6d06286-0f20-468c-af74-e0d9c46d775e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756219639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.2756219639
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2397371143
Short name T953
Test name
Test status
Simulation time 28501671 ps
CPU time 1.54 seconds
Started Jun 26 06:38:14 PM PDT 24
Finished Jun 26 06:38:23 PM PDT 24
Peak memory 209296 kb
Host smart-85e9310d-9cbd-48bf-9231-dc93f22cb07c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397371143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.2397371143
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1883205026
Short name T926
Test name
Test status
Simulation time 41284456 ps
CPU time 0.86 seconds
Started Jun 26 06:38:13 PM PDT 24
Finished Jun 26 06:38:21 PM PDT 24
Peak memory 209860 kb
Host smart-b130bd1a-1b4f-4694-b070-c01b53a4a79f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883205026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.1883205026
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1592436499
Short name T992
Test name
Test status
Simulation time 131048139 ps
CPU time 1.26 seconds
Started Jun 26 06:38:13 PM PDT 24
Finished Jun 26 06:38:20 PM PDT 24
Peak memory 219084 kb
Host smart-ae3c4fb1-fc94-4b97-9e06-55f5cbed0cd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592436499 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1592436499
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1510827438
Short name T951
Test name
Test status
Simulation time 60189772 ps
CPU time 1.91 seconds
Started Jun 26 06:38:05 PM PDT 24
Finished Jun 26 06:38:08 PM PDT 24
Peak memory 209224 kb
Host smart-4ea56d69-e73f-4fad-a02a-385cf5b4c668
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510827438 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1510827438
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1583397249
Short name T955
Test name
Test status
Simulation time 1096366693 ps
CPU time 3.56 seconds
Started Jun 26 06:38:13 PM PDT 24
Finished Jun 26 06:38:24 PM PDT 24
Peak memory 208508 kb
Host smart-9966c58d-aa57-440c-86d7-d985c44ab08b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583397249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1583397249
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1080747114
Short name T149
Test name
Test status
Simulation time 356356913 ps
CPU time 4.48 seconds
Started Jun 26 06:38:12 PM PDT 24
Finished Jun 26 06:38:23 PM PDT 24
Peak memory 209216 kb
Host smart-e3497c9a-b0b7-4856-adca-b5ba688a958f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080747114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1080747114
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3277156957
Short name T933
Test name
Test status
Simulation time 283787295 ps
CPU time 2.24 seconds
Started Jun 26 06:38:10 PM PDT 24
Finished Jun 26 06:38:14 PM PDT 24
Peak memory 217392 kb
Host smart-d453b7b2-a79d-4c93-a9e9-fb6d9203ff21
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277156957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3277156957
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1937729523
Short name T917
Test name
Test status
Simulation time 597728067 ps
CPU time 2.85 seconds
Started Jun 26 06:38:11 PM PDT 24
Finished Jun 26 06:38:18 PM PDT 24
Peak memory 218616 kb
Host smart-1a5c3d4f-69e8-4919-8511-e3e809d0c638
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193772
9523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1937729523
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3713218453
Short name T897
Test name
Test status
Simulation time 406330524 ps
CPU time 1.64 seconds
Started Jun 26 06:38:12 PM PDT 24
Finished Jun 26 06:38:20 PM PDT 24
Peak memory 209124 kb
Host smart-9e8cecfa-c857-459c-8c02-e831567cf71e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713218453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3713218453
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.216416702
Short name T915
Test name
Test status
Simulation time 56184347 ps
CPU time 1.18 seconds
Started Jun 26 06:38:16 PM PDT 24
Finished Jun 26 06:38:24 PM PDT 24
Peak memory 209376 kb
Host smart-c6f567cc-662a-4658-9bdf-f7c39aada63f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216416702 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.216416702
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.414363935
Short name T934
Test name
Test status
Simulation time 145111474 ps
CPU time 1.65 seconds
Started Jun 26 06:38:14 PM PDT 24
Finished Jun 26 06:38:22 PM PDT 24
Peak memory 217640 kb
Host smart-571b4a3e-a148-4389-9886-5e51d71d88b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414363935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
same_csr_outstanding.414363935
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1676590319
Short name T961
Test name
Test status
Simulation time 149586318 ps
CPU time 2.89 seconds
Started Jun 26 06:38:11 PM PDT 24
Finished Jun 26 06:38:17 PM PDT 24
Peak memory 218528 kb
Host smart-8390bc5e-d5a5-4a2f-9f7b-ab068fc4fd1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676590319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1676590319
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3827735753
Short name T137
Test name
Test status
Simulation time 289757279 ps
CPU time 2.45 seconds
Started Jun 26 06:38:11 PM PDT 24
Finished Jun 26 06:38:18 PM PDT 24
Peak memory 217556 kb
Host smart-2be8de33-d4dc-4ee0-b104-8a23cb9eaaa8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827735753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3827735753
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.753425387
Short name T940
Test name
Test status
Simulation time 36889095 ps
CPU time 1.73 seconds
Started Jun 26 06:38:11 PM PDT 24
Finished Jun 26 06:38:16 PM PDT 24
Peak memory 209224 kb
Host smart-9d939774-91ae-4f59-ac2b-75817b593353
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753425387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.753425387
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3626162267
Short name T160
Test name
Test status
Simulation time 88955807 ps
CPU time 1.21 seconds
Started Jun 26 06:38:14 PM PDT 24
Finished Jun 26 06:38:22 PM PDT 24
Peak memory 217860 kb
Host smart-db6d581e-efde-43cf-8c7a-bee3b45892cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626162267 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3626162267
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.357677820
Short name T906
Test name
Test status
Simulation time 115998610 ps
CPU time 0.99 seconds
Started Jun 26 06:38:12 PM PDT 24
Finished Jun 26 06:38:19 PM PDT 24
Peak memory 209316 kb
Host smart-bb52fab3-65dc-4b93-a4ce-d5f1cb7f3bc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357677820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.357677820
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.460188826
Short name T879
Test name
Test status
Simulation time 85125807 ps
CPU time 2.55 seconds
Started Jun 26 06:38:11 PM PDT 24
Finished Jun 26 06:38:17 PM PDT 24
Peak memory 209216 kb
Host smart-d9831099-7d48-4383-a844-9d6906a93db4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460188826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.460188826
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3492403220
Short name T908
Test name
Test status
Simulation time 380420982 ps
CPU time 4.99 seconds
Started Jun 26 06:38:12 PM PDT 24
Finished Jun 26 06:38:21 PM PDT 24
Peak memory 208900 kb
Host smart-349abbd9-a433-4e50-a73b-131d2a9de0e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492403220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3492403220
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2991299101
Short name T947
Test name
Test status
Simulation time 3458079914 ps
CPU time 17.29 seconds
Started Jun 26 06:38:10 PM PDT 24
Finished Jun 26 06:38:30 PM PDT 24
Peak memory 209252 kb
Host smart-338a32dc-4e33-4798-a47c-8653f87ca2c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991299101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.2991299101
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1218805530
Short name T984
Test name
Test status
Simulation time 192673950 ps
CPU time 2.59 seconds
Started Jun 26 06:38:13 PM PDT 24
Finished Jun 26 06:38:22 PM PDT 24
Peak memory 217452 kb
Host smart-b368fec2-1527-4fc7-b55a-dba81b4f5340
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218805530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1218805530
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3200611053
Short name T132
Test name
Test status
Simulation time 477117539 ps
CPU time 3.37 seconds
Started Jun 26 06:38:14 PM PDT 24
Finished Jun 26 06:38:25 PM PDT 24
Peak memory 218620 kb
Host smart-9c75c9ce-c6b5-4922-a7e5-3daf3d8b9b13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320061
1053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3200611053
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.313557005
Short name T889
Test name
Test status
Simulation time 335468709 ps
CPU time 1.59 seconds
Started Jun 26 06:38:13 PM PDT 24
Finished Jun 26 06:38:22 PM PDT 24
Peak memory 209244 kb
Host smart-e6a86db3-a2ee-4c04-a0ab-22dd95f45ae5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313557005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.313557005
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1791226586
Short name T159
Test name
Test status
Simulation time 47840673 ps
CPU time 1.5 seconds
Started Jun 26 06:38:13 PM PDT 24
Finished Jun 26 06:38:21 PM PDT 24
Peak memory 211328 kb
Host smart-903a9111-272b-4135-b32d-295378fd3957
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791226586 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1791226586
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2151901407
Short name T204
Test name
Test status
Simulation time 43244958 ps
CPU time 0.95 seconds
Started Jun 26 06:38:12 PM PDT 24
Finished Jun 26 06:38:17 PM PDT 24
Peak memory 217372 kb
Host smart-0043e813-2b71-4031-96fb-eab5e3b8441c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151901407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.2151901407
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2200355022
Short name T964
Test name
Test status
Simulation time 578491681 ps
CPU time 1.88 seconds
Started Jun 26 06:38:11 PM PDT 24
Finished Jun 26 06:38:16 PM PDT 24
Peak memory 217604 kb
Host smart-a96e380e-ad17-4a8a-9a56-c664d253c443
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200355022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.2200355022
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2494274168
Short name T123
Test name
Test status
Simulation time 61446888 ps
CPU time 1.98 seconds
Started Jun 26 06:38:13 PM PDT 24
Finished Jun 26 06:38:21 PM PDT 24
Peak memory 222060 kb
Host smart-7e048871-8f5e-4788-93b7-c27a362a3d59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494274168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2494274168
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.180137175
Short name T880
Test name
Test status
Simulation time 25798358 ps
CPU time 1.64 seconds
Started Jun 26 06:38:38 PM PDT 24
Finished Jun 26 06:38:49 PM PDT 24
Peak memory 219260 kb
Host smart-0c591679-3c30-42d7-b339-99e44cd050a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180137175 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.180137175
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1646276954
Short name T932
Test name
Test status
Simulation time 16954932 ps
CPU time 1.11 seconds
Started Jun 26 06:38:39 PM PDT 24
Finished Jun 26 06:38:50 PM PDT 24
Peak memory 209424 kb
Host smart-0b04b98b-f0bf-43b7-93fe-2681c37a1d93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646276954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1646276954
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1272528676
Short name T958
Test name
Test status
Simulation time 18579792 ps
CPU time 1.22 seconds
Started Jun 26 06:38:50 PM PDT 24
Finished Jun 26 06:38:59 PM PDT 24
Peak memory 217528 kb
Host smart-66ff26d4-5c79-472d-8971-b7b8e8bd453f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272528676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.1272528676
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1493019798
Short name T120
Test name
Test status
Simulation time 89720067 ps
CPU time 3.62 seconds
Started Jun 26 06:38:49 PM PDT 24
Finished Jun 26 06:39:01 PM PDT 24
Peak memory 217496 kb
Host smart-f3c62ebd-8fe3-4882-bee7-0c65f81cea64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493019798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1493019798
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1756746607
Short name T118
Test name
Test status
Simulation time 98826140 ps
CPU time 1.48 seconds
Started Jun 26 06:38:42 PM PDT 24
Finished Jun 26 06:38:53 PM PDT 24
Peak memory 217700 kb
Host smart-e43439d8-2fc0-4355-8b2c-eab37c6450a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756746607 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1756746607
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.365459933
Short name T199
Test name
Test status
Simulation time 47245334 ps
CPU time 0.87 seconds
Started Jun 26 06:38:49 PM PDT 24
Finished Jun 26 06:38:59 PM PDT 24
Peak memory 208920 kb
Host smart-940e43db-8ec7-424e-b47a-e93d940881b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365459933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.365459933
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1837362339
Short name T205
Test name
Test status
Simulation time 16518396 ps
CPU time 1.05 seconds
Started Jun 26 06:38:38 PM PDT 24
Finished Jun 26 06:38:50 PM PDT 24
Peak memory 209380 kb
Host smart-4223c5ab-0b9d-4342-b0b7-cbfa629c11e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837362339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1837362339
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1639973123
Short name T130
Test name
Test status
Simulation time 120159770 ps
CPU time 4.63 seconds
Started Jun 26 06:38:37 PM PDT 24
Finished Jun 26 06:38:51 PM PDT 24
Peak memory 217492 kb
Host smart-34bff66d-598d-4cfd-ab17-9cddd44b7a1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639973123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1639973123
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2556340975
Short name T138
Test name
Test status
Simulation time 182468840 ps
CPU time 3.79 seconds
Started Jun 26 06:38:38 PM PDT 24
Finished Jun 26 06:38:52 PM PDT 24
Peak memory 217524 kb
Host smart-7db4c85e-70ba-4691-853c-77fc2ccbb553
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556340975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.2556340975
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.602647360
Short name T968
Test name
Test status
Simulation time 70705423 ps
CPU time 0.98 seconds
Started Jun 26 06:38:41 PM PDT 24
Finished Jun 26 06:38:51 PM PDT 24
Peak memory 217616 kb
Host smart-d6eabea0-f7f3-4953-aaa0-83b7cfdb3a1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602647360 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.602647360
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.83061078
Short name T929
Test name
Test status
Simulation time 15711474 ps
CPU time 1.1 seconds
Started Jun 26 06:38:37 PM PDT 24
Finished Jun 26 06:38:48 PM PDT 24
Peak memory 208776 kb
Host smart-e510251b-6e8f-4440-86f2-99bcce05e290
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83061078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.83061078
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3250032763
Short name T121
Test name
Test status
Simulation time 57222138 ps
CPU time 1.26 seconds
Started Jun 26 06:38:39 PM PDT 24
Finished Jun 26 06:38:51 PM PDT 24
Peak memory 211452 kb
Host smart-d144b6c4-a4f8-4e29-b462-818019ce27b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250032763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3250032763
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2576121906
Short name T973
Test name
Test status
Simulation time 50149706 ps
CPU time 1.7 seconds
Started Jun 26 06:38:38 PM PDT 24
Finished Jun 26 06:38:50 PM PDT 24
Peak memory 217584 kb
Host smart-4bda92a0-cccc-4b94-8261-45a910ee03bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576121906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2576121906
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1723037828
Short name T930
Test name
Test status
Simulation time 141850844 ps
CPU time 1.82 seconds
Started Jun 26 06:38:42 PM PDT 24
Finished Jun 26 06:38:54 PM PDT 24
Peak memory 222696 kb
Host smart-95c049ab-6381-4464-bc07-f9bd646ecdb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723037828 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1723037828
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.311138575
Short name T967
Test name
Test status
Simulation time 24587232 ps
CPU time 0.84 seconds
Started Jun 26 06:38:49 PM PDT 24
Finished Jun 26 06:38:59 PM PDT 24
Peak memory 209248 kb
Host smart-570190e2-c96e-44d8-9ee3-adf890ab1434
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311138575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.311138575
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3082400120
Short name T925
Test name
Test status
Simulation time 36442317 ps
CPU time 1.61 seconds
Started Jun 26 06:38:37 PM PDT 24
Finished Jun 26 06:38:48 PM PDT 24
Peak memory 217564 kb
Host smart-f7c397dd-bfa6-43d6-aa2f-5de1a571f6db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082400120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.3082400120
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2135940244
Short name T895
Test name
Test status
Simulation time 90894516 ps
CPU time 3.86 seconds
Started Jun 26 06:38:37 PM PDT 24
Finished Jun 26 06:38:51 PM PDT 24
Peak memory 217516 kb
Host smart-eef9622e-0b14-4ed5-9adc-b65646cee8c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135940244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2135940244
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2689280547
Short name T113
Test name
Test status
Simulation time 96310153 ps
CPU time 2.23 seconds
Started Jun 26 06:38:41 PM PDT 24
Finished Jun 26 06:38:53 PM PDT 24
Peak memory 217556 kb
Host smart-f1f87a53-a7b2-4b53-ac9f-48f3b9fd0f56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689280547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.2689280547
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3458851893
Short name T986
Test name
Test status
Simulation time 25169521 ps
CPU time 1.12 seconds
Started Jun 26 06:38:50 PM PDT 24
Finished Jun 26 06:38:59 PM PDT 24
Peak memory 217544 kb
Host smart-f28dc102-9d80-4c99-a5b9-956e6217502d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458851893 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.3458851893
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1386719721
Short name T928
Test name
Test status
Simulation time 16084110 ps
CPU time 1.03 seconds
Started Jun 26 06:38:40 PM PDT 24
Finished Jun 26 06:38:51 PM PDT 24
Peak memory 209164 kb
Host smart-d3876986-807b-4e30-b76f-d367d0b0843c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386719721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1386719721
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.682702841
Short name T977
Test name
Test status
Simulation time 55464132 ps
CPU time 1.59 seconds
Started Jun 26 06:38:39 PM PDT 24
Finished Jun 26 06:38:51 PM PDT 24
Peak memory 209372 kb
Host smart-d4bd3705-c23a-4701-bc52-94f6b21022fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682702841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.682702841
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1945940235
Short name T974
Test name
Test status
Simulation time 34456438 ps
CPU time 2.25 seconds
Started Jun 26 06:38:42 PM PDT 24
Finished Jun 26 06:38:53 PM PDT 24
Peak memory 217508 kb
Host smart-79c585e6-ec91-4454-8464-0bfeda2b445d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945940235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.1945940235
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2211946670
Short name T140
Test name
Test status
Simulation time 107441394 ps
CPU time 1.89 seconds
Started Jun 26 06:38:41 PM PDT 24
Finished Jun 26 06:38:53 PM PDT 24
Peak memory 221472 kb
Host smart-b1696392-ad77-48c2-8771-81da3956f9f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211946670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2211946670
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.175888658
Short name T119
Test name
Test status
Simulation time 94793405 ps
CPU time 1.58 seconds
Started Jun 26 06:38:36 PM PDT 24
Finished Jun 26 06:38:47 PM PDT 24
Peak memory 223048 kb
Host smart-c41fb3e4-3b6b-4d40-a4ec-b2314bb4c29c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175888658 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.175888658
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.167998861
Short name T912
Test name
Test status
Simulation time 24805484 ps
CPU time 0.88 seconds
Started Jun 26 06:38:38 PM PDT 24
Finished Jun 26 06:38:49 PM PDT 24
Peak memory 208652 kb
Host smart-651e3879-4eff-4472-9ac6-d9594544c328
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167998861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.167998861
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.97953120
Short name T941
Test name
Test status
Simulation time 510207143 ps
CPU time 1.91 seconds
Started Jun 26 06:38:39 PM PDT 24
Finished Jun 26 06:38:51 PM PDT 24
Peak memory 211284 kb
Host smart-1f8e4d63-8908-40a0-a05b-75feeefa0f9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97953120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
same_csr_outstanding.97953120
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.253151809
Short name T960
Test name
Test status
Simulation time 49449401 ps
CPU time 2.23 seconds
Started Jun 26 06:38:39 PM PDT 24
Finished Jun 26 06:38:51 PM PDT 24
Peak memory 217516 kb
Host smart-511b0937-632b-4fc6-87a7-276596c3c996
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253151809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.253151809
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.711438024
Short name T124
Test name
Test status
Simulation time 217517084 ps
CPU time 2.41 seconds
Started Jun 26 06:38:42 PM PDT 24
Finished Jun 26 06:38:54 PM PDT 24
Peak memory 217604 kb
Host smart-115f2678-41e0-45b0-8a6b-a1223712f894
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711438024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg_
err.711438024
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2151012598
Short name T899
Test name
Test status
Simulation time 19612290 ps
CPU time 1.45 seconds
Started Jun 26 06:38:39 PM PDT 24
Finished Jun 26 06:38:51 PM PDT 24
Peak memory 217644 kb
Host smart-0d09431c-c599-4a14-bfb8-06f93dc9d9a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151012598 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2151012598
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3390897012
Short name T982
Test name
Test status
Simulation time 106802405 ps
CPU time 0.9 seconds
Started Jun 26 06:38:38 PM PDT 24
Finished Jun 26 06:38:50 PM PDT 24
Peak memory 209292 kb
Host smart-4b4ff19c-01f4-413d-8ce9-85bb157774e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390897012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3390897012
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1877667634
Short name T893
Test name
Test status
Simulation time 14547203 ps
CPU time 1 seconds
Started Jun 26 06:38:37 PM PDT 24
Finished Jun 26 06:38:48 PM PDT 24
Peak memory 209552 kb
Host smart-6a81727b-b007-47bd-867a-b61ee8a288bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877667634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.1877667634
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2713705876
Short name T948
Test name
Test status
Simulation time 240978194 ps
CPU time 1.95 seconds
Started Jun 26 06:38:38 PM PDT 24
Finished Jun 26 06:38:49 PM PDT 24
Peak memory 217880 kb
Host smart-c061e9ac-8eb4-4c15-b26d-038fd06eaedd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713705876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.2713705876
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1360577676
Short name T175
Test name
Test status
Simulation time 107803107 ps
CPU time 1.62 seconds
Started Jun 26 06:38:50 PM PDT 24
Finished Jun 26 06:39:00 PM PDT 24
Peak memory 217716 kb
Host smart-9da4687f-1ff5-4e50-a977-6145272fd9a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360577676 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1360577676
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3406065347
Short name T945
Test name
Test status
Simulation time 11717508 ps
CPU time 0.86 seconds
Started Jun 26 06:38:42 PM PDT 24
Finished Jun 26 06:38:53 PM PDT 24
Peak memory 209236 kb
Host smart-b4e76d93-2a3d-41bb-af27-f54f0a46a610
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406065347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.3406065347
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3667425561
Short name T207
Test name
Test status
Simulation time 47807149 ps
CPU time 1.06 seconds
Started Jun 26 06:38:38 PM PDT 24
Finished Jun 26 06:38:50 PM PDT 24
Peak memory 217472 kb
Host smart-03aecd27-c1e6-4d5a-9c63-9701724d4146
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667425561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.3667425561
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1724887674
Short name T962
Test name
Test status
Simulation time 211998675 ps
CPU time 2.71 seconds
Started Jun 26 06:38:39 PM PDT 24
Finished Jun 26 06:38:52 PM PDT 24
Peak memory 217572 kb
Host smart-d11be63d-03a2-449f-a143-477fb81407d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724887674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.1724887674
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1587664371
Short name T966
Test name
Test status
Simulation time 106558203 ps
CPU time 2.18 seconds
Started Jun 26 06:38:49 PM PDT 24
Finished Jun 26 06:39:00 PM PDT 24
Peak memory 217604 kb
Host smart-35e728b6-5efc-49bd-a4c2-95b372be5b1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587664371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1587664371
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.4264438123
Short name T881
Test name
Test status
Simulation time 100610268 ps
CPU time 1.21 seconds
Started Jun 26 06:38:39 PM PDT 24
Finished Jun 26 06:38:51 PM PDT 24
Peak memory 217620 kb
Host smart-bd8b4cc6-7dd1-4ab4-a1c5-b3fb0875fe5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264438123 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.4264438123
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.720823903
Short name T959
Test name
Test status
Simulation time 16421637 ps
CPU time 1.09 seconds
Started Jun 26 06:38:42 PM PDT 24
Finished Jun 26 06:38:52 PM PDT 24
Peak memory 217212 kb
Host smart-182e6443-6469-4e5c-b0a9-6c2830253440
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720823903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.720823903
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3357894524
Short name T203
Test name
Test status
Simulation time 34917732 ps
CPU time 0.95 seconds
Started Jun 26 06:38:38 PM PDT 24
Finished Jun 26 06:38:48 PM PDT 24
Peak memory 209504 kb
Host smart-2f90f813-81cb-4adc-92ec-47f462acfb3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357894524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3357894524
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.20082153
Short name T896
Test name
Test status
Simulation time 49356285 ps
CPU time 1 seconds
Started Jun 26 06:38:50 PM PDT 24
Finished Jun 26 06:38:59 PM PDT 24
Peak memory 217708 kb
Host smart-33dcd54d-360c-4dd4-9a24-1c50245257bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20082153 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.20082153
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1205567320
Short name T200
Test name
Test status
Simulation time 55135940 ps
CPU time 0.92 seconds
Started Jun 26 06:38:51 PM PDT 24
Finished Jun 26 06:39:01 PM PDT 24
Peak memory 209244 kb
Host smart-011213a0-18f8-4719-82ae-2dedc4b66841
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205567320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1205567320
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.220739519
Short name T935
Test name
Test status
Simulation time 40690576 ps
CPU time 1.93 seconds
Started Jun 26 06:39:03 PM PDT 24
Finished Jun 26 06:39:12 PM PDT 24
Peak memory 217768 kb
Host smart-949aedb6-2eeb-47e8-b41c-c62528b2e3d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220739519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_same_csr_outstanding.220739519
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1432434612
Short name T911
Test name
Test status
Simulation time 71822914 ps
CPU time 1.37 seconds
Started Jun 26 06:38:37 PM PDT 24
Finished Jun 26 06:38:48 PM PDT 24
Peak memory 217328 kb
Host smart-8a9b0e1c-9d1c-4de2-b7f4-92df1eb5792b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432434612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.1432434612
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.674541951
Short name T129
Test name
Test status
Simulation time 69491053 ps
CPU time 2.06 seconds
Started Jun 26 06:38:49 PM PDT 24
Finished Jun 26 06:39:00 PM PDT 24
Peak memory 221900 kb
Host smart-66225411-a564-46c3-bdcc-7f4a4702911f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674541951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_
err.674541951
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1021267308
Short name T198
Test name
Test status
Simulation time 91962666 ps
CPU time 1.28 seconds
Started Jun 26 06:38:13 PM PDT 24
Finished Jun 26 06:38:21 PM PDT 24
Peak memory 209240 kb
Host smart-1a616139-c1bd-49c0-bb4e-982727f32392
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021267308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.1021267308
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3125071404
Short name T954
Test name
Test status
Simulation time 144322287 ps
CPU time 1.31 seconds
Started Jun 26 06:38:14 PM PDT 24
Finished Jun 26 06:38:23 PM PDT 24
Peak memory 209312 kb
Host smart-550eb3a9-2985-4b2c-a2eb-ae2d0876b2b3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125071404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.3125071404
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2896649601
Short name T194
Test name
Test status
Simulation time 54553955 ps
CPU time 1.08 seconds
Started Jun 26 06:38:13 PM PDT 24
Finished Jun 26 06:38:21 PM PDT 24
Peak memory 210000 kb
Host smart-9a8b4bdc-f9cc-4c1e-b3b9-786dc313aead
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896649601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.2896649601
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.98593651
Short name T174
Test name
Test status
Simulation time 183450548 ps
CPU time 1.18 seconds
Started Jun 26 06:38:11 PM PDT 24
Finished Jun 26 06:38:16 PM PDT 24
Peak memory 218664 kb
Host smart-68da6d34-eaed-4c84-b6f1-78a4599677fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98593651 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.98593651
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.972521104
Short name T162
Test name
Test status
Simulation time 17219563 ps
CPU time 0.97 seconds
Started Jun 26 06:38:11 PM PDT 24
Finished Jun 26 06:38:14 PM PDT 24
Peak memory 209304 kb
Host smart-fe3bbd5b-6698-4e76-8d1e-9746e65a380b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972521104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.972521104
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.375376939
Short name T931
Test name
Test status
Simulation time 259173535 ps
CPU time 2.34 seconds
Started Jun 26 06:38:12 PM PDT 24
Finished Jun 26 06:38:20 PM PDT 24
Peak memory 209172 kb
Host smart-efe080f1-e274-4ea5-8eb0-9badc4083065
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375376939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_jtag_alert_test.375376939
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3415240142
Short name T971
Test name
Test status
Simulation time 368419389 ps
CPU time 3.99 seconds
Started Jun 26 06:38:13 PM PDT 24
Finished Jun 26 06:38:24 PM PDT 24
Peak memory 208888 kb
Host smart-d5c05749-b2fa-48f7-a818-cc74c7494eaf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415240142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.3415240142
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4088421272
Short name T876
Test name
Test status
Simulation time 493256821 ps
CPU time 5.12 seconds
Started Jun 26 06:38:16 PM PDT 24
Finished Jun 26 06:38:28 PM PDT 24
Peak memory 208952 kb
Host smart-faded3f3-7018-4652-a49b-cb6aafc27a06
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088421272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.4088421272
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3816836462
Short name T891
Test name
Test status
Simulation time 214650208 ps
CPU time 1.27 seconds
Started Jun 26 06:38:16 PM PDT 24
Finished Jun 26 06:38:24 PM PDT 24
Peak memory 210768 kb
Host smart-769784f0-c40f-4039-b1a2-3b5c9163fa22
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816836462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3816836462
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2107668804
Short name T136
Test name
Test status
Simulation time 109174973 ps
CPU time 1.3 seconds
Started Jun 26 06:38:13 PM PDT 24
Finished Jun 26 06:38:21 PM PDT 24
Peak memory 218632 kb
Host smart-04d1e41a-1a6c-4a66-82ce-22c6363fa313
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210766
8804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2107668804
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2938006696
Short name T957
Test name
Test status
Simulation time 176786766 ps
CPU time 1.46 seconds
Started Jun 26 06:38:12 PM PDT 24
Finished Jun 26 06:38:17 PM PDT 24
Peak memory 209044 kb
Host smart-2e7b6ec0-3ee9-4f20-8554-7c60c716b054
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938006696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.2938006696
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2916948981
Short name T994
Test name
Test status
Simulation time 145042779 ps
CPU time 1.32 seconds
Started Jun 26 06:38:12 PM PDT 24
Finished Jun 26 06:38:17 PM PDT 24
Peak memory 211184 kb
Host smart-364088ef-d011-4791-93e0-b7cd27707e78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916948981 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.2916948981
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.812165570
Short name T209
Test name
Test status
Simulation time 85595099 ps
CPU time 1.3 seconds
Started Jun 26 06:38:11 PM PDT 24
Finished Jun 26 06:38:16 PM PDT 24
Peak memory 209492 kb
Host smart-446c707e-26bf-4991-a683-26f9013aee04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812165570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
same_csr_outstanding.812165570
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1491824518
Short name T923
Test name
Test status
Simulation time 371407366 ps
CPU time 1.84 seconds
Started Jun 26 06:38:13 PM PDT 24
Finished Jun 26 06:38:22 PM PDT 24
Peak memory 218540 kb
Host smart-3e298d31-19cb-4e5c-9b50-cdf6c46d8eb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491824518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1491824518
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2717047862
Short name T195
Test name
Test status
Simulation time 36147368 ps
CPU time 1.34 seconds
Started Jun 26 06:38:25 PM PDT 24
Finished Jun 26 06:38:31 PM PDT 24
Peak memory 209432 kb
Host smart-e97585f8-e9b7-49b8-9261-176d9189776d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717047862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.2717047862
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1882703516
Short name T988
Test name
Test status
Simulation time 35653867 ps
CPU time 1.17 seconds
Started Jun 26 06:38:02 PM PDT 24
Finished Jun 26 06:38:06 PM PDT 24
Peak memory 209220 kb
Host smart-696b3f92-3ba3-41af-94b6-b4af1b15e199
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882703516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.1882703516
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2089281110
Short name T920
Test name
Test status
Simulation time 31466035 ps
CPU time 0.97 seconds
Started Jun 26 06:38:13 PM PDT 24
Finished Jun 26 06:38:21 PM PDT 24
Peak memory 209804 kb
Host smart-4503be18-4774-4be8-990e-6c3cbb86661d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089281110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.2089281110
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.529022002
Short name T905
Test name
Test status
Simulation time 49714402 ps
CPU time 1.19 seconds
Started Jun 26 06:38:39 PM PDT 24
Finished Jun 26 06:38:50 PM PDT 24
Peak memory 222076 kb
Host smart-d651b67f-c7f2-453f-b233-dd4199a43e76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529022002 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.529022002
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4093313467
Short name T904
Test name
Test status
Simulation time 27189380 ps
CPU time 0.97 seconds
Started Jun 26 06:38:13 PM PDT 24
Finished Jun 26 06:38:21 PM PDT 24
Peak memory 209220 kb
Host smart-9848db9d-e103-4a4f-9c10-93c782e927f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093313467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.4093313467
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2764964957
Short name T900
Test name
Test status
Simulation time 98374534 ps
CPU time 1.54 seconds
Started Jun 26 06:38:17 PM PDT 24
Finished Jun 26 06:38:25 PM PDT 24
Peak memory 209192 kb
Host smart-1c895651-4815-47b5-93cb-d8fc53d26fad
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764964957 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2764964957
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2203743160
Short name T993
Test name
Test status
Simulation time 826435159 ps
CPU time 5.86 seconds
Started Jun 26 06:38:14 PM PDT 24
Finished Jun 26 06:38:28 PM PDT 24
Peak memory 209236 kb
Host smart-71c1c024-77da-47fc-b667-a9ecd0cb099d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203743160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2203743160
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.649046003
Short name T878
Test name
Test status
Simulation time 4670029539 ps
CPU time 14.8 seconds
Started Jun 26 06:38:15 PM PDT 24
Finished Jun 26 06:38:37 PM PDT 24
Peak memory 217316 kb
Host smart-369f4a8e-2e45-4526-8119-62794abb9682
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649046003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.649046003
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1891696801
Short name T898
Test name
Test status
Simulation time 1242837490 ps
CPU time 2.96 seconds
Started Jun 26 06:38:17 PM PDT 24
Finished Jun 26 06:38:26 PM PDT 24
Peak memory 210888 kb
Host smart-1d229780-24e1-48f3-905e-2282de485628
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891696801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.1891696801
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2143274840
Short name T979
Test name
Test status
Simulation time 49618722 ps
CPU time 1.95 seconds
Started Jun 26 06:38:16 PM PDT 24
Finished Jun 26 06:38:24 PM PDT 24
Peak memory 217752 kb
Host smart-b744415f-6b58-4d32-89d8-29d75e2fd261
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214327
4840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2143274840
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4161580075
Short name T127
Test name
Test status
Simulation time 167221401 ps
CPU time 1.08 seconds
Started Jun 26 06:38:13 PM PDT 24
Finished Jun 26 06:38:21 PM PDT 24
Peak memory 216912 kb
Host smart-cc919f45-a394-40ec-9120-234538e6eef1
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161580075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.4161580075
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3298990197
Short name T980
Test name
Test status
Simulation time 126950922 ps
CPU time 1.01 seconds
Started Jun 26 06:38:17 PM PDT 24
Finished Jun 26 06:38:24 PM PDT 24
Peak memory 217592 kb
Host smart-c5aec12d-621f-4193-97ec-2e8b9d6f264a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298990197 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3298990197
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.728523680
Short name T937
Test name
Test status
Simulation time 143546395 ps
CPU time 1.08 seconds
Started Jun 26 06:38:29 PM PDT 24
Finished Jun 26 06:38:37 PM PDT 24
Peak memory 209388 kb
Host smart-e7df8fb7-821c-4532-873d-1d6aee11a3d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728523680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.728523680
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3860412699
Short name T126
Test name
Test status
Simulation time 123467398 ps
CPU time 2.18 seconds
Started Jun 26 06:38:13 PM PDT 24
Finished Jun 26 06:38:21 PM PDT 24
Peak memory 217692 kb
Host smart-ef5d4723-fd33-4ce5-83bc-4bf3052ec505
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860412699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.3860412699
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4170498741
Short name T201
Test name
Test status
Simulation time 59959364 ps
CPU time 1.16 seconds
Started Jun 26 06:38:34 PM PDT 24
Finished Jun 26 06:38:44 PM PDT 24
Peak memory 208652 kb
Host smart-695ab935-44a4-401e-986e-0815ea22d0a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170498741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.4170498741
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.917568526
Short name T885
Test name
Test status
Simulation time 241696661 ps
CPU time 1.74 seconds
Started Jun 26 06:38:30 PM PDT 24
Finished Jun 26 06:38:39 PM PDT 24
Peak memory 209276 kb
Host smart-38fbb21f-02dd-4c21-a32d-ea788081db1c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917568526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash
.917568526
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1799609844
Short name T202
Test name
Test status
Simulation time 23479617 ps
CPU time 1.1 seconds
Started Jun 26 06:38:27 PM PDT 24
Finished Jun 26 06:38:34 PM PDT 24
Peak memory 211420 kb
Host smart-ae310485-6f5d-49d2-91be-db3a9b7e1eb0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799609844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1799609844
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3212766806
Short name T963
Test name
Test status
Simulation time 49319667 ps
CPU time 1.22 seconds
Started Jun 26 06:38:28 PM PDT 24
Finished Jun 26 06:38:36 PM PDT 24
Peak memory 217684 kb
Host smart-fdfd3f92-893a-4b79-8960-84e8badfb4bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212766806 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3212766806
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2031183946
Short name T883
Test name
Test status
Simulation time 12987046 ps
CPU time 0.86 seconds
Started Jun 26 06:38:28 PM PDT 24
Finished Jun 26 06:38:35 PM PDT 24
Peak memory 209188 kb
Host smart-7580671b-8e5f-4eab-bc81-fb29a2093f03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031183946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2031183946
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.431891541
Short name T886
Test name
Test status
Simulation time 19342548 ps
CPU time 0.88 seconds
Started Jun 26 06:38:27 PM PDT 24
Finished Jun 26 06:38:34 PM PDT 24
Peak memory 209168 kb
Host smart-7c49489c-5e9f-4ce9-a0ce-a9ecea969fa4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431891541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_alert_test.431891541
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2852811349
Short name T985
Test name
Test status
Simulation time 1085399860 ps
CPU time 9.41 seconds
Started Jun 26 06:38:32 PM PDT 24
Finished Jun 26 06:38:50 PM PDT 24
Peak memory 208908 kb
Host smart-ddc1104b-27f2-46b1-b44d-757d8b0926eb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852811349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2852811349
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.683493226
Short name T874
Test name
Test status
Simulation time 695740784 ps
CPU time 18.4 seconds
Started Jun 26 06:38:32 PM PDT 24
Finished Jun 26 06:38:59 PM PDT 24
Peak memory 217108 kb
Host smart-8b489658-3309-4e0c-bba4-00bf484b5b5f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683493226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.683493226
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3990128971
Short name T943
Test name
Test status
Simulation time 694154524 ps
CPU time 1.42 seconds
Started Jun 26 06:38:26 PM PDT 24
Finished Jun 26 06:38:33 PM PDT 24
Peak memory 217648 kb
Host smart-4bf0ed47-19d8-467e-bfeb-cd674076a656
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399012
8971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3990128971
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3033854401
Short name T888
Test name
Test status
Simulation time 64935316 ps
CPU time 2.36 seconds
Started Jun 26 06:38:28 PM PDT 24
Finished Jun 26 06:38:36 PM PDT 24
Peak memory 209224 kb
Host smart-f43e7f44-0144-44af-b027-cc7f16671740
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033854401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.3033854401
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.224682164
Short name T208
Test name
Test status
Simulation time 72210393 ps
CPU time 1.39 seconds
Started Jun 26 06:38:25 PM PDT 24
Finished Jun 26 06:38:31 PM PDT 24
Peak memory 217480 kb
Host smart-8793d085-d82a-4eae-8dca-b7a07a466577
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224682164 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.224682164
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2066978324
Short name T990
Test name
Test status
Simulation time 20274581 ps
CPU time 1.32 seconds
Started Jun 26 06:38:32 PM PDT 24
Finished Jun 26 06:38:42 PM PDT 24
Peak memory 209472 kb
Host smart-2c37a93e-8114-4a73-bb37-bec93eb1c782
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066978324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.2066978324
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.653489096
Short name T991
Test name
Test status
Simulation time 46379163 ps
CPU time 1.58 seconds
Started Jun 26 06:38:28 PM PDT 24
Finished Jun 26 06:38:37 PM PDT 24
Peak memory 217464 kb
Host smart-77d0476b-850a-474f-8755-b8cf9ae7c96b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653489096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.653489096
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3439864396
Short name T995
Test name
Test status
Simulation time 19062461 ps
CPU time 1.2 seconds
Started Jun 26 06:38:27 PM PDT 24
Finished Jun 26 06:38:34 PM PDT 24
Peak memory 218020 kb
Host smart-1c3a1c16-2aa7-4309-b14b-bdf6ae5c43e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439864396 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3439864396
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3992321002
Short name T196
Test name
Test status
Simulation time 14833317 ps
CPU time 0.87 seconds
Started Jun 26 06:39:16 PM PDT 24
Finished Jun 26 06:39:22 PM PDT 24
Peak memory 209288 kb
Host smart-2c29cea5-2c08-4edc-8a34-e6e2ec542bd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992321002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.3992321002
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2944962045
Short name T148
Test name
Test status
Simulation time 46741330 ps
CPU time 1.13 seconds
Started Jun 26 06:38:45 PM PDT 24
Finished Jun 26 06:38:56 PM PDT 24
Peak memory 209208 kb
Host smart-3070c1f6-6953-4b29-aeba-f9497def1f29
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944962045 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2944962045
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4209544611
Short name T965
Test name
Test status
Simulation time 957395860 ps
CPU time 5.89 seconds
Started Jun 26 06:38:27 PM PDT 24
Finished Jun 26 06:38:39 PM PDT 24
Peak memory 208952 kb
Host smart-d2b5af2c-5448-4bea-910f-93319ec94255
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209544611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.4209544611
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4117239985
Short name T989
Test name
Test status
Simulation time 356319332 ps
CPU time 5.6 seconds
Started Jun 26 06:38:30 PM PDT 24
Finished Jun 26 06:38:43 PM PDT 24
Peak memory 209160 kb
Host smart-1e1ff55d-35fa-4ea2-8c00-dcd0bbb7ac29
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117239985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.4117239985
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3329177999
Short name T970
Test name
Test status
Simulation time 181865459 ps
CPU time 1.85 seconds
Started Jun 26 06:38:28 PM PDT 24
Finished Jun 26 06:38:37 PM PDT 24
Peak memory 209188 kb
Host smart-6f50f8e0-9fb6-4f37-9bd5-6d1b6f9ccba9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329177999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3329177999
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1286692029
Short name T902
Test name
Test status
Simulation time 57604169 ps
CPU time 1.46 seconds
Started Jun 26 06:38:26 PM PDT 24
Finished Jun 26 06:38:32 PM PDT 24
Peak memory 217632 kb
Host smart-7428d59b-9d13-4021-99df-5d2ed93e52f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128669
2029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1286692029
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1281287861
Short name T147
Test name
Test status
Simulation time 64373753 ps
CPU time 2.14 seconds
Started Jun 26 06:38:30 PM PDT 24
Finished Jun 26 06:38:40 PM PDT 24
Peak memory 209248 kb
Host smart-9a8ab04e-d032-4032-ab73-3460a1e716e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281287861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.1281287861
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.529704522
Short name T956
Test name
Test status
Simulation time 99268664 ps
CPU time 1.36 seconds
Started Jun 26 06:38:30 PM PDT 24
Finished Jun 26 06:38:39 PM PDT 24
Peak memory 217528 kb
Host smart-f82dc090-c4fb-4816-a395-60a50ef17579
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529704522 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.529704522
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1363760994
Short name T972
Test name
Test status
Simulation time 63745092 ps
CPU time 1.37 seconds
Started Jun 26 06:38:26 PM PDT 24
Finished Jun 26 06:38:34 PM PDT 24
Peak memory 209376 kb
Host smart-f6e30cf2-edde-4636-bac5-d147cd4968e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363760994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.1363760994
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3866653365
Short name T125
Test name
Test status
Simulation time 192875338 ps
CPU time 1.63 seconds
Started Jun 26 06:40:06 PM PDT 24
Finished Jun 26 06:40:08 PM PDT 24
Peak memory 218388 kb
Host smart-24f2fa7c-c7d1-493d-9d57-e77afdddfe22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866653365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3866653365
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3388866919
Short name T936
Test name
Test status
Simulation time 59378850 ps
CPU time 1.35 seconds
Started Jun 26 06:38:27 PM PDT 24
Finished Jun 26 06:38:34 PM PDT 24
Peak memory 222844 kb
Host smart-1b80e68a-4901-4e9f-8643-3d027badbee9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388866919 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3388866919
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1090792461
Short name T976
Test name
Test status
Simulation time 121898849 ps
CPU time 0.84 seconds
Started Jun 26 06:38:28 PM PDT 24
Finished Jun 26 06:38:36 PM PDT 24
Peak memory 209136 kb
Host smart-07ca571d-ad78-4b9b-b468-21f7d3a875eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090792461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1090792461
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.852378638
Short name T950
Test name
Test status
Simulation time 76255127 ps
CPU time 1.2 seconds
Started Jun 26 06:38:28 PM PDT 24
Finished Jun 26 06:38:35 PM PDT 24
Peak memory 208720 kb
Host smart-0aa21a26-d209-448e-8f97-98378bcd8ec4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852378638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.lc_ctrl_jtag_alert_test.852378638
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2050125844
Short name T919
Test name
Test status
Simulation time 1465406397 ps
CPU time 6.44 seconds
Started Jun 26 06:38:29 PM PDT 24
Finished Jun 26 06:38:42 PM PDT 24
Peak memory 217036 kb
Host smart-56e3757a-1451-41d4-a69f-632cfa61f388
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050125844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2050125844
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.185086942
Short name T913
Test name
Test status
Simulation time 1662168168 ps
CPU time 10.55 seconds
Started Jun 26 06:38:28 PM PDT 24
Finished Jun 26 06:38:46 PM PDT 24
Peak memory 208884 kb
Host smart-07b88b25-358b-4321-91f6-30ea21f1f0bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185086942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.185086942
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1800384088
Short name T927
Test name
Test status
Simulation time 95589914 ps
CPU time 2.86 seconds
Started Jun 26 06:38:30 PM PDT 24
Finished Jun 26 06:38:40 PM PDT 24
Peak memory 217444 kb
Host smart-75b47fa2-faa1-4893-b65e-2fcfe54075ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800384088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1800384088
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3266777055
Short name T975
Test name
Test status
Simulation time 62559350 ps
CPU time 1.31 seconds
Started Jun 26 06:38:30 PM PDT 24
Finished Jun 26 06:38:39 PM PDT 24
Peak memory 209156 kb
Host smart-6f45405b-6d83-48a9-b999-fe3aded3ab92
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266777055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.3266777055
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.979786307
Short name T921
Test name
Test status
Simulation time 81525506 ps
CPU time 1.27 seconds
Started Jun 26 06:38:30 PM PDT 24
Finished Jun 26 06:38:39 PM PDT 24
Peak memory 209388 kb
Host smart-008bb807-2934-4603-bbbc-c29b6c820530
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979786307 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.979786307
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.513436942
Short name T894
Test name
Test status
Simulation time 88074239 ps
CPU time 1.09 seconds
Started Jun 26 06:38:28 PM PDT 24
Finished Jun 26 06:38:36 PM PDT 24
Peak memory 209328 kb
Host smart-f8bab5b1-1137-4771-8e73-0371f6ce5361
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513436942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
same_csr_outstanding.513436942
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1217354062
Short name T922
Test name
Test status
Simulation time 1248271581 ps
CPU time 2.99 seconds
Started Jun 26 06:38:27 PM PDT 24
Finished Jun 26 06:38:36 PM PDT 24
Peak memory 217492 kb
Host smart-90d2b6af-a90e-4f79-b24d-82f5e0387b8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217354062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1217354062
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1247584887
Short name T981
Test name
Test status
Simulation time 28624594 ps
CPU time 1.62 seconds
Started Jun 26 06:38:27 PM PDT 24
Finished Jun 26 06:38:35 PM PDT 24
Peak memory 217612 kb
Host smart-9e79b5b7-b941-42cc-b4a0-a4a4a39f76d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247584887 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1247584887
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1196084599
Short name T877
Test name
Test status
Simulation time 14978425 ps
CPU time 0.88 seconds
Started Jun 26 06:38:25 PM PDT 24
Finished Jun 26 06:38:30 PM PDT 24
Peak memory 209452 kb
Host smart-5badd12c-8abd-49ce-9478-2ed224c967dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196084599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1196084599
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3227357352
Short name T997
Test name
Test status
Simulation time 87926741 ps
CPU time 1.19 seconds
Started Jun 26 06:38:34 PM PDT 24
Finished Jun 26 06:38:44 PM PDT 24
Peak memory 208720 kb
Host smart-ce93c19a-0fb1-4a0b-b39c-10c2b3defdc0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227357352 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3227357352
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3823163437
Short name T890
Test name
Test status
Simulation time 263370600 ps
CPU time 6.51 seconds
Started Jun 26 06:38:28 PM PDT 24
Finished Jun 26 06:38:42 PM PDT 24
Peak memory 209008 kb
Host smart-3e6093bd-d313-4fa1-ac7e-51e59a64deec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823163437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3823163437
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.4171291120
Short name T884
Test name
Test status
Simulation time 1387527915 ps
CPU time 7.36 seconds
Started Jun 26 06:38:30 PM PDT 24
Finished Jun 26 06:38:45 PM PDT 24
Peak memory 209200 kb
Host smart-500a5448-3071-4684-a51e-851faee87268
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171291120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.4171291120
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1863711033
Short name T983
Test name
Test status
Simulation time 181158632 ps
CPU time 1.54 seconds
Started Jun 26 06:38:27 PM PDT 24
Finished Jun 26 06:38:34 PM PDT 24
Peak memory 217424 kb
Host smart-56684ca7-7dbe-4809-be18-90ac1d24260a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863711033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1863711033
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.868867740
Short name T887
Test name
Test status
Simulation time 57734094 ps
CPU time 1.41 seconds
Started Jun 26 06:38:26 PM PDT 24
Finished Jun 26 06:38:33 PM PDT 24
Peak memory 219848 kb
Host smart-3d7edd6f-7e29-47a9-95ef-df7ac02c7a76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868867
740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.868867740
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1403060849
Short name T882
Test name
Test status
Simulation time 131347274 ps
CPU time 1.2 seconds
Started Jun 26 06:38:28 PM PDT 24
Finished Jun 26 06:38:36 PM PDT 24
Peak memory 209200 kb
Host smart-17b54430-478b-4702-b999-0ae66256073b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403060849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.1403060849
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.4203707230
Short name T161
Test name
Test status
Simulation time 177834571 ps
CPU time 1.34 seconds
Started Jun 26 06:38:32 PM PDT 24
Finished Jun 26 06:38:42 PM PDT 24
Peak memory 211244 kb
Host smart-e1a94bdc-a336-41a3-83b7-5378656d8b2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203707230 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.4203707230
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3996057218
Short name T938
Test name
Test status
Simulation time 182587163 ps
CPU time 1.43 seconds
Started Jun 26 06:38:28 PM PDT 24
Finished Jun 26 06:38:35 PM PDT 24
Peak memory 217572 kb
Host smart-24e0dec7-6534-4aad-8bd3-86737699754b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996057218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3996057218
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3168311476
Short name T987
Test name
Test status
Simulation time 163290424 ps
CPU time 2.59 seconds
Started Jun 26 06:38:30 PM PDT 24
Finished Jun 26 06:38:40 PM PDT 24
Peak memory 217480 kb
Host smart-bffc2285-52e9-4dcd-916b-ea364137379c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168311476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3168311476
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2947014719
Short name T144
Test name
Test status
Simulation time 49269605 ps
CPU time 1.92 seconds
Started Jun 26 06:38:26 PM PDT 24
Finished Jun 26 06:38:34 PM PDT 24
Peak memory 222036 kb
Host smart-a6d48ee8-de95-4a00-8eb6-87c286d01805
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947014719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2947014719
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1718978156
Short name T892
Test name
Test status
Simulation time 24246404 ps
CPU time 1.71 seconds
Started Jun 26 06:39:02 PM PDT 24
Finished Jun 26 06:39:10 PM PDT 24
Peak memory 217756 kb
Host smart-532fc378-d60f-4229-b5be-5932b0ff7eb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718978156 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1718978156
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2609284243
Short name T910
Test name
Test status
Simulation time 14577992 ps
CPU time 1.03 seconds
Started Jun 26 06:38:27 PM PDT 24
Finished Jun 26 06:38:34 PM PDT 24
Peak memory 209284 kb
Host smart-4eea12ab-b04a-4a33-a387-baecbb95ee76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609284243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2609284243
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.4182625983
Short name T918
Test name
Test status
Simulation time 151659749 ps
CPU time 1.12 seconds
Started Jun 26 06:38:29 PM PDT 24
Finished Jun 26 06:38:38 PM PDT 24
Peak memory 209160 kb
Host smart-41e9ab18-322d-40df-ae99-06e7c323b73b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182625983 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.4182625983
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3717055416
Short name T907
Test name
Test status
Simulation time 1031787326 ps
CPU time 19.54 seconds
Started Jun 26 06:38:30 PM PDT 24
Finished Jun 26 06:38:56 PM PDT 24
Peak memory 209020 kb
Host smart-255bd110-7f5c-4e79-b24c-494d832f69e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717055416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3717055416
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3443028288
Short name T978
Test name
Test status
Simulation time 1543399784 ps
CPU time 4.64 seconds
Started Jun 26 06:38:34 PM PDT 24
Finished Jun 26 06:38:48 PM PDT 24
Peak memory 208936 kb
Host smart-2592c45a-0641-4ce0-8307-a42d86569e27
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443028288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3443028288
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1870687709
Short name T146
Test name
Test status
Simulation time 247293589 ps
CPU time 1.83 seconds
Started Jun 26 06:38:27 PM PDT 24
Finished Jun 26 06:38:35 PM PDT 24
Peak memory 210840 kb
Host smart-1b65d9ac-298d-430a-a48d-a055bf2cc459
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870687709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.1870687709
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.190736287
Short name T952
Test name
Test status
Simulation time 263755917 ps
CPU time 2.81 seconds
Started Jun 26 06:38:32 PM PDT 24
Finished Jun 26 06:38:42 PM PDT 24
Peak memory 217696 kb
Host smart-2426e06f-8684-4b58-8825-1280f82b2cd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190736
287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.190736287
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.118596675
Short name T909
Test name
Test status
Simulation time 62491009 ps
CPU time 2.16 seconds
Started Jun 26 06:38:27 PM PDT 24
Finished Jun 26 06:38:35 PM PDT 24
Peak memory 209300 kb
Host smart-c031a0e0-2e88-4775-acc9-ecaf2b4d6bd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118596675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.118596675
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3346153514
Short name T903
Test name
Test status
Simulation time 223800805 ps
CPU time 0.96 seconds
Started Jun 26 06:38:27 PM PDT 24
Finished Jun 26 06:38:34 PM PDT 24
Peak memory 209280 kb
Host smart-9c93f142-c0c1-4838-97e0-8feaad198953
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346153514 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3346153514
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.744055437
Short name T969
Test name
Test status
Simulation time 86904070 ps
CPU time 1.95 seconds
Started Jun 26 06:38:32 PM PDT 24
Finished Jun 26 06:38:42 PM PDT 24
Peak memory 211332 kb
Host smart-d27b45c5-9703-4bad-9b3e-7c94efa1b97b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744055437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
same_csr_outstanding.744055437
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3503325229
Short name T942
Test name
Test status
Simulation time 290393412 ps
CPU time 1.64 seconds
Started Jun 26 06:38:47 PM PDT 24
Finished Jun 26 06:38:58 PM PDT 24
Peak memory 217580 kb
Host smart-0822340c-caac-469c-8da8-e87c7c45e7a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503325229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3503325229
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3464681164
Short name T134
Test name
Test status
Simulation time 133879923 ps
CPU time 1.82 seconds
Started Jun 26 06:38:32 PM PDT 24
Finished Jun 26 06:38:42 PM PDT 24
Peak memory 217716 kb
Host smart-8a4aaafc-ff2b-454a-b6b1-e949168248e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464681164 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3464681164
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.4021606865
Short name T901
Test name
Test status
Simulation time 15316126 ps
CPU time 0.87 seconds
Started Jun 26 06:38:33 PM PDT 24
Finished Jun 26 06:38:42 PM PDT 24
Peak memory 209300 kb
Host smart-149099ab-afda-44ae-9500-85c89a441895
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021606865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.4021606865
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2120854989
Short name T944
Test name
Test status
Simulation time 110488898 ps
CPU time 1.53 seconds
Started Jun 26 06:38:34 PM PDT 24
Finished Jun 26 06:38:45 PM PDT 24
Peak memory 209172 kb
Host smart-def3f909-dde4-4882-8b54-db20197971a7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120854989 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2120854989
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1487359563
Short name T914
Test name
Test status
Simulation time 443592675 ps
CPU time 5.47 seconds
Started Jun 26 06:38:29 PM PDT 24
Finished Jun 26 06:38:41 PM PDT 24
Peak memory 216992 kb
Host smart-1506d4c7-a480-4d1d-8291-d45e099bad48
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487359563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1487359563
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.835208064
Short name T939
Test name
Test status
Simulation time 969029752 ps
CPU time 18.16 seconds
Started Jun 26 06:38:32 PM PDT 24
Finished Jun 26 06:38:58 PM PDT 24
Peak memory 208992 kb
Host smart-ab35e7cd-bb05-406f-a519-632b4a9c7b93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835208064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.835208064
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2756693939
Short name T916
Test name
Test status
Simulation time 568266872 ps
CPU time 3.48 seconds
Started Jun 26 06:38:32 PM PDT 24
Finished Jun 26 06:38:44 PM PDT 24
Peak memory 210864 kb
Host smart-cb54c525-d9f1-4e92-a231-0a4d74edf55b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756693939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2756693939
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1559621516
Short name T176
Test name
Test status
Simulation time 357863320 ps
CPU time 1.9 seconds
Started Jun 26 06:38:33 PM PDT 24
Finished Jun 26 06:38:43 PM PDT 24
Peak memory 219100 kb
Host smart-e478f071-6775-48ec-8015-66ba5de32a65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155962
1516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1559621516
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3102033820
Short name T875
Test name
Test status
Simulation time 186165803 ps
CPU time 1.59 seconds
Started Jun 26 06:38:33 PM PDT 24
Finished Jun 26 06:38:45 PM PDT 24
Peak memory 217276 kb
Host smart-4dcadc1b-e28b-46f0-85e6-35fae11d921b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102033820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3102033820
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1757575241
Short name T924
Test name
Test status
Simulation time 22523578 ps
CPU time 1.13 seconds
Started Jun 26 06:38:32 PM PDT 24
Finished Jun 26 06:38:41 PM PDT 24
Peak memory 209352 kb
Host smart-316a68c7-5172-4091-af3d-df488b8c8aff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757575241 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1757575241
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2011270412
Short name T996
Test name
Test status
Simulation time 179380887 ps
CPU time 1.92 seconds
Started Jun 26 06:38:32 PM PDT 24
Finished Jun 26 06:38:43 PM PDT 24
Peak memory 209376 kb
Host smart-d64b6a67-ebba-4775-a913-d0748f8fcbaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011270412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2011270412
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1849526384
Short name T117
Test name
Test status
Simulation time 122464588 ps
CPU time 5.19 seconds
Started Jun 26 06:38:33 PM PDT 24
Finished Jun 26 06:38:46 PM PDT 24
Peak memory 217396 kb
Host smart-e4e14444-569f-42e9-81e8-1e8f8fb835cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849526384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1849526384
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.554484401
Short name T554
Test name
Test status
Simulation time 44116935 ps
CPU time 1.02 seconds
Started Jun 26 06:51:49 PM PDT 24
Finished Jun 26 06:51:52 PM PDT 24
Peak memory 209240 kb
Host smart-2d060a58-4b80-4f5c-9a75-79591ce2c0be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554484401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.554484401
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.2032901971
Short name T13
Test name
Test status
Simulation time 29131499 ps
CPU time 0.8 seconds
Started Jun 26 06:51:26 PM PDT 24
Finished Jun 26 06:51:29 PM PDT 24
Peak memory 209176 kb
Host smart-bb236bea-3c7b-4ab3-a6a4-161b6846c32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032901971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.2032901971
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.2502427101
Short name T257
Test name
Test status
Simulation time 550876897 ps
CPU time 18.3 seconds
Started Jun 26 06:51:26 PM PDT 24
Finished Jun 26 06:51:47 PM PDT 24
Peak memory 218436 kb
Host smart-c0cfe520-8eeb-4e5b-857d-ff9e120d9979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502427101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2502427101
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.1368340978
Short name T866
Test name
Test status
Simulation time 130372087 ps
CPU time 4.26 seconds
Started Jun 26 06:51:49 PM PDT 24
Finished Jun 26 06:51:56 PM PDT 24
Peak memory 217528 kb
Host smart-779d880c-3231-4f01-8e32-f6964a7a3050
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368340978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.1368340978
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.2040718572
Short name T339
Test name
Test status
Simulation time 7227233301 ps
CPU time 76.05 seconds
Started Jun 26 06:51:48 PM PDT 24
Finished Jun 26 06:53:06 PM PDT 24
Peak memory 219372 kb
Host smart-f88b4c52-68fc-4bed-bbff-a1d1dfebdc93
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040718572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.2040718572
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1350807809
Short name T687
Test name
Test status
Simulation time 543143379 ps
CPU time 6.79 seconds
Started Jun 26 06:51:50 PM PDT 24
Finished Jun 26 06:51:59 PM PDT 24
Peak memory 217620 kb
Host smart-24859f42-754d-4b92-bb40-27eec1ad1d28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350807809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
350807809
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3377297313
Short name T418
Test name
Test status
Simulation time 544402338 ps
CPU time 8.1 seconds
Started Jun 26 06:51:50 PM PDT 24
Finished Jun 26 06:52:01 PM PDT 24
Peak memory 218440 kb
Host smart-d517b329-1c75-4d9d-9083-5288642174db
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377297313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3377297313
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3408181296
Short name T504
Test name
Test status
Simulation time 4669579439 ps
CPU time 17.2 seconds
Started Jun 26 06:51:48 PM PDT 24
Finished Jun 26 06:52:08 PM PDT 24
Peak memory 217988 kb
Host smart-505e425a-c901-463d-af35-7a422da74b8b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408181296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.3408181296
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.4013352016
Short name T845
Test name
Test status
Simulation time 1324194877 ps
CPU time 8.77 seconds
Started Jun 26 06:51:26 PM PDT 24
Finished Jun 26 06:51:37 PM PDT 24
Peak memory 217928 kb
Host smart-996d9e4a-2d4a-4057-b64d-197f47522512
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013352016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
4013352016
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1603691791
Short name T291
Test name
Test status
Simulation time 4259629839 ps
CPU time 129.02 seconds
Started Jun 26 06:51:25 PM PDT 24
Finished Jun 26 06:53:36 PM PDT 24
Peak memory 251156 kb
Host smart-05eda22e-e34c-4c1e-bb31-802e8e45130d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603691791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1603691791
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.658940536
Short name T233
Test name
Test status
Simulation time 715758622 ps
CPU time 12.56 seconds
Started Jun 26 06:51:48 PM PDT 24
Finished Jun 26 06:52:02 PM PDT 24
Peak memory 222084 kb
Host smart-c73c0011-2721-46f1-a3de-8ef274e1ddc0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658940536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.658940536
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1263373862
Short name T276
Test name
Test status
Simulation time 27443466 ps
CPU time 2.15 seconds
Started Jun 26 06:51:25 PM PDT 24
Finished Jun 26 06:51:30 PM PDT 24
Peak memory 218452 kb
Host smart-e7cfd120-eb3f-480b-a3ae-6c55bbdba0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263373862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1263373862
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3387099342
Short name T72
Test name
Test status
Simulation time 3755508655 ps
CPU time 12.57 seconds
Started Jun 26 06:51:25 PM PDT 24
Finished Jun 26 06:51:39 PM PDT 24
Peak memory 215660 kb
Host smart-469ca425-a878-4006-99bb-92fc86e59c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387099342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3387099342
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.1886946530
Short name T103
Test name
Test status
Simulation time 206310210 ps
CPU time 40.74 seconds
Started Jun 26 06:51:51 PM PDT 24
Finished Jun 26 06:52:34 PM PDT 24
Peak memory 269948 kb
Host smart-5ac71bef-7579-4357-89a6-8dc19d5d475d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886946530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.1886946530
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.695554747
Short name T251
Test name
Test status
Simulation time 466162695 ps
CPU time 11.24 seconds
Started Jun 26 06:51:48 PM PDT 24
Finished Jun 26 06:52:01 PM PDT 24
Peak memory 226248 kb
Host smart-333b991a-2371-4633-ac5c-8d93e0702184
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695554747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.695554747
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2475009312
Short name T856
Test name
Test status
Simulation time 1532837075 ps
CPU time 9.65 seconds
Started Jun 26 06:51:48 PM PDT 24
Finished Jun 26 06:51:59 PM PDT 24
Peak memory 218460 kb
Host smart-bd1c43f9-375f-4306-9e1c-d5d286af1098
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475009312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2475009312
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.3709714026
Short name T304
Test name
Test status
Simulation time 293938575 ps
CPU time 6.35 seconds
Started Jun 26 06:51:50 PM PDT 24
Finished Jun 26 06:51:59 PM PDT 24
Peak memory 226264 kb
Host smart-95718cb1-d496-4f77-abd2-0549be9dd2e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709714026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.3
709714026
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.3077541014
Short name T587
Test name
Test status
Simulation time 681805693 ps
CPU time 7.85 seconds
Started Jun 26 06:51:28 PM PDT 24
Finished Jun 26 06:51:37 PM PDT 24
Peak memory 218564 kb
Host smart-dcd51387-4c0c-4e8c-b90f-0f2e62c4469a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077541014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3077541014
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.3475473387
Short name T87
Test name
Test status
Simulation time 105214936 ps
CPU time 4.73 seconds
Started Jun 26 06:51:24 PM PDT 24
Finished Jun 26 06:51:30 PM PDT 24
Peak memory 217956 kb
Host smart-568913c5-8dc1-40ff-850d-aa3bf927d6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475473387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3475473387
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.3445766998
Short name T234
Test name
Test status
Simulation time 675315573 ps
CPU time 27.76 seconds
Started Jun 26 06:51:25 PM PDT 24
Finished Jun 26 06:51:55 PM PDT 24
Peak memory 251160 kb
Host smart-692df1a7-2729-4c69-a790-cfcdace9c107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445766998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3445766998
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2261055401
Short name T855
Test name
Test status
Simulation time 77937268 ps
CPU time 8.64 seconds
Started Jun 26 06:51:26 PM PDT 24
Finished Jun 26 06:51:36 PM PDT 24
Peak memory 251116 kb
Host smart-efe134e9-d739-498a-b224-13a8d0c33d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261055401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2261055401
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.3307224920
Short name T82
Test name
Test status
Simulation time 8080536379 ps
CPU time 266.87 seconds
Started Jun 26 06:51:49 PM PDT 24
Finished Jun 26 06:56:19 PM PDT 24
Peak memory 223252 kb
Host smart-e3e8fa23-5c11-4f4e-8633-5c9a4e3e0ec0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307224920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.3307224920
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.195450431
Short name T494
Test name
Test status
Simulation time 43536552 ps
CPU time 0.96 seconds
Started Jun 26 06:51:26 PM PDT 24
Finished Jun 26 06:51:29 PM PDT 24
Peak memory 213308 kb
Host smart-aa28d791-67de-4ac5-81f2-7169d75c7727
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195450431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr
l_volatile_unlock_smoke.195450431
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3681985538
Short name T769
Test name
Test status
Simulation time 36287397 ps
CPU time 0.9 seconds
Started Jun 26 06:51:50 PM PDT 24
Finished Jun 26 06:51:53 PM PDT 24
Peak memory 209172 kb
Host smart-41809022-57f0-4fde-b83b-3adb3aadad81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681985538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3681985538
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1160060868
Short name T170
Test name
Test status
Simulation time 1469606777 ps
CPU time 11.83 seconds
Started Jun 26 06:51:47 PM PDT 24
Finished Jun 26 06:52:00 PM PDT 24
Peak memory 226204 kb
Host smart-1e0dfec9-c6fb-4e61-9d3f-85eb699b505c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160060868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1160060868
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.3752010461
Short name T580
Test name
Test status
Simulation time 762353538 ps
CPU time 17.78 seconds
Started Jun 26 06:51:49 PM PDT 24
Finished Jun 26 06:52:09 PM PDT 24
Peak memory 217652 kb
Host smart-0771809c-7729-4743-a0d6-f2728a20b663
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752010461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.3752010461
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2481646138
Short name T768
Test name
Test status
Simulation time 4666821052 ps
CPU time 129.04 seconds
Started Jun 26 06:51:49 PM PDT 24
Finished Jun 26 06:54:00 PM PDT 24
Peak memory 220192 kb
Host smart-7e91c2e4-fcb7-4bfc-b770-9856bc3de489
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481646138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2481646138
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.987437225
Short name T450
Test name
Test status
Simulation time 3569277518 ps
CPU time 15.46 seconds
Started Jun 26 06:51:49 PM PDT 24
Finished Jun 26 06:52:07 PM PDT 24
Peak memory 218056 kb
Host smart-655d3106-867a-4708-a854-a3ecb92b94e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987437225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.987437225
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1037425323
Short name T218
Test name
Test status
Simulation time 255796791 ps
CPU time 2.85 seconds
Started Jun 26 06:51:49 PM PDT 24
Finished Jun 26 06:51:54 PM PDT 24
Peak memory 218416 kb
Host smart-e5db0f2f-2eeb-4e4d-bc02-231f6c0028b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037425323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.1037425323
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3746530395
Short name T538
Test name
Test status
Simulation time 4520892410 ps
CPU time 16.11 seconds
Started Jun 26 06:51:51 PM PDT 24
Finished Jun 26 06:52:09 PM PDT 24
Peak memory 218000 kb
Host smart-b140a23c-2cdc-4f9b-a86e-52b9049c3da8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746530395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3746530395
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.2738910666
Short name T485
Test name
Test status
Simulation time 183230735 ps
CPU time 3.26 seconds
Started Jun 26 06:51:49 PM PDT 24
Finished Jun 26 06:51:55 PM PDT 24
Peak memory 217916 kb
Host smart-5aa82c44-1015-4c73-a807-589462b09ea4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738910666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
2738910666
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3294844731
Short name T399
Test name
Test status
Simulation time 19682433300 ps
CPU time 28.11 seconds
Started Jun 26 06:51:50 PM PDT 24
Finished Jun 26 06:52:20 PM PDT 24
Peak memory 251176 kb
Host smart-9f704730-f1ce-4507-a432-383895a75de6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294844731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3294844731
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3888780343
Short name T841
Test name
Test status
Simulation time 4415038834 ps
CPU time 29.06 seconds
Started Jun 26 06:51:49 PM PDT 24
Finished Jun 26 06:52:20 PM PDT 24
Peak memory 250964 kb
Host smart-7e5c84e5-d3be-4da0-bc5c-6323efec9c21
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888780343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.3888780343
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.645629485
Short name T188
Test name
Test status
Simulation time 307526277 ps
CPU time 3.05 seconds
Started Jun 26 06:51:50 PM PDT 24
Finished Jun 26 06:51:56 PM PDT 24
Peak memory 218436 kb
Host smart-3920caff-2128-4f68-bec0-5fed810acfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645629485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.645629485
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.3287751525
Short name T659
Test name
Test status
Simulation time 353124105 ps
CPU time 10.13 seconds
Started Jun 26 06:51:49 PM PDT 24
Finished Jun 26 06:52:01 PM PDT 24
Peak memory 214972 kb
Host smart-8ffb8405-628c-4801-a053-33b2265ed85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287751525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3287751525
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.1428493866
Short name T95
Test name
Test status
Simulation time 225578790 ps
CPU time 35.51 seconds
Started Jun 26 06:51:49 PM PDT 24
Finished Jun 26 06:52:27 PM PDT 24
Peak memory 283268 kb
Host smart-b4b6cf9b-2122-413c-a8bb-ae05f7efc240
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428493866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.1428493866
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.502646078
Short name T751
Test name
Test status
Simulation time 230558251 ps
CPU time 9.56 seconds
Started Jun 26 06:51:49 PM PDT 24
Finished Jun 26 06:52:01 PM PDT 24
Peak memory 226224 kb
Host smart-55e22789-105d-4efb-b68c-d84c4e458175
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502646078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.502646078
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.121876470
Short name T577
Test name
Test status
Simulation time 223133042 ps
CPU time 10 seconds
Started Jun 26 06:51:48 PM PDT 24
Finished Jun 26 06:51:59 PM PDT 24
Peak memory 218596 kb
Host smart-54ea9ca0-53b4-414d-90db-ac4091a06052
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121876470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dig
est.121876470
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.3049727172
Short name T402
Test name
Test status
Simulation time 2725553941 ps
CPU time 11.91 seconds
Started Jun 26 06:51:49 PM PDT 24
Finished Jun 26 06:52:03 PM PDT 24
Peak memory 218508 kb
Host smart-49fa42b9-d654-4d89-8bc2-53e550991023
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049727172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.3
049727172
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.2662049408
Short name T471
Test name
Test status
Simulation time 407039933 ps
CPU time 14.16 seconds
Started Jun 26 06:51:48 PM PDT 24
Finished Jun 26 06:52:05 PM PDT 24
Peak memory 218528 kb
Host smart-c8291af9-b841-423b-b3c8-534412ef6858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662049408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2662049408
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.4230201121
Short name T861
Test name
Test status
Simulation time 20866132 ps
CPU time 1.5 seconds
Started Jun 26 06:51:48 PM PDT 24
Finished Jun 26 06:51:52 PM PDT 24
Peak memory 214008 kb
Host smart-7971ff26-f9e5-41e8-90e9-e2a533734b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230201121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.4230201121
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3777865682
Short name T605
Test name
Test status
Simulation time 757025830 ps
CPU time 32.94 seconds
Started Jun 26 06:51:50 PM PDT 24
Finished Jun 26 06:52:25 PM PDT 24
Peak memory 251160 kb
Host smart-2112a3c7-e08f-4d53-acf8-2b500eecbcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777865682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3777865682
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.3254839574
Short name T329
Test name
Test status
Simulation time 199156959 ps
CPU time 6.94 seconds
Started Jun 26 06:51:51 PM PDT 24
Finished Jun 26 06:52:00 PM PDT 24
Peak memory 251144 kb
Host smart-63602846-d1bb-42a7-bdf1-4f7cd0622a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254839574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3254839574
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.567207203
Short name T735
Test name
Test status
Simulation time 8895648170 ps
CPU time 165.05 seconds
Started Jun 26 06:51:50 PM PDT 24
Finished Jun 26 06:54:37 PM PDT 24
Peak memory 251192 kb
Host smart-d508914f-6611-4e15-8751-65e9141e888c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567207203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.567207203
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2613390752
Short name T817
Test name
Test status
Simulation time 14456695 ps
CPU time 1.08 seconds
Started Jun 26 06:51:50 PM PDT 24
Finished Jun 26 06:51:54 PM PDT 24
Peak memory 212032 kb
Host smart-95d983f0-01f5-4fef-a775-e39434b1062e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613390752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2613390752
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.1433401165
Short name T455
Test name
Test status
Simulation time 28470190 ps
CPU time 1.32 seconds
Started Jun 26 06:53:31 PM PDT 24
Finished Jun 26 06:53:34 PM PDT 24
Peak memory 209160 kb
Host smart-f64dec1f-e8ff-4929-a82e-1804faba0a7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433401165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.1433401165
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.3211536436
Short name T255
Test name
Test status
Simulation time 294022836 ps
CPU time 9.7 seconds
Started Jun 26 06:53:28 PM PDT 24
Finished Jun 26 06:53:39 PM PDT 24
Peak memory 218396 kb
Host smart-74486ed2-0802-4029-a4fb-0e2dd70eff38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211536436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.3211536436
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.165379978
Short name T421
Test name
Test status
Simulation time 481868680 ps
CPU time 3.24 seconds
Started Jun 26 06:53:35 PM PDT 24
Finished Jun 26 06:53:40 PM PDT 24
Peak memory 217432 kb
Host smart-4bf085e1-2a2a-4fe0-ac90-109956157fca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165379978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.165379978
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2456145153
Short name T636
Test name
Test status
Simulation time 8234275433 ps
CPU time 94.86 seconds
Started Jun 26 06:53:29 PM PDT 24
Finished Jun 26 06:55:07 PM PDT 24
Peak memory 219216 kb
Host smart-b0b30475-e303-4a82-8a5f-ad3e9dd36285
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456145153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2456145153
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1706102632
Short name T410
Test name
Test status
Simulation time 138225288 ps
CPU time 3.65 seconds
Started Jun 26 06:53:30 PM PDT 24
Finished Jun 26 06:53:35 PM PDT 24
Peak memory 222052 kb
Host smart-ddcad41f-36ac-4dcb-a9c3-31255c4e3205
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706102632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1706102632
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.1960528335
Short name T396
Test name
Test status
Simulation time 304456320 ps
CPU time 9 seconds
Started Jun 26 06:53:32 PM PDT 24
Finished Jun 26 06:53:42 PM PDT 24
Peak memory 217896 kb
Host smart-96367417-fb47-4134-a0a5-cceda584e628
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960528335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.1960528335
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2096797980
Short name T657
Test name
Test status
Simulation time 7352222737 ps
CPU time 70.75 seconds
Started Jun 26 06:53:28 PM PDT 24
Finished Jun 26 06:54:40 PM PDT 24
Peak memory 283936 kb
Host smart-c81dc1cd-5b2a-4439-9780-3e6e31ab9479
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096797980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2096797980
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.1191823074
Short name T4
Test name
Test status
Simulation time 557951442 ps
CPU time 21.4 seconds
Started Jun 26 06:53:28 PM PDT 24
Finished Jun 26 06:53:51 PM PDT 24
Peak memory 251112 kb
Host smart-c3667399-110f-4351-9b7a-d42b28445667
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191823074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.1191823074
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.3694556795
Short name T786
Test name
Test status
Simulation time 26392786 ps
CPU time 2.01 seconds
Started Jun 26 06:53:29 PM PDT 24
Finished Jun 26 06:53:33 PM PDT 24
Peak memory 218348 kb
Host smart-dcd476d2-e134-4150-b503-784669e27b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694556795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.3694556795
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3060003026
Short name T628
Test name
Test status
Simulation time 669807185 ps
CPU time 8.36 seconds
Started Jun 26 06:53:31 PM PDT 24
Finished Jun 26 06:53:41 PM PDT 24
Peak memory 218472 kb
Host smart-97ec0a95-10a1-4285-a7b1-c131adfd8de8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060003026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3060003026
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2993200248
Short name T454
Test name
Test status
Simulation time 454731131 ps
CPU time 12.31 seconds
Started Jun 26 06:53:31 PM PDT 24
Finished Jun 26 06:53:45 PM PDT 24
Peak memory 226152 kb
Host smart-b5598392-3cf6-475c-8f76-ab0538466344
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993200248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
2993200248
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.666058449
Short name T214
Test name
Test status
Simulation time 747929007 ps
CPU time 13.91 seconds
Started Jun 26 06:53:30 PM PDT 24
Finished Jun 26 06:53:46 PM PDT 24
Peak memory 218520 kb
Host smart-5ce3d0fa-785b-4205-a574-8f1d6008cac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666058449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.666058449
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.2484295421
Short name T501
Test name
Test status
Simulation time 78875538 ps
CPU time 2.94 seconds
Started Jun 26 06:53:29 PM PDT 24
Finished Jun 26 06:53:35 PM PDT 24
Peak memory 217888 kb
Host smart-262c4f47-5510-4542-b012-234f0ce4827b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484295421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.2484295421
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.71583382
Short name T445
Test name
Test status
Simulation time 288710551 ps
CPU time 24.99 seconds
Started Jun 26 06:53:30 PM PDT 24
Finished Jun 26 06:53:57 PM PDT 24
Peak memory 251132 kb
Host smart-c9effde9-e309-4e12-a5c8-c26904aca183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71583382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.71583382
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.4078102730
Short name T850
Test name
Test status
Simulation time 118169988 ps
CPU time 7.8 seconds
Started Jun 26 06:53:33 PM PDT 24
Finished Jun 26 06:53:42 PM PDT 24
Peak memory 251108 kb
Host smart-0f79cb1e-8787-489a-be09-631cc1a251bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078102730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.4078102730
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.226839604
Short name T834
Test name
Test status
Simulation time 66342238075 ps
CPU time 315.6 seconds
Started Jun 26 06:53:32 PM PDT 24
Finished Jun 26 06:58:50 PM PDT 24
Peak memory 284096 kb
Host smart-a6a2c0fc-6a0c-4da2-a1a3-af3f4532e9eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=226839604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.226839604
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.4120780648
Short name T654
Test name
Test status
Simulation time 13302542 ps
CPU time 1.06 seconds
Started Jun 26 06:53:30 PM PDT 24
Finished Jun 26 06:53:33 PM PDT 24
Peak memory 212068 kb
Host smart-24778b38-559e-4a27-b360-8c9f08a560e5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120780648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.4120780648
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.3461409790
Short name T578
Test name
Test status
Simulation time 49137557 ps
CPU time 0.84 seconds
Started Jun 26 06:53:47 PM PDT 24
Finished Jun 26 06:53:48 PM PDT 24
Peak memory 209052 kb
Host smart-9341a207-e669-4e62-bfdc-0e087a2c9f37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461409790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3461409790
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.1985899985
Short name T252
Test name
Test status
Simulation time 1996424881 ps
CPU time 14.61 seconds
Started Jun 26 06:53:31 PM PDT 24
Finished Jun 26 06:53:48 PM PDT 24
Peak memory 218420 kb
Host smart-272ce4e6-faf3-4d00-ac94-7a3bbe18e17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985899985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.1985899985
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.4261041626
Short name T870
Test name
Test status
Simulation time 7343448181 ps
CPU time 29.38 seconds
Started Jun 26 06:53:35 PM PDT 24
Finished Jun 26 06:54:06 PM PDT 24
Peak memory 218404 kb
Host smart-cd9c575d-550e-4a14-84d1-e062cf3241d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261041626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.4261041626
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1360070835
Short name T280
Test name
Test status
Simulation time 133380596 ps
CPU time 3.08 seconds
Started Jun 26 06:53:35 PM PDT 24
Finished Jun 26 06:53:40 PM PDT 24
Peak memory 218424 kb
Host smart-92578afa-3942-4a9b-8542-273ab7b9ce40
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360070835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.1360070835
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3318702730
Short name T672
Test name
Test status
Simulation time 250220337 ps
CPU time 5.38 seconds
Started Jun 26 06:53:35 PM PDT 24
Finished Jun 26 06:53:42 PM PDT 24
Peak memory 217904 kb
Host smart-822052ab-879a-4666-ab85-575d25760bc0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318702730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.3318702730
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3073094213
Short name T676
Test name
Test status
Simulation time 10006891131 ps
CPU time 153.18 seconds
Started Jun 26 06:53:33 PM PDT 24
Finished Jun 26 06:56:07 PM PDT 24
Peak memory 283904 kb
Host smart-2f87c5ac-eb14-4346-ac13-0d546c6b4093
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073094213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3073094213
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.2328313271
Short name T381
Test name
Test status
Simulation time 298089309 ps
CPU time 9.76 seconds
Started Jun 26 06:53:34 PM PDT 24
Finished Jun 26 06:53:46 PM PDT 24
Peak memory 246336 kb
Host smart-94ab637a-0024-4138-9d16-af56dba772c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328313271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.2328313271
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.3260805674
Short name T703
Test name
Test status
Simulation time 79111679 ps
CPU time 3.69 seconds
Started Jun 26 06:53:30 PM PDT 24
Finished Jun 26 06:53:35 PM PDT 24
Peak memory 218456 kb
Host smart-a5bbb60d-efae-4595-8671-b3f82fa72e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260805674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3260805674
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.368360635
Short name T272
Test name
Test status
Simulation time 530456323 ps
CPU time 8.38 seconds
Started Jun 26 06:53:35 PM PDT 24
Finished Jun 26 06:53:45 PM PDT 24
Peak memory 219088 kb
Host smart-7280ce6e-32ea-4c8e-857b-6521956a328c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368360635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.368360635
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2385331294
Short name T747
Test name
Test status
Simulation time 484656935 ps
CPU time 11.27 seconds
Started Jun 26 06:53:41 PM PDT 24
Finished Jun 26 06:53:54 PM PDT 24
Peak memory 218472 kb
Host smart-dfaa0356-f2dd-475b-a6d6-aa03432c3841
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385331294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2385331294
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.2380129747
Short name T166
Test name
Test status
Simulation time 271273550 ps
CPU time 8.51 seconds
Started Jun 26 06:53:43 PM PDT 24
Finished Jun 26 06:53:53 PM PDT 24
Peak memory 218436 kb
Host smart-97bacad7-0785-45e7-a2cb-cd187989a6a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380129747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
2380129747
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.3951194407
Short name T164
Test name
Test status
Simulation time 1411843343 ps
CPU time 12.33 seconds
Started Jun 26 06:53:31 PM PDT 24
Finished Jun 26 06:53:45 PM PDT 24
Peak memory 225896 kb
Host smart-fe441f68-be51-42a3-8dd8-4c6785805a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951194407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.3951194407
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2428051453
Short name T220
Test name
Test status
Simulation time 17784732 ps
CPU time 1.34 seconds
Started Jun 26 06:53:32 PM PDT 24
Finished Jun 26 06:53:35 PM PDT 24
Peak memory 217936 kb
Host smart-0df95e86-841e-4a91-9012-ba0078e1e3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428051453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2428051453
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1818287683
Short name T310
Test name
Test status
Simulation time 477086539 ps
CPU time 30.75 seconds
Started Jun 26 06:53:32 PM PDT 24
Finished Jun 26 06:54:04 PM PDT 24
Peak memory 251188 kb
Host smart-e186d75b-38f4-4039-b80a-3c2c6af8a64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818287683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1818287683
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.4135750541
Short name T787
Test name
Test status
Simulation time 185752108 ps
CPU time 8.01 seconds
Started Jun 26 06:53:32 PM PDT 24
Finished Jun 26 06:53:42 PM PDT 24
Peak memory 251080 kb
Host smart-131a0033-590c-400c-b485-0a7d363ac283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135750541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.4135750541
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.2284208795
Short name T604
Test name
Test status
Simulation time 4447842097 ps
CPU time 56.03 seconds
Started Jun 26 06:53:42 PM PDT 24
Finished Jun 26 06:54:40 PM PDT 24
Peak memory 251248 kb
Host smart-f36acdf4-c01f-4b3d-bbf6-3dfd9bd93b36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284208795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.2284208795
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2440847980
Short name T777
Test name
Test status
Simulation time 32676489 ps
CPU time 0.91 seconds
Started Jun 26 06:53:31 PM PDT 24
Finished Jun 26 06:53:34 PM PDT 24
Peak memory 212052 kb
Host smart-05673a71-a987-480c-bd6d-9988929e4b1e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440847980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2440847980
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.4191248733
Short name T284
Test name
Test status
Simulation time 17326424 ps
CPU time 1.12 seconds
Started Jun 26 06:53:43 PM PDT 24
Finished Jun 26 06:53:46 PM PDT 24
Peak memory 209132 kb
Host smart-955b5502-3b78-4a3e-9911-1aa9d2e39536
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191248733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.4191248733
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1462611762
Short name T801
Test name
Test status
Simulation time 270404823 ps
CPU time 12.37 seconds
Started Jun 26 06:53:42 PM PDT 24
Finished Jun 26 06:53:56 PM PDT 24
Peak memory 218460 kb
Host smart-28103194-eca5-4f7b-a801-0c54482d30da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462611762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1462611762
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.3220399899
Short name T602
Test name
Test status
Simulation time 105776652 ps
CPU time 3.44 seconds
Started Jun 26 06:53:42 PM PDT 24
Finished Jun 26 06:53:48 PM PDT 24
Peak memory 217360 kb
Host smart-5f0821c8-2bb1-494e-ac65-8d0782289196
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220399899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3220399899
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.43921255
Short name T436
Test name
Test status
Simulation time 1154575036 ps
CPU time 36.22 seconds
Started Jun 26 06:53:42 PM PDT 24
Finished Jun 26 06:54:20 PM PDT 24
Peak memory 218408 kb
Host smart-fa53b117-051b-45ad-b07b-571c906a6a07
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43921255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_err
ors.43921255
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3495589887
Short name T470
Test name
Test status
Simulation time 306258643 ps
CPU time 9.01 seconds
Started Jun 26 06:53:40 PM PDT 24
Finished Jun 26 06:53:51 PM PDT 24
Peak memory 223216 kb
Host smart-4e4d040b-bd4d-4ea8-b35f-2cb4e6764f51
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495589887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.3495589887
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.870692223
Short name T800
Test name
Test status
Simulation time 1185618134 ps
CPU time 8.5 seconds
Started Jun 26 06:53:41 PM PDT 24
Finished Jun 26 06:53:52 PM PDT 24
Peak memory 217928 kb
Host smart-f17ee4de-708f-4626-becc-7d80a8c24e49
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870692223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke.
870692223
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2586314797
Short name T670
Test name
Test status
Simulation time 2856493140 ps
CPU time 62.82 seconds
Started Jun 26 06:53:42 PM PDT 24
Finished Jun 26 06:54:47 PM PDT 24
Peak memory 282616 kb
Host smart-4db164a3-4c94-4443-ac4c-30aa188b4e5a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586314797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.2586314797
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3701409383
Short name T871
Test name
Test status
Simulation time 262550776 ps
CPU time 12.72 seconds
Started Jun 26 06:53:42 PM PDT 24
Finished Jun 26 06:53:57 PM PDT 24
Peak memory 251144 kb
Host smart-e00080dc-a135-4e69-830c-38bab69dee88
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701409383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3701409383
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.2800108670
Short name T308
Test name
Test status
Simulation time 186390593 ps
CPU time 2.05 seconds
Started Jun 26 06:53:40 PM PDT 24
Finished Jun 26 06:53:43 PM PDT 24
Peak memory 218452 kb
Host smart-dfc4a6f5-7961-42e8-81d8-b4465e15af03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800108670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2800108670
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.930042921
Short name T847
Test name
Test status
Simulation time 701587779 ps
CPU time 13.24 seconds
Started Jun 26 06:53:42 PM PDT 24
Finished Jun 26 06:53:57 PM PDT 24
Peak memory 218672 kb
Host smart-cd97421f-5ef6-4c80-8d21-1cae04e560fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930042921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_di
gest.930042921
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1718288580
Short name T262
Test name
Test status
Simulation time 1160514725 ps
CPU time 11.42 seconds
Started Jun 26 06:53:42 PM PDT 24
Finished Jun 26 06:53:55 PM PDT 24
Peak memory 218412 kb
Host smart-d6d3227b-b1e0-497b-ab1e-174ca0bbff86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718288580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1718288580
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.1139049793
Short name T518
Test name
Test status
Simulation time 693729881 ps
CPU time 13.23 seconds
Started Jun 26 06:53:41 PM PDT 24
Finished Jun 26 06:53:56 PM PDT 24
Peak memory 226220 kb
Host smart-d44ab7d4-e5ea-4b41-a67c-817cd348d8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139049793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.1139049793
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.54625563
Short name T346
Test name
Test status
Simulation time 17111520 ps
CPU time 1.1 seconds
Started Jun 26 06:53:42 PM PDT 24
Finished Jun 26 06:53:46 PM PDT 24
Peak memory 212152 kb
Host smart-351bb459-b616-4ddf-978e-fe1bd45d0984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54625563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.54625563
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.787634513
Short name T335
Test name
Test status
Simulation time 312709894 ps
CPU time 22.33 seconds
Started Jun 26 06:53:47 PM PDT 24
Finished Jun 26 06:54:10 PM PDT 24
Peak memory 251120 kb
Host smart-fc42b5c1-d57d-4b65-bda5-cde565c29bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787634513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.787634513
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2562606224
Short name T414
Test name
Test status
Simulation time 243942715 ps
CPU time 7.07 seconds
Started Jun 26 06:53:47 PM PDT 24
Finished Jun 26 06:53:55 PM PDT 24
Peak memory 242948 kb
Host smart-6221776c-1e10-4597-a8ce-d1c69d93af9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562606224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2562606224
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.1480028326
Short name T102
Test name
Test status
Simulation time 26265256469 ps
CPU time 222.53 seconds
Started Jun 26 06:53:43 PM PDT 24
Finished Jun 26 06:57:27 PM PDT 24
Peak memory 275468 kb
Host smart-3532b541-5edf-4bf7-8216-932e15170abd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480028326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.1480028326
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3741006495
Short name T274
Test name
Test status
Simulation time 63420352 ps
CPU time 0.87 seconds
Started Jun 26 06:53:42 PM PDT 24
Finished Jun 26 06:53:45 PM PDT 24
Peak memory 212112 kb
Host smart-60b50565-82a0-4be4-9fcd-1fe1f8eab2ae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741006495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3741006495
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3526871784
Short name T9
Test name
Test status
Simulation time 31104373 ps
CPU time 0.93 seconds
Started Jun 26 06:53:58 PM PDT 24
Finished Jun 26 06:54:00 PM PDT 24
Peak memory 209124 kb
Host smart-ff27bcac-631a-4085-8b02-6886239cde6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526871784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3526871784
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.643590213
Short name T475
Test name
Test status
Simulation time 628583521 ps
CPU time 20.36 seconds
Started Jun 26 06:53:43 PM PDT 24
Finished Jun 26 06:54:05 PM PDT 24
Peak memory 218320 kb
Host smart-7cb8003b-a8b7-48ec-a95f-1baba2319c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643590213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.643590213
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.2457025876
Short name T673
Test name
Test status
Simulation time 1558263981 ps
CPU time 3.35 seconds
Started Jun 26 06:53:58 PM PDT 24
Finished Jun 26 06:54:03 PM PDT 24
Peak memory 217312 kb
Host smart-5ae32cee-e2eb-47b1-a89f-f1d3a64f5802
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457025876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.2457025876
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2055380430
Short name T521
Test name
Test status
Simulation time 235497290 ps
CPU time 5.25 seconds
Started Jun 26 06:53:56 PM PDT 24
Finished Jun 26 06:54:03 PM PDT 24
Peak memory 218416 kb
Host smart-99e08e01-fb4c-489b-a424-8b2793ccb863
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055380430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2055380430
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.556285435
Short name T714
Test name
Test status
Simulation time 1312985137 ps
CPU time 5.78 seconds
Started Jun 26 06:53:53 PM PDT 24
Finished Jun 26 06:54:01 PM PDT 24
Peak memory 217916 kb
Host smart-29d4ce8c-b93a-4e47-a205-52db7cb3c2c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556285435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.
556285435
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2407045218
Short name T713
Test name
Test status
Simulation time 4455710430 ps
CPU time 44.1 seconds
Started Jun 26 06:53:55 PM PDT 24
Finished Jun 26 06:54:41 PM PDT 24
Peak memory 275680 kb
Host smart-afdebdfd-2602-4be7-800d-2720b553dd2f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407045218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2407045218
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3428999962
Short name T446
Test name
Test status
Simulation time 3003906082 ps
CPU time 11.65 seconds
Started Jun 26 06:53:54 PM PDT 24
Finished Jun 26 06:54:08 PM PDT 24
Peak memory 246728 kb
Host smart-3ff6a939-212a-4c29-a869-1976681fb4be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428999962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.3428999962
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.1827229944
Short name T246
Test name
Test status
Simulation time 180805063 ps
CPU time 3.48 seconds
Started Jun 26 06:53:42 PM PDT 24
Finished Jun 26 06:53:47 PM PDT 24
Peak memory 222488 kb
Host smart-03da6390-e718-40b8-a876-996f658eceab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827229944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.1827229944
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.2991594781
Short name T600
Test name
Test status
Simulation time 2274699722 ps
CPU time 14.38 seconds
Started Jun 26 06:53:57 PM PDT 24
Finished Jun 26 06:54:13 PM PDT 24
Peak memory 219160 kb
Host smart-084ef549-6571-48df-b0d8-df3726a16eec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991594781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.2991594781
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3247805121
Short name T449
Test name
Test status
Simulation time 348523070 ps
CPU time 13.84 seconds
Started Jun 26 06:53:55 PM PDT 24
Finished Jun 26 06:54:11 PM PDT 24
Peak memory 218552 kb
Host smart-d3023639-1575-4e10-9893-7b899484da67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247805121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.3247805121
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1572029459
Short name T169
Test name
Test status
Simulation time 1559636239 ps
CPU time 10.24 seconds
Started Jun 26 06:53:56 PM PDT 24
Finished Jun 26 06:54:08 PM PDT 24
Peak memory 218596 kb
Host smart-844249c1-4a2d-4125-a3eb-c3138739fd56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572029459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1572029459
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.673895294
Short name T707
Test name
Test status
Simulation time 346212546 ps
CPU time 6.15 seconds
Started Jun 26 06:53:53 PM PDT 24
Finished Jun 26 06:54:02 PM PDT 24
Peak memory 218508 kb
Host smart-5947eeae-82fc-404f-a2c9-117b3c5d2024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673895294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.673895294
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1467140133
Short name T815
Test name
Test status
Simulation time 287976541 ps
CPU time 4.55 seconds
Started Jun 26 06:53:47 PM PDT 24
Finished Jun 26 06:53:52 PM PDT 24
Peak memory 217936 kb
Host smart-de4fcf48-6314-47fa-be3a-7c9684d03d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467140133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1467140133
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.400180944
Short name T99
Test name
Test status
Simulation time 456757526 ps
CPU time 29.23 seconds
Started Jun 26 06:53:43 PM PDT 24
Finished Jun 26 06:54:14 PM PDT 24
Peak memory 251116 kb
Host smart-4fcfe97b-dc07-4201-b881-a42b5a89bccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400180944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.400180944
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1242062800
Short name T487
Test name
Test status
Simulation time 770803210 ps
CPU time 7.87 seconds
Started Jun 26 06:53:41 PM PDT 24
Finished Jun 26 06:53:51 PM PDT 24
Peak memory 251144 kb
Host smart-a25e5053-7d6e-4832-be17-d019d3407aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242062800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1242062800
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3099578902
Short name T677
Test name
Test status
Simulation time 7551760238 ps
CPU time 87.83 seconds
Started Jun 26 06:53:53 PM PDT 24
Finished Jun 26 06:55:23 PM PDT 24
Peak memory 274428 kb
Host smart-f6f990d5-c67c-4436-87ac-23da2d2f4984
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099578902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3099578902
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1286823014
Short name T22
Test name
Test status
Simulation time 97922428 ps
CPU time 0.95 seconds
Started Jun 26 06:53:41 PM PDT 24
Finished Jun 26 06:53:44 PM PDT 24
Peak memory 213152 kb
Host smart-85a6838c-0230-47b1-91f6-43d4626010ba
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286823014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.1286823014
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2952118516
Short name T598
Test name
Test status
Simulation time 44644143 ps
CPU time 0.92 seconds
Started Jun 26 06:53:56 PM PDT 24
Finished Jun 26 06:53:59 PM PDT 24
Peak memory 209204 kb
Host smart-021315f9-d83e-4410-93a9-9681c9cf0665
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952118516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2952118516
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2247331357
Short name T289
Test name
Test status
Simulation time 663093985 ps
CPU time 7.68 seconds
Started Jun 26 06:53:56 PM PDT 24
Finished Jun 26 06:54:06 PM PDT 24
Peak memory 226452 kb
Host smart-24eec1c4-c169-4e8e-afc4-9b7e4cf2103a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247331357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2247331357
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3169177566
Short name T33
Test name
Test status
Simulation time 247866111 ps
CPU time 3.66 seconds
Started Jun 26 06:53:55 PM PDT 24
Finished Jun 26 06:54:01 PM PDT 24
Peak memory 217468 kb
Host smart-78bcf09c-b0a4-4438-99ea-b55f0ce84877
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169177566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3169177566
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.3700636279
Short name T711
Test name
Test status
Simulation time 12650000767 ps
CPU time 89.29 seconds
Started Jun 26 06:53:53 PM PDT 24
Finished Jun 26 06:55:24 PM PDT 24
Peak memory 219896 kb
Host smart-912b602a-6ef7-4d69-b8db-749869af0d0a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700636279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.3700636279
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.3842005442
Short name T181
Test name
Test status
Simulation time 615029310 ps
CPU time 16.73 seconds
Started Jun 26 06:53:56 PM PDT 24
Finished Jun 26 06:54:15 PM PDT 24
Peak memory 218416 kb
Host smart-b48238f5-fdb2-4ebe-b34c-778b828e1f51
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842005442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.3842005442
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.2600252434
Short name T759
Test name
Test status
Simulation time 955149457 ps
CPU time 3.01 seconds
Started Jun 26 06:53:53 PM PDT 24
Finished Jun 26 06:53:57 PM PDT 24
Peak memory 217928 kb
Host smart-2ca73bce-987e-43b8-b2c6-603654f53a73
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600252434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.2600252434
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2421054637
Short name T811
Test name
Test status
Simulation time 890793350 ps
CPU time 29.11 seconds
Started Jun 26 06:53:55 PM PDT 24
Finished Jun 26 06:54:27 PM PDT 24
Peak memory 267484 kb
Host smart-c0d57723-5a14-4da3-84ae-936b21a0d8a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421054637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2421054637
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1630689264
Short name T334
Test name
Test status
Simulation time 541457678 ps
CPU time 21.58 seconds
Started Jun 26 06:53:58 PM PDT 24
Finished Jun 26 06:54:21 PM PDT 24
Peak memory 251072 kb
Host smart-d50e024e-6de5-4d65-849c-2b29893125ca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630689264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.1630689264
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2865751227
Short name T690
Test name
Test status
Simulation time 42312064 ps
CPU time 2.23 seconds
Started Jun 26 06:53:54 PM PDT 24
Finished Jun 26 06:53:59 PM PDT 24
Peak memory 218456 kb
Host smart-ff56c63f-31dc-4e08-9484-fa7b21009b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865751227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2865751227
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.494284677
Short name T168
Test name
Test status
Simulation time 2865076693 ps
CPU time 15.49 seconds
Started Jun 26 06:53:54 PM PDT 24
Finished Jun 26 06:54:12 PM PDT 24
Peak memory 219160 kb
Host smart-c2ab83cc-8446-49a8-a536-65ac253d86d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494284677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.494284677
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.2087173772
Short name T818
Test name
Test status
Simulation time 2285170253 ps
CPU time 15.02 seconds
Started Jun 26 06:53:54 PM PDT 24
Finished Jun 26 06:54:11 PM PDT 24
Peak memory 218516 kb
Host smart-a1786470-c25b-4b32-bf63-be4e4220f04d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087173772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.2087173772
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.2358543016
Short name T296
Test name
Test status
Simulation time 924534395 ps
CPU time 7.2 seconds
Started Jun 26 06:53:54 PM PDT 24
Finished Jun 26 06:54:04 PM PDT 24
Peak memory 218428 kb
Host smart-f10ac9df-a4ba-4e02-bd3f-a3a786a36501
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358543016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
2358543016
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1892330742
Short name T746
Test name
Test status
Simulation time 1872205577 ps
CPU time 12.39 seconds
Started Jun 26 06:53:54 PM PDT 24
Finished Jun 26 06:54:09 PM PDT 24
Peak memory 218576 kb
Host smart-94409834-ca54-467c-83d9-5cf774545e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892330742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1892330742
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1437887408
Short name T688
Test name
Test status
Simulation time 153932382 ps
CPU time 5.21 seconds
Started Jun 26 06:53:54 PM PDT 24
Finished Jun 26 06:54:02 PM PDT 24
Peak memory 217960 kb
Host smart-fa4fed3d-2081-45ec-a756-2783ad758793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437887408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1437887408
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.1797325581
Short name T842
Test name
Test status
Simulation time 855717042 ps
CPU time 27.02 seconds
Started Jun 26 06:53:54 PM PDT 24
Finished Jun 26 06:54:24 PM PDT 24
Peak memory 251136 kb
Host smart-ea0a24f2-8aaa-43d8-af1a-c88cf0e152b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797325581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.1797325581
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.2504428005
Short name T333
Test name
Test status
Simulation time 143397213 ps
CPU time 6.51 seconds
Started Jun 26 06:53:55 PM PDT 24
Finished Jun 26 06:54:04 PM PDT 24
Peak memory 247444 kb
Host smart-ce258a18-a349-405e-ae63-7e28b1aff747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504428005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.2504428005
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.3099236382
Short name T183
Test name
Test status
Simulation time 7822009461 ps
CPU time 213.55 seconds
Started Jun 26 06:53:54 PM PDT 24
Finished Jun 26 06:57:31 PM PDT 24
Peak memory 222288 kb
Host smart-f3527f68-b122-41f3-a639-4645e20eec99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099236382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.3099236382
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3081735128
Short name T444
Test name
Test status
Simulation time 13046664 ps
CPU time 1.01 seconds
Started Jun 26 06:53:55 PM PDT 24
Finished Jun 26 06:53:58 PM PDT 24
Peak memory 212228 kb
Host smart-a595ae92-801e-4e2f-a27e-5739940bff99
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081735128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3081735128
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2973235695
Short name T69
Test name
Test status
Simulation time 51555409 ps
CPU time 1.16 seconds
Started Jun 26 06:54:04 PM PDT 24
Finished Jun 26 06:54:07 PM PDT 24
Peak memory 209156 kb
Host smart-03148068-c506-4c83-8f27-457d6514f33d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973235695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2973235695
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.1047899877
Short name T543
Test name
Test status
Simulation time 1142698506 ps
CPU time 12.09 seconds
Started Jun 26 06:54:07 PM PDT 24
Finished Jun 26 06:54:20 PM PDT 24
Peak memory 226248 kb
Host smart-722778bc-bd39-4318-a1e3-83b6f14cf03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047899877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.1047899877
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1343633969
Short name T36
Test name
Test status
Simulation time 610067166 ps
CPU time 2.63 seconds
Started Jun 26 06:54:06 PM PDT 24
Finished Jun 26 06:54:11 PM PDT 24
Peak memory 217448 kb
Host smart-b2d272b7-a417-4c31-9195-8cce63882212
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343633969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1343633969
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.3918122670
Short name T452
Test name
Test status
Simulation time 4241148437 ps
CPU time 21.05 seconds
Started Jun 26 06:54:10 PM PDT 24
Finished Jun 26 06:54:32 PM PDT 24
Peak memory 219108 kb
Host smart-d292d6c7-ebf1-445f-9263-390397254cda
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918122670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.3918122670
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.568155720
Short name T642
Test name
Test status
Simulation time 159166836 ps
CPU time 3.33 seconds
Started Jun 26 06:54:05 PM PDT 24
Finished Jun 26 06:54:10 PM PDT 24
Peak memory 218432 kb
Host smart-036eafe8-b622-4d6a-b324-338be1cc7aff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568155720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.568155720
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.2495700802
Short name T237
Test name
Test status
Simulation time 407456539 ps
CPU time 5.8 seconds
Started Jun 26 06:54:04 PM PDT 24
Finished Jun 26 06:54:11 PM PDT 24
Peak memory 217932 kb
Host smart-b44ff472-3163-4ac6-9f9d-a861ef998823
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495700802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.2495700802
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.4266141113
Short name T108
Test name
Test status
Simulation time 1062696339 ps
CPU time 35.29 seconds
Started Jun 26 06:54:06 PM PDT 24
Finished Jun 26 06:54:43 PM PDT 24
Peak memory 251820 kb
Host smart-6ef8d87f-070a-422f-bfcb-861a60f17625
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266141113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.4266141113
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.918202187
Short name T382
Test name
Test status
Simulation time 1443345811 ps
CPU time 8.55 seconds
Started Jun 26 06:54:04 PM PDT 24
Finished Jun 26 06:54:14 PM PDT 24
Peak memory 223196 kb
Host smart-6fbb0541-2b00-4eea-9f8d-ca2891fb0ec7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918202187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_state_post_trans.918202187
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1070953763
Short name T754
Test name
Test status
Simulation time 31301596 ps
CPU time 1.46 seconds
Started Jun 26 06:54:06 PM PDT 24
Finished Jun 26 06:54:09 PM PDT 24
Peak memory 218524 kb
Host smart-7ea28da9-57f4-4f79-9dcb-484114e8d96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070953763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1070953763
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.2660517414
Short name T477
Test name
Test status
Simulation time 1782387381 ps
CPU time 14.33 seconds
Started Jun 26 06:54:07 PM PDT 24
Finished Jun 26 06:54:23 PM PDT 24
Peak memory 226248 kb
Host smart-d2074733-10e6-485c-ac9b-639830ded001
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660517414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.2660517414
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.1583757304
Short name T401
Test name
Test status
Simulation time 344580491 ps
CPU time 11.26 seconds
Started Jun 26 06:54:03 PM PDT 24
Finished Jun 26 06:54:15 PM PDT 24
Peak memory 218468 kb
Host smart-d5c7a59e-04e8-4426-96d6-48125e321e41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583757304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.1583757304
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1632326426
Short name T575
Test name
Test status
Simulation time 2693040100 ps
CPU time 9.73 seconds
Started Jun 26 06:54:10 PM PDT 24
Finished Jun 26 06:54:21 PM PDT 24
Peak memory 226240 kb
Host smart-1b4b29ab-38ae-493a-950e-79908774c125
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632326426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1632326426
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.789401729
Short name T765
Test name
Test status
Simulation time 2344210048 ps
CPU time 9.66 seconds
Started Jun 26 06:54:07 PM PDT 24
Finished Jun 26 06:54:18 PM PDT 24
Peak memory 218540 kb
Host smart-491fd999-b1ee-44f6-ae84-1e66632958ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789401729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.789401729
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1817431242
Short name T686
Test name
Test status
Simulation time 1065769171 ps
CPU time 14.68 seconds
Started Jun 26 06:54:10 PM PDT 24
Finished Jun 26 06:54:26 PM PDT 24
Peak memory 217876 kb
Host smart-e9353c06-2916-4ad2-8ae6-21bd298e4db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817431242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1817431242
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.2311368399
Short name T185
Test name
Test status
Simulation time 179425941 ps
CPU time 24.38 seconds
Started Jun 26 06:54:04 PM PDT 24
Finished Jun 26 06:54:30 PM PDT 24
Peak memory 251112 kb
Host smart-9e262e3a-ccf6-4f07-96f2-36f3e414a235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311368399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2311368399
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.275636183
Short name T229
Test name
Test status
Simulation time 128939639 ps
CPU time 7.59 seconds
Started Jun 26 06:54:06 PM PDT 24
Finished Jun 26 06:54:15 PM PDT 24
Peak memory 251200 kb
Host smart-265ebe35-7ecb-4beb-b373-19f8f0da22ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275636183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.275636183
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.2702643546
Short name T599
Test name
Test status
Simulation time 3800356724 ps
CPU time 29.56 seconds
Started Jun 26 06:54:10 PM PDT 24
Finished Jun 26 06:54:41 PM PDT 24
Peak memory 246488 kb
Host smart-a61d8c83-cbff-438e-86da-7060810d6795
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702643546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.2702643546
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3817233242
Short name T317
Test name
Test status
Simulation time 15514227 ps
CPU time 1.27 seconds
Started Jun 26 06:54:02 PM PDT 24
Finished Jun 26 06:54:04 PM PDT 24
Peak memory 218120 kb
Host smart-c058ecef-5ebf-40bb-bf2e-906ed862cf70
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817233242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.3817233242
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.1670206859
Short name T332
Test name
Test status
Simulation time 90015458 ps
CPU time 0.99 seconds
Started Jun 26 06:54:16 PM PDT 24
Finished Jun 26 06:54:19 PM PDT 24
Peak memory 209364 kb
Host smart-7da342b6-6aab-4ac4-91a4-cb6c2370069f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670206859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.1670206859
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.3519111074
Short name T851
Test name
Test status
Simulation time 1033042244 ps
CPU time 11.96 seconds
Started Jun 26 06:54:04 PM PDT 24
Finished Jun 26 06:54:18 PM PDT 24
Peak memory 218392 kb
Host smart-7560fc16-0467-44b3-87ef-9fefc97fae4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519111074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3519111074
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.2008813948
Short name T432
Test name
Test status
Simulation time 1366724405 ps
CPU time 16.09 seconds
Started Jun 26 06:54:06 PM PDT 24
Finished Jun 26 06:54:24 PM PDT 24
Peak memory 217672 kb
Host smart-a8f519d0-c427-44da-9ada-db87bbed69b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008813948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.2008813948
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.1331333061
Short name T627
Test name
Test status
Simulation time 2499771147 ps
CPU time 39.43 seconds
Started Jun 26 06:54:05 PM PDT 24
Finished Jun 26 06:54:46 PM PDT 24
Peak memory 218512 kb
Host smart-81f1b347-d453-4437-8d8e-7bc16c565483
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331333061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.1331333061
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.220015079
Short name T823
Test name
Test status
Simulation time 3276238453 ps
CPU time 12.01 seconds
Started Jun 26 06:54:04 PM PDT 24
Finished Jun 26 06:54:18 PM PDT 24
Peak memory 218496 kb
Host smart-14edd59b-31be-4dd2-8c13-e09bad821d89
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220015079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag
_prog_failure.220015079
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.409419420
Short name T80
Test name
Test status
Simulation time 211415653 ps
CPU time 1.4 seconds
Started Jun 26 06:54:10 PM PDT 24
Finished Jun 26 06:54:12 PM PDT 24
Peak memory 217864 kb
Host smart-cb3b9b8c-c138-4d07-a574-b8f138ca6deb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409419420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke.
409419420
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.926529096
Short name T325
Test name
Test status
Simulation time 8528840675 ps
CPU time 31.35 seconds
Started Jun 26 06:54:07 PM PDT 24
Finished Jun 26 06:54:40 PM PDT 24
Peak memory 251184 kb
Host smart-b448b65b-3d53-4403-90f1-3dcfb42d2ff6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926529096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_state_failure.926529096
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3462593741
Short name T41
Test name
Test status
Simulation time 1866962478 ps
CPU time 22.79 seconds
Started Jun 26 06:54:05 PM PDT 24
Finished Jun 26 06:54:29 PM PDT 24
Peak memory 251136 kb
Host smart-c6bda39b-e7b7-4c02-99b1-3bad5839308a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462593741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3462593741
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.988947606
Short name T802
Test name
Test status
Simulation time 383421667 ps
CPU time 3.37 seconds
Started Jun 26 06:54:03 PM PDT 24
Finished Jun 26 06:54:08 PM PDT 24
Peak memory 218444 kb
Host smart-989b3694-22f4-476b-9708-0e3ae74dd7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988947606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.988947606
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.2794608323
Short name T247
Test name
Test status
Simulation time 1724695002 ps
CPU time 12.06 seconds
Started Jun 26 06:54:17 PM PDT 24
Finished Jun 26 06:54:31 PM PDT 24
Peak memory 226272 kb
Host smart-ca81ab82-f092-44f4-a3ad-93c3de08ee04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794608323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.2794608323
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1036560833
Short name T624
Test name
Test status
Simulation time 1718865447 ps
CPU time 8.65 seconds
Started Jun 26 06:54:18 PM PDT 24
Finished Jun 26 06:54:29 PM PDT 24
Peak memory 218504 kb
Host smart-d5347ca5-ee68-403d-9279-8f55a5b4d6e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036560833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.1036560833
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.4192574248
Short name T40
Test name
Test status
Simulation time 896499100 ps
CPU time 13.05 seconds
Started Jun 26 06:54:18 PM PDT 24
Finished Jun 26 06:54:33 PM PDT 24
Peak memory 218468 kb
Host smart-78d21fde-d556-49fd-9af6-2aab1ac059cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192574248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
4192574248
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.535034412
Short name T635
Test name
Test status
Simulation time 280408701 ps
CPU time 10.66 seconds
Started Jun 26 06:54:04 PM PDT 24
Finished Jun 26 06:54:16 PM PDT 24
Peak memory 218572 kb
Host smart-7aea2e31-9c57-4531-bde9-500844175bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535034412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.535034412
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.2900305723
Short name T637
Test name
Test status
Simulation time 80555514 ps
CPU time 1.75 seconds
Started Jun 26 06:54:05 PM PDT 24
Finished Jun 26 06:54:08 PM PDT 24
Peak memory 214260 kb
Host smart-39b91719-7315-46dc-948c-cb94001c9f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900305723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.2900305723
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1233404101
Short name T481
Test name
Test status
Simulation time 845716265 ps
CPU time 26.33 seconds
Started Jun 26 06:54:10 PM PDT 24
Finished Jun 26 06:54:38 PM PDT 24
Peak memory 251056 kb
Host smart-57d837d1-e797-450c-9052-5cb218bd7202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233404101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1233404101
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.283453327
Short name T522
Test name
Test status
Simulation time 59392039 ps
CPU time 3.05 seconds
Started Jun 26 06:54:10 PM PDT 24
Finished Jun 26 06:54:14 PM PDT 24
Peak memory 222576 kb
Host smart-80397896-7ffc-4cb2-879c-0a5a4e7a48b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283453327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.283453327
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.3121341537
Short name T409
Test name
Test status
Simulation time 2507385469 ps
CPU time 96.12 seconds
Started Jun 26 06:54:16 PM PDT 24
Finished Jun 26 06:55:55 PM PDT 24
Peak memory 279272 kb
Host smart-cda42f6b-1844-4109-a989-73194d1ae4ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121341537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.3121341537
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3925569807
Short name T525
Test name
Test status
Simulation time 71420939 ps
CPU time 0.93 seconds
Started Jun 26 06:54:05 PM PDT 24
Finished Jun 26 06:54:07 PM PDT 24
Peak memory 217904 kb
Host smart-b44a5a62-88a9-439b-acac-514c56701ecc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925569807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3925569807
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.3826750603
Short name T222
Test name
Test status
Simulation time 19160760 ps
CPU time 0.96 seconds
Started Jun 26 06:54:17 PM PDT 24
Finished Jun 26 06:54:20 PM PDT 24
Peak memory 209160 kb
Host smart-0465c54b-b406-4755-a00e-edf1fd79ab35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826750603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.3826750603
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.1085338527
Short name T327
Test name
Test status
Simulation time 786062209 ps
CPU time 8.5 seconds
Started Jun 26 06:54:18 PM PDT 24
Finished Jun 26 06:54:29 PM PDT 24
Peak memory 226208 kb
Host smart-a7691c15-e379-415b-80d8-0fd41d95ce37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085338527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1085338527
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.3297429033
Short name T392
Test name
Test status
Simulation time 107057339 ps
CPU time 3.57 seconds
Started Jun 26 06:54:23 PM PDT 24
Finished Jun 26 06:54:27 PM PDT 24
Peak memory 217320 kb
Host smart-1b9b0b1c-b5e9-4313-b601-d6257f2d8180
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297429033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.3297429033
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.2408893785
Short name T503
Test name
Test status
Simulation time 3394224455 ps
CPU time 51.38 seconds
Started Jun 26 06:54:15 PM PDT 24
Finished Jun 26 06:55:08 PM PDT 24
Peak memory 226304 kb
Host smart-571196c4-4dff-46a6-ae92-fa325ed5e5f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408893785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.2408893785
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2653477032
Short name T28
Test name
Test status
Simulation time 375809087 ps
CPU time 8.52 seconds
Started Jun 26 06:54:16 PM PDT 24
Finished Jun 26 06:54:26 PM PDT 24
Peak memory 218444 kb
Host smart-fd637557-14a0-4a69-a37a-edea6b4c20dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653477032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.2653477032
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.2113047211
Short name T742
Test name
Test status
Simulation time 950932389 ps
CPU time 6.77 seconds
Started Jun 26 06:54:17 PM PDT 24
Finished Jun 26 06:54:26 PM PDT 24
Peak memory 217928 kb
Host smart-01741808-a721-4fb8-881f-9be5fbd7c4ff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113047211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.2113047211
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.400976158
Short name T630
Test name
Test status
Simulation time 11149115003 ps
CPU time 56.81 seconds
Started Jun 26 06:54:16 PM PDT 24
Finished Jun 26 06:55:15 PM PDT 24
Peak memory 251072 kb
Host smart-429461f9-bcae-4a07-95ab-a6907e43fd15
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400976158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.400976158
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.4265789649
Short name T383
Test name
Test status
Simulation time 2895183668 ps
CPU time 17.95 seconds
Started Jun 26 06:54:21 PM PDT 24
Finished Jun 26 06:54:40 PM PDT 24
Peak memory 251176 kb
Host smart-71d8b94d-1d12-4b58-961d-43f2f8cbaa7a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265789649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.4265789649
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.102002292
Short name T634
Test name
Test status
Simulation time 272630024 ps
CPU time 3.84 seconds
Started Jun 26 06:54:15 PM PDT 24
Finished Jun 26 06:54:20 PM PDT 24
Peak memory 218496 kb
Host smart-9a56e124-bc2b-4a19-a5ec-4c18bf0ac3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102002292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.102002292
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.184946312
Short name T607
Test name
Test status
Simulation time 468990968 ps
CPU time 10.73 seconds
Started Jun 26 06:54:16 PM PDT 24
Finished Jun 26 06:54:29 PM PDT 24
Peak memory 226208 kb
Host smart-03d76336-a469-4bb0-9c3c-94f5cf95358a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184946312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.184946312
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.133359987
Short name T613
Test name
Test status
Simulation time 387121537 ps
CPU time 10.93 seconds
Started Jun 26 06:54:16 PM PDT 24
Finished Jun 26 06:54:29 PM PDT 24
Peak memory 218440 kb
Host smart-858081a3-baa5-40e2-9660-02db57b4c974
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133359987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_di
gest.133359987
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.22251867
Short name T260
Test name
Test status
Simulation time 2687288823 ps
CPU time 13.35 seconds
Started Jun 26 06:54:19 PM PDT 24
Finished Jun 26 06:54:34 PM PDT 24
Peak memory 226268 kb
Host smart-13ce4cf1-7746-49e5-8b2a-af360feab686
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22251867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.22251867
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.1034810917
Short name T790
Test name
Test status
Simulation time 445963607 ps
CPU time 6.58 seconds
Started Jun 26 06:54:16 PM PDT 24
Finished Jun 26 06:54:24 PM PDT 24
Peak memory 218520 kb
Host smart-2d73b5be-59d0-4f31-963d-b556783f309d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034810917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.1034810917
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.150531959
Short name T519
Test name
Test status
Simulation time 118969340 ps
CPU time 2.42 seconds
Started Jun 26 06:54:17 PM PDT 24
Finished Jun 26 06:54:22 PM PDT 24
Peak memory 217952 kb
Host smart-7a470227-b1a5-4fdd-ba49-62d83cf4c12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150531959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.150531959
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.598796140
Short name T561
Test name
Test status
Simulation time 196597075 ps
CPU time 16.61 seconds
Started Jun 26 06:54:17 PM PDT 24
Finished Jun 26 06:54:36 PM PDT 24
Peak memory 251140 kb
Host smart-8dde1a57-46d7-40e3-81d7-6fa3d4324e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598796140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.598796140
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.756256610
Short name T360
Test name
Test status
Simulation time 295191392 ps
CPU time 6.44 seconds
Started Jun 26 06:54:19 PM PDT 24
Finished Jun 26 06:54:27 PM PDT 24
Peak memory 247172 kb
Host smart-fcde3e6f-9c83-4c41-81bc-3bfb2d8ca12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756256610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.756256610
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.1737397604
Short name T660
Test name
Test status
Simulation time 67423212 ps
CPU time 0.87 seconds
Started Jun 26 06:54:17 PM PDT 24
Finished Jun 26 06:54:20 PM PDT 24
Peak memory 212192 kb
Host smart-81e42668-cb96-4ddf-9631-ff20ccc3b255
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737397604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.1737397604
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.1557806733
Short name T606
Test name
Test status
Simulation time 31613039 ps
CPU time 0.88 seconds
Started Jun 26 06:54:31 PM PDT 24
Finished Jun 26 06:54:34 PM PDT 24
Peak memory 208948 kb
Host smart-a5145e75-7fe9-4168-9684-55d0103a9007
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557806733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1557806733
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3988952773
Short name T597
Test name
Test status
Simulation time 1576888176 ps
CPU time 8.27 seconds
Started Jun 26 06:54:15 PM PDT 24
Finished Jun 26 06:54:25 PM PDT 24
Peak memory 218448 kb
Host smart-756c76e0-f9c3-448e-9e77-9789486c0fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988952773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3988952773
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.978090737
Short name T34
Test name
Test status
Simulation time 11125575899 ps
CPU time 8.82 seconds
Started Jun 26 06:54:28 PM PDT 24
Finished Jun 26 06:54:38 PM PDT 24
Peak memory 217992 kb
Host smart-63069e0c-06aa-4fde-991b-3b5b5ad662e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978090737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.978090737
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1661360291
Short name T372
Test name
Test status
Simulation time 4791020147 ps
CPU time 39.46 seconds
Started Jun 26 06:54:28 PM PDT 24
Finished Jun 26 06:55:10 PM PDT 24
Peak memory 220184 kb
Host smart-d20e43e0-24b9-4d7e-b742-d8d325108ab6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661360291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1661360291
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.419384007
Short name T563
Test name
Test status
Simulation time 882566533 ps
CPU time 8.18 seconds
Started Jun 26 06:54:30 PM PDT 24
Finished Jun 26 06:54:40 PM PDT 24
Peak memory 224292 kb
Host smart-05360fe7-9f32-493d-9b66-751679370617
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419384007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_prog_failure.419384007
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.4276642501
Short name T819
Test name
Test status
Simulation time 970869085 ps
CPU time 3.75 seconds
Started Jun 26 06:54:16 PM PDT 24
Finished Jun 26 06:54:22 PM PDT 24
Peak memory 217928 kb
Host smart-325e754d-6f75-49d8-87ac-dd7724fa97a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276642501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.4276642501
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1994758054
Short name T631
Test name
Test status
Simulation time 1183198492 ps
CPU time 16.32 seconds
Started Jun 26 06:54:29 PM PDT 24
Finished Jun 26 06:54:47 PM PDT 24
Peak memory 249892 kb
Host smart-b629c2b1-bc6c-4760-95cd-a57ce6f9a48e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994758054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.1994758054
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.2371615883
Short name T529
Test name
Test status
Simulation time 132482973 ps
CPU time 1.77 seconds
Started Jun 26 06:54:17 PM PDT 24
Finished Jun 26 06:54:21 PM PDT 24
Peak memory 218436 kb
Host smart-ea5cf52a-d39e-4e62-b558-2208c3f64594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371615883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2371615883
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.9339930
Short name T368
Test name
Test status
Simulation time 424842081 ps
CPU time 14.08 seconds
Started Jun 26 06:54:30 PM PDT 24
Finished Jun 26 06:54:46 PM PDT 24
Peak memory 226224 kb
Host smart-31098c22-28b4-40c7-b7af-3b787b1533f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9339930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.9339930
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.3262168199
Short name T400
Test name
Test status
Simulation time 1099997055 ps
CPU time 11.13 seconds
Started Jun 26 06:54:29 PM PDT 24
Finished Jun 26 06:54:42 PM PDT 24
Peak memory 218412 kb
Host smart-84ec1ddd-e962-41a9-b2d7-26e809dc4f42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262168199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.3262168199
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1606487693
Short name T393
Test name
Test status
Simulation time 2609829005 ps
CPU time 13 seconds
Started Jun 26 06:54:29 PM PDT 24
Finished Jun 26 06:54:45 PM PDT 24
Peak memory 218488 kb
Host smart-eeca16c6-8cdd-4c50-a629-76bcbe72cc72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606487693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1606487693
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2598031357
Short name T551
Test name
Test status
Simulation time 1158510987 ps
CPU time 8.83 seconds
Started Jun 26 06:54:17 PM PDT 24
Finished Jun 26 06:54:28 PM PDT 24
Peak memory 218500 kb
Host smart-6e7b9ed4-a8c7-47e9-91df-fd530c1aba3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598031357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2598031357
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.2905052032
Short name T267
Test name
Test status
Simulation time 115552281 ps
CPU time 1.69 seconds
Started Jun 26 06:54:18 PM PDT 24
Finished Jun 26 06:54:22 PM PDT 24
Peak memory 214184 kb
Host smart-c1aeb9d1-67af-4f5a-8cf5-71307839987f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905052032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2905052032
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2033295361
Short name T770
Test name
Test status
Simulation time 421727213 ps
CPU time 21.18 seconds
Started Jun 26 06:54:18 PM PDT 24
Finished Jun 26 06:54:41 PM PDT 24
Peak memory 251132 kb
Host smart-3e65e445-bc95-4e70-ba6d-91e4cbf8e75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033295361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2033295361
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2132481525
Short name T226
Test name
Test status
Simulation time 386756660 ps
CPU time 9.27 seconds
Started Jun 26 06:54:19 PM PDT 24
Finished Jun 26 06:54:30 PM PDT 24
Peak memory 251116 kb
Host smart-02aeb278-87a4-4f5f-bce3-feb47b5c84fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132481525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2132481525
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.1369058371
Short name T748
Test name
Test status
Simulation time 11010872550 ps
CPU time 254.75 seconds
Started Jun 26 06:54:29 PM PDT 24
Finished Jun 26 06:58:46 PM PDT 24
Peak memory 250752 kb
Host smart-9b40d538-9408-452c-b9c5-f57eb95bbb73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369058371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.1369058371
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.1590266112
Short name T158
Test name
Test status
Simulation time 120582479775 ps
CPU time 1016.83 seconds
Started Jun 26 06:54:30 PM PDT 24
Finished Jun 26 07:11:29 PM PDT 24
Peak memory 333248 kb
Host smart-9959bfcc-2e86-4d4f-af0a-daa5ec8eeb6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1590266112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.1590266112
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.379579763
Short name T573
Test name
Test status
Simulation time 14264790 ps
CPU time 1.07 seconds
Started Jun 26 06:54:16 PM PDT 24
Finished Jun 26 06:54:19 PM PDT 24
Peak memory 212172 kb
Host smart-d9cf6c57-c394-43b9-a542-3d9540b989de
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379579763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.379579763
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.727336492
Short name T397
Test name
Test status
Simulation time 110103121 ps
CPU time 0.9 seconds
Started Jun 26 06:54:29 PM PDT 24
Finished Jun 26 06:54:32 PM PDT 24
Peak memory 209176 kb
Host smart-1c34d369-3c69-4546-8b74-4132dd4726f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727336492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.727336492
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.3817904300
Short name T738
Test name
Test status
Simulation time 252401944 ps
CPU time 9.09 seconds
Started Jun 26 06:54:31 PM PDT 24
Finished Jun 26 06:54:42 PM PDT 24
Peak memory 218420 kb
Host smart-5ee9b713-135a-4c4e-967d-880fbb10e282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817904300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.3817904300
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.3687999719
Short name T193
Test name
Test status
Simulation time 1131301923 ps
CPU time 14.74 seconds
Started Jun 26 06:54:30 PM PDT 24
Finished Jun 26 06:54:47 PM PDT 24
Peak memory 217684 kb
Host smart-576855e6-cffc-4bc4-a6f0-07c366554035
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687999719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.3687999719
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2605289348
Short name T265
Test name
Test status
Simulation time 5678388572 ps
CPU time 39.48 seconds
Started Jun 26 06:54:28 PM PDT 24
Finished Jun 26 06:55:09 PM PDT 24
Peak memory 219012 kb
Host smart-e92377d8-4362-46d7-9890-2b40514649b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605289348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2605289348
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2185095634
Short name T664
Test name
Test status
Simulation time 1001545428 ps
CPU time 14.37 seconds
Started Jun 26 06:54:28 PM PDT 24
Finished Jun 26 06:54:45 PM PDT 24
Peak memory 218424 kb
Host smart-1e4d2f1e-6a63-4793-ad64-0fecaf387f6d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185095634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.2185095634
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2579823861
Short name T352
Test name
Test status
Simulation time 280526040 ps
CPU time 4.96 seconds
Started Jun 26 06:54:29 PM PDT 24
Finished Jun 26 06:54:36 PM PDT 24
Peak memory 217916 kb
Host smart-ef30cfb2-f518-476a-b78c-c3fa1232509e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579823861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2579823861
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.902626604
Short name T584
Test name
Test status
Simulation time 307325658 ps
CPU time 10.46 seconds
Started Jun 26 06:54:29 PM PDT 24
Finished Jun 26 06:54:42 PM PDT 24
Peak memory 250496 kb
Host smart-8f4c8a54-dd9c-4f84-8fde-8a3e743dc1eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902626604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_
jtag_state_post_trans.902626604
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3986386964
Short name T572
Test name
Test status
Simulation time 286542595 ps
CPU time 2.15 seconds
Started Jun 26 06:54:28 PM PDT 24
Finished Jun 26 06:54:31 PM PDT 24
Peak memory 222496 kb
Host smart-6c5e9957-4d36-4081-b4d6-ad26225dd9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986386964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3986386964
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.2605944624
Short name T309
Test name
Test status
Simulation time 330994869 ps
CPU time 14.5 seconds
Started Jun 26 06:54:32 PM PDT 24
Finished Jun 26 06:54:48 PM PDT 24
Peak memory 226232 kb
Host smart-4de27a4f-60dd-42f1-ad98-2773a9775d5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605944624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.2605944624
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2092069398
Short name T798
Test name
Test status
Simulation time 1806041133 ps
CPU time 18.14 seconds
Started Jun 26 06:54:30 PM PDT 24
Finished Jun 26 06:54:51 PM PDT 24
Peak memory 218664 kb
Host smart-d831cbf5-c866-40d6-922f-0a7875db8239
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092069398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.2092069398
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.3762880678
Short name T478
Test name
Test status
Simulation time 1226854339 ps
CPU time 9.85 seconds
Started Jun 26 06:54:30 PM PDT 24
Finished Jun 26 06:54:42 PM PDT 24
Peak memory 218452 kb
Host smart-57f5ec85-81af-4847-a525-50c944b5b661
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762880678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
3762880678
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.596047444
Short name T614
Test name
Test status
Simulation time 347314296 ps
CPU time 12.86 seconds
Started Jun 26 06:54:31 PM PDT 24
Finished Jun 26 06:54:46 PM PDT 24
Peak memory 218524 kb
Host smart-745d0e7f-2a3f-41c4-8ac5-2c9b41af7801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596047444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.596047444
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.3412901188
Short name T863
Test name
Test status
Simulation time 40186924 ps
CPU time 0.97 seconds
Started Jun 26 06:54:29 PM PDT 24
Finished Jun 26 06:54:32 PM PDT 24
Peak memory 212576 kb
Host smart-434b9bdf-efe8-4d4f-b0ac-d67566626f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412901188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3412901188
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1617042384
Short name T313
Test name
Test status
Simulation time 442109650 ps
CPU time 24.41 seconds
Started Jun 26 06:54:29 PM PDT 24
Finished Jun 26 06:54:56 PM PDT 24
Peak memory 251152 kb
Host smart-a30fba2d-c85e-4b54-9e82-04048cbfb472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617042384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1617042384
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2344327812
Short name T533
Test name
Test status
Simulation time 296296127 ps
CPU time 3.39 seconds
Started Jun 26 06:54:30 PM PDT 24
Finished Jun 26 06:54:35 PM PDT 24
Peak memory 218344 kb
Host smart-7caa1340-a7e8-4f21-b991-6a74e38332e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344327812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2344327812
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1771353161
Short name T63
Test name
Test status
Simulation time 58802589292 ps
CPU time 251.8 seconds
Started Jun 26 06:54:30 PM PDT 24
Finished Jun 26 06:58:44 PM PDT 24
Peak memory 276824 kb
Host smart-dcdb24b4-3b2c-4d77-942d-d060afdc9055
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771353161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1771353161
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3047693067
Short name T571
Test name
Test status
Simulation time 14664483 ps
CPU time 0.9 seconds
Started Jun 26 06:54:30 PM PDT 24
Finished Jun 26 06:54:33 PM PDT 24
Peak memory 212320 kb
Host smart-73cd7b3c-d4ab-4780-bb84-760b387b6501
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047693067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3047693067
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.656505918
Short name T821
Test name
Test status
Simulation time 144190889 ps
CPU time 1.36 seconds
Started Jun 26 06:52:04 PM PDT 24
Finished Jun 26 06:52:07 PM PDT 24
Peak memory 209424 kb
Host smart-715a35ec-7b7e-4a13-a565-97f4ce79c16a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656505918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.656505918
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.3501793367
Short name T42
Test name
Test status
Simulation time 38045320 ps
CPU time 0.93 seconds
Started Jun 26 06:52:08 PM PDT 24
Finished Jun 26 06:52:10 PM PDT 24
Peak memory 209196 kb
Host smart-3def5d7f-155e-4153-8598-051b5a770479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501793367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.3501793367
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.3716052832
Short name T492
Test name
Test status
Simulation time 1115512346 ps
CPU time 11.77 seconds
Started Jun 26 06:52:07 PM PDT 24
Finished Jun 26 06:52:20 PM PDT 24
Peak memory 218376 kb
Host smart-4b02fcef-f45f-4dfb-bbe7-7f3f70248a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716052832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.3716052832
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.722548580
Short name T716
Test name
Test status
Simulation time 819556416 ps
CPU time 3.56 seconds
Started Jun 26 06:52:02 PM PDT 24
Finished Jun 26 06:52:07 PM PDT 24
Peak memory 217288 kb
Host smart-3758c017-f669-4294-b59c-18cfcdc43ecd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722548580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.722548580
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.2494548384
Short name T542
Test name
Test status
Simulation time 9586031090 ps
CPU time 33.64 seconds
Started Jun 26 06:52:08 PM PDT 24
Finished Jun 26 06:52:43 PM PDT 24
Peak memory 218904 kb
Host smart-9c94beda-11de-494a-91a0-57b89fcb4251
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494548384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.2494548384
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.564198514
Short name T693
Test name
Test status
Simulation time 433350994 ps
CPU time 4.85 seconds
Started Jun 26 06:52:04 PM PDT 24
Finished Jun 26 06:52:09 PM PDT 24
Peak memory 217652 kb
Host smart-77866a4e-3b27-42ee-9cae-1ecc48478203
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564198514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.564198514
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3433767929
Short name T318
Test name
Test status
Simulation time 347994725 ps
CPU time 6.11 seconds
Started Jun 26 06:52:07 PM PDT 24
Finished Jun 26 06:52:14 PM PDT 24
Peak memory 218380 kb
Host smart-fb450559-7631-4e43-a152-6ccded3530f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433767929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3433767929
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3986180420
Short name T433
Test name
Test status
Simulation time 1947282521 ps
CPU time 14.55 seconds
Started Jun 26 06:52:03 PM PDT 24
Finished Jun 26 06:52:18 PM PDT 24
Peak memory 217936 kb
Host smart-e9345c7a-90f5-46ea-8535-aa820130a73a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986180420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.3986180420
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1880746581
Short name T278
Test name
Test status
Simulation time 725209111 ps
CPU time 5.7 seconds
Started Jun 26 06:52:03 PM PDT 24
Finished Jun 26 06:52:10 PM PDT 24
Peak memory 217928 kb
Host smart-28b7a797-b70a-4c0a-be04-a9b23dc663f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880746581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1880746581
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.9067166
Short name T415
Test name
Test status
Simulation time 2746721727 ps
CPU time 54.06 seconds
Started Jun 26 06:52:03 PM PDT 24
Finished Jun 26 06:52:58 PM PDT 24
Peak memory 271204 kb
Host smart-89d56cd5-079e-4a88-b856-398dd4077b04
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9067166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_st
ate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_s
tate_failure.9067166
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.375406476
Short name T570
Test name
Test status
Simulation time 1535676128 ps
CPU time 23.35 seconds
Started Jun 26 06:52:06 PM PDT 24
Finished Jun 26 06:52:31 PM PDT 24
Peak memory 250652 kb
Host smart-566d3697-194c-4ce5-8c1a-c5a06c78e815
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375406476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.375406476
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3256161587
Short name T838
Test name
Test status
Simulation time 61782176 ps
CPU time 2.68 seconds
Started Jun 26 06:52:08 PM PDT 24
Finished Jun 26 06:52:12 PM PDT 24
Peak memory 218384 kb
Host smart-2f3ad152-82ef-4b1f-bc4f-827714fab081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256161587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3256161587
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.283930191
Short name T293
Test name
Test status
Simulation time 408979182 ps
CPU time 15.6 seconds
Started Jun 26 06:52:07 PM PDT 24
Finished Jun 26 06:52:24 PM PDT 24
Peak memory 215052 kb
Host smart-13aa35bc-6797-432c-89e5-78ad1da570b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283930191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.283930191
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2956288312
Short name T94
Test name
Test status
Simulation time 458077122 ps
CPU time 24 seconds
Started Jun 26 06:52:03 PM PDT 24
Finished Jun 26 06:52:28 PM PDT 24
Peak memory 280076 kb
Host smart-47864e3d-8928-4d3c-a918-5d7f51632df6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956288312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2956288312
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.400655655
Short name T553
Test name
Test status
Simulation time 384810130 ps
CPU time 8.98 seconds
Started Jun 26 06:52:07 PM PDT 24
Finished Jun 26 06:52:17 PM PDT 24
Peak memory 226212 kb
Host smart-4fe6ac24-da16-49a8-b37f-9bc4489292c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400655655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.400655655
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.165569905
Short name T536
Test name
Test status
Simulation time 346657841 ps
CPU time 11.34 seconds
Started Jun 26 06:52:02 PM PDT 24
Finished Jun 26 06:52:15 PM PDT 24
Peak memory 218472 kb
Host smart-27c60212-e028-463e-941e-bb474c7b03fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165569905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_dig
est.165569905
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.3642620546
Short name T479
Test name
Test status
Simulation time 1503989380 ps
CPU time 5.98 seconds
Started Jun 26 06:52:05 PM PDT 24
Finished Jun 26 06:52:12 PM PDT 24
Peak memory 218364 kb
Host smart-b00793c9-2fad-496f-9a31-cc07ea79e604
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642620546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.3
642620546
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.1870330147
Short name T859
Test name
Test status
Simulation time 339854240 ps
CPU time 10.49 seconds
Started Jun 26 06:52:04 PM PDT 24
Finished Jun 26 06:52:16 PM PDT 24
Peak memory 218712 kb
Host smart-6d64d0c0-c353-416d-8b6c-a54004c65060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870330147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1870330147
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.2212576328
Short name T843
Test name
Test status
Simulation time 83090135 ps
CPU time 1.72 seconds
Started Jun 26 06:52:02 PM PDT 24
Finished Jun 26 06:52:05 PM PDT 24
Peak memory 214124 kb
Host smart-fda82166-b303-47a7-899d-e5eca8e75799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212576328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.2212576328
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.16034334
Short name T249
Test name
Test status
Simulation time 1195309803 ps
CPU time 27.37 seconds
Started Jun 26 06:52:08 PM PDT 24
Finished Jun 26 06:52:36 PM PDT 24
Peak memory 251104 kb
Host smart-260dad0b-91bc-4cb9-ba75-c07bf2259800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16034334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.16034334
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.3641051015
Short name T545
Test name
Test status
Simulation time 60972890 ps
CPU time 6.79 seconds
Started Jun 26 06:52:02 PM PDT 24
Finished Jun 26 06:52:10 PM PDT 24
Peak memory 251000 kb
Host smart-d936eb87-3236-48fc-ab84-af43bc98795e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641051015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3641051015
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2891409905
Short name T499
Test name
Test status
Simulation time 32048690405 ps
CPU time 268.67 seconds
Started Jun 26 06:52:01 PM PDT 24
Finished Jun 26 06:56:30 PM PDT 24
Peak memory 227168 kb
Host smart-71a82525-0131-4ebf-9037-7f6ef4e832ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891409905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2891409905
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.313150820
Short name T497
Test name
Test status
Simulation time 24031145 ps
CPU time 1.05 seconds
Started Jun 26 06:52:05 PM PDT 24
Finished Jun 26 06:52:07 PM PDT 24
Peak memory 212252 kb
Host smart-0b573dd4-9cd5-478d-bda0-ca0dc53b6ffb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313150820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr
l_volatile_unlock_smoke.313150820
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.3347162838
Short name T510
Test name
Test status
Simulation time 18236910 ps
CPU time 1 seconds
Started Jun 26 06:55:06 PM PDT 24
Finished Jun 26 06:55:09 PM PDT 24
Peak memory 209172 kb
Host smart-ae0d305f-44b0-46f4-9edc-eef99d96e367
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347162838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.3347162838
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.2015356193
Short name T298
Test name
Test status
Simulation time 283528734 ps
CPU time 10.97 seconds
Started Jun 26 06:54:46 PM PDT 24
Finished Jun 26 06:54:59 PM PDT 24
Peak memory 217932 kb
Host smart-4412ba26-1e8a-4a4d-b781-3b2f6edf0040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015356193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2015356193
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.265487769
Short name T661
Test name
Test status
Simulation time 267213635 ps
CPU time 4.03 seconds
Started Jun 26 06:54:42 PM PDT 24
Finished Jun 26 06:54:48 PM PDT 24
Peak memory 217604 kb
Host smart-8ac90e3f-6c30-4ad4-8df3-f79d56c0ba8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265487769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.265487769
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2646372980
Short name T653
Test name
Test status
Simulation time 124006832 ps
CPU time 3.61 seconds
Started Jun 26 06:54:43 PM PDT 24
Finished Jun 26 06:54:49 PM PDT 24
Peak memory 218412 kb
Host smart-5187fd5f-e68a-40d3-95af-fdff0384cce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646372980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2646372980
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.3208318166
Short name T749
Test name
Test status
Simulation time 239906548 ps
CPU time 10.16 seconds
Started Jun 26 06:54:47 PM PDT 24
Finished Jun 26 06:54:59 PM PDT 24
Peak memory 218396 kb
Host smart-68290862-5146-4b67-8140-4d7cfdf8f708
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208318166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.3208318166
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.439555118
Short name T785
Test name
Test status
Simulation time 2754542712 ps
CPU time 14.2 seconds
Started Jun 26 06:54:41 PM PDT 24
Finished Jun 26 06:54:57 PM PDT 24
Peak memory 218544 kb
Host smart-99f9e8b1-ed2e-4a7e-8ebc-340004ccbb77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439555118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_di
gest.439555118
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.804640546
Short name T706
Test name
Test status
Simulation time 638026725 ps
CPU time 12.72 seconds
Started Jun 26 06:54:44 PM PDT 24
Finished Jun 26 06:55:00 PM PDT 24
Peak memory 218476 kb
Host smart-38c09edb-5372-408f-bb75-c6878ab38101
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804640546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.804640546
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.3391198081
Short name T514
Test name
Test status
Simulation time 109519752 ps
CPU time 2.88 seconds
Started Jun 26 06:54:31 PM PDT 24
Finished Jun 26 06:54:36 PM PDT 24
Peak memory 217912 kb
Host smart-3fac891e-268d-4d0e-8403-9616890c8b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391198081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3391198081
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.1088951445
Short name T227
Test name
Test status
Simulation time 211995789 ps
CPU time 21.37 seconds
Started Jun 26 06:54:42 PM PDT 24
Finished Jun 26 06:55:05 PM PDT 24
Peak memory 251136 kb
Host smart-a3f6f3c4-6c73-4ff8-9ac9-891d1c54ee70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088951445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1088951445
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.44376300
Short name T840
Test name
Test status
Simulation time 64612746 ps
CPU time 6.94 seconds
Started Jun 26 06:54:45 PM PDT 24
Finished Jun 26 06:54:55 PM PDT 24
Peak memory 250020 kb
Host smart-a63de1a4-8365-4e77-97a4-ac43be303c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44376300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.44376300
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2725779226
Short name T532
Test name
Test status
Simulation time 32993546265 ps
CPU time 247.39 seconds
Started Jun 26 06:54:41 PM PDT 24
Finished Jun 26 06:58:50 PM PDT 24
Peak memory 300244 kb
Host smart-afe8bac8-d7a7-4a4b-a368-adac44d32d85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725779226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2725779226
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.2118931055
Short name T151
Test name
Test status
Simulation time 100109455157 ps
CPU time 570.54 seconds
Started Jun 26 06:54:45 PM PDT 24
Finished Jun 26 07:04:18 PM PDT 24
Peak memory 497080 kb
Host smart-b49df78a-e9f4-42c7-a53b-6ed34e8f627b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2118931055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.2118931055
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.531630591
Short name T331
Test name
Test status
Simulation time 18735550 ps
CPU time 0.78 seconds
Started Jun 26 06:54:42 PM PDT 24
Finished Jun 26 06:54:45 PM PDT 24
Peak memory 207292 kb
Host smart-d2def498-36ef-4281-a779-a98ddb5adbc7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531630591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ct
rl_volatile_unlock_smoke.531630591
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.2357571227
Short name T374
Test name
Test status
Simulation time 13874715 ps
CPU time 0.83 seconds
Started Jun 26 06:54:45 PM PDT 24
Finished Jun 26 06:54:48 PM PDT 24
Peak memory 209004 kb
Host smart-a21026f6-f0de-4914-9ff5-b244442cf2f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357571227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2357571227
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.2572137998
Short name T283
Test name
Test status
Simulation time 309459788 ps
CPU time 15.26 seconds
Started Jun 26 06:54:44 PM PDT 24
Finished Jun 26 06:55:02 PM PDT 24
Peak memory 218448 kb
Host smart-7a662f29-38ab-4a83-8894-da7faeb2dfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572137998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.2572137998
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.757548446
Short name T564
Test name
Test status
Simulation time 1142900318 ps
CPU time 7.56 seconds
Started Jun 26 06:54:41 PM PDT 24
Finished Jun 26 06:54:50 PM PDT 24
Peak memory 217636 kb
Host smart-4aa16032-e00a-4ee4-a53f-b6640702e5f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757548446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.757548446
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.299825944
Short name T526
Test name
Test status
Simulation time 74988920 ps
CPU time 1.86 seconds
Started Jun 26 06:54:42 PM PDT 24
Finished Jun 26 06:54:47 PM PDT 24
Peak memory 222220 kb
Host smart-97d265c9-c41b-4ad9-bab5-c9371a0788a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299825944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.299825944
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.3760611112
Short name T827
Test name
Test status
Simulation time 1149568739 ps
CPU time 13.1 seconds
Started Jun 26 06:54:40 PM PDT 24
Finished Jun 26 06:54:54 PM PDT 24
Peak memory 219104 kb
Host smart-0b3c32ed-9a30-4cbf-af9c-de9132cb4399
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760611112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3760611112
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1536444177
Short name T511
Test name
Test status
Simulation time 563122805 ps
CPU time 17.87 seconds
Started Jun 26 06:54:43 PM PDT 24
Finished Jun 26 06:55:03 PM PDT 24
Peak memory 218548 kb
Host smart-17af04b1-5c3e-4cdc-8e76-d72d6fdc9e41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536444177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1536444177
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.4205538336
Short name T849
Test name
Test status
Simulation time 1359134583 ps
CPU time 11.36 seconds
Started Jun 26 06:54:41 PM PDT 24
Finished Jun 26 06:54:55 PM PDT 24
Peak memory 218644 kb
Host smart-2e99b32e-c657-4b7c-95d6-753902528a7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205538336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
4205538336
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2875134736
Short name T586
Test name
Test status
Simulation time 1548629343 ps
CPU time 9.16 seconds
Started Jun 26 06:54:41 PM PDT 24
Finished Jun 26 06:54:52 PM PDT 24
Peak memory 218504 kb
Host smart-136eb4a0-bfca-4aa2-be42-6628089048f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875134736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2875134736
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.2203935441
Short name T794
Test name
Test status
Simulation time 69085207 ps
CPU time 2.6 seconds
Started Jun 26 06:54:47 PM PDT 24
Finished Jun 26 06:54:51 PM PDT 24
Peak memory 217888 kb
Host smart-f9afb5fb-9c5d-4a28-b540-056fd7580d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203935441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.2203935441
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.437908202
Short name T338
Test name
Test status
Simulation time 184255260 ps
CPU time 25.14 seconds
Started Jun 26 06:54:42 PM PDT 24
Finished Jun 26 06:55:09 PM PDT 24
Peak memory 251116 kb
Host smart-f817b84c-3e7f-4f0a-a0aa-b43fd1b5e451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437908202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.437908202
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.884007090
Short name T326
Test name
Test status
Simulation time 285723029 ps
CPU time 7.34 seconds
Started Jun 26 06:54:45 PM PDT 24
Finished Jun 26 06:54:55 PM PDT 24
Peak memory 249924 kb
Host smart-7aa8feec-0a3b-4a05-939e-9acf8651fb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884007090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.884007090
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.2486164289
Short name T191
Test name
Test status
Simulation time 1955729246 ps
CPU time 54.26 seconds
Started Jun 26 06:54:42 PM PDT 24
Finished Jun 26 06:55:38 PM PDT 24
Peak memory 251116 kb
Host smart-ba5556e1-dbe9-469f-9703-d4b52d5af3ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486164289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.2486164289
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.1613509274
Short name T153
Test name
Test status
Simulation time 20180172208 ps
CPU time 1028.63 seconds
Started Jun 26 06:54:43 PM PDT 24
Finished Jun 26 07:11:54 PM PDT 24
Peak memory 497072 kb
Host smart-79b2961c-97a1-47c3-b1db-57b53b731ddc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1613509274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.1613509274
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.4001134420
Short name T238
Test name
Test status
Simulation time 19585999 ps
CPU time 1.02 seconds
Started Jun 26 06:54:42 PM PDT 24
Finished Jun 26 06:54:46 PM PDT 24
Peak memory 212044 kb
Host smart-2e272bf9-5c84-4732-a0f7-45f1ee5b6322
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001134420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.4001134420
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.993111883
Short name T848
Test name
Test status
Simulation time 116127852 ps
CPU time 0.93 seconds
Started Jun 26 06:54:55 PM PDT 24
Finished Jun 26 06:54:58 PM PDT 24
Peak memory 209188 kb
Host smart-420c8d04-c1c6-4c27-86d5-3a8d1e2bc2cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993111883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.993111883
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2178757399
Short name T761
Test name
Test status
Simulation time 275652825 ps
CPU time 11.53 seconds
Started Jun 26 06:54:41 PM PDT 24
Finished Jun 26 06:54:55 PM PDT 24
Peak memory 226252 kb
Host smart-64cd24b3-e623-482e-a0ee-246118ce6ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178757399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2178757399
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.2691425796
Short name T71
Test name
Test status
Simulation time 374167605 ps
CPU time 1.33 seconds
Started Jun 26 06:54:55 PM PDT 24
Finished Jun 26 06:54:59 PM PDT 24
Peak memory 217336 kb
Host smart-6c4c3ee8-d732-4c4a-8c77-85a219772167
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691425796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.2691425796
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3187217114
Short name T709
Test name
Test status
Simulation time 83324912 ps
CPU time 2.85 seconds
Started Jun 26 06:54:44 PM PDT 24
Finished Jun 26 06:54:49 PM PDT 24
Peak memory 218444 kb
Host smart-9f8672a9-7a58-436d-87eb-ebc16ff85d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187217114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3187217114
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.190916743
Short name T47
Test name
Test status
Simulation time 1376284047 ps
CPU time 16.37 seconds
Started Jun 26 06:54:56 PM PDT 24
Finished Jun 26 06:55:14 PM PDT 24
Peak memory 226188 kb
Host smart-8f157151-6733-4ac8-be2d-51e044a6aa19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190916743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.190916743
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3466831324
Short name T758
Test name
Test status
Simulation time 618879127 ps
CPU time 14.31 seconds
Started Jun 26 06:54:55 PM PDT 24
Finished Jun 26 06:55:12 PM PDT 24
Peak memory 218532 kb
Host smart-0c1b1365-13ee-4be3-bd69-453808dd1786
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466831324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3466831324
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.1079623736
Short name T809
Test name
Test status
Simulation time 1577108111 ps
CPU time 10.45 seconds
Started Jun 26 06:54:54 PM PDT 24
Finished Jun 26 06:55:06 PM PDT 24
Peak memory 218432 kb
Host smart-9519ea04-1f9e-4738-94e0-f0a5de236eed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079623736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
1079623736
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.3221983066
Short name T464
Test name
Test status
Simulation time 506646747 ps
CPU time 10.27 seconds
Started Jun 26 06:54:57 PM PDT 24
Finished Jun 26 06:55:09 PM PDT 24
Peak memory 218516 kb
Host smart-201d3c23-8e00-4b5e-95bf-0d5b8877cf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221983066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3221983066
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.3188636296
Short name T724
Test name
Test status
Simulation time 515545547 ps
CPU time 2.65 seconds
Started Jun 26 06:54:43 PM PDT 24
Finished Jun 26 06:54:48 PM PDT 24
Peak memory 214948 kb
Host smart-3ccc176a-c98a-4fe5-b0e8-e965b1c8c9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188636296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3188636296
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.1320100260
Short name T647
Test name
Test status
Simulation time 210117811 ps
CPU time 19.25 seconds
Started Jun 26 06:54:46 PM PDT 24
Finished Jun 26 06:55:07 PM PDT 24
Peak memory 250652 kb
Host smart-4db7f8c5-8162-44a6-b2fa-64f1aeeb34ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320100260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1320100260
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1127188493
Short name T271
Test name
Test status
Simulation time 208314108 ps
CPU time 6.59 seconds
Started Jun 26 06:54:44 PM PDT 24
Finished Jun 26 06:54:53 PM PDT 24
Peak memory 250728 kb
Host smart-39cdc7f4-9f3b-4618-8367-bd28ec88b756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127188493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1127188493
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.188724886
Short name T788
Test name
Test status
Simulation time 64117210151 ps
CPU time 484.95 seconds
Started Jun 26 06:54:56 PM PDT 24
Finished Jun 26 07:03:03 PM PDT 24
Peak memory 266800 kb
Host smart-12207c70-345a-4425-a727-1fbaff7e08e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188724886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.188724886
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.523397394
Short name T384
Test name
Test status
Simulation time 21596721 ps
CPU time 0.93 seconds
Started Jun 26 06:54:44 PM PDT 24
Finished Jun 26 06:54:47 PM PDT 24
Peak memory 212104 kb
Host smart-727ff147-19ce-4821-a5a7-f22345520c79
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523397394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct
rl_volatile_unlock_smoke.523397394
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.2758525703
Short name T171
Test name
Test status
Simulation time 11197588 ps
CPU time 0.86 seconds
Started Jun 26 06:54:53 PM PDT 24
Finished Jun 26 06:54:56 PM PDT 24
Peak memory 209048 kb
Host smart-659193b6-9dcc-48e1-bab3-22a01193db86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758525703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2758525703
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3668241512
Short name T51
Test name
Test status
Simulation time 1804746009 ps
CPU time 10.67 seconds
Started Jun 26 06:54:54 PM PDT 24
Finished Jun 26 06:55:07 PM PDT 24
Peak memory 218384 kb
Host smart-7d634258-840d-4ce1-9165-433bfb491445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668241512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3668241512
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.3999219953
Short name T405
Test name
Test status
Simulation time 402759383 ps
CPU time 5.56 seconds
Started Jun 26 06:54:56 PM PDT 24
Finished Jun 26 06:55:03 PM PDT 24
Peak memory 217336 kb
Host smart-b5faac84-8a47-457a-b1af-d8908c804065
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999219953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.3999219953
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.467543969
Short name T744
Test name
Test status
Simulation time 17332969 ps
CPU time 1.6 seconds
Started Jun 26 06:54:55 PM PDT 24
Finished Jun 26 06:54:59 PM PDT 24
Peak memory 218408 kb
Host smart-47b1f4c3-b547-4d26-bda4-404fc1125c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467543969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.467543969
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.1761473228
Short name T38
Test name
Test status
Simulation time 175015812 ps
CPU time 9.06 seconds
Started Jun 26 06:54:55 PM PDT 24
Finished Jun 26 06:55:06 PM PDT 24
Peak memory 226236 kb
Host smart-8c1024c1-2aa3-44a6-98e5-ca9e05bbe29d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761473228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1761473228
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1946602404
Short name T387
Test name
Test status
Simulation time 195717199 ps
CPU time 8.81 seconds
Started Jun 26 06:54:54 PM PDT 24
Finished Jun 26 06:55:04 PM PDT 24
Peak memory 218480 kb
Host smart-458792fc-de09-4f9e-8535-15222ae65827
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946602404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.1946602404
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.199856183
Short name T582
Test name
Test status
Simulation time 372840494 ps
CPU time 9.43 seconds
Started Jun 26 06:54:54 PM PDT 24
Finished Jun 26 06:55:05 PM PDT 24
Peak memory 218452 kb
Host smart-f3ee645e-fbaa-475e-a424-798a4de4c6fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199856183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.199856183
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.1777203053
Short name T406
Test name
Test status
Simulation time 163095754 ps
CPU time 7.68 seconds
Started Jun 26 06:54:53 PM PDT 24
Finished Jun 26 06:55:02 PM PDT 24
Peak memory 218552 kb
Host smart-9952c916-7d45-43cd-8101-57ad40936915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777203053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1777203053
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.3358388822
Short name T245
Test name
Test status
Simulation time 69803929 ps
CPU time 2.01 seconds
Started Jun 26 06:54:55 PM PDT 24
Finished Jun 26 06:55:00 PM PDT 24
Peak memory 223764 kb
Host smart-4468fbb5-7763-49c4-b541-7a5097047448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358388822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.3358388822
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.1788287983
Short name T228
Test name
Test status
Simulation time 334811314 ps
CPU time 29.12 seconds
Started Jun 26 06:54:55 PM PDT 24
Finished Jun 26 06:55:26 PM PDT 24
Peak memory 251116 kb
Host smart-9e96d657-d372-411d-aa60-53994fea235b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788287983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1788287983
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.96657228
Short name T328
Test name
Test status
Simulation time 64472818 ps
CPU time 8.4 seconds
Started Jun 26 06:54:55 PM PDT 24
Finished Jun 26 06:55:06 PM PDT 24
Peak memory 251168 kb
Host smart-877145c5-a284-446c-b8f6-ff35dd304601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96657228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.96657228
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.2286310648
Short name T370
Test name
Test status
Simulation time 17191857729 ps
CPU time 114.56 seconds
Started Jun 26 06:54:56 PM PDT 24
Finished Jun 26 06:56:53 PM PDT 24
Peak memory 284000 kb
Host smart-2e9a8ec0-d70f-4f3e-8414-4819cd477242
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286310648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.2286310648
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2097561115
Short name T430
Test name
Test status
Simulation time 50115163 ps
CPU time 0.96 seconds
Started Jun 26 06:54:56 PM PDT 24
Finished Jun 26 06:54:59 PM PDT 24
Peak memory 212040 kb
Host smart-188d3e23-8767-4bd5-94a0-39a9f832c3f6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097561115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.2097561115
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.1814516895
Short name T799
Test name
Test status
Simulation time 44510878 ps
CPU time 1.31 seconds
Started Jun 26 06:54:56 PM PDT 24
Finished Jun 26 06:54:59 PM PDT 24
Peak memory 209236 kb
Host smart-c75cefef-2871-496e-abf5-e1edbe635583
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814516895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1814516895
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1399128272
Short name T46
Test name
Test status
Simulation time 460876147 ps
CPU time 11.11 seconds
Started Jun 26 06:54:57 PM PDT 24
Finished Jun 26 06:55:10 PM PDT 24
Peak memory 218448 kb
Host smart-99744452-c13a-4953-9f0c-1700ef472212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399128272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1399128272
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.4205494369
Short name T615
Test name
Test status
Simulation time 548955958 ps
CPU time 8.16 seconds
Started Jun 26 06:54:54 PM PDT 24
Finished Jun 26 06:55:04 PM PDT 24
Peak memory 217768 kb
Host smart-e3a77331-5205-4a57-b4c8-6c420906f8ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205494369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.4205494369
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1557395771
Short name T745
Test name
Test status
Simulation time 138929887 ps
CPU time 3.07 seconds
Started Jun 26 06:54:54 PM PDT 24
Finished Jun 26 06:54:59 PM PDT 24
Peak memory 218388 kb
Host smart-e1556f94-cc71-4803-9ad6-7a014f992ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557395771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1557395771
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.3403020827
Short name T829
Test name
Test status
Simulation time 266777352 ps
CPU time 9.7 seconds
Started Jun 26 06:54:54 PM PDT 24
Finished Jun 26 06:55:06 PM PDT 24
Peak memory 226324 kb
Host smart-b6fc2764-22b5-4fc5-af41-105da3f3558b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403020827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.3403020827
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.4271420703
Short name T725
Test name
Test status
Simulation time 3647673655 ps
CPU time 13.33 seconds
Started Jun 26 06:54:56 PM PDT 24
Finished Jun 26 06:55:12 PM PDT 24
Peak memory 218504 kb
Host smart-fd2e8762-fc4d-462b-8e73-c53130932476
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271420703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.4271420703
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2845756193
Short name T106
Test name
Test status
Simulation time 2305082830 ps
CPU time 8.73 seconds
Started Jun 26 06:54:56 PM PDT 24
Finished Jun 26 06:55:07 PM PDT 24
Peak memory 218508 kb
Host smart-696fae84-c92c-4a02-8b07-86fd6dde5f8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845756193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
2845756193
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.936500505
Short name T215
Test name
Test status
Simulation time 421552969 ps
CPU time 13.81 seconds
Started Jun 26 06:54:54 PM PDT 24
Finished Jun 26 06:55:11 PM PDT 24
Peak memory 218508 kb
Host smart-76756a1d-0db9-4ee1-aab1-692658539bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936500505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.936500505
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.3078027794
Short name T19
Test name
Test status
Simulation time 50189490 ps
CPU time 2.23 seconds
Started Jun 26 06:54:53 PM PDT 24
Finished Jun 26 06:54:57 PM PDT 24
Peak memory 214548 kb
Host smart-d5e84ad0-f6de-4a15-b917-b223f22d7538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078027794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3078027794
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.4202573232
Short name T391
Test name
Test status
Simulation time 202243225 ps
CPU time 27.95 seconds
Started Jun 26 06:54:56 PM PDT 24
Finished Jun 26 06:55:26 PM PDT 24
Peak memory 251136 kb
Host smart-78f7b827-3c3d-4941-8ead-95ad2d7a6207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202573232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.4202573232
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.2810083914
Short name T2
Test name
Test status
Simulation time 289075178 ps
CPU time 3.27 seconds
Started Jun 26 06:54:57 PM PDT 24
Finished Jun 26 06:55:02 PM PDT 24
Peak memory 222552 kb
Host smart-0452914c-c9bc-461f-bb2a-b30407f6b0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810083914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.2810083914
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3865610680
Short name T101
Test name
Test status
Simulation time 2056042325 ps
CPU time 77.89 seconds
Started Jun 26 06:54:54 PM PDT 24
Finished Jun 26 06:56:15 PM PDT 24
Peak memory 278824 kb
Host smart-e00e84d6-616a-4e31-a299-97bf39a1af75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865610680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3865610680
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3814578058
Short name T549
Test name
Test status
Simulation time 23824661 ps
CPU time 1.03 seconds
Started Jun 26 06:54:54 PM PDT 24
Finished Jun 26 06:54:58 PM PDT 24
Peak memory 212392 kb
Host smart-8513eef3-f534-4680-b38c-ef6beca59489
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814578058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3814578058
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.1266247081
Short name T596
Test name
Test status
Simulation time 21534488 ps
CPU time 1.17 seconds
Started Jun 26 06:55:05 PM PDT 24
Finished Jun 26 06:55:08 PM PDT 24
Peak memory 209232 kb
Host smart-79c0513c-5bdc-498f-9995-8f7c33f5fe14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266247081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.1266247081
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.2534092482
Short name T700
Test name
Test status
Simulation time 343604786 ps
CPU time 3.04 seconds
Started Jun 26 06:55:07 PM PDT 24
Finished Jun 26 06:55:12 PM PDT 24
Peak memory 217348 kb
Host smart-9c38b7ca-2043-4845-92e1-143c63236861
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534092482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.2534092482
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.4120899073
Short name T812
Test name
Test status
Simulation time 150301028 ps
CPU time 3.25 seconds
Started Jun 26 06:55:05 PM PDT 24
Finished Jun 26 06:55:10 PM PDT 24
Peak memory 222820 kb
Host smart-a7495572-fd29-4078-82d7-e0dc3c1669ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120899073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.4120899073
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.349107791
Short name T105
Test name
Test status
Simulation time 1215541983 ps
CPU time 12.12 seconds
Started Jun 26 06:55:08 PM PDT 24
Finished Jun 26 06:55:22 PM PDT 24
Peak memory 219116 kb
Host smart-b9059107-a0b5-46db-8abf-c81570b1aee1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349107791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.349107791
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2656705995
Short name T186
Test name
Test status
Simulation time 1017111587 ps
CPU time 20.16 seconds
Started Jun 26 06:55:07 PM PDT 24
Finished Jun 26 06:55:29 PM PDT 24
Peak memory 218420 kb
Host smart-0b4f3cb9-1213-4acb-8f1d-8e8fa2c5b576
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656705995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2656705995
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1308046647
Short name T349
Test name
Test status
Simulation time 508196252 ps
CPU time 10.59 seconds
Started Jun 26 06:55:10 PM PDT 24
Finished Jun 26 06:55:21 PM PDT 24
Peak memory 226256 kb
Host smart-c6b1f8b6-f50e-48c3-b1d0-be623258f275
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308046647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1308046647
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1494055270
Short name T679
Test name
Test status
Simulation time 1122109834 ps
CPU time 18.68 seconds
Started Jun 26 06:55:05 PM PDT 24
Finished Jun 26 06:55:25 PM PDT 24
Peak memory 218508 kb
Host smart-63cf872e-77e1-4bf7-be68-3141b580225b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494055270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1494055270
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3904652313
Short name T717
Test name
Test status
Simulation time 44410024 ps
CPU time 3.56 seconds
Started Jun 26 06:55:08 PM PDT 24
Finished Jun 26 06:55:13 PM PDT 24
Peak memory 217928 kb
Host smart-43ca82d1-6718-46c8-a850-3cc82199c181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904652313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3904652313
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.2120024671
Short name T767
Test name
Test status
Simulation time 361037868 ps
CPU time 37.97 seconds
Started Jun 26 06:55:05 PM PDT 24
Finished Jun 26 06:55:45 PM PDT 24
Peak memory 251164 kb
Host smart-8e89a757-a658-4059-a06d-58fa23471567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120024671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2120024671
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3166377051
Short name T569
Test name
Test status
Simulation time 106470690 ps
CPU time 6.54 seconds
Started Jun 26 06:55:06 PM PDT 24
Finished Jun 26 06:55:14 PM PDT 24
Peak memory 246768 kb
Host smart-08d33930-c269-441b-8821-720b1123f5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166377051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3166377051
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.3522065315
Short name T358
Test name
Test status
Simulation time 43689197308 ps
CPU time 370.52 seconds
Started Jun 26 06:55:04 PM PDT 24
Finished Jun 26 07:01:15 PM PDT 24
Peak memory 283832 kb
Host smart-1646ea53-4ba5-4ef7-b408-330858ed73ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522065315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.3522065315
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2899659329
Short name T655
Test name
Test status
Simulation time 13891835 ps
CPU time 0.81 seconds
Started Jun 26 06:55:09 PM PDT 24
Finished Jun 26 06:55:11 PM PDT 24
Peak memory 208344 kb
Host smart-863caf23-7562-46d5-8871-1924b12c299f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899659329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2899659329
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1954500873
Short name T601
Test name
Test status
Simulation time 81288104 ps
CPU time 0.86 seconds
Started Jun 26 06:55:08 PM PDT 24
Finished Jun 26 06:55:11 PM PDT 24
Peak memory 209256 kb
Host smart-0c79727d-d391-4c80-9aa9-46418a12a0da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954500873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1954500873
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.1782181523
Short name T671
Test name
Test status
Simulation time 2270876427 ps
CPU time 14.37 seconds
Started Jun 26 06:55:07 PM PDT 24
Finished Jun 26 06:55:23 PM PDT 24
Peak memory 218424 kb
Host smart-04a7e207-4a13-4051-b30b-4a7de5cb3606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782181523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1782181523
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.794293473
Short name T416
Test name
Test status
Simulation time 2466116894 ps
CPU time 6.15 seconds
Started Jun 26 06:55:08 PM PDT 24
Finished Jun 26 06:55:16 PM PDT 24
Peak memory 217852 kb
Host smart-a42c5c3c-6ea6-465f-8a7e-c9852a2254e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794293473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.794293473
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.524762006
Short name T395
Test name
Test status
Simulation time 162005973 ps
CPU time 2.71 seconds
Started Jun 26 06:55:08 PM PDT 24
Finished Jun 26 06:55:13 PM PDT 24
Peak memory 218360 kb
Host smart-3a96509a-c921-45a4-8cb5-631c29111147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524762006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.524762006
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.994656933
Short name T236
Test name
Test status
Simulation time 2233784527 ps
CPU time 16.83 seconds
Started Jun 26 06:55:06 PM PDT 24
Finished Jun 26 06:55:25 PM PDT 24
Peak memory 226324 kb
Host smart-d8753603-0d57-4eb5-857f-1edce81ad667
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994656933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.994656933
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2521244939
Short name T612
Test name
Test status
Simulation time 776192473 ps
CPU time 9.27 seconds
Started Jun 26 06:55:04 PM PDT 24
Finished Jun 26 06:55:14 PM PDT 24
Peak memory 218408 kb
Host smart-b9858ab5-5d05-4748-ac41-5c0d1a905a11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521244939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.2521244939
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3276127912
Short name T484
Test name
Test status
Simulation time 395821355 ps
CPU time 8.87 seconds
Started Jun 26 06:55:08 PM PDT 24
Finished Jun 26 06:55:19 PM PDT 24
Peak memory 218464 kb
Host smart-519c3fe6-5ddc-4729-9d0e-ace41ac969ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276127912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3276127912
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3018482609
Short name T315
Test name
Test status
Simulation time 754766386 ps
CPU time 14.36 seconds
Started Jun 26 06:55:05 PM PDT 24
Finished Jun 26 06:55:20 PM PDT 24
Peak memory 218516 kb
Host smart-6dbe6170-5632-411c-b871-b9d1f282cd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018482609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3018482609
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.2621548076
Short name T456
Test name
Test status
Simulation time 159457057 ps
CPU time 2.72 seconds
Started Jun 26 06:55:06 PM PDT 24
Finished Jun 26 06:55:11 PM PDT 24
Peak memory 217812 kb
Host smart-2d43c12d-a8fa-4416-ac6a-dc39cef507ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621548076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.2621548076
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.2357966381
Short name T404
Test name
Test status
Simulation time 1433790420 ps
CPU time 35.06 seconds
Started Jun 26 06:55:06 PM PDT 24
Finished Jun 26 06:55:43 PM PDT 24
Peak memory 251160 kb
Host smart-29032746-9951-4f93-9fef-c00fed92060b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357966381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.2357966381
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.936334096
Short name T741
Test name
Test status
Simulation time 215307683 ps
CPU time 6.82 seconds
Started Jun 26 06:55:07 PM PDT 24
Finished Jun 26 06:55:16 PM PDT 24
Peak memory 242968 kb
Host smart-af0eb498-eeb7-4c76-8cdc-8e539fefd77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936334096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.936334096
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.3308529245
Short name T90
Test name
Test status
Simulation time 10171446439 ps
CPU time 94.39 seconds
Started Jun 26 06:55:06 PM PDT 24
Finished Jun 26 06:56:43 PM PDT 24
Peak memory 281196 kb
Host smart-57114288-5fcf-440e-8147-5fb4dfd10fd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308529245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.3308529245
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.937872128
Short name T462
Test name
Test status
Simulation time 13680451 ps
CPU time 1.04 seconds
Started Jun 26 06:55:05 PM PDT 24
Finished Jun 26 06:55:08 PM PDT 24
Peak memory 212092 kb
Host smart-8f3914e2-3c7f-4e45-8855-fe45dc22f399
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937872128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ct
rl_volatile_unlock_smoke.937872128
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.3943058725
Short name T698
Test name
Test status
Simulation time 66156011 ps
CPU time 0.99 seconds
Started Jun 26 06:55:24 PM PDT 24
Finished Jun 26 06:55:27 PM PDT 24
Peak memory 209196 kb
Host smart-85bfea79-900b-4a58-bf2d-d515eb129170
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943058725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3943058725
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.67308881
Short name T681
Test name
Test status
Simulation time 329912144 ps
CPU time 11.97 seconds
Started Jun 26 06:55:08 PM PDT 24
Finished Jun 26 06:55:22 PM PDT 24
Peak memory 218420 kb
Host smart-a7ab9bf5-ba55-46b5-bb39-7851e7fa7740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67308881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.67308881
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1058173868
Short name T697
Test name
Test status
Simulation time 721385606 ps
CPU time 4.34 seconds
Started Jun 26 06:55:24 PM PDT 24
Finished Jun 26 06:55:30 PM PDT 24
Peak memory 217624 kb
Host smart-7f33c496-c107-44d7-a15d-37bb1190c76e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058173868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1058173868
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.1586774588
Short name T111
Test name
Test status
Simulation time 83077101 ps
CPU time 3.05 seconds
Started Jun 26 06:55:05 PM PDT 24
Finished Jun 26 06:55:09 PM PDT 24
Peak memory 218528 kb
Host smart-ad4c5e3f-30b1-4410-9972-9849ae3043c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586774588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.1586774588
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.3719947429
Short name T178
Test name
Test status
Simulation time 458170107 ps
CPU time 11.71 seconds
Started Jun 26 06:55:22 PM PDT 24
Finished Jun 26 06:55:35 PM PDT 24
Peak memory 218412 kb
Host smart-861c939a-fdad-4833-9a61-4b5208cf3fed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719947429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3719947429
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1506477808
Short name T275
Test name
Test status
Simulation time 611780454 ps
CPU time 13.8 seconds
Started Jun 26 06:55:22 PM PDT 24
Finished Jun 26 06:55:37 PM PDT 24
Peak memory 218512 kb
Host smart-15428542-58fd-43d8-ad67-cc639e159d6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506477808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.1506477808
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2201427972
Short name T797
Test name
Test status
Simulation time 846765072 ps
CPU time 12.69 seconds
Started Jun 26 06:55:23 PM PDT 24
Finished Jun 26 06:55:37 PM PDT 24
Peak memory 218444 kb
Host smart-4ec6468f-455a-4dcc-8fbb-24718e01a8e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201427972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2201427972
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.3710045185
Short name T704
Test name
Test status
Simulation time 502377114 ps
CPU time 6.31 seconds
Started Jun 26 06:55:24 PM PDT 24
Finished Jun 26 06:55:33 PM PDT 24
Peak memory 218500 kb
Host smart-320dfd88-113d-49a3-870f-25ffdcba9d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710045185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3710045185
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.294668245
Short name T378
Test name
Test status
Simulation time 66009898 ps
CPU time 2.81 seconds
Started Jun 26 06:55:04 PM PDT 24
Finished Jun 26 06:55:08 PM PDT 24
Peak memory 217940 kb
Host smart-87ce5a0e-715c-4aef-8710-815b5009a12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294668245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.294668245
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3628923743
Short name T225
Test name
Test status
Simulation time 245220732 ps
CPU time 25.47 seconds
Started Jun 26 06:55:07 PM PDT 24
Finished Jun 26 06:55:34 PM PDT 24
Peak memory 251088 kb
Host smart-39daf88e-1cd1-4f6f-819f-561594ff9e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628923743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3628923743
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.1872115716
Short name T508
Test name
Test status
Simulation time 55912059 ps
CPU time 6.54 seconds
Started Jun 26 06:55:08 PM PDT 24
Finished Jun 26 06:55:16 PM PDT 24
Peak memory 247012 kb
Host smart-5b76779a-6cdd-41d6-b765-c92b295f42d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872115716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1872115716
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.2179896563
Short name T85
Test name
Test status
Simulation time 13968224335 ps
CPU time 74.07 seconds
Started Jun 26 06:55:25 PM PDT 24
Finished Jun 26 06:56:41 PM PDT 24
Peak memory 251872 kb
Host smart-1b08e4d4-7f34-4d9f-8d3a-cac2ae5bd2d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179896563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.2179896563
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2548316122
Short name T282
Test name
Test status
Simulation time 19014633 ps
CPU time 0.84 seconds
Started Jun 26 06:55:07 PM PDT 24
Finished Jun 26 06:55:09 PM PDT 24
Peak memory 212076 kb
Host smart-8768597b-1fad-433b-84cd-ee3a3b61311b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548316122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2548316122
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.3397347640
Short name T458
Test name
Test status
Simulation time 32008135 ps
CPU time 1.37 seconds
Started Jun 26 06:55:22 PM PDT 24
Finished Jun 26 06:55:25 PM PDT 24
Peak memory 209204 kb
Host smart-f68069be-2a42-44b7-91c8-9b00c6cd1914
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397347640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.3397347640
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.1891132488
Short name T14
Test name
Test status
Simulation time 1358689802 ps
CPU time 15.33 seconds
Started Jun 26 06:55:27 PM PDT 24
Finished Jun 26 06:55:43 PM PDT 24
Peak memory 218384 kb
Host smart-084a937a-fb8c-472d-a490-ea154275f304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891132488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.1891132488
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1453827477
Short name T31
Test name
Test status
Simulation time 450041920 ps
CPU time 3.6 seconds
Started Jun 26 06:55:24 PM PDT 24
Finished Jun 26 06:55:29 PM PDT 24
Peak memory 217548 kb
Host smart-b7ec7e67-2b3b-4806-8d3f-778e4b62fc75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453827477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1453827477
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2652260258
Short name T621
Test name
Test status
Simulation time 72279420 ps
CPU time 3.75 seconds
Started Jun 26 06:55:23 PM PDT 24
Finished Jun 26 06:55:28 PM PDT 24
Peak memory 218368 kb
Host smart-bffd488a-a97f-4cb6-9bce-f481c30136d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652260258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2652260258
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.4213916339
Short name T867
Test name
Test status
Simulation time 319288111 ps
CPU time 16.57 seconds
Started Jun 26 06:55:25 PM PDT 24
Finished Jun 26 06:55:44 PM PDT 24
Peak memory 226224 kb
Host smart-cbb0ebc4-28ac-45a5-a676-5003e75726a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213916339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.4213916339
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.358944501
Short name T305
Test name
Test status
Simulation time 3162620311 ps
CPU time 13.3 seconds
Started Jun 26 06:55:25 PM PDT 24
Finished Jun 26 06:55:41 PM PDT 24
Peak memory 219144 kb
Host smart-98e0562d-715b-40b7-8a25-b1e9092eafc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358944501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_di
gest.358944501
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1738050694
Short name T248
Test name
Test status
Simulation time 570491996 ps
CPU time 11.38 seconds
Started Jun 26 06:55:23 PM PDT 24
Finished Jun 26 06:55:36 PM PDT 24
Peak memory 225540 kb
Host smart-f18cb058-9ea6-4399-9c77-a8511a87c8ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738050694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
1738050694
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.1407344959
Short name T773
Test name
Test status
Simulation time 651552228 ps
CPU time 11.59 seconds
Started Jun 26 06:55:23 PM PDT 24
Finished Jun 26 06:55:37 PM PDT 24
Peak memory 218480 kb
Host smart-04297c4e-78f2-4fc4-bcc4-7bd35664da8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407344959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1407344959
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.3382094022
Short name T70
Test name
Test status
Simulation time 22032407 ps
CPU time 0.98 seconds
Started Jun 26 06:55:25 PM PDT 24
Finished Jun 26 06:55:28 PM PDT 24
Peak memory 212232 kb
Host smart-aa951f3c-149d-40bd-8c88-072b4244d71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382094022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.3382094022
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.1482916352
Short name T560
Test name
Test status
Simulation time 660408962 ps
CPU time 30.22 seconds
Started Jun 26 06:55:24 PM PDT 24
Finished Jun 26 06:55:56 PM PDT 24
Peak memory 251032 kb
Host smart-275b4a86-d90f-4321-91f8-1821518a87f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482916352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.1482916352
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2484340463
Short name T639
Test name
Test status
Simulation time 135136157 ps
CPU time 6.29 seconds
Started Jun 26 06:55:23 PM PDT 24
Finished Jun 26 06:55:30 PM PDT 24
Peak memory 250548 kb
Host smart-468c68fd-3f14-493a-b018-2dfa4823ead9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484340463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2484340463
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3880490686
Short name T731
Test name
Test status
Simulation time 189848857492 ps
CPU time 285.7 seconds
Started Jun 26 06:55:22 PM PDT 24
Finished Jun 26 07:00:09 PM PDT 24
Peak memory 268396 kb
Host smart-8c9fe5d2-3b9d-4d1f-ad0f-0aaa13f9a91f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880490686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3880490686
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.2723049915
Short name T98
Test name
Test status
Simulation time 19818443615 ps
CPU time 111.03 seconds
Started Jun 26 06:55:24 PM PDT 24
Finished Jun 26 06:57:17 PM PDT 24
Peak memory 267796 kb
Host smart-dd83bdb9-1767-4ef3-bcf6-a6fa12eaf6b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2723049915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.2723049915
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3514405737
Short name T854
Test name
Test status
Simulation time 42447963 ps
CPU time 0.91 seconds
Started Jun 26 06:55:25 PM PDT 24
Finished Jun 26 06:55:28 PM PDT 24
Peak memory 212160 kb
Host smart-9823ebed-78aa-4478-9999-d4241249b84e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514405737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3514405737
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.2660567942
Short name T766
Test name
Test status
Simulation time 16876356 ps
CPU time 1.12 seconds
Started Jun 26 06:55:25 PM PDT 24
Finished Jun 26 06:55:28 PM PDT 24
Peak memory 209172 kb
Host smart-e1315427-26a0-4aa3-ad5b-ea1b2d10ae0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660567942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2660567942
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3298330149
Short name T541
Test name
Test status
Simulation time 324873035 ps
CPU time 14.24 seconds
Started Jun 26 06:55:22 PM PDT 24
Finished Jun 26 06:55:38 PM PDT 24
Peak memory 218456 kb
Host smart-044349fe-5aa0-48b3-95e4-c1a50f1568d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298330149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3298330149
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2105155440
Short name T778
Test name
Test status
Simulation time 104075151 ps
CPU time 1.94 seconds
Started Jun 26 06:55:24 PM PDT 24
Finished Jun 26 06:55:28 PM PDT 24
Peak memory 217404 kb
Host smart-e49ce5d5-21be-4662-aba1-7a276599ff9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105155440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2105155440
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.600370639
Short name T648
Test name
Test status
Simulation time 266341611 ps
CPU time 2.65 seconds
Started Jun 26 06:55:24 PM PDT 24
Finished Jun 26 06:55:29 PM PDT 24
Peak memory 218408 kb
Host smart-5919e0b1-b5d4-40d6-8476-fe8f9285ea8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600370639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.600370639
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.374246466
Short name T620
Test name
Test status
Simulation time 2823592047 ps
CPU time 17.88 seconds
Started Jun 26 06:55:25 PM PDT 24
Finished Jun 26 06:55:45 PM PDT 24
Peak memory 226324 kb
Host smart-3da7f46f-5a0b-4b6a-bd13-0445a2d4e5a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374246466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.374246466
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1125799068
Short name T860
Test name
Test status
Simulation time 4356949002 ps
CPU time 10.93 seconds
Started Jun 26 06:55:25 PM PDT 24
Finished Jun 26 06:55:38 PM PDT 24
Peak memory 218452 kb
Host smart-e787cf0f-b380-4497-81ce-6fb978dcfb8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125799068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1125799068
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1733057847
Short name T591
Test name
Test status
Simulation time 1079196897 ps
CPU time 10.47 seconds
Started Jun 26 06:55:24 PM PDT 24
Finished Jun 26 06:55:37 PM PDT 24
Peak memory 218428 kb
Host smart-86e17198-65c1-4f00-9b12-22d0a1ddb5f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733057847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
1733057847
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.336187408
Short name T772
Test name
Test status
Simulation time 243053913 ps
CPU time 9.41 seconds
Started Jun 26 06:55:25 PM PDT 24
Finished Jun 26 06:55:37 PM PDT 24
Peak memory 218488 kb
Host smart-b1521a22-47c5-4ee6-a492-26f06c6a4bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336187408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.336187408
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.252863389
Short name T77
Test name
Test status
Simulation time 95201974 ps
CPU time 2.52 seconds
Started Jun 26 06:55:23 PM PDT 24
Finished Jun 26 06:55:27 PM PDT 24
Peak memory 214440 kb
Host smart-bc7f473a-0f54-4367-9ef5-f9f03ef553e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252863389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.252863389
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.4099471794
Short name T65
Test name
Test status
Simulation time 2451375640 ps
CPU time 23.76 seconds
Started Jun 26 06:55:24 PM PDT 24
Finished Jun 26 06:55:49 PM PDT 24
Peak memory 251200 kb
Host smart-e1ab613d-343c-4959-bfe8-e3fb71d24eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099471794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.4099471794
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2387804283
Short name T820
Test name
Test status
Simulation time 567324248 ps
CPU time 6.11 seconds
Started Jun 26 06:55:23 PM PDT 24
Finished Jun 26 06:55:32 PM PDT 24
Peak memory 247196 kb
Host smart-a10d6f58-3c39-49d0-85b4-b9f84e00df21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387804283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2387804283
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1471493325
Short name T75
Test name
Test status
Simulation time 4516152919 ps
CPU time 96.07 seconds
Started Jun 26 06:55:24 PM PDT 24
Finished Jun 26 06:57:02 PM PDT 24
Peak memory 251164 kb
Host smart-1757daee-0c14-4456-b5bd-acd09b88b2f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471493325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1471493325
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.2746083050
Short name T152
Test name
Test status
Simulation time 36535592666 ps
CPU time 1420.7 seconds
Started Jun 26 06:55:24 PM PDT 24
Finished Jun 26 07:19:07 PM PDT 24
Peak memory 497044 kb
Host smart-dcb57966-f51b-4270-8cc1-bc0138a3c364
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2746083050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.2746083050
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1690946473
Short name T294
Test name
Test status
Simulation time 20976277 ps
CPU time 0.88 seconds
Started Jun 26 06:55:24 PM PDT 24
Finished Jun 26 06:55:28 PM PDT 24
Peak memory 212064 kb
Host smart-6e727795-323a-4f4c-928f-8a0f07ccdfb8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690946473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.1690946473
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1481827695
Short name T302
Test name
Test status
Simulation time 15350514 ps
CPU time 1.05 seconds
Started Jun 26 06:52:15 PM PDT 24
Finished Jun 26 06:52:17 PM PDT 24
Peak memory 209180 kb
Host smart-602c29f7-2e86-46f3-9a6b-d96a167748be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481827695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1481827695
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.4267011409
Short name T806
Test name
Test status
Simulation time 13946090 ps
CPU time 0.82 seconds
Started Jun 26 06:52:18 PM PDT 24
Finished Jun 26 06:52:20 PM PDT 24
Peak memory 208980 kb
Host smart-258870b0-5eb8-478b-8292-b888682866d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267011409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.4267011409
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.3719198505
Short name T408
Test name
Test status
Simulation time 1966625407 ps
CPU time 15.26 seconds
Started Jun 26 06:52:07 PM PDT 24
Finished Jun 26 06:52:24 PM PDT 24
Peak memory 218376 kb
Host smart-87887dcb-64f3-4605-bad7-711678a9cc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719198505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3719198505
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.2849863339
Short name T557
Test name
Test status
Simulation time 263608170 ps
CPU time 6.33 seconds
Started Jun 26 06:52:16 PM PDT 24
Finished Jun 26 06:52:24 PM PDT 24
Peak memory 217316 kb
Host smart-0c1c81c1-8387-4d4e-acc8-ca350ad94a8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849863339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.2849863339
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.66347562
Short name T365
Test name
Test status
Simulation time 8521648222 ps
CPU time 63.99 seconds
Started Jun 26 06:52:15 PM PDT 24
Finished Jun 26 06:53:21 PM PDT 24
Peak memory 226324 kb
Host smart-660cb776-60dc-408a-ad4d-e012056951a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66347562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_erro
rs.66347562
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.2927330208
Short name T26
Test name
Test status
Simulation time 636482284 ps
CPU time 14.55 seconds
Started Jun 26 06:52:17 PM PDT 24
Finished Jun 26 06:52:33 PM PDT 24
Peak memory 217992 kb
Host smart-0df8b903-ee20-488b-85fd-ef057a44de9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927330208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.2
927330208
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.290370028
Short name T353
Test name
Test status
Simulation time 375375598 ps
CPU time 6.52 seconds
Started Jun 26 06:52:16 PM PDT 24
Finished Jun 26 06:52:24 PM PDT 24
Peak memory 218408 kb
Host smart-52b5eed9-3783-4857-bb89-987cd28e8ef3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290370028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
prog_failure.290370028
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.795828102
Short name T792
Test name
Test status
Simulation time 1058501804 ps
CPU time 13.76 seconds
Started Jun 26 06:52:15 PM PDT 24
Finished Jun 26 06:52:29 PM PDT 24
Peak memory 217944 kb
Host smart-911bfaf2-d6c7-4ac0-ba67-22c6abb822ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795828102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_regwen_during_op.795828102
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.4120809270
Short name T556
Test name
Test status
Simulation time 547088521 ps
CPU time 3.72 seconds
Started Jun 26 06:52:15 PM PDT 24
Finished Jun 26 06:52:20 PM PDT 24
Peak memory 217820 kb
Host smart-6ec95a73-331e-4580-a487-fd05b078ce7f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120809270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
4120809270
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3634038477
Short name T588
Test name
Test status
Simulation time 954922434 ps
CPU time 46.65 seconds
Started Jun 26 06:52:15 PM PDT 24
Finished Jun 26 06:53:03 PM PDT 24
Peak memory 251076 kb
Host smart-ad84f2ad-3b7d-48d9-89d2-a45efa2492a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634038477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.3634038477
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.3637925562
Short name T440
Test name
Test status
Simulation time 1644656709 ps
CPU time 11.25 seconds
Started Jun 26 06:52:16 PM PDT 24
Finished Jun 26 06:52:29 PM PDT 24
Peak memory 250588 kb
Host smart-8f00de0f-d8fe-48a1-99cf-31b39c0d925e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637925562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.3637925562
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.4124061138
Short name T864
Test name
Test status
Simulation time 41056423 ps
CPU time 2.43 seconds
Started Jun 26 06:52:07 PM PDT 24
Finished Jun 26 06:52:11 PM PDT 24
Peak memory 218396 kb
Host smart-3a6e2d6e-8690-4fd3-abc7-0fde5e62cf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124061138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.4124061138
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.2394743277
Short name T776
Test name
Test status
Simulation time 688222613 ps
CPU time 14.34 seconds
Started Jun 26 06:52:15 PM PDT 24
Finished Jun 26 06:52:30 PM PDT 24
Peak memory 218136 kb
Host smart-a39e5a86-d085-4356-901a-040272dd221c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394743277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.2394743277
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.3095297031
Short name T96
Test name
Test status
Simulation time 763973640 ps
CPU time 41.55 seconds
Started Jun 26 06:52:17 PM PDT 24
Finished Jun 26 06:53:00 PM PDT 24
Peak memory 284244 kb
Host smart-dd23ed8c-8542-4ce3-9d6d-fda9e36eeab3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095297031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.3095297031
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.2146354545
Short name T509
Test name
Test status
Simulation time 243143899 ps
CPU time 13.04 seconds
Started Jun 26 06:52:19 PM PDT 24
Finished Jun 26 06:52:33 PM PDT 24
Peak memory 226228 kb
Host smart-92937413-d236-4482-9c62-b698703dd65e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146354545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.2146354545
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3508564431
Short name T109
Test name
Test status
Simulation time 2182875093 ps
CPU time 13.27 seconds
Started Jun 26 06:52:16 PM PDT 24
Finished Jun 26 06:52:31 PM PDT 24
Peak memory 218540 kb
Host smart-9acfd489-23c0-4430-8098-1dfb9d0f84eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508564431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.3508564431
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1983106685
Short name T652
Test name
Test status
Simulation time 1015689888 ps
CPU time 10.85 seconds
Started Jun 26 06:52:17 PM PDT 24
Finished Jun 26 06:52:29 PM PDT 24
Peak memory 218564 kb
Host smart-7fba5110-82bf-4292-a330-9feb55999511
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983106685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
983106685
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.1006460528
Short name T459
Test name
Test status
Simulation time 1683279379 ps
CPU time 12.33 seconds
Started Jun 26 06:52:18 PM PDT 24
Finished Jun 26 06:52:31 PM PDT 24
Peak memory 226220 kb
Host smart-be776ab6-59c0-480c-b223-7f0a956f85c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006460528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1006460528
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.884897755
Short name T84
Test name
Test status
Simulation time 155894242 ps
CPU time 2.5 seconds
Started Jun 26 06:52:04 PM PDT 24
Finished Jun 26 06:52:07 PM PDT 24
Peak memory 214432 kb
Host smart-34143ebc-948f-4adb-8e59-6f657ddf8e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884897755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.884897755
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3944159387
Short name T110
Test name
Test status
Simulation time 1719150594 ps
CPU time 19.63 seconds
Started Jun 26 06:52:08 PM PDT 24
Finished Jun 26 06:52:29 PM PDT 24
Peak memory 251068 kb
Host smart-85ff4b63-97ce-4c05-a50f-a9a63672dbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944159387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3944159387
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.3949433263
Short name T609
Test name
Test status
Simulation time 136453424 ps
CPU time 10.02 seconds
Started Jun 26 06:52:07 PM PDT 24
Finished Jun 26 06:52:18 PM PDT 24
Peak memory 251124 kb
Host smart-38522355-1c34-4cb0-8d72-ab26190da3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949433263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3949433263
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.2885052280
Short name T62
Test name
Test status
Simulation time 50170539093 ps
CPU time 331.32 seconds
Started Jun 26 06:52:15 PM PDT 24
Finished Jun 26 06:57:48 PM PDT 24
Peak memory 223004 kb
Host smart-c2d64d45-9219-44dc-b19c-94e49624b3b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885052280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.2885052280
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.830123260
Short name T273
Test name
Test status
Simulation time 13452504 ps
CPU time 1.06 seconds
Started Jun 26 06:52:05 PM PDT 24
Finished Jun 26 06:52:07 PM PDT 24
Peak memory 211992 kb
Host smart-a605a0a3-fbcc-4807-898d-9b2301ceb717
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830123260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctr
l_volatile_unlock_smoke.830123260
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.2808125719
Short name T398
Test name
Test status
Simulation time 19610255 ps
CPU time 0.95 seconds
Started Jun 26 06:55:40 PM PDT 24
Finished Jun 26 06:55:43 PM PDT 24
Peak memory 209272 kb
Host smart-74e9a9ea-a053-4b86-bdec-cb610766322a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808125719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2808125719
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.241263418
Short name T239
Test name
Test status
Simulation time 418964647 ps
CPU time 11.06 seconds
Started Jun 26 06:55:35 PM PDT 24
Finished Jun 26 06:55:47 PM PDT 24
Peak memory 218652 kb
Host smart-58dfe57e-51a8-4d44-8748-01dd8b3e69d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241263418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.241263418
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.2254219731
Short name T752
Test name
Test status
Simulation time 211120956 ps
CPU time 6.68 seconds
Started Jun 26 06:55:39 PM PDT 24
Finished Jun 26 06:55:48 PM PDT 24
Peak memory 217324 kb
Host smart-5fb73a0f-3f10-4101-b3ff-3c91d66e02b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254219731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.2254219731
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.1777707264
Short name T548
Test name
Test status
Simulation time 153389610 ps
CPU time 3.04 seconds
Started Jun 26 06:55:37 PM PDT 24
Finished Jun 26 06:55:42 PM PDT 24
Peak memory 222824 kb
Host smart-16d00e64-4e6b-48fc-99b9-e7ee6c533487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777707264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.1777707264
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.704815359
Short name T559
Test name
Test status
Simulation time 2330001718 ps
CPU time 17.78 seconds
Started Jun 26 06:55:36 PM PDT 24
Finished Jun 26 06:55:56 PM PDT 24
Peak memory 226296 kb
Host smart-eddaf025-fdcb-4012-9502-dd9ba6d831c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704815359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.704815359
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.2660218122
Short name T763
Test name
Test status
Simulation time 696829307 ps
CPU time 9.78 seconds
Started Jun 26 06:55:37 PM PDT 24
Finished Jun 26 06:55:49 PM PDT 24
Peak memory 218540 kb
Host smart-ca4f7e4c-7e6a-452f-8b29-ef4d9c1b1cd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660218122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.2660218122
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.953414383
Short name T480
Test name
Test status
Simulation time 4721248653 ps
CPU time 9.18 seconds
Started Jun 26 06:55:39 PM PDT 24
Finished Jun 26 06:55:50 PM PDT 24
Peak memory 226288 kb
Host smart-a01e4fe7-2ceb-4d76-ab63-d825c1f0a971
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953414383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.953414383
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1584034216
Short name T663
Test name
Test status
Simulation time 269493354 ps
CPU time 10.62 seconds
Started Jun 26 06:55:42 PM PDT 24
Finished Jun 26 06:55:54 PM PDT 24
Peak memory 218320 kb
Host smart-b980ed9c-83eb-445b-813c-8dcf5aa974b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584034216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1584034216
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2345726127
Short name T550
Test name
Test status
Simulation time 34541338 ps
CPU time 1.58 seconds
Started Jun 26 06:55:24 PM PDT 24
Finished Jun 26 06:55:28 PM PDT 24
Peak memory 217924 kb
Host smart-18d2842c-cf1c-46e2-90d7-bdd6aa296feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345726127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2345726127
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.2207929695
Short name T45
Test name
Test status
Simulation time 693244227 ps
CPU time 15.88 seconds
Started Jun 26 06:55:40 PM PDT 24
Finished Jun 26 06:55:57 PM PDT 24
Peak memory 251112 kb
Host smart-19b75ba5-c92c-41b0-a606-aaec183f01a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207929695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.2207929695
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.1788913339
Short name T685
Test name
Test status
Simulation time 117226352 ps
CPU time 8.82 seconds
Started Jun 26 06:55:39 PM PDT 24
Finished Jun 26 06:55:50 PM PDT 24
Peak memory 251164 kb
Host smart-2b899715-1a21-469f-8558-1902065b63e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788913339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.1788913339
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3622239760
Short name T367
Test name
Test status
Simulation time 23091800958 ps
CPU time 252.79 seconds
Started Jun 26 06:55:39 PM PDT 24
Finished Jun 26 06:59:54 PM PDT 24
Peak memory 283940 kb
Host smart-18cd0352-fccb-4699-85e5-20904f0a27df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622239760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3622239760
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.1399156160
Short name T97
Test name
Test status
Simulation time 12787895190 ps
CPU time 290.22 seconds
Started Jun 26 06:55:36 PM PDT 24
Finished Jun 26 07:00:28 PM PDT 24
Peak memory 260116 kb
Host smart-59247242-7d93-4d96-a964-6cc8edf9350b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1399156160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.1399156160
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.4128151997
Short name T357
Test name
Test status
Simulation time 33741961 ps
CPU time 0.86 seconds
Started Jun 26 06:55:37 PM PDT 24
Finished Jun 26 06:55:39 PM PDT 24
Peak memory 212152 kb
Host smart-0fdbe210-941c-494e-907f-1f156273c8a8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128151997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.4128151997
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3080280765
Short name T231
Test name
Test status
Simulation time 21620857 ps
CPU time 0.95 seconds
Started Jun 26 06:55:36 PM PDT 24
Finished Jun 26 06:55:39 PM PDT 24
Peak memory 209244 kb
Host smart-723b0249-a201-4ceb-bc3f-e500156d29c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080280765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3080280765
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1826025979
Short name T513
Test name
Test status
Simulation time 704264896 ps
CPU time 15.23 seconds
Started Jun 26 06:55:39 PM PDT 24
Finished Jun 26 06:55:56 PM PDT 24
Peak memory 218432 kb
Host smart-6492d23b-fa54-42fc-9d55-92f8b5cc8da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826025979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1826025979
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.2503333390
Short name T865
Test name
Test status
Simulation time 178234258 ps
CPU time 1.84 seconds
Started Jun 26 06:55:38 PM PDT 24
Finished Jun 26 06:55:42 PM PDT 24
Peak memory 217176 kb
Host smart-4ca1c670-89a9-4fe2-b430-cc722c8aba4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503333390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.2503333390
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.1967749287
Short name T300
Test name
Test status
Simulation time 20918308 ps
CPU time 1.76 seconds
Started Jun 26 06:55:42 PM PDT 24
Finished Jun 26 06:55:45 PM PDT 24
Peak memory 218432 kb
Host smart-269bcad7-70b7-449d-bab8-b8d645da1325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967749287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.1967749287
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.3531123352
Short name T750
Test name
Test status
Simulation time 306239713 ps
CPU time 12.93 seconds
Started Jun 26 06:55:39 PM PDT 24
Finished Jun 26 06:55:53 PM PDT 24
Peak memory 226268 kb
Host smart-e988e004-b3a0-4746-92b2-0c90ab1c16e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531123352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.3531123352
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2292572512
Short name T793
Test name
Test status
Simulation time 2121137782 ps
CPU time 10.98 seconds
Started Jun 26 06:55:39 PM PDT 24
Finished Jun 26 06:55:51 PM PDT 24
Peak memory 218440 kb
Host smart-f2508537-74ac-453e-b17b-064381856d94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292572512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.2292572512
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.38197254
Short name T729
Test name
Test status
Simulation time 239364023 ps
CPU time 5.73 seconds
Started Jun 26 06:55:39 PM PDT 24
Finished Jun 26 06:55:47 PM PDT 24
Peak memory 225184 kb
Host smart-a363d071-6ed2-44e9-a2f0-017a7804551b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38197254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.38197254
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.2866005866
Short name T451
Test name
Test status
Simulation time 2118918055 ps
CPU time 7.45 seconds
Started Jun 26 06:55:39 PM PDT 24
Finished Jun 26 06:55:48 PM PDT 24
Peak memory 218644 kb
Host smart-6dd480d1-f70f-4b99-aeb7-e6d596797a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866005866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.2866005866
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.39138351
Short name T43
Test name
Test status
Simulation time 177493710 ps
CPU time 1.86 seconds
Started Jun 26 06:55:42 PM PDT 24
Finished Jun 26 06:55:44 PM PDT 24
Peak memory 217864 kb
Host smart-e66cc4b4-cfe9-4979-8276-e22d6ccb49eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39138351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.39138351
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.3445867901
Short name T495
Test name
Test status
Simulation time 5200129195 ps
CPU time 29.68 seconds
Started Jun 26 06:55:36 PM PDT 24
Finished Jun 26 06:56:08 PM PDT 24
Peak memory 251212 kb
Host smart-eb396515-92a5-4f3d-9862-569dd93aae17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445867901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.3445867901
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1091070451
Short name T723
Test name
Test status
Simulation time 521764813 ps
CPU time 9.5 seconds
Started Jun 26 06:55:35 PM PDT 24
Finished Jun 26 06:55:45 PM PDT 24
Peak memory 251132 kb
Host smart-78bb1dca-0fcf-434d-a8b5-3ca45c491e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091070451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1091070451
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3198479371
Short name T539
Test name
Test status
Simulation time 7521356449 ps
CPU time 171.26 seconds
Started Jun 26 06:55:37 PM PDT 24
Finished Jun 26 06:58:30 PM PDT 24
Peak memory 251200 kb
Host smart-bdfec8ac-9b7a-4ad5-b1a6-641221dce1e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198479371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3198479371
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1764045476
Short name T422
Test name
Test status
Simulation time 14113397 ps
CPU time 0.9 seconds
Started Jun 26 06:55:34 PM PDT 24
Finished Jun 26 06:55:36 PM PDT 24
Peak memory 213100 kb
Host smart-e5f64b5a-eedd-4230-af2d-a517f67a9872
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764045476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1764045476
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3731459324
Short name T258
Test name
Test status
Simulation time 20378529 ps
CPU time 0.99 seconds
Started Jun 26 06:55:38 PM PDT 24
Finished Jun 26 06:55:40 PM PDT 24
Peak memory 209164 kb
Host smart-0e515b90-698a-4f0f-bc4a-df2334d49771
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731459324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3731459324
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2916031759
Short name T520
Test name
Test status
Simulation time 198434914 ps
CPU time 10.28 seconds
Started Jun 26 06:55:40 PM PDT 24
Finished Jun 26 06:55:52 PM PDT 24
Peak memory 218464 kb
Host smart-d5081304-8869-4832-b9d2-21cf5f5d18ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916031759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2916031759
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.3139030796
Short name T826
Test name
Test status
Simulation time 187868077 ps
CPU time 1.29 seconds
Started Jun 26 06:55:40 PM PDT 24
Finished Jun 26 06:55:43 PM PDT 24
Peak memory 217304 kb
Host smart-bf7ebd22-9500-4f59-8219-5b63029adcc7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139030796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.3139030796
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.1833463405
Short name T474
Test name
Test status
Simulation time 147611173 ps
CPU time 3.01 seconds
Started Jun 26 06:55:42 PM PDT 24
Finished Jun 26 06:55:46 PM PDT 24
Peak memory 218344 kb
Host smart-03687592-8933-4193-b4c7-88dcde6af9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833463405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1833463405
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.3496762909
Short name T825
Test name
Test status
Simulation time 464843833 ps
CPU time 19.44 seconds
Started Jun 26 06:55:36 PM PDT 24
Finished Jun 26 06:55:56 PM PDT 24
Peak memory 226232 kb
Host smart-1754f571-e4be-413c-a9e9-6985769374c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496762909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3496762909
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.322106732
Short name T377
Test name
Test status
Simulation time 1635815444 ps
CPU time 9.95 seconds
Started Jun 26 06:55:38 PM PDT 24
Finished Jun 26 06:55:49 PM PDT 24
Peak memory 218440 kb
Host smart-915b31b1-6d8c-40d6-b1b3-0e37a0a6de45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322106732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_di
gest.322106732
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1520537360
Short name T496
Test name
Test status
Simulation time 655720232 ps
CPU time 13.29 seconds
Started Jun 26 06:55:37 PM PDT 24
Finished Jun 26 06:55:52 PM PDT 24
Peak memory 226264 kb
Host smart-b4e079e1-c236-4077-b4de-f68e041f7b5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520537360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1520537360
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.2204711605
Short name T56
Test name
Test status
Simulation time 483949439 ps
CPU time 10.29 seconds
Started Jun 26 06:55:37 PM PDT 24
Finished Jun 26 06:55:49 PM PDT 24
Peak memory 218572 kb
Host smart-a1f9b936-a3a0-400b-bbd0-187a13d053fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204711605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.2204711605
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.3686486130
Short name T83
Test name
Test status
Simulation time 100129535 ps
CPU time 1.41 seconds
Started Jun 26 06:55:38 PM PDT 24
Finished Jun 26 06:55:41 PM PDT 24
Peak memory 213872 kb
Host smart-dbafc993-0021-432d-aea1-21a6e1eb1d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686486130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3686486130
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.134666604
Short name T264
Test name
Test status
Simulation time 301590659 ps
CPU time 29.74 seconds
Started Jun 26 06:55:36 PM PDT 24
Finished Jun 26 06:56:06 PM PDT 24
Peak memory 251200 kb
Host smart-ea3ba57b-9c00-41fc-b406-fd65de938fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134666604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.134666604
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.149570343
Short name T17
Test name
Test status
Simulation time 176644896 ps
CPU time 4.81 seconds
Started Jun 26 06:55:36 PM PDT 24
Finished Jun 26 06:55:42 PM PDT 24
Peak memory 218452 kb
Host smart-4ff38681-99a5-4365-b5f6-ffab4c94d8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149570343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.149570343
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.2911503559
Short name T694
Test name
Test status
Simulation time 1790904409 ps
CPU time 33.41 seconds
Started Jun 26 06:55:42 PM PDT 24
Finished Jun 26 06:56:16 PM PDT 24
Peak memory 226196 kb
Host smart-7ef94fe8-d778-44ef-85fd-6b3fd25b8bbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911503559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.2911503559
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2684998151
Short name T438
Test name
Test status
Simulation time 58374719 ps
CPU time 0.86 seconds
Started Jun 26 06:55:39 PM PDT 24
Finished Jun 26 06:55:41 PM PDT 24
Peak memory 212112 kb
Host smart-4f3a8926-f6f4-4212-ad74-df9832b10503
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684998151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.2684998151
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.52184876
Short name T281
Test name
Test status
Simulation time 43017023 ps
CPU time 0.85 seconds
Started Jun 26 06:55:53 PM PDT 24
Finished Jun 26 06:55:56 PM PDT 24
Peak memory 208972 kb
Host smart-d1cffda4-9f5a-4e8b-810c-e2f8ebd6ce72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52184876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.52184876
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.1541415309
Short name T49
Test name
Test status
Simulation time 1706238253 ps
CPU time 15.33 seconds
Started Jun 26 06:55:50 PM PDT 24
Finished Jun 26 06:56:07 PM PDT 24
Peak memory 218416 kb
Host smart-230f3a7c-aeae-4297-8fd5-7bd149f1733b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541415309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1541415309
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.2767411666
Short name T762
Test name
Test status
Simulation time 1462976540 ps
CPU time 10.16 seconds
Started Jun 26 06:55:49 PM PDT 24
Finished Jun 26 06:56:01 PM PDT 24
Peak memory 217548 kb
Host smart-9eed13e2-6b01-4756-b141-dc281f27b932
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767411666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.2767411666
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.215325613
Short name T295
Test name
Test status
Simulation time 555731669 ps
CPU time 2.96 seconds
Started Jun 26 06:55:55 PM PDT 24
Finished Jun 26 06:56:00 PM PDT 24
Peak memory 222600 kb
Host smart-13758c58-a313-47ce-b4ea-8e2500bd3c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215325613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.215325613
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.2367625231
Short name T566
Test name
Test status
Simulation time 888255823 ps
CPU time 10.27 seconds
Started Jun 26 06:55:54 PM PDT 24
Finished Jun 26 06:56:07 PM PDT 24
Peak memory 226224 kb
Host smart-8addbf19-e29b-46d9-808d-84c2e1898da0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367625231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2367625231
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.194939688
Short name T235
Test name
Test status
Simulation time 300162858 ps
CPU time 9.45 seconds
Started Jun 26 06:55:47 PM PDT 24
Finished Jun 26 06:55:57 PM PDT 24
Peak memory 218456 kb
Host smart-cab298f6-34fa-465b-aafa-530c0f3518ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194939688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_di
gest.194939688
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.166711525
Short name T312
Test name
Test status
Simulation time 412354774 ps
CPU time 8.53 seconds
Started Jun 26 06:55:53 PM PDT 24
Finished Jun 26 06:56:04 PM PDT 24
Peak memory 218456 kb
Host smart-b830a13b-47da-49bd-b79a-90c6b2a7c0c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166711525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.166711525
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.2542571380
Short name T674
Test name
Test status
Simulation time 326177835 ps
CPU time 7.03 seconds
Started Jun 26 06:55:51 PM PDT 24
Finished Jun 26 06:56:01 PM PDT 24
Peak memory 218644 kb
Host smart-7cda4001-b3c3-4c15-80bc-b878a6a51054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542571380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2542571380
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.4113355807
Short name T76
Test name
Test status
Simulation time 465016770 ps
CPU time 7.68 seconds
Started Jun 26 06:55:36 PM PDT 24
Finished Jun 26 06:55:46 PM PDT 24
Peak memory 217940 kb
Host smart-b58f98b8-12ca-4bcd-8953-8f9ef288559c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113355807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.4113355807
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.785216790
Short name T417
Test name
Test status
Simulation time 328233799 ps
CPU time 31.94 seconds
Started Jun 26 06:55:53 PM PDT 24
Finished Jun 26 06:56:27 PM PDT 24
Peak memory 251152 kb
Host smart-c849da9f-5076-4568-b0b9-c3e768bb5459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785216790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.785216790
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3373372948
Short name T669
Test name
Test status
Simulation time 199432687 ps
CPU time 7.9 seconds
Started Jun 26 06:55:50 PM PDT 24
Finished Jun 26 06:56:00 PM PDT 24
Peak memory 251140 kb
Host smart-dda7d094-2569-4a7d-aaeb-d9863d76ab4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373372948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3373372948
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.2056257886
Short name T824
Test name
Test status
Simulation time 26447988268 ps
CPU time 227.7 seconds
Started Jun 26 06:55:51 PM PDT 24
Finished Jun 26 06:59:40 PM PDT 24
Peak memory 281464 kb
Host smart-7cec296f-dc24-44dc-841a-28e1ce79235e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056257886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.2056257886
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1690308142
Short name T263
Test name
Test status
Simulation time 26098662 ps
CPU time 1.03 seconds
Started Jun 26 06:55:50 PM PDT 24
Finished Jun 26 06:55:53 PM PDT 24
Peak memory 212216 kb
Host smart-822cce37-7276-4fd8-b773-dfa591d932ec
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690308142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.1690308142
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.3345296459
Short name T44
Test name
Test status
Simulation time 21969660 ps
CPU time 0.85 seconds
Started Jun 26 06:55:51 PM PDT 24
Finished Jun 26 06:55:55 PM PDT 24
Peak memory 209060 kb
Host smart-3a0b89d9-50f1-418e-b9e7-973a9a5d9a9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345296459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3345296459
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.596424960
Short name T277
Test name
Test status
Simulation time 338527212 ps
CPU time 16.04 seconds
Started Jun 26 06:55:49 PM PDT 24
Finished Jun 26 06:56:06 PM PDT 24
Peak memory 218396 kb
Host smart-f0356778-4921-4a01-84d8-76f62f7559b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596424960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.596424960
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.4095455741
Short name T641
Test name
Test status
Simulation time 350458485 ps
CPU time 2.81 seconds
Started Jun 26 06:55:52 PM PDT 24
Finished Jun 26 06:55:57 PM PDT 24
Peak memory 217392 kb
Host smart-177d00f6-3dc9-4fa2-842d-40938f088222
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095455741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.4095455741
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.3266118546
Short name T1
Test name
Test status
Simulation time 159138797 ps
CPU time 2.79 seconds
Started Jun 26 06:55:53 PM PDT 24
Finished Jun 26 06:55:58 PM PDT 24
Peak memory 218444 kb
Host smart-55c58944-60c5-4f77-9107-048cd664307c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266118546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3266118546
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.2048267944
Short name T583
Test name
Test status
Simulation time 2333651570 ps
CPU time 18.31 seconds
Started Jun 26 06:55:54 PM PDT 24
Finished Jun 26 06:56:14 PM PDT 24
Peak memory 226320 kb
Host smart-791965ad-de9a-4c0d-8c73-3ca69d55e030
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048267944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.2048267944
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3201126626
Short name T299
Test name
Test status
Simulation time 1422853778 ps
CPU time 11.64 seconds
Started Jun 26 06:55:51 PM PDT 24
Finished Jun 26 06:56:06 PM PDT 24
Peak memory 218472 kb
Host smart-c8a6d273-2c69-4b25-8988-c9f72b064d57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201126626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3201126626
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2726335867
Short name T722
Test name
Test status
Simulation time 322860032 ps
CPU time 10.25 seconds
Started Jun 26 06:55:54 PM PDT 24
Finished Jun 26 06:56:06 PM PDT 24
Peak memory 218456 kb
Host smart-fde8b5e3-e139-44d4-9dc6-6b0bfe2d4200
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726335867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2726335867
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.1610130377
Short name T633
Test name
Test status
Simulation time 900921020 ps
CPU time 14.64 seconds
Started Jun 26 06:55:49 PM PDT 24
Finished Jun 26 06:56:05 PM PDT 24
Peak memory 218488 kb
Host smart-105bd9e4-36ea-4c38-bdcb-fcf290cd08a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610130377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.1610130377
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2641988724
Short name T344
Test name
Test status
Simulation time 266670531 ps
CPU time 10.85 seconds
Started Jun 26 06:55:50 PM PDT 24
Finished Jun 26 06:56:03 PM PDT 24
Peak memory 218052 kb
Host smart-007c7e81-a63e-4b1c-b629-ef5ccfdaa11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641988724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2641988724
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1397818904
Short name T386
Test name
Test status
Simulation time 711301623 ps
CPU time 20.29 seconds
Started Jun 26 06:55:51 PM PDT 24
Finished Jun 26 06:56:14 PM PDT 24
Peak memory 251140 kb
Host smart-4498c8a1-f49e-40f3-97e9-fc84ac19dc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397818904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1397818904
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.1406211979
Short name T321
Test name
Test status
Simulation time 99045009 ps
CPU time 3.57 seconds
Started Jun 26 06:55:51 PM PDT 24
Finished Jun 26 06:55:58 PM PDT 24
Peak memory 223044 kb
Host smart-1b75765b-3314-4cc6-a0d8-cd12c25a5316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406211979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1406211979
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3677033945
Short name T165
Test name
Test status
Simulation time 11490712090 ps
CPU time 120.64 seconds
Started Jun 26 06:55:53 PM PDT 24
Finished Jun 26 06:57:56 PM PDT 24
Peak memory 267552 kb
Host smart-cf02f880-cace-491f-87e5-3dbe107ae8c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677033945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3677033945
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3964325508
Short name T489
Test name
Test status
Simulation time 70085013 ps
CPU time 0.89 seconds
Started Jun 26 06:55:51 PM PDT 24
Finished Jun 26 06:55:54 PM PDT 24
Peak memory 212092 kb
Host smart-836c4b7e-9054-47e4-bcb4-28fe94d7414f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964325508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.3964325508
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.227143843
Short name T380
Test name
Test status
Simulation time 37483704 ps
CPU time 0.95 seconds
Started Jun 26 06:55:51 PM PDT 24
Finished Jun 26 06:55:55 PM PDT 24
Peak memory 209156 kb
Host smart-79fe7700-e28a-408b-a6a9-e90af319e3df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227143843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.227143843
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.3423110436
Short name T784
Test name
Test status
Simulation time 950104774 ps
CPU time 9.94 seconds
Started Jun 26 06:55:51 PM PDT 24
Finished Jun 26 06:56:03 PM PDT 24
Peak memory 218444 kb
Host smart-7b7c5099-eddc-4f5b-916e-9a8986ce09ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423110436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.3423110436
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.1461251571
Short name T6
Test name
Test status
Simulation time 462050483 ps
CPU time 5.26 seconds
Started Jun 26 06:55:51 PM PDT 24
Finished Jun 26 06:55:59 PM PDT 24
Peak memory 217308 kb
Host smart-9d75f508-9b06-4cf1-880c-ab4e3faa9338
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461251571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.1461251571
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.489836671
Short name T755
Test name
Test status
Simulation time 70611674 ps
CPU time 3.97 seconds
Started Jun 26 06:55:51 PM PDT 24
Finished Jun 26 06:55:58 PM PDT 24
Peak memory 218436 kb
Host smart-7f7e6075-bd81-4adb-8fbe-92df6d3ef5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489836671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.489836671
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.3696672347
Short name T562
Test name
Test status
Simulation time 328845099 ps
CPU time 11.58 seconds
Started Jun 26 06:55:50 PM PDT 24
Finished Jun 26 06:56:04 PM PDT 24
Peak memory 226264 kb
Host smart-b1f7801b-3e45-4d63-89ff-8ed06504f5ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696672347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.3696672347
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.1566120976
Short name T268
Test name
Test status
Simulation time 1279440772 ps
CPU time 10.18 seconds
Started Jun 26 06:55:54 PM PDT 24
Finished Jun 26 06:56:06 PM PDT 24
Peak memory 218444 kb
Host smart-7968e34e-fefa-4518-8229-b7579f8034aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566120976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.1566120976
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1889169327
Short name T184
Test name
Test status
Simulation time 348830792 ps
CPU time 11.72 seconds
Started Jun 26 06:55:50 PM PDT 24
Finished Jun 26 06:56:04 PM PDT 24
Peak memory 226264 kb
Host smart-02c6c9b9-88fe-4206-b80a-1e48f2726357
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889169327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
1889169327
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.1836879907
Short name T57
Test name
Test status
Simulation time 954244727 ps
CPU time 8.09 seconds
Started Jun 26 06:55:55 PM PDT 24
Finished Jun 26 06:56:05 PM PDT 24
Peak memory 218552 kb
Host smart-d92a4def-8dd3-41f4-b4d0-1bf9cd91c363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836879907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.1836879907
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3614279844
Short name T385
Test name
Test status
Simulation time 186927596 ps
CPU time 2.51 seconds
Started Jun 26 06:55:52 PM PDT 24
Finished Jun 26 06:55:57 PM PDT 24
Peak memory 214844 kb
Host smart-e8dc655f-e1be-4dfc-8181-7692736a1566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614279844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3614279844
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.1627186414
Short name T643
Test name
Test status
Simulation time 780248773 ps
CPU time 19.59 seconds
Started Jun 26 06:55:50 PM PDT 24
Finished Jun 26 06:56:12 PM PDT 24
Peak memory 251108 kb
Host smart-75b52c80-7a83-459a-abe1-51146a4fcfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627186414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.1627186414
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.1725057687
Short name T611
Test name
Test status
Simulation time 85607455 ps
CPU time 8.1 seconds
Started Jun 26 06:55:51 PM PDT 24
Finished Jun 26 06:56:02 PM PDT 24
Peak memory 251152 kb
Host smart-a8309865-1ce3-43dd-b8f7-820ba0333753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725057687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1725057687
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2711135574
Short name T324
Test name
Test status
Simulation time 27797626993 ps
CPU time 293.54 seconds
Started Jun 26 06:55:51 PM PDT 24
Finished Jun 26 07:00:47 PM PDT 24
Peak memory 251960 kb
Host smart-a90b0e60-62ce-40c1-99fd-3ca3ada68f7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711135574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2711135574
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.3954636605
Short name T154
Test name
Test status
Simulation time 16293454068 ps
CPU time 301.56 seconds
Started Jun 26 06:55:51 PM PDT 24
Finished Jun 26 07:00:55 PM PDT 24
Peak memory 284192 kb
Host smart-5a221565-0d96-4fbf-bd4a-be93da80f78d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3954636605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.3954636605
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1321276783
Short name T373
Test name
Test status
Simulation time 38536026 ps
CPU time 1 seconds
Started Jun 26 06:55:50 PM PDT 24
Finished Jun 26 06:55:52 PM PDT 24
Peak memory 212044 kb
Host smart-706ade4e-b859-44d5-b7df-6ea3abf12f90
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321276783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.1321276783
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3451820666
Short name T364
Test name
Test status
Simulation time 49874010 ps
CPU time 0.95 seconds
Started Jun 26 06:56:02 PM PDT 24
Finished Jun 26 06:56:04 PM PDT 24
Peak memory 209452 kb
Host smart-3c5293d6-f2a5-4eae-a2cd-c94def5fa834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451820666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3451820666
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.1109898209
Short name T303
Test name
Test status
Simulation time 183282437 ps
CPU time 7.62 seconds
Started Jun 26 06:56:02 PM PDT 24
Finished Jun 26 06:56:11 PM PDT 24
Peak memory 218388 kb
Host smart-1deb70d7-37f4-4fde-bc8f-7ace637d2cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109898209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.1109898209
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.4175415950
Short name T35
Test name
Test status
Simulation time 73398944 ps
CPU time 1.94 seconds
Started Jun 26 06:56:05 PM PDT 24
Finished Jun 26 06:56:08 PM PDT 24
Peak memory 217408 kb
Host smart-7a264938-b14d-461b-9489-787b71a24b55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175415950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.4175415950
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.2755376674
Short name T217
Test name
Test status
Simulation time 1219035358 ps
CPU time 4.2 seconds
Started Jun 26 06:56:05 PM PDT 24
Finished Jun 26 06:56:11 PM PDT 24
Peak memory 218436 kb
Host smart-48dfa682-4e54-45a0-8eec-850ceb43d531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755376674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2755376674
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1432632997
Short name T467
Test name
Test status
Simulation time 2294238016 ps
CPU time 13.05 seconds
Started Jun 26 06:56:03 PM PDT 24
Finished Jun 26 06:56:17 PM PDT 24
Peak memory 226296 kb
Host smart-c8958dc1-614c-45c9-abce-b5a5d9ca2761
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432632997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1432632997
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.4037331145
Short name T547
Test name
Test status
Simulation time 1423686335 ps
CPU time 10.08 seconds
Started Jun 26 06:56:04 PM PDT 24
Finished Jun 26 06:56:16 PM PDT 24
Peak memory 218452 kb
Host smart-259f3454-3e64-4fdc-a70e-9408f4754c1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037331145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.4037331145
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3010891115
Short name T423
Test name
Test status
Simulation time 2535389180 ps
CPU time 11.34 seconds
Started Jun 26 06:56:04 PM PDT 24
Finished Jun 26 06:56:17 PM PDT 24
Peak memory 218508 kb
Host smart-559f570a-19f9-48cb-bc74-a36743c02a90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010891115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3010891115
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.3949565300
Short name T810
Test name
Test status
Simulation time 744670827 ps
CPU time 14.09 seconds
Started Jun 26 06:56:05 PM PDT 24
Finished Jun 26 06:56:21 PM PDT 24
Peak memory 218484 kb
Host smart-bbfa5a5d-aeb2-4af0-be3e-b48293f70425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949565300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.3949565300
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2312769998
Short name T435
Test name
Test status
Simulation time 52051051 ps
CPU time 2.76 seconds
Started Jun 26 06:55:51 PM PDT 24
Finished Jun 26 06:55:56 PM PDT 24
Peak memory 214832 kb
Host smart-1631e861-e089-40a8-8cdc-ebc120e0d7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312769998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2312769998
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3699603455
Short name T427
Test name
Test status
Simulation time 311675221 ps
CPU time 30.34 seconds
Started Jun 26 06:55:51 PM PDT 24
Finished Jun 26 06:56:24 PM PDT 24
Peak memory 251140 kb
Host smart-f1886e58-51af-4a44-95b7-bcda175cef19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699603455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3699603455
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3879648852
Short name T836
Test name
Test status
Simulation time 160769349 ps
CPU time 6.2 seconds
Started Jun 26 06:56:04 PM PDT 24
Finished Jun 26 06:56:12 PM PDT 24
Peak memory 226692 kb
Host smart-2a70b15d-531b-47c8-b08b-c1226ed8c7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879648852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3879648852
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.3125670010
Short name T546
Test name
Test status
Simulation time 41840967764 ps
CPU time 149.64 seconds
Started Jun 26 06:56:05 PM PDT 24
Finished Jun 26 06:58:37 PM PDT 24
Peak memory 268296 kb
Host smart-c84053a8-a0a3-488d-a10a-cf824ad33a8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125670010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.3125670010
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1014991102
Short name T157
Test name
Test status
Simulation time 37349285 ps
CPU time 0.88 seconds
Started Jun 26 06:55:47 PM PDT 24
Finished Jun 26 06:55:49 PM PDT 24
Peak memory 212028 kb
Host smart-18247cd6-7a61-4f6b-812f-368051848bac
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014991102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1014991102
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.4258052386
Short name T288
Test name
Test status
Simulation time 14259101 ps
CPU time 0.88 seconds
Started Jun 26 06:56:14 PM PDT 24
Finished Jun 26 06:56:16 PM PDT 24
Peak memory 209220 kb
Host smart-e20479ad-9029-45b7-805f-bebdb49b8797
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258052386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.4258052386
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2100599976
Short name T390
Test name
Test status
Simulation time 488736289 ps
CPU time 11.32 seconds
Started Jun 26 06:56:05 PM PDT 24
Finished Jun 26 06:56:18 PM PDT 24
Peak memory 218348 kb
Host smart-02f3997e-db75-401e-97cf-c853124b286b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100599976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2100599976
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.3273916972
Short name T736
Test name
Test status
Simulation time 452759649 ps
CPU time 10.64 seconds
Started Jun 26 06:56:02 PM PDT 24
Finished Jun 26 06:56:14 PM PDT 24
Peak memory 217356 kb
Host smart-b9fd8276-f01c-40a6-85cb-7dba46d577c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273916972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.3273916972
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3532763610
Short name T483
Test name
Test status
Simulation time 130047519 ps
CPU time 3.51 seconds
Started Jun 26 06:56:03 PM PDT 24
Finished Jun 26 06:56:08 PM PDT 24
Peak memory 218504 kb
Host smart-6cb90343-92ac-45e6-bd85-d8608ebb632d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532763610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3532763610
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2260736792
Short name T453
Test name
Test status
Simulation time 340760622 ps
CPU time 12.19 seconds
Started Jun 26 06:56:05 PM PDT 24
Finished Jun 26 06:56:19 PM PDT 24
Peak memory 226228 kb
Host smart-f691fe4d-3b65-452f-9895-e988434bf97d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260736792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2260736792
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.3172361314
Short name T684
Test name
Test status
Simulation time 481219767 ps
CPU time 14.93 seconds
Started Jun 26 06:56:14 PM PDT 24
Finished Jun 26 06:56:31 PM PDT 24
Peak memory 218664 kb
Host smart-952b71bd-d622-4fcd-a919-62a61f448f96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172361314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.3172361314
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.1357253686
Short name T646
Test name
Test status
Simulation time 384962540 ps
CPU time 13.23 seconds
Started Jun 26 06:56:02 PM PDT 24
Finished Jun 26 06:56:17 PM PDT 24
Peak memory 218452 kb
Host smart-8ad01dfa-72b0-4270-9293-1601483ec85a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357253686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
1357253686
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.381434119
Short name T771
Test name
Test status
Simulation time 362236348 ps
CPU time 14.41 seconds
Started Jun 26 06:56:04 PM PDT 24
Finished Jun 26 06:56:19 PM PDT 24
Peak memory 218460 kb
Host smart-cd48a75a-f751-47e4-b5ba-76407a1b4a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381434119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.381434119
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.653520774
Short name T104
Test name
Test status
Simulation time 478695867 ps
CPU time 2.46 seconds
Started Jun 26 06:56:11 PM PDT 24
Finished Jun 26 06:56:16 PM PDT 24
Peak memory 214656 kb
Host smart-507486ff-192b-4009-b54f-71e6b1617041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653520774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.653520774
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3910826720
Short name T718
Test name
Test status
Simulation time 534771242 ps
CPU time 18.03 seconds
Started Jun 26 06:56:04 PM PDT 24
Finished Jun 26 06:56:24 PM PDT 24
Peak memory 251144 kb
Host smart-b2262109-1016-422d-838f-9be383730235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910826720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3910826720
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.3671885737
Short name T524
Test name
Test status
Simulation time 3776402378 ps
CPU time 9.3 seconds
Started Jun 26 06:56:01 PM PDT 24
Finished Jun 26 06:56:12 PM PDT 24
Peak memory 251184 kb
Host smart-dcffc233-8253-4848-965b-9e9f4d08c8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671885737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.3671885737
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.4087195508
Short name T537
Test name
Test status
Simulation time 14842365003 ps
CPU time 482.91 seconds
Started Jun 26 06:56:04 PM PDT 24
Finished Jun 26 07:04:09 PM PDT 24
Peak memory 304228 kb
Host smart-10b31227-b68b-4912-b6b7-5d033ad6b205
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087195508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.4087195508
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3890558317
Short name T608
Test name
Test status
Simulation time 23445858 ps
CPU time 0.99 seconds
Started Jun 26 06:56:12 PM PDT 24
Finished Jun 26 06:56:14 PM PDT 24
Peak memory 212056 kb
Host smart-4ae11f42-1099-40cd-8daf-3d522b515681
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890558317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3890558317
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3401022632
Short name T579
Test name
Test status
Simulation time 21480500 ps
CPU time 1 seconds
Started Jun 26 06:56:15 PM PDT 24
Finished Jun 26 06:56:17 PM PDT 24
Peak memory 209364 kb
Host smart-c2f4c723-a2d2-47c2-a42e-f85551625eb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401022632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3401022632
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.3400232538
Short name T285
Test name
Test status
Simulation time 1022030818 ps
CPU time 14.49 seconds
Started Jun 26 06:56:11 PM PDT 24
Finished Jun 26 06:56:26 PM PDT 24
Peak memory 218448 kb
Host smart-f5885214-f111-4058-b5c0-1d9f6277e4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400232538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.3400232538
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1273146859
Short name T804
Test name
Test status
Simulation time 2100760346 ps
CPU time 5.9 seconds
Started Jun 26 06:56:11 PM PDT 24
Finished Jun 26 06:56:19 PM PDT 24
Peak memory 217468 kb
Host smart-ca21c5a7-0cfa-4b1c-b2c8-0c974bcc11ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273146859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.1273146859
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3539363847
Short name T846
Test name
Test status
Simulation time 122331779 ps
CPU time 5.3 seconds
Started Jun 26 06:56:15 PM PDT 24
Finished Jun 26 06:56:22 PM PDT 24
Peak memory 218636 kb
Host smart-fd68f6eb-6713-48b7-a60f-be75054d918c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539363847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3539363847
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1180954132
Short name T447
Test name
Test status
Simulation time 943552061 ps
CPU time 11.9 seconds
Started Jun 26 06:56:05 PM PDT 24
Finished Jun 26 06:56:19 PM PDT 24
Peak memory 226248 kb
Host smart-3d26324b-fd6d-496d-a1f0-d789f59020ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180954132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1180954132
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2776880578
Short name T287
Test name
Test status
Simulation time 253421022 ps
CPU time 9.51 seconds
Started Jun 26 06:56:14 PM PDT 24
Finished Jun 26 06:56:25 PM PDT 24
Peak memory 218672 kb
Host smart-65e51221-73ef-448f-b13a-17576a7a57d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776880578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.2776880578
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.1633383432
Short name T167
Test name
Test status
Simulation time 4200860699 ps
CPU time 7.29 seconds
Started Jun 26 06:56:02 PM PDT 24
Finished Jun 26 06:56:11 PM PDT 24
Peak memory 218372 kb
Host smart-ec08c74f-73b1-4e6c-bd72-498fd23cbf61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633383432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
1633383432
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.1743586280
Short name T60
Test name
Test status
Simulation time 1285104774 ps
CPU time 12.79 seconds
Started Jun 26 06:56:14 PM PDT 24
Finished Jun 26 06:56:29 PM PDT 24
Peak memory 218664 kb
Host smart-3b86f82a-521f-47e2-8a20-96bfc96b89af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743586280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1743586280
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.3701112611
Short name T187
Test name
Test status
Simulation time 21756323 ps
CPU time 1.7 seconds
Started Jun 26 06:56:14 PM PDT 24
Finished Jun 26 06:56:18 PM PDT 24
Peak memory 223552 kb
Host smart-77eeec17-b420-4e14-994f-701976a0da17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701112611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.3701112611
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.1848803845
Short name T689
Test name
Test status
Simulation time 797225711 ps
CPU time 17.55 seconds
Started Jun 26 06:56:11 PM PDT 24
Finished Jun 26 06:56:30 PM PDT 24
Peak memory 251144 kb
Host smart-bb5c2c50-0a4d-49cd-8fa2-e41917409162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848803845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.1848803845
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.237357735
Short name T362
Test name
Test status
Simulation time 102569781 ps
CPU time 3.43 seconds
Started Jun 26 06:56:03 PM PDT 24
Finished Jun 26 06:56:08 PM PDT 24
Peak memory 226548 kb
Host smart-d1d918ef-ab95-4971-84a8-db501a04ed0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237357735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.237357735
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.2603300053
Short name T617
Test name
Test status
Simulation time 17281280688 ps
CPU time 60.82 seconds
Started Jun 26 06:56:07 PM PDT 24
Finished Jun 26 06:57:09 PM PDT 24
Peak memory 274428 kb
Host smart-b9544357-707a-4161-bf8d-5aa7a3ac6fdd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603300053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.2603300053
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.934583727
Short name T756
Test name
Test status
Simulation time 14955025 ps
CPU time 0.89 seconds
Started Jun 26 06:56:03 PM PDT 24
Finished Jun 26 06:56:04 PM PDT 24
Peak memory 211876 kb
Host smart-8bc84201-c6a7-4df7-b362-094b2fe933a9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934583727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.934583727
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.3420474125
Short name T156
Test name
Test status
Simulation time 11306369 ps
CPU time 0.95 seconds
Started Jun 26 06:56:19 PM PDT 24
Finished Jun 26 06:56:21 PM PDT 24
Peak memory 209176 kb
Host smart-1e3654de-8218-41ec-9756-1e0a8365fd0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420474125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3420474125
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.1923188213
Short name T732
Test name
Test status
Simulation time 306958605 ps
CPU time 15.91 seconds
Started Jun 26 06:56:19 PM PDT 24
Finished Jun 26 06:56:36 PM PDT 24
Peak memory 218456 kb
Host smart-7a5759d4-c178-4606-83c3-b80024040fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923188213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1923188213
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.1687841533
Short name T506
Test name
Test status
Simulation time 259387397 ps
CPU time 7.43 seconds
Started Jun 26 06:56:23 PM PDT 24
Finished Jun 26 06:56:32 PM PDT 24
Peak memory 217316 kb
Host smart-91c36826-d22c-4cbd-b251-1559eb25bb72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687841533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.1687841533
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.341412066
Short name T589
Test name
Test status
Simulation time 98107901 ps
CPU time 2.55 seconds
Started Jun 26 06:56:19 PM PDT 24
Finished Jun 26 06:56:23 PM PDT 24
Peak memory 222516 kb
Host smart-a939d566-1f38-441a-9fa8-65dbb2d5c952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341412066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.341412066
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3837597314
Short name T680
Test name
Test status
Simulation time 247934735 ps
CPU time 8.83 seconds
Started Jun 26 06:56:20 PM PDT 24
Finished Jun 26 06:56:30 PM PDT 24
Peak memory 219124 kb
Host smart-674dbf3a-d0ed-46e3-a72c-eda1191b1dfc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837597314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3837597314
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.729495323
Short name T230
Test name
Test status
Simulation time 424642067 ps
CPU time 9.16 seconds
Started Jun 26 06:56:18 PM PDT 24
Finished Jun 26 06:56:29 PM PDT 24
Peak memory 218552 kb
Host smart-6817acd0-0b11-45dd-9ddb-da94eb050aa7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729495323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.729495323
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2616419495
Short name T240
Test name
Test status
Simulation time 1097991948 ps
CPU time 8.29 seconds
Started Jun 26 06:56:17 PM PDT 24
Finished Jun 26 06:56:27 PM PDT 24
Peak memory 218432 kb
Host smart-e062baac-fd97-479d-93eb-aa8e004dad82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616419495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2616419495
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.1887476388
Short name T461
Test name
Test status
Simulation time 1058185268 ps
CPU time 7.81 seconds
Started Jun 26 06:56:17 PM PDT 24
Finished Jun 26 06:56:26 PM PDT 24
Peak memory 218452 kb
Host smart-55e4f61a-22c5-459b-9181-2a0af3747b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887476388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.1887476388
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.2546151785
Short name T320
Test name
Test status
Simulation time 53741229 ps
CPU time 3.36 seconds
Started Jun 26 06:56:17 PM PDT 24
Finished Jun 26 06:56:22 PM PDT 24
Peak memory 214952 kb
Host smart-63d4c54d-20d2-4323-91bc-31963fb168a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546151785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.2546151785
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3535744520
Short name T651
Test name
Test status
Simulation time 229770609 ps
CPU time 20.61 seconds
Started Jun 26 06:56:19 PM PDT 24
Finished Jun 26 06:56:41 PM PDT 24
Peak memory 251132 kb
Host smart-8eb6dbbe-c077-42ce-ae9b-a1b94be21a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535744520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3535744520
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.3072531531
Short name T290
Test name
Test status
Simulation time 92050340 ps
CPU time 7.19 seconds
Started Jun 26 06:56:17 PM PDT 24
Finished Jun 26 06:56:26 PM PDT 24
Peak memory 247380 kb
Host smart-5b002ace-205f-4c88-ae50-0cda2509c526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072531531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3072531531
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.2514315129
Short name T29
Test name
Test status
Simulation time 1901888001 ps
CPU time 28.8 seconds
Started Jun 26 06:56:19 PM PDT 24
Finished Jun 26 06:56:49 PM PDT 24
Peak memory 247432 kb
Host smart-cf19d245-34b4-4f39-b10e-369205f83bdb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514315129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.2514315129
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.1072055799
Short name T808
Test name
Test status
Simulation time 20750704454 ps
CPU time 815.52 seconds
Started Jun 26 06:56:20 PM PDT 24
Finished Jun 26 07:09:57 PM PDT 24
Peak memory 333244 kb
Host smart-9bcc3d85-d1ac-41af-9f1f-11aef47ca09c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1072055799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.1072055799
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2051210891
Short name T223
Test name
Test status
Simulation time 61300876 ps
CPU time 1.16 seconds
Started Jun 26 06:56:17 PM PDT 24
Finished Jun 26 06:56:19 PM PDT 24
Peak memory 213224 kb
Host smart-e8fb5c1a-88bb-4acd-bf5b-5722bab491b1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051210891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.2051210891
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.1954676230
Short name T460
Test name
Test status
Simulation time 18928297 ps
CPU time 0.9 seconds
Started Jun 26 06:52:29 PM PDT 24
Finished Jun 26 06:52:32 PM PDT 24
Peak memory 209152 kb
Host smart-61a499a6-95d0-4706-b5bb-b13fc6e907e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954676230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.1954676230
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1095328497
Short name T517
Test name
Test status
Simulation time 1082919093 ps
CPU time 10.37 seconds
Started Jun 26 06:52:17 PM PDT 24
Finished Jun 26 06:52:28 PM PDT 24
Peak memory 218652 kb
Host smart-57edb9ef-1002-45d1-b621-a135a4d54408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095328497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1095328497
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.618096297
Short name T730
Test name
Test status
Simulation time 166820315 ps
CPU time 1.36 seconds
Started Jun 26 06:52:27 PM PDT 24
Finished Jun 26 06:52:30 PM PDT 24
Peak memory 217372 kb
Host smart-a3bfab32-ce66-49dc-a5d6-5c7339c42516
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618096297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.618096297
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1210584560
Short name T701
Test name
Test status
Simulation time 16804425319 ps
CPU time 35.25 seconds
Started Jun 26 06:52:28 PM PDT 24
Finished Jun 26 06:53:05 PM PDT 24
Peak memory 226228 kb
Host smart-669c982b-e98e-4e0f-866e-6e29eb2f353e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210584560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1210584560
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.1529744883
Short name T286
Test name
Test status
Simulation time 304300970 ps
CPU time 1.71 seconds
Started Jun 26 06:52:28 PM PDT 24
Finished Jun 26 06:52:32 PM PDT 24
Peak memory 217528 kb
Host smart-7ca4f335-cc69-4852-9c03-6171031e45d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529744883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.1
529744883
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1484073247
Short name T857
Test name
Test status
Simulation time 876789074 ps
CPU time 7.17 seconds
Started Jun 26 06:52:26 PM PDT 24
Finished Jun 26 06:52:35 PM PDT 24
Peak memory 218432 kb
Host smart-939f57c1-b4df-4d83-9b52-a692a596d65c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484073247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.1484073247
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2882532467
Short name T20
Test name
Test status
Simulation time 812276496 ps
CPU time 11.86 seconds
Started Jun 26 06:52:25 PM PDT 24
Finished Jun 26 06:52:38 PM PDT 24
Peak memory 217912 kb
Host smart-03b2c46d-e8a3-4623-9aeb-cc736e123732
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882532467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.2882532467
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.3265896788
Short name T581
Test name
Test status
Simulation time 764784517 ps
CPU time 5.1 seconds
Started Jun 26 06:52:28 PM PDT 24
Finished Jun 26 06:52:35 PM PDT 24
Peak memory 217924 kb
Host smart-4ed5e3ac-565c-493c-b11b-b07826c3122e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265896788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
3265896788
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3648394299
Short name T311
Test name
Test status
Simulation time 24809791997 ps
CPU time 63.19 seconds
Started Jun 26 06:52:26 PM PDT 24
Finished Jun 26 06:53:30 PM PDT 24
Peak memory 270924 kb
Host smart-30a737e3-1d43-40eb-95b0-22bd129454bc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648394299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.3648394299
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.527859691
Short name T369
Test name
Test status
Simulation time 438736860 ps
CPU time 12.28 seconds
Started Jun 26 06:52:28 PM PDT 24
Finished Jun 26 06:52:42 PM PDT 24
Peak memory 251112 kb
Host smart-597ae703-6058-4857-aa72-148b85c5e9ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527859691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_state_post_trans.527859691
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.2269268585
Short name T270
Test name
Test status
Simulation time 342456909 ps
CPU time 3.58 seconds
Started Jun 26 06:52:15 PM PDT 24
Finished Jun 26 06:52:19 PM PDT 24
Peak memory 218348 kb
Host smart-43f8a012-9610-4c6f-8496-5fc2ae0315f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269268585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.2269268585
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2286604614
Short name T375
Test name
Test status
Simulation time 399970227 ps
CPU time 6.33 seconds
Started Jun 26 06:52:27 PM PDT 24
Finished Jun 26 06:52:36 PM PDT 24
Peak memory 214708 kb
Host smart-986e3dc7-0e93-4ce4-a069-0c84e436b6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286604614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2286604614
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.4046032870
Short name T666
Test name
Test status
Simulation time 501710172 ps
CPU time 19.1 seconds
Started Jun 26 06:52:29 PM PDT 24
Finished Jun 26 06:52:50 PM PDT 24
Peak memory 226232 kb
Host smart-a48d9233-8b35-4ceb-a9af-9950eebbe0c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046032870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.4046032870
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2679958833
Short name T831
Test name
Test status
Simulation time 368880377 ps
CPU time 15.53 seconds
Started Jun 26 06:52:28 PM PDT 24
Finished Jun 26 06:52:46 PM PDT 24
Peak memory 218448 kb
Host smart-7a160054-4f71-4333-b694-e34378bf67e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679958833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.2679958833
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.2569553596
Short name T590
Test name
Test status
Simulation time 2049017736 ps
CPU time 9.74 seconds
Started Jun 26 06:52:27 PM PDT 24
Finished Jun 26 06:52:39 PM PDT 24
Peak memory 218432 kb
Host smart-4ae16b22-4599-4770-a3af-9e46126b90bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569553596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.2
569553596
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.2118973478
Short name T828
Test name
Test status
Simulation time 173471569 ps
CPU time 8.09 seconds
Started Jun 26 06:52:28 PM PDT 24
Finished Jun 26 06:52:39 PM PDT 24
Peak memory 224904 kb
Host smart-657b57ae-c431-4a33-a92f-e8f759d32572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118973478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.2118973478
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3657117022
Short name T576
Test name
Test status
Simulation time 257138972 ps
CPU time 3.77 seconds
Started Jun 26 06:52:17 PM PDT 24
Finished Jun 26 06:52:22 PM PDT 24
Peak memory 217952 kb
Host smart-74783b65-c245-4f9c-b15a-a537988bea9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657117022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3657117022
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.4261232283
Short name T715
Test name
Test status
Simulation time 714347567 ps
CPU time 22.53 seconds
Started Jun 26 06:52:17 PM PDT 24
Finished Jun 26 06:52:41 PM PDT 24
Peak memory 251160 kb
Host smart-762d9061-f705-4287-b1dd-edc6521aa74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261232283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.4261232283
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3292921229
Short name T640
Test name
Test status
Simulation time 319461656 ps
CPU time 8.11 seconds
Started Jun 26 06:52:16 PM PDT 24
Finished Jun 26 06:52:26 PM PDT 24
Peak memory 251180 kb
Host smart-ece9a77c-e869-41f9-8b70-e57605d7f5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292921229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3292921229
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.3014721670
Short name T88
Test name
Test status
Simulation time 13637056511 ps
CPU time 117.73 seconds
Started Jun 26 06:52:27 PM PDT 24
Finished Jun 26 06:54:26 PM PDT 24
Peak memory 275792 kb
Host smart-dc45cbbf-6ef1-4291-bbc0-e65d82c45ab4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014721670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.3014721670
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2333223725
Short name T629
Test name
Test status
Simulation time 73307012 ps
CPU time 0.84 seconds
Started Jun 26 06:52:17 PM PDT 24
Finished Jun 26 06:52:19 PM PDT 24
Peak memory 212048 kb
Host smart-24cd42de-ec01-47d0-8a85-02837a2363ae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333223725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.2333223725
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.978818229
Short name T221
Test name
Test status
Simulation time 14909882 ps
CPU time 0.88 seconds
Started Jun 26 06:56:18 PM PDT 24
Finished Jun 26 06:56:20 PM PDT 24
Peak memory 209176 kb
Host smart-9b785cac-4bf3-4c60-bd00-702af76e0de7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978818229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.978818229
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2513825484
Short name T355
Test name
Test status
Simulation time 198686238 ps
CPU time 7.55 seconds
Started Jun 26 06:56:18 PM PDT 24
Finished Jun 26 06:56:27 PM PDT 24
Peak memory 218456 kb
Host smart-5d01e822-46b0-47bd-9aa8-db010e280cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513825484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2513825484
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1408893803
Short name T192
Test name
Test status
Simulation time 1534528423 ps
CPU time 4.9 seconds
Started Jun 26 06:56:19 PM PDT 24
Finished Jun 26 06:56:25 PM PDT 24
Peak memory 217348 kb
Host smart-920bdbb3-97ed-4ce1-be64-d11c8e6d4462
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408893803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1408893803
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.2381489690
Short name T710
Test name
Test status
Simulation time 268295021 ps
CPU time 1.78 seconds
Started Jun 26 06:56:20 PM PDT 24
Finished Jun 26 06:56:23 PM PDT 24
Peak memory 218448 kb
Host smart-dcb608d8-1830-4e4d-a205-a9e15abce13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381489690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2381489690
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.3648315744
Short name T728
Test name
Test status
Simulation time 1844282672 ps
CPU time 15.08 seconds
Started Jun 26 06:56:17 PM PDT 24
Finished Jun 26 06:56:33 PM PDT 24
Peak memory 219112 kb
Host smart-db50478f-1f74-4404-bdf9-adebd7acd6a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648315744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.3648315744
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1328613185
Short name T757
Test name
Test status
Simulation time 1340113198 ps
CPU time 14.58 seconds
Started Jun 26 06:56:21 PM PDT 24
Finished Jun 26 06:56:37 PM PDT 24
Peak memory 218536 kb
Host smart-681b28d2-60f3-4f3e-b93a-f23d74ab8ee8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328613185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1328613185
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.4070017373
Short name T301
Test name
Test status
Simulation time 13598252790 ps
CPU time 18.97 seconds
Started Jun 26 06:56:17 PM PDT 24
Finished Jun 26 06:56:37 PM PDT 24
Peak memory 218488 kb
Host smart-312fd23f-6e14-4e5d-b648-c3964d6f07f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070017373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
4070017373
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.3985749073
Short name T58
Test name
Test status
Simulation time 918501353 ps
CPU time 8.42 seconds
Started Jun 26 06:56:18 PM PDT 24
Finished Jun 26 06:56:29 PM PDT 24
Peak memory 218504 kb
Host smart-fe7d859c-d4b4-4bca-859c-533af0f78a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985749073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3985749073
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.2290595030
Short name T112
Test name
Test status
Simulation time 61810652 ps
CPU time 3.13 seconds
Started Jun 26 06:56:17 PM PDT 24
Finished Jun 26 06:56:22 PM PDT 24
Peak memory 215396 kb
Host smart-394d25cd-9305-4524-afac-046394152fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290595030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.2290595030
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.2897380556
Short name T837
Test name
Test status
Simulation time 1338780948 ps
CPU time 12.18 seconds
Started Jun 26 06:56:23 PM PDT 24
Finished Jun 26 06:56:36 PM PDT 24
Peak memory 251144 kb
Host smart-97d6d63b-d08b-4d3f-8b38-c90527c55492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897380556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.2897380556
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.61122323
Short name T568
Test name
Test status
Simulation time 111062335 ps
CPU time 8.13 seconds
Started Jun 26 06:56:17 PM PDT 24
Finished Jun 26 06:56:26 PM PDT 24
Peak memory 251268 kb
Host smart-7fba455c-0f32-4faa-adfa-775045f343ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61122323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.61122323
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.3810087208
Short name T512
Test name
Test status
Simulation time 29660393427 ps
CPU time 139.2 seconds
Started Jun 26 06:56:24 PM PDT 24
Finished Jun 26 06:58:45 PM PDT 24
Peak memory 251200 kb
Host smart-ee1d8bb2-e91d-4028-aa61-99098dd2128f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810087208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.3810087208
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.727842211
Short name T254
Test name
Test status
Simulation time 190319000 ps
CPU time 0.85 seconds
Started Jun 26 06:56:17 PM PDT 24
Finished Jun 26 06:56:20 PM PDT 24
Peak memory 213108 kb
Host smart-50a31bae-a4c6-4de8-a9bc-c7b2665b1337
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727842211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ct
rl_volatile_unlock_smoke.727842211
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.400692986
Short name T552
Test name
Test status
Simulation time 456166142 ps
CPU time 19.57 seconds
Started Jun 26 06:56:38 PM PDT 24
Finished Jun 26 06:57:00 PM PDT 24
Peak memory 218436 kb
Host smart-7cefe70f-4f03-4ecc-8c8b-7c2d43138845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400692986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.400692986
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3399298406
Short name T7
Test name
Test status
Simulation time 1535667645 ps
CPU time 5.59 seconds
Started Jun 26 06:56:38 PM PDT 24
Finished Jun 26 06:56:46 PM PDT 24
Peak memory 217712 kb
Host smart-8c3d60ab-4423-4fa4-be75-0733b9870a25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399298406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.3399298406
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.3523996159
Short name T441
Test name
Test status
Simulation time 779449802 ps
CPU time 3.86 seconds
Started Jun 26 06:56:17 PM PDT 24
Finished Jun 26 06:56:23 PM PDT 24
Peak memory 218532 kb
Host smart-4994ab56-eaeb-478c-a4eb-96fc27cd10e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523996159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.3523996159
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.1955397546
Short name T61
Test name
Test status
Simulation time 313400945 ps
CPU time 15.1 seconds
Started Jun 26 06:56:37 PM PDT 24
Finished Jun 26 06:56:54 PM PDT 24
Peak memory 226212 kb
Host smart-bfe9bb7e-4fd3-4d56-a692-13f4f0955ab6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955397546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1955397546
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.3792772487
Short name T565
Test name
Test status
Simulation time 284207165 ps
CPU time 11.32 seconds
Started Jun 26 06:56:40 PM PDT 24
Finished Jun 26 06:56:54 PM PDT 24
Peak memory 218548 kb
Host smart-397119ad-6460-48c4-86e7-73e94a66a4e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792772487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.3792772487
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2684085338
Short name T774
Test name
Test status
Simulation time 911262297 ps
CPU time 10.47 seconds
Started Jun 26 06:56:37 PM PDT 24
Finished Jun 26 06:56:50 PM PDT 24
Peak memory 226244 kb
Host smart-cf36476b-1b3c-4c05-9afb-3ab139f8fa27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684085338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
2684085338
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3765751175
Short name T555
Test name
Test status
Simulation time 612510607 ps
CPU time 12.55 seconds
Started Jun 26 06:56:38 PM PDT 24
Finished Jun 26 06:56:54 PM PDT 24
Peak memory 226084 kb
Host smart-7835e32a-4b12-4da9-84e6-d5022b91dc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765751175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3765751175
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.3847719436
Short name T68
Test name
Test status
Simulation time 95853264 ps
CPU time 2.42 seconds
Started Jun 26 06:56:22 PM PDT 24
Finished Jun 26 06:56:25 PM PDT 24
Peak memory 214520 kb
Host smart-ad71c93d-4ac5-46ee-96af-b001fe82732c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847719436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.3847719436
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.772863514
Short name T486
Test name
Test status
Simulation time 1061581296 ps
CPU time 18.88 seconds
Started Jun 26 06:56:19 PM PDT 24
Finished Jun 26 06:56:39 PM PDT 24
Peak memory 251128 kb
Host smart-4b11fb69-fe9c-46d9-8c6a-a99313277d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772863514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.772863514
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.4042685795
Short name T394
Test name
Test status
Simulation time 350529037 ps
CPU time 3.42 seconds
Started Jun 26 06:56:18 PM PDT 24
Finished Jun 26 06:56:23 PM PDT 24
Peak memory 222952 kb
Host smart-94dff096-8f64-4879-8e9c-ef33047373af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042685795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.4042685795
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.3198252524
Short name T488
Test name
Test status
Simulation time 18314338987 ps
CPU time 189.85 seconds
Started Jun 26 06:56:40 PM PDT 24
Finished Jun 26 06:59:53 PM PDT 24
Peak memory 226276 kb
Host smart-9ae9f2d8-04e9-4578-914b-9c8b1661b6d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198252524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.3198252524
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1298175224
Short name T625
Test name
Test status
Simulation time 23947603 ps
CPU time 1.04 seconds
Started Jun 26 06:56:18 PM PDT 24
Finished Jun 26 06:56:21 PM PDT 24
Peak memory 212076 kb
Host smart-b6787789-21a0-48f6-aaa0-c62626c7d425
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298175224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1298175224
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.488289332
Short name T530
Test name
Test status
Simulation time 52445484 ps
CPU time 1.07 seconds
Started Jun 26 06:56:40 PM PDT 24
Finished Jun 26 06:56:44 PM PDT 24
Peak memory 209500 kb
Host smart-227cd5dd-2774-4467-9a34-a3be7fa88c87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488289332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.488289332
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2530813838
Short name T813
Test name
Test status
Simulation time 254492803 ps
CPU time 8.98 seconds
Started Jun 26 06:56:37 PM PDT 24
Finished Jun 26 06:56:47 PM PDT 24
Peak memory 218456 kb
Host smart-c3e9ea2d-2102-42c5-8b66-ab51216aea08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530813838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2530813838
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3954900550
Short name T780
Test name
Test status
Simulation time 164770295 ps
CPU time 1.58 seconds
Started Jun 26 06:56:38 PM PDT 24
Finished Jun 26 06:56:42 PM PDT 24
Peak memory 217340 kb
Host smart-e0e48843-5a37-43d4-92b8-2d64feb8a1fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954900550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3954900550
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.1997348001
Short name T593
Test name
Test status
Simulation time 223309719 ps
CPU time 3.58 seconds
Started Jun 26 06:56:35 PM PDT 24
Finished Jun 26 06:56:40 PM PDT 24
Peak memory 222564 kb
Host smart-c39a8f56-9a97-438b-9d3e-a675d120f69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997348001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1997348001
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.1520834867
Short name T180
Test name
Test status
Simulation time 3648607500 ps
CPU time 8.12 seconds
Started Jun 26 06:56:39 PM PDT 24
Finished Jun 26 06:56:50 PM PDT 24
Peak memory 226284 kb
Host smart-0c6a2e4d-2374-4cae-921d-5426fd253b87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520834867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1520834867
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1187309729
Short name T177
Test name
Test status
Simulation time 1594073902 ps
CPU time 15.77 seconds
Started Jun 26 06:56:40 PM PDT 24
Finished Jun 26 06:56:59 PM PDT 24
Peak memory 218480 kb
Host smart-f22173b9-ac42-4b2b-b166-b5cec58faf97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187309729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.1187309729
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.1524918336
Short name T356
Test name
Test status
Simulation time 217697067 ps
CPU time 8.62 seconds
Started Jun 26 06:56:39 PM PDT 24
Finished Jun 26 06:56:51 PM PDT 24
Peak memory 218448 kb
Host smart-b9db0307-0a41-441a-a768-35e8812a68f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524918336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
1524918336
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.1958899533
Short name T74
Test name
Test status
Simulation time 139904308 ps
CPU time 5.4 seconds
Started Jun 26 06:56:40 PM PDT 24
Finished Jun 26 06:56:49 PM PDT 24
Peak memory 217864 kb
Host smart-348afb8c-46e6-4591-a19b-4c73a30b2e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958899533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1958899533
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.2409145658
Short name T764
Test name
Test status
Simulation time 206487907 ps
CPU time 25.45 seconds
Started Jun 26 06:56:37 PM PDT 24
Finished Jun 26 06:57:05 PM PDT 24
Peak memory 251144 kb
Host smart-6959ec42-2704-4f95-ae9c-062752b7f60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409145658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.2409145658
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.854809433
Short name T388
Test name
Test status
Simulation time 334110469 ps
CPU time 4.5 seconds
Started Jun 26 06:56:38 PM PDT 24
Finished Jun 26 06:56:46 PM PDT 24
Peak memory 222788 kb
Host smart-811baae1-93a7-4d88-9b81-33b14cd5906f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854809433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.854809433
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.2530440430
Short name T419
Test name
Test status
Simulation time 13734483819 ps
CPU time 246.45 seconds
Started Jun 26 06:56:40 PM PDT 24
Finished Jun 26 07:00:49 PM PDT 24
Peak memory 278860 kb
Host smart-c92fa49d-466a-4f10-9dba-8acf639fdc69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530440430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.2530440430
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.3144188660
Short name T702
Test name
Test status
Simulation time 13003795148 ps
CPU time 390 seconds
Started Jun 26 06:56:39 PM PDT 24
Finished Jun 26 07:03:12 PM PDT 24
Peak memory 259488 kb
Host smart-3b7db9c6-7510-4a6e-96db-3e2f07869b8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3144188660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.3144188660
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.941019676
Short name T319
Test name
Test status
Simulation time 36263885 ps
CPU time 0.94 seconds
Started Jun 26 06:56:36 PM PDT 24
Finished Jun 26 06:56:39 PM PDT 24
Peak memory 212080 kb
Host smart-7b4c8c2e-bf64-4003-8ff1-05f3bac2df16
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941019676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ct
rl_volatile_unlock_smoke.941019676
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.183644350
Short name T505
Test name
Test status
Simulation time 16274368 ps
CPU time 0.96 seconds
Started Jun 26 06:56:39 PM PDT 24
Finished Jun 26 06:56:43 PM PDT 24
Peak memory 209356 kb
Host smart-e4c3cbd5-3bcb-456d-bd1d-bf383850b7be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183644350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.183644350
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.3363376878
Short name T515
Test name
Test status
Simulation time 1211812624 ps
CPU time 15.1 seconds
Started Jun 26 06:56:38 PM PDT 24
Finished Jun 26 06:56:56 PM PDT 24
Peak memory 218384 kb
Host smart-fc0a3183-dcaa-494a-8a51-0eb348e09d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363376878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3363376878
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.2452750499
Short name T336
Test name
Test status
Simulation time 763607136 ps
CPU time 5.31 seconds
Started Jun 26 06:56:37 PM PDT 24
Finished Jun 26 06:56:44 PM PDT 24
Peak memory 217716 kb
Host smart-b7291ece-0558-4cb0-828d-eff5ff01b551
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452750499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.2452750499
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.284113038
Short name T695
Test name
Test status
Simulation time 87527823 ps
CPU time 3.18 seconds
Started Jun 26 06:56:38 PM PDT 24
Finished Jun 26 06:56:44 PM PDT 24
Peak memory 218400 kb
Host smart-62f1fc20-0179-4243-b4b6-fcdc12fe3e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284113038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.284113038
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.2878455454
Short name T734
Test name
Test status
Simulation time 585969272 ps
CPU time 16.2 seconds
Started Jun 26 06:56:40 PM PDT 24
Finished Jun 26 06:56:59 PM PDT 24
Peak memory 219060 kb
Host smart-9e717db1-47ac-44fd-809c-68e047d4c8c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878455454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2878455454
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1257931471
Short name T253
Test name
Test status
Simulation time 431157188 ps
CPU time 13.07 seconds
Started Jun 26 06:56:38 PM PDT 24
Finished Jun 26 06:56:55 PM PDT 24
Peak memory 218536 kb
Host smart-312a5c49-ff79-4388-8315-2e50aff0d0d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257931471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.1257931471
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2980348156
Short name T379
Test name
Test status
Simulation time 352469603 ps
CPU time 8.99 seconds
Started Jun 26 06:56:37 PM PDT 24
Finished Jun 26 06:56:49 PM PDT 24
Peak memory 218408 kb
Host smart-8f747f9a-1d31-4bc4-a63a-6193dba643ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980348156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2980348156
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.4215742033
Short name T476
Test name
Test status
Simulation time 2987354837 ps
CPU time 10.39 seconds
Started Jun 26 06:56:38 PM PDT 24
Finished Jun 26 06:56:52 PM PDT 24
Peak memory 218572 kb
Host smart-83226955-a33d-4c9a-b707-464bb135fc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215742033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.4215742033
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.343393002
Short name T708
Test name
Test status
Simulation time 35460502 ps
CPU time 2.11 seconds
Started Jun 26 06:56:38 PM PDT 24
Finished Jun 26 06:56:43 PM PDT 24
Peak memory 214408 kb
Host smart-8ae8bd13-280e-41c2-b19a-e98815c0316a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343393002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.343393002
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.3672441350
Short name T259
Test name
Test status
Simulation time 1264787786 ps
CPU time 23.16 seconds
Started Jun 26 06:56:37 PM PDT 24
Finished Jun 26 06:57:02 PM PDT 24
Peak memory 251156 kb
Host smart-e2037ef7-87f2-4927-835b-f15abce30b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672441350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3672441350
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2628908267
Short name T359
Test name
Test status
Simulation time 306169891 ps
CPU time 2.99 seconds
Started Jun 26 06:56:39 PM PDT 24
Finished Jun 26 06:56:45 PM PDT 24
Peak memory 222696 kb
Host smart-0d7a4fdd-1097-4b0e-b642-250c23e4612d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628908267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2628908267
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.2176470644
Short name T558
Test name
Test status
Simulation time 9119375847 ps
CPU time 40.46 seconds
Started Jun 26 06:56:37 PM PDT 24
Finished Jun 26 06:57:20 PM PDT 24
Peak memory 251180 kb
Host smart-ad49690d-e693-4b60-a4eb-d74d2f06975e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176470644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.2176470644
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.579315447
Short name T678
Test name
Test status
Simulation time 12922105 ps
CPU time 1.06 seconds
Started Jun 26 06:56:36 PM PDT 24
Finished Jun 26 06:56:39 PM PDT 24
Peak memory 212140 kb
Host smart-8586d3e6-062a-47fa-85ba-2024a5c9e471
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579315447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ct
rl_volatile_unlock_smoke.579315447
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.2247663097
Short name T567
Test name
Test status
Simulation time 144998648 ps
CPU time 1.05 seconds
Started Jun 26 06:57:05 PM PDT 24
Finished Jun 26 06:57:10 PM PDT 24
Peak memory 209208 kb
Host smart-4ed3a342-db41-4d24-af45-9ac63f17de07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247663097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.2247663097
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.768621034
Short name T534
Test name
Test status
Simulation time 329544045 ps
CPU time 16.61 seconds
Started Jun 26 06:56:40 PM PDT 24
Finished Jun 26 06:56:59 PM PDT 24
Peak memory 218396 kb
Host smart-e9ae3bb4-c57b-4672-af80-a9115315acf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768621034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.768621034
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.1725732695
Short name T469
Test name
Test status
Simulation time 268393023 ps
CPU time 2.1 seconds
Started Jun 26 06:56:36 PM PDT 24
Finished Jun 26 06:56:40 PM PDT 24
Peak memory 217372 kb
Host smart-04a352c6-6368-4b5a-b592-34ff6974ecf0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725732695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.1725732695
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.724248773
Short name T354
Test name
Test status
Simulation time 941070566 ps
CPU time 2.72 seconds
Started Jun 26 06:56:39 PM PDT 24
Finished Jun 26 06:56:45 PM PDT 24
Peak memory 218432 kb
Host smart-7478abb2-a410-4e73-8c12-3adcde1bc0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724248773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.724248773
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.2696716467
Short name T434
Test name
Test status
Simulation time 1860999878 ps
CPU time 15.17 seconds
Started Jun 26 06:56:40 PM PDT 24
Finished Jun 26 06:56:58 PM PDT 24
Peak memory 219088 kb
Host smart-c7cf54af-d102-44b4-840f-91efe12d65ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696716467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2696716467
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2892786795
Short name T638
Test name
Test status
Simulation time 1714209125 ps
CPU time 12.27 seconds
Started Jun 26 06:56:37 PM PDT 24
Finished Jun 26 06:56:51 PM PDT 24
Peak memory 218456 kb
Host smart-abbef6a2-074f-4966-b172-2eb2035dad09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892786795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2892786795
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1124661143
Short name T361
Test name
Test status
Simulation time 2985046042 ps
CPU time 17.8 seconds
Started Jun 26 06:56:37 PM PDT 24
Finished Jun 26 06:56:57 PM PDT 24
Peak memory 219156 kb
Host smart-b045a913-c87d-49ea-8067-b4fb2f5b7467
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124661143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1124661143
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.4294602749
Short name T721
Test name
Test status
Simulation time 372783917 ps
CPU time 12.59 seconds
Started Jun 26 06:56:39 PM PDT 24
Finished Jun 26 06:56:55 PM PDT 24
Peak memory 218516 kb
Host smart-576bba91-cf78-42d8-90c3-31b62980b830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294602749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.4294602749
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.656847586
Short name T92
Test name
Test status
Simulation time 66281941 ps
CPU time 2.92 seconds
Started Jun 26 06:56:37 PM PDT 24
Finished Jun 26 06:56:42 PM PDT 24
Peak memory 215224 kb
Host smart-8737b4e9-ca04-4bb0-bd95-e757e986616f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656847586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.656847586
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2932736214
Short name T350
Test name
Test status
Simulation time 2238538308 ps
CPU time 18.93 seconds
Started Jun 26 06:56:38 PM PDT 24
Finished Jun 26 06:57:01 PM PDT 24
Peak memory 251168 kb
Host smart-e77cd7b2-29bb-447d-a1f6-ca4b15054abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932736214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2932736214
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.15650739
Short name T371
Test name
Test status
Simulation time 188603514 ps
CPU time 13.27 seconds
Started Jun 26 06:56:41 PM PDT 24
Finished Jun 26 06:56:57 PM PDT 24
Peak memory 251036 kb
Host smart-b01680ef-ed05-4d80-a006-f31d688047e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15650739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.15650739
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2306419745
Short name T592
Test name
Test status
Simulation time 2419666638 ps
CPU time 60.99 seconds
Started Jun 26 06:57:06 PM PDT 24
Finished Jun 26 06:58:11 PM PDT 24
Peak memory 251276 kb
Host smart-67be04b9-7f4a-4a06-9a1e-0fb6ac02f42b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306419745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2306419745
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.958497483
Short name T740
Test name
Test status
Simulation time 13314851 ps
CPU time 1.03 seconds
Started Jun 26 06:56:37 PM PDT 24
Finished Jun 26 06:56:40 PM PDT 24
Peak memory 212204 kb
Host smart-a8cc1053-c374-4c07-b876-776d7a5b66d9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958497483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ct
rl_volatile_unlock_smoke.958497483
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.3169003526
Short name T78
Test name
Test status
Simulation time 87082488 ps
CPU time 0.97 seconds
Started Jun 26 06:57:04 PM PDT 24
Finished Jun 26 06:57:09 PM PDT 24
Peak memory 209308 kb
Host smart-e99645b4-66bd-4a1c-a066-3ab9d8198806
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169003526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.3169003526
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1374980920
Short name T720
Test name
Test status
Simulation time 211019580 ps
CPU time 9.89 seconds
Started Jun 26 06:57:04 PM PDT 24
Finished Jun 26 06:57:18 PM PDT 24
Peak memory 218500 kb
Host smart-0ef18a68-b2c8-42ce-be5f-1e2b573cd089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374980920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1374980920
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.3004456939
Short name T190
Test name
Test status
Simulation time 2849732702 ps
CPU time 16.26 seconds
Started Jun 26 06:57:05 PM PDT 24
Finished Jun 26 06:57:25 PM PDT 24
Peak memory 217984 kb
Host smart-4c8f3e93-7dc0-4dd1-89b7-3de04bfbed60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004456939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3004456939
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.4230965164
Short name T330
Test name
Test status
Simulation time 239560155 ps
CPU time 2.73 seconds
Started Jun 26 06:57:06 PM PDT 24
Finished Jun 26 06:57:13 PM PDT 24
Peak memory 218444 kb
Host smart-9bb10831-ed43-4528-8703-1ee4c81f8f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230965164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.4230965164
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.2883685693
Short name T658
Test name
Test status
Simulation time 492399322 ps
CPU time 13.5 seconds
Started Jun 26 06:57:04 PM PDT 24
Finished Jun 26 06:57:22 PM PDT 24
Peak memory 226236 kb
Host smart-c410b3e9-7326-4c79-964b-f7e331437a3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883685693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.2883685693
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.284453089
Short name T322
Test name
Test status
Simulation time 253468388 ps
CPU time 7.86 seconds
Started Jun 26 06:57:04 PM PDT 24
Finished Jun 26 06:57:16 PM PDT 24
Peak memory 218552 kb
Host smart-3850e3e0-00b9-4da9-af01-90cf3336043d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284453089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_di
gest.284453089
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.4205197713
Short name T833
Test name
Test status
Simulation time 474350893 ps
CPU time 8.83 seconds
Started Jun 26 06:57:06 PM PDT 24
Finished Jun 26 06:57:19 PM PDT 24
Peak memory 218460 kb
Host smart-027a9a7c-babd-4fc4-8a50-8f057e68c805
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205197713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
4205197713
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1270400717
Short name T498
Test name
Test status
Simulation time 3863127350 ps
CPU time 11.02 seconds
Started Jun 26 06:57:04 PM PDT 24
Finished Jun 26 06:57:19 PM PDT 24
Peak memory 218648 kb
Host smart-e7657e43-e359-4f62-80b4-10568f291469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270400717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1270400717
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.3900140790
Short name T523
Test name
Test status
Simulation time 90351690 ps
CPU time 2.16 seconds
Started Jun 26 06:57:02 PM PDT 24
Finished Jun 26 06:57:06 PM PDT 24
Peak memory 214516 kb
Host smart-45e2b8cb-cbea-450d-9bc1-fe891a6dde75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900140790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3900140790
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.664973108
Short name T500
Test name
Test status
Simulation time 1422720999 ps
CPU time 17.44 seconds
Started Jun 26 06:57:05 PM PDT 24
Finished Jun 26 06:57:26 PM PDT 24
Peak memory 251040 kb
Host smart-4c5e8049-623e-4d45-b35b-0d7f5c357ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664973108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.664973108
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.1953073148
Short name T472
Test name
Test status
Simulation time 587586088 ps
CPU time 9.56 seconds
Started Jun 26 06:57:03 PM PDT 24
Finished Jun 26 06:57:16 PM PDT 24
Peak memory 251116 kb
Host smart-686f34b8-7c60-4234-8b89-9be44fe04dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953073148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.1953073148
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.441947276
Short name T442
Test name
Test status
Simulation time 6528442487 ps
CPU time 193.06 seconds
Started Jun 26 06:57:05 PM PDT 24
Finished Jun 26 07:00:22 PM PDT 24
Peak memory 251168 kb
Host smart-dd7748f3-5dfa-46d8-9a58-878da16762ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441947276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.441947276
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3901953509
Short name T491
Test name
Test status
Simulation time 17513959 ps
CPU time 0.93 seconds
Started Jun 26 06:57:05 PM PDT 24
Finished Jun 26 06:57:10 PM PDT 24
Peak memory 209232 kb
Host smart-eee7bd80-e226-473b-9e5b-2e044c08adbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901953509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3901953509
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.103728419
Short name T490
Test name
Test status
Simulation time 1631047149 ps
CPU time 17.92 seconds
Started Jun 26 06:57:02 PM PDT 24
Finished Jun 26 06:57:22 PM PDT 24
Peak memory 218448 kb
Host smart-968b1912-ef84-4a56-8bf1-8b92daca0090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103728419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.103728419
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.760819156
Short name T340
Test name
Test status
Simulation time 222659541 ps
CPU time 6.53 seconds
Started Jun 26 06:57:02 PM PDT 24
Finished Jun 26 06:57:09 PM PDT 24
Peak memory 217556 kb
Host smart-4beb5104-d9ca-4f07-9c92-003530295fd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760819156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.760819156
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3024815522
Short name T269
Test name
Test status
Simulation time 66195863 ps
CPU time 2.42 seconds
Started Jun 26 06:57:04 PM PDT 24
Finished Jun 26 06:57:10 PM PDT 24
Peak memory 218408 kb
Host smart-ceed627b-5b19-4f86-97a4-e7fcbc6d62da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024815522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3024815522
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.760484642
Short name T623
Test name
Test status
Simulation time 1793097917 ps
CPU time 13.82 seconds
Started Jun 26 06:57:03 PM PDT 24
Finished Jun 26 06:57:20 PM PDT 24
Peak memory 219096 kb
Host smart-78cb9ac4-15ca-4e09-8403-2e114da9a3a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760484642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.760484642
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.2493196272
Short name T232
Test name
Test status
Simulation time 1364538311 ps
CPU time 26.43 seconds
Started Jun 26 06:57:05 PM PDT 24
Finished Jun 26 06:57:35 PM PDT 24
Peak memory 218532 kb
Host smart-6808de65-4e42-49f3-8fcd-42915ea505ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493196272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.2493196272
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.4052805355
Short name T585
Test name
Test status
Simulation time 616095171 ps
CPU time 11.09 seconds
Started Jun 26 06:57:02 PM PDT 24
Finished Jun 26 06:57:14 PM PDT 24
Peak memory 218412 kb
Host smart-61adea74-de44-4ed9-87f8-7fdb089add92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052805355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
4052805355
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.2726533329
Short name T869
Test name
Test status
Simulation time 89210597 ps
CPU time 1.97 seconds
Started Jun 26 06:57:06 PM PDT 24
Finished Jun 26 06:57:12 PM PDT 24
Peak memory 214504 kb
Host smart-9d4229e7-1d80-4d7b-bf4b-79887cacccdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726533329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2726533329
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.956208076
Short name T463
Test name
Test status
Simulation time 258372602 ps
CPU time 24.92 seconds
Started Jun 26 06:57:03 PM PDT 24
Finished Jun 26 06:57:32 PM PDT 24
Peak memory 251152 kb
Host smart-d92774b5-949f-434f-a136-1089a02c42d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956208076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.956208076
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.4109641070
Short name T243
Test name
Test status
Simulation time 302107641 ps
CPU time 3.46 seconds
Started Jun 26 06:57:05 PM PDT 24
Finished Jun 26 06:57:13 PM PDT 24
Peak memory 221564 kb
Host smart-0d14b55f-fd9d-4d36-8196-29b18bfd6280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109641070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.4109641070
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1516279232
Short name T822
Test name
Test status
Simulation time 97072554479 ps
CPU time 582.19 seconds
Started Jun 26 06:57:04 PM PDT 24
Finished Jun 26 07:06:50 PM PDT 24
Peak memory 251188 kb
Host smart-f1ad7f58-7d15-4bca-8360-69a144051795
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516279232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1516279232
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.28217013
Short name T173
Test name
Test status
Simulation time 14093101682 ps
CPU time 532.81 seconds
Started Jun 26 06:57:05 PM PDT 24
Finished Jun 26 07:06:02 PM PDT 24
Peak memory 268060 kb
Host smart-1d3ef405-23cd-42f5-838a-c6752b8c99d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=28217013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.28217013
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.470302708
Short name T261
Test name
Test status
Simulation time 22231828 ps
CPU time 0.84 seconds
Started Jun 26 06:57:04 PM PDT 24
Finished Jun 26 06:57:09 PM PDT 24
Peak memory 212028 kb
Host smart-ce5d61dd-8cd0-4e31-abec-7b610fd4b500
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470302708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ct
rl_volatile_unlock_smoke.470302708
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.252482677
Short name T803
Test name
Test status
Simulation time 471781054 ps
CPU time 1.32 seconds
Started Jun 26 06:57:07 PM PDT 24
Finished Jun 26 06:57:12 PM PDT 24
Peak memory 209168 kb
Host smart-e0239512-ef46-4e42-afd9-e770619c4c20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252482677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.252482677
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1334769931
Short name T691
Test name
Test status
Simulation time 1172655049 ps
CPU time 8.36 seconds
Started Jun 26 06:57:04 PM PDT 24
Finished Jun 26 06:57:16 PM PDT 24
Peak memory 218320 kb
Host smart-adf14c11-4fda-4ed7-8a49-9cea9b625fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334769931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1334769931
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.2463354627
Short name T443
Test name
Test status
Simulation time 591725522 ps
CPU time 3.89 seconds
Started Jun 26 06:57:04 PM PDT 24
Finished Jun 26 06:57:12 PM PDT 24
Peak memory 217296 kb
Host smart-c161be0a-37ec-4a27-a753-241d62a98a83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463354627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.2463354627
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.1300101567
Short name T437
Test name
Test status
Simulation time 326221753 ps
CPU time 3.12 seconds
Started Jun 26 06:57:07 PM PDT 24
Finished Jun 26 06:57:14 PM PDT 24
Peak memory 218392 kb
Host smart-04051eaa-8453-4572-a6dc-5edc17fd9ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300101567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1300101567
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.1230552423
Short name T403
Test name
Test status
Simulation time 489017078 ps
CPU time 22.09 seconds
Started Jun 26 06:57:03 PM PDT 24
Finished Jun 26 06:57:29 PM PDT 24
Peak memory 226200 kb
Host smart-66f78a7e-ce8f-40ef-a517-c7046ca81155
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230552423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.1230552423
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.161710909
Short name T39
Test name
Test status
Simulation time 907468673 ps
CPU time 12.55 seconds
Started Jun 26 06:57:04 PM PDT 24
Finished Jun 26 06:57:20 PM PDT 24
Peak memory 218480 kb
Host smart-326ec102-163f-4182-aae6-59b9bca63f3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161710909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di
gest.161710909
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3867519821
Short name T868
Test name
Test status
Simulation time 686250095 ps
CPU time 13.3 seconds
Started Jun 26 06:57:04 PM PDT 24
Finished Jun 26 06:57:21 PM PDT 24
Peak memory 218412 kb
Host smart-adedd05a-01c4-4485-b43e-fc4c0f6ec1fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867519821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3867519821
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.815973466
Short name T835
Test name
Test status
Simulation time 1683514611 ps
CPU time 11.43 seconds
Started Jun 26 06:57:05 PM PDT 24
Finished Jun 26 06:57:20 PM PDT 24
Peak memory 217396 kb
Host smart-0729d25a-ed01-424b-94cc-0f2ca288191d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815973466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.815973466
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.1519419965
Short name T182
Test name
Test status
Simulation time 52976838 ps
CPU time 1.57 seconds
Started Jun 26 06:57:02 PM PDT 24
Finished Jun 26 06:57:04 PM PDT 24
Peak memory 214232 kb
Host smart-e226fb77-d3ca-4e83-b743-9fc7abb95612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519419965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.1519419965
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.1235863565
Short name T341
Test name
Test status
Simulation time 2062525477 ps
CPU time 39.49 seconds
Started Jun 26 06:57:04 PM PDT 24
Finished Jun 26 06:57:48 PM PDT 24
Peak memory 251132 kb
Host smart-fbdccfaa-e878-4cb8-9e42-91823b260229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235863565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1235863565
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3381314446
Short name T775
Test name
Test status
Simulation time 56695527 ps
CPU time 5.63 seconds
Started Jun 26 06:57:04 PM PDT 24
Finished Jun 26 06:57:13 PM PDT 24
Peak memory 246856 kb
Host smart-93f9d99d-463f-49b1-8792-d0ad188596fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381314446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3381314446
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.1695752485
Short name T743
Test name
Test status
Simulation time 12379032085 ps
CPU time 75.78 seconds
Started Jun 26 06:57:05 PM PDT 24
Finished Jun 26 06:58:26 PM PDT 24
Peak memory 283940 kb
Host smart-0ecef43e-e7c0-40e5-b117-8b43f1a94cc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695752485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.1695752485
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.63634423
Short name T789
Test name
Test status
Simulation time 31065487785 ps
CPU time 321.78 seconds
Started Jun 26 06:57:05 PM PDT 24
Finished Jun 26 07:02:32 PM PDT 24
Peak memory 300448 kb
Host smart-84ff7bc9-48b1-422d-9276-72f90df7aa67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=63634423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.63634423
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2552014673
Short name T675
Test name
Test status
Simulation time 23044597 ps
CPU time 1.01 seconds
Started Jun 26 06:57:04 PM PDT 24
Finished Jun 26 06:57:09 PM PDT 24
Peak memory 212052 kb
Host smart-4324cee0-dec8-427f-aef4-869fa3066d2c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552014673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2552014673
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.3017007823
Short name T610
Test name
Test status
Simulation time 39789407 ps
CPU time 0.92 seconds
Started Jun 26 06:57:06 PM PDT 24
Finished Jun 26 06:57:11 PM PDT 24
Peak memory 209296 kb
Host smart-34e1a962-0f07-4e21-86a7-9a218d4cc8bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017007823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3017007823
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.3265523246
Short name T683
Test name
Test status
Simulation time 3804178452 ps
CPU time 13.44 seconds
Started Jun 26 06:57:07 PM PDT 24
Finished Jun 26 06:57:25 PM PDT 24
Peak memory 219192 kb
Host smart-49b266c1-cfa7-49f7-885f-caefa9ee4542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265523246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3265523246
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.3404176680
Short name T493
Test name
Test status
Simulation time 128943565 ps
CPU time 4 seconds
Started Jun 26 06:57:09 PM PDT 24
Finished Jun 26 06:57:16 PM PDT 24
Peak memory 217452 kb
Host smart-eda6aa24-19fb-4288-bb8c-5e5d3d39b97f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404176680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.3404176680
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.373607869
Short name T189
Test name
Test status
Simulation time 74924868 ps
CPU time 1.63 seconds
Started Jun 26 06:57:07 PM PDT 24
Finished Jun 26 06:57:13 PM PDT 24
Peak memory 218384 kb
Host smart-101f6bb7-e973-46e5-a5a6-eacbfb37334c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373607869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.373607869
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.1451620708
Short name T389
Test name
Test status
Simulation time 1508061358 ps
CPU time 10.36 seconds
Started Jun 26 06:57:06 PM PDT 24
Finished Jun 26 06:57:21 PM PDT 24
Peak memory 218448 kb
Host smart-cf5aca1a-d588-4531-a011-c90ae4bc263b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451620708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.1451620708
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.828486104
Short name T256
Test name
Test status
Simulation time 505368287 ps
CPU time 15.31 seconds
Started Jun 26 06:57:08 PM PDT 24
Finished Jun 26 06:57:27 PM PDT 24
Peak memory 218420 kb
Host smart-52e5f468-965c-4793-ae72-aad9b50d4584
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828486104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.828486104
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.685894253
Short name T18
Test name
Test status
Simulation time 991481735 ps
CPU time 17.64 seconds
Started Jun 26 06:57:09 PM PDT 24
Finished Jun 26 06:57:29 PM PDT 24
Peak memory 226256 kb
Host smart-8e19674b-d49b-4318-86e7-5822b469ff10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685894253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.685894253
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.339822777
Short name T807
Test name
Test status
Simulation time 423710270 ps
CPU time 8.88 seconds
Started Jun 26 06:57:09 PM PDT 24
Finished Jun 26 06:57:21 PM PDT 24
Peak memory 226252 kb
Host smart-6378c348-92e9-4235-a685-f34daccf68b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339822777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.339822777
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.906171899
Short name T73
Test name
Test status
Simulation time 84646542 ps
CPU time 2.7 seconds
Started Jun 26 06:57:04 PM PDT 24
Finished Jun 26 06:57:12 PM PDT 24
Peak memory 214588 kb
Host smart-ebfa6bff-fb24-432d-9c13-faba03f9e2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906171899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.906171899
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.4022289140
Short name T250
Test name
Test status
Simulation time 193122166 ps
CPU time 16.53 seconds
Started Jun 26 06:57:03 PM PDT 24
Finished Jun 26 06:57:23 PM PDT 24
Peak memory 251116 kb
Host smart-f725f38d-b589-42a8-b9bb-d7863ceca018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022289140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.4022289140
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.2274687236
Short name T366
Test name
Test status
Simulation time 425545960 ps
CPU time 8.77 seconds
Started Jun 26 06:57:09 PM PDT 24
Finished Jun 26 06:57:21 PM PDT 24
Peak memory 251136 kb
Host smart-a971c15a-30d3-432d-9c53-29d004cbee92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274687236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2274687236
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3589174158
Short name T81
Test name
Test status
Simulation time 71790594768 ps
CPU time 358.25 seconds
Started Jun 26 06:56:48 PM PDT 24
Finished Jun 26 07:02:47 PM PDT 24
Peak memory 267800 kb
Host smart-06d440f5-8b2a-45c4-afd5-d0d757890b7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589174158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3589174158
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3370373295
Short name T696
Test name
Test status
Simulation time 66057713 ps
CPU time 0.85 seconds
Started Jun 26 06:57:04 PM PDT 24
Finished Jun 26 06:57:09 PM PDT 24
Peak memory 212180 kb
Host smart-031281c2-f5a4-49e7-b05c-96c5b62551d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370373295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3370373295
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.2718550202
Short name T858
Test name
Test status
Simulation time 20692394 ps
CPU time 0.93 seconds
Started Jun 26 06:57:21 PM PDT 24
Finished Jun 26 06:57:24 PM PDT 24
Peak memory 209152 kb
Host smart-d2e978ee-a8ad-4d5c-976b-58fcbcb8c209
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718550202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.2718550202
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3102453771
Short name T616
Test name
Test status
Simulation time 1413245772 ps
CPU time 15.63 seconds
Started Jun 26 06:57:19 PM PDT 24
Finished Jun 26 06:57:37 PM PDT 24
Peak memory 218452 kb
Host smart-e652a9a1-e804-4831-8be9-53214333bdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102453771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3102453771
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.2243860807
Short name T32
Test name
Test status
Simulation time 197768411 ps
CPU time 2.86 seconds
Started Jun 26 06:57:26 PM PDT 24
Finished Jun 26 06:57:32 PM PDT 24
Peak memory 217324 kb
Host smart-e4e35769-ab5b-4484-9578-096856cc58d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243860807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.2243860807
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.192548404
Short name T531
Test name
Test status
Simulation time 103932153 ps
CPU time 4.05 seconds
Started Jun 26 06:57:07 PM PDT 24
Finished Jun 26 06:57:15 PM PDT 24
Peak memory 222944 kb
Host smart-d6f81cf2-027c-4340-b441-a81f536bc0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192548404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.192548404
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.676390432
Short name T816
Test name
Test status
Simulation time 849160112 ps
CPU time 8.84 seconds
Started Jun 26 06:57:19 PM PDT 24
Finished Jun 26 06:57:30 PM PDT 24
Peak memory 219100 kb
Host smart-f64e702e-7821-4b33-a6f0-3a60e79e22a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676390432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.676390432
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2047955423
Short name T314
Test name
Test status
Simulation time 538973479 ps
CPU time 11.5 seconds
Started Jun 26 06:57:24 PM PDT 24
Finished Jun 26 06:57:39 PM PDT 24
Peak memory 218440 kb
Host smart-7f68abbd-b6d9-419b-a65e-236e7b5aa807
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047955423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.2047955423
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.4234058434
Short name T782
Test name
Test status
Simulation time 361947575 ps
CPU time 11.14 seconds
Started Jun 26 06:57:20 PM PDT 24
Finished Jun 26 06:57:34 PM PDT 24
Peak memory 226368 kb
Host smart-e60fc892-4bdc-4558-acfc-adee730918a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234058434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
4234058434
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.2920100454
Short name T306
Test name
Test status
Simulation time 224917258 ps
CPU time 9.55 seconds
Started Jun 26 06:57:20 PM PDT 24
Finished Jun 26 06:57:31 PM PDT 24
Peak memory 218504 kb
Host smart-0a8bc244-dd37-46dc-ab06-c62427ae6937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920100454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.2920100454
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.3355699451
Short name T351
Test name
Test status
Simulation time 81224700 ps
CPU time 3.88 seconds
Started Jun 26 06:57:06 PM PDT 24
Finished Jun 26 06:57:14 PM PDT 24
Peak memory 217944 kb
Host smart-bc3c60dd-90ff-4477-9cb9-ed9eddb4370b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355699451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3355699451
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.277919737
Short name T412
Test name
Test status
Simulation time 150011209 ps
CPU time 23.07 seconds
Started Jun 26 06:57:07 PM PDT 24
Finished Jun 26 06:57:34 PM PDT 24
Peak memory 251132 kb
Host smart-6d248609-0a57-49f0-b8f8-756143e4b5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277919737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.277919737
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.3660796722
Short name T10
Test name
Test status
Simulation time 429585639 ps
CPU time 7.8 seconds
Started Jun 26 06:57:07 PM PDT 24
Finished Jun 26 06:57:19 PM PDT 24
Peak memory 250928 kb
Host smart-4976e45e-e77f-4c63-81d2-e1524fff6902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660796722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3660796722
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2385669861
Short name T482
Test name
Test status
Simulation time 4053413493 ps
CPU time 74.47 seconds
Started Jun 26 06:57:22 PM PDT 24
Finished Jun 26 06:58:38 PM PDT 24
Peak memory 220500 kb
Host smart-2f460648-840c-4ebf-b0df-0748c1c2880d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385669861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2385669861
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.3696859172
Short name T150
Test name
Test status
Simulation time 141040888090 ps
CPU time 847.28 seconds
Started Jun 26 06:57:22 PM PDT 24
Finished Jun 26 07:11:32 PM PDT 24
Peak memory 464300 kb
Host smart-e2303872-4ea2-4c72-80cf-f0c729990038
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3696859172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.3696859172
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2803648549
Short name T622
Test name
Test status
Simulation time 17141264 ps
CPU time 1.03 seconds
Started Jun 26 06:57:07 PM PDT 24
Finished Jun 26 06:57:12 PM PDT 24
Peak memory 212044 kb
Host smart-d19d2bf9-cd3b-4bfc-9097-90af3b79879d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803648549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.2803648549
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3779852499
Short name T665
Test name
Test status
Simulation time 58209291 ps
CPU time 0.85 seconds
Started Jun 26 06:52:39 PM PDT 24
Finished Jun 26 06:52:40 PM PDT 24
Peak memory 209040 kb
Host smart-022b2c51-8e2d-4985-b338-7e84061eb4cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779852499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3779852499
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.3317097563
Short name T429
Test name
Test status
Simulation time 20451014 ps
CPU time 0.89 seconds
Started Jun 26 06:52:40 PM PDT 24
Finished Jun 26 06:52:42 PM PDT 24
Peak memory 209020 kb
Host smart-2d347692-f1ed-492a-9881-415a7ab287dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317097563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.3317097563
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.1868330679
Short name T618
Test name
Test status
Simulation time 347580612 ps
CPU time 14.15 seconds
Started Jun 26 06:52:38 PM PDT 24
Finished Jun 26 06:52:53 PM PDT 24
Peak memory 218512 kb
Host smart-e8e8c3bc-5f87-498c-b120-ae86d4a2564b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868330679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1868330679
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.4182349888
Short name T8
Test name
Test status
Simulation time 719045966 ps
CPU time 5.55 seconds
Started Jun 26 06:52:38 PM PDT 24
Finished Jun 26 06:52:45 PM PDT 24
Peak memory 217536 kb
Host smart-4868c9a4-2086-463a-8a27-aaae46bb7983
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182349888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.4182349888
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1112914242
Short name T431
Test name
Test status
Simulation time 18724732123 ps
CPU time 41.1 seconds
Started Jun 26 06:52:36 PM PDT 24
Finished Jun 26 06:53:18 PM PDT 24
Peak memory 219160 kb
Host smart-f4fe0593-1d78-4a28-b51c-758ec85ef371
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112914242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1112914242
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.4148296634
Short name T345
Test name
Test status
Simulation time 535312400 ps
CPU time 7.08 seconds
Started Jun 26 06:52:38 PM PDT 24
Finished Jun 26 06:52:46 PM PDT 24
Peak memory 217724 kb
Host smart-61da9184-6b26-4a2e-979f-2cef00231610
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148296634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.4
148296634
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.735598212
Short name T347
Test name
Test status
Simulation time 567805711 ps
CPU time 4.75 seconds
Started Jun 26 06:52:44 PM PDT 24
Finished Jun 26 06:52:49 PM PDT 24
Peak memory 218392 kb
Host smart-e2005ec9-46d3-44cd-b0ec-3313a6d2076d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735598212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
prog_failure.735598212
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1507717566
Short name T535
Test name
Test status
Simulation time 885771401 ps
CPU time 12.32 seconds
Started Jun 26 06:52:45 PM PDT 24
Finished Jun 26 06:52:58 PM PDT 24
Peak memory 217916 kb
Host smart-e62b98e1-7484-4870-8098-b431a706e49b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507717566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.1507717566
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3139871131
Short name T67
Test name
Test status
Simulation time 714286976 ps
CPU time 8.08 seconds
Started Jun 26 06:52:40 PM PDT 24
Finished Jun 26 06:52:49 PM PDT 24
Peak memory 217932 kb
Host smart-13df8108-cee5-4e5a-9ac6-ee0c7bf1e870
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139871131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3139871131
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2623584769
Short name T297
Test name
Test status
Simulation time 2634655532 ps
CPU time 91.57 seconds
Started Jun 26 06:52:41 PM PDT 24
Finished Jun 26 06:54:14 PM PDT 24
Peak memory 267508 kb
Host smart-526c1bc2-953c-4c1c-883d-ee8986a2121f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623584769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2623584769
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.1066745232
Short name T814
Test name
Test status
Simulation time 1416613875 ps
CPU time 16.38 seconds
Started Jun 26 06:52:38 PM PDT 24
Finished Jun 26 06:52:55 PM PDT 24
Peak memory 246332 kb
Host smart-a882d35f-2bea-49d4-bae8-f3a4234bce80
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066745232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.1066745232
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.517329505
Short name T179
Test name
Test status
Simulation time 49034673 ps
CPU time 1.74 seconds
Started Jun 26 06:52:41 PM PDT 24
Finished Jun 26 06:52:44 PM PDT 24
Peak memory 218436 kb
Host smart-672aacb5-1975-45d2-ab2f-febcc92bbdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517329505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.517329505
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.416282489
Short name T24
Test name
Test status
Simulation time 3853790057 ps
CPU time 19.77 seconds
Started Jun 26 06:52:37 PM PDT 24
Finished Jun 26 06:52:57 PM PDT 24
Peak memory 215072 kb
Host smart-6e7f50f3-aee2-4086-93a7-433acc630d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416282489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.416282489
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1514616666
Short name T574
Test name
Test status
Simulation time 1664229990 ps
CPU time 24.41 seconds
Started Jun 26 06:52:38 PM PDT 24
Finished Jun 26 06:53:04 PM PDT 24
Peak memory 226224 kb
Host smart-63946d09-9a72-4970-afeb-f3dd4a0310f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514616666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1514616666
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3833565153
Short name T779
Test name
Test status
Simulation time 800183389 ps
CPU time 21.08 seconds
Started Jun 26 06:52:37 PM PDT 24
Finished Jun 26 06:52:59 PM PDT 24
Peak memory 218472 kb
Host smart-cc8fa4fa-d463-4fb5-8b11-4833edd7ff01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833565153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.3833565153
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.2143406003
Short name T411
Test name
Test status
Simulation time 552352096 ps
CPU time 6.92 seconds
Started Jun 26 06:52:38 PM PDT 24
Finished Jun 26 06:52:46 PM PDT 24
Peak memory 218636 kb
Host smart-74b3500a-c3f2-4b52-b081-df0dfaaf81a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143406003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.2143406003
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.4254809967
Short name T376
Test name
Test status
Simulation time 41980857 ps
CPU time 1.67 seconds
Started Jun 26 06:52:27 PM PDT 24
Finished Jun 26 06:52:30 PM PDT 24
Peak memory 222752 kb
Host smart-89bfa4e9-d34d-4927-8511-549345a4d82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254809967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.4254809967
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.3059955225
Short name T830
Test name
Test status
Simulation time 282763348 ps
CPU time 25.54 seconds
Started Jun 26 06:52:27 PM PDT 24
Finished Jun 26 06:52:54 PM PDT 24
Peak memory 251120 kb
Host smart-f5e2600a-d5db-40df-92a5-d18d5eebc0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059955225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3059955225
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.4155474334
Short name T544
Test name
Test status
Simulation time 412566278 ps
CPU time 6.83 seconds
Started Jun 26 06:52:27 PM PDT 24
Finished Jun 26 06:52:36 PM PDT 24
Peak memory 246976 kb
Host smart-ba130360-babe-4036-8868-18a9f20a7645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155474334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.4155474334
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.622195041
Short name T86
Test name
Test status
Simulation time 31175360721 ps
CPU time 150.54 seconds
Started Jun 26 06:52:39 PM PDT 24
Finished Jun 26 06:55:10 PM PDT 24
Peak memory 226276 kb
Host smart-2cafad99-6e5b-4e60-a5ec-9741185bcdb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622195041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.622195041
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2211507977
Short name T244
Test name
Test status
Simulation time 16557616 ps
CPU time 0.95 seconds
Started Jun 26 06:52:26 PM PDT 24
Finished Jun 26 06:52:29 PM PDT 24
Peak memory 212156 kb
Host smart-eb9c3cb7-cf0c-4e2c-bf97-efff7ef923c7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211507977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.2211507977
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.1722711900
Short name T457
Test name
Test status
Simulation time 31032639 ps
CPU time 1.15 seconds
Started Jun 26 06:52:52 PM PDT 24
Finished Jun 26 06:52:54 PM PDT 24
Peak memory 209192 kb
Host smart-b40a8654-bf1f-4cc7-9dc7-38fd43addd33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722711900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1722711900
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.351075581
Short name T210
Test name
Test status
Simulation time 33246829 ps
CPU time 0.88 seconds
Started Jun 26 06:52:50 PM PDT 24
Finished Jun 26 06:52:52 PM PDT 24
Peak memory 209172 kb
Host smart-2894009a-bcfd-42a8-b0e9-c71e59d33d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351075581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.351075581
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.2537865428
Short name T50
Test name
Test status
Simulation time 1331042543 ps
CPU time 16.33 seconds
Started Jun 26 06:52:49 PM PDT 24
Finished Jun 26 06:53:06 PM PDT 24
Peak memory 226256 kb
Host smart-ff9fe684-d3cf-4aaa-a7c3-9389ecf29bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537865428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.2537865428
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.591809514
Short name T337
Test name
Test status
Simulation time 192388081 ps
CPU time 3 seconds
Started Jun 26 06:52:50 PM PDT 24
Finished Jun 26 06:52:54 PM PDT 24
Peak memory 217332 kb
Host smart-667ff791-a99f-46a0-b8fc-d6d8bc4d8869
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591809514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.591809514
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.859700080
Short name T781
Test name
Test status
Simulation time 15346521973 ps
CPU time 36.6 seconds
Started Jun 26 06:52:50 PM PDT 24
Finished Jun 26 06:53:28 PM PDT 24
Peak memory 218504 kb
Host smart-9f69b792-1700-4be9-bc2c-382ee1e049d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859700080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_err
ors.859700080
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.3786956282
Short name T796
Test name
Test status
Simulation time 476932906 ps
CPU time 7.22 seconds
Started Jun 26 06:52:50 PM PDT 24
Finished Jun 26 06:52:59 PM PDT 24
Peak memory 217996 kb
Host smart-e57839f0-6e3d-44a8-9cc4-df818b44ad68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786956282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.3
786956282
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2871668222
Short name T872
Test name
Test status
Simulation time 8862242208 ps
CPU time 20.83 seconds
Started Jun 26 06:52:50 PM PDT 24
Finished Jun 26 06:53:12 PM PDT 24
Peak memory 218524 kb
Host smart-96fc27c5-28af-42e0-b443-db22c9bf2d11
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871668222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2871668222
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1670316116
Short name T307
Test name
Test status
Simulation time 3780029324 ps
CPU time 15.44 seconds
Started Jun 26 06:52:49 PM PDT 24
Finished Jun 26 06:53:06 PM PDT 24
Peak memory 217976 kb
Host smart-31bb2981-8eb1-4752-964d-e12d37fc8afc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670316116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1670316116
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.1375283972
Short name T656
Test name
Test status
Simulation time 4309024348 ps
CPU time 7 seconds
Started Jun 26 06:52:52 PM PDT 24
Finished Jun 26 06:53:00 PM PDT 24
Peak memory 217988 kb
Host smart-3a17cdff-005b-4427-998c-32ac3621e9e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375283972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
1375283972
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.625923332
Short name T760
Test name
Test status
Simulation time 2705797946 ps
CPU time 58.27 seconds
Started Jun 26 06:52:50 PM PDT 24
Finished Jun 26 06:53:50 PM PDT 24
Peak memory 251196 kb
Host smart-8ea32100-2b03-4c19-a9ca-99ace8051d67
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625923332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_state_failure.625923332
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2725435597
Short name T466
Test name
Test status
Simulation time 1217191495 ps
CPU time 18.92 seconds
Started Jun 26 06:52:49 PM PDT 24
Finished Jun 26 06:53:09 PM PDT 24
Peak memory 251120 kb
Host smart-671da6d1-3b5f-4c1f-9d6f-c08ffdb92901
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725435597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.2725435597
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.4216055952
Short name T626
Test name
Test status
Simulation time 256718408 ps
CPU time 3.33 seconds
Started Jun 26 06:52:49 PM PDT 24
Finished Jun 26 06:52:54 PM PDT 24
Peak memory 222704 kb
Host smart-75d7310d-084e-4486-a18a-1cd77416c269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216055952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.4216055952
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.791643142
Short name T733
Test name
Test status
Simulation time 1572638863 ps
CPU time 14.9 seconds
Started Jun 26 06:52:50 PM PDT 24
Finished Jun 26 06:53:07 PM PDT 24
Peak memory 217928 kb
Host smart-900c227a-d4b5-4a21-9a46-6576b44e47c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791643142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.791643142
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.3744525103
Short name T448
Test name
Test status
Simulation time 244708202 ps
CPU time 11.47 seconds
Started Jun 26 06:52:52 PM PDT 24
Finished Jun 26 06:53:05 PM PDT 24
Peak memory 226240 kb
Host smart-56a02ecf-4397-4a4d-838e-b6390dff5e4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744525103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3744525103
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.3132249528
Short name T839
Test name
Test status
Simulation time 957168548 ps
CPU time 7.8 seconds
Started Jun 26 06:52:50 PM PDT 24
Finished Jun 26 06:52:59 PM PDT 24
Peak memory 218480 kb
Host smart-2ec37d13-ce2b-45c1-9887-3a6f6950ca89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132249528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.3132249528
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.254154344
Short name T649
Test name
Test status
Simulation time 390763700 ps
CPU time 13.78 seconds
Started Jun 26 06:52:51 PM PDT 24
Finished Jun 26 06:53:06 PM PDT 24
Peak memory 218364 kb
Host smart-7bf6e630-80fe-4683-91e4-0d1934a86337
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254154344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.254154344
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.3637529818
Short name T739
Test name
Test status
Simulation time 459781437 ps
CPU time 7.17 seconds
Started Jun 26 06:52:49 PM PDT 24
Finished Jun 26 06:52:57 PM PDT 24
Peak memory 218528 kb
Host smart-f6431088-28f6-4c7e-9903-2dcdd0646d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637529818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3637529818
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.468706342
Short name T424
Test name
Test status
Simulation time 83441931 ps
CPU time 3.18 seconds
Started Jun 26 06:52:42 PM PDT 24
Finished Jun 26 06:52:46 PM PDT 24
Peak memory 217880 kb
Host smart-73822ffa-6246-4b55-b2f4-0e4935fd5ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468706342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.468706342
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.2858267618
Short name T348
Test name
Test status
Simulation time 822405618 ps
CPU time 23.78 seconds
Started Jun 26 06:52:39 PM PDT 24
Finished Jun 26 06:53:04 PM PDT 24
Peak memory 247656 kb
Host smart-9ca609c7-e14b-428a-a041-85bffe7c54e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858267618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.2858267618
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.1684233359
Short name T363
Test name
Test status
Simulation time 277412704 ps
CPU time 8.31 seconds
Started Jun 26 06:52:42 PM PDT 24
Finished Jun 26 06:52:51 PM PDT 24
Peak memory 251076 kb
Host smart-57a8b648-9cbc-41d4-b10b-4560ed504603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684233359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.1684233359
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.4142940568
Short name T420
Test name
Test status
Simulation time 3215001345 ps
CPU time 30.93 seconds
Started Jun 26 06:52:51 PM PDT 24
Finished Jun 26 06:53:23 PM PDT 24
Peak memory 251136 kb
Host smart-6e5cc67d-52c2-4dfb-9e59-f1a0a1ae9485
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142940568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.4142940568
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.588142318
Short name T844
Test name
Test status
Simulation time 30174522 ps
CPU time 1.17 seconds
Started Jun 26 06:52:39 PM PDT 24
Finished Jun 26 06:52:41 PM PDT 24
Peak memory 213144 kb
Host smart-5df53715-13a2-4c28-a8dd-cad329ddea1b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588142318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctr
l_volatile_unlock_smoke.588142318
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.3571383082
Short name T645
Test name
Test status
Simulation time 18696938 ps
CPU time 0.98 seconds
Started Jun 26 06:53:05 PM PDT 24
Finished Jun 26 06:53:08 PM PDT 24
Peak memory 209340 kb
Host smart-30730b99-6e63-4a97-bd21-f43afa48859a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571383082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.3571383082
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3800055788
Short name T832
Test name
Test status
Simulation time 14217840 ps
CPU time 0.81 seconds
Started Jun 26 06:52:52 PM PDT 24
Finished Jun 26 06:52:54 PM PDT 24
Peak memory 208928 kb
Host smart-cd8e3a8a-4883-4cb3-98ab-e24d3ab5d93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800055788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3800055788
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1012504085
Short name T668
Test name
Test status
Simulation time 1191481548 ps
CPU time 13.63 seconds
Started Jun 26 06:52:51 PM PDT 24
Finished Jun 26 06:53:06 PM PDT 24
Peak memory 218376 kb
Host smart-072ac83c-93e5-49f9-8d1c-37e8266ce464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012504085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1012504085
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.1196602785
Short name T413
Test name
Test status
Simulation time 1392013368 ps
CPU time 18.55 seconds
Started Jun 26 06:53:05 PM PDT 24
Finished Jun 26 06:53:25 PM PDT 24
Peak memory 217392 kb
Host smart-5d103a1c-ae6f-4eb8-a557-fff50bae560b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196602785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.1196602785
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.4057724161
Short name T93
Test name
Test status
Simulation time 6890685392 ps
CPU time 44.87 seconds
Started Jun 26 06:53:02 PM PDT 24
Finished Jun 26 06:53:49 PM PDT 24
Peak memory 226292 kb
Host smart-1181983b-5b8d-4e5b-a326-e599065ad900
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057724161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.4057724161
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.1813604826
Short name T862
Test name
Test status
Simulation time 128779605 ps
CPU time 2.51 seconds
Started Jun 26 06:53:01 PM PDT 24
Finished Jun 26 06:53:05 PM PDT 24
Peak memory 217992 kb
Host smart-7efbf51a-68df-4bc3-9061-4d32e19ea26e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813604826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.1
813604826
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.4234839968
Short name T502
Test name
Test status
Simulation time 4141979618 ps
CPU time 8.22 seconds
Started Jun 26 06:53:00 PM PDT 24
Finished Jun 26 06:53:09 PM PDT 24
Peak memory 218504 kb
Host smart-64e53108-12dd-492f-a3e8-f4d1f53d48ed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234839968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.4234839968
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.323825420
Short name T342
Test name
Test status
Simulation time 2903820058 ps
CPU time 19.1 seconds
Started Jun 26 06:53:05 PM PDT 24
Finished Jun 26 06:53:26 PM PDT 24
Peak memory 217940 kb
Host smart-2fd42290-9606-40d6-a881-d0ecc0fbca1b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323825420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.323825420
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1016552434
Short name T439
Test name
Test status
Simulation time 185662797 ps
CPU time 1.43 seconds
Started Jun 26 06:52:58 PM PDT 24
Finished Jun 26 06:53:00 PM PDT 24
Peak memory 217224 kb
Host smart-e6eaa031-7637-4284-a7c6-38def6f21d11
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016552434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1016552434
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.3064141474
Short name T650
Test name
Test status
Simulation time 6115730753 ps
CPU time 44.44 seconds
Started Jun 26 06:53:01 PM PDT 24
Finished Jun 26 06:53:47 PM PDT 24
Peak memory 276980 kb
Host smart-83fb4405-3863-47c9-ba66-d4f64b2de26a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064141474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.3064141474
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.3618034383
Short name T783
Test name
Test status
Simulation time 437051837 ps
CPU time 11.54 seconds
Started Jun 26 06:53:02 PM PDT 24
Finished Jun 26 06:53:15 PM PDT 24
Peak memory 250728 kb
Host smart-4563ecb0-661d-4f7d-9c39-2b82bedf44dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618034383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.3618034383
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1837340850
Short name T241
Test name
Test status
Simulation time 140400154 ps
CPU time 3.2 seconds
Started Jun 26 06:52:51 PM PDT 24
Finished Jun 26 06:52:55 PM PDT 24
Peak memory 222632 kb
Host smart-9d2f5e85-d37f-4c10-86d2-a9f2714be296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837340850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1837340850
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.2432663191
Short name T91
Test name
Test status
Simulation time 783406552 ps
CPU time 7.76 seconds
Started Jun 26 06:52:52 PM PDT 24
Finished Jun 26 06:53:01 PM PDT 24
Peak memory 217888 kb
Host smart-753f1833-d114-446e-b139-073864993550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432663191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.2432663191
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.2493487717
Short name T343
Test name
Test status
Simulation time 1209186914 ps
CPU time 11.92 seconds
Started Jun 26 06:53:06 PM PDT 24
Finished Jun 26 06:53:19 PM PDT 24
Peak memory 219308 kb
Host smart-3ef9ee3e-207f-49ed-bbaa-eac705f2a5e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493487717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2493487717
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.900908602
Short name T16
Test name
Test status
Simulation time 1922998683 ps
CPU time 16.56 seconds
Started Jun 26 06:53:03 PM PDT 24
Finished Jun 26 06:53:21 PM PDT 24
Peak memory 218376 kb
Host smart-81a3fee9-a068-4bbb-923d-d31851fae9df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900908602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dig
est.900908602
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.3630690808
Short name T853
Test name
Test status
Simulation time 2176697237 ps
CPU time 16.94 seconds
Started Jun 26 06:53:02 PM PDT 24
Finished Jun 26 06:53:20 PM PDT 24
Peak memory 226292 kb
Host smart-1708ee6c-f14d-46bd-ab94-4cce3bd0aa42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630690808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.3
630690808
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.1795641202
Short name T323
Test name
Test status
Simulation time 1186327994 ps
CPU time 7.14 seconds
Started Jun 26 06:52:56 PM PDT 24
Finished Jun 26 06:53:04 PM PDT 24
Peak memory 218516 kb
Host smart-d3cf0810-c231-43be-8f99-d133d6adcca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795641202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1795641202
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1225578260
Short name T64
Test name
Test status
Simulation time 239603059 ps
CPU time 2.94 seconds
Started Jun 26 06:52:58 PM PDT 24
Finished Jun 26 06:53:01 PM PDT 24
Peak memory 214508 kb
Host smart-2272bd31-99da-4345-b04a-eed9c512073c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225578260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1225578260
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1320034163
Short name T316
Test name
Test status
Simulation time 185263954 ps
CPU time 20.71 seconds
Started Jun 26 06:52:52 PM PDT 24
Finished Jun 26 06:53:14 PM PDT 24
Peak memory 251020 kb
Host smart-b6f61cb0-d222-4576-8358-96dbdb51b8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320034163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1320034163
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.4161508966
Short name T603
Test name
Test status
Simulation time 289508929 ps
CPU time 8.1 seconds
Started Jun 26 06:52:52 PM PDT 24
Finished Jun 26 06:53:01 PM PDT 24
Peak memory 251020 kb
Host smart-05f04447-c674-4839-b4a2-5d236fe03920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161508966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.4161508966
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.3926944743
Short name T619
Test name
Test status
Simulation time 10313904878 ps
CPU time 214.28 seconds
Started Jun 26 06:53:02 PM PDT 24
Finished Jun 26 06:56:38 PM PDT 24
Peak memory 277104 kb
Host smart-a463bd98-bd90-4ee6-bf6f-65efba0284ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926944743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.3926944743
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2488222238
Short name T507
Test name
Test status
Simulation time 47820345 ps
CPU time 0.89 seconds
Started Jun 26 06:52:50 PM PDT 24
Finished Jun 26 06:52:53 PM PDT 24
Peak memory 212184 kb
Host smart-fe948e72-64df-45bb-b1d0-2491e3e806bb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488222238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.2488222238
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.884217686
Short name T632
Test name
Test status
Simulation time 64785561 ps
CPU time 0.92 seconds
Started Jun 26 06:53:17 PM PDT 24
Finished Jun 26 06:53:20 PM PDT 24
Peak memory 209244 kb
Host smart-fc42dc45-4ea2-4410-a947-376c6199da2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884217686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.884217686
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.1931213613
Short name T216
Test name
Test status
Simulation time 390920134 ps
CPU time 13.66 seconds
Started Jun 26 06:53:03 PM PDT 24
Finished Jun 26 06:53:19 PM PDT 24
Peak memory 226224 kb
Host smart-5ac04fca-0294-4335-8845-0f22905ef4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931213613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1931213613
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1994864020
Short name T692
Test name
Test status
Simulation time 1838231146 ps
CPU time 5.64 seconds
Started Jun 26 06:53:01 PM PDT 24
Finished Jun 26 06:53:08 PM PDT 24
Peak memory 217912 kb
Host smart-92bd4ec7-9cdc-4052-9b24-ba445545d06a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994864020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1994864020
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1343114531
Short name T516
Test name
Test status
Simulation time 2960585024 ps
CPU time 53.58 seconds
Started Jun 26 06:53:02 PM PDT 24
Finished Jun 26 06:53:57 PM PDT 24
Peak memory 226312 kb
Host smart-be9814d3-42e7-48e6-8555-f62d9f531e86
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343114531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1343114531
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2193084587
Short name T292
Test name
Test status
Simulation time 214648813 ps
CPU time 6.59 seconds
Started Jun 26 06:53:17 PM PDT 24
Finished Jun 26 06:53:25 PM PDT 24
Peak memory 217768 kb
Host smart-c5813e9a-06f9-418d-adce-93bc8dc29633
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193084587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
193084587
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3163237299
Short name T727
Test name
Test status
Simulation time 931517457 ps
CPU time 13.97 seconds
Started Jun 26 06:53:01 PM PDT 24
Finished Jun 26 06:53:16 PM PDT 24
Peak memory 218444 kb
Host smart-42bce3d4-5df4-4b35-bf37-71a1d5c8d9a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163237299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3163237299
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.4042381301
Short name T527
Test name
Test status
Simulation time 3377402621 ps
CPU time 30.41 seconds
Started Jun 26 06:53:16 PM PDT 24
Finished Jun 26 06:53:48 PM PDT 24
Peak memory 218048 kb
Host smart-21da3f42-c81d-4451-8be6-218ed4b5b5b2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042381301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.4042381301
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2360435305
Short name T407
Test name
Test status
Simulation time 718579923 ps
CPU time 5.79 seconds
Started Jun 26 06:53:01 PM PDT 24
Finished Jun 26 06:53:08 PM PDT 24
Peak memory 217904 kb
Host smart-58c8ef29-d7c2-488f-b69d-86f7b45b1bbf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360435305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2360435305
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.477582835
Short name T473
Test name
Test status
Simulation time 6936775639 ps
CPU time 59.28 seconds
Started Jun 26 06:53:06 PM PDT 24
Finished Jun 26 06:54:07 PM PDT 24
Peak memory 246172 kb
Host smart-cb4a4f60-4694-4251-a0e4-8b32deb5f1d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477582835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_state_failure.477582835
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3422028126
Short name T465
Test name
Test status
Simulation time 322207169 ps
CPU time 9.55 seconds
Started Jun 26 06:53:02 PM PDT 24
Finished Jun 26 06:53:13 PM PDT 24
Peak memory 246464 kb
Host smart-087249e3-b311-49bb-a955-3c4cf3ec6058
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422028126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.3422028126
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2679922609
Short name T852
Test name
Test status
Simulation time 147209973 ps
CPU time 2.72 seconds
Started Jun 26 06:53:01 PM PDT 24
Finished Jun 26 06:53:04 PM PDT 24
Peak memory 218328 kb
Host smart-c3687de4-1af7-4dd0-b8aa-be9c57b15e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679922609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2679922609
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3200890865
Short name T805
Test name
Test status
Simulation time 1313084581 ps
CPU time 18.48 seconds
Started Jun 26 06:53:03 PM PDT 24
Finished Jun 26 06:53:23 PM PDT 24
Peak memory 214944 kb
Host smart-d0ae0814-e83e-4e3b-95b2-636225740b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200890865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3200890865
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.557995259
Short name T107
Test name
Test status
Simulation time 413059079 ps
CPU time 18.14 seconds
Started Jun 26 06:53:17 PM PDT 24
Finished Jun 26 06:53:37 PM PDT 24
Peak memory 226232 kb
Host smart-f9ca6cf4-f9b4-409e-8163-3c76220709b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557995259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.557995259
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.6040533
Short name T242
Test name
Test status
Simulation time 315776757 ps
CPU time 12.24 seconds
Started Jun 26 06:53:17 PM PDT 24
Finished Jun 26 06:53:31 PM PDT 24
Peak memory 218488 kb
Host smart-37d48e30-c5c1-4977-a730-412aa947a5b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6040533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dige
st_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_diges
t.6040533
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.178575535
Short name T791
Test name
Test status
Simulation time 1018499948 ps
CPU time 9.46 seconds
Started Jun 26 06:53:16 PM PDT 24
Finished Jun 26 06:53:27 PM PDT 24
Peak memory 218440 kb
Host smart-4fb311db-2a4e-4013-82fc-a47476a33562
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178575535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.178575535
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.3783833210
Short name T428
Test name
Test status
Simulation time 2100335028 ps
CPU time 11.31 seconds
Started Jun 26 06:53:04 PM PDT 24
Finished Jun 26 06:53:17 PM PDT 24
Peak memory 218596 kb
Host smart-586b75c8-1d52-48cc-94f1-7acff26aadf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783833210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3783833210
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.737568486
Short name T89
Test name
Test status
Simulation time 26517559 ps
CPU time 1.11 seconds
Started Jun 26 06:53:06 PM PDT 24
Finished Jun 26 06:53:08 PM PDT 24
Peak memory 212712 kb
Host smart-54519cad-76a5-46b9-8de3-9b730626cf80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737568486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.737568486
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.4172002703
Short name T219
Test name
Test status
Simulation time 183724801 ps
CPU time 27.06 seconds
Started Jun 26 06:53:01 PM PDT 24
Finished Jun 26 06:53:30 PM PDT 24
Peak memory 251148 kb
Host smart-0cfd5a77-5641-4d65-bc33-f86217a63c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172002703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.4172002703
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.2531675746
Short name T795
Test name
Test status
Simulation time 179087506 ps
CPU time 7.81 seconds
Started Jun 26 06:53:05 PM PDT 24
Finished Jun 26 06:53:15 PM PDT 24
Peak memory 251112 kb
Host smart-e28ae4fd-f8e5-4e3e-ab05-701e69a9e428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531675746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2531675746
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.4266310894
Short name T425
Test name
Test status
Simulation time 1677777746 ps
CPU time 42.01 seconds
Started Jun 26 06:53:19 PM PDT 24
Finished Jun 26 06:54:02 PM PDT 24
Peak memory 251108 kb
Host smart-530694fd-7928-4040-91f4-02c5d2899aff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266310894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.4266310894
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.3988719422
Short name T667
Test name
Test status
Simulation time 131780124559 ps
CPU time 613.22 seconds
Started Jun 26 06:53:16 PM PDT 24
Finished Jun 26 07:03:31 PM PDT 24
Peak memory 273244 kb
Host smart-7fd52262-4b9c-470c-a0c3-e66f5e12bc8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3988719422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.3988719422
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.706944941
Short name T594
Test name
Test status
Simulation time 40773405 ps
CPU time 0.81 seconds
Started Jun 26 06:53:03 PM PDT 24
Finished Jun 26 06:53:06 PM PDT 24
Peak memory 212100 kb
Host smart-c6fda974-516f-4a66-8970-c380f72d93b5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706944941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr
l_volatile_unlock_smoke.706944941
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.332907043
Short name T540
Test name
Test status
Simulation time 107762801 ps
CPU time 0.94 seconds
Started Jun 26 06:53:16 PM PDT 24
Finished Jun 26 06:53:19 PM PDT 24
Peak memory 209236 kb
Host smart-4a444d90-73ae-4203-b984-8c793a95778a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332907043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.332907043
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.4285529660
Short name T737
Test name
Test status
Simulation time 222374969 ps
CPU time 11.81 seconds
Started Jun 26 06:53:15 PM PDT 24
Finished Jun 26 06:53:28 PM PDT 24
Peak memory 218456 kb
Host smart-8fe3a157-3a80-4dad-ac4d-fa0523a170aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285529660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.4285529660
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.1022229703
Short name T644
Test name
Test status
Simulation time 927992572 ps
CPU time 7.53 seconds
Started Jun 26 06:53:17 PM PDT 24
Finished Jun 26 06:53:26 PM PDT 24
Peak memory 217388 kb
Host smart-8686bb17-1424-42c4-aaca-0dd60c908f4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022229703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.1022229703
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1067906721
Short name T528
Test name
Test status
Simulation time 4917898728 ps
CPU time 70.29 seconds
Started Jun 26 06:53:18 PM PDT 24
Finished Jun 26 06:54:30 PM PDT 24
Peak memory 219140 kb
Host smart-b5734cbc-50df-48b4-9ca0-09f5a29d0da8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067906721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1067906721
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2881518884
Short name T426
Test name
Test status
Simulation time 828773514 ps
CPU time 5.79 seconds
Started Jun 26 06:53:18 PM PDT 24
Finished Jun 26 06:53:26 PM PDT 24
Peak memory 217740 kb
Host smart-9f6625dd-035c-4af5-90eb-5a1e8e4cdb3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881518884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
881518884
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1724956502
Short name T3
Test name
Test status
Simulation time 87818942 ps
CPU time 2.74 seconds
Started Jun 26 06:53:15 PM PDT 24
Finished Jun 26 06:53:19 PM PDT 24
Peak memory 218436 kb
Host smart-01a2a926-907f-4a7e-ae7e-69f5445bd736
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724956502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.1724956502
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3443158169
Short name T79
Test name
Test status
Simulation time 1128491515 ps
CPU time 16.69 seconds
Started Jun 26 06:53:17 PM PDT 24
Finished Jun 26 06:53:35 PM PDT 24
Peak memory 217932 kb
Host smart-e6a2a891-93ed-4d50-8a80-928d11c43b6d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443158169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3443158169
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.1504906616
Short name T662
Test name
Test status
Simulation time 1868547896 ps
CPU time 2.13 seconds
Started Jun 26 06:53:18 PM PDT 24
Finished Jun 26 06:53:22 PM PDT 24
Peak memory 217848 kb
Host smart-ac6d807c-67ee-4b74-aadb-faa5fb885fe2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504906616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
1504906616
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1744713808
Short name T100
Test name
Test status
Simulation time 4216989902 ps
CPU time 82.02 seconds
Started Jun 26 06:53:18 PM PDT 24
Finished Jun 26 06:54:42 PM PDT 24
Peak memory 275780 kb
Host smart-ae9730da-7493-4d93-a29c-3e3d99453e6b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744713808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.1744713808
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1160485349
Short name T699
Test name
Test status
Simulation time 728741445 ps
CPU time 25.14 seconds
Started Jun 26 06:53:19 PM PDT 24
Finished Jun 26 06:53:46 PM PDT 24
Peak memory 251332 kb
Host smart-faf6cd2e-7607-4aea-aef0-40b6acce0fcb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160485349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1160485349
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1266700008
Short name T266
Test name
Test status
Simulation time 21868637 ps
CPU time 1.76 seconds
Started Jun 26 06:53:17 PM PDT 24
Finished Jun 26 06:53:21 PM PDT 24
Peak memory 222208 kb
Host smart-cc146350-2c5f-4d89-87fc-37f568360dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266700008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1266700008
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3739069767
Short name T705
Test name
Test status
Simulation time 566693571 ps
CPU time 20.16 seconds
Started Jun 26 06:53:16 PM PDT 24
Finished Jun 26 06:53:37 PM PDT 24
Peak memory 217932 kb
Host smart-8c361f22-1c0b-4907-a58a-7d03e3c6d284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739069767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3739069767
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1360909025
Short name T66
Test name
Test status
Simulation time 268334430 ps
CPU time 10.52 seconds
Started Jun 26 06:53:18 PM PDT 24
Finished Jun 26 06:53:30 PM PDT 24
Peak memory 226276 kb
Host smart-f3de1256-a568-4dcf-96a4-bbdac96b27d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360909025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1360909025
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.504771152
Short name T873
Test name
Test status
Simulation time 2297540845 ps
CPU time 13.23 seconds
Started Jun 26 06:53:16 PM PDT 24
Finished Jun 26 06:53:31 PM PDT 24
Peak memory 218584 kb
Host smart-d717406d-45a3-43d9-b54b-8bf2b5e10d03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504771152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dig
est.504771152
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.867520351
Short name T726
Test name
Test status
Simulation time 386344015 ps
CPU time 6.66 seconds
Started Jun 26 06:53:19 PM PDT 24
Finished Jun 26 06:53:27 PM PDT 24
Peak memory 218412 kb
Host smart-2bc6ba5c-661c-480e-96d7-f40845e3aea8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867520351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.867520351
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.3909896970
Short name T468
Test name
Test status
Simulation time 216086400 ps
CPU time 3.09 seconds
Started Jun 26 06:53:17 PM PDT 24
Finished Jun 26 06:53:21 PM PDT 24
Peak memory 214700 kb
Host smart-01595249-eba4-47ad-aac6-4ee4552e901b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909896970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.3909896970
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.945942010
Short name T719
Test name
Test status
Simulation time 604338471 ps
CPU time 21.26 seconds
Started Jun 26 06:53:16 PM PDT 24
Finished Jun 26 06:53:39 PM PDT 24
Peak memory 251068 kb
Host smart-8232187d-c7e4-4482-ad3a-b11a94f945d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945942010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.945942010
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.2197381643
Short name T595
Test name
Test status
Simulation time 64062889 ps
CPU time 6.76 seconds
Started Jun 26 06:53:17 PM PDT 24
Finished Jun 26 06:53:26 PM PDT 24
Peak memory 243124 kb
Host smart-de37e40a-d15b-423a-84cc-c34f383ecc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197381643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.2197381643
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.847699804
Short name T712
Test name
Test status
Simulation time 15343264315 ps
CPU time 147.83 seconds
Started Jun 26 06:53:17 PM PDT 24
Finished Jun 26 06:55:46 PM PDT 24
Peak memory 270880 kb
Host smart-8a034bb0-03d3-4e6e-adf9-0f74e4f04d58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847699804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.847699804
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.3945032600
Short name T753
Test name
Test status
Simulation time 63919850888 ps
CPU time 266.98 seconds
Started Jun 26 06:53:18 PM PDT 24
Finished Jun 26 06:57:47 PM PDT 24
Peak memory 267708 kb
Host smart-6bf20e07-83ee-4398-a0b5-0b653e35a0ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3945032600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.3945032600
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.4053985945
Short name T682
Test name
Test status
Simulation time 13881482 ps
CPU time 1.08 seconds
Started Jun 26 06:53:16 PM PDT 24
Finished Jun 26 06:53:18 PM PDT 24
Peak memory 212140 kb
Host smart-96cbf05f-5894-4ecc-ac19-e437d70ccd9c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053985945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.4053985945
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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