Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

112657379

1

T1

34453

T2

10979

T3

1335

auto[1]

1450394

1

T9

99

T11

198

T14

5635

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

112666632

1

T1

34453

T2

10979

T3

1335

auto[1]

1441141

1

T11

396

T14

4352

T15

891

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7685795	1			T1	93		T2	406		T3	202
auto[IdleSt]	24736314	1			T1	34360		T2	8898		T3	80
auto[ClkMuxSt]	37293	1			T2	4		T3	2		T4	6
auto[CntIncrSt]	36926	1			T2	4		T3	2		T4	6
auto[CntProgSt]	2082493	1			T2	8		T3	120		T4	28
auto[TransCheckSt]	28667	1			T2	4		T3	2		T4	6
auto[TokenHashSt]	44040977	1			T2	63		T3	197		T4	615
auto[FlashRmaSt]	29733	1			T2	4		T3	2		T4	6
auto[TokenCheck0St]	13384	1			T2	4		T3	2		T4	6
auto[TokenCheck1St]	9958	1			T2	4		T3	2		T4	6
auto[TransProgSt]	539610	1			T2	8		T3	20		T4	25
auto[PostTransSt]	14954944	1			T2	1572		T3	704		T4	2679
auto[ScrapSt]	242281	1			T4	666		T13	21		T14	8
auto[EscalateSt]	7278080	1			T9	142		T11	806		T14	31969
auto[InvalidSt]	12389238	1			T14	18959		T37	702		T29	9006

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2080	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12389238	1			T14	18959		T37	702		T29	9006
EscalateSt	7278080	1			T9	142		T11	806		T14	31969
ScrapSt	242281	1			T4	666		T13	21		T14	8
PostTransSt	14954944	1			T2	1572		T3	704		T4	2679
TransProgSt	539610	1			T2	8		T3	20		T4	25
TokenCheck1St	9958	1			T2	4		T3	2		T4	6
TokenCheck0St	13384	1			T2	4		T3	2		T4	6
FlashRmaSt	29733	1			T2	4		T3	2		T4	6
TokenHashSt	44040977	1			T2	63		T3	197		T4	615
TransCheckSt	28667	1			T2	4		T3	2		T4	6
CntProgSt	2082493	1			T2	8		T3	120		T4	28
CntIncrSt	36926	1			T2	4		T3	2		T4	6
ClkMuxSt	37293	1			T2	4		T3	2		T4	6
IdleSt	24736314	1			T1	34360		T2	8898		T3	80
ResetSt	7685795	1			T1	93		T2	406		T3	202
arcs[ResetSt=>IdleSt]	56238	1			T1	1		T2	4		T3	2
arcs[IdleSt=>ScrapSt]	335	1			T4	1		T13	2		T14	1
arcs[IdleSt=>ClkMuxSt]	36988	1			T2	4		T3	2		T4	6
arcs[ClkMuxSt=>CntIncrSt]	36926	1			T2	4		T3	2		T4	6
arcs[CntIncrSt=>PostTransSt]	1875	1			T14	21		T15	13		T16	19
arcs[CntIncrSt=>CntProgSt]	34971	1			T2	4		T3	2		T4	6
arcs[CntProgSt=>PostTransSt]	5324	1			T9	1		T11	6		T14	72
arcs[CntProgSt=>TransCheckSt]	28667	1			T2	4		T3	2		T4	6
arcs[TransCheckSt=>PostTransSt]	3828	1			T8	35		T17	34		T14	18
arcs[TransCheckSt=>TokenHashSt]	24667	1			T2	4		T3	2		T4	6
arcs[TokenHashSt=>PostTransSt]	10451	1			T8	9		T10	95		T17	7
arcs[TokenHashSt=>FlashRmaSt]	13490	1			T2	4		T3	2		T4	6
arcs[FlashRmaSt=>TokenCheck0St]	13384	1			T2	4		T3	2		T4	6
arcs[TokenCheck0St=>PostTransSt]	3396	1			T8	14		T17	10		T14	21
arcs[TokenCheck0St=>TokenCheck1St]	9958	1			T2	4		T3	2		T4	6
arcs[TokenCheck1St=>PostTransSt]	669	1			T8	3		T17	6		T15	1
arcs[TransProgSt=>PostTransSt]	8414	1			T2	4		T3	2		T4	6
arcs[IdleSt=>EscalateSt]	185	1			T40	7		T41	10		T44	9
arcs[ClkMuxSt=>EscalateSt]	62	1			T40	1		T41	1		T42	2
arcs[CntIncrSt=>EscalateSt]	80	1			T41	1		T43	1		T42	2
arcs[CntProgSt=>EscalateSt]	980	1			T40	9		T41	14		T43	7
arcs[TransCheckSt=>EscalateSt]	172	1			T40	15		T41	1		T43	4
arcs[TokenHashSt=>EscalateSt]	726	1			T40	19		T41	14		T43	17
arcs[FlashRmaSt=>EscalateSt]	106	1			T40	2		T41	3		T44	2
arcs[TokenCheck0St=>EscalateSt]	30	1			T40	2		T41	2		T44	2
arcs[TokenCheck1St=>EscalateSt]	147	1			T40	1		T41	2		T43	1
arcs[TransProgSt=>EscalateSt]	728	1			T40	11		T41	22		T43	7
arcs[PostTransSt=>EscalateSt]	5633	1			T9	1		T11	6		T14	73
arcs[InvalidSt=>EscalateSt]	14430	1			T14	28		T37	5		T29	66

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7685592	1			T1	93		T2	406		T3	202
auto[0]	auto[IdleSt]	24736194	1			T1	34360		T2	8898		T3	80
auto[0]	auto[ClkMuxSt]	37252	1			T2	4		T3	2		T4	6
auto[0]	auto[CntIncrSt]	36870	1			T2	4		T3	2		T4	6
auto[0]	auto[CntProgSt]	2081865	1			T2	8		T3	120		T4	28
auto[0]	auto[TransCheckSt]	28546	1			T2	4		T3	2		T4	6
auto[0]	auto[TokenHashSt]	44040513	1			T2	63		T3	197		T4	615
auto[0]	auto[FlashRmaSt]	29658	1			T2	4		T3	2		T4	6
auto[0]	auto[TokenCheck0St]	13368	1			T2	4		T3	2		T4	6
auto[0]	auto[TokenCheck1St]	9854	1			T2	4		T3	2		T4	6
auto[0]	auto[TransProgSt]	539141	1			T2	8		T3	20		T4	25
auto[0]	auto[PostTransSt]	14952112	1			T2	1572		T3	704		T4	2679
auto[0]	auto[ScrapSt]	242235	1			T4	666		T13	21		T14	8
auto[0]	auto[EscalateSt]	5840167	1			T9	44		T11	610		T14	26391
auto[0]	auto[InvalidSt]	12381932	1			T14	18941		T37	699		T29	8974
auto[1]	auto[ResetSt]	203	1			T40	5		T41	4		T43	7
auto[1]	auto[IdleSt]	120	1			T40	6		T41	4		T44	4
auto[1]	auto[ClkMuxSt]	41	1			T40	1		T41	1		T228	1
auto[1]	auto[CntIncrSt]	56	1			T41	1		T43	1		T42	1
auto[1]	auto[CntProgSt]	628	1			T40	4		T41	11		T43	4
auto[1]	auto[TransCheckSt]	121	1			T40	12		T41	1		T43	3
auto[1]	auto[TokenHashSt]	464	1			T40	13		T41	9		T43	12
auto[1]	auto[FlashRmaSt]	75	1			T40	2		T41	3		T44	1
auto[1]	auto[TokenCheck0St]	16	1			T40	2		T41	1		T44	1
auto[1]	auto[TokenCheck1St]	104	1			T40	1		T41	1		T43	1
auto[1]	auto[TransProgSt]	469	1			T40	6		T41	15		T43	5
auto[1]	auto[PostTransSt]	2832	1			T9	1		T11	2		T14	39
auto[1]	auto[ScrapSt]	46	1			T40	1		T41	1		T43	1
auto[1]	auto[EscalateSt]	1437913	1			T9	98		T11	196		T14	5578
auto[1]	auto[InvalidSt]	7306	1			T14	18		T37	3		T29	32

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7685609	1			T1	93		T2	406		T3	202
auto[0]	auto[IdleSt]	24736192	1			T1	34360		T2	8898		T3	80
auto[0]	auto[ClkMuxSt]	37247	1			T2	4		T3	2		T4	6
auto[0]	auto[CntIncrSt]	36875	1			T2	4		T3	2		T4	6
auto[0]	auto[CntProgSt]	2081849	1			T2	8		T3	120		T4	28
auto[0]	auto[TransCheckSt]	28553	1			T2	4		T3	2		T4	6
auto[0]	auto[TokenHashSt]	44040462	1			T2	63		T3	197		T4	615
auto[0]	auto[FlashRmaSt]	29663	1			T2	4		T3	2		T4	6
auto[0]	auto[TokenCheck0St]	13364	1			T2	4		T3	2		T4	6
auto[0]	auto[TokenCheck1St]	9864	1			T2	4		T3	2		T4	6
auto[0]	auto[TransProgSt]	539141	1			T2	8		T3	20		T4	25
auto[0]	auto[PostTransSt]	14952063	1			T2	1572		T3	704		T4	2679
auto[0]	auto[ScrapSt]	242247	1			T4	666		T13	21		T14	8
auto[0]	auto[EscalateSt]	5849309	1			T9	142		T11	414		T14	27661
auto[0]	auto[InvalidSt]	12382114	1			T14	18949		T37	700		T29	8972
auto[1]	auto[ResetSt]	186	1			T40	6		T41	3		T43	3
auto[1]	auto[IdleSt]	122	1			T40	4		T41	8		T44	7
auto[1]	auto[ClkMuxSt]	46	1			T42	2		T228	3		T229	2
auto[1]	auto[CntIncrSt]	51	1			T41	1		T42	2		T230	3
auto[1]	auto[CntProgSt]	644	1			T40	8		T41	8		T43	5
auto[1]	auto[TransCheckSt]	114	1			T40	10		T43	3		T42	3
auto[1]	auto[TokenHashSt]	515	1			T40	15		T41	10		T43	13
auto[1]	auto[FlashRmaSt]	70	1			T40	1		T41	2		T44	2
auto[1]	auto[TokenCheck0St]	20	1			T40	1		T41	1		T44	1
auto[1]	auto[TokenCheck1St]	94	1			T41	2		T44	2		T42	1
auto[1]	auto[TransProgSt]	469	1			T40	9		T41	13		T43	5
auto[1]	auto[PostTransSt]	2881	1			T11	4		T14	34		T15	9
auto[1]	auto[ScrapSt]	34	1			T41	1		T42	1		T228	1
auto[1]	auto[EscalateSt]	1428771	1			T11	392		T14	4308		T15	882
auto[1]	auto[InvalidSt]	7124	1			T14	10		T37	2		T29	34