Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

120984192

1

T1

1164

T2

1851

T3

860

auto[1]

1419591

1

T4

2963

T13

594

T10

2744

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

120981778

1

T1

1164

T2

1851

T3

860

auto[1]

1422005

1

T4

2567

T13

297

T10

2548

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7799410	1			T1	88		T2	105		T3	98
auto[IdleSt]	22893225	1			T1	16		T2	1746		T3	16
auto[ClkMuxSt]	38303	1			T1	1		T3	1		T4	275
auto[CntIncrSt]	37920	1			T1	1		T3	1		T4	271
auto[CntProgSt]	1868934	1			T1	14		T3	5		T4	467
auto[TransCheckSt]	29652	1			T1	1		T3	1		T4	204
auto[TokenHashSt]	55363515	1			T1	12		T3	73		T4	261934
auto[FlashRmaSt]	31111	1			T4	238		T5	14		T6	20
auto[TokenCheck0St]	13867	1			T4	92		T5	14		T6	6
auto[TokenCheck1St]	10419	1			T4	66		T5	14		T6	6
auto[TransProgSt]	484088	1			T4	123		T5	297		T6	12
auto[PostTransSt]	13867675	1			T1	1031		T3	665		T4	157600
auto[ScrapSt]	243073	1			T4	20		T5	26		T6	722
auto[EscalateSt]	7166907	1			T4	49326		T13	1330		T10	25763
auto[InvalidSt]	12553631	1			T4	37357		T10	88580		T21	7204

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2053	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12553631	1			T4	37357		T10	88580		T21	7204
EscalateSt	7166907	1			T4	49326		T13	1330		T10	25763
ScrapSt	243073	1			T4	20		T5	26		T6	722
PostTransSt	13867675	1			T1	1031		T3	665		T4	157600
TransProgSt	484088	1			T4	123		T5	297		T6	12
TokenCheck1St	10419	1			T4	66		T5	14		T6	6
TokenCheck0St	13867	1			T4	92		T5	14		T6	6
FlashRmaSt	31111	1			T4	238		T5	14		T6	20
TokenHashSt	55363515	1			T1	12		T3	73		T4	261934
TransCheckSt	29652	1			T1	1		T3	1		T4	204
CntProgSt	1868934	1			T1	14		T3	5		T4	467
CntIncrSt	37920	1			T1	1		T3	1		T4	271
ClkMuxSt	38303	1			T1	1		T3	1		T4	275
IdleSt	22893225	1			T1	16		T2	1746		T3	16
ResetSt	7799410	1			T1	88		T2	105		T3	98
arcs[ResetSt=>IdleSt]	57977	1			T1	1		T2	1		T3	1
arcs[IdleSt=>ScrapSt]	302	1			T4	2		T5	1		T6	1
arcs[IdleSt=>ClkMuxSt]	37979	1			T1	1		T3	1		T4	271
arcs[ClkMuxSt=>CntIncrSt]	37920	1			T1	1		T3	1		T4	271
arcs[CntIncrSt=>PostTransSt]	2040	1			T4	26		T13	16		T15	12
arcs[CntIncrSt=>CntProgSt]	35809	1			T1	1		T3	1		T4	245
arcs[CntProgSt=>PostTransSt]	5053	1			T4	41		T13	9		T15	99
arcs[CntProgSt=>TransCheckSt]	29652	1			T1	1		T3	1		T4	204
arcs[TransCheckSt=>PostTransSt]	3892	1			T4	22		T13	8		T15	19
arcs[TransCheckSt=>TokenHashSt]	25668	1			T1	1		T3	1		T4	182
arcs[TokenHashSt=>PostTransSt]	11099	1			T1	1		T3	1		T4	90
arcs[TokenHashSt=>FlashRmaSt]	13954	1			T4	92		T5	14		T6	6
arcs[FlashRmaSt=>TokenCheck0St]	13867	1			T4	92		T5	14		T6	6
arcs[TokenCheck0St=>PostTransSt]	3428	1			T4	26		T13	5		T15	17
arcs[TokenCheck0St=>TokenCheck1St]	10419	1			T4	66		T5	14		T6	6
arcs[TokenCheck1St=>PostTransSt]	664	1			T4	4		T15	2		T55	10
arcs[TransProgSt=>PostTransSt]	8918	1			T4	62		T5	14		T6	6
arcs[IdleSt=>EscalateSt]	159	1			T48	7		T45	7		T46	4
arcs[ClkMuxSt=>EscalateSt]	59	1			T44	3		T45	1		T46	1
arcs[CntIncrSt=>EscalateSt]	71	1			T44	3		T45	1		T47	4
arcs[CntProgSt=>EscalateSt]	1104	1			T48	13		T44	26		T45	10
arcs[TransCheckSt=>EscalateSt]	92	1			T48	7		T44	2		T45	3
arcs[TokenHashSt=>EscalateSt]	615	1			T48	14		T44	14		T56	2
arcs[FlashRmaSt=>EscalateSt]	87	1			T44	3		T45	3		T47	2
arcs[TokenCheck0St=>EscalateSt]	20	1			T52	2		T53	1		T54	1
arcs[TokenCheck1St=>EscalateSt]	127	1			T48	2		T44	4		T45	1
arcs[TransProgSt=>EscalateSt]	710	1			T48	8		T44	21		T45	7
arcs[PostTransSt=>EscalateSt]	5257	1			T4	42		T13	9		T15	99
arcs[InvalidSt=>EscalateSt]	15123	1			T4	14		T10	54		T21	53

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7799251	1			T1	88		T2	105		T3	98
auto[0]	auto[IdleSt]	22893115	1			T1	16		T2	1746		T3	16
auto[0]	auto[ClkMuxSt]	38259	1			T1	1		T3	1		T4	275
auto[0]	auto[CntIncrSt]	37877	1			T1	1		T3	1		T4	271
auto[0]	auto[CntProgSt]	1868194	1			T1	14		T3	5		T4	467
auto[0]	auto[TransCheckSt]	29589	1			T1	1		T3	1		T4	204
auto[0]	auto[TokenHashSt]	55363097	1			T1	12		T3	73		T4	261934
auto[0]	auto[FlashRmaSt]	31061	1			T4	238		T5	14		T6	20
auto[0]	auto[TokenCheck0St]	13855	1			T4	92		T5	14		T6	6
auto[0]	auto[TokenCheck1St]	10338	1			T4	66		T5	14		T6	6
auto[0]	auto[TransProgSt]	483615	1			T4	123		T5	297		T6	12
auto[0]	auto[PostTransSt]	13865009	1			T1	1031		T3	665		T4	157577
auto[0]	auto[ScrapSt]	243039	1			T4	20		T5	26		T6	722
auto[0]	auto[EscalateSt]	5759704	1			T4	46393		T13	742		T10	23047
auto[0]	auto[InvalidSt]	12546136	1			T4	37350		T10	88552		T21	7182
auto[1]	auto[ResetSt]	159	1			T48	2		T44	5		T45	4
auto[1]	auto[IdleSt]	110	1			T48	7		T45	3		T46	3
auto[1]	auto[ClkMuxSt]	44	1			T44	2		T45	1		T46	1
auto[1]	auto[CntIncrSt]	43	1			T44	2		T45	1		T47	2
auto[1]	auto[CntProgSt]	740	1			T48	9		T44	15		T45	6
auto[1]	auto[TransCheckSt]	63	1			T48	4		T44	2		T45	3
auto[1]	auto[TokenHashSt]	418	1			T48	8		T44	12		T56	1
auto[1]	auto[FlashRmaSt]	50	1			T44	1		T45	3		T47	2
auto[1]	auto[TokenCheck0St]	12	1			T52	2		T219	1		T220	2
auto[1]	auto[TokenCheck1St]	81	1			T48	1		T44	2		T45	1
auto[1]	auto[TransProgSt]	473	1			T48	7		T44	16		T45	4
auto[1]	auto[PostTransSt]	2666	1			T4	23		T13	6		T15	40
auto[1]	auto[ScrapSt]	34	1			T44	3		T221	1		T54	1
auto[1]	auto[EscalateSt]	1407203	1			T4	2933		T13	588		T10	2716
auto[1]	auto[InvalidSt]	7495	1			T4	7		T10	28		T21	22

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7799258	1			T1	88		T2	105		T3	98
auto[0]	auto[IdleSt]	22893124	1			T1	16		T2	1746		T3	16
auto[0]	auto[ClkMuxSt]	38266	1			T1	1		T3	1		T4	275
auto[0]	auto[CntIncrSt]	37870	1			T1	1		T3	1		T4	271
auto[0]	auto[CntProgSt]	1868213	1			T1	14		T3	5		T4	467
auto[0]	auto[TransCheckSt]	29585	1			T1	1		T3	1		T4	204
auto[0]	auto[TokenHashSt]	55363126	1			T1	12		T3	73		T4	261934
auto[0]	auto[FlashRmaSt]	31047	1			T4	238		T5	14		T6	20
auto[0]	auto[TokenCheck0St]	13851	1			T4	92		T5	14		T6	6
auto[0]	auto[TokenCheck1St]	10340	1			T4	66		T5	14		T6	6
auto[0]	auto[TransProgSt]	483619	1			T4	123		T5	297		T6	12
auto[0]	auto[PostTransSt]	13865029	1			T1	1031		T3	665		T4	157581
auto[0]	auto[ScrapSt]	243038	1			T4	20		T5	26		T6	722
auto[0]	auto[EscalateSt]	5757356	1			T4	46785		T13	1036		T10	23241
auto[0]	auto[InvalidSt]	12546003	1			T4	37350		T10	88554		T21	7173
auto[1]	auto[ResetSt]	152	1			T48	4		T44	4		T45	3
auto[1]	auto[IdleSt]	101	1			T48	5		T45	6		T46	4
auto[1]	auto[ClkMuxSt]	37	1			T44	3		T45	1		T46	1
auto[1]	auto[CntIncrSt]	50	1			T44	3		T47	4		T222	1
auto[1]	auto[CntProgSt]	721	1			T48	10		T44	18		T45	6
auto[1]	auto[TransCheckSt]	67	1			T48	6		T44	2		T45	2
auto[1]	auto[TokenHashSt]	389	1			T48	9		T44	9		T56	1
auto[1]	auto[FlashRmaSt]	64	1			T44	2		T45	2		T47	1
auto[1]	auto[TokenCheck0St]	16	1			T52	2		T53	1		T54	1
auto[1]	auto[TokenCheck1St]	79	1			T48	1		T44	3		T45	1
auto[1]	auto[TransProgSt]	469	1			T48	4		T44	13		T45	4
auto[1]	auto[PostTransSt]	2646	1			T4	19		T13	3		T15	59
auto[1]	auto[ScrapSt]	35	1			T48	1		T44	1		T45	2
auto[1]	auto[EscalateSt]	1409551	1			T4	2541		T13	294		T10	2522
auto[1]	auto[InvalidSt]	7628	1			T4	7		T10	26		T21	31