Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.90 97.92 95.93 93.38 97.62 98.52 99.00 95.94


Total test records in report: 984
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T807 /workspace/coverage/default/8.lc_ctrl_state_post_trans.2752314805 Jun 28 06:38:25 PM PDT 24 Jun 28 06:39:20 PM PDT 24 244704180 ps
T808 /workspace/coverage/default/38.lc_ctrl_alert_test.2152611939 Jun 28 06:48:29 PM PDT 24 Jun 28 06:50:21 PM PDT 24 60358629 ps
T809 /workspace/coverage/default/41.lc_ctrl_jtag_access.1221349212 Jun 28 06:48:54 PM PDT 24 Jun 28 06:50:57 PM PDT 24 752116972 ps
T810 /workspace/coverage/default/22.lc_ctrl_stress_all.3825072087 Jun 28 06:43:17 PM PDT 24 Jun 28 06:48:15 PM PDT 24 12121158308 ps
T112 /workspace/coverage/default/3.lc_ctrl_sec_cm.2876094090 Jun 28 06:37:31 PM PDT 24 Jun 28 06:38:16 PM PDT 24 301083583 ps
T811 /workspace/coverage/default/6.lc_ctrl_jtag_access.3269936110 Jun 28 06:38:22 PM PDT 24 Jun 28 06:39:16 PM PDT 24 2997775368 ps
T812 /workspace/coverage/default/2.lc_ctrl_jtag_errors.1387759932 Jun 28 06:37:13 PM PDT 24 Jun 28 06:38:00 PM PDT 24 1621606422 ps
T813 /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2463361140 Jun 28 06:41:52 PM PDT 24 Jun 28 06:44:02 PM PDT 24 975210152 ps
T814 /workspace/coverage/default/15.lc_ctrl_jtag_access.2476324994 Jun 28 06:40:33 PM PDT 24 Jun 28 06:42:47 PM PDT 24 404790051 ps
T815 /workspace/coverage/default/9.lc_ctrl_sec_token_digest.1347253206 Jun 28 06:39:01 PM PDT 24 Jun 28 06:39:53 PM PDT 24 2279471464 ps
T816 /workspace/coverage/default/6.lc_ctrl_jtag_smoke.2963272374 Jun 28 06:38:23 PM PDT 24 Jun 28 06:39:13 PM PDT 24 401492951 ps
T817 /workspace/coverage/default/41.lc_ctrl_sec_mubi.2413885794 Jun 28 06:49:20 PM PDT 24 Jun 28 06:51:07 PM PDT 24 420108162 ps
T818 /workspace/coverage/default/38.lc_ctrl_stress_all.2517242420 Jun 28 06:48:33 PM PDT 24 Jun 28 06:51:36 PM PDT 24 13014066964 ps
T819 /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.1949286608 Jun 28 06:38:20 PM PDT 24 Jun 28 06:39:10 PM PDT 24 1443346131 ps
T820 /workspace/coverage/default/35.lc_ctrl_smoke.4093453892 Jun 28 06:47:15 PM PDT 24 Jun 28 06:49:23 PM PDT 24 134839306 ps
T821 /workspace/coverage/default/44.lc_ctrl_stress_all.53716342 Jun 28 06:50:06 PM PDT 24 Jun 28 06:51:51 PM PDT 24 3071892338 ps
T822 /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.4062119126 Jun 28 06:37:16 PM PDT 24 Jun 28 06:38:45 PM PDT 24 8545440942 ps
T823 /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3087855553 Jun 28 06:39:03 PM PDT 24 Jun 28 06:39:52 PM PDT 24 3314979435 ps
T824 /workspace/coverage/default/6.lc_ctrl_jtag_priority.434050639 Jun 28 06:38:20 PM PDT 24 Jun 28 06:39:50 PM PDT 24 14807174317 ps
T825 /workspace/coverage/default/46.lc_ctrl_sec_token_mux.2678310840 Jun 28 06:50:36 PM PDT 24 Jun 28 06:51:45 PM PDT 24 194315718 ps
T826 /workspace/coverage/default/7.lc_ctrl_alert_test.300018821 Jun 28 06:38:26 PM PDT 24 Jun 28 06:39:15 PM PDT 24 82828025 ps
T827 /workspace/coverage/default/1.lc_ctrl_security_escalation.1689825685 Jun 28 06:37:02 PM PDT 24 Jun 28 06:37:13 PM PDT 24 907791554 ps
T828 /workspace/coverage/default/48.lc_ctrl_stress_all.1765333669 Jun 28 06:51:15 PM PDT 24 Jun 28 06:56:28 PM PDT 24 9826602205 ps
T829 /workspace/coverage/default/17.lc_ctrl_jtag_errors.3860699795 Jun 28 06:41:10 PM PDT 24 Jun 28 06:44:43 PM PDT 24 14943888331 ps
T830 /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2000146922 Jun 28 06:40:23 PM PDT 24 Jun 28 06:42:06 PM PDT 24 204017016 ps
T831 /workspace/coverage/default/43.lc_ctrl_errors.1993248714 Jun 28 06:49:43 PM PDT 24 Jun 28 06:51:26 PM PDT 24 363093627 ps
T832 /workspace/coverage/default/2.lc_ctrl_alert_test.43656023 Jun 28 06:37:12 PM PDT 24 Jun 28 06:37:14 PM PDT 24 17506950 ps
T833 /workspace/coverage/default/48.lc_ctrl_state_failure.1839895722 Jun 28 06:50:46 PM PDT 24 Jun 28 06:52:03 PM PDT 24 332223052 ps
T834 /workspace/coverage/default/3.lc_ctrl_jtag_errors.788110523 Jun 28 06:37:22 PM PDT 24 Jun 28 06:37:53 PM PDT 24 1710394513 ps
T835 /workspace/coverage/default/3.lc_ctrl_errors.840503221 Jun 28 06:37:15 PM PDT 24 Jun 28 06:37:32 PM PDT 24 346656841 ps
T836 /workspace/coverage/default/21.lc_ctrl_sec_mubi.4181107242 Jun 28 06:43:03 PM PDT 24 Jun 28 06:45:36 PM PDT 24 1541732133 ps
T837 /workspace/coverage/default/18.lc_ctrl_state_post_trans.1712956760 Jun 28 06:41:40 PM PDT 24 Jun 28 06:43:29 PM PDT 24 49220942 ps
T838 /workspace/coverage/default/10.lc_ctrl_jtag_smoke.1239382051 Jun 28 06:39:15 PM PDT 24 Jun 28 06:39:43 PM PDT 24 293193337 ps
T839 /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1815494381 Jun 28 06:43:20 PM PDT 24 Jun 28 06:46:14 PM PDT 24 12667432 ps
T840 /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.3679697887 Jun 28 06:42:59 PM PDT 24 Jun 28 06:52:27 PM PDT 24 15035317016 ps
T841 /workspace/coverage/default/48.lc_ctrl_prog_failure.652609744 Jun 28 06:51:00 PM PDT 24 Jun 28 06:51:51 PM PDT 24 341047426 ps
T842 /workspace/coverage/default/10.lc_ctrl_prog_failure.264354013 Jun 28 06:39:06 PM PDT 24 Jun 28 06:39:34 PM PDT 24 537189996 ps
T843 /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1672440376 Jun 28 06:40:08 PM PDT 24 Jun 28 06:41:18 PM PDT 24 48496740 ps
T844 /workspace/coverage/default/22.lc_ctrl_smoke.4252356126 Jun 28 06:43:01 PM PDT 24 Jun 28 06:45:28 PM PDT 24 16285355 ps
T845 /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.3020804173 Jun 28 06:37:54 PM PDT 24 Jun 28 06:40:59 PM PDT 24 8223260960 ps
T846 /workspace/coverage/default/1.lc_ctrl_stress_all.3447575346 Jun 28 06:37:13 PM PDT 24 Jun 28 06:39:27 PM PDT 24 25189886826 ps
T847 /workspace/coverage/default/13.lc_ctrl_jtag_errors.1925039958 Jun 28 06:40:11 PM PDT 24 Jun 28 06:41:56 PM PDT 24 7681324527 ps
T86 /workspace/coverage/default/23.lc_ctrl_smoke.3792337900 Jun 28 06:43:15 PM PDT 24 Jun 28 06:46:36 PM PDT 24 371555404 ps
T848 /workspace/coverage/default/6.lc_ctrl_state_post_trans.2820549965 Jun 28 06:38:05 PM PDT 24 Jun 28 06:38:31 PM PDT 24 92472326 ps
T849 /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.4040259664 Jun 28 06:40:09 PM PDT 24 Jun 28 06:42:04 PM PDT 24 1092738607 ps
T850 /workspace/coverage/default/27.lc_ctrl_sec_mubi.744233957 Jun 28 06:44:55 PM PDT 24 Jun 28 06:47:22 PM PDT 24 1095286910 ps
T851 /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.129647909 Jun 28 06:49:57 PM PDT 24 Jun 28 06:51:13 PM PDT 24 18779696 ps
T852 /workspace/coverage/default/7.lc_ctrl_state_failure.533365118 Jun 28 06:38:21 PM PDT 24 Jun 28 06:39:30 PM PDT 24 209687870 ps
T853 /workspace/coverage/default/37.lc_ctrl_sec_token_mux.602031065 Jun 28 06:48:22 PM PDT 24 Jun 28 06:50:29 PM PDT 24 196818976 ps
T143 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3577590093 Jun 28 06:35:26 PM PDT 24 Jun 28 06:35:29 PM PDT 24 79363690 ps
T135 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.30239677 Jun 28 06:35:19 PM PDT 24 Jun 28 06:35:21 PM PDT 24 38100973 ps
T130 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3109771561 Jun 28 06:34:52 PM PDT 24 Jun 28 06:35:00 PM PDT 24 2466017949 ps
T151 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2633770083 Jun 28 06:35:24 PM PDT 24 Jun 28 06:35:29 PM PDT 24 377048733 ps
T125 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1966022003 Jun 28 06:35:01 PM PDT 24 Jun 28 06:35:04 PM PDT 24 131436539 ps
T126 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.742859751 Jun 28 06:35:15 PM PDT 24 Jun 28 06:35:19 PM PDT 24 108596728 ps
T171 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.837710888 Jun 28 06:35:36 PM PDT 24 Jun 28 06:35:42 PM PDT 24 39835210 ps
T127 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2227265932 Jun 28 06:35:26 PM PDT 24 Jun 28 06:35:31 PM PDT 24 162714219 ps
T132 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3971106527 Jun 28 06:35:23 PM PDT 24 Jun 28 06:35:25 PM PDT 24 52944695 ps
T161 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3904494370 Jun 28 06:35:23 PM PDT 24 Jun 28 06:35:26 PM PDT 24 17755088 ps
T131 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1895136999 Jun 28 06:35:44 PM PDT 24 Jun 28 06:35:51 PM PDT 24 402165233 ps
T133 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1596628900 Jun 28 06:35:25 PM PDT 24 Jun 28 06:35:31 PM PDT 24 940588956 ps
T134 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3582018496 Jun 28 06:35:36 PM PDT 24 Jun 28 06:35:42 PM PDT 24 78282454 ps
T854 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2127770746 Jun 28 06:35:26 PM PDT 24 Jun 28 06:35:33 PM PDT 24 1640645371 ps
T207 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.570537132 Jun 28 06:34:51 PM PDT 24 Jun 28 06:34:53 PM PDT 24 21960157 ps
T168 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3598643091 Jun 28 06:35:29 PM PDT 24 Jun 28 06:35:33 PM PDT 24 116235216 ps
T141 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.4023224716 Jun 28 06:35:25 PM PDT 24 Jun 28 06:35:31 PM PDT 24 195801806 ps
T855 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.14724089 Jun 28 06:35:22 PM PDT 24 Jun 28 06:35:36 PM PDT 24 3124691972 ps
T196 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.757936043 Jun 28 06:35:02 PM PDT 24 Jun 28 06:35:04 PM PDT 24 25910592 ps
T154 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.576921967 Jun 28 06:35:32 PM PDT 24 Jun 28 06:35:38 PM PDT 24 241310565 ps
T138 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3680715096 Jun 28 06:35:35 PM PDT 24 Jun 28 06:35:42 PM PDT 24 143558381 ps
T856 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.584753524 Jun 28 06:34:45 PM PDT 24 Jun 28 06:34:48 PM PDT 24 42230591 ps
T169 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1757224002 Jun 28 06:34:43 PM PDT 24 Jun 28 06:34:47 PM PDT 24 27158468 ps
T208 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3165770164 Jun 28 06:35:34 PM PDT 24 Jun 28 06:35:38 PM PDT 24 13561792 ps
T857 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3487778981 Jun 28 06:35:43 PM PDT 24 Jun 28 06:35:47 PM PDT 24 50438462 ps
T155 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2276772627 Jun 28 06:35:33 PM PDT 24 Jun 28 06:35:39 PM PDT 24 87619616 ps
T170 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.785886873 Jun 28 06:35:34 PM PDT 24 Jun 28 06:35:39 PM PDT 24 17689182 ps
T144 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1192203087 Jun 28 06:34:42 PM PDT 24 Jun 28 06:34:45 PM PDT 24 114180980 ps
T159 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3567969804 Jun 28 06:34:43 PM PDT 24 Jun 28 06:34:48 PM PDT 24 82444592 ps
T858 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1701389802 Jun 28 06:34:58 PM PDT 24 Jun 28 06:35:00 PM PDT 24 24097653 ps
T859 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3940115441 Jun 28 06:35:02 PM PDT 24 Jun 28 06:35:06 PM PDT 24 127546951 ps
T860 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2654709711 Jun 28 06:35:40 PM PDT 24 Jun 28 06:35:45 PM PDT 24 201974309 ps
T160 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.184535210 Jun 28 06:34:51 PM PDT 24 Jun 28 06:35:18 PM PDT 24 4785545430 ps
T861 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2181290129 Jun 28 06:34:43 PM PDT 24 Jun 28 06:34:46 PM PDT 24 15044210 ps
T862 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.63548109 Jun 28 06:34:51 PM PDT 24 Jun 28 06:34:54 PM PDT 24 104474922 ps
T863 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.665315975 Jun 28 06:35:24 PM PDT 24 Jun 28 06:35:33 PM PDT 24 664237951 ps
T864 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1147233776 Jun 28 06:35:04 PM PDT 24 Jun 28 06:35:07 PM PDT 24 15381769 ps
T865 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.193735564 Jun 28 06:34:41 PM PDT 24 Jun 28 06:34:49 PM PDT 24 1797145127 ps
T866 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3071518924 Jun 28 06:34:44 PM PDT 24 Jun 28 06:34:49 PM PDT 24 102386589 ps
T867 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3803629974 Jun 28 06:35:02 PM PDT 24 Jun 28 06:35:04 PM PDT 24 15986968 ps
T209 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3001158781 Jun 28 06:34:51 PM PDT 24 Jun 28 06:34:53 PM PDT 24 13861207 ps
T868 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1604687355 Jun 28 06:35:23 PM PDT 24 Jun 28 06:35:33 PM PDT 24 694687612 ps
T869 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.699460140 Jun 28 06:35:01 PM PDT 24 Jun 28 06:35:03 PM PDT 24 24727335 ps
T210 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1937608342 Jun 28 06:34:44 PM PDT 24 Jun 28 06:34:47 PM PDT 24 46693206 ps
T211 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.979569539 Jun 28 06:35:37 PM PDT 24 Jun 28 06:35:43 PM PDT 24 89836781 ps
T870 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1454295788 Jun 28 06:35:14 PM PDT 24 Jun 28 06:35:26 PM PDT 24 472904815 ps
T142 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.89758985 Jun 28 06:35:01 PM PDT 24 Jun 28 06:35:06 PM PDT 24 416606140 ps
T871 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1146093406 Jun 28 06:35:01 PM PDT 24 Jun 28 06:35:06 PM PDT 24 106571775 ps
T872 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.311840621 Jun 28 06:35:45 PM PDT 24 Jun 28 06:35:48 PM PDT 24 52906868 ps
T139 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3515577343 Jun 28 06:35:31 PM PDT 24 Jun 28 06:35:37 PM PDT 24 93718643 ps
T873 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2875994919 Jun 28 06:35:34 PM PDT 24 Jun 28 06:35:39 PM PDT 24 30233430 ps
T212 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2823867714 Jun 28 06:35:33 PM PDT 24 Jun 28 06:35:38 PM PDT 24 42879187 ps
T140 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3212924831 Jun 28 06:35:41 PM PDT 24 Jun 28 06:35:47 PM PDT 24 154994214 ps
T197 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3792804537 Jun 28 06:35:20 PM PDT 24 Jun 28 06:35:22 PM PDT 24 31155010 ps
T874 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.223613301 Jun 28 06:34:54 PM PDT 24 Jun 28 06:35:04 PM PDT 24 1715605767 ps
T875 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2835735196 Jun 28 06:35:22 PM PDT 24 Jun 28 06:35:25 PM PDT 24 112968028 ps
T876 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.4232478624 Jun 28 06:35:35 PM PDT 24 Jun 28 06:35:41 PM PDT 24 26212414 ps
T877 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2585448200 Jun 28 06:35:33 PM PDT 24 Jun 28 06:35:39 PM PDT 24 160990446 ps
T878 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.930830869 Jun 28 06:35:03 PM PDT 24 Jun 28 06:35:17 PM PDT 24 8602625952 ps
T146 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.978377657 Jun 28 06:34:52 PM PDT 24 Jun 28 06:34:56 PM PDT 24 99795155 ps
T879 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3472535103 Jun 28 06:35:04 PM PDT 24 Jun 28 06:35:09 PM PDT 24 464995122 ps
T880 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4163447790 Jun 28 06:34:54 PM PDT 24 Jun 28 06:34:57 PM PDT 24 198870893 ps
T881 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3987216906 Jun 28 06:34:43 PM PDT 24 Jun 28 06:34:48 PM PDT 24 95029284 ps
T158 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.4177507732 Jun 28 06:35:20 PM PDT 24 Jun 28 06:35:24 PM PDT 24 70604870 ps
T882 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2934638973 Jun 28 06:35:15 PM PDT 24 Jun 28 06:35:17 PM PDT 24 167355719 ps
T883 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1190083901 Jun 28 06:34:44 PM PDT 24 Jun 28 06:34:48 PM PDT 24 198443846 ps
T884 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1677606477 Jun 28 06:35:25 PM PDT 24 Jun 28 06:35:30 PM PDT 24 175676494 ps
T885 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.4049289141 Jun 28 06:34:43 PM PDT 24 Jun 28 06:34:50 PM PDT 24 139978026 ps
T886 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1471530920 Jun 28 06:35:23 PM PDT 24 Jun 28 06:35:27 PM PDT 24 100403752 ps
T887 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1905533568 Jun 28 06:34:58 PM PDT 24 Jun 28 06:35:00 PM PDT 24 82793178 ps
T888 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1451364896 Jun 28 06:35:14 PM PDT 24 Jun 28 06:35:17 PM PDT 24 274628034 ps
T889 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.650920094 Jun 28 06:34:44 PM PDT 24 Jun 28 06:34:49 PM PDT 24 215553204 ps
T890 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2279389628 Jun 28 06:34:49 PM PDT 24 Jun 28 06:34:51 PM PDT 24 41843328 ps
T891 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1145584745 Jun 28 06:35:19 PM PDT 24 Jun 28 06:35:22 PM PDT 24 52095606 ps
T892 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3609866942 Jun 28 06:35:12 PM PDT 24 Jun 28 06:35:14 PM PDT 24 20252583 ps
T893 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2953748366 Jun 28 06:35:37 PM PDT 24 Jun 28 06:35:42 PM PDT 24 176169226 ps
T147 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.4092093215 Jun 28 06:35:34 PM PDT 24 Jun 28 06:35:40 PM PDT 24 389274899 ps
T894 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.566338873 Jun 28 06:35:24 PM PDT 24 Jun 28 06:35:27 PM PDT 24 96646942 ps
T895 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3831987101 Jun 28 06:34:53 PM PDT 24 Jun 28 06:34:56 PM PDT 24 125909811 ps
T896 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3044405941 Jun 28 06:35:14 PM PDT 24 Jun 28 06:35:16 PM PDT 24 136128839 ps
T897 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1714574194 Jun 28 06:35:23 PM PDT 24 Jun 28 06:35:26 PM PDT 24 13525818 ps
T898 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1641161711 Jun 28 06:35:32 PM PDT 24 Jun 28 06:35:38 PM PDT 24 28028186 ps
T899 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1598770727 Jun 28 06:35:03 PM PDT 24 Jun 28 06:35:08 PM PDT 24 513970610 ps
T900 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2259109117 Jun 28 06:35:24 PM PDT 24 Jun 28 06:35:30 PM PDT 24 100378102 ps
T901 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3842307724 Jun 28 06:34:46 PM PDT 24 Jun 28 06:34:50 PM PDT 24 88015641 ps
T902 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1634620205 Jun 28 06:35:26 PM PDT 24 Jun 28 06:35:31 PM PDT 24 120138216 ps
T903 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1294976667 Jun 28 06:35:33 PM PDT 24 Jun 28 06:35:39 PM PDT 24 313394806 ps
T904 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4239562274 Jun 28 06:35:22 PM PDT 24 Jun 28 06:35:25 PM PDT 24 60856410 ps
T905 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2963799041 Jun 28 06:34:43 PM PDT 24 Jun 28 06:34:50 PM PDT 24 1467688978 ps
T148 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3281431165 Jun 28 06:35:32 PM PDT 24 Jun 28 06:35:39 PM PDT 24 87967125 ps
T906 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1904927275 Jun 28 06:35:22 PM PDT 24 Jun 28 06:35:26 PM PDT 24 45814665 ps
T907 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.816892738 Jun 28 06:35:15 PM PDT 24 Jun 28 06:35:26 PM PDT 24 5421049636 ps
T908 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3072136353 Jun 28 06:35:01 PM PDT 24 Jun 28 06:35:05 PM PDT 24 276698910 ps
T198 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3213841571 Jun 28 06:35:34 PM PDT 24 Jun 28 06:35:39 PM PDT 24 16677168 ps
T152 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3362536277 Jun 28 06:35:42 PM PDT 24 Jun 28 06:35:48 PM PDT 24 122027945 ps
T199 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.305308899 Jun 28 06:35:32 PM PDT 24 Jun 28 06:35:37 PM PDT 24 13897193 ps
T909 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1423618438 Jun 28 06:35:44 PM PDT 24 Jun 28 06:35:49 PM PDT 24 168143245 ps
T910 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3677468461 Jun 28 06:34:54 PM PDT 24 Jun 28 06:34:59 PM PDT 24 227542134 ps
T911 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.941054256 Jun 28 06:34:47 PM PDT 24 Jun 28 06:34:50 PM PDT 24 189344462 ps
T912 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.4057163171 Jun 28 06:35:04 PM PDT 24 Jun 28 06:35:08 PM PDT 24 259522436 ps
T200 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1730199596 Jun 28 06:35:14 PM PDT 24 Jun 28 06:35:16 PM PDT 24 14028198 ps
T913 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2996129171 Jun 28 06:34:44 PM PDT 24 Jun 28 06:34:47 PM PDT 24 47097632 ps
T201 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2964239519 Jun 28 06:35:34 PM PDT 24 Jun 28 06:35:40 PM PDT 24 15823786 ps
T914 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2580905948 Jun 28 06:35:26 PM PDT 24 Jun 28 06:35:30 PM PDT 24 17419466 ps
T915 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2634171042 Jun 28 06:35:19 PM PDT 24 Jun 28 06:35:21 PM PDT 24 67814462 ps
T202 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1666823064 Jun 28 06:35:01 PM PDT 24 Jun 28 06:35:03 PM PDT 24 47520958 ps
T916 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3613428347 Jun 28 06:35:26 PM PDT 24 Jun 28 06:35:33 PM PDT 24 266541617 ps
T157 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.371170116 Jun 28 06:35:32 PM PDT 24 Jun 28 06:35:37 PM PDT 24 187275259 ps
T149 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1200719622 Jun 28 06:34:54 PM PDT 24 Jun 28 06:35:00 PM PDT 24 272417325 ps
T917 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2779338499 Jun 28 06:34:59 PM PDT 24 Jun 28 06:35:01 PM PDT 24 58715691 ps
T918 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.4171054762 Jun 28 06:35:15 PM PDT 24 Jun 28 06:35:18 PM PDT 24 18143131 ps
T919 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3127507618 Jun 28 06:34:43 PM PDT 24 Jun 28 06:34:46 PM PDT 24 35934969 ps
T920 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1231341970 Jun 28 06:34:45 PM PDT 24 Jun 28 06:34:48 PM PDT 24 28066021 ps
T921 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3191366771 Jun 28 06:34:58 PM PDT 24 Jun 28 06:35:00 PM PDT 24 125684080 ps
T922 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3716586264 Jun 28 06:35:29 PM PDT 24 Jun 28 06:35:33 PM PDT 24 208281309 ps
T923 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.904523691 Jun 28 06:35:42 PM PDT 24 Jun 28 06:35:46 PM PDT 24 44081512 ps
T924 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1442240710 Jun 28 06:35:34 PM PDT 24 Jun 28 06:35:40 PM PDT 24 29573485 ps
T203 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2836496901 Jun 28 06:35:31 PM PDT 24 Jun 28 06:35:36 PM PDT 24 31113090 ps
T925 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3512006100 Jun 28 06:35:34 PM PDT 24 Jun 28 06:35:41 PM PDT 24 127824926 ps
T926 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1470014774 Jun 28 06:34:58 PM PDT 24 Jun 28 06:35:00 PM PDT 24 53663991 ps
T927 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1270778290 Jun 28 06:35:01 PM PDT 24 Jun 28 06:35:04 PM PDT 24 38521931 ps
T928 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1536967983 Jun 28 06:34:45 PM PDT 24 Jun 28 06:34:50 PM PDT 24 67013105 ps
T929 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3268580781 Jun 28 06:35:15 PM PDT 24 Jun 28 06:35:19 PM PDT 24 56057188 ps
T930 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3150144817 Jun 28 06:35:23 PM PDT 24 Jun 28 06:35:26 PM PDT 24 49768375 ps
T931 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.492251198 Jun 28 06:35:15 PM PDT 24 Jun 28 06:35:17 PM PDT 24 109851955 ps
T932 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2615308082 Jun 28 06:34:53 PM PDT 24 Jun 28 06:34:55 PM PDT 24 59587039 ps
T933 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3248744704 Jun 28 06:35:15 PM PDT 24 Jun 28 06:35:21 PM PDT 24 718785594 ps
T934 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.549875392 Jun 28 06:35:25 PM PDT 24 Jun 28 06:35:33 PM PDT 24 5352338355 ps
T204 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.347928595 Jun 28 06:34:43 PM PDT 24 Jun 28 06:34:46 PM PDT 24 22906036 ps
T935 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1380814436 Jun 28 06:35:35 PM PDT 24 Jun 28 06:35:40 PM PDT 24 20767959 ps
T936 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.388450669 Jun 28 06:35:33 PM PDT 24 Jun 28 06:35:38 PM PDT 24 169800633 ps
T937 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.622805419 Jun 28 06:34:58 PM PDT 24 Jun 28 06:35:01 PM PDT 24 145446447 ps
T938 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.81735517 Jun 28 06:35:15 PM PDT 24 Jun 28 06:35:17 PM PDT 24 134564801 ps
T153 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2468932125 Jun 28 06:35:33 PM PDT 24 Jun 28 06:35:40 PM PDT 24 105441694 ps
T939 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.137199787 Jun 28 06:35:03 PM PDT 24 Jun 28 06:35:06 PM PDT 24 34460212 ps
T940 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1435053580 Jun 28 06:35:14 PM PDT 24 Jun 28 06:35:34 PM PDT 24 6830446374 ps
T941 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2133341389 Jun 28 06:35:31 PM PDT 24 Jun 28 06:35:36 PM PDT 24 50382510 ps
T942 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1996804071 Jun 28 06:35:31 PM PDT 24 Jun 28 06:35:37 PM PDT 24 291775499 ps
T943 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1107315003 Jun 28 06:35:15 PM PDT 24 Jun 28 06:35:19 PM PDT 24 410748816 ps
T944 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.4247848254 Jun 28 06:35:13 PM PDT 24 Jun 28 06:35:16 PM PDT 24 93226505 ps
T945 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3138212728 Jun 28 06:35:04 PM PDT 24 Jun 28 06:35:08 PM PDT 24 320535052 ps
T946 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.249830494 Jun 28 06:35:14 PM PDT 24 Jun 28 06:35:18 PM PDT 24 811835839 ps
T947 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3799479585 Jun 28 06:35:34 PM PDT 24 Jun 28 06:35:42 PM PDT 24 76748065 ps
T948 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2589463936 Jun 28 06:35:01 PM PDT 24 Jun 28 06:35:19 PM PDT 24 1237828323 ps
T949 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2208972156 Jun 28 06:35:32 PM PDT 24 Jun 28 06:35:37 PM PDT 24 30923293 ps
T950 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3587501634 Jun 28 06:35:34 PM PDT 24 Jun 28 06:35:40 PM PDT 24 43625076 ps
T951 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.55939714 Jun 28 06:34:54 PM PDT 24 Jun 28 06:34:58 PM PDT 24 478871065 ps
T952 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1636604924 Jun 28 06:35:32 PM PDT 24 Jun 28 06:35:38 PM PDT 24 256235960 ps
T150 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1408426692 Jun 28 06:35:26 PM PDT 24 Jun 28 06:35:32 PM PDT 24 290689182 ps
T953 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1765050897 Jun 28 06:34:43 PM PDT 24 Jun 28 06:34:46 PM PDT 24 87952644 ps
T954 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.792615236 Jun 28 06:34:49 PM PDT 24 Jun 28 06:35:02 PM PDT 24 3320152862 ps
T955 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.359163850 Jun 28 06:35:20 PM PDT 24 Jun 28 06:35:23 PM PDT 24 48330764 ps
T156 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1671975130 Jun 28 06:34:45 PM PDT 24 Jun 28 06:34:49 PM PDT 24 64560821 ps
T145 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2296428820 Jun 28 06:35:03 PM PDT 24 Jun 28 06:35:08 PM PDT 24 280555143 ps
T956 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1543931653 Jun 28 06:34:55 PM PDT 24 Jun 28 06:34:58 PM PDT 24 156057532 ps
T957 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1630331689 Jun 28 06:35:24 PM PDT 24 Jun 28 06:35:29 PM PDT 24 89826699 ps
T958 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2855335054 Jun 28 06:35:23 PM PDT 24 Jun 28 06:35:56 PM PDT 24 4965923940 ps
T205 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.573658485 Jun 28 06:34:47 PM PDT 24 Jun 28 06:34:49 PM PDT 24 16843912 ps
T959 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.36848321 Jun 28 06:34:43 PM PDT 24 Jun 28 06:34:47 PM PDT 24 43848044 ps
T960 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2156026341 Jun 28 06:35:17 PM PDT 24 Jun 28 06:35:20 PM PDT 24 396781425 ps
T961 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.766616697 Jun 28 06:35:05 PM PDT 24 Jun 28 06:35:15 PM PDT 24 1325482087 ps
T962 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3265326451 Jun 28 06:35:25 PM PDT 24 Jun 28 06:35:30 PM PDT 24 45989013 ps
T963 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.479273458 Jun 28 06:35:42 PM PDT 24 Jun 28 06:35:46 PM PDT 24 17148858 ps
T964 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2139484654 Jun 28 06:34:54 PM PDT 24 Jun 28 06:34:57 PM PDT 24 59907285 ps
T965 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3097645233 Jun 28 06:34:55 PM PDT 24 Jun 28 06:34:59 PM PDT 24 55634929 ps
T966 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2011496637 Jun 28 06:35:42 PM PDT 24 Jun 28 06:35:47 PM PDT 24 43498965 ps
T967 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3363355785 Jun 28 06:34:47 PM PDT 24 Jun 28 06:34:50 PM PDT 24 96245420 ps
T968 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.691970708 Jun 28 06:35:24 PM PDT 24 Jun 28 06:35:28 PM PDT 24 25221466 ps
T969 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2980496371 Jun 28 06:35:36 PM PDT 24 Jun 28 06:35:42 PM PDT 24 27944362 ps
T970 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2884730380 Jun 28 06:35:36 PM PDT 24 Jun 28 06:35:42 PM PDT 24 27291244 ps
T971 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2269668608 Jun 28 06:35:33 PM PDT 24 Jun 28 06:35:38 PM PDT 24 17908787 ps
T972 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1716359897 Jun 28 06:35:21 PM PDT 24 Jun 28 06:35:23 PM PDT 24 72563457 ps
T973 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.228973583 Jun 28 06:35:20 PM PDT 24 Jun 28 06:35:23 PM PDT 24 50884486 ps
T974 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.41193912 Jun 28 06:34:54 PM PDT 24 Jun 28 06:34:58 PM PDT 24 375069201 ps
T975 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2790787939 Jun 28 06:35:34 PM PDT 24 Jun 28 06:35:39 PM PDT 24 44583884 ps
T976 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.4138206830 Jun 28 06:35:15 PM PDT 24 Jun 28 06:35:18 PM PDT 24 42888815 ps
T977 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1367938308 Jun 28 06:35:25 PM PDT 24 Jun 28 06:35:28 PM PDT 24 138835397 ps
T978 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.937797731 Jun 28 06:35:34 PM PDT 24 Jun 28 06:35:42 PM PDT 24 155025268 ps
T979 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1130069062 Jun 28 06:34:43 PM PDT 24 Jun 28 06:34:53 PM PDT 24 333931383 ps
T980 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.949578431 Jun 28 06:34:43 PM PDT 24 Jun 28 06:34:47 PM PDT 24 33738678 ps
T981 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1731184792 Jun 28 06:34:54 PM PDT 24 Jun 28 06:34:57 PM PDT 24 14395208 ps
T206 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1239442543 Jun 28 06:35:33 PM PDT 24 Jun 28 06:35:37 PM PDT 24 92185929 ps
T982 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.857133906 Jun 28 06:35:36 PM PDT 24 Jun 28 06:35:42 PM PDT 24 69930881 ps
T983 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3881866540 Jun 28 06:35:32 PM PDT 24 Jun 28 06:35:37 PM PDT 24 86580346 ps
T984 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2104413829 Jun 28 06:35:33 PM PDT 24 Jun 28 06:35:38 PM PDT 24 77494463 ps

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3041092740
Short name T4
Test name
Test status
Simulation time 47419685284 ps
CPU time 164.56 seconds
Started Jun 28 06:45:09 PM PDT 24
Finished Jun 28 06:49:46 PM PDT 24
Peak memory 270156 kb
Host smart-83343c6e-0296-49fc-b779-e2e217d5634a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041092740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3041092740
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.4101446022
Short name T48
Test name
Test status
Simulation time 246293644 ps
CPU time 10.05 seconds
Started Jun 28 06:49:01 PM PDT 24
Finished Jun 28 06:50:49 PM PDT 24
Peak memory 225528 kb
Host smart-845769b2-0eda-4a4a-ad03-f89a31ac9848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101446022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.4101446022
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.2426369481
Short name T15
Test name
Test status
Simulation time 26454366347 ps
CPU time 517.52 seconds
Started Jun 28 06:49:44 PM PDT 24
Finished Jun 28 06:59:47 PM PDT 24
Peak memory 447848 kb
Host smart-b7d58449-92c6-4207-97ec-cfcd06b5c2a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2426369481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.2426369481
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.998389090
Short name T37
Test name
Test status
Simulation time 2360282994 ps
CPU time 17.92 seconds
Started Jun 28 06:39:01 PM PDT 24
Finished Jun 28 06:39:45 PM PDT 24
Peak memory 226308 kb
Host smart-3fcf6b4d-5cf9-488d-aec7-f08ddf4a49f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998389090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.998389090
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.226790984
Short name T52
Test name
Test status
Simulation time 1212073164 ps
CPU time 13.36 seconds
Started Jun 28 06:40:03 PM PDT 24
Finished Jun 28 06:41:10 PM PDT 24
Peak memory 218572 kb
Host smart-58b7b601-29c7-4330-b0b3-8c17e97e979f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226790984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.226790984
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3109771561
Short name T130
Test name
Test status
Simulation time 2466017949 ps
CPU time 6.52 seconds
Started Jun 28 06:34:52 PM PDT 24
Finished Jun 28 06:35:00 PM PDT 24
Peak memory 218744 kb
Host smart-924dd750-97f3-4d3b-9e75-fa5ac272c498
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310977
1561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3109771561
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.2251420801
Short name T121
Test name
Test status
Simulation time 13366177905 ps
CPU time 362.52 seconds
Started Jun 28 06:49:08 PM PDT 24
Finished Jun 28 06:56:55 PM PDT 24
Peak memory 333228 kb
Host smart-fd9a0012-0d15-4364-92d9-6c0bdb9282a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2251420801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.2251420801
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.929661611
Short name T50
Test name
Test status
Simulation time 733093360 ps
CPU time 24.47 seconds
Started Jun 28 06:37:15 PM PDT 24
Finished Jun 28 06:37:43 PM PDT 24
Peak memory 269172 kb
Host smart-a9242e53-d1b8-4123-b680-1bfcbeb7757b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929661611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.929661611
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1895136999
Short name T131
Test name
Test status
Simulation time 402165233 ps
CPU time 4.66 seconds
Started Jun 28 06:35:44 PM PDT 24
Finished Jun 28 06:35:51 PM PDT 24
Peak memory 217580 kb
Host smart-e2568500-3bb0-4bdd-85d0-cfbff0c7bd6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895136999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1895136999
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.3118704490
Short name T7
Test name
Test status
Simulation time 782770854 ps
CPU time 8.06 seconds
Started Jun 28 06:47:03 PM PDT 24
Finished Jun 28 06:49:18 PM PDT 24
Peak memory 217728 kb
Host smart-2f9f60ff-52ac-4761-ac30-69fdd5dceb2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118704490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.3118704490
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.458687420
Short name T2
Test name
Test status
Simulation time 18717640 ps
CPU time 1.11 seconds
Started Jun 28 06:49:54 PM PDT 24
Finished Jun 28 06:51:12 PM PDT 24
Peak memory 209152 kb
Host smart-c9237fa5-890e-4aaf-9999-67e89da5dee1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458687420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.458687420
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1257862096
Short name T62
Test name
Test status
Simulation time 625274466 ps
CPU time 14.55 seconds
Started Jun 28 06:44:55 PM PDT 24
Finished Jun 28 06:47:34 PM PDT 24
Peak memory 218452 kb
Host smart-9cd7f337-2023-48a6-ad9d-a8342fde3850
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257862096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1257862096
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.573658485
Short name T205
Test name
Test status
Simulation time 16843912 ps
CPU time 1.09 seconds
Started Jun 28 06:34:47 PM PDT 24
Finished Jun 28 06:34:49 PM PDT 24
Peak memory 209312 kb
Host smart-2ad42d5a-1ec3-4e1f-a13a-b91051b142b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573658485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing
.573658485
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.3827983490
Short name T91
Test name
Test status
Simulation time 42245662310 ps
CPU time 1581.56 seconds
Started Jun 28 06:39:33 PM PDT 24
Finished Jun 28 07:06:16 PM PDT 24
Peak memory 562228 kb
Host smart-fb275433-0529-496b-b9b0-7094dbf7823c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3827983490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.3827983490
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3515577343
Short name T139
Test name
Test status
Simulation time 93718643 ps
CPU time 3.35 seconds
Started Jun 28 06:35:31 PM PDT 24
Finished Jun 28 06:35:37 PM PDT 24
Peak memory 217808 kb
Host smart-4ba22746-915b-4d03-85b5-9183d234a2b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515577343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3515577343
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.3283736008
Short name T13
Test name
Test status
Simulation time 2489570779 ps
CPU time 14.43 seconds
Started Jun 28 06:44:09 PM PDT 24
Finished Jun 28 06:46:37 PM PDT 24
Peak memory 218500 kb
Host smart-d1c1785a-31b0-467c-8072-a1b32778c8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283736008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.3283736008
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2296428820
Short name T145
Test name
Test status
Simulation time 280555143 ps
CPU time 3.47 seconds
Started Jun 28 06:35:03 PM PDT 24
Finished Jun 28 06:35:08 PM PDT 24
Peak memory 222484 kb
Host smart-83f09ecc-0774-40ec-bf03-4add0c1469d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296428820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.2296428820
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2468932125
Short name T153
Test name
Test status
Simulation time 105441694 ps
CPU time 3.93 seconds
Started Jun 28 06:35:33 PM PDT 24
Finished Jun 28 06:35:40 PM PDT 24
Peak memory 217640 kb
Host smart-4dc50ebc-ce9e-4c59-80d7-89240c0d7c55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468932125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2468932125
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.530719616
Short name T425
Test name
Test status
Simulation time 232515851 ps
CPU time 7.05 seconds
Started Jun 28 06:39:35 PM PDT 24
Finished Jun 28 06:40:02 PM PDT 24
Peak memory 218544 kb
Host smart-8ffd8bde-4cf3-4c22-81a2-6cf8a83c5a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530719616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.530719616
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.3447575346
Short name T846
Test name
Test status
Simulation time 25189886826 ps
CPU time 132.54 seconds
Started Jun 28 06:37:13 PM PDT 24
Finished Jun 28 06:39:27 PM PDT 24
Peak memory 282924 kb
Host smart-b0693bf8-db75-46cc-abba-f1ad6939423f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447575346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.3447575346
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.699360388
Short name T3
Test name
Test status
Simulation time 22713206 ps
CPU time 0.86 seconds
Started Jun 28 06:50:06 PM PDT 24
Finished Jun 28 06:51:21 PM PDT 24
Peak memory 212196 kb
Host smart-35885d67-d270-4f79-904d-47b2f42ababd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699360388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ct
rl_volatile_unlock_smoke.699360388
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.576921967
Short name T154
Test name
Test status
Simulation time 241310565 ps
CPU time 3.16 seconds
Started Jun 28 06:35:32 PM PDT 24
Finished Jun 28 06:35:38 PM PDT 24
Peak memory 222340 kb
Host smart-a2c37725-4437-4de1-a413-2e4ca2cf849f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576921967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_
err.576921967
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1937608342
Short name T210
Test name
Test status
Simulation time 46693206 ps
CPU time 1.05 seconds
Started Jun 28 06:34:44 PM PDT 24
Finished Jun 28 06:34:47 PM PDT 24
Peak memory 209384 kb
Host smart-afb2a0c3-3a00-431f-9388-89943f711151
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937608342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.1937608342
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.1023055340
Short name T101
Test name
Test status
Simulation time 125515045608 ps
CPU time 1025.27 seconds
Started Jun 28 06:45:09 PM PDT 24
Finished Jun 28 07:04:38 PM PDT 24
Peak memory 546180 kb
Host smart-543866ac-0ab6-4d36-b120-b06d3bc3abcf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1023055340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.1023055340
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.3751010258
Short name T92
Test name
Test status
Simulation time 86101937606 ps
CPU time 659.08 seconds
Started Jun 28 06:38:19 PM PDT 24
Finished Jun 28 06:50:05 PM PDT 24
Peak memory 308920 kb
Host smart-fb934bf0-d419-466e-9419-08c6d50b0299
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3751010258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.3751010258
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.1532651946
Short name T5
Test name
Test status
Simulation time 46802556 ps
CPU time 2.93 seconds
Started Jun 28 06:40:40 PM PDT 24
Finished Jun 28 06:42:50 PM PDT 24
Peak memory 218072 kb
Host smart-09cafce4-ddea-401f-87fd-b149c7a5fbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532651946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.1532651946
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.371170116
Short name T157
Test name
Test status
Simulation time 187275259 ps
CPU time 2.39 seconds
Started Jun 28 06:35:32 PM PDT 24
Finished Jun 28 06:35:37 PM PDT 24
Peak memory 217580 kb
Host smart-ff324a49-bf20-4a6b-81dd-8fc21c4f304f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371170116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_
err.371170116
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.4092093215
Short name T147
Test name
Test status
Simulation time 389274899 ps
CPU time 1.85 seconds
Started Jun 28 06:35:34 PM PDT 24
Finished Jun 28 06:35:40 PM PDT 24
Peak memory 221752 kb
Host smart-cfd4476c-5832-44d6-a017-bbff1fca4258
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092093215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.4092093215
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.742859751
Short name T126
Test name
Test status
Simulation time 108596728 ps
CPU time 3.01 seconds
Started Jun 28 06:35:15 PM PDT 24
Finished Jun 28 06:35:19 PM PDT 24
Peak memory 222376 kb
Host smart-7e0752b9-f85b-46a6-ac56-1cf8cca7216f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742859751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_e
rr.742859751
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1594278574
Short name T215
Test name
Test status
Simulation time 92764751 ps
CPU time 0.95 seconds
Started Jun 28 06:37:02 PM PDT 24
Finished Jun 28 06:37:07 PM PDT 24
Peak memory 209212 kb
Host smart-8f250508-9d6a-4afd-a54a-a6565cd200da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594278574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.1594278574
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.3902904668
Short name T218
Test name
Test status
Simulation time 30384741 ps
CPU time 0.85 seconds
Started Jun 28 06:38:03 PM PDT 24
Finished Jun 28 06:38:28 PM PDT 24
Peak memory 209152 kb
Host smart-81462a26-a202-4dcf-9f9f-a8eda6c8092a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902904668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.3902904668
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.4136665796
Short name T63
Test name
Test status
Simulation time 486624194 ps
CPU time 13 seconds
Started Jun 28 06:41:29 PM PDT 24
Finished Jun 28 06:43:38 PM PDT 24
Peak memory 226128 kb
Host smart-afa5fe0f-a688-41e8-8ac0-ba5d4252f5c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136665796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.4136665796
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1671975130
Short name T156
Test name
Test status
Simulation time 64560821 ps
CPU time 1.9 seconds
Started Jun 28 06:34:45 PM PDT 24
Finished Jun 28 06:34:49 PM PDT 24
Peak memory 221620 kb
Host smart-e5a18555-bd9f-49a5-be2e-4d163aa30294
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671975130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.1671975130
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2276772627
Short name T155
Test name
Test status
Simulation time 87619616 ps
CPU time 2.82 seconds
Started Jun 28 06:35:33 PM PDT 24
Finished Jun 28 06:35:39 PM PDT 24
Peak memory 217584 kb
Host smart-8333eecf-7939-4e61-b2be-2dfe6df157e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276772627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.2276772627
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3362536277
Short name T152
Test name
Test status
Simulation time 122027945 ps
CPU time 2.85 seconds
Started Jun 28 06:35:42 PM PDT 24
Finished Jun 28 06:35:48 PM PDT 24
Peak memory 222036 kb
Host smart-01393739-e80c-4c22-9493-9ae7e1de3f09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362536277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.3362536277
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1200719622
Short name T149
Test name
Test status
Simulation time 272417325 ps
CPU time 3.59 seconds
Started Jun 28 06:34:54 PM PDT 24
Finished Jun 28 06:35:00 PM PDT 24
Peak memory 217644 kb
Host smart-0cf72309-47ff-4c9a-85d4-8cc53ae17681
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200719622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.1200719622
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1408426692
Short name T150
Test name
Test status
Simulation time 290689182 ps
CPU time 3.45 seconds
Started Jun 28 06:35:26 PM PDT 24
Finished Jun 28 06:35:32 PM PDT 24
Peak memory 217556 kb
Host smart-e4987e18-a00d-4888-ac97-220c776c6b4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408426692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.1408426692
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.245221862
Short name T136
Test name
Test status
Simulation time 2463971450 ps
CPU time 35.68 seconds
Started Jun 28 06:40:47 PM PDT 24
Finished Jun 28 06:43:18 PM PDT 24
Peak memory 226300 kb
Host smart-5128e11d-2772-43e5-9551-6de762f0be85
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245221862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_er
rors.245221862
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.1436307864
Short name T41
Test name
Test status
Simulation time 7635032766 ps
CPU time 13.02 seconds
Started Jun 28 06:37:15 PM PDT 24
Finished Jun 28 06:37:31 PM PDT 24
Peak memory 218612 kb
Host smart-167d5cdc-cd04-46ed-8ad6-70564de2e502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436307864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.1436307864
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.2667155403
Short name T43
Test name
Test status
Simulation time 56949194350 ps
CPU time 958.7 seconds
Started Jun 28 06:48:47 PM PDT 24
Finished Jun 28 07:06:38 PM PDT 24
Peak memory 275808 kb
Host smart-94045471-cf9c-4651-8193-260af203816e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2667155403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.2667155403
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.3896926049
Short name T10
Test name
Test status
Simulation time 1466694109 ps
CPU time 38.93 seconds
Started Jun 28 06:37:00 PM PDT 24
Finished Jun 28 06:37:40 PM PDT 24
Peak memory 275704 kb
Host smart-0a22f41b-3c6d-4763-a2c1-982229b5a39b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896926049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.3896926049
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2176641402
Short name T24
Test name
Test status
Simulation time 6735460444 ps
CPU time 37.76 seconds
Started Jun 28 06:37:13 PM PDT 24
Finished Jun 28 06:37:53 PM PDT 24
Peak memory 226296 kb
Host smart-e4b22961-1004-44a6-90da-87808dcff64c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176641402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2176641402
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2996129171
Short name T913
Test name
Test status
Simulation time 47097632 ps
CPU time 1.42 seconds
Started Jun 28 06:34:44 PM PDT 24
Finished Jun 28 06:34:47 PM PDT 24
Peak memory 216972 kb
Host smart-d0a07f9a-ba45-4593-9a80-8116263bf36c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996129171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.2996129171
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3127507618
Short name T919
Test name
Test status
Simulation time 35934969 ps
CPU time 0.95 seconds
Started Jun 28 06:34:43 PM PDT 24
Finished Jun 28 06:34:46 PM PDT 24
Peak memory 209464 kb
Host smart-47ed1e6a-e7b6-4b64-a409-a93f220039f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127507618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.3127507618
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.36848321
Short name T959
Test name
Test status
Simulation time 43848044 ps
CPU time 1.59 seconds
Started Jun 28 06:34:43 PM PDT 24
Finished Jun 28 06:34:47 PM PDT 24
Peak memory 217644 kb
Host smart-339a0d35-9ea8-45c5-9335-647cfb074a06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36848321 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.36848321
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.584753524
Short name T856
Test name
Test status
Simulation time 42230591 ps
CPU time 0.89 seconds
Started Jun 28 06:34:45 PM PDT 24
Finished Jun 28 06:34:48 PM PDT 24
Peak memory 209252 kb
Host smart-0e6241cb-7360-4333-9d69-c36f7df0ea6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584753524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.584753524
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3071518924
Short name T866
Test name
Test status
Simulation time 102386589 ps
CPU time 2.93 seconds
Started Jun 28 06:34:44 PM PDT 24
Finished Jun 28 06:34:49 PM PDT 24
Peak memory 209208 kb
Host smart-b57e9457-7db8-4eb4-ae22-c34ca35ae1bb
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071518924 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3071518924
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.193735564
Short name T865
Test name
Test status
Simulation time 1797145127 ps
CPU time 6.92 seconds
Started Jun 28 06:34:41 PM PDT 24
Finished Jun 28 06:34:49 PM PDT 24
Peak memory 217124 kb
Host smart-a5bd626f-e51f-40e5-9f32-7e7e8d322584
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193735564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.193735564
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2963799041
Short name T905
Test name
Test status
Simulation time 1467688978 ps
CPU time 4.66 seconds
Started Jun 28 06:34:43 PM PDT 24
Finished Jun 28 06:34:50 PM PDT 24
Peak memory 217044 kb
Host smart-a050fd31-1d69-414f-a3d9-c6c42a8d89ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963799041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2963799041
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.941054256
Short name T911
Test name
Test status
Simulation time 189344462 ps
CPU time 1.33 seconds
Started Jun 28 06:34:47 PM PDT 24
Finished Jun 28 06:34:50 PM PDT 24
Peak memory 217424 kb
Host smart-aa1149b4-02f3-401d-b015-c860909505e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941054256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.941054256
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3363355785
Short name T967
Test name
Test status
Simulation time 96245420 ps
CPU time 1.62 seconds
Started Jun 28 06:34:47 PM PDT 24
Finished Jun 28 06:34:50 PM PDT 24
Peak memory 218748 kb
Host smart-5b9f603c-de5f-4c4f-bf06-7dee049d1489
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336335
5785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3363355785
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3567969804
Short name T159
Test name
Test status
Simulation time 82444592 ps
CPU time 2.5 seconds
Started Jun 28 06:34:43 PM PDT 24
Finished Jun 28 06:34:48 PM PDT 24
Peak memory 209192 kb
Host smart-e5d0e600-9768-4d6e-92ec-decda7ba9bd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567969804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3567969804
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2279389628
Short name T890
Test name
Test status
Simulation time 41843328 ps
CPU time 1.22 seconds
Started Jun 28 06:34:49 PM PDT 24
Finished Jun 28 06:34:51 PM PDT 24
Peak memory 217596 kb
Host smart-b4eaf26b-d46e-4ff0-bb6d-465b4bc8af3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279389628 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.2279389628
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.4049289141
Short name T885
Test name
Test status
Simulation time 139978026 ps
CPU time 4.75 seconds
Started Jun 28 06:34:43 PM PDT 24
Finished Jun 28 06:34:50 PM PDT 24
Peak memory 217448 kb
Host smart-7718122c-84d4-4cf9-a4cb-2822ab02abad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049289141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.4049289141
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1192203087
Short name T144
Test name
Test status
Simulation time 114180980 ps
CPU time 2.19 seconds
Started Jun 28 06:34:42 PM PDT 24
Finished Jun 28 06:34:45 PM PDT 24
Peak memory 221652 kb
Host smart-75e640dc-6366-497e-b32f-e289173e4492
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192203087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.1192203087
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1231341970
Short name T920
Test name
Test status
Simulation time 28066021 ps
CPU time 1.18 seconds
Started Jun 28 06:34:45 PM PDT 24
Finished Jun 28 06:34:48 PM PDT 24
Peak memory 209380 kb
Host smart-86783738-c747-4a7a-8338-547b7ef2b90f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231341970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.1231341970
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1536967983
Short name T928
Test name
Test status
Simulation time 67013105 ps
CPU time 2.15 seconds
Started Jun 28 06:34:45 PM PDT 24
Finished Jun 28 06:34:50 PM PDT 24
Peak memory 209248 kb
Host smart-ead37edf-81fb-44a6-82e2-dd7883125251
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536967983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.1536967983
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2181290129
Short name T861
Test name
Test status
Simulation time 15044210 ps
CPU time 1.11 seconds
Started Jun 28 06:34:43 PM PDT 24
Finished Jun 28 06:34:46 PM PDT 24
Peak memory 209800 kb
Host smart-7257f7ab-74df-4df4-abde-7ef2db59cb4a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181290129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.2181290129
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1470014774
Short name T926
Test name
Test status
Simulation time 53663991 ps
CPU time 1.69 seconds
Started Jun 28 06:34:58 PM PDT 24
Finished Jun 28 06:35:00 PM PDT 24
Peak memory 217816 kb
Host smart-3e6915cc-7458-498e-b01b-55984a060e89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470014774 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1470014774
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.347928595
Short name T204
Test name
Test status
Simulation time 22906036 ps
CPU time 1.01 seconds
Started Jun 28 06:34:43 PM PDT 24
Finished Jun 28 06:34:46 PM PDT 24
Peak memory 209292 kb
Host smart-00a3a31f-ca71-41ee-b1c9-90f49889765a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347928595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.347928595
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1765050897
Short name T953
Test name
Test status
Simulation time 87952644 ps
CPU time 0.88 seconds
Started Jun 28 06:34:43 PM PDT 24
Finished Jun 28 06:34:46 PM PDT 24
Peak memory 209168 kb
Host smart-27e0a3ac-8fb1-47a7-86cd-e50be7640017
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765050897 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1765050897
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1130069062
Short name T979
Test name
Test status
Simulation time 333931383 ps
CPU time 8.09 seconds
Started Jun 28 06:34:43 PM PDT 24
Finished Jun 28 06:34:53 PM PDT 24
Peak memory 209096 kb
Host smart-bbc196ba-511f-45dc-b9ab-587dd0c0ed1d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130069062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1130069062
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.792615236
Short name T954
Test name
Test status
Simulation time 3320152862 ps
CPU time 12.01 seconds
Started Jun 28 06:34:49 PM PDT 24
Finished Jun 28 06:35:02 PM PDT 24
Peak memory 209296 kb
Host smart-95c2c00d-8db1-4187-8c3b-dc61dc058276
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792615236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.792615236
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1190083901
Short name T883
Test name
Test status
Simulation time 198443846 ps
CPU time 1.85 seconds
Started Jun 28 06:34:44 PM PDT 24
Finished Jun 28 06:34:48 PM PDT 24
Peak memory 217440 kb
Host smart-ce4b4f20-eb1d-43c0-bfc3-a2733d6aac54
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190083901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1190083901
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.650920094
Short name T889
Test name
Test status
Simulation time 215553204 ps
CPU time 2.13 seconds
Started Jun 28 06:34:44 PM PDT 24
Finished Jun 28 06:34:49 PM PDT 24
Peak memory 222176 kb
Host smart-fbfaf389-b766-4d70-9fea-8f7438372871
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650920
094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.650920094
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3842307724
Short name T901
Test name
Test status
Simulation time 88015641 ps
CPU time 2.5 seconds
Started Jun 28 06:34:46 PM PDT 24
Finished Jun 28 06:34:50 PM PDT 24
Peak memory 209256 kb
Host smart-ed9283bb-c8e0-4937-bde5-bffffaae09f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842307724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.3842307724
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.949578431
Short name T980
Test name
Test status
Simulation time 33738678 ps
CPU time 1.28 seconds
Started Jun 28 06:34:43 PM PDT 24
Finished Jun 28 06:34:47 PM PDT 24
Peak memory 209376 kb
Host smart-aec62aa1-477a-45b0-889b-6d7105373c2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949578431 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.949578431
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1757224002
Short name T169
Test name
Test status
Simulation time 27158468 ps
CPU time 1.44 seconds
Started Jun 28 06:34:43 PM PDT 24
Finished Jun 28 06:34:47 PM PDT 24
Peak memory 209388 kb
Host smart-0ac375da-f734-4baa-b79c-bd86facc873c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757224002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.1757224002
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3987216906
Short name T881
Test name
Test status
Simulation time 95029284 ps
CPU time 2.95 seconds
Started Jun 28 06:34:43 PM PDT 24
Finished Jun 28 06:34:48 PM PDT 24
Peak memory 217708 kb
Host smart-2882edab-9db1-4906-a6df-d808af8a58e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987216906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.3987216906
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3582018496
Short name T134
Test name
Test status
Simulation time 78282454 ps
CPU time 1.69 seconds
Started Jun 28 06:35:36 PM PDT 24
Finished Jun 28 06:35:42 PM PDT 24
Peak memory 217784 kb
Host smart-082a360c-3078-4c1e-a5f1-48a8c2561f43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582018496 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.3582018496
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2964239519
Short name T201
Test name
Test status
Simulation time 15823786 ps
CPU time 1.04 seconds
Started Jun 28 06:35:34 PM PDT 24
Finished Jun 28 06:35:40 PM PDT 24
Peak memory 209244 kb
Host smart-1eaec443-a5ff-44d4-8532-ff70d67ce051
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964239519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2964239519
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.979569539
Short name T211
Test name
Test status
Simulation time 89836781 ps
CPU time 1.08 seconds
Started Jun 28 06:35:37 PM PDT 24
Finished Jun 28 06:35:43 PM PDT 24
Peak memory 209384 kb
Host smart-bc3b668d-e4e9-4980-9b84-93c8a97fc411
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979569539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.979569539
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1294976667
Short name T903
Test name
Test status
Simulation time 313394806 ps
CPU time 2.71 seconds
Started Jun 28 06:35:33 PM PDT 24
Finished Jun 28 06:35:39 PM PDT 24
Peak memory 217632 kb
Host smart-652c62db-e5d7-47a7-ba0e-5d17c0f54a32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294976667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1294976667
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.837710888
Short name T171
Test name
Test status
Simulation time 39835210 ps
CPU time 1.42 seconds
Started Jun 28 06:35:36 PM PDT 24
Finished Jun 28 06:35:42 PM PDT 24
Peak memory 222280 kb
Host smart-c23e273f-148c-4724-87d4-48c2298fd17f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837710888 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.837710888
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2836496901
Short name T203
Test name
Test status
Simulation time 31113090 ps
CPU time 0.97 seconds
Started Jun 28 06:35:31 PM PDT 24
Finished Jun 28 06:35:36 PM PDT 24
Peak memory 209112 kb
Host smart-c212181e-c453-48a3-a584-c901525a9ac3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836496901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2836496901
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1442240710
Short name T924
Test name
Test status
Simulation time 29573485 ps
CPU time 1.55 seconds
Started Jun 28 06:35:34 PM PDT 24
Finished Jun 28 06:35:40 PM PDT 24
Peak memory 209328 kb
Host smart-6a135908-691d-4816-982d-f2e2b1b718db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442240710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1442240710
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.937797731
Short name T978
Test name
Test status
Simulation time 155025268 ps
CPU time 3.44 seconds
Started Jun 28 06:35:34 PM PDT 24
Finished Jun 28 06:35:42 PM PDT 24
Peak memory 217532 kb
Host smart-f8be5425-64f5-41fb-8125-55ad85d9adc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937797731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.937797731
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.785886873
Short name T170
Test name
Test status
Simulation time 17689182 ps
CPU time 1.23 seconds
Started Jun 28 06:35:34 PM PDT 24
Finished Jun 28 06:35:39 PM PDT 24
Peak memory 217564 kb
Host smart-ea5de693-a9f9-4d31-b382-8e8638f7416b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785886873 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.785886873
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.305308899
Short name T199
Test name
Test status
Simulation time 13897193 ps
CPU time 0.89 seconds
Started Jun 28 06:35:32 PM PDT 24
Finished Jun 28 06:35:37 PM PDT 24
Peak memory 209320 kb
Host smart-b9f83be1-7e9a-488a-b866-b317cb942fd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305308899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.305308899
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2104413829
Short name T984
Test name
Test status
Simulation time 77494463 ps
CPU time 1.32 seconds
Started Jun 28 06:35:33 PM PDT 24
Finished Jun 28 06:35:38 PM PDT 24
Peak memory 217632 kb
Host smart-ffe8ca7f-8597-40ad-a5bc-b0afeef414f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104413829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.2104413829
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.388450669
Short name T936
Test name
Test status
Simulation time 169800633 ps
CPU time 1.42 seconds
Started Jun 28 06:35:33 PM PDT 24
Finished Jun 28 06:35:38 PM PDT 24
Peak memory 218796 kb
Host smart-57fded85-3fbe-45e8-9c8f-3b9cd44c44f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388450669 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.388450669
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3213841571
Short name T198
Test name
Test status
Simulation time 16677168 ps
CPU time 1.11 seconds
Started Jun 28 06:35:34 PM PDT 24
Finished Jun 28 06:35:39 PM PDT 24
Peak memory 209320 kb
Host smart-bd6c21db-e70c-4d56-96ec-4c6a69a522cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213841571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3213841571
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.4232478624
Short name T876
Test name
Test status
Simulation time 26212414 ps
CPU time 1.16 seconds
Started Jun 28 06:35:35 PM PDT 24
Finished Jun 28 06:35:41 PM PDT 24
Peak memory 217644 kb
Host smart-24516952-5854-4c64-b1f0-6914f5da76ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232478624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.4232478624
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3799479585
Short name T947
Test name
Test status
Simulation time 76748065 ps
CPU time 3.37 seconds
Started Jun 28 06:35:34 PM PDT 24
Finished Jun 28 06:35:42 PM PDT 24
Peak memory 217532 kb
Host smart-e5c9fdb3-f83a-438d-9d4a-4a7255d6dd47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799479585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3799479585
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3587501634
Short name T950
Test name
Test status
Simulation time 43625076 ps
CPU time 1.6 seconds
Started Jun 28 06:35:34 PM PDT 24
Finished Jun 28 06:35:40 PM PDT 24
Peak memory 219260 kb
Host smart-c8d157f3-7d73-4b06-9424-937ea370ca05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587501634 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.3587501634
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1239442543
Short name T206
Test name
Test status
Simulation time 92185929 ps
CPU time 0.94 seconds
Started Jun 28 06:35:33 PM PDT 24
Finished Jun 28 06:35:37 PM PDT 24
Peak memory 208948 kb
Host smart-98668655-fb80-4d91-a9fe-074e075e34de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239442543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1239442543
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.857133906
Short name T982
Test name
Test status
Simulation time 69930881 ps
CPU time 1.32 seconds
Started Jun 28 06:35:36 PM PDT 24
Finished Jun 28 06:35:42 PM PDT 24
Peak memory 209384 kb
Host smart-224cb40c-8107-4255-97e0-df1d43819278
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857133906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.857133906
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1996804071
Short name T942
Test name
Test status
Simulation time 291775499 ps
CPU time 2.24 seconds
Started Jun 28 06:35:31 PM PDT 24
Finished Jun 28 06:35:37 PM PDT 24
Peak memory 217544 kb
Host smart-62bc5a87-8be6-4bea-8b25-7509e0f00faa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996804071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.1996804071
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1636604924
Short name T952
Test name
Test status
Simulation time 256235960 ps
CPU time 1.99 seconds
Started Jun 28 06:35:32 PM PDT 24
Finished Jun 28 06:35:38 PM PDT 24
Peak memory 221996 kb
Host smart-6226e997-5a1f-4f5d-9adf-fdb7872e521b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636604924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1636604924
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2790787939
Short name T975
Test name
Test status
Simulation time 44583884 ps
CPU time 1.3 seconds
Started Jun 28 06:35:34 PM PDT 24
Finished Jun 28 06:35:39 PM PDT 24
Peak memory 217720 kb
Host smart-65c72bf1-a09b-4128-8be3-e6b2633ebbf1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790787939 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2790787939
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2875994919
Short name T873
Test name
Test status
Simulation time 30233430 ps
CPU time 0.98 seconds
Started Jun 28 06:35:34 PM PDT 24
Finished Jun 28 06:35:39 PM PDT 24
Peak memory 209320 kb
Host smart-f72e2988-e3d8-4435-9cb9-a93f6265e3ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875994919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2875994919
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2823867714
Short name T212
Test name
Test status
Simulation time 42879187 ps
CPU time 1.39 seconds
Started Jun 28 06:35:33 PM PDT 24
Finished Jun 28 06:35:38 PM PDT 24
Peak memory 209368 kb
Host smart-6fc7950a-1e05-4201-859b-1d8b49b900ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823867714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.2823867714
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3512006100
Short name T925
Test name
Test status
Simulation time 127824926 ps
CPU time 3.16 seconds
Started Jun 28 06:35:34 PM PDT 24
Finished Jun 28 06:35:41 PM PDT 24
Peak memory 217648 kb
Host smart-6ef6cd5b-41e0-4da6-8866-10440203afe2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512006100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.3512006100
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2208972156
Short name T949
Test name
Test status
Simulation time 30923293 ps
CPU time 1.28 seconds
Started Jun 28 06:35:32 PM PDT 24
Finished Jun 28 06:35:37 PM PDT 24
Peak memory 217836 kb
Host smart-25993047-4889-4cbb-82f0-3d42df7a22fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208972156 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2208972156
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2269668608
Short name T971
Test name
Test status
Simulation time 17908787 ps
CPU time 0.94 seconds
Started Jun 28 06:35:33 PM PDT 24
Finished Jun 28 06:35:38 PM PDT 24
Peak memory 209296 kb
Host smart-047f241a-2346-42dd-938a-176816060bce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269668608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.2269668608
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2980496371
Short name T969
Test name
Test status
Simulation time 27944362 ps
CPU time 0.99 seconds
Started Jun 28 06:35:36 PM PDT 24
Finished Jun 28 06:35:42 PM PDT 24
Peak memory 209488 kb
Host smart-16772476-1212-41c7-8163-6916653d24e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980496371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2980496371
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2884730380
Short name T970
Test name
Test status
Simulation time 27291244 ps
CPU time 1.63 seconds
Started Jun 28 06:35:36 PM PDT 24
Finished Jun 28 06:35:42 PM PDT 24
Peak memory 217680 kb
Host smart-53164c8d-ef16-4d63-8840-ecf29888318e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884730380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.2884730380
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2585448200
Short name T877
Test name
Test status
Simulation time 160990446 ps
CPU time 2.03 seconds
Started Jun 28 06:35:33 PM PDT 24
Finished Jun 28 06:35:39 PM PDT 24
Peak memory 222004 kb
Host smart-e616d3bf-a6a2-4901-abe3-e6afd5325219
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585448200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.2585448200
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1641161711
Short name T898
Test name
Test status
Simulation time 28028186 ps
CPU time 1.59 seconds
Started Jun 28 06:35:32 PM PDT 24
Finished Jun 28 06:35:38 PM PDT 24
Peak memory 222504 kb
Host smart-1dccd41d-c687-42df-aff1-36c39c345297
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641161711 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1641161711
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1380814436
Short name T935
Test name
Test status
Simulation time 20767959 ps
CPU time 0.83 seconds
Started Jun 28 06:35:35 PM PDT 24
Finished Jun 28 06:35:40 PM PDT 24
Peak memory 209164 kb
Host smart-ca5c6b0a-fa62-4adc-ad44-9138bb0c4c28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380814436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1380814436
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2133341389
Short name T941
Test name
Test status
Simulation time 50382510 ps
CPU time 2.11 seconds
Started Jun 28 06:35:31 PM PDT 24
Finished Jun 28 06:35:36 PM PDT 24
Peak memory 209364 kb
Host smart-675a2f99-ce21-4499-9ec9-c1b2c919ca1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133341389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2133341389
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3680715096
Short name T138
Test name
Test status
Simulation time 143558381 ps
CPU time 2.42 seconds
Started Jun 28 06:35:35 PM PDT 24
Finished Jun 28 06:35:42 PM PDT 24
Peak memory 217492 kb
Host smart-789415e8-26b6-4a96-b030-38611cdfd3e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680715096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.3680715096
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3281431165
Short name T148
Test name
Test status
Simulation time 87967125 ps
CPU time 2.85 seconds
Started Jun 28 06:35:32 PM PDT 24
Finished Jun 28 06:35:39 PM PDT 24
Peak memory 222068 kb
Host smart-2f9b4a6e-6761-4bde-9da7-cc8abb91ee00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281431165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3281431165
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.311840621
Short name T872
Test name
Test status
Simulation time 52906868 ps
CPU time 0.95 seconds
Started Jun 28 06:35:45 PM PDT 24
Finished Jun 28 06:35:48 PM PDT 24
Peak memory 217748 kb
Host smart-3dd306b0-4f33-4c3f-a555-7a7a287c227a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311840621 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.311840621
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.904523691
Short name T923
Test name
Test status
Simulation time 44081512 ps
CPU time 1.04 seconds
Started Jun 28 06:35:42 PM PDT 24
Finished Jun 28 06:35:46 PM PDT 24
Peak memory 209100 kb
Host smart-5ef99d41-3556-4b17-bd0a-fd031722bcb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904523691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.904523691
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2011496637
Short name T966
Test name
Test status
Simulation time 43498965 ps
CPU time 1.43 seconds
Started Jun 28 06:35:42 PM PDT 24
Finished Jun 28 06:35:47 PM PDT 24
Peak memory 209492 kb
Host smart-3ea20402-6ff7-4c3b-939f-b89094e9a8c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011496637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.2011496637
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3212924831
Short name T140
Test name
Test status
Simulation time 154994214 ps
CPU time 2.56 seconds
Started Jun 28 06:35:41 PM PDT 24
Finished Jun 28 06:35:47 PM PDT 24
Peak memory 217692 kb
Host smart-0ac08b72-e10c-40f3-ba45-08e760ea099d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212924831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3212924831
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2654709711
Short name T860
Test name
Test status
Simulation time 201974309 ps
CPU time 1.82 seconds
Started Jun 28 06:35:40 PM PDT 24
Finished Jun 28 06:35:45 PM PDT 24
Peak memory 218732 kb
Host smart-2dced2fd-f4de-4d27-90e2-24a4711e7030
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654709711 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2654709711
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3487778981
Short name T857
Test name
Test status
Simulation time 50438462 ps
CPU time 0.89 seconds
Started Jun 28 06:35:43 PM PDT 24
Finished Jun 28 06:35:47 PM PDT 24
Peak memory 209196 kb
Host smart-e45dc3c2-5540-4ed0-a4b2-fecb496a8ad0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487778981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.3487778981
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.479273458
Short name T963
Test name
Test status
Simulation time 17148858 ps
CPU time 1.07 seconds
Started Jun 28 06:35:42 PM PDT 24
Finished Jun 28 06:35:46 PM PDT 24
Peak memory 209504 kb
Host smart-d660332f-2d13-4a6d-ae8a-d9aea996d264
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479273458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_same_csr_outstanding.479273458
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1423618438
Short name T909
Test name
Test status
Simulation time 168143245 ps
CPU time 2.69 seconds
Started Jun 28 06:35:44 PM PDT 24
Finished Jun 28 06:35:49 PM PDT 24
Peak memory 218400 kb
Host smart-104c05b4-9853-43a7-92a1-7547d6ecaa89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423618438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.1423618438
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1701389802
Short name T858
Test name
Test status
Simulation time 24097653 ps
CPU time 1.06 seconds
Started Jun 28 06:34:58 PM PDT 24
Finished Jun 28 06:35:00 PM PDT 24
Peak memory 217668 kb
Host smart-5731d801-218b-4147-80f7-bc669c2fd378
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701389802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.1701389802
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1146093406
Short name T871
Test name
Test status
Simulation time 106571775 ps
CPU time 3.34 seconds
Started Jun 28 06:35:01 PM PDT 24
Finished Jun 28 06:35:06 PM PDT 24
Peak memory 209272 kb
Host smart-835ce324-3d56-4dc6-9802-ac395f3fb529
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146093406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.1146093406
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1731184792
Short name T981
Test name
Test status
Simulation time 14395208 ps
CPU time 0.88 seconds
Started Jun 28 06:34:54 PM PDT 24
Finished Jun 28 06:34:57 PM PDT 24
Peak memory 209740 kb
Host smart-ecbcc45e-bfee-421f-b7cb-b618524f2f8a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731184792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.1731184792
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2139484654
Short name T964
Test name
Test status
Simulation time 59907285 ps
CPU time 1.26 seconds
Started Jun 28 06:34:54 PM PDT 24
Finished Jun 28 06:34:57 PM PDT 24
Peak memory 217644 kb
Host smart-8440887c-093a-481d-8abd-3ce9121edfc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139484654 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2139484654
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3001158781
Short name T209
Test name
Test status
Simulation time 13861207 ps
CPU time 1.05 seconds
Started Jun 28 06:34:51 PM PDT 24
Finished Jun 28 06:34:53 PM PDT 24
Peak memory 209320 kb
Host smart-ed6ed821-0cbd-4e50-9112-297c01ba74b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001158781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3001158781
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3191366771
Short name T921
Test name
Test status
Simulation time 125684080 ps
CPU time 1.38 seconds
Started Jun 28 06:34:58 PM PDT 24
Finished Jun 28 06:35:00 PM PDT 24
Peak memory 208908 kb
Host smart-c589810d-fcfb-4040-8acf-02c8d10522f6
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191366771 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3191366771
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.184535210
Short name T160
Test name
Test status
Simulation time 4785545430 ps
CPU time 25.79 seconds
Started Jun 28 06:34:51 PM PDT 24
Finished Jun 28 06:35:18 PM PDT 24
Peak memory 209260 kb
Host smart-06bede6b-1575-4e0a-b4f5-f7486975dfc5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184535210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.184535210
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.223613301
Short name T874
Test name
Test status
Simulation time 1715605767 ps
CPU time 8.08 seconds
Started Jun 28 06:34:54 PM PDT 24
Finished Jun 28 06:35:04 PM PDT 24
Peak memory 216876 kb
Host smart-9024ffc8-aa01-4fd2-a87f-6bbd24467e44
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223613301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.223613301
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4163447790
Short name T880
Test name
Test status
Simulation time 198870893 ps
CPU time 1.18 seconds
Started Jun 28 06:34:54 PM PDT 24
Finished Jun 28 06:34:57 PM PDT 24
Peak memory 217436 kb
Host smart-0baa9849-3f20-46af-b172-a683cbe8627c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163447790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.4163447790
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2779338499
Short name T917
Test name
Test status
Simulation time 58715691 ps
CPU time 1.57 seconds
Started Jun 28 06:34:59 PM PDT 24
Finished Jun 28 06:35:01 PM PDT 24
Peak memory 217812 kb
Host smart-8b524fa7-b03b-4efe-9f02-73dc48586604
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277933
8499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2779338499
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3097645233
Short name T965
Test name
Test status
Simulation time 55634929 ps
CPU time 2.04 seconds
Started Jun 28 06:34:55 PM PDT 24
Finished Jun 28 06:34:59 PM PDT 24
Peak memory 217348 kb
Host smart-271d8978-7c37-443b-b02f-472eb795818f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097645233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3097645233
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1270778290
Short name T927
Test name
Test status
Simulation time 38521931 ps
CPU time 1.85 seconds
Started Jun 28 06:35:01 PM PDT 24
Finished Jun 28 06:35:04 PM PDT 24
Peak memory 217592 kb
Host smart-8327aef3-ebf7-41ee-8303-076bd95b88f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270778290 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1270778290
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.570537132
Short name T207
Test name
Test status
Simulation time 21960157 ps
CPU time 1.17 seconds
Started Jun 28 06:34:51 PM PDT 24
Finished Jun 28 06:34:53 PM PDT 24
Peak memory 209484 kb
Host smart-ea04aaba-ee61-4126-9677-c36fe31501f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570537132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
same_csr_outstanding.570537132
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.978377657
Short name T146
Test name
Test status
Simulation time 99795155 ps
CPU time 2.93 seconds
Started Jun 28 06:34:52 PM PDT 24
Finished Jun 28 06:34:56 PM PDT 24
Peak memory 217524 kb
Host smart-721d7249-1d4d-432a-ae45-34ba42943ac2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978377657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.978377657
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1966022003
Short name T125
Test name
Test status
Simulation time 131436539 ps
CPU time 2.12 seconds
Started Jun 28 06:35:01 PM PDT 24
Finished Jun 28 06:35:04 PM PDT 24
Peak memory 222044 kb
Host smart-7cebbe7f-a26b-456c-b471-a02f7c499653
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966022003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1966022003
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1905533568
Short name T887
Test name
Test status
Simulation time 82793178 ps
CPU time 1.01 seconds
Started Jun 28 06:34:58 PM PDT 24
Finished Jun 28 06:35:00 PM PDT 24
Peak memory 209384 kb
Host smart-e1cc68cb-6362-4e5d-b603-e6dcfe98b6b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905533568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.1905533568
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.63548109
Short name T862
Test name
Test status
Simulation time 104474922 ps
CPU time 1.86 seconds
Started Jun 28 06:34:51 PM PDT 24
Finished Jun 28 06:34:54 PM PDT 24
Peak memory 217160 kb
Host smart-4664c668-e083-4f87-8e57-0097d9366ef5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63548109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bash.63548109
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.699460140
Short name T869
Test name
Test status
Simulation time 24727335 ps
CPU time 1.04 seconds
Started Jun 28 06:35:01 PM PDT 24
Finished Jun 28 06:35:03 PM PDT 24
Peak memory 209956 kb
Host smart-5a99670e-9543-4981-9a45-d0508707c279
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699460140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_reset
.699460140
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1147233776
Short name T864
Test name
Test status
Simulation time 15381769 ps
CPU time 0.99 seconds
Started Jun 28 06:35:04 PM PDT 24
Finished Jun 28 06:35:07 PM PDT 24
Peak memory 217700 kb
Host smart-a5330acb-23f0-4107-bc9c-c6c4d8d820b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147233776 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.1147233776
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2615308082
Short name T932
Test name
Test status
Simulation time 59587039 ps
CPU time 0.97 seconds
Started Jun 28 06:34:53 PM PDT 24
Finished Jun 28 06:34:55 PM PDT 24
Peak memory 209316 kb
Host smart-e72ef6de-9aa3-44b5-8a41-399a675018a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615308082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2615308082
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.55939714
Short name T951
Test name
Test status
Simulation time 478871065 ps
CPU time 2.21 seconds
Started Jun 28 06:34:54 PM PDT 24
Finished Jun 28 06:34:58 PM PDT 24
Peak memory 209208 kb
Host smart-d366d14f-2cc5-40cf-8a9d-0caf22868627
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55939714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_alert_test.55939714
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3677468461
Short name T910
Test name
Test status
Simulation time 227542134 ps
CPU time 3.22 seconds
Started Jun 28 06:34:54 PM PDT 24
Finished Jun 28 06:34:59 PM PDT 24
Peak memory 217028 kb
Host smart-0b357499-8c2c-4179-b8cf-db26e6f8b5e7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677468461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3677468461
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2589463936
Short name T948
Test name
Test status
Simulation time 1237828323 ps
CPU time 16.99 seconds
Started Jun 28 06:35:01 PM PDT 24
Finished Jun 28 06:35:19 PM PDT 24
Peak memory 209028 kb
Host smart-27486d33-760b-4aaa-9d80-0b58bfbd408e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589463936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.2589463936
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.41193912
Short name T974
Test name
Test status
Simulation time 375069201 ps
CPU time 1.98 seconds
Started Jun 28 06:34:54 PM PDT 24
Finished Jun 28 06:34:58 PM PDT 24
Peak memory 210872 kb
Host smart-e5ab3cd9-63f2-4104-9e89-95ac1d28e73d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41193912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.41193912
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1543931653
Short name T956
Test name
Test status
Simulation time 156057532 ps
CPU time 1.68 seconds
Started Jun 28 06:34:55 PM PDT 24
Finished Jun 28 06:34:58 PM PDT 24
Peak memory 209260 kb
Host smart-81e075a9-5ef3-4f56-9d46-f39dbce969b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543931653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.1543931653
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3831987101
Short name T895
Test name
Test status
Simulation time 125909811 ps
CPU time 1.45 seconds
Started Jun 28 06:34:53 PM PDT 24
Finished Jun 28 06:34:56 PM PDT 24
Peak memory 217588 kb
Host smart-a6c46f1a-c79f-42e7-9cc0-27756b3a709c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831987101 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3831987101
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.622805419
Short name T937
Test name
Test status
Simulation time 145446447 ps
CPU time 1.64 seconds
Started Jun 28 06:34:58 PM PDT 24
Finished Jun 28 06:35:01 PM PDT 24
Peak memory 217700 kb
Host smart-c16c9213-5391-43c2-b0ea-fa2f6db2e9c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622805419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.622805419
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3072136353
Short name T908
Test name
Test status
Simulation time 276698910 ps
CPU time 2.4 seconds
Started Jun 28 06:35:01 PM PDT 24
Finished Jun 28 06:35:05 PM PDT 24
Peak memory 217532 kb
Host smart-385702bc-b6ea-4d9c-b2ae-29b0de956b28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072136353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.3072136353
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1666823064
Short name T202
Test name
Test status
Simulation time 47520958 ps
CPU time 1.01 seconds
Started Jun 28 06:35:01 PM PDT 24
Finished Jun 28 06:35:03 PM PDT 24
Peak memory 209392 kb
Host smart-2aa23acd-cc55-430e-afd2-1d225ea1fbcd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666823064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.1666823064
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.4057163171
Short name T912
Test name
Test status
Simulation time 259522436 ps
CPU time 1.82 seconds
Started Jun 28 06:35:04 PM PDT 24
Finished Jun 28 06:35:08 PM PDT 24
Peak memory 209272 kb
Host smart-2b656897-1915-417d-a696-f895e199e422
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057163171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.4057163171
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.757936043
Short name T196
Test name
Test status
Simulation time 25910592 ps
CPU time 0.93 seconds
Started Jun 28 06:35:02 PM PDT 24
Finished Jun 28 06:35:04 PM PDT 24
Peak memory 209460 kb
Host smart-a9018221-b006-4abf-b7ac-49ea3bb9c30f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757936043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_reset
.757936043
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.81735517
Short name T938
Test name
Test status
Simulation time 134564801 ps
CPU time 1.58 seconds
Started Jun 28 06:35:15 PM PDT 24
Finished Jun 28 06:35:17 PM PDT 24
Peak memory 218268 kb
Host smart-8f07fa4f-2968-44b8-81a0-4d39f0240012
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81735517 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.81735517
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3803629974
Short name T867
Test name
Test status
Simulation time 15986968 ps
CPU time 0.91 seconds
Started Jun 28 06:35:02 PM PDT 24
Finished Jun 28 06:35:04 PM PDT 24
Peak memory 209292 kb
Host smart-1fe5ee54-3edc-45a6-a99f-915df222ac33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803629974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3803629974
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3940115441
Short name T859
Test name
Test status
Simulation time 127546951 ps
CPU time 2.3 seconds
Started Jun 28 06:35:02 PM PDT 24
Finished Jun 28 06:35:06 PM PDT 24
Peak memory 209236 kb
Host smart-38f83be4-a47a-4078-8ef0-34a64a53fba8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940115441 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3940115441
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.766616697
Short name T961
Test name
Test status
Simulation time 1325482087 ps
CPU time 8.8 seconds
Started Jun 28 06:35:05 PM PDT 24
Finished Jun 28 06:35:15 PM PDT 24
Peak memory 208980 kb
Host smart-7eb4ba2e-f151-43fe-a7ec-14d049168e2e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766616697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.766616697
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.930830869
Short name T878
Test name
Test status
Simulation time 8602625952 ps
CPU time 11.85 seconds
Started Jun 28 06:35:03 PM PDT 24
Finished Jun 28 06:35:17 PM PDT 24
Peak memory 209084 kb
Host smart-6f590b3c-eee6-4a17-b380-1d7964a559bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930830869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.930830869
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1598770727
Short name T899
Test name
Test status
Simulation time 513970610 ps
CPU time 2.82 seconds
Started Jun 28 06:35:03 PM PDT 24
Finished Jun 28 06:35:08 PM PDT 24
Peak memory 210696 kb
Host smart-43a2e5ba-187d-4241-b0c6-6c6e75158312
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598770727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.1598770727
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3472535103
Short name T879
Test name
Test status
Simulation time 464995122 ps
CPU time 3.95 seconds
Started Jun 28 06:35:04 PM PDT 24
Finished Jun 28 06:35:09 PM PDT 24
Peak memory 217736 kb
Host smart-09b8a4db-8f1e-42a0-8aa2-c46c23a69650
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347253
5103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3472535103
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.137199787
Short name T939
Test name
Test status
Simulation time 34460212 ps
CPU time 1.56 seconds
Started Jun 28 06:35:03 PM PDT 24
Finished Jun 28 06:35:06 PM PDT 24
Peak memory 209264 kb
Host smart-8ed606bc-5e97-424c-991e-7052899a1bc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137199787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.137199787
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3138212728
Short name T945
Test name
Test status
Simulation time 320535052 ps
CPU time 1.85 seconds
Started Jun 28 06:35:04 PM PDT 24
Finished Jun 28 06:35:08 PM PDT 24
Peak memory 209368 kb
Host smart-3a53dcb6-4c4e-4b7b-a537-1ed78d5f0db7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138212728 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.3138212728
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3609866942
Short name T892
Test name
Test status
Simulation time 20252583 ps
CPU time 1.22 seconds
Started Jun 28 06:35:12 PM PDT 24
Finished Jun 28 06:35:14 PM PDT 24
Peak memory 209508 kb
Host smart-e61fe94e-d1fb-4642-9190-d60bcd36a2fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609866942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.3609866942
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.89758985
Short name T142
Test name
Test status
Simulation time 416606140 ps
CPU time 4.2 seconds
Started Jun 28 06:35:01 PM PDT 24
Finished Jun 28 06:35:06 PM PDT 24
Peak memory 217492 kb
Host smart-fba1ec1b-9164-41fd-8262-11cf86308e98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89758985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.89758985
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.4171054762
Short name T918
Test name
Test status
Simulation time 18143131 ps
CPU time 1.5 seconds
Started Jun 28 06:35:15 PM PDT 24
Finished Jun 28 06:35:18 PM PDT 24
Peak memory 219528 kb
Host smart-755c25d9-50e0-4be8-90fb-a8084414216a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171054762 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.4171054762
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3792804537
Short name T197
Test name
Test status
Simulation time 31155010 ps
CPU time 1 seconds
Started Jun 28 06:35:20 PM PDT 24
Finished Jun 28 06:35:22 PM PDT 24
Peak memory 209240 kb
Host smart-34ed70ea-0d44-4e2a-8d08-d78b30fd71e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792804537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.3792804537
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.492251198
Short name T931
Test name
Test status
Simulation time 109851955 ps
CPU time 1.25 seconds
Started Jun 28 06:35:15 PM PDT 24
Finished Jun 28 06:35:17 PM PDT 24
Peak memory 209248 kb
Host smart-dbdb1fb4-0754-411d-ac46-a6b378bc3edb
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492251198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.lc_ctrl_jtag_alert_test.492251198
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.249830494
Short name T946
Test name
Test status
Simulation time 811835839 ps
CPU time 2.83 seconds
Started Jun 28 06:35:14 PM PDT 24
Finished Jun 28 06:35:18 PM PDT 24
Peak memory 208980 kb
Host smart-82c38ed1-512d-4d6c-b5bd-a1364f5b611a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249830494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.249830494
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1435053580
Short name T940
Test name
Test status
Simulation time 6830446374 ps
CPU time 18.88 seconds
Started Jun 28 06:35:14 PM PDT 24
Finished Jun 28 06:35:34 PM PDT 24
Peak memory 217300 kb
Host smart-8ad3f2e7-97ec-4a63-ab18-b6c29a84064e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435053580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1435053580
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2156026341
Short name T960
Test name
Test status
Simulation time 396781425 ps
CPU time 1.63 seconds
Started Jun 28 06:35:17 PM PDT 24
Finished Jun 28 06:35:20 PM PDT 24
Peak memory 217456 kb
Host smart-da2d586f-8d5f-42f1-912d-9cb82dc57c72
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156026341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2156026341
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3248744704
Short name T933
Test name
Test status
Simulation time 718785594 ps
CPU time 5.29 seconds
Started Jun 28 06:35:15 PM PDT 24
Finished Jun 28 06:35:21 PM PDT 24
Peak memory 222444 kb
Host smart-13622eb8-22b8-4701-9f7b-fa363b714e55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324874
4704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3248744704
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2934638973
Short name T882
Test name
Test status
Simulation time 167355719 ps
CPU time 1.26 seconds
Started Jun 28 06:35:15 PM PDT 24
Finished Jun 28 06:35:17 PM PDT 24
Peak memory 209256 kb
Host smart-54cf16f1-b9e9-468d-b4a2-3fd9a73c7990
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934638973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.2934638973
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2634171042
Short name T915
Test name
Test status
Simulation time 67814462 ps
CPU time 1.2 seconds
Started Jun 28 06:35:19 PM PDT 24
Finished Jun 28 06:35:21 PM PDT 24
Peak memory 211448 kb
Host smart-6d1b9aab-6a55-4483-bee4-6de70c21e7a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634171042 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.2634171042
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.359163850
Short name T955
Test name
Test status
Simulation time 48330764 ps
CPU time 1.48 seconds
Started Jun 28 06:35:20 PM PDT 24
Finished Jun 28 06:35:23 PM PDT 24
Peak memory 209312 kb
Host smart-a5de38fb-3682-4470-b053-4cf68e932db3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359163850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
same_csr_outstanding.359163850
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.228973583
Short name T973
Test name
Test status
Simulation time 50884486 ps
CPU time 1.82 seconds
Started Jun 28 06:35:20 PM PDT 24
Finished Jun 28 06:35:23 PM PDT 24
Peak memory 218476 kb
Host smart-197a889a-6013-455f-b6ff-228f84c7d04b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228973583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.228973583
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.4177507732
Short name T158
Test name
Test status
Simulation time 70604870 ps
CPU time 2.89 seconds
Started Jun 28 06:35:20 PM PDT 24
Finished Jun 28 06:35:24 PM PDT 24
Peak memory 222480 kb
Host smart-69eef2ee-58b6-4135-b786-c477a440306c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177507732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.4177507732
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.4138206830
Short name T976
Test name
Test status
Simulation time 42888815 ps
CPU time 1.75 seconds
Started Jun 28 06:35:15 PM PDT 24
Finished Jun 28 06:35:18 PM PDT 24
Peak memory 217716 kb
Host smart-fd9637b8-3bd9-4189-a498-c4281860dbba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138206830 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.4138206830
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1730199596
Short name T200
Test name
Test status
Simulation time 14028198 ps
CPU time 1.08 seconds
Started Jun 28 06:35:14 PM PDT 24
Finished Jun 28 06:35:16 PM PDT 24
Peak memory 209324 kb
Host smart-f00d2db7-12c4-4719-b257-141bae4995b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730199596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1730199596
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1145584745
Short name T891
Test name
Test status
Simulation time 52095606 ps
CPU time 1.89 seconds
Started Jun 28 06:35:19 PM PDT 24
Finished Jun 28 06:35:22 PM PDT 24
Peak memory 209240 kb
Host smart-dca30d58-9d23-4ff4-a14e-28ff77991508
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145584745 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1145584745
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1454295788
Short name T870
Test name
Test status
Simulation time 472904815 ps
CPU time 11.17 seconds
Started Jun 28 06:35:14 PM PDT 24
Finished Jun 28 06:35:26 PM PDT 24
Peak memory 217104 kb
Host smart-9ff7d408-28aa-4ad3-b90d-3fb32a29fac8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454295788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1454295788
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.816892738
Short name T907
Test name
Test status
Simulation time 5421049636 ps
CPU time 9.78 seconds
Started Jun 28 06:35:15 PM PDT 24
Finished Jun 28 06:35:26 PM PDT 24
Peak memory 209284 kb
Host smart-d60c24ab-0423-4d2b-85be-08b59d21f2c8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816892738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.816892738
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4239562274
Short name T904
Test name
Test status
Simulation time 60856410 ps
CPU time 2.07 seconds
Started Jun 28 06:35:22 PM PDT 24
Finished Jun 28 06:35:25 PM PDT 24
Peak memory 210696 kb
Host smart-d7aad9fd-8920-4093-849b-9be141b4cc33
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239562274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.4239562274
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3268580781
Short name T929
Test name
Test status
Simulation time 56057188 ps
CPU time 2.8 seconds
Started Jun 28 06:35:15 PM PDT 24
Finished Jun 28 06:35:19 PM PDT 24
Peak memory 217732 kb
Host smart-1d4b4975-5718-416c-96a1-e39eab0a71f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326858
0781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3268580781
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3044405941
Short name T896
Test name
Test status
Simulation time 136128839 ps
CPU time 1.52 seconds
Started Jun 28 06:35:14 PM PDT 24
Finished Jun 28 06:35:16 PM PDT 24
Peak memory 209228 kb
Host smart-8cccc1b2-5ae4-494c-b8f8-316e4fa4e1b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044405941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.3044405941
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1451364896
Short name T888
Test name
Test status
Simulation time 274628034 ps
CPU time 2.01 seconds
Started Jun 28 06:35:14 PM PDT 24
Finished Jun 28 06:35:17 PM PDT 24
Peak memory 209400 kb
Host smart-b9536857-2a0c-4f16-a202-420a9eef3020
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451364896 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1451364896
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.30239677
Short name T135
Test name
Test status
Simulation time 38100973 ps
CPU time 1.48 seconds
Started Jun 28 06:35:19 PM PDT 24
Finished Jun 28 06:35:21 PM PDT 24
Peak memory 217668 kb
Host smart-d242ff40-ba91-40a8-b77c-b7e8cf30ce7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30239677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_s
ame_csr_outstanding.30239677
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.4247848254
Short name T944
Test name
Test status
Simulation time 93226505 ps
CPU time 1.86 seconds
Started Jun 28 06:35:13 PM PDT 24
Finished Jun 28 06:35:16 PM PDT 24
Peak memory 217616 kb
Host smart-ba658944-aef4-49b4-a291-87dca81bf42e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247848254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.4247848254
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3971106527
Short name T132
Test name
Test status
Simulation time 52944695 ps
CPU time 0.99 seconds
Started Jun 28 06:35:23 PM PDT 24
Finished Jun 28 06:35:25 PM PDT 24
Peak memory 217620 kb
Host smart-b4b61238-20ea-4b35-aa10-defc7ddaa842
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971106527 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3971106527
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3150144817
Short name T930
Test name
Test status
Simulation time 49768375 ps
CPU time 0.86 seconds
Started Jun 28 06:35:23 PM PDT 24
Finished Jun 28 06:35:26 PM PDT 24
Peak memory 209196 kb
Host smart-75b32065-b608-4dff-99d8-8e9333d2af13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150144817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.3150144817
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3265326451
Short name T962
Test name
Test status
Simulation time 45989013 ps
CPU time 1.84 seconds
Started Jun 28 06:35:25 PM PDT 24
Finished Jun 28 06:35:30 PM PDT 24
Peak memory 209244 kb
Host smart-1aabcddc-72f9-463a-abd9-7a94d064f38d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265326451 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3265326451
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.665315975
Short name T863
Test name
Test status
Simulation time 664237951 ps
CPU time 6.61 seconds
Started Jun 28 06:35:24 PM PDT 24
Finished Jun 28 06:35:33 PM PDT 24
Peak memory 216944 kb
Host smart-2f03dd3e-0d34-4bf9-82be-c96f610af716
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665315975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.665315975
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2855335054
Short name T958
Test name
Test status
Simulation time 4965923940 ps
CPU time 31.45 seconds
Started Jun 28 06:35:23 PM PDT 24
Finished Jun 28 06:35:56 PM PDT 24
Peak memory 209268 kb
Host smart-58288007-6894-454c-bf14-64a2728990be
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855335054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2855335054
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1107315003
Short name T943
Test name
Test status
Simulation time 410748816 ps
CPU time 3.09 seconds
Started Jun 28 06:35:15 PM PDT 24
Finished Jun 28 06:35:19 PM PDT 24
Peak memory 210952 kb
Host smart-2b7f687c-e0bd-4472-aa35-64447b444450
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107315003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1107315003
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2633770083
Short name T151
Test name
Test status
Simulation time 377048733 ps
CPU time 1.97 seconds
Started Jun 28 06:35:24 PM PDT 24
Finished Jun 28 06:35:29 PM PDT 24
Peak memory 217644 kb
Host smart-1f410c8d-1597-444c-84ac-cc5729a5d0e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263377
0083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2633770083
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1904927275
Short name T906
Test name
Test status
Simulation time 45814665 ps
CPU time 1.76 seconds
Started Jun 28 06:35:22 PM PDT 24
Finished Jun 28 06:35:26 PM PDT 24
Peak memory 209256 kb
Host smart-a1bdfb6b-6cab-4bdb-a246-d8ad79beb2a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904927275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.1904927275
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2580905948
Short name T914
Test name
Test status
Simulation time 17419466 ps
CPU time 1.22 seconds
Started Jun 28 06:35:26 PM PDT 24
Finished Jun 28 06:35:30 PM PDT 24
Peak memory 209360 kb
Host smart-7e8c920f-d8ea-4a2e-85bf-1abb0de910d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580905948 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2580905948
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3577590093
Short name T143
Test name
Test status
Simulation time 79363690 ps
CPU time 1.38 seconds
Started Jun 28 06:35:26 PM PDT 24
Finished Jun 28 06:35:29 PM PDT 24
Peak memory 209388 kb
Host smart-97e6c293-d921-4740-846f-0d4296d36ac0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577590093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3577590093
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1634620205
Short name T902
Test name
Test status
Simulation time 120138216 ps
CPU time 2.5 seconds
Started Jun 28 06:35:26 PM PDT 24
Finished Jun 28 06:35:31 PM PDT 24
Peak memory 217532 kb
Host smart-8955f6a8-19d5-4ca4-a9c4-3269806ec54e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634620205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1634620205
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.691970708
Short name T968
Test name
Test status
Simulation time 25221466 ps
CPU time 1.15 seconds
Started Jun 28 06:35:24 PM PDT 24
Finished Jun 28 06:35:28 PM PDT 24
Peak memory 217700 kb
Host smart-e4917df8-9c2c-43dd-b94f-a25ca98fb978
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691970708 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.691970708
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1714574194
Short name T897
Test name
Test status
Simulation time 13525818 ps
CPU time 1.03 seconds
Started Jun 28 06:35:23 PM PDT 24
Finished Jun 28 06:35:26 PM PDT 24
Peak memory 209324 kb
Host smart-6b883492-ea3f-4376-a637-63de540da3aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714574194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.1714574194
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1471530920
Short name T886
Test name
Test status
Simulation time 100403752 ps
CPU time 1.89 seconds
Started Jun 28 06:35:23 PM PDT 24
Finished Jun 28 06:35:27 PM PDT 24
Peak memory 209228 kb
Host smart-19db9191-0857-4228-a1fa-8a83a22fe651
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471530920 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.1471530920
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.14724089
Short name T855
Test name
Test status
Simulation time 3124691972 ps
CPU time 11.89 seconds
Started Jun 28 06:35:22 PM PDT 24
Finished Jun 28 06:35:36 PM PDT 24
Peak memory 217328 kb
Host smart-cdf3ef26-e427-4a1e-829e-fcb96922f947
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14724089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.lc_ctrl_jtag_csr_aliasing.14724089
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1604687355
Short name T868
Test name
Test status
Simulation time 694687612 ps
CPU time 8.55 seconds
Started Jun 28 06:35:23 PM PDT 24
Finished Jun 28 06:35:33 PM PDT 24
Peak memory 216992 kb
Host smart-3fc344ee-ec33-42ce-acba-fa1a38c6a847
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604687355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.1604687355
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2835735196
Short name T875
Test name
Test status
Simulation time 112968028 ps
CPU time 1.4 seconds
Started Jun 28 06:35:22 PM PDT 24
Finished Jun 28 06:35:25 PM PDT 24
Peak memory 210688 kb
Host smart-4d135a55-00ff-48a0-8b66-076fcea6f609
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835735196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2835735196
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1630331689
Short name T957
Test name
Test status
Simulation time 89826699 ps
CPU time 3.15 seconds
Started Jun 28 06:35:24 PM PDT 24
Finished Jun 28 06:35:29 PM PDT 24
Peak memory 217776 kb
Host smart-60f47534-e5fd-47e4-bc80-51907e7831cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163033
1689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1630331689
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.566338873
Short name T894
Test name
Test status
Simulation time 96646942 ps
CPU time 1.39 seconds
Started Jun 28 06:35:24 PM PDT 24
Finished Jun 28 06:35:27 PM PDT 24
Peak memory 217396 kb
Host smart-ecb1ff77-ff4c-4417-817b-f250503eaaa5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566338873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.566338873
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1716359897
Short name T972
Test name
Test status
Simulation time 72563457 ps
CPU time 1.44 seconds
Started Jun 28 06:35:21 PM PDT 24
Finished Jun 28 06:35:23 PM PDT 24
Peak memory 211604 kb
Host smart-8209590e-bea2-4a64-8893-8ee580714296
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716359897 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.1716359897
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3598643091
Short name T168
Test name
Test status
Simulation time 116235216 ps
CPU time 1.35 seconds
Started Jun 28 06:35:29 PM PDT 24
Finished Jun 28 06:35:33 PM PDT 24
Peak memory 209412 kb
Host smart-2dd272d5-9f58-480c-ac85-97c868462762
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598643091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.3598643091
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2259109117
Short name T900
Test name
Test status
Simulation time 100378102 ps
CPU time 4.25 seconds
Started Jun 28 06:35:24 PM PDT 24
Finished Jun 28 06:35:30 PM PDT 24
Peak memory 217564 kb
Host smart-ecdfcb49-112b-40e9-9200-e8e476510620
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259109117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.2259109117
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2227265932
Short name T127
Test name
Test status
Simulation time 162714219 ps
CPU time 1.9 seconds
Started Jun 28 06:35:26 PM PDT 24
Finished Jun 28 06:35:31 PM PDT 24
Peak memory 222080 kb
Host smart-03459e4c-26a8-493a-b8e8-d5486da56787
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227265932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2227265932
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2953748366
Short name T893
Test name
Test status
Simulation time 176169226 ps
CPU time 1.28 seconds
Started Jun 28 06:35:37 PM PDT 24
Finished Jun 28 06:35:42 PM PDT 24
Peak memory 217644 kb
Host smart-57928264-c928-42a2-a2fa-5c54b3a293d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953748366 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2953748366
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3165770164
Short name T208
Test name
Test status
Simulation time 13561792 ps
CPU time 0.84 seconds
Started Jun 28 06:35:34 PM PDT 24
Finished Jun 28 06:35:38 PM PDT 24
Peak memory 209168 kb
Host smart-4af3f9e7-f7c2-410b-907c-e38fc980baeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165770164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3165770164
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3904494370
Short name T161
Test name
Test status
Simulation time 17755088 ps
CPU time 0.9 seconds
Started Jun 28 06:35:23 PM PDT 24
Finished Jun 28 06:35:26 PM PDT 24
Peak memory 208616 kb
Host smart-ab071e8a-6280-4fed-8e39-ad973aa93ead
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904494370 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.3904494370
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2127770746
Short name T854
Test name
Test status
Simulation time 1640645371 ps
CPU time 4.49 seconds
Started Jun 28 06:35:26 PM PDT 24
Finished Jun 28 06:35:33 PM PDT 24
Peak memory 208984 kb
Host smart-bccabe2d-5b17-44af-90d7-74a52ad02439
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127770746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2127770746
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.549875392
Short name T934
Test name
Test status
Simulation time 5352338355 ps
CPU time 5.48 seconds
Started Jun 28 06:35:25 PM PDT 24
Finished Jun 28 06:35:33 PM PDT 24
Peak memory 209232 kb
Host smart-8ec7d49c-26e5-402e-8ad2-9b0a88bfb1fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549875392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.549875392
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3613428347
Short name T916
Test name
Test status
Simulation time 266541617 ps
CPU time 3.95 seconds
Started Jun 28 06:35:26 PM PDT 24
Finished Jun 28 06:35:33 PM PDT 24
Peak memory 210968 kb
Host smart-81257cf4-96b1-4664-8187-0c37531d1b88
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613428347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3613428347
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1596628900
Short name T133
Test name
Test status
Simulation time 940588956 ps
CPU time 3.44 seconds
Started Jun 28 06:35:25 PM PDT 24
Finished Jun 28 06:35:31 PM PDT 24
Peak memory 218748 kb
Host smart-0d6e8a23-d958-467a-9667-4c9af216e0c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159662
8900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1596628900
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1367938308
Short name T977
Test name
Test status
Simulation time 138835397 ps
CPU time 1.13 seconds
Started Jun 28 06:35:25 PM PDT 24
Finished Jun 28 06:35:28 PM PDT 24
Peak memory 209048 kb
Host smart-dd411530-5267-43e3-a188-f55a5f571db1
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367938308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1367938308
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3716586264
Short name T922
Test name
Test status
Simulation time 208281309 ps
CPU time 1.51 seconds
Started Jun 28 06:35:29 PM PDT 24
Finished Jun 28 06:35:33 PM PDT 24
Peak memory 211496 kb
Host smart-1441b104-695c-4ef6-af19-4f9f9d987690
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716586264 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3716586264
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3881866540
Short name T983
Test name
Test status
Simulation time 86580346 ps
CPU time 1.05 seconds
Started Jun 28 06:35:32 PM PDT 24
Finished Jun 28 06:35:37 PM PDT 24
Peak memory 209344 kb
Host smart-0d6f5af9-a79e-4b81-9c65-108410b22170
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881866540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.3881866540
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1677606477
Short name T884
Test name
Test status
Simulation time 175676494 ps
CPU time 2.54 seconds
Started Jun 28 06:35:25 PM PDT 24
Finished Jun 28 06:35:30 PM PDT 24
Peak memory 217532 kb
Host smart-9381862a-1403-4454-9e10-af5bd53f9690
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677606477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1677606477
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.4023224716
Short name T141
Test name
Test status
Simulation time 195801806 ps
CPU time 2.65 seconds
Started Jun 28 06:35:25 PM PDT 24
Finished Jun 28 06:35:31 PM PDT 24
Peak memory 222452 kb
Host smart-721e96e1-c69c-4889-bdc1-d54fddc7185f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023224716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.4023224716
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.2755800740
Short name T111
Test name
Test status
Simulation time 53931270 ps
CPU time 1.07 seconds
Started Jun 28 06:37:01 PM PDT 24
Finished Jun 28 06:37:04 PM PDT 24
Peak memory 209140 kb
Host smart-0cdf2d61-4def-428b-bac4-c020314aee97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755800740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2755800740
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.2621449547
Short name T444
Test name
Test status
Simulation time 41853135 ps
CPU time 0.91 seconds
Started Jun 28 06:37:02 PM PDT 24
Finished Jun 28 06:37:05 PM PDT 24
Peak memory 209212 kb
Host smart-dae61d4b-1059-4700-836c-25245a1d5734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621449547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.2621449547
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.2413058549
Short name T482
Test name
Test status
Simulation time 4357108790 ps
CPU time 12 seconds
Started Jun 28 06:37:01 PM PDT 24
Finished Jun 28 06:37:14 PM PDT 24
Peak memory 226316 kb
Host smart-fc5692c7-5e0f-41e7-9f99-bc526c194d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413058549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2413058549
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.1788341316
Short name T30
Test name
Test status
Simulation time 5076740584 ps
CPU time 27.15 seconds
Started Jun 28 06:37:01 PM PDT 24
Finished Jun 28 06:37:31 PM PDT 24
Peak memory 217984 kb
Host smart-0e167879-6dfb-47d8-b75b-c88f6cc17f1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788341316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.1788341316
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3973059180
Short name T236
Test name
Test status
Simulation time 10332617842 ps
CPU time 37.58 seconds
Started Jun 28 06:37:00 PM PDT 24
Finished Jun 28 06:37:38 PM PDT 24
Peak memory 219168 kb
Host smart-517c0c87-cff0-40e8-8f72-5cd7e5cf85c2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973059180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3973059180
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1829071768
Short name T764
Test name
Test status
Simulation time 605971335 ps
CPU time 7.22 seconds
Started Jun 28 06:37:02 PM PDT 24
Finished Jun 28 06:37:12 PM PDT 24
Peak memory 217540 kb
Host smart-e51ff20b-0525-4709-af30-53c679437143
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829071768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
829071768
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3934636007
Short name T458
Test name
Test status
Simulation time 243911660 ps
CPU time 4.91 seconds
Started Jun 28 06:37:01 PM PDT 24
Finished Jun 28 06:37:08 PM PDT 24
Peak memory 223116 kb
Host smart-d32eb452-5846-488d-8144-31e01712411d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934636007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3934636007
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2578868160
Short name T777
Test name
Test status
Simulation time 1303490348 ps
CPU time 10.3 seconds
Started Jun 28 06:37:03 PM PDT 24
Finished Jun 28 06:37:16 PM PDT 24
Peak memory 217868 kb
Host smart-e58e9f4c-4f9e-43a4-996c-9c60c3f71ac5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578868160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.2578868160
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.4025073739
Short name T496
Test name
Test status
Simulation time 2106055725 ps
CPU time 5.38 seconds
Started Jun 28 06:37:02 PM PDT 24
Finished Jun 28 06:37:10 PM PDT 24
Peak memory 217920 kb
Host smart-f0102d5e-8c32-4e72-bfe2-93269dc9ffdb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025073739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
4025073739
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2678528863
Short name T539
Test name
Test status
Simulation time 401136063 ps
CPU time 17.53 seconds
Started Jun 28 06:37:02 PM PDT 24
Finished Jun 28 06:37:22 PM PDT 24
Peak memory 246824 kb
Host smart-b6267200-3140-41fa-b752-6d8be7facaf8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678528863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.2678528863
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1106875336
Short name T93
Test name
Test status
Simulation time 27513703 ps
CPU time 1.81 seconds
Started Jun 28 06:36:48 PM PDT 24
Finished Jun 28 06:36:51 PM PDT 24
Peak memory 218412 kb
Host smart-6b100986-da68-4a81-9c26-30fa5be4ab4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106875336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1106875336
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1306842377
Short name T612
Test name
Test status
Simulation time 1151871217 ps
CPU time 19.37 seconds
Started Jun 28 06:37:01 PM PDT 24
Finished Jun 28 06:37:22 PM PDT 24
Peak memory 217852 kb
Host smart-f12fcd1f-fd8a-49df-825f-ac52bc1164a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306842377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1306842377
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.268343434
Short name T87
Test name
Test status
Simulation time 120565884 ps
CPU time 24.79 seconds
Started Jun 28 06:37:01 PM PDT 24
Finished Jun 28 06:37:27 PM PDT 24
Peak memory 269304 kb
Host smart-7fd216f9-dbc3-4030-afa7-115e518c97ce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268343434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.268343434
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.1334956468
Short name T582
Test name
Test status
Simulation time 304796610 ps
CPU time 10.84 seconds
Started Jun 28 06:37:03 PM PDT 24
Finished Jun 28 06:37:17 PM PDT 24
Peak memory 226208 kb
Host smart-3cf2910d-4f07-46a7-96cf-21f8caecb913
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334956468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.1334956468
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1115439355
Short name T402
Test name
Test status
Simulation time 473290659 ps
CPU time 17 seconds
Started Jun 28 06:37:02 PM PDT 24
Finished Jun 28 06:37:22 PM PDT 24
Peak memory 218464 kb
Host smart-d7a75269-1d28-4561-b913-5f49e6e0b196
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115439355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.1115439355
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.519146704
Short name T448
Test name
Test status
Simulation time 1174032156 ps
CPU time 11.67 seconds
Started Jun 28 06:37:03 PM PDT 24
Finished Jun 28 06:37:18 PM PDT 24
Peak memory 218432 kb
Host smart-9710c177-2909-4b01-b969-05d1fb860df4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519146704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.519146704
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.1856973581
Short name T696
Test name
Test status
Simulation time 1625299887 ps
CPU time 10.76 seconds
Started Jun 28 06:37:04 PM PDT 24
Finished Jun 28 06:37:17 PM PDT 24
Peak memory 218476 kb
Host smart-382dd160-e59b-4153-b990-506ced26b466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856973581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.1856973581
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.4098105016
Short name T73
Test name
Test status
Simulation time 422627679 ps
CPU time 6.23 seconds
Started Jun 28 06:36:45 PM PDT 24
Finished Jun 28 06:36:53 PM PDT 24
Peak memory 217932 kb
Host smart-3d11d74f-78de-4b4d-b55f-371269fa91d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098105016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.4098105016
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.1312123005
Short name T178
Test name
Test status
Simulation time 666676541 ps
CPU time 17.63 seconds
Started Jun 28 06:36:47 PM PDT 24
Finished Jun 28 06:37:06 PM PDT 24
Peak memory 251140 kb
Host smart-d93056c1-e7e8-448a-9740-910d0fcebe84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312123005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1312123005
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.4096196960
Short name T576
Test name
Test status
Simulation time 65533469 ps
CPU time 6.08 seconds
Started Jun 28 06:36:46 PM PDT 24
Finished Jun 28 06:36:53 PM PDT 24
Peak memory 246992 kb
Host smart-dc19e98c-fcaa-4d34-ab7a-03715e51869a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096196960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.4096196960
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.3170488779
Short name T729
Test name
Test status
Simulation time 30249587865 ps
CPU time 192.38 seconds
Started Jun 28 06:37:03 PM PDT 24
Finished Jun 28 06:40:18 PM PDT 24
Peak memory 267488 kb
Host smart-6fc688cf-6705-41dc-b12f-2219dc6ba64d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170488779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.3170488779
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.603673813
Short name T563
Test name
Test status
Simulation time 14254829 ps
CPU time 1.09 seconds
Started Jun 28 06:36:44 PM PDT 24
Finished Jun 28 06:36:47 PM PDT 24
Peak memory 212036 kb
Host smart-9cf378cd-e226-42c9-b76e-aec368e5d3a8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603673813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr
l_volatile_unlock_smoke.603673813
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3970247439
Short name T176
Test name
Test status
Simulation time 26977571 ps
CPU time 1.34 seconds
Started Jun 28 06:37:15 PM PDT 24
Finished Jun 28 06:37:19 PM PDT 24
Peak memory 209176 kb
Host smart-59ade69a-b898-47c4-a8b2-ddc9532d5d4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970247439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3970247439
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.3566070912
Short name T555
Test name
Test status
Simulation time 1460913882 ps
CPU time 10.38 seconds
Started Jun 28 06:37:02 PM PDT 24
Finished Jun 28 06:37:16 PM PDT 24
Peak memory 226256 kb
Host smart-74a5e611-cdab-4398-baf1-33aa26b86ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566070912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.3566070912
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1138165276
Short name T589
Test name
Test status
Simulation time 150560282 ps
CPU time 4.46 seconds
Started Jun 28 06:37:16 PM PDT 24
Finished Jun 28 06:37:23 PM PDT 24
Peak memory 217300 kb
Host smart-e8638654-9998-4a25-a801-cc411c6d3e27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138165276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1138165276
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.570619085
Short name T473
Test name
Test status
Simulation time 1195444335 ps
CPU time 5.77 seconds
Started Jun 28 06:37:12 PM PDT 24
Finished Jun 28 06:37:19 PM PDT 24
Peak memory 217756 kb
Host smart-5542d6b6-c5a5-4551-a5d2-256c4bfb4dcc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570619085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.570619085
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2248138436
Short name T274
Test name
Test status
Simulation time 780594847 ps
CPU time 10.49 seconds
Started Jun 28 06:37:03 PM PDT 24
Finished Jun 28 06:37:16 PM PDT 24
Peak memory 218436 kb
Host smart-e3cf0898-edef-4bfa-b845-0588bf6723dc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248138436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2248138436
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.601562069
Short name T6
Test name
Test status
Simulation time 1850068439 ps
CPU time 12.94 seconds
Started Jun 28 06:37:14 PM PDT 24
Finished Jun 28 06:37:29 PM PDT 24
Peak memory 217920 kb
Host smart-4d193679-14f4-423c-9f96-0f94b112a07d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601562069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_regwen_during_op.601562069
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.1186070819
Short name T686
Test name
Test status
Simulation time 1084205826 ps
CPU time 8.29 seconds
Started Jun 28 06:37:01 PM PDT 24
Finished Jun 28 06:37:12 PM PDT 24
Peak memory 217916 kb
Host smart-57546664-0367-41ab-90f9-76e18c1e53ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186070819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
1186070819
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.1313203855
Short name T718
Test name
Test status
Simulation time 6417856884 ps
CPU time 39.78 seconds
Started Jun 28 06:37:03 PM PDT 24
Finished Jun 28 06:37:46 PM PDT 24
Peak memory 267460 kb
Host smart-c00458f2-6ca1-485d-b86f-c3afd6b4fa94
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313203855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.1313203855
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.164275113
Short name T20
Test name
Test status
Simulation time 2588988222 ps
CPU time 16.29 seconds
Started Jun 28 06:37:03 PM PDT 24
Finished Jun 28 06:37:23 PM PDT 24
Peak memory 251068 kb
Host smart-3bb159fd-fb84-4833-89e5-d12433aec36e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164275113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_state_post_trans.164275113
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.888986176
Short name T640
Test name
Test status
Simulation time 68254781 ps
CPU time 1.84 seconds
Started Jun 28 06:37:04 PM PDT 24
Finished Jun 28 06:37:09 PM PDT 24
Peak memory 218436 kb
Host smart-7553afc7-2a82-4c66-a97f-28286fe7c036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888986176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.888986176
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.3130376154
Short name T213
Test name
Test status
Simulation time 225063297 ps
CPU time 5.44 seconds
Started Jun 28 06:37:02 PM PDT 24
Finished Jun 28 06:37:11 PM PDT 24
Peak memory 217928 kb
Host smart-004f8c87-d63d-46f1-a2e9-11f3c60083c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130376154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3130376154
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.4108655220
Short name T541
Test name
Test status
Simulation time 378228757 ps
CPU time 12.96 seconds
Started Jun 28 06:37:13 PM PDT 24
Finished Jun 28 06:37:28 PM PDT 24
Peak memory 226244 kb
Host smart-0c48eec2-ca85-49f0-8037-d2ec894e99fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108655220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.4108655220
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.2174543287
Short name T385
Test name
Test status
Simulation time 572702318 ps
CPU time 7.34 seconds
Started Jun 28 06:37:12 PM PDT 24
Finished Jun 28 06:37:21 PM PDT 24
Peak memory 218472 kb
Host smart-bfebca9a-b0ff-4d6d-8946-8af20fc6a86a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174543287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.2174543287
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.1127642754
Short name T355
Test name
Test status
Simulation time 207288498 ps
CPU time 5.77 seconds
Started Jun 28 06:37:13 PM PDT 24
Finished Jun 28 06:37:20 PM PDT 24
Peak memory 225040 kb
Host smart-ff23ca64-edc3-432b-9881-687b9edd4f3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127642754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.1
127642754
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.1689825685
Short name T827
Test name
Test status
Simulation time 907791554 ps
CPU time 8.3 seconds
Started Jun 28 06:37:02 PM PDT 24
Finished Jun 28 06:37:13 PM PDT 24
Peak memory 218504 kb
Host smart-d960c2af-ead1-470e-b8f2-2295d0c48160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689825685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.1689825685
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.1806569369
Short name T513
Test name
Test status
Simulation time 57958531 ps
CPU time 2.42 seconds
Started Jun 28 06:37:04 PM PDT 24
Finished Jun 28 06:37:09 PM PDT 24
Peak memory 214416 kb
Host smart-42d03f60-6214-423a-bc3b-5142b2880709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806569369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1806569369
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.1170041441
Short name T344
Test name
Test status
Simulation time 941543348 ps
CPU time 23.34 seconds
Started Jun 28 06:37:02 PM PDT 24
Finished Jun 28 06:37:28 PM PDT 24
Peak memory 251136 kb
Host smart-d82e1425-4b91-4d15-b2d8-b7d9d1f13dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170041441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1170041441
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.2264820409
Short name T108
Test name
Test status
Simulation time 83419719 ps
CPU time 7.64 seconds
Started Jun 28 06:37:01 PM PDT 24
Finished Jun 28 06:37:11 PM PDT 24
Peak memory 250972 kb
Host smart-7e8da7d6-563b-48ee-91fd-1f0a81382288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264820409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2264820409
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1917884790
Short name T753
Test name
Test status
Simulation time 15324135 ps
CPU time 0.95 seconds
Started Jun 28 06:37:01 PM PDT 24
Finished Jun 28 06:37:04 PM PDT 24
Peak memory 213172 kb
Host smart-ecd43b2c-6ab1-42e6-abdb-63324cec39e5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917884790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1917884790
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.3480303071
Short name T601
Test name
Test status
Simulation time 18932613 ps
CPU time 0.98 seconds
Started Jun 28 06:39:31 PM PDT 24
Finished Jun 28 06:39:54 PM PDT 24
Peak memory 209188 kb
Host smart-964fd22f-dda9-40cb-bc1d-5421d6cd668b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480303071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3480303071
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.137718565
Short name T227
Test name
Test status
Simulation time 290739726 ps
CPU time 9.16 seconds
Started Jun 28 06:39:03 PM PDT 24
Finished Jun 28 06:39:38 PM PDT 24
Peak memory 218440 kb
Host smart-cc805a39-f230-4d7d-9858-a8d0e760fd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137718565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.137718565
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.2259797056
Short name T487
Test name
Test status
Simulation time 128690079 ps
CPU time 2.56 seconds
Started Jun 28 06:39:13 PM PDT 24
Finished Jun 28 06:39:40 PM PDT 24
Peak memory 217372 kb
Host smart-bea6b017-d5a3-49d7-9dcb-aabb2230b4e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259797056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.2259797056
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1269429089
Short name T269
Test name
Test status
Simulation time 2236504285 ps
CPU time 25.03 seconds
Started Jun 28 06:39:15 PM PDT 24
Finished Jun 28 06:40:06 PM PDT 24
Peak memory 225732 kb
Host smart-c0bfceaf-2a00-4388-8113-312360f16f2c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269429089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1269429089
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3903284941
Short name T497
Test name
Test status
Simulation time 2824898637 ps
CPU time 18.82 seconds
Started Jun 28 06:39:14 PM PDT 24
Finished Jun 28 06:39:57 PM PDT 24
Peak memory 218596 kb
Host smart-b6cc0588-7099-4169-91cc-4fe814819643
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903284941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.3903284941
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.1239382051
Short name T838
Test name
Test status
Simulation time 293193337 ps
CPU time 2.68 seconds
Started Jun 28 06:39:15 PM PDT 24
Finished Jun 28 06:39:43 PM PDT 24
Peak memory 218016 kb
Host smart-9548e846-d704-440a-beb3-c8a82f6cdd1e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239382051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.1239382051
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2613964416
Short name T562
Test name
Test status
Simulation time 2387994293 ps
CPU time 49.99 seconds
Started Jun 28 06:39:14 PM PDT 24
Finished Jun 28 06:40:28 PM PDT 24
Peak memory 268004 kb
Host smart-8e07bbfb-cd05-4494-b9ab-9edb127338b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613964416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2613964416
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.901021725
Short name T23
Test name
Test status
Simulation time 2535589709 ps
CPU time 12.34 seconds
Started Jun 28 06:39:18 PM PDT 24
Finished Jun 28 06:39:55 PM PDT 24
Peak memory 226620 kb
Host smart-838cbd50-9aa6-4b4d-867d-7ab35bebb109
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901021725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
jtag_state_post_trans.901021725
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.264354013
Short name T842
Test name
Test status
Simulation time 537189996 ps
CPU time 3.05 seconds
Started Jun 28 06:39:06 PM PDT 24
Finished Jun 28 06:39:34 PM PDT 24
Peak memory 222644 kb
Host smart-db6aaf0a-7eaa-45e1-942d-f81a00c3c789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264354013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.264354013
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3230763473
Short name T500
Test name
Test status
Simulation time 310946779 ps
CPU time 16.04 seconds
Started Jun 28 06:39:18 PM PDT 24
Finished Jun 28 06:39:59 PM PDT 24
Peak memory 226272 kb
Host smart-83ef50e2-b263-470f-925c-da95c8625422
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230763473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3230763473
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.31509870
Short name T575
Test name
Test status
Simulation time 1804001132 ps
CPU time 15 seconds
Started Jun 28 06:39:34 PM PDT 24
Finished Jun 28 06:40:09 PM PDT 24
Peak memory 218460 kb
Host smart-d67460df-4d74-4127-be97-cc803079d5bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31509870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_dig
est.31509870
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1306937374
Short name T756
Test name
Test status
Simulation time 272347936 ps
CPU time 7.52 seconds
Started Jun 28 06:39:32 PM PDT 24
Finished Jun 28 06:40:01 PM PDT 24
Peak memory 218424 kb
Host smart-8ea92256-165c-4253-8767-826e3811e0e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306937374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1306937374
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.3708940462
Short name T219
Test name
Test status
Simulation time 334717113 ps
CPU time 10.73 seconds
Started Jun 28 06:39:17 PM PDT 24
Finished Jun 28 06:39:53 PM PDT 24
Peak memory 218512 kb
Host smart-73d24c53-c6f1-4dc0-94d9-77e867510747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708940462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.3708940462
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3574681619
Short name T679
Test name
Test status
Simulation time 48684031 ps
CPU time 2.1 seconds
Started Jun 28 06:39:02 PM PDT 24
Finished Jun 28 06:39:31 PM PDT 24
Peak memory 217956 kb
Host smart-ae2f5aef-47ed-41fb-9000-736934277923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574681619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3574681619
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.2886166398
Short name T466
Test name
Test status
Simulation time 176320147 ps
CPU time 25.2 seconds
Started Jun 28 06:39:04 PM PDT 24
Finished Jun 28 06:39:57 PM PDT 24
Peak memory 251136 kb
Host smart-efc403d4-b21c-4572-8ac6-6f81d09dc7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886166398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.2886166398
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2856689570
Short name T364
Test name
Test status
Simulation time 140849201 ps
CPU time 3.3 seconds
Started Jun 28 06:39:06 PM PDT 24
Finished Jun 28 06:39:36 PM PDT 24
Peak memory 222828 kb
Host smart-02ccec8e-1f18-4c6a-9bb5-8cdeb479460c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856689570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2856689570
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.789539467
Short name T629
Test name
Test status
Simulation time 5703157270 ps
CPU time 222.98 seconds
Started Jun 28 06:39:34 PM PDT 24
Finished Jun 28 06:43:37 PM PDT 24
Peak memory 250192 kb
Host smart-70843413-2bc0-4633-bd86-809b45cebbee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789539467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.789539467
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.4204827090
Short name T368
Test name
Test status
Simulation time 14595005 ps
CPU time 0.97 seconds
Started Jun 28 06:39:05 PM PDT 24
Finished Jun 28 06:39:32 PM PDT 24
Peak memory 212072 kb
Host smart-93e3e6e0-8b49-4b0b-86c2-7ea52edb6dd3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204827090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.4204827090
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.2481600238
Short name T90
Test name
Test status
Simulation time 17480240 ps
CPU time 1.08 seconds
Started Jun 28 06:40:03 PM PDT 24
Finished Jun 28 06:40:57 PM PDT 24
Peak memory 209256 kb
Host smart-2e1701f1-db3c-478f-a966-27367a452145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481600238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2481600238
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3595738343
Short name T713
Test name
Test status
Simulation time 380826914 ps
CPU time 12.86 seconds
Started Jun 28 06:39:37 PM PDT 24
Finished Jun 28 06:40:09 PM PDT 24
Peak memory 226236 kb
Host smart-b07e50bb-189f-4b54-ac00-15e4f23c718f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595738343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3595738343
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.766116668
Short name T795
Test name
Test status
Simulation time 840193551 ps
CPU time 3.6 seconds
Started Jun 28 06:40:01 PM PDT 24
Finished Jun 28 06:40:53 PM PDT 24
Peak memory 217304 kb
Host smart-b08093f0-8160-44d1-a19e-860fd52defeb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766116668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.766116668
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.3426106417
Short name T97
Test name
Test status
Simulation time 35579208046 ps
CPU time 50.07 seconds
Started Jun 28 06:40:00 PM PDT 24
Finished Jun 28 06:41:32 PM PDT 24
Peak memory 226312 kb
Host smart-d1930348-1a64-440a-adb6-a607a587b42b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426106417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.3426106417
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1839431415
Short name T590
Test name
Test status
Simulation time 2708994098 ps
CPU time 7.53 seconds
Started Jun 28 06:39:59 PM PDT 24
Finished Jun 28 06:40:42 PM PDT 24
Peak memory 218484 kb
Host smart-7fb13f90-3ab6-4116-91b6-60b68d5830c2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839431415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.1839431415
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.1544921703
Short name T78
Test name
Test status
Simulation time 1514652142 ps
CPU time 6.34 seconds
Started Jun 28 06:39:36 PM PDT 24
Finished Jun 28 06:40:02 PM PDT 24
Peak memory 217916 kb
Host smart-18f9f637-8895-4cac-b108-950b221084d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544921703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.1544921703
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.1890790475
Short name T441
Test name
Test status
Simulation time 2849249297 ps
CPU time 61.73 seconds
Started Jun 28 06:39:39 PM PDT 24
Finished Jun 28 06:41:02 PM PDT 24
Peak memory 270856 kb
Host smart-62c7a4bc-688d-4c5f-9864-41f4e3c015a1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890790475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.1890790475
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.2012808228
Short name T113
Test name
Test status
Simulation time 2425821418 ps
CPU time 22.94 seconds
Started Jun 28 06:39:39 PM PDT 24
Finished Jun 28 06:40:23 PM PDT 24
Peak memory 251176 kb
Host smart-6a92b924-87a7-4d6c-94fc-ba6f4be98dc5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012808228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.2012808228
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.3134849364
Short name T475
Test name
Test status
Simulation time 140828604 ps
CPU time 2.33 seconds
Started Jun 28 06:39:33 PM PDT 24
Finished Jun 28 06:39:56 PM PDT 24
Peak memory 222344 kb
Host smart-f3033d0a-7591-46b1-9bdf-5e50de0f66cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134849364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3134849364
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.3596942842
Short name T734
Test name
Test status
Simulation time 998208566 ps
CPU time 11.85 seconds
Started Jun 28 06:40:02 PM PDT 24
Finished Jun 28 06:41:01 PM PDT 24
Peak memory 218440 kb
Host smart-50e29cc0-2f99-43f7-bba1-db4cc5d72f58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596942842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.3596942842
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2376960603
Short name T357
Test name
Test status
Simulation time 1534738265 ps
CPU time 15.88 seconds
Started Jun 28 06:39:59 PM PDT 24
Finished Jun 28 06:40:50 PM PDT 24
Peak memory 218540 kb
Host smart-b2abb952-7607-4a05-a9e7-4a534cb5d42f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376960603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2376960603
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3347000821
Short name T292
Test name
Test status
Simulation time 1508377449 ps
CPU time 10.12 seconds
Started Jun 28 06:40:01 PM PDT 24
Finished Jun 28 06:40:59 PM PDT 24
Peak memory 226268 kb
Host smart-1262aca0-794a-4390-b4aa-e54a404f53af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347000821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3347000821
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.1673570132
Short name T429
Test name
Test status
Simulation time 114901560 ps
CPU time 7.13 seconds
Started Jun 28 06:39:34 PM PDT 24
Finished Jun 28 06:40:02 PM PDT 24
Peak memory 217904 kb
Host smart-9b9a04db-23ef-4636-83ef-79b53c2d83ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673570132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.1673570132
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1261550710
Short name T275
Test name
Test status
Simulation time 617709532 ps
CPU time 31.18 seconds
Started Jun 28 06:39:36 PM PDT 24
Finished Jun 28 06:40:27 PM PDT 24
Peak memory 251140 kb
Host smart-21a9e46b-f9db-47dc-a01e-fc15fbdb518b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261550710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1261550710
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.1502466379
Short name T250
Test name
Test status
Simulation time 107074755 ps
CPU time 7.8 seconds
Started Jun 28 06:39:36 PM PDT 24
Finished Jun 28 06:40:04 PM PDT 24
Peak memory 250632 kb
Host smart-b358df87-df9a-4e41-8c65-5666322a91d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502466379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1502466379
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.72257252
Short name T471
Test name
Test status
Simulation time 11243718655 ps
CPU time 104.5 seconds
Started Jun 28 06:40:03 PM PDT 24
Finished Jun 28 06:42:41 PM PDT 24
Peak memory 251076 kb
Host smart-cdcec574-0d52-4a99-80b2-09f850a9d126
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72257252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.lc_ctrl_stress_all.72257252
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3154271005
Short name T628
Test name
Test status
Simulation time 32275700 ps
CPU time 0.98 seconds
Started Jun 28 06:39:34 PM PDT 24
Finished Jun 28 06:39:55 PM PDT 24
Peak memory 212144 kb
Host smart-c1b85aa4-87a5-486a-b0ad-5cc5fc5175e0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154271005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.3154271005
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.740861135
Short name T623
Test name
Test status
Simulation time 78315680 ps
CPU time 1.05 seconds
Started Jun 28 06:40:10 PM PDT 24
Finished Jun 28 06:41:29 PM PDT 24
Peak memory 209292 kb
Host smart-98540fdb-b8d5-43d1-b333-1b8d6c819312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740861135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.740861135
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1053678670
Short name T494
Test name
Test status
Simulation time 217450944 ps
CPU time 10.51 seconds
Started Jun 28 06:40:05 PM PDT 24
Finished Jun 28 06:41:15 PM PDT 24
Peak memory 218364 kb
Host smart-d390c082-b077-4db1-99a3-d5ebf0eba408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053678670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1053678670
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.1143677560
Short name T763
Test name
Test status
Simulation time 316358222 ps
CPU time 8.87 seconds
Started Jun 28 06:40:11 PM PDT 24
Finished Jun 28 06:41:38 PM PDT 24
Peak memory 217704 kb
Host smart-dbca18f8-6caf-4f93-b1a8-0c70025cf3ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143677560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.1143677560
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.553620888
Short name T39
Test name
Test status
Simulation time 2650903650 ps
CPU time 22.71 seconds
Started Jun 28 06:40:09 PM PDT 24
Finished Jun 28 06:41:50 PM PDT 24
Peak memory 219148 kb
Host smart-f955a7c6-cc6f-4bd0-95a4-68064b6e016f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553620888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_er
rors.553620888
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3572993011
Short name T637
Test name
Test status
Simulation time 1419393775 ps
CPU time 6 seconds
Started Jun 28 06:40:06 PM PDT 24
Finished Jun 28 06:41:11 PM PDT 24
Peak memory 218404 kb
Host smart-bf1e21e9-e6f9-4fe0-8ffc-3af9a4464c9f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572993011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.3572993011
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3494001037
Short name T715
Test name
Test status
Simulation time 185119011 ps
CPU time 5.99 seconds
Started Jun 28 06:40:06 PM PDT 24
Finished Jun 28 06:41:11 PM PDT 24
Peak memory 217896 kb
Host smart-e6bca0f9-7816-4bf6-982a-429d1f945684
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494001037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.3494001037
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1919193259
Short name T388
Test name
Test status
Simulation time 1831446204 ps
CPU time 44.52 seconds
Started Jun 28 06:40:01 PM PDT 24
Finished Jun 28 06:41:34 PM PDT 24
Peak memory 267528 kb
Host smart-7c556146-aa70-4903-b5c2-4872519ff5be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919193259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1919193259
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.339927862
Short name T395
Test name
Test status
Simulation time 703460340 ps
CPU time 20.63 seconds
Started Jun 28 06:40:05 PM PDT 24
Finished Jun 28 06:41:25 PM PDT 24
Peak memory 224596 kb
Host smart-d2879f22-bc78-4700-8010-cff468d71062
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339927862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_
jtag_state_post_trans.339927862
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.4045816451
Short name T280
Test name
Test status
Simulation time 163664222 ps
CPU time 2.85 seconds
Started Jun 28 06:40:02 PM PDT 24
Finished Jun 28 06:40:52 PM PDT 24
Peak memory 218452 kb
Host smart-7ac6d02e-1a49-4763-9056-282832580905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045816451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.4045816451
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.3740178498
Short name T633
Test name
Test status
Simulation time 390597239 ps
CPU time 13.42 seconds
Started Jun 28 06:40:10 PM PDT 24
Finished Jun 28 06:41:42 PM PDT 24
Peak memory 226240 kb
Host smart-f1689e46-8393-46de-a419-c48f21c80728
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740178498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.3740178498
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.4273943204
Short name T424
Test name
Test status
Simulation time 292311601 ps
CPU time 14.68 seconds
Started Jun 28 06:40:10 PM PDT 24
Finished Jun 28 06:41:43 PM PDT 24
Peak memory 218532 kb
Host smart-ad15c9af-8fb9-4193-bcd8-7ee96dc38bdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273943204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.4273943204
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1723364138
Short name T786
Test name
Test status
Simulation time 246682398 ps
CPU time 7.06 seconds
Started Jun 28 06:40:12 PM PDT 24
Finished Jun 28 06:41:44 PM PDT 24
Peak memory 226252 kb
Host smart-12cc7429-2e57-4bc8-bc0a-e84d5c6c3e40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723364138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1723364138
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.998914823
Short name T352
Test name
Test status
Simulation time 261323196 ps
CPU time 2.68 seconds
Started Jun 28 06:40:03 PM PDT 24
Finished Jun 28 06:40:59 PM PDT 24
Peak memory 217904 kb
Host smart-e349616a-5e28-4dd4-bb37-86d00b11aeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998914823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.998914823
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.3505248543
Short name T544
Test name
Test status
Simulation time 330854012 ps
CPU time 30.98 seconds
Started Jun 28 06:40:02 PM PDT 24
Finished Jun 28 06:41:27 PM PDT 24
Peak memory 251136 kb
Host smart-97b3c7a1-dbb0-405d-bcd9-8661ddc24862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505248543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.3505248543
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.1744210725
Short name T525
Test name
Test status
Simulation time 214163317 ps
CPU time 6.53 seconds
Started Jun 28 06:40:02 PM PDT 24
Finished Jun 28 06:41:02 PM PDT 24
Peak memory 242880 kb
Host smart-1164388b-71aa-47fe-8a29-e4656291e149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744210725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1744210725
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2402105489
Short name T804
Test name
Test status
Simulation time 11100568176 ps
CPU time 203.28 seconds
Started Jun 28 06:40:10 PM PDT 24
Finished Jun 28 06:44:51 PM PDT 24
Peak memory 224240 kb
Host smart-99c8934e-8e36-4622-ad8b-9e304d42ee43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402105489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2402105489
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2453477626
Short name T258
Test name
Test status
Simulation time 25151011 ps
CPU time 0.9 seconds
Started Jun 28 06:40:00 PM PDT 24
Finished Jun 28 06:40:43 PM PDT 24
Peak memory 212016 kb
Host smart-af9d0067-0877-477b-8767-8e352709380d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453477626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.2453477626
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.1463099157
Short name T377
Test name
Test status
Simulation time 50195556 ps
CPU time 0.84 seconds
Started Jun 28 06:40:13 PM PDT 24
Finished Jun 28 06:41:46 PM PDT 24
Peak memory 209064 kb
Host smart-296420d4-cb18-480f-b9fd-f1368926680d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463099157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.1463099157
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1889426267
Short name T568
Test name
Test status
Simulation time 197228135 ps
CPU time 11.1 seconds
Started Jun 28 06:40:09 PM PDT 24
Finished Jun 28 06:41:39 PM PDT 24
Peak memory 226176 kb
Host smart-d99cb702-ad06-463d-ba12-45bbaa815362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889426267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1889426267
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3786023019
Short name T409
Test name
Test status
Simulation time 1138185599 ps
CPU time 27.17 seconds
Started Jun 28 06:40:13 PM PDT 24
Finished Jun 28 06:42:05 PM PDT 24
Peak memory 217576 kb
Host smart-eebc4dbd-5940-4b17-9dde-e345aff8918d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786023019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3786023019
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.1925039958
Short name T847
Test name
Test status
Simulation time 7681324527 ps
CPU time 26.97 seconds
Started Jun 28 06:40:11 PM PDT 24
Finished Jun 28 06:41:56 PM PDT 24
Peak memory 218912 kb
Host smart-e1088f12-2321-4101-8bdd-678e1eff7c56
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925039958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.1925039958
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.294432007
Short name T309
Test name
Test status
Simulation time 202707010 ps
CPU time 4.01 seconds
Started Jun 28 06:40:12 PM PDT 24
Finished Jun 28 06:41:53 PM PDT 24
Peak memory 218324 kb
Host smart-20ed0c94-85b9-423b-b634-4d91774df0a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294432007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag
_prog_failure.294432007
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.664680769
Short name T528
Test name
Test status
Simulation time 1495683506 ps
CPU time 6.88 seconds
Started Jun 28 06:40:11 PM PDT 24
Finished Jun 28 06:41:36 PM PDT 24
Peak memory 217904 kb
Host smart-f49af46f-3f70-4e18-a5b0-e6b0eebe1442
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664680769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.
664680769
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.4040259664
Short name T849
Test name
Test status
Simulation time 1092738607 ps
CPU time 36.69 seconds
Started Jun 28 06:40:09 PM PDT 24
Finished Jun 28 06:42:04 PM PDT 24
Peak memory 251132 kb
Host smart-e192e4c1-d433-4daf-b5d8-0df5988e00f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040259664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.4040259664
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3421977718
Short name T660
Test name
Test status
Simulation time 319622416 ps
CPU time 14.47 seconds
Started Jun 28 06:40:12 PM PDT 24
Finished Jun 28 06:42:04 PM PDT 24
Peak memory 242912 kb
Host smart-95a12519-5b96-4907-979e-ec8ae23300dc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421977718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.3421977718
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.4092510081
Short name T788
Test name
Test status
Simulation time 112804619 ps
CPU time 2.99 seconds
Started Jun 28 06:40:10 PM PDT 24
Finished Jun 28 06:41:32 PM PDT 24
Peak memory 222536 kb
Host smart-839206c8-38aa-40d9-a67d-092f7f5e3744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092510081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.4092510081
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.1918099036
Short name T293
Test name
Test status
Simulation time 253476897 ps
CPU time 12.94 seconds
Started Jun 28 06:40:12 PM PDT 24
Finished Jun 28 06:42:02 PM PDT 24
Peak memory 226252 kb
Host smart-94827cb6-5a08-49d1-af17-cf8d0c7aca03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918099036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.1918099036
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.1048589120
Short name T94
Test name
Test status
Simulation time 1228794036 ps
CPU time 12.86 seconds
Started Jun 28 06:40:13 PM PDT 24
Finished Jun 28 06:41:58 PM PDT 24
Peak memory 218532 kb
Host smart-5d40735b-063f-4b93-a6f9-e9f01dddeb3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048589120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.1048589120
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.4250969583
Short name T452
Test name
Test status
Simulation time 3492391155 ps
CPU time 11.91 seconds
Started Jun 28 06:40:13 PM PDT 24
Finished Jun 28 06:41:57 PM PDT 24
Peak memory 218516 kb
Host smart-3633db08-a62f-460e-a2b5-5771671ee533
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250969583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
4250969583
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.1513014661
Short name T53
Test name
Test status
Simulation time 515684035 ps
CPU time 11.33 seconds
Started Jun 28 06:40:10 PM PDT 24
Finished Jun 28 06:41:40 PM PDT 24
Peak memory 218504 kb
Host smart-cc0d3271-ecea-40f4-a58e-58a3a5483bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513014661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.1513014661
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.3228582274
Short name T670
Test name
Test status
Simulation time 78717115 ps
CPU time 1.91 seconds
Started Jun 28 06:40:10 PM PDT 24
Finished Jun 28 06:41:30 PM PDT 24
Peak memory 223268 kb
Host smart-41ab54c5-0e7b-4dc5-a0d9-79a5705e9884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228582274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.3228582274
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.1937923949
Short name T324
Test name
Test status
Simulation time 718042536 ps
CPU time 18.99 seconds
Started Jun 28 06:40:09 PM PDT 24
Finished Jun 28 06:41:46 PM PDT 24
Peak memory 251096 kb
Host smart-5648d088-54ac-4fbb-b83e-404327614e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937923949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.1937923949
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1728053085
Short name T561
Test name
Test status
Simulation time 57919846 ps
CPU time 10.12 seconds
Started Jun 28 06:40:10 PM PDT 24
Finished Jun 28 06:41:38 PM PDT 24
Peak memory 251124 kb
Host smart-284fcd75-26aa-496c-a2be-99392dfbcefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728053085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1728053085
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3168622726
Short name T493
Test name
Test status
Simulation time 3058223133 ps
CPU time 50.01 seconds
Started Jun 28 06:40:14 PM PDT 24
Finished Jun 28 06:42:35 PM PDT 24
Peak memory 218196 kb
Host smart-cb9968e1-aacb-4703-a01f-74bc40621a35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168622726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3168622726
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1672440376
Short name T843
Test name
Test status
Simulation time 48496740 ps
CPU time 0.87 seconds
Started Jun 28 06:40:08 PM PDT 24
Finished Jun 28 06:41:18 PM PDT 24
Peak memory 212124 kb
Host smart-f2a32b2f-ed6f-4b33-b60f-bd6cd118dea4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672440376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.1672440376
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.1474306858
Short name T335
Test name
Test status
Simulation time 14379267 ps
CPU time 1.05 seconds
Started Jun 28 06:40:20 PM PDT 24
Finished Jun 28 06:41:59 PM PDT 24
Peak memory 209172 kb
Host smart-a544e3d3-c5b5-4975-935d-eceb9c1e683e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474306858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.1474306858
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2791649429
Short name T450
Test name
Test status
Simulation time 778579627 ps
CPU time 10.55 seconds
Started Jun 28 06:40:15 PM PDT 24
Finished Jun 28 06:41:59 PM PDT 24
Peak memory 226244 kb
Host smart-798f4dd2-d43f-45c8-951d-908515b27691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791649429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2791649429
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.4008069053
Short name T98
Test name
Test status
Simulation time 474124561 ps
CPU time 3.74 seconds
Started Jun 28 06:40:19 PM PDT 24
Finished Jun 28 06:42:02 PM PDT 24
Peak memory 217368 kb
Host smart-752055b7-a4c0-4126-839a-e6410372f801
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008069053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.4008069053
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.3966697402
Short name T680
Test name
Test status
Simulation time 1457250518 ps
CPU time 44.23 seconds
Started Jun 28 06:40:18 PM PDT 24
Finished Jun 28 06:42:34 PM PDT 24
Peak memory 226244 kb
Host smart-56a8ff99-bb71-4873-85c1-3d80f3357956
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966697402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.3966697402
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2475489954
Short name T549
Test name
Test status
Simulation time 494313682 ps
CPU time 3.18 seconds
Started Jun 28 06:40:19 PM PDT 24
Finished Jun 28 06:42:01 PM PDT 24
Peak memory 218424 kb
Host smart-0977ad7e-ff3c-4434-81c2-a01477a5e3c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475489954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2475489954
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1792234827
Short name T789
Test name
Test status
Simulation time 416212693 ps
CPU time 10.91 seconds
Started Jun 28 06:40:24 PM PDT 24
Finished Jun 28 06:42:13 PM PDT 24
Peak memory 217620 kb
Host smart-083886fd-00bd-448d-8d25-1e2c7853653e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792234827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1792234827
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2691582080
Short name T118
Test name
Test status
Simulation time 3953697138 ps
CPU time 31.28 seconds
Started Jun 28 06:40:23 PM PDT 24
Finished Jun 28 06:42:30 PM PDT 24
Peak memory 251308 kb
Host smart-d26f0987-a9ba-49aa-bca8-7e96fe1f3b46
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691582080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2691582080
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.4079028449
Short name T516
Test name
Test status
Simulation time 780609148 ps
CPU time 19.07 seconds
Started Jun 28 06:40:22 PM PDT 24
Finished Jun 28 06:42:18 PM PDT 24
Peak memory 251128 kb
Host smart-4e13b150-cc62-44b9-be9a-6b062cbd3697
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079028449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.4079028449
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.1889806328
Short name T381
Test name
Test status
Simulation time 45759414 ps
CPU time 1.54 seconds
Started Jun 28 06:40:15 PM PDT 24
Finished Jun 28 06:41:50 PM PDT 24
Peak memory 221996 kb
Host smart-fffa2627-5858-403d-ab41-084a25f3d326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889806328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.1889806328
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.4170742141
Short name T417
Test name
Test status
Simulation time 1595074390 ps
CPU time 11.59 seconds
Started Jun 28 06:40:21 PM PDT 24
Finished Jun 28 06:42:10 PM PDT 24
Peak memory 219148 kb
Host smart-10b69565-e82c-464c-aa29-9d80a0a15686
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170742141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.4170742141
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.4006800269
Short name T632
Test name
Test status
Simulation time 421061636 ps
CPU time 16.42 seconds
Started Jun 28 06:40:20 PM PDT 24
Finished Jun 28 06:42:15 PM PDT 24
Peak memory 218532 kb
Host smart-bc183888-90ae-4b43-b1fa-08f13b470977
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006800269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.4006800269
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.4043522708
Short name T618
Test name
Test status
Simulation time 986101775 ps
CPU time 10.4 seconds
Started Jun 28 06:40:21 PM PDT 24
Finished Jun 28 06:42:09 PM PDT 24
Peak memory 218432 kb
Host smart-dcc9ba92-8996-47a6-8dd8-829d30127433
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043522708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
4043522708
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2746274230
Short name T399
Test name
Test status
Simulation time 1209513664 ps
CPU time 11.36 seconds
Started Jun 28 06:40:15 PM PDT 24
Finished Jun 28 06:41:57 PM PDT 24
Peak memory 218508 kb
Host smart-d0a412e5-8705-4042-99bd-a0c1c00c3867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746274230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2746274230
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.2931309179
Short name T80
Test name
Test status
Simulation time 65610356 ps
CPU time 2.25 seconds
Started Jun 28 06:40:13 PM PDT 24
Finished Jun 28 06:41:47 PM PDT 24
Peak memory 217936 kb
Host smart-cc9ff381-12e6-4473-ae1d-ede632dcb4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931309179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2931309179
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.1053119633
Short name T793
Test name
Test status
Simulation time 801948157 ps
CPU time 26.26 seconds
Started Jun 28 06:40:14 PM PDT 24
Finished Jun 28 06:42:12 PM PDT 24
Peak memory 251140 kb
Host smart-e5114aa1-1567-49d4-a422-c9d50ceda368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053119633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.1053119633
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.3200804716
Short name T509
Test name
Test status
Simulation time 157345352 ps
CPU time 7.57 seconds
Started Jun 28 06:40:15 PM PDT 24
Finished Jun 28 06:41:53 PM PDT 24
Peak memory 251136 kb
Host smart-75947b7b-42a2-48ca-802f-c8af90788f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200804716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3200804716
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.3278102462
Short name T194
Test name
Test status
Simulation time 2931257305 ps
CPU time 104.12 seconds
Started Jun 28 06:40:20 PM PDT 24
Finished Jun 28 06:43:42 PM PDT 24
Peak memory 220360 kb
Host smart-342112f2-81c4-4eb6-b0d5-0bc7466db5dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278102462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.3278102462
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.1294989147
Short name T123
Test name
Test status
Simulation time 47012223822 ps
CPU time 1528.63 seconds
Started Jun 28 06:40:26 PM PDT 24
Finished Jun 28 07:07:31 PM PDT 24
Peak memory 405952 kb
Host smart-4e812806-c6f2-4e69-b8e0-af9ea361f83c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1294989147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.1294989147
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.949581586
Short name T423
Test name
Test status
Simulation time 59184643 ps
CPU time 0.88 seconds
Started Jun 28 06:40:15 PM PDT 24
Finished Jun 28 06:41:50 PM PDT 24
Peak memory 218024 kb
Host smart-34c492df-dbc3-4c54-8d50-3f9c12b0d2a0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949581586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ct
rl_volatile_unlock_smoke.949581586
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.1094367938
Short name T288
Test name
Test status
Simulation time 27003812 ps
CPU time 1.05 seconds
Started Jun 28 06:40:35 PM PDT 24
Finished Jun 28 06:42:48 PM PDT 24
Peak memory 209168 kb
Host smart-aff72cd6-31e4-416d-8004-0fed6a0edce1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094367938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.1094367938
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2110738321
Short name T760
Test name
Test status
Simulation time 3203753154 ps
CPU time 14.43 seconds
Started Jun 28 06:40:20 PM PDT 24
Finished Jun 28 06:42:13 PM PDT 24
Peak memory 226240 kb
Host smart-8f19e185-c4f8-4e33-8be1-eb71499003e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110738321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2110738321
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2476324994
Short name T814
Test name
Test status
Simulation time 404790051 ps
CPU time 11.4 seconds
Started Jun 28 06:40:33 PM PDT 24
Finished Jun 28 06:42:47 PM PDT 24
Peak memory 217684 kb
Host smart-6cfd2abf-8668-445e-8fef-9cac6d77fcde
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476324994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2476324994
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.3502023395
Short name T768
Test name
Test status
Simulation time 18051033919 ps
CPU time 85.91 seconds
Started Jun 28 06:40:27 PM PDT 24
Finished Jun 28 06:43:28 PM PDT 24
Peak memory 219164 kb
Host smart-b2c02f69-21d4-46aa-b213-24aeb0ce4ada
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502023395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.3502023395
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2000146922
Short name T830
Test name
Test status
Simulation time 204017016 ps
CPU time 6.84 seconds
Started Jun 28 06:40:23 PM PDT 24
Finished Jun 28 06:42:06 PM PDT 24
Peak memory 218424 kb
Host smart-19c327eb-b698-48d1-9dc0-3ee089004aaf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000146922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.2000146922
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3507294907
Short name T82
Test name
Test status
Simulation time 317472832 ps
CPU time 9.29 seconds
Started Jun 28 06:40:22 PM PDT 24
Finished Jun 28 06:42:08 PM PDT 24
Peak memory 217904 kb
Host smart-0b4a09e5-eefd-42c0-8e2d-64054f10df1d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507294907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.3507294907
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3884367009
Short name T538
Test name
Test status
Simulation time 23820230114 ps
CPU time 41.69 seconds
Started Jun 28 06:40:25 PM PDT 24
Finished Jun 28 06:42:44 PM PDT 24
Peak memory 267588 kb
Host smart-97ae9da0-03ab-451a-af07-ff42f28ad257
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884367009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3884367009
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.3292287434
Short name T755
Test name
Test status
Simulation time 801894286 ps
CPU time 13.79 seconds
Started Jun 28 06:40:23 PM PDT 24
Finished Jun 28 06:42:37 PM PDT 24
Peak memory 226552 kb
Host smart-f66859ed-7972-4e14-abec-abad04753746
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292287434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.3292287434
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.3709999416
Short name T474
Test name
Test status
Simulation time 159689636 ps
CPU time 3.95 seconds
Started Jun 28 06:40:28 PM PDT 24
Finished Jun 28 06:42:07 PM PDT 24
Peak memory 223024 kb
Host smart-486577d9-8972-4fae-804f-524c804d2e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709999416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.3709999416
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.423533654
Short name T757
Test name
Test status
Simulation time 1950625399 ps
CPU time 15.07 seconds
Started Jun 28 06:40:31 PM PDT 24
Finished Jun 28 06:43:07 PM PDT 24
Peak memory 219104 kb
Host smart-17040de6-0924-4fed-8866-c1a51be2a3fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423533654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.423533654
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2997230458
Short name T548
Test name
Test status
Simulation time 191683997 ps
CPU time 9.29 seconds
Started Jun 28 06:40:34 PM PDT 24
Finished Jun 28 06:42:51 PM PDT 24
Peak memory 218460 kb
Host smart-59280fc0-40c8-4e03-adf6-9e4ff7c4b94b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997230458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2997230458
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.194607327
Short name T446
Test name
Test status
Simulation time 2709159772 ps
CPU time 18.58 seconds
Started Jun 28 06:40:32 PM PDT 24
Finished Jun 28 06:43:05 PM PDT 24
Peak memory 218432 kb
Host smart-04568565-6346-4788-af4f-e949ae1f37f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194607327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.194607327
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.1065982328
Short name T422
Test name
Test status
Simulation time 307216889 ps
CPU time 11.07 seconds
Started Jun 28 06:40:22 PM PDT 24
Finished Jun 28 06:42:10 PM PDT 24
Peak memory 218436 kb
Host smart-4449c0cc-f29d-4ea5-b4ce-5b9bd1bddb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065982328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.1065982328
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.883031919
Short name T173
Test name
Test status
Simulation time 72407642 ps
CPU time 2.36 seconds
Started Jun 28 06:40:21 PM PDT 24
Finished Jun 28 06:42:01 PM PDT 24
Peak memory 214468 kb
Host smart-8d50d41d-510e-4fe5-a405-eebac8c10214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883031919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.883031919
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.4284699237
Short name T179
Test name
Test status
Simulation time 1931673569 ps
CPU time 16.94 seconds
Started Jun 28 06:40:22 PM PDT 24
Finished Jun 28 06:42:15 PM PDT 24
Peak memory 251152 kb
Host smart-ebe666a7-99b7-4e88-8838-2ca151e68eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284699237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.4284699237
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.495074908
Short name T669
Test name
Test status
Simulation time 491265824 ps
CPU time 7.62 seconds
Started Jun 28 06:40:21 PM PDT 24
Finished Jun 28 06:42:06 PM PDT 24
Peak memory 251132 kb
Host smart-fd46f608-74bf-4c70-b7f0-2117bad7169e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495074908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.495074908
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.2135316504
Short name T762
Test name
Test status
Simulation time 4490413377 ps
CPU time 92.77 seconds
Started Jun 28 06:40:31 PM PDT 24
Finished Jun 28 06:44:15 PM PDT 24
Peak memory 226268 kb
Host smart-cd0ae2f1-e12e-4c9e-b74f-4982eef5e250
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135316504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.2135316504
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2883161756
Short name T337
Test name
Test status
Simulation time 15233162 ps
CPU time 0.79 seconds
Started Jun 28 06:40:24 PM PDT 24
Finished Jun 28 06:42:02 PM PDT 24
Peak memory 208176 kb
Host smart-6d8d20ef-cd01-44d1-a1e3-469a54a6fd09
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883161756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2883161756
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.3935535479
Short name T782
Test name
Test status
Simulation time 13638467 ps
CPU time 0.86 seconds
Started Jun 28 06:41:04 PM PDT 24
Finished Jun 28 06:42:53 PM PDT 24
Peak memory 208992 kb
Host smart-4f39d008-5a80-459d-a6a1-30b4a7d8db69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935535479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.3935535479
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.950033554
Short name T469
Test name
Test status
Simulation time 7327227483 ps
CPU time 18.19 seconds
Started Jun 28 06:40:47 PM PDT 24
Finished Jun 28 06:43:01 PM PDT 24
Peak memory 218824 kb
Host smart-f40a8ec3-9ebc-4be8-a199-74199bd65215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950033554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.950033554
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.2248683736
Short name T766
Test name
Test status
Simulation time 481912484 ps
CPU time 4.04 seconds
Started Jun 28 06:41:58 PM PDT 24
Finished Jun 28 06:44:11 PM PDT 24
Peak memory 217456 kb
Host smart-6921fff1-6c3d-4225-95d8-faf66c816a97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248683736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.2248683736
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.1272588961
Short name T285
Test name
Test status
Simulation time 169494416 ps
CPU time 3.65 seconds
Started Jun 28 06:43:13 PM PDT 24
Finished Jun 28 06:45:41 PM PDT 24
Peak memory 217964 kb
Host smart-24ed6e92-0ba9-4287-ad8c-42849c429f8c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272588961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.1272588961
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1862421910
Short name T802
Test name
Test status
Simulation time 1908569455 ps
CPU time 35.77 seconds
Started Jun 28 06:42:01 PM PDT 24
Finished Jun 28 06:44:43 PM PDT 24
Peak memory 276944 kb
Host smart-bd752d40-ad36-4890-8b88-9a9e0e79a2bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862421910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.1862421910
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.1718571898
Short name T505
Test name
Test status
Simulation time 3352154813 ps
CPU time 13.16 seconds
Started Jun 28 06:41:56 PM PDT 24
Finished Jun 28 06:44:42 PM PDT 24
Peak memory 251104 kb
Host smart-bcd01f97-3721-4a74-a3fd-e71a55cbbdf4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718571898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.1718571898
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2027089580
Short name T662
Test name
Test status
Simulation time 303048198 ps
CPU time 3.53 seconds
Started Jun 28 06:40:47 PM PDT 24
Finished Jun 28 06:42:46 PM PDT 24
Peak memory 218436 kb
Host smart-1811c9e5-b6b4-41e5-b7b5-629d5bb40ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027089580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2027089580
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1223701789
Short name T658
Test name
Test status
Simulation time 1263987215 ps
CPU time 16.77 seconds
Started Jun 28 06:40:50 PM PDT 24
Finished Jun 28 06:42:59 PM PDT 24
Peak memory 226268 kb
Host smart-167b7029-d4a2-4812-9aab-d8c5074d37dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223701789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1223701789
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.406209138
Short name T526
Test name
Test status
Simulation time 6783785299 ps
CPU time 12.01 seconds
Started Jun 28 06:42:14 PM PDT 24
Finished Jun 28 06:45:03 PM PDT 24
Peak memory 218540 kb
Host smart-9b8f88ac-3f64-46ba-89ea-df4831af0dc6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406209138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_di
gest.406209138
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.2767548292
Short name T604
Test name
Test status
Simulation time 1943203579 ps
CPU time 8.88 seconds
Started Jun 28 06:41:59 PM PDT 24
Finished Jun 28 06:44:31 PM PDT 24
Peak memory 218496 kb
Host smart-601cb79e-197f-41ba-8480-7392cd0d6bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767548292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2767548292
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2502776977
Short name T746
Test name
Test status
Simulation time 168868503 ps
CPU time 16.54 seconds
Started Jun 28 06:40:38 PM PDT 24
Finished Jun 28 06:43:04 PM PDT 24
Peak memory 251156 kb
Host smart-546ea58a-93d5-4077-9907-537b00aa54bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502776977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2502776977
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2724247280
Short name T796
Test name
Test status
Simulation time 21131022390 ps
CPU time 306.2 seconds
Started Jun 28 06:41:01 PM PDT 24
Finished Jun 28 06:47:57 PM PDT 24
Peak memory 283244 kb
Host smart-3d9b07ab-e615-4654-8707-44292bbcb80e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724247280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2724247280
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2350635657
Short name T400
Test name
Test status
Simulation time 42061000 ps
CPU time 1.2 seconds
Started Jun 28 06:40:32 PM PDT 24
Finished Jun 28 06:42:43 PM PDT 24
Peak memory 218100 kb
Host smart-b5774d6b-8f55-47ba-bb15-0c76552cab24
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350635657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.2350635657
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1830508704
Short name T308
Test name
Test status
Simulation time 65945966 ps
CPU time 1.02 seconds
Started Jun 28 06:41:40 PM PDT 24
Finished Jun 28 06:43:36 PM PDT 24
Peak memory 209192 kb
Host smart-52a4fee0-95c4-4fc8-9f50-974c9d5a3de9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830508704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1830508704
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.2144707585
Short name T254
Test name
Test status
Simulation time 489716810 ps
CPU time 14.27 seconds
Started Jun 28 06:41:15 PM PDT 24
Finished Jun 28 06:44:17 PM PDT 24
Peak memory 218432 kb
Host smart-e45571c2-ab1f-4e3e-9650-893a6ecc46c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144707585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.2144707585
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.3835306082
Short name T709
Test name
Test status
Simulation time 587558786 ps
CPU time 4.01 seconds
Started Jun 28 06:41:16 PM PDT 24
Finished Jun 28 06:43:39 PM PDT 24
Peak memory 217456 kb
Host smart-28cdb0b7-eebc-4644-8140-431c8265d69a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835306082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.3835306082
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3860699795
Short name T829
Test name
Test status
Simulation time 14943888331 ps
CPU time 50.74 seconds
Started Jun 28 06:41:10 PM PDT 24
Finished Jun 28 06:44:43 PM PDT 24
Peak memory 226288 kb
Host smart-017e02a4-b5e1-420e-a13f-f2806bddd35a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860699795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3860699795
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.412862383
Short name T412
Test name
Test status
Simulation time 281261125 ps
CPU time 9.15 seconds
Started Jun 28 06:41:15 PM PDT 24
Finished Jun 28 06:45:00 PM PDT 24
Peak memory 218336 kb
Host smart-6615923b-7d49-4737-a260-7423b1b70814
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412862383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.412862383
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.3480259967
Short name T66
Test name
Test status
Simulation time 3217471076 ps
CPU time 2.39 seconds
Started Jun 28 06:41:02 PM PDT 24
Finished Jun 28 06:43:42 PM PDT 24
Peak memory 217952 kb
Host smart-cf7a262b-3d21-415a-b9bb-df453e95f2b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480259967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.3480259967
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1560518466
Short name T244
Test name
Test status
Simulation time 3123083293 ps
CPU time 51.27 seconds
Started Jun 28 06:41:01 PM PDT 24
Finished Jun 28 06:43:43 PM PDT 24
Peak memory 267704 kb
Host smart-adf5cd93-e14d-4e02-b117-0981fc52671d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560518466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.1560518466
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3263606413
Short name T656
Test name
Test status
Simulation time 17214075847 ps
CPU time 34.26 seconds
Started Jun 28 06:41:10 PM PDT 24
Finished Jun 28 06:44:13 PM PDT 24
Peak memory 251008 kb
Host smart-bb905a73-14b8-4a68-857b-a11b28ed3192
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263606413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.3263606413
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2718883731
Short name T769
Test name
Test status
Simulation time 21279056 ps
CPU time 1.92 seconds
Started Jun 28 06:41:02 PM PDT 24
Finished Jun 28 06:43:27 PM PDT 24
Peak memory 222232 kb
Host smart-5a65ce5f-5939-4478-9bf3-6b170e100b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718883731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2718883731
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3307980650
Short name T737
Test name
Test status
Simulation time 1213047288 ps
CPU time 25.47 seconds
Started Jun 28 06:41:27 PM PDT 24
Finished Jun 28 06:44:05 PM PDT 24
Peak memory 218440 kb
Host smart-2320ae35-df73-47e1-9bb6-fe6497b4adaf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307980650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.3307980650
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2740703978
Short name T383
Test name
Test status
Simulation time 215644245 ps
CPU time 7.99 seconds
Started Jun 28 06:41:29 PM PDT 24
Finished Jun 28 06:44:25 PM PDT 24
Peak memory 226240 kb
Host smart-8474fada-c3e0-4602-a6aa-34aabe1112bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740703978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2740703978
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3041376349
Short name T641
Test name
Test status
Simulation time 7891009673 ps
CPU time 9.47 seconds
Started Jun 28 06:41:16 PM PDT 24
Finished Jun 28 06:43:49 PM PDT 24
Peak memory 218556 kb
Host smart-8f5788a6-b202-40f3-b8d4-4dcce127d401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041376349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3041376349
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.1872585257
Short name T251
Test name
Test status
Simulation time 181299757 ps
CPU time 6.55 seconds
Started Jun 28 06:41:03 PM PDT 24
Finished Jun 28 06:42:58 PM PDT 24
Peak memory 217956 kb
Host smart-3ccec025-9668-4718-a4cd-55a62d1520fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872585257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1872585257
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2866631090
Short name T367
Test name
Test status
Simulation time 138378364 ps
CPU time 15.56 seconds
Started Jun 28 06:41:02 PM PDT 24
Finished Jun 28 06:43:55 PM PDT 24
Peak memory 251052 kb
Host smart-ae1d98b1-dc79-4bdf-a268-d5af19007adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866631090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2866631090
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3425091691
Short name T621
Test name
Test status
Simulation time 224680131 ps
CPU time 7.87 seconds
Started Jun 28 06:41:02 PM PDT 24
Finished Jun 28 06:43:47 PM PDT 24
Peak memory 251132 kb
Host smart-04a8f496-3b71-43db-bd7e-09ab5b3df160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425091691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3425091691
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.393669255
Short name T550
Test name
Test status
Simulation time 35841006860 ps
CPU time 142.02 seconds
Started Jun 28 06:41:40 PM PDT 24
Finished Jun 28 06:45:58 PM PDT 24
Peak memory 283912 kb
Host smart-8be0f787-c59d-4c54-a4a6-914667eb5a92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393669255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.393669255
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2755777973
Short name T712
Test name
Test status
Simulation time 122960004 ps
CPU time 0.86 seconds
Started Jun 28 06:41:02 PM PDT 24
Finished Jun 28 06:42:53 PM PDT 24
Peak memory 212040 kb
Host smart-3fc79373-9e3c-4a79-9bed-0c3c9c34a719
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755777973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.2755777973
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3169477733
Short name T725
Test name
Test status
Simulation time 17766838 ps
CPU time 0.9 seconds
Started Jun 28 06:43:14 PM PDT 24
Finished Jun 28 06:45:38 PM PDT 24
Peak memory 209164 kb
Host smart-02e06d07-a603-4b30-94f8-e8e4ff873558
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169477733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3169477733
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.1082579096
Short name T271
Test name
Test status
Simulation time 476344402 ps
CPU time 11.38 seconds
Started Jun 28 06:41:44 PM PDT 24
Finished Jun 28 06:43:48 PM PDT 24
Peak memory 218372 kb
Host smart-f6589f48-0f5e-4169-a381-00b765edce2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082579096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.1082579096
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.1843047420
Short name T9
Test name
Test status
Simulation time 607234445 ps
CPU time 3.52 seconds
Started Jun 28 06:42:00 PM PDT 24
Finished Jun 28 06:44:32 PM PDT 24
Peak memory 217420 kb
Host smart-54266f30-03ee-4904-9436-9f34e1f139a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843047420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.1843047420
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1797805940
Short name T533
Test name
Test status
Simulation time 16411151858 ps
CPU time 50.97 seconds
Started Jun 28 06:41:53 PM PDT 24
Finished Jun 28 06:44:58 PM PDT 24
Peak memory 226336 kb
Host smart-ce13afe4-7f79-448d-98fd-49793b488dfa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797805940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1797805940
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.1322516073
Short name T776
Test name
Test status
Simulation time 917842604 ps
CPU time 23.52 seconds
Started Jun 28 06:41:59 PM PDT 24
Finished Jun 28 06:44:30 PM PDT 24
Peak memory 218332 kb
Host smart-5a36ecbe-84ff-46c9-9c17-e7ada24eb87d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322516073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.1322516073
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2463361140
Short name T813
Test name
Test status
Simulation time 975210152 ps
CPU time 13.21 seconds
Started Jun 28 06:41:52 PM PDT 24
Finished Jun 28 06:44:02 PM PDT 24
Peak memory 217920 kb
Host smart-4949ccaa-b451-4ba2-ab01-713ea22abfc6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463361140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2463361140
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1602876900
Short name T797
Test name
Test status
Simulation time 9748935970 ps
CPU time 62.13 seconds
Started Jun 28 06:41:51 PM PDT 24
Finished Jun 28 06:45:09 PM PDT 24
Peak memory 277248 kb
Host smart-253547f1-cdc8-4a3c-840d-8e2d2f5d3750
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602876900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1602876900
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1969502607
Short name T315
Test name
Test status
Simulation time 1503464159 ps
CPU time 21.17 seconds
Started Jun 28 06:41:53 PM PDT 24
Finished Jun 28 06:44:50 PM PDT 24
Peak memory 223332 kb
Host smart-d6bcdbc2-5933-4a0c-b784-612c0e969813
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969502607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.1969502607
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.1976374591
Short name T532
Test name
Test status
Simulation time 68134749 ps
CPU time 2.84 seconds
Started Jun 28 06:41:40 PM PDT 24
Finished Jun 28 06:43:27 PM PDT 24
Peak memory 218436 kb
Host smart-41ea51a6-12d0-4066-bd1e-b31dc7b35f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976374591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.1976374591
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.2241543987
Short name T465
Test name
Test status
Simulation time 1207126659 ps
CPU time 9.59 seconds
Started Jun 28 06:41:54 PM PDT 24
Finished Jun 28 06:43:59 PM PDT 24
Peak memory 226196 kb
Host smart-c78b55a9-de93-4acc-b861-b1998c1ecfd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241543987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2241543987
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.2149297333
Short name T289
Test name
Test status
Simulation time 1974431786 ps
CPU time 20.48 seconds
Started Jun 28 06:42:07 PM PDT 24
Finished Jun 28 06:44:38 PM PDT 24
Peak memory 218532 kb
Host smart-1753a65c-47ce-45e8-84ab-38e497d6fd24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149297333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.2149297333
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1594450141
Short name T300
Test name
Test status
Simulation time 531402323 ps
CPU time 7.72 seconds
Started Jun 28 06:43:18 PM PDT 24
Finished Jun 28 06:45:43 PM PDT 24
Peak memory 218440 kb
Host smart-abce0398-4f38-410b-aa76-036befe18b21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594450141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1594450141
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.3727937516
Short name T361
Test name
Test status
Simulation time 242502701 ps
CPU time 9.04 seconds
Started Jun 28 06:41:54 PM PDT 24
Finished Jun 28 06:44:01 PM PDT 24
Peak memory 218636 kb
Host smart-16075ea1-5f8e-417e-a930-169d00e2e6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727937516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3727937516
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.3636519483
Short name T699
Test name
Test status
Simulation time 35435671 ps
CPU time 2.55 seconds
Started Jun 28 06:41:40 PM PDT 24
Finished Jun 28 06:43:26 PM PDT 24
Peak memory 214844 kb
Host smart-7fdbc0d3-e666-44de-9d3f-8a7c754714d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636519483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.3636519483
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.1372612291
Short name T735
Test name
Test status
Simulation time 989230315 ps
CPU time 29.06 seconds
Started Jun 28 06:41:39 PM PDT 24
Finished Jun 28 06:44:57 PM PDT 24
Peak memory 251144 kb
Host smart-7cff2458-3c84-4062-9f32-1533ebf66bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372612291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.1372612291
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.1712956760
Short name T837
Test name
Test status
Simulation time 49220942 ps
CPU time 5.86 seconds
Started Jun 28 06:41:40 PM PDT 24
Finished Jun 28 06:43:29 PM PDT 24
Peak memory 246516 kb
Host smart-24e933c2-03c4-4ea0-bb26-be53dd0fa637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712956760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1712956760
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2803614500
Short name T387
Test name
Test status
Simulation time 12254230347 ps
CPU time 167.13 seconds
Started Jun 28 06:42:07 PM PDT 24
Finished Jun 28 06:47:16 PM PDT 24
Peak memory 283948 kb
Host smart-6f45d01c-fb5d-4adc-a341-e790f60a1af0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803614500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2803614500
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.1863460849
Short name T214
Test name
Test status
Simulation time 65757112637 ps
CPU time 5047.45 seconds
Started Jun 28 06:42:06 PM PDT 24
Finished Jun 28 08:08:36 PM PDT 24
Peak memory 1652404 kb
Host smart-c03cfa53-693f-48b1-9f19-ae5277fbc93d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1863460849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.1863460849
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.785364941
Short name T490
Test name
Test status
Simulation time 13322744 ps
CPU time 0.87 seconds
Started Jun 28 06:41:40 PM PDT 24
Finished Jun 28 06:43:24 PM PDT 24
Peak memory 213124 kb
Host smart-c86fdb1f-abe8-4010-a6cf-7624dc9602c0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785364941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.785364941
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.3566456042
Short name T12
Test name
Test status
Simulation time 35857933 ps
CPU time 0.83 seconds
Started Jun 28 06:42:39 PM PDT 24
Finished Jun 28 06:44:30 PM PDT 24
Peak memory 209212 kb
Host smart-4a57badf-01ec-42e1-9dac-4bd063ea3fe8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566456042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.3566456042
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1295496513
Short name T510
Test name
Test status
Simulation time 2669590017 ps
CPU time 13.82 seconds
Started Jun 28 06:42:25 PM PDT 24
Finished Jun 28 06:45:48 PM PDT 24
Peak memory 218500 kb
Host smart-d9f0163c-865b-4dd0-b473-c5ab6133684f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295496513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1295496513
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.699368820
Short name T26
Test name
Test status
Simulation time 119805639 ps
CPU time 1.98 seconds
Started Jun 28 06:42:37 PM PDT 24
Finished Jun 28 06:44:31 PM PDT 24
Peak memory 217400 kb
Host smart-2275c1d6-cb53-49b0-b3c7-ace61ae64653
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699368820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.699368820
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.1570800438
Short name T262
Test name
Test status
Simulation time 18744743693 ps
CPU time 69.2 seconds
Started Jun 28 06:42:39 PM PDT 24
Finished Jun 28 06:46:00 PM PDT 24
Peak memory 219976 kb
Host smart-e3d65eea-fa81-47fa-b3d9-2eb815ca4b90
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570800438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.1570800438
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1351137754
Short name T783
Test name
Test status
Simulation time 200798304 ps
CPU time 7.06 seconds
Started Jun 28 06:45:18 PM PDT 24
Finished Jun 28 06:47:59 PM PDT 24
Peak memory 223532 kb
Host smart-8e942ac8-250d-41a3-bdbd-9f64b09f4ca7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351137754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.1351137754
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.583776095
Short name T551
Test name
Test status
Simulation time 2024674845 ps
CPU time 6.06 seconds
Started Jun 28 06:42:24 PM PDT 24
Finished Jun 28 06:44:43 PM PDT 24
Peak memory 217912 kb
Host smart-3da0819f-933e-4a2c-aa74-a567ba74ede6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583776095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke.
583776095
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.820037586
Short name T758
Test name
Test status
Simulation time 2344755153 ps
CPU time 54.16 seconds
Started Jun 28 06:42:24 PM PDT 24
Finished Jun 28 06:45:23 PM PDT 24
Peak memory 283940 kb
Host smart-4ca645b7-b594-4f1c-9340-f93e4cca3eab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820037586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_state_failure.820037586
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1408948957
Short name T404
Test name
Test status
Simulation time 1095967664 ps
CPU time 9.21 seconds
Started Jun 28 06:42:23 PM PDT 24
Finished Jun 28 06:44:37 PM PDT 24
Peak memory 218360 kb
Host smart-d0249c80-c56c-49d6-a480-046c9919a0a8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408948957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1408948957
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3167966881
Short name T468
Test name
Test status
Simulation time 281931803 ps
CPU time 3.4 seconds
Started Jun 28 06:42:07 PM PDT 24
Finished Jun 28 06:44:11 PM PDT 24
Peak memory 222672 kb
Host smart-93a38305-f453-4808-8905-34080f769ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167966881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3167966881
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3497631696
Short name T578
Test name
Test status
Simulation time 984481085 ps
CPU time 10.36 seconds
Started Jun 28 06:42:46 PM PDT 24
Finished Jun 28 06:44:59 PM PDT 24
Peak memory 226168 kb
Host smart-27c840dd-a89e-49e2-bccc-cab52adca203
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497631696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3497631696
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3534620670
Short name T57
Test name
Test status
Simulation time 1408208485 ps
CPU time 19.34 seconds
Started Jun 28 06:42:39 PM PDT 24
Finished Jun 28 06:45:08 PM PDT 24
Peak memory 218464 kb
Host smart-09909a00-b58d-4214-b277-fa15a0e09892
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534620670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.3534620670
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.638320280
Short name T724
Test name
Test status
Simulation time 659007575 ps
CPU time 9.73 seconds
Started Jun 28 06:42:40 PM PDT 24
Finished Jun 28 06:45:27 PM PDT 24
Peak memory 218364 kb
Host smart-ebeefe00-4786-4ff9-9818-e7728172ff3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638320280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.638320280
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.2273109169
Short name T486
Test name
Test status
Simulation time 1003186958 ps
CPU time 10.01 seconds
Started Jun 28 06:42:23 PM PDT 24
Finished Jun 28 06:44:39 PM PDT 24
Peak memory 218492 kb
Host smart-4068c103-3307-4b32-b7b6-e1bd4e3c1e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273109169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2273109169
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.2577493427
Short name T362
Test name
Test status
Simulation time 144549783 ps
CPU time 2.4 seconds
Started Jun 28 06:42:08 PM PDT 24
Finished Jun 28 06:44:26 PM PDT 24
Peak memory 214272 kb
Host smart-64aff7ef-4c5b-48b7-af2c-85e12c035fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577493427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2577493427
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.327994376
Short name T453
Test name
Test status
Simulation time 294164132 ps
CPU time 30.19 seconds
Started Jun 28 06:43:11 PM PDT 24
Finished Jun 28 06:45:58 PM PDT 24
Peak memory 245052 kb
Host smart-6068d7fc-fa8b-4719-b0d9-81303b9b84c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327994376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.327994376
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.1799760246
Short name T759
Test name
Test status
Simulation time 285440296 ps
CPU time 7.92 seconds
Started Jun 28 06:42:07 PM PDT 24
Finished Jun 28 06:44:45 PM PDT 24
Peak memory 251060 kb
Host smart-d35f8a63-80e9-4f2c-98a5-e70cb3a6d92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799760246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1799760246
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.3145612615
Short name T380
Test name
Test status
Simulation time 23540448093 ps
CPU time 127.41 seconds
Started Jun 28 06:42:36 PM PDT 24
Finished Jun 28 06:46:36 PM PDT 24
Peak memory 283956 kb
Host smart-4e8faeaa-f09b-4c03-b245-c5f06bf94ffb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145612615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.3145612615
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.514323571
Short name T239
Test name
Test status
Simulation time 78197063 ps
CPU time 0.88 seconds
Started Jun 28 06:42:08 PM PDT 24
Finished Jun 28 06:44:20 PM PDT 24
Peak memory 212136 kb
Host smart-ff2646fa-3f9a-40a3-8d6a-cc5baa9a7934
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514323571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct
rl_volatile_unlock_smoke.514323571
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.43656023
Short name T832
Test name
Test status
Simulation time 17506950 ps
CPU time 1.18 seconds
Started Jun 28 06:37:12 PM PDT 24
Finished Jun 28 06:37:14 PM PDT 24
Peak memory 209160 kb
Host smart-0b2fc967-8133-4da3-aa9d-0cf274b06319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43656023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.43656023
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.693952201
Short name T299
Test name
Test status
Simulation time 11141425 ps
CPU time 0.96 seconds
Started Jun 28 06:37:16 PM PDT 24
Finished Jun 28 06:37:20 PM PDT 24
Peak memory 209156 kb
Host smart-37ccaee0-0ff8-44da-b70e-99111b1884d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693952201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.693952201
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.3464954157
Short name T801
Test name
Test status
Simulation time 201100249 ps
CPU time 1.91 seconds
Started Jun 28 06:37:15 PM PDT 24
Finished Jun 28 06:37:20 PM PDT 24
Peak memory 217264 kb
Host smart-23c2a6f5-206b-49a6-853d-0dbf1d50d989
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464954157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.3464954157
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1387759932
Short name T812
Test name
Test status
Simulation time 1621606422 ps
CPU time 44.31 seconds
Started Jun 28 06:37:13 PM PDT 24
Finished Jun 28 06:38:00 PM PDT 24
Peak memory 218548 kb
Host smart-6acc55d6-07d0-4f84-87fc-fdb98c9a0b1b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387759932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1387759932
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.3800502716
Short name T195
Test name
Test status
Simulation time 2249975298 ps
CPU time 3.37 seconds
Started Jun 28 06:37:13 PM PDT 24
Finished Jun 28 06:37:18 PM PDT 24
Peak memory 217744 kb
Host smart-9ebf60ac-ca98-495c-a56b-d4408a5565d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800502716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.3
800502716
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2896090028
Short name T407
Test name
Test status
Simulation time 279857867 ps
CPU time 8.8 seconds
Started Jun 28 06:37:13 PM PDT 24
Finished Jun 28 06:37:24 PM PDT 24
Peak memory 218432 kb
Host smart-570babfd-a296-49ec-8ed1-2b63302c6661
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896090028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2896090028
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.128364213
Short name T267
Test name
Test status
Simulation time 4712464078 ps
CPU time 15.17 seconds
Started Jun 28 06:37:13 PM PDT 24
Finished Jun 28 06:37:30 PM PDT 24
Peak memory 217976 kb
Host smart-d75a12b7-a34c-4bfd-8cfd-cbebcaff8f36
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128364213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_regwen_during_op.128364213
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.3698334309
Short name T69
Test name
Test status
Simulation time 196059144 ps
CPU time 2.98 seconds
Started Jun 28 06:37:12 PM PDT 24
Finished Jun 28 06:37:16 PM PDT 24
Peak memory 217944 kb
Host smart-63282140-c605-44e5-92d1-1ee10b6f497b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698334309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
3698334309
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.4062119126
Short name T822
Test name
Test status
Simulation time 8545440942 ps
CPU time 86.25 seconds
Started Jun 28 06:37:16 PM PDT 24
Finished Jun 28 06:38:45 PM PDT 24
Peak memory 279072 kb
Host smart-e2e74156-c967-4d74-9820-519de0e9b234
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062119126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.4062119126
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.746137216
Short name T259
Test name
Test status
Simulation time 416951732 ps
CPU time 11.7 seconds
Started Jun 28 06:37:13 PM PDT 24
Finished Jun 28 06:37:26 PM PDT 24
Peak memory 250768 kb
Host smart-2db38ac7-1f59-44ca-b759-8d9c1b24f751
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746137216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.746137216
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.93704662
Short name T472
Test name
Test status
Simulation time 76249634 ps
CPU time 2.35 seconds
Started Jun 28 06:37:13 PM PDT 24
Finished Jun 28 06:37:17 PM PDT 24
Peak memory 222352 kb
Host smart-2b83e1a7-bca5-41df-a6d9-63c20f9a038e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93704662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.93704662
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1944401902
Short name T320
Test name
Test status
Simulation time 239961350 ps
CPU time 8.65 seconds
Started Jun 28 06:37:14 PM PDT 24
Finished Jun 28 06:37:24 PM PDT 24
Peak memory 217908 kb
Host smart-83e2742d-e443-4142-8ac8-5f5242aa1015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944401902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1944401902
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1616428085
Short name T51
Test name
Test status
Simulation time 200660613 ps
CPU time 37.78 seconds
Started Jun 28 06:37:12 PM PDT 24
Finished Jun 28 06:37:51 PM PDT 24
Peak memory 282272 kb
Host smart-8e09b20d-8659-4768-8d9d-db5cbf2944ab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616428085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1616428085
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.3060558670
Short name T107
Test name
Test status
Simulation time 906113288 ps
CPU time 9.63 seconds
Started Jun 28 06:37:14 PM PDT 24
Finished Jun 28 06:37:26 PM PDT 24
Peak memory 226244 kb
Host smart-07725a61-55b1-45de-a362-6c38992721cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060558670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.3060558670
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.1254086011
Short name T379
Test name
Test status
Simulation time 628543616 ps
CPU time 11.33 seconds
Started Jun 28 06:37:16 PM PDT 24
Finished Jun 28 06:37:30 PM PDT 24
Peak memory 218500 kb
Host smart-34820bfe-a419-4824-90dd-0aeaf0b766d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254086011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.1254086011
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.867422252
Short name T321
Test name
Test status
Simulation time 248229323 ps
CPU time 8.64 seconds
Started Jun 28 06:37:12 PM PDT 24
Finished Jun 28 06:37:22 PM PDT 24
Peak memory 218432 kb
Host smart-c3ad87e2-3365-402f-b7bf-67ef9de61710
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867422252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.867422252
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.1978416321
Short name T406
Test name
Test status
Simulation time 1874897334 ps
CPU time 11.96 seconds
Started Jun 28 06:37:19 PM PDT 24
Finished Jun 28 06:37:32 PM PDT 24
Peak memory 218508 kb
Host smart-934a29ee-be22-4418-9656-d0a52737a061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978416321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1978416321
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.4001281370
Short name T266
Test name
Test status
Simulation time 90427190 ps
CPU time 2.68 seconds
Started Jun 28 06:37:15 PM PDT 24
Finished Jun 28 06:37:20 PM PDT 24
Peak memory 217920 kb
Host smart-dae2ef68-ce0d-40e3-860f-a1caaa4c27e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001281370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.4001281370
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.3080106069
Short name T507
Test name
Test status
Simulation time 1940766239 ps
CPU time 24.65 seconds
Started Jun 28 06:37:13 PM PDT 24
Finished Jun 28 06:37:40 PM PDT 24
Peak memory 251140 kb
Host smart-1ba7f091-0adb-4514-93b8-de98942c8f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080106069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3080106069
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.3164042426
Short name T771
Test name
Test status
Simulation time 53309096 ps
CPU time 8.35 seconds
Started Jun 28 06:37:15 PM PDT 24
Finished Jun 28 06:37:27 PM PDT 24
Peak memory 251080 kb
Host smart-ea68c077-0505-4d34-a314-2fec91e1d4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164042426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3164042426
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.3483938909
Short name T325
Test name
Test status
Simulation time 6720076627 ps
CPU time 220.52 seconds
Started Jun 28 06:37:16 PM PDT 24
Finished Jun 28 06:40:59 PM PDT 24
Peak memory 282676 kb
Host smart-d9992beb-cbf1-4a90-a585-3e9465a88da4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483938909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.3483938909
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.484549813
Short name T261
Test name
Test status
Simulation time 24832465 ps
CPU time 0.93 seconds
Started Jun 28 06:37:11 PM PDT 24
Finished Jun 28 06:37:13 PM PDT 24
Peak memory 212168 kb
Host smart-02a288d0-e40c-4eac-8359-9d5d00e20c63
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484549813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr
l_volatile_unlock_smoke.484549813
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1996198175
Short name T184
Test name
Test status
Simulation time 16257161 ps
CPU time 0.9 seconds
Started Jun 28 06:42:58 PM PDT 24
Finished Jun 28 06:45:38 PM PDT 24
Peak memory 209188 kb
Host smart-8fc2d8c0-966c-4ea1-8413-4e432cb55622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996198175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1996198175
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3430379306
Short name T598
Test name
Test status
Simulation time 714953992 ps
CPU time 11.4 seconds
Started Jun 28 06:42:36 PM PDT 24
Finished Jun 28 06:45:29 PM PDT 24
Peak memory 218388 kb
Host smart-20a769a5-641b-4030-b7f6-5d2a3ea80380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430379306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3430379306
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.3779008746
Short name T457
Test name
Test status
Simulation time 331466605 ps
CPU time 9.32 seconds
Started Jun 28 06:42:40 PM PDT 24
Finished Jun 28 06:45:01 PM PDT 24
Peak memory 217668 kb
Host smart-733f4a9c-5630-4a06-acf3-4b61dd670561
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779008746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.3779008746
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2650432330
Short name T416
Test name
Test status
Simulation time 289098188 ps
CPU time 3.28 seconds
Started Jun 28 06:42:36 PM PDT 24
Finished Jun 28 06:44:53 PM PDT 24
Peak memory 218352 kb
Host smart-2acfc880-3f49-4461-863f-b09e08b3d360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650432330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2650432330
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.953757127
Short name T515
Test name
Test status
Simulation time 491522859 ps
CPU time 18.78 seconds
Started Jun 28 06:42:40 PM PDT 24
Finished Jun 28 06:44:57 PM PDT 24
Peak memory 218536 kb
Host smart-1f91feaf-4e1d-4b5c-a2bb-88aa15260ebf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953757127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.953757127
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.1668253683
Short name T328
Test name
Test status
Simulation time 2130567078 ps
CPU time 13.3 seconds
Started Jun 28 06:42:53 PM PDT 24
Finished Jun 28 06:45:31 PM PDT 24
Peak memory 218516 kb
Host smart-72fbde59-40fd-4be0-a889-f221bf86f1cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668253683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.1668253683
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.237150171
Short name T257
Test name
Test status
Simulation time 501011129 ps
CPU time 9.28 seconds
Started Jun 28 06:42:54 PM PDT 24
Finished Jun 28 06:45:56 PM PDT 24
Peak memory 218440 kb
Host smart-ce177bc2-411a-4280-8505-c225daf9219e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237150171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.237150171
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.988947181
Short name T54
Test name
Test status
Simulation time 876747916 ps
CPU time 14.33 seconds
Started Jun 28 06:43:49 PM PDT 24
Finished Jun 28 06:46:50 PM PDT 24
Peak memory 218512 kb
Host smart-8c433579-f913-45fb-acce-1eb3fe921785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988947181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.988947181
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1065208990
Short name T376
Test name
Test status
Simulation time 39305521 ps
CPU time 1.1 seconds
Started Jun 28 06:42:36 PM PDT 24
Finished Jun 28 06:44:30 PM PDT 24
Peak memory 217936 kb
Host smart-a8a97345-194d-4181-9508-a5109ff627d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065208990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1065208990
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.2704785903
Short name T234
Test name
Test status
Simulation time 2072775434 ps
CPU time 21.88 seconds
Started Jun 28 06:42:37 PM PDT 24
Finished Jun 28 06:45:40 PM PDT 24
Peak memory 251120 kb
Host smart-ba1b0786-d1be-41ec-a88c-ca19c009b599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704785903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2704785903
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1790172857
Short name T675
Test name
Test status
Simulation time 1104835153 ps
CPU time 22.05 seconds
Started Jun 28 06:42:54 PM PDT 24
Finished Jun 28 06:45:59 PM PDT 24
Peak memory 242940 kb
Host smart-469e08b7-12b6-4afb-ad63-55d41c639754
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790172857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.1790172857
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.3679697887
Short name T840
Test name
Test status
Simulation time 15035317016 ps
CPU time 429.49 seconds
Started Jun 28 06:42:59 PM PDT 24
Finished Jun 28 06:52:27 PM PDT 24
Peak memory 282936 kb
Host smart-baac50d5-400a-42e7-a7ae-39c508a97e1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3679697887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.3679697887
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.258246210
Short name T1
Test name
Test status
Simulation time 23293113 ps
CPU time 1.03 seconds
Started Jun 28 06:42:37 PM PDT 24
Finished Jun 28 06:45:38 PM PDT 24
Peak memory 212084 kb
Host smart-70519f71-7272-4683-bd52-b04f391cabca
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258246210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ct
rl_volatile_unlock_smoke.258246210
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.4153517234
Short name T249
Test name
Test status
Simulation time 16072200 ps
CPU time 1.06 seconds
Started Jun 28 06:43:01 PM PDT 24
Finished Jun 28 06:45:19 PM PDT 24
Peak memory 209116 kb
Host smart-cb26fc48-8e0c-4407-909b-49b8d36da4d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153517234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.4153517234
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.3469743376
Short name T433
Test name
Test status
Simulation time 618147254 ps
CPU time 15.68 seconds
Started Jun 28 06:43:18 PM PDT 24
Finished Jun 28 06:46:26 PM PDT 24
Peak memory 217468 kb
Host smart-fe52deca-6a41-445c-a287-92d430bb75b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469743376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.3469743376
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.2530437959
Short name T596
Test name
Test status
Simulation time 274034251 ps
CPU time 2.82 seconds
Started Jun 28 06:42:53 PM PDT 24
Finished Jun 28 06:45:21 PM PDT 24
Peak memory 222744 kb
Host smart-52dbb5d4-8aa8-4efc-b868-4c9b1edf9202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530437959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.2530437959
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.4181107242
Short name T836
Test name
Test status
Simulation time 1541732133 ps
CPU time 18.33 seconds
Started Jun 28 06:43:03 PM PDT 24
Finished Jun 28 06:45:36 PM PDT 24
Peak memory 226248 kb
Host smart-ecdeb8e3-ed13-4200-a017-5d7cf1ff3d7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181107242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.4181107242
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.3413791953
Short name T16
Test name
Test status
Simulation time 784525578 ps
CPU time 11.04 seconds
Started Jun 28 06:43:04 PM PDT 24
Finished Jun 28 06:45:48 PM PDT 24
Peak memory 218508 kb
Host smart-dc715b4e-3058-4d67-ae68-4252cc2570cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413791953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.3413791953
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.1209250612
Short name T592
Test name
Test status
Simulation time 359778412 ps
CPU time 9.86 seconds
Started Jun 28 06:43:04 PM PDT 24
Finished Jun 28 06:45:28 PM PDT 24
Peak memory 218432 kb
Host smart-8ab4a8a0-0753-4c7b-8f72-73bf453ed5aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209250612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
1209250612
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2310865695
Short name T622
Test name
Test status
Simulation time 656702051 ps
CPU time 8.8 seconds
Started Jun 28 06:42:55 PM PDT 24
Finished Jun 28 06:45:27 PM PDT 24
Peak memory 226252 kb
Host smart-7f7618e1-78b9-4f71-b391-812844cec569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310865695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2310865695
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.3338487851
Short name T60
Test name
Test status
Simulation time 712679311 ps
CPU time 2.95 seconds
Started Jun 28 06:42:55 PM PDT 24
Finished Jun 28 06:45:21 PM PDT 24
Peak memory 215120 kb
Host smart-c6e73173-c0f7-458d-8344-86365224079e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338487851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3338487851
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.1229979065
Short name T369
Test name
Test status
Simulation time 589449952 ps
CPU time 27.7 seconds
Started Jun 28 06:42:53 PM PDT 24
Finished Jun 28 06:45:56 PM PDT 24
Peak memory 251216 kb
Host smart-37252fcd-c099-4440-ba47-1b4114b3bee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229979065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1229979065
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3966256399
Short name T536
Test name
Test status
Simulation time 148831873 ps
CPU time 7.2 seconds
Started Jun 28 06:42:53 PM PDT 24
Finished Jun 28 06:45:25 PM PDT 24
Peak memory 251120 kb
Host smart-20030aa6-572f-4601-ad6a-e005ecc40be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966256399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3966256399
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.2099844580
Short name T646
Test name
Test status
Simulation time 1585302241 ps
CPU time 31.18 seconds
Started Jun 28 06:43:01 PM PDT 24
Finished Jun 28 06:45:49 PM PDT 24
Peak memory 249656 kb
Host smart-c6087d00-4a42-4107-ad4a-bc96f4b77bc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099844580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.2099844580
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3356777333
Short name T286
Test name
Test status
Simulation time 36230976 ps
CPU time 0.84 seconds
Started Jun 28 06:42:56 PM PDT 24
Finished Jun 28 06:45:19 PM PDT 24
Peak memory 212072 kb
Host smart-6bc1778f-c6cf-4bd2-910b-fb92520ecf01
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356777333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.3356777333
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2798360823
Short name T689
Test name
Test status
Simulation time 26105968 ps
CPU time 1.33 seconds
Started Jun 28 06:43:18 PM PDT 24
Finished Jun 28 06:45:37 PM PDT 24
Peak memory 209228 kb
Host smart-9e864858-1c86-47e7-a25f-cc90f2a0dce6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798360823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2798360823
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.548328418
Short name T710
Test name
Test status
Simulation time 1159627586 ps
CPU time 15.53 seconds
Started Jun 28 06:43:17 PM PDT 24
Finished Jun 28 06:46:29 PM PDT 24
Peak memory 218448 kb
Host smart-14207a0b-9bd8-4d54-b388-7c70cdfaeff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548328418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.548328418
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.980892628
Short name T703
Test name
Test status
Simulation time 757447560 ps
CPU time 7.6 seconds
Started Jun 28 06:43:07 PM PDT 24
Finished Jun 28 06:45:37 PM PDT 24
Peak memory 217604 kb
Host smart-0928a9b9-7d0e-4a8f-96ec-8da5285f3406
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980892628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.980892628
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2258264580
Short name T772
Test name
Test status
Simulation time 38517068 ps
CPU time 2.67 seconds
Started Jun 28 06:43:01 PM PDT 24
Finished Jun 28 06:45:17 PM PDT 24
Peak memory 222460 kb
Host smart-5f42bc46-6ca3-45d8-bfc0-3480a6cf5df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258264580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2258264580
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.134571085
Short name T609
Test name
Test status
Simulation time 1739612077 ps
CPU time 15.6 seconds
Started Jun 28 06:43:05 PM PDT 24
Finished Jun 28 06:45:34 PM PDT 24
Peak memory 226032 kb
Host smart-58ba3f33-4d5f-494b-9e5c-56e7ec059694
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134571085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.134571085
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.2864022342
Short name T166
Test name
Test status
Simulation time 1326358143 ps
CPU time 10.51 seconds
Started Jun 28 06:43:17 PM PDT 24
Finished Jun 28 06:46:41 PM PDT 24
Peak memory 218472 kb
Host smart-3ce67b32-31b6-4e54-94f5-85d33a2abdda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864022342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.2864022342
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.744698384
Short name T653
Test name
Test status
Simulation time 1237914503 ps
CPU time 12.49 seconds
Started Jun 28 06:43:04 PM PDT 24
Finished Jun 28 06:45:29 PM PDT 24
Peak memory 218432 kb
Host smart-3ae35f3a-f843-446e-8eea-81e0cc9d8a12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744698384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.744698384
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.2528862491
Short name T278
Test name
Test status
Simulation time 240009822 ps
CPU time 9.98 seconds
Started Jun 28 06:43:05 PM PDT 24
Finished Jun 28 06:45:27 PM PDT 24
Peak memory 218528 kb
Host smart-4126ec51-6656-45be-b12f-92eae70400b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528862491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.2528862491
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.4252356126
Short name T844
Test name
Test status
Simulation time 16285355 ps
CPU time 1.32 seconds
Started Jun 28 06:43:01 PM PDT 24
Finished Jun 28 06:45:28 PM PDT 24
Peak memory 217944 kb
Host smart-8035c595-84e2-4bbb-823d-d299d84d051a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252356126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.4252356126
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.3344873825
Short name T467
Test name
Test status
Simulation time 481696018 ps
CPU time 24.94 seconds
Started Jun 28 06:43:03 PM PDT 24
Finished Jun 28 06:45:43 PM PDT 24
Peak memory 251140 kb
Host smart-3279be2a-27db-4673-ac99-d8f85ab0ca9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344873825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.3344873825
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.3601324620
Short name T175
Test name
Test status
Simulation time 268526809 ps
CPU time 10.33 seconds
Started Jun 28 06:43:03 PM PDT 24
Finished Jun 28 06:45:28 PM PDT 24
Peak memory 251136 kb
Host smart-4fecf684-ad77-4089-aeb6-32d0c4c53c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601324620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3601324620
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3825072087
Short name T810
Test name
Test status
Simulation time 12121158308 ps
CPU time 106.29 seconds
Started Jun 28 06:43:17 PM PDT 24
Finished Jun 28 06:48:15 PM PDT 24
Peak memory 421324 kb
Host smart-c3f11dbb-f2e0-413c-8038-2a99f110ea22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825072087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3825072087
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3366251589
Short name T323
Test name
Test status
Simulation time 19648404 ps
CPU time 0.84 seconds
Started Jun 28 06:43:04 PM PDT 24
Finished Jun 28 06:45:18 PM PDT 24
Peak memory 212168 kb
Host smart-7259a04f-216e-415f-b938-19131773821d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366251589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.3366251589
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.250601146
Short name T273
Test name
Test status
Simulation time 31660099 ps
CPU time 0.89 seconds
Started Jun 28 06:43:29 PM PDT 24
Finished Jun 28 06:46:31 PM PDT 24
Peak memory 209252 kb
Host smart-a6475f16-078f-4cf3-b92f-9e8722bc0923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250601146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.250601146
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.4283898753
Short name T765
Test name
Test status
Simulation time 590444185 ps
CPU time 16.92 seconds
Started Jun 28 06:43:16 PM PDT 24
Finished Jun 28 06:46:06 PM PDT 24
Peak memory 226248 kb
Host smart-61dc6f90-5eb6-452a-9c99-0fa8c6682a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283898753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.4283898753
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.1507007142
Short name T792
Test name
Test status
Simulation time 3884531234 ps
CPU time 9.48 seconds
Started Jun 28 06:43:24 PM PDT 24
Finished Jun 28 06:45:46 PM PDT 24
Peak memory 217972 kb
Host smart-447a3776-8eb3-4816-991b-a273fffea1b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507007142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1507007142
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.3582544429
Short name T714
Test name
Test status
Simulation time 51261021 ps
CPU time 2.72 seconds
Started Jun 28 06:43:18 PM PDT 24
Finished Jun 28 06:46:33 PM PDT 24
Peak memory 218436 kb
Host smart-f22d183d-4bca-4ab9-950f-1fcbb90f1c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582544429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3582544429
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.881507675
Short name T685
Test name
Test status
Simulation time 292079941 ps
CPU time 13.04 seconds
Started Jun 28 06:43:30 PM PDT 24
Finished Jun 28 06:46:58 PM PDT 24
Peak memory 226212 kb
Host smart-79bcd54b-831b-403f-90b7-07925095984c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881507675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.881507675
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3786440780
Short name T237
Test name
Test status
Simulation time 330237185 ps
CPU time 11.71 seconds
Started Jun 28 06:43:24 PM PDT 24
Finished Jun 28 06:45:48 PM PDT 24
Peak memory 218424 kb
Host smart-22b5523a-fbfc-401f-93e2-a58d09828dda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786440780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
3786440780
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.3344324623
Short name T46
Test name
Test status
Simulation time 6787057663 ps
CPU time 10.36 seconds
Started Jun 28 06:43:13 PM PDT 24
Finished Jun 28 06:45:47 PM PDT 24
Peak memory 218560 kb
Host smart-6efa4316-eb94-4483-b4fc-4892e31178ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344324623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3344324623
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.3792337900
Short name T86
Test name
Test status
Simulation time 371555404 ps
CPU time 5.13 seconds
Started Jun 28 06:43:15 PM PDT 24
Finished Jun 28 06:46:36 PM PDT 24
Peak memory 217940 kb
Host smart-f01c99dd-a926-4265-bd9b-253ab9d2b008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792337900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.3792337900
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.4267709120
Short name T238
Test name
Test status
Simulation time 221564289 ps
CPU time 6.24 seconds
Started Jun 28 06:43:18 PM PDT 24
Finished Jun 28 06:46:28 PM PDT 24
Peak memory 246448 kb
Host smart-a1b292d5-cd88-4586-ba8d-42840eb645a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267709120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.4267709120
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.2777212732
Short name T248
Test name
Test status
Simulation time 2995026820 ps
CPU time 116.14 seconds
Started Jun 28 06:43:30 PM PDT 24
Finished Jun 28 06:48:25 PM PDT 24
Peak memory 327620 kb
Host smart-20fde239-0aca-4ed3-96d0-b12a79f121bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777212732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.2777212732
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1815494381
Short name T839
Test name
Test status
Simulation time 12667432 ps
CPU time 1.07 seconds
Started Jun 28 06:43:20 PM PDT 24
Finished Jun 28 06:46:14 PM PDT 24
Peak memory 212120 kb
Host smart-dfae74e8-be0a-417d-a7de-bde65b0a1f20
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815494381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.1815494381
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.1200859439
Short name T419
Test name
Test status
Simulation time 38369585 ps
CPU time 1.16 seconds
Started Jun 28 06:43:56 PM PDT 24
Finished Jun 28 06:46:46 PM PDT 24
Peak memory 209160 kb
Host smart-0ae9ebc0-dd94-4c21-9752-04976f82eda2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200859439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1200859439
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.427358392
Short name T36
Test name
Test status
Simulation time 392073750 ps
CPU time 13.99 seconds
Started Jun 28 06:43:40 PM PDT 24
Finished Jun 28 06:46:51 PM PDT 24
Peak memory 218388 kb
Host smart-59ffcd9e-c8c2-4406-bfb0-8d9a85832d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427358392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.427358392
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.2823659870
Short name T449
Test name
Test status
Simulation time 1813044365 ps
CPU time 5.97 seconds
Started Jun 28 06:43:41 PM PDT 24
Finished Jun 28 06:46:51 PM PDT 24
Peak memory 217892 kb
Host smart-77c54b5f-6020-46fc-9b84-c41ccfee306d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823659870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.2823659870
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1376355493
Short name T583
Test name
Test status
Simulation time 283278009 ps
CPU time 4.06 seconds
Started Jun 28 06:43:41 PM PDT 24
Finished Jun 28 06:46:49 PM PDT 24
Peak memory 218372 kb
Host smart-f25b46cb-6d38-4d6e-86d3-35876a28df54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376355493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1376355493
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.1213923975
Short name T18
Test name
Test status
Simulation time 719816221 ps
CPU time 11.37 seconds
Started Jun 28 06:45:08 PM PDT 24
Finished Jun 28 06:47:54 PM PDT 24
Peak memory 218432 kb
Host smart-e802a392-d0e1-4359-8baf-70dc460503e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213923975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.1213923975
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1452712051
Short name T742
Test name
Test status
Simulation time 2643007323 ps
CPU time 16.09 seconds
Started Jun 28 06:43:56 PM PDT 24
Finished Jun 28 06:47:01 PM PDT 24
Peak memory 218528 kb
Host smart-09ea0f06-17cd-450b-9547-47033305e61c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452712051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1452712051
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2090523612
Short name T502
Test name
Test status
Simulation time 2149988985 ps
CPU time 11.34 seconds
Started Jun 28 06:43:40 PM PDT 24
Finished Jun 28 06:46:25 PM PDT 24
Peak memory 218516 kb
Host smart-bff098a5-7435-42cd-9e0c-e0975d1b7066
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090523612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
2090523612
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.339064680
Short name T386
Test name
Test status
Simulation time 168703680 ps
CPU time 7.37 seconds
Started Jun 28 06:43:40 PM PDT 24
Finished Jun 28 06:45:51 PM PDT 24
Peak memory 218508 kb
Host smart-11476a56-0ba2-42e5-90dd-502fbcb85b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339064680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.339064680
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1184563291
Short name T480
Test name
Test status
Simulation time 165025490 ps
CPU time 19.99 seconds
Started Jun 28 06:43:27 PM PDT 24
Finished Jun 28 06:46:49 PM PDT 24
Peak memory 251176 kb
Host smart-8516f3ca-673f-433d-9364-00fb8b48a607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184563291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1184563291
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.4044299134
Short name T665
Test name
Test status
Simulation time 383528351 ps
CPU time 8.66 seconds
Started Jun 28 06:43:41 PM PDT 24
Finished Jun 28 06:46:09 PM PDT 24
Peak memory 251136 kb
Host smart-cbae91d6-182f-4963-b561-0386e209ebe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044299134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.4044299134
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.1199525236
Short name T326
Test name
Test status
Simulation time 19139563064 ps
CPU time 279.58 seconds
Started Jun 28 06:43:55 PM PDT 24
Finished Jun 28 06:50:51 PM PDT 24
Peak memory 251156 kb
Host smart-264f3a34-39a7-4954-a79f-2941f5a9f488
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199525236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.1199525236
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.2552278927
Short name T128
Test name
Test status
Simulation time 81494413201 ps
CPU time 1501.39 seconds
Started Jun 28 06:43:54 PM PDT 24
Finished Jun 28 07:11:32 PM PDT 24
Peak memory 496988 kb
Host smart-0d7e393d-5a68-4a51-8ccc-448f7574404a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2552278927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.2552278927
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3604131162
Short name T442
Test name
Test status
Simulation time 12641760 ps
CPU time 1.02 seconds
Started Jun 28 06:43:26 PM PDT 24
Finished Jun 28 06:45:44 PM PDT 24
Peak memory 212148 kb
Host smart-46efb06e-b52d-4ffe-b0f3-2756a16c58de
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604131162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3604131162
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.631883021
Short name T435
Test name
Test status
Simulation time 342707418 ps
CPU time 14.65 seconds
Started Jun 28 06:43:55 PM PDT 24
Finished Jun 28 06:46:26 PM PDT 24
Peak memory 218424 kb
Host smart-5787cb38-d841-492a-9685-eae7b9a26f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631883021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.631883021
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.102780034
Short name T28
Test name
Test status
Simulation time 1284429540 ps
CPU time 11.3 seconds
Started Jun 28 06:44:20 PM PDT 24
Finished Jun 28 06:46:36 PM PDT 24
Peak memory 217628 kb
Host smart-85ce13c8-38d0-43ac-8204-4b9e2fb24990
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102780034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.102780034
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.524459715
Short name T186
Test name
Test status
Simulation time 106950785 ps
CPU time 3.55 seconds
Started Jun 28 06:43:55 PM PDT 24
Finished Jun 28 06:46:33 PM PDT 24
Peak memory 218448 kb
Host smart-313b6bba-04b5-4edc-8741-97bf5dcedf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524459715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.524459715
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.575876275
Short name T366
Test name
Test status
Simulation time 316251170 ps
CPU time 11.12 seconds
Started Jun 28 06:45:19 PM PDT 24
Finished Jun 28 06:47:30 PM PDT 24
Peak memory 226228 kb
Host smart-aed7c115-e48f-4d8e-91c8-5aed4001b57b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575876275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.575876275
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1022510638
Short name T676
Test name
Test status
Simulation time 1024182939 ps
CPU time 27.38 seconds
Started Jun 28 06:44:09 PM PDT 24
Finished Jun 28 06:47:04 PM PDT 24
Peak memory 218452 kb
Host smart-72ca87cd-c68c-4c3e-9fb5-153c83c106ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022510638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1022510638
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.913799495
Short name T99
Test name
Test status
Simulation time 699492867 ps
CPU time 6.46 seconds
Started Jun 28 06:44:26 PM PDT 24
Finished Jun 28 06:46:35 PM PDT 24
Peak memory 225596 kb
Host smart-c4e6b0ed-d44a-4144-9549-653ed6f0dd06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913799495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.913799495
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1966204574
Short name T673
Test name
Test status
Simulation time 260380174 ps
CPU time 7.06 seconds
Started Jun 28 06:43:56 PM PDT 24
Finished Jun 28 06:46:37 PM PDT 24
Peak memory 218560 kb
Host smart-2f296af7-8a4f-4e39-bb36-b1e9a8d848a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966204574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1966204574
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3185982806
Short name T663
Test name
Test status
Simulation time 266902558 ps
CPU time 2.87 seconds
Started Jun 28 06:43:55 PM PDT 24
Finished Jun 28 06:46:33 PM PDT 24
Peak memory 214720 kb
Host smart-746fb3f3-c3b2-452b-8e3a-be6ad1a82211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185982806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3185982806
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.413610047
Short name T68
Test name
Test status
Simulation time 1463911456 ps
CPU time 24.85 seconds
Started Jun 28 06:43:56 PM PDT 24
Finished Jun 28 06:47:02 PM PDT 24
Peak memory 251144 kb
Host smart-cb711c4f-07f1-4f69-a277-a74d6b8de810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413610047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.413610047
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.2233192083
Short name T392
Test name
Test status
Simulation time 593441482 ps
CPU time 9.39 seconds
Started Jun 28 06:43:57 PM PDT 24
Finished Jun 28 06:46:09 PM PDT 24
Peak memory 251120 kb
Host smart-61b3629d-e873-4f49-8b3b-11481cdb829f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233192083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.2233192083
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.48982290
Short name T277
Test name
Test status
Simulation time 5247799094 ps
CPU time 46.65 seconds
Started Jun 28 06:44:21 PM PDT 24
Finished Jun 28 06:47:23 PM PDT 24
Peak memory 251112 kb
Host smart-16d56ce3-57f8-4600-b66e-f0565b5d28bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48982290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.lc_ctrl_stress_all.48982290
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2500679465
Short name T717
Test name
Test status
Simulation time 19668087 ps
CPU time 0.84 seconds
Started Jun 28 06:43:57 PM PDT 24
Finished Jun 28 06:46:37 PM PDT 24
Peak memory 212092 kb
Host smart-5aca067d-0328-469b-9982-01a0635cbdf8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500679465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2500679465
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.566015766
Short name T711
Test name
Test status
Simulation time 19601634 ps
CPU time 1.13 seconds
Started Jun 28 06:44:48 PM PDT 24
Finished Jun 28 06:46:46 PM PDT 24
Peak memory 209144 kb
Host smart-87104027-cf9e-4a84-849d-7293e6ee00e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566015766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.566015766
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.1976120586
Short name T340
Test name
Test status
Simulation time 1079048237 ps
CPU time 12.18 seconds
Started Jun 28 06:44:34 PM PDT 24
Finished Jun 28 06:47:48 PM PDT 24
Peak memory 218428 kb
Host smart-193de4ee-d671-446e-9449-625381826c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976120586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1976120586
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1767232998
Short name T784
Test name
Test status
Simulation time 1212588031 ps
CPU time 8.64 seconds
Started Jun 28 06:44:33 PM PDT 24
Finished Jun 28 06:47:20 PM PDT 24
Peak memory 217464 kb
Host smart-a3f64b1d-ab52-4aa9-a445-059a405cc5ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767232998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1767232998
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.773158566
Short name T761
Test name
Test status
Simulation time 582692242 ps
CPU time 13.12 seconds
Started Jun 28 06:44:34 PM PDT 24
Finished Jun 28 06:47:25 PM PDT 24
Peak memory 226252 kb
Host smart-59c77aee-1802-428b-ad1f-aaba4dad6aff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773158566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.773158566
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.754525248
Short name T451
Test name
Test status
Simulation time 481249598 ps
CPU time 15.39 seconds
Started Jun 28 06:44:34 PM PDT 24
Finished Jun 28 06:47:47 PM PDT 24
Peak memory 218452 kb
Host smart-36515a2b-2a3e-44fb-8449-14ed624dde13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754525248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_di
gest.754525248
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3095799624
Short name T183
Test name
Test status
Simulation time 1941897067 ps
CPU time 11.38 seconds
Started Jun 28 06:44:35 PM PDT 24
Finished Jun 28 06:47:11 PM PDT 24
Peak memory 218436 kb
Host smart-77ae695b-f1ec-4023-96b2-d629c1460b95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095799624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3095799624
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.228432498
Short name T105
Test name
Test status
Simulation time 360442265 ps
CPU time 8.2 seconds
Started Jun 28 06:44:33 PM PDT 24
Finished Jun 28 06:47:19 PM PDT 24
Peak memory 226304 kb
Host smart-87bbac80-d1f6-4781-8ee4-d7cfdbc59b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228432498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.228432498
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.84246244
Short name T606
Test name
Test status
Simulation time 42288708 ps
CPU time 3.17 seconds
Started Jun 28 06:44:21 PM PDT 24
Finished Jun 28 06:46:39 PM PDT 24
Peak memory 214744 kb
Host smart-63698c3d-c86a-44f9-bd29-2397457d6f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84246244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.84246244
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3045316062
Short name T485
Test name
Test status
Simulation time 229968147 ps
CPU time 24.94 seconds
Started Jun 28 06:44:21 PM PDT 24
Finished Jun 28 06:47:01 PM PDT 24
Peak memory 251116 kb
Host smart-02e11f01-7e89-4bc0-b997-f8f5dcaa2cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045316062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3045316062
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.2846640402
Short name T373
Test name
Test status
Simulation time 15590697844 ps
CPU time 504.94 seconds
Started Jun 28 06:44:34 PM PDT 24
Finished Jun 28 06:55:37 PM PDT 24
Peak memory 267648 kb
Host smart-d1e2165f-208a-4f43-84ad-84c3b3405675
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846640402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.2846640402
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.321649748
Short name T342
Test name
Test status
Simulation time 72134421 ps
CPU time 0.82 seconds
Started Jun 28 06:44:22 PM PDT 24
Finished Jun 28 06:46:38 PM PDT 24
Peak memory 212084 kb
Host smart-b1972722-fe82-4a09-8547-b82107af0b26
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321649748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ct
rl_volatile_unlock_smoke.321649748
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2908698339
Short name T625
Test name
Test status
Simulation time 58944335 ps
CPU time 0.88 seconds
Started Jun 28 06:45:09 PM PDT 24
Finished Jun 28 06:47:21 PM PDT 24
Peak memory 209180 kb
Host smart-aead73d2-3e3c-403a-bce6-2695dcc3c621
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908698339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2908698339
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.2429519848
Short name T462
Test name
Test status
Simulation time 284420169 ps
CPU time 13.49 seconds
Started Jun 28 06:44:56 PM PDT 24
Finished Jun 28 06:47:33 PM PDT 24
Peak memory 218440 kb
Host smart-afe55dea-bd70-4f89-9844-1f1d2784b46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429519848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2429519848
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1689193926
Short name T436
Test name
Test status
Simulation time 3039522135 ps
CPU time 6.72 seconds
Started Jun 28 06:44:56 PM PDT 24
Finished Jun 28 06:47:26 PM PDT 24
Peak memory 218000 kb
Host smart-3cc93ba1-b03d-4745-9f6b-334a2d68c919
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689193926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1689193926
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.4011701444
Short name T229
Test name
Test status
Simulation time 47186256 ps
CPU time 2.02 seconds
Started Jun 28 06:44:49 PM PDT 24
Finished Jun 28 06:47:23 PM PDT 24
Peak memory 222216 kb
Host smart-3a3f0eec-5c5f-4e6a-b471-d175e988b0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011701444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.4011701444
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.744233957
Short name T850
Test name
Test status
Simulation time 1095286910 ps
CPU time 11.25 seconds
Started Jun 28 06:44:55 PM PDT 24
Finished Jun 28 06:47:22 PM PDT 24
Peak memory 226236 kb
Host smart-466dc50b-03d5-4624-a2f3-ca004ee36de6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744233957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.744233957
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.4019795022
Short name T437
Test name
Test status
Simulation time 485583596 ps
CPU time 9.98 seconds
Started Jun 28 06:44:56 PM PDT 24
Finished Jun 28 06:47:29 PM PDT 24
Peak memory 218516 kb
Host smart-1c71d5b2-5f56-4345-a8ce-9d1dfb9e0ce2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019795022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.4019795022
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.1773189687
Short name T634
Test name
Test status
Simulation time 387794224 ps
CPU time 7.65 seconds
Started Jun 28 06:44:51 PM PDT 24
Finished Jun 28 06:46:53 PM PDT 24
Peak memory 218564 kb
Host smart-2bb7a566-34b1-4a2b-ae2b-1fbfae097f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773189687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1773189687
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.2381081992
Short name T231
Test name
Test status
Simulation time 167975237 ps
CPU time 2.18 seconds
Started Jun 28 06:44:41 PM PDT 24
Finished Jun 28 06:47:23 PM PDT 24
Peak memory 214604 kb
Host smart-f1f98d32-403a-4f9f-90ea-1f996121b0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381081992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2381081992
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3815599618
Short name T524
Test name
Test status
Simulation time 3475078565 ps
CPU time 26.43 seconds
Started Jun 28 06:44:43 PM PDT 24
Finished Jun 28 06:47:46 PM PDT 24
Peak memory 251200 kb
Host smart-5a56e61a-e5ca-4425-9c1b-5763bddad705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815599618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3815599618
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.2961872447
Short name T306
Test name
Test status
Simulation time 143722710 ps
CPU time 7.43 seconds
Started Jun 28 06:44:41 PM PDT 24
Finished Jun 28 06:46:53 PM PDT 24
Peak memory 247532 kb
Host smart-6f73d48f-e77b-4e4a-a24b-d7bd8f6eaf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961872447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.2961872447
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.4280772488
Short name T359
Test name
Test status
Simulation time 51376145 ps
CPU time 1.01 seconds
Started Jun 28 06:45:39 PM PDT 24
Finished Jun 28 06:47:36 PM PDT 24
Peak memory 209172 kb
Host smart-40c22c9b-b2f0-4d21-8c13-0037c20a7b5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280772488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.4280772488
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3666434594
Short name T460
Test name
Test status
Simulation time 205375895 ps
CPU time 8.42 seconds
Started Jun 28 06:46:32 PM PDT 24
Finished Jun 28 06:48:43 PM PDT 24
Peak memory 226248 kb
Host smart-7b37ef4c-49f0-41b9-8b2a-fe2f2ba2e4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666434594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3666434594
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.684118321
Short name T747
Test name
Test status
Simulation time 369689182 ps
CPU time 1.37 seconds
Started Jun 28 06:47:05 PM PDT 24
Finished Jun 28 06:49:22 PM PDT 24
Peak memory 217744 kb
Host smart-09e629eb-8a55-46a5-b812-64d10be50786
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684118321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.684118321
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.1403280880
Short name T434
Test name
Test status
Simulation time 75675869 ps
CPU time 3.05 seconds
Started Jun 28 06:45:23 PM PDT 24
Finished Jun 28 06:47:22 PM PDT 24
Peak memory 222656 kb
Host smart-364a2a07-3bd5-4c72-b8c1-714524873d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403280880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.1403280880
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.1448991486
Short name T294
Test name
Test status
Simulation time 2127603670 ps
CPU time 9.93 seconds
Started Jun 28 06:45:19 PM PDT 24
Finished Jun 28 06:47:29 PM PDT 24
Peak memory 219208 kb
Host smart-4c1b76c9-c5bc-462a-b70b-81565265136b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448991486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1448991486
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.236642121
Short name T427
Test name
Test status
Simulation time 349993599 ps
CPU time 12.09 seconds
Started Jun 28 06:45:19 PM PDT 24
Finished Jun 28 06:47:31 PM PDT 24
Peak memory 218440 kb
Host smart-8acc4dfb-0eb3-44b2-895e-886efa7fa64d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236642121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.236642121
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.3345021064
Short name T639
Test name
Test status
Simulation time 1413155792 ps
CPU time 8.99 seconds
Started Jun 28 06:45:29 PM PDT 24
Finished Jun 28 06:47:52 PM PDT 24
Peak memory 218496 kb
Host smart-1c048dad-7b99-435b-9d6f-839bf874cdc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345021064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.3345021064
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.533556261
Short name T701
Test name
Test status
Simulation time 29641259 ps
CPU time 1.57 seconds
Started Jun 28 06:45:09 PM PDT 24
Finished Jun 28 06:47:44 PM PDT 24
Peak memory 214332 kb
Host smart-756e1d70-8e20-4a61-8a16-bc50b71fb168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533556261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.533556261
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.408652341
Short name T226
Test name
Test status
Simulation time 489230501 ps
CPU time 26.19 seconds
Started Jun 28 06:45:18 PM PDT 24
Finished Jun 28 06:48:23 PM PDT 24
Peak memory 247588 kb
Host smart-a8c67cde-c9fc-46b3-b105-abcb0af27059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408652341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.408652341
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.4135951208
Short name T233
Test name
Test status
Simulation time 85122952 ps
CPU time 6.88 seconds
Started Jun 28 06:47:50 PM PDT 24
Finished Jun 28 06:49:45 PM PDT 24
Peak memory 250552 kb
Host smart-93ac5d89-942f-4ada-ab16-2d3f29263e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135951208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.4135951208
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.1382989560
Short name T557
Test name
Test status
Simulation time 20896080054 ps
CPU time 44.52 seconds
Started Jun 28 06:46:48 PM PDT 24
Finished Jun 28 06:49:31 PM PDT 24
Peak memory 271520 kb
Host smart-873cea3e-d56e-4d17-a958-e8e511549ab3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382989560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.1382989560
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.3511547212
Short name T165
Test name
Test status
Simulation time 80103479030 ps
CPU time 770.09 seconds
Started Jun 28 06:48:14 PM PDT 24
Finished Jun 28 07:03:00 PM PDT 24
Peak memory 308784 kb
Host smart-c3e7d0ef-7733-429d-b9fd-b852ed00b365
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3511547212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.3511547212
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.674466459
Short name T110
Test name
Test status
Simulation time 43747426 ps
CPU time 0.97 seconds
Started Jun 28 06:45:08 PM PDT 24
Finished Jun 28 06:47:33 PM PDT 24
Peak memory 212108 kb
Host smart-932b7105-b7fe-4d3f-ad12-b9fc61e492fc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674466459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ct
rl_volatile_unlock_smoke.674466459
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1056571083
Short name T774
Test name
Test status
Simulation time 566934447 ps
CPU time 4.57 seconds
Started Jun 28 06:46:00 PM PDT 24
Finished Jun 28 06:49:42 PM PDT 24
Peak memory 217296 kb
Host smart-c2921b3c-103a-4129-8a5e-6d7209539032
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056571083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.1056571083
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.327211358
Short name T464
Test name
Test status
Simulation time 1189029594 ps
CPU time 3.5 seconds
Started Jun 28 06:45:46 PM PDT 24
Finished Jun 28 06:48:39 PM PDT 24
Peak memory 218436 kb
Host smart-3fd691dd-b7e9-4ac8-a525-3c5a68c02fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327211358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.327211358
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.3014174386
Short name T313
Test name
Test status
Simulation time 416295819 ps
CPU time 13.84 seconds
Started Jun 28 06:45:57 PM PDT 24
Finished Jun 28 06:48:23 PM PDT 24
Peak memory 226248 kb
Host smart-438c9646-1708-43fa-94ee-c1c6545f69f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014174386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.3014174386
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2284737961
Short name T570
Test name
Test status
Simulation time 1545017210 ps
CPU time 9.07 seconds
Started Jun 28 06:45:54 PM PDT 24
Finished Jun 28 06:48:33 PM PDT 24
Peak memory 218520 kb
Host smart-3f918bb6-e899-4783-9592-8539a3ed21e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284737961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.2284737961
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.717572806
Short name T61
Test name
Test status
Simulation time 3522172140 ps
CPU time 23.98 seconds
Started Jun 28 06:45:47 PM PDT 24
Finished Jun 28 06:49:10 PM PDT 24
Peak memory 219152 kb
Host smart-1cf27f6e-3850-404e-8089-7653a650f0ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717572806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.717572806
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.3688289129
Short name T76
Test name
Test status
Simulation time 45864601 ps
CPU time 1.06 seconds
Started Jun 28 06:45:30 PM PDT 24
Finished Jun 28 06:47:44 PM PDT 24
Peak memory 212596 kb
Host smart-341642f9-aa2c-4752-b391-f51a2a23b499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688289129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.3688289129
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.2836161389
Short name T445
Test name
Test status
Simulation time 536235799 ps
CPU time 33.94 seconds
Started Jun 28 06:47:01 PM PDT 24
Finished Jun 28 06:49:43 PM PDT 24
Peak memory 246028 kb
Host smart-452aa69e-3200-46fd-a6d4-268a84305e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836161389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2836161389
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.3267152239
Short name T748
Test name
Test status
Simulation time 70984060 ps
CPU time 2.92 seconds
Started Jun 28 06:45:55 PM PDT 24
Finished Jun 28 06:47:56 PM PDT 24
Peak memory 222632 kb
Host smart-0726b25d-0c08-440c-8b7c-da44aef1b6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267152239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3267152239
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.2092499118
Short name T584
Test name
Test status
Simulation time 11117401230 ps
CPU time 362.62 seconds
Started Jun 28 06:46:07 PM PDT 24
Finished Jun 28 06:54:27 PM PDT 24
Peak memory 251184 kb
Host smart-3a8d0cbc-bf73-4b0d-ba42-667ec062c73a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092499118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.2092499118
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.4030113357
Short name T740
Test name
Test status
Simulation time 14863814 ps
CPU time 0.89 seconds
Started Jun 28 06:45:47 PM PDT 24
Finished Jun 28 06:48:10 PM PDT 24
Peak memory 212136 kb
Host smart-3db4b9ea-43d5-4480-97ea-36ca55aaa6af
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030113357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.4030113357
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.196941406
Short name T463
Test name
Test status
Simulation time 18021541 ps
CPU time 0.91 seconds
Started Jun 28 06:37:27 PM PDT 24
Finished Jun 28 06:37:34 PM PDT 24
Peak memory 209244 kb
Host smart-9b3e81e0-1ef0-4980-b5f4-f8ab351d0cf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196941406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.196941406
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.1825127187
Short name T217
Test name
Test status
Simulation time 58862925 ps
CPU time 0.8 seconds
Started Jun 28 06:37:26 PM PDT 24
Finished Jun 28 06:37:30 PM PDT 24
Peak memory 209188 kb
Host smart-d9417001-c54a-49c1-b6b6-565a60c0ce38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825127187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1825127187
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.840503221
Short name T835
Test name
Test status
Simulation time 346656841 ps
CPU time 13.25 seconds
Started Jun 28 06:37:15 PM PDT 24
Finished Jun 28 06:37:32 PM PDT 24
Peak memory 226264 kb
Host smart-a7345d5b-dfb2-40c5-ba9c-fd8d5a9c51cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840503221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.840503221
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.1702423849
Short name T420
Test name
Test status
Simulation time 614877053 ps
CPU time 14.74 seconds
Started Jun 28 06:37:17 PM PDT 24
Finished Jun 28 06:37:34 PM PDT 24
Peak memory 217628 kb
Host smart-04d6ec9c-bab3-4f48-8043-e700a7dd48b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702423849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.1702423849
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.788110523
Short name T834
Test name
Test status
Simulation time 1710394513 ps
CPU time 29.61 seconds
Started Jun 28 06:37:22 PM PDT 24
Finished Jun 28 06:37:53 PM PDT 24
Peak memory 218444 kb
Host smart-c87d90af-a6ed-45a0-bbe6-80163797dddd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788110523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_err
ors.788110523
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.657147959
Short name T287
Test name
Test status
Simulation time 2914309190 ps
CPU time 7.15 seconds
Started Jun 28 06:37:16 PM PDT 24
Finished Jun 28 06:37:26 PM PDT 24
Peak memory 218100 kb
Host smart-805794ea-53de-464c-bc24-4d4a1783fad3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657147959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.657147959
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1238576292
Short name T659
Test name
Test status
Simulation time 1164608032 ps
CPU time 9.19 seconds
Started Jun 28 06:37:17 PM PDT 24
Finished Jun 28 06:37:29 PM PDT 24
Peak memory 218444 kb
Host smart-d7cb3d5a-2999-46b8-99a0-090b819950dc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238576292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1238576292
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.449083470
Short name T728
Test name
Test status
Simulation time 645343488 ps
CPU time 10.89 seconds
Started Jun 28 06:37:26 PM PDT 24
Finished Jun 28 06:37:42 PM PDT 24
Peak memory 217940 kb
Host smart-dffd5841-e01b-4146-a355-dbe619fe0298
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449083470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_regwen_during_op.449083470
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.935399267
Short name T372
Test name
Test status
Simulation time 261878087 ps
CPU time 7.13 seconds
Started Jun 28 06:37:16 PM PDT 24
Finished Jun 28 06:37:26 PM PDT 24
Peak memory 217864 kb
Host smart-3a1e8dbf-5fcb-4425-a3dc-59f9b15c4b69
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935399267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.935399267
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3157664161
Short name T704
Test name
Test status
Simulation time 1149717775 ps
CPU time 41.51 seconds
Started Jun 28 06:37:23 PM PDT 24
Finished Jun 28 06:38:05 PM PDT 24
Peak memory 252048 kb
Host smart-555f3014-fe43-4690-8f42-e5ce313dada4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157664161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.3157664161
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.2534307487
Short name T189
Test name
Test status
Simulation time 530954294 ps
CPU time 23.66 seconds
Started Jun 28 06:37:13 PM PDT 24
Finished Jun 28 06:37:39 PM PDT 24
Peak memory 251116 kb
Host smart-17880656-5c9a-4a87-94df-81ec720a5baa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534307487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.2534307487
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.633961033
Short name T721
Test name
Test status
Simulation time 130078123 ps
CPU time 1.89 seconds
Started Jun 28 06:37:18 PM PDT 24
Finished Jun 28 06:37:22 PM PDT 24
Peak memory 218432 kb
Host smart-74fcc20f-0563-4f07-84ed-0ef53204de2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633961033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.633961033
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1199488451
Short name T624
Test name
Test status
Simulation time 334537948 ps
CPU time 9.05 seconds
Started Jun 28 06:37:15 PM PDT 24
Finished Jun 28 06:37:27 PM PDT 24
Peak memory 214496 kb
Host smart-cbf0de32-ee14-43f1-9aea-015d2b41204c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199488451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1199488451
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.2876094090
Short name T112
Test name
Test status
Simulation time 301083583 ps
CPU time 35.86 seconds
Started Jun 28 06:37:31 PM PDT 24
Finished Jun 28 06:38:16 PM PDT 24
Peak memory 269020 kb
Host smart-cf438294-55cd-4a04-bb84-9002895a4f28
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876094090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2876094090
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.1575252622
Short name T295
Test name
Test status
Simulation time 428885308 ps
CPU time 13.4 seconds
Started Jun 28 06:37:16 PM PDT 24
Finished Jun 28 06:37:32 PM PDT 24
Peak memory 219108 kb
Host smart-f5861f1e-b670-416c-a118-4f4857c41331
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575252622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1575252622
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.1057086659
Short name T264
Test name
Test status
Simulation time 1638485426 ps
CPU time 15.21 seconds
Started Jun 28 06:37:30 PM PDT 24
Finished Jun 28 06:37:55 PM PDT 24
Peak memory 218340 kb
Host smart-aa9ce1ee-1b1e-41cf-b35c-e7a5820759e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057086659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.1057086659
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.2398807544
Short name T432
Test name
Test status
Simulation time 1272557616 ps
CPU time 12.23 seconds
Started Jun 28 06:37:30 PM PDT 24
Finished Jun 28 06:37:52 PM PDT 24
Peak memory 218400 kb
Host smart-6f46afa1-4154-4bbb-a540-aa15c2f0d14f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398807544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.2
398807544
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.1528219832
Short name T45
Test name
Test status
Simulation time 434225662 ps
CPU time 7.51 seconds
Started Jun 28 06:37:16 PM PDT 24
Finished Jun 28 06:37:26 PM PDT 24
Peak memory 218508 kb
Host smart-e9e81e77-74d5-46c3-a5a1-1f12a8e2b23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528219832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1528219832
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.3168605202
Short name T470
Test name
Test status
Simulation time 100596749 ps
CPU time 1.57 seconds
Started Jun 28 06:37:19 PM PDT 24
Finished Jun 28 06:37:22 PM PDT 24
Peak memory 214200 kb
Host smart-583689b8-890b-4b45-9450-b4ddad40c1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168605202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3168605202
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.1278614867
Short name T230
Test name
Test status
Simulation time 296154111 ps
CPU time 27.04 seconds
Started Jun 28 06:37:20 PM PDT 24
Finished Jun 28 06:37:48 PM PDT 24
Peak memory 251212 kb
Host smart-8072e697-f6a3-4621-935c-5246e53b7e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278614867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1278614867
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1297916925
Short name T405
Test name
Test status
Simulation time 98549449 ps
CPU time 3.26 seconds
Started Jun 28 06:37:16 PM PDT 24
Finished Jun 28 06:37:22 PM PDT 24
Peak memory 226252 kb
Host smart-bd52d58d-4268-42e9-8f97-661bf94f3504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297916925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1297916925
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3176738705
Short name T421
Test name
Test status
Simulation time 6730590464 ps
CPU time 51.7 seconds
Started Jun 28 06:37:30 PM PDT 24
Finished Jun 28 06:38:31 PM PDT 24
Peak memory 268272 kb
Host smart-18117073-7f80-42e1-a304-7a4c00857e10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176738705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3176738705
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2104770978
Short name T11
Test name
Test status
Simulation time 25983575 ps
CPU time 1.1 seconds
Started Jun 28 06:37:19 PM PDT 24
Finished Jun 28 06:37:21 PM PDT 24
Peak memory 217944 kb
Host smart-e5ba5471-57f5-4294-a780-c01c6e2c1aad
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104770978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2104770978
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.632465759
Short name T707
Test name
Test status
Simulation time 52609716 ps
CPU time 1.1 seconds
Started Jun 28 06:46:18 PM PDT 24
Finished Jun 28 06:48:03 PM PDT 24
Peak memory 209188 kb
Host smart-a245647e-9781-49d7-a918-a67154943fda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632465759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.632465759
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.3260503996
Short name T56
Test name
Test status
Simulation time 380111764 ps
CPU time 12.5 seconds
Started Jun 28 06:46:10 PM PDT 24
Finished Jun 28 06:48:37 PM PDT 24
Peak memory 218436 kb
Host smart-53ef65ad-696a-44e0-a378-43fac3243162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260503996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3260503996
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.2281143559
Short name T32
Test name
Test status
Simulation time 979659343 ps
CPU time 6.65 seconds
Started Jun 28 06:46:10 PM PDT 24
Finished Jun 28 06:48:41 PM PDT 24
Peak memory 217716 kb
Host smart-f1ac838e-e44a-43a5-9720-ed3681f666e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281143559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.2281143559
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.991905168
Short name T613
Test name
Test status
Simulation time 124535116 ps
CPU time 1.84 seconds
Started Jun 28 06:46:07 PM PDT 24
Finished Jun 28 06:48:09 PM PDT 24
Peak memory 218440 kb
Host smart-0b780587-89b0-444d-a3a3-67be8ceed451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991905168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.991905168
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.3492756844
Short name T732
Test name
Test status
Simulation time 307078193 ps
CPU time 12.53 seconds
Started Jun 28 06:48:43 PM PDT 24
Finished Jun 28 06:51:05 PM PDT 24
Peak memory 218412 kb
Host smart-3bea00ba-5f2f-4f98-a931-6a317b765b87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492756844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.3492756844
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.3707841268
Short name T246
Test name
Test status
Simulation time 59290240 ps
CPU time 1.55 seconds
Started Jun 28 06:46:08 PM PDT 24
Finished Jun 28 06:48:37 PM PDT 24
Peak memory 214052 kb
Host smart-3ce1fcb4-0b55-4144-b27c-8e16aa17dc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707841268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3707841268
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.2702790546
Short name T750
Test name
Test status
Simulation time 6113732472 ps
CPU time 154.91 seconds
Started Jun 28 06:47:22 PM PDT 24
Finished Jun 28 06:52:46 PM PDT 24
Peak memory 282716 kb
Host smart-ee426f8c-9c09-4681-88bc-e7394daa0b95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702790546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.2702790546
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.1355792987
Short name T164
Test name
Test status
Simulation time 30336597680 ps
CPU time 190.32 seconds
Started Jun 28 06:46:16 PM PDT 24
Finished Jun 28 06:51:46 PM PDT 24
Peak memory 365584 kb
Host smart-40eceed0-7e4f-4479-87c5-1427fc621628
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1355792987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.1355792987
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.968361016
Short name T702
Test name
Test status
Simulation time 99425019 ps
CPU time 0.82 seconds
Started Jun 28 06:46:10 PM PDT 24
Finished Jun 28 06:48:36 PM PDT 24
Peak memory 212072 kb
Host smart-95903b85-5907-4fac-899d-c387e6851ce5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968361016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct
rl_volatile_unlock_smoke.968361016
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.1077686507
Short name T33
Test name
Test status
Simulation time 19488338 ps
CPU time 0.97 seconds
Started Jun 28 06:46:28 PM PDT 24
Finished Jun 28 06:48:46 PM PDT 24
Peak memory 209168 kb
Host smart-21bdfae5-6a2d-498f-9ba8-42af77be829c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077686507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1077686507
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.3625015228
Short name T438
Test name
Test status
Simulation time 1749827645 ps
CPU time 12.56 seconds
Started Jun 28 06:46:29 PM PDT 24
Finished Jun 28 06:48:47 PM PDT 24
Peak memory 226252 kb
Host smart-86d2d8fa-6857-420e-9471-cff6399aa576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625015228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3625015228
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3729422288
Short name T498
Test name
Test status
Simulation time 486320019 ps
CPU time 3.53 seconds
Started Jun 28 06:46:42 PM PDT 24
Finished Jun 28 06:49:12 PM PDT 24
Peak memory 217488 kb
Host smart-695855c9-19ce-450f-a3f0-f6cd8ebd87ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729422288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3729422288
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.2681865987
Short name T705
Test name
Test status
Simulation time 79659518 ps
CPU time 1.83 seconds
Started Jun 28 06:49:02 PM PDT 24
Finished Jun 28 06:50:41 PM PDT 24
Peak memory 218436 kb
Host smart-40ce4683-5a62-42aa-b07c-c097ed6eb3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681865987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.2681865987
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.1029890402
Short name T518
Test name
Test status
Simulation time 587869113 ps
CPU time 12.71 seconds
Started Jun 28 06:48:14 PM PDT 24
Finished Jun 28 06:50:24 PM PDT 24
Peak memory 219100 kb
Host smart-4eb47d42-3725-4391-b1fb-2ae7ce7aa6cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029890402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.1029890402
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2081621
Short name T235
Test name
Test status
Simulation time 1681341567 ps
CPU time 13.07 seconds
Started Jun 28 06:46:33 PM PDT 24
Finished Jun 28 06:49:44 PM PDT 24
Peak memory 218456 kb
Host smart-968b66a4-c70f-42aa-9480-ba0226d7742f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dige
st_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_dige
st.2081621
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2546805819
Short name T488
Test name
Test status
Simulation time 608337822 ps
CPU time 7.84 seconds
Started Jun 28 06:46:34 PM PDT 24
Finished Jun 28 06:49:17 PM PDT 24
Peak memory 218428 kb
Host smart-cf6bd567-ef5c-425c-a814-11c78748d7d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546805819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
2546805819
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.1046014106
Short name T650
Test name
Test status
Simulation time 293501961 ps
CPU time 7.47 seconds
Started Jun 28 06:46:39 PM PDT 24
Finished Jun 28 06:49:27 PM PDT 24
Peak memory 218628 kb
Host smart-874182f6-8070-4283-8b53-1240419b8642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046014106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1046014106
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.308851773
Short name T336
Test name
Test status
Simulation time 136494202 ps
CPU time 3.78 seconds
Started Jun 28 06:46:17 PM PDT 24
Finished Jun 28 06:48:39 PM PDT 24
Peak memory 217924 kb
Host smart-504e4c73-0900-43ca-8199-ddeeeb975a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308851773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.308851773
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.3121865548
Short name T260
Test name
Test status
Simulation time 431814228 ps
CPU time 19.62 seconds
Started Jun 28 06:48:08 PM PDT 24
Finished Jun 28 06:50:22 PM PDT 24
Peak memory 251136 kb
Host smart-6d7dd2e8-3a3b-47ed-83da-51c5ec6ecb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121865548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.3121865548
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.2578623706
Short name T652
Test name
Test status
Simulation time 599787110 ps
CPU time 3.25 seconds
Started Jun 28 06:46:34 PM PDT 24
Finished Jun 28 06:48:38 PM PDT 24
Peak memory 222468 kb
Host smart-518add9c-6e23-4fd5-955e-5678986d76f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578623706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.2578623706
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3370968739
Short name T415
Test name
Test status
Simulation time 45104812265 ps
CPU time 433.45 seconds
Started Jun 28 06:49:21 PM PDT 24
Finished Jun 28 06:58:17 PM PDT 24
Peak memory 405780 kb
Host smart-5e92d5e3-9b81-41c4-85bf-07f0bcd93812
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370968739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3370968739
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.2824050726
Short name T671
Test name
Test status
Simulation time 104634001376 ps
CPU time 1058.69 seconds
Started Jun 28 06:47:48 PM PDT 24
Finished Jun 28 07:07:17 PM PDT 24
Peak memory 292288 kb
Host smart-280e4a7c-aa78-453b-a72d-ab78c350593c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2824050726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.2824050726
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1738766075
Short name T537
Test name
Test status
Simulation time 62652854 ps
CPU time 0.9 seconds
Started Jun 28 06:48:03 PM PDT 24
Finished Jun 28 06:50:05 PM PDT 24
Peak memory 213136 kb
Host smart-d04e933d-c94a-4d63-8d19-8c0ed99eccfc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738766075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1738766075
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.4163774362
Short name T397
Test name
Test status
Simulation time 171527041 ps
CPU time 1 seconds
Started Jun 28 06:46:55 PM PDT 24
Finished Jun 28 06:49:00 PM PDT 24
Peak memory 209176 kb
Host smart-14a035a8-c2f5-4014-a7a1-42151a68a1dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163774362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.4163774362
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2163562431
Short name T334
Test name
Test status
Simulation time 1084970955 ps
CPU time 9.16 seconds
Started Jun 28 06:46:45 PM PDT 24
Finished Jun 28 06:48:56 PM PDT 24
Peak memory 218436 kb
Host smart-69e28391-2226-4323-8eb3-8d43121fd2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163562431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2163562431
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2106000857
Short name T456
Test name
Test status
Simulation time 256312321 ps
CPU time 3.57 seconds
Started Jun 28 06:46:48 PM PDT 24
Finished Jun 28 06:48:47 PM PDT 24
Peak memory 217372 kb
Host smart-4e71f883-4044-4e82-a980-5cfa0f516dca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106000857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.2106000857
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.4061944060
Short name T413
Test name
Test status
Simulation time 42568258 ps
CPU time 1.81 seconds
Started Jun 28 06:46:33 PM PDT 24
Finished Jun 28 06:49:33 PM PDT 24
Peak memory 218420 kb
Host smart-6ba61114-60a0-45e2-9876-078b4cb5c7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061944060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.4061944060
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.357447277
Short name T491
Test name
Test status
Simulation time 279510455 ps
CPU time 14.85 seconds
Started Jun 28 06:46:28 PM PDT 24
Finished Jun 28 06:49:00 PM PDT 24
Peak memory 226352 kb
Host smart-94fa3a0b-b6ae-4ed8-ba8c-05f0dd74aa30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357447277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.357447277
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.3083455243
Short name T104
Test name
Test status
Simulation time 1162481654 ps
CPU time 11.38 seconds
Started Jun 28 06:46:33 PM PDT 24
Finished Jun 28 06:49:11 PM PDT 24
Peak memory 218464 kb
Host smart-6f73ac94-7254-4250-a699-5011583a8fff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083455243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.3083455243
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.119130809
Short name T614
Test name
Test status
Simulation time 326224503 ps
CPU time 11.56 seconds
Started Jun 28 06:49:10 PM PDT 24
Finished Jun 28 06:51:11 PM PDT 24
Peak memory 218488 kb
Host smart-dca6810b-d2cb-445b-bfbb-0646a6fa8992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119130809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.119130809
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.1014574836
Short name T489
Test name
Test status
Simulation time 176622094 ps
CPU time 2.68 seconds
Started Jun 28 06:46:37 PM PDT 24
Finished Jun 28 06:49:23 PM PDT 24
Peak memory 214940 kb
Host smart-9d9a5e4f-6c57-4a3b-9aac-e1b7c9084ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014574836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.1014574836
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.606912507
Short name T21
Test name
Test status
Simulation time 462760694 ps
CPU time 16.65 seconds
Started Jun 28 06:46:33 PM PDT 24
Finished Jun 28 06:48:43 PM PDT 24
Peak memory 251108 kb
Host smart-65646baa-6fda-4c33-ba2c-01ccf2f96ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606912507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.606912507
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.2505824108
Short name T627
Test name
Test status
Simulation time 587011225 ps
CPU time 6.57 seconds
Started Jun 28 06:46:33 PM PDT 24
Finished Jun 28 06:48:52 PM PDT 24
Peak memory 246860 kb
Host smart-04fd9cac-7bba-4258-aa44-2119c1ec3d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505824108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.2505824108
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.4249523758
Short name T296
Test name
Test status
Simulation time 2403470505 ps
CPU time 35.7 seconds
Started Jun 28 06:47:54 PM PDT 24
Finished Jun 28 06:50:43 PM PDT 24
Peak memory 226224 kb
Host smart-7df6dd88-af7d-4650-9d26-9ad7b69ae464
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249523758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.4249523758
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1833666393
Short name T96
Test name
Test status
Simulation time 10476531 ps
CPU time 0.87 seconds
Started Jun 28 06:47:48 PM PDT 24
Finished Jun 28 06:50:12 PM PDT 24
Peak memory 208500 kb
Host smart-99cabdee-c40c-46e4-bb34-4d48eab47e74
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833666393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1833666393
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.335580822
Short name T333
Test name
Test status
Simulation time 23859072 ps
CPU time 0.97 seconds
Started Jun 28 06:46:51 PM PDT 24
Finished Jun 28 06:48:45 PM PDT 24
Peak memory 209220 kb
Host smart-a711f86a-e8db-4512-880f-c5c9acfabbab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335580822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.335580822
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.819492437
Short name T483
Test name
Test status
Simulation time 217025117 ps
CPU time 10.54 seconds
Started Jun 28 06:46:40 PM PDT 24
Finished Jun 28 06:49:42 PM PDT 24
Peak memory 218436 kb
Host smart-86ddec05-bd7e-4968-b1da-f812bbe60c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819492437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.819492437
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.2012144860
Short name T654
Test name
Test status
Simulation time 724972515 ps
CPU time 4.61 seconds
Started Jun 28 06:47:05 PM PDT 24
Finished Jun 28 06:50:17 PM PDT 24
Peak memory 217428 kb
Host smart-943708ca-0fe1-4f5f-b3a0-8a054314bfbc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012144860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.2012144860
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1890898220
Short name T34
Test name
Test status
Simulation time 122039321 ps
CPU time 2.18 seconds
Started Jun 28 06:47:53 PM PDT 24
Finished Jun 28 06:50:28 PM PDT 24
Peak memory 218412 kb
Host smart-6f91fc95-a431-48ba-8f61-c024ee39d453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890898220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1890898220
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.3096393780
Short name T304
Test name
Test status
Simulation time 400477732 ps
CPU time 13 seconds
Started Jun 28 06:48:03 PM PDT 24
Finished Jun 28 06:50:17 PM PDT 24
Peak memory 226252 kb
Host smart-9e6547ed-783e-48bc-915b-37f902076cf0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096393780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.3096393780
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3222155661
Short name T722
Test name
Test status
Simulation time 4187954336 ps
CPU time 16.1 seconds
Started Jun 28 06:46:57 PM PDT 24
Finished Jun 28 06:49:16 PM PDT 24
Peak memory 218644 kb
Host smart-45c7e3ba-9f9d-4a30-a61e-fed4f50428f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222155661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.3222155661
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3547005149
Short name T492
Test name
Test status
Simulation time 4648985466 ps
CPU time 12.26 seconds
Started Jun 28 06:46:58 PM PDT 24
Finished Jun 28 06:49:38 PM PDT 24
Peak memory 218504 kb
Host smart-30a6b7d0-aa83-4d34-a963-53aa2811ac01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547005149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3547005149
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.1690871894
Short name T607
Test name
Test status
Simulation time 40629451 ps
CPU time 2.03 seconds
Started Jun 28 06:47:54 PM PDT 24
Finished Jun 28 06:49:52 PM PDT 24
Peak memory 214256 kb
Host smart-720ad2c6-3d1a-4af7-8406-6644d1e88c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690871894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1690871894
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.3110444637
Short name T693
Test name
Test status
Simulation time 266817648 ps
CPU time 27.52 seconds
Started Jun 28 06:46:41 PM PDT 24
Finished Jun 28 06:49:12 PM PDT 24
Peak memory 251128 kb
Host smart-773134be-b37f-49d7-8298-2acef88f1119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110444637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3110444637
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.25712291
Short name T566
Test name
Test status
Simulation time 183370135 ps
CPU time 3.46 seconds
Started Jun 28 06:47:53 PM PDT 24
Finished Jun 28 06:49:42 PM PDT 24
Peak memory 222592 kb
Host smart-efb8fbcc-16c5-4bce-a549-94979636d50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25712291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.25712291
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1265429611
Short name T119
Test name
Test status
Simulation time 20348940031 ps
CPU time 635.12 seconds
Started Jun 28 06:46:58 PM PDT 24
Finished Jun 28 06:59:31 PM PDT 24
Peak memory 283912 kb
Host smart-2fd542cf-06ff-486d-b5f1-895ca93594a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265429611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1265429611
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.574781563
Short name T162
Test name
Test status
Simulation time 79454553265 ps
CPU time 760.89 seconds
Started Jun 28 06:47:05 PM PDT 24
Finished Jun 28 07:01:51 PM PDT 24
Peak memory 284156 kb
Host smart-d5a4a356-f197-4e6b-9938-4b20a9723eed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=574781563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.574781563
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.966680527
Short name T739
Test name
Test status
Simulation time 22087602 ps
CPU time 0.93 seconds
Started Jun 28 06:50:39 PM PDT 24
Finished Jun 28 06:51:39 PM PDT 24
Peak memory 212176 kb
Host smart-dff3b314-832a-4ea7-97b4-67d538b1ac42
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966680527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct
rl_volatile_unlock_smoke.966680527
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1111715836
Short name T591
Test name
Test status
Simulation time 21047576 ps
CPU time 0.95 seconds
Started Jun 28 06:47:22 PM PDT 24
Finished Jun 28 06:49:32 PM PDT 24
Peak memory 209152 kb
Host smart-2d1adcd6-da67-476b-b46f-3aeffd40a9cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111715836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1111715836
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.3053090510
Short name T619
Test name
Test status
Simulation time 349013173 ps
CPU time 9.41 seconds
Started Jun 28 06:47:06 PM PDT 24
Finished Jun 28 06:49:18 PM PDT 24
Peak memory 218440 kb
Host smart-3a0ecefa-5ea6-42ad-a1ab-710e9dc9cb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053090510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.3053090510
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.1028612789
Short name T588
Test name
Test status
Simulation time 323837306 ps
CPU time 3.24 seconds
Started Jun 28 06:47:03 PM PDT 24
Finished Jun 28 06:49:13 PM PDT 24
Peak memory 218508 kb
Host smart-e5342658-d315-4cf6-a1f6-5a1cf7dc4933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028612789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1028612789
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.1091273540
Short name T396
Test name
Test status
Simulation time 1659143774 ps
CPU time 14.02 seconds
Started Jun 28 06:47:13 PM PDT 24
Finished Jun 28 06:49:52 PM PDT 24
Peak memory 226256 kb
Host smart-041189cb-58ea-48b3-a30b-86a8d17d9722
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091273540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1091273540
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.762192754
Short name T282
Test name
Test status
Simulation time 1040721335 ps
CPU time 10.25 seconds
Started Jun 28 06:47:21 PM PDT 24
Finished Jun 28 06:50:21 PM PDT 24
Peak memory 218452 kb
Host smart-42957779-00ab-41d6-a2ba-3cbaac96a17e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762192754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.762192754
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.342765141
Short name T339
Test name
Test status
Simulation time 503396841 ps
CPU time 11.31 seconds
Started Jun 28 06:48:33 PM PDT 24
Finished Jun 28 06:50:32 PM PDT 24
Peak memory 226236 kb
Host smart-c7d24f49-b429-47a1-839b-6132664d6f53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342765141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.342765141
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.2063494390
Short name T44
Test name
Test status
Simulation time 296925267 ps
CPU time 9.42 seconds
Started Jun 28 06:47:05 PM PDT 24
Finished Jun 28 06:49:29 PM PDT 24
Peak memory 218568 kb
Host smart-87ffa29e-77a7-480c-8e19-8be8cf4f9aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063494390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.2063494390
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2173752048
Short name T71
Test name
Test status
Simulation time 245735521 ps
CPU time 3.64 seconds
Started Jun 28 06:47:04 PM PDT 24
Finished Jun 28 06:49:13 PM PDT 24
Peak memory 217920 kb
Host smart-40f53dd6-8f1b-4144-9d1f-5025a4072d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173752048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2173752048
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.135197128
Short name T517
Test name
Test status
Simulation time 656589928 ps
CPU time 36.99 seconds
Started Jun 28 06:47:03 PM PDT 24
Finished Jun 28 06:49:47 PM PDT 24
Peak memory 251108 kb
Host smart-df7bfc49-db1a-416e-b88a-0d5cef406d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135197128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.135197128
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.1340175379
Short name T573
Test name
Test status
Simulation time 300249161 ps
CPU time 4.14 seconds
Started Jun 28 06:47:05 PM PDT 24
Finished Jun 28 06:49:24 PM PDT 24
Peak memory 222592 kb
Host smart-bbf0f14f-2fc5-4bcb-9867-0dee0fa1d1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340175379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1340175379
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.4028513239
Short name T64
Test name
Test status
Simulation time 4126979018 ps
CPU time 47.89 seconds
Started Jun 28 06:47:17 PM PDT 24
Finished Jun 28 06:50:20 PM PDT 24
Peak memory 253920 kb
Host smart-19d7a554-b1c6-416b-baf5-5fa767b3a1f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028513239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.4028513239
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.1072520721
Short name T124
Test name
Test status
Simulation time 30944338255 ps
CPU time 1078.58 seconds
Started Jun 28 06:47:15 PM PDT 24
Finished Jun 28 07:07:08 PM PDT 24
Peak memory 314044 kb
Host smart-e6d8a8ae-9bc7-4ee4-afdc-0c2318a15b13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1072520721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.1072520721
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.476315670
Short name T384
Test name
Test status
Simulation time 31673172 ps
CPU time 0.89 seconds
Started Jun 28 06:47:05 PM PDT 24
Finished Jun 28 06:49:21 PM PDT 24
Peak memory 212192 kb
Host smart-5081e9c0-754d-4a47-9e48-e8cf923daddc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476315670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ct
rl_volatile_unlock_smoke.476315670
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.1350670239
Short name T410
Test name
Test status
Simulation time 69781188 ps
CPU time 0.88 seconds
Started Jun 28 06:47:36 PM PDT 24
Finished Jun 28 06:49:26 PM PDT 24
Peak memory 209112 kb
Host smart-9b99f747-626b-4f7c-828b-e5cedfaefb78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350670239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1350670239
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.2708700405
Short name T744
Test name
Test status
Simulation time 1620447644 ps
CPU time 16.8 seconds
Started Jun 28 06:47:32 PM PDT 24
Finished Jun 28 06:49:48 PM PDT 24
Peak memory 218376 kb
Host smart-ca19c4d4-e661-401b-a947-548b0e5f1b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708700405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.2708700405
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2752603476
Short name T719
Test name
Test status
Simulation time 40310152 ps
CPU time 1.69 seconds
Started Jun 28 06:47:33 PM PDT 24
Finished Jun 28 06:49:33 PM PDT 24
Peak memory 217364 kb
Host smart-5fd8b34f-2da9-44f5-ad03-7c5dce12ca09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752603476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2752603476
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.3042150060
Short name T512
Test name
Test status
Simulation time 439074649 ps
CPU time 3.41 seconds
Started Jun 28 06:48:39 PM PDT 24
Finished Jun 28 06:50:30 PM PDT 24
Peak memory 218436 kb
Host smart-cf147743-8722-4c8f-8865-1a4d3e1a8fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042150060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3042150060
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.839845699
Short name T530
Test name
Test status
Simulation time 1234654108 ps
CPU time 10 seconds
Started Jun 28 06:47:32 PM PDT 24
Finished Jun 28 06:49:42 PM PDT 24
Peak memory 219076 kb
Host smart-b0878030-6dbc-42b4-890b-9e2687cf4c2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839845699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.839845699
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.360378316
Short name T332
Test name
Test status
Simulation time 242991315 ps
CPU time 8.27 seconds
Started Jun 28 06:47:32 PM PDT 24
Finished Jun 28 06:49:39 PM PDT 24
Peak memory 218448 kb
Host smart-3d275b6a-d15e-4d05-9fab-3ab3410370f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360378316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_di
gest.360378316
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.2083430492
Short name T319
Test name
Test status
Simulation time 5016356922 ps
CPU time 10.29 seconds
Started Jun 28 06:47:32 PM PDT 24
Finished Jun 28 06:49:42 PM PDT 24
Peak memory 226308 kb
Host smart-e3cc62d1-57c2-4a07-a0bc-008fd9c985e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083430492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
2083430492
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.3052480180
Short name T545
Test name
Test status
Simulation time 357960243 ps
CPU time 9.43 seconds
Started Jun 28 06:47:33 PM PDT 24
Finished Jun 28 06:50:16 PM PDT 24
Peak memory 218572 kb
Host smart-5c4d368d-e38b-475c-bbaf-11f5c32fd877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052480180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3052480180
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.4093453892
Short name T820
Test name
Test status
Simulation time 134839306 ps
CPU time 2.6 seconds
Started Jun 28 06:47:15 PM PDT 24
Finished Jun 28 06:49:23 PM PDT 24
Peak memory 214608 kb
Host smart-09bf9887-d291-4e2a-8721-974b141464b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093453892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.4093453892
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.2212727024
Short name T553
Test name
Test status
Simulation time 469536341 ps
CPU time 21.48 seconds
Started Jun 28 06:47:22 PM PDT 24
Finished Jun 28 06:50:00 PM PDT 24
Peak memory 251140 kb
Host smart-136edb2e-560f-41d5-be30-bb6ef0a659f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212727024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.2212727024
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.411312045
Short name T781
Test name
Test status
Simulation time 147562837 ps
CPU time 6.25 seconds
Started Jun 28 06:47:22 PM PDT 24
Finished Jun 28 06:49:32 PM PDT 24
Peak memory 250848 kb
Host smart-fbbe7b83-f973-440a-b6a7-642038e722a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411312045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.411312045
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.1707261921
Short name T560
Test name
Test status
Simulation time 21534709458 ps
CPU time 206.24 seconds
Started Jun 28 06:48:47 PM PDT 24
Finished Jun 28 06:53:59 PM PDT 24
Peak memory 283948 kb
Host smart-38018a61-9f38-4c30-b407-c2561939bb52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707261921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.1707261921
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1048258686
Short name T188
Test name
Test status
Simulation time 39422853 ps
CPU time 0.82 seconds
Started Jun 28 06:47:17 PM PDT 24
Finished Jun 28 06:49:32 PM PDT 24
Peak memory 212088 kb
Host smart-85b1307e-41d0-4bf0-aabd-583c75ca8b8b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048258686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.1048258686
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3028092575
Short name T314
Test name
Test status
Simulation time 68883991 ps
CPU time 0.95 seconds
Started Jun 28 06:47:42 PM PDT 24
Finished Jun 28 06:50:12 PM PDT 24
Peak memory 209332 kb
Host smart-05ab63a0-c75a-4216-b933-6a25a52a57e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028092575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3028092575
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.1071351049
Short name T317
Test name
Test status
Simulation time 961653767 ps
CPU time 9.03 seconds
Started Jun 28 06:47:43 PM PDT 24
Finished Jun 28 06:49:48 PM PDT 24
Peak memory 218372 kb
Host smart-a6656a23-0efd-4f4b-8114-f1655eef972b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071351049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.1071351049
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1410217506
Short name T522
Test name
Test status
Simulation time 247971713 ps
CPU time 1.54 seconds
Started Jun 28 06:48:04 PM PDT 24
Finished Jun 28 06:49:59 PM PDT 24
Peak memory 217308 kb
Host smart-7fc09e3e-48d0-46f2-a26a-d0d12dbfe466
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410217506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1410217506
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.1579424109
Short name T327
Test name
Test status
Simulation time 307755855 ps
CPU time 2.96 seconds
Started Jun 28 06:48:47 PM PDT 24
Finished Jun 28 06:50:36 PM PDT 24
Peak memory 218424 kb
Host smart-c2a18c3e-41f5-4f3f-9445-67d9483c7b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579424109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1579424109
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.4259820924
Short name T174
Test name
Test status
Simulation time 551523198 ps
CPU time 22.92 seconds
Started Jun 28 06:48:04 PM PDT 24
Finished Jun 28 06:50:44 PM PDT 24
Peak memory 226256 kb
Host smart-f66bf8a9-524c-428a-a661-ff8dcf51c1ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259820924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.4259820924
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.2485706417
Short name T572
Test name
Test status
Simulation time 322407868 ps
CPU time 8.45 seconds
Started Jun 28 06:47:43 PM PDT 24
Finished Jun 28 06:49:40 PM PDT 24
Peak memory 218464 kb
Host smart-b2b40bfc-4f79-41c1-95e1-4f54319e9b2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485706417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.2485706417
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2258871132
Short name T651
Test name
Test status
Simulation time 760862000 ps
CPU time 12.37 seconds
Started Jun 28 06:47:44 PM PDT 24
Finished Jun 28 06:49:51 PM PDT 24
Peak memory 218456 kb
Host smart-41efbae5-19a8-4518-b582-f446751498a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258871132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2258871132
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.3251534327
Short name T477
Test name
Test status
Simulation time 364823296 ps
CPU time 12.82 seconds
Started Jun 28 06:47:44 PM PDT 24
Finished Jun 28 06:50:02 PM PDT 24
Peak memory 218508 kb
Host smart-16afbcbf-f462-4ea8-9e8c-2a75263cfab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251534327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.3251534327
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2128368409
Short name T177
Test name
Test status
Simulation time 168889430 ps
CPU time 3.18 seconds
Started Jun 28 06:48:37 PM PDT 24
Finished Jun 28 06:50:29 PM PDT 24
Peak memory 214964 kb
Host smart-313f78eb-b01d-424f-a6ba-33f88aa27721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128368409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2128368409
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3408847908
Short name T529
Test name
Test status
Simulation time 350951079 ps
CPU time 28.56 seconds
Started Jun 28 06:48:39 PM PDT 24
Finished Jun 28 06:50:55 PM PDT 24
Peak memory 251160 kb
Host smart-342353d1-8ce2-47d6-99db-225278dc27e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408847908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3408847908
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.2430290039
Short name T191
Test name
Test status
Simulation time 195073910 ps
CPU time 8.04 seconds
Started Jun 28 06:47:32 PM PDT 24
Finished Jun 28 06:49:40 PM PDT 24
Peak memory 251056 kb
Host smart-91659680-b733-4d4b-85d1-798d837db403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430290039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2430290039
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.4166714816
Short name T70
Test name
Test status
Simulation time 37488240568 ps
CPU time 121.05 seconds
Started Jun 28 06:49:09 PM PDT 24
Finished Jun 28 06:52:53 PM PDT 24
Peak memory 251188 kb
Host smart-7d65a837-5ec7-4c32-be78-80667cb026c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166714816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.4166714816
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.964544603
Short name T767
Test name
Test status
Simulation time 134168683003 ps
CPU time 2211.69 seconds
Started Jun 28 06:47:44 PM PDT 24
Finished Jun 28 07:26:32 PM PDT 24
Peak memory 944456 kb
Host smart-90fb8936-d6fb-4568-945b-d4bbc5b9f256
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=964544603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.964544603
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2096641291
Short name T733
Test name
Test status
Simulation time 45891830 ps
CPU time 1 seconds
Started Jun 28 06:47:29 PM PDT 24
Finished Jun 28 06:49:32 PM PDT 24
Peak memory 212104 kb
Host smart-fce0fd8b-48db-42d2-8ac0-009b4f1065e0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096641291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.2096641291
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.2856098166
Short name T547
Test name
Test status
Simulation time 30689831 ps
CPU time 1.08 seconds
Started Jun 28 06:48:20 PM PDT 24
Finished Jun 28 06:50:22 PM PDT 24
Peak memory 209172 kb
Host smart-66280c34-a4fb-4e0d-b308-65e406ee6065
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856098166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.2856098166
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1129925374
Short name T751
Test name
Test status
Simulation time 873849777 ps
CPU time 18.58 seconds
Started Jun 28 06:48:02 PM PDT 24
Finished Jun 28 06:50:45 PM PDT 24
Peak memory 218460 kb
Host smart-cb5361aa-0b6b-4915-aed2-6a1efe3db35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129925374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1129925374
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.3808235592
Short name T785
Test name
Test status
Simulation time 425830731 ps
CPU time 5.17 seconds
Started Jun 28 06:48:03 PM PDT 24
Finished Jun 28 06:50:08 PM PDT 24
Peak memory 217420 kb
Host smart-b393ff57-202e-42c4-a62d-4da729e14b6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808235592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.3808235592
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2482176588
Short name T322
Test name
Test status
Simulation time 204846829 ps
CPU time 4.52 seconds
Started Jun 28 06:48:05 PM PDT 24
Finished Jun 28 06:50:07 PM PDT 24
Peak memory 218428 kb
Host smart-7fdf1b0f-aff3-4f2d-abf8-5d9cd33a7eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482176588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2482176588
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.1135959020
Short name T403
Test name
Test status
Simulation time 469572191 ps
CPU time 14.93 seconds
Started Jun 28 06:48:02 PM PDT 24
Finished Jun 28 06:50:18 PM PDT 24
Peak memory 219164 kb
Host smart-e22f269e-5610-4782-a415-2c15d2ed95f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135959020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.1135959020
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.595020350
Short name T523
Test name
Test status
Simulation time 1180558234 ps
CPU time 10.22 seconds
Started Jun 28 06:48:21 PM PDT 24
Finished Jun 28 06:50:24 PM PDT 24
Peak memory 218448 kb
Host smart-0cddbfe2-a6c2-46c3-854c-6292c62e7548
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595020350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_di
gest.595020350
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.602031065
Short name T853
Test name
Test status
Simulation time 196818976 ps
CPU time 7.78 seconds
Started Jun 28 06:48:22 PM PDT 24
Finished Jun 28 06:50:29 PM PDT 24
Peak memory 218412 kb
Host smart-f9541147-7ccd-4c0a-abcf-e938de81b76c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602031065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.602031065
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.1948214068
Short name T542
Test name
Test status
Simulation time 718818237 ps
CPU time 5.7 seconds
Started Jun 28 06:48:02 PM PDT 24
Finished Jun 28 06:50:09 PM PDT 24
Peak memory 218584 kb
Host smart-437ec2f5-5b8e-4592-a8b1-adf174f8ea41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948214068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.1948214068
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.1709380925
Short name T350
Test name
Test status
Simulation time 35869193 ps
CPU time 2.58 seconds
Started Jun 28 06:47:52 PM PDT 24
Finished Jun 28 06:49:41 PM PDT 24
Peak memory 214772 kb
Host smart-39cb45bf-3588-420c-880e-7679af9c21f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709380925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.1709380925
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.2278812994
Short name T571
Test name
Test status
Simulation time 211441734 ps
CPU time 26.08 seconds
Started Jun 28 06:47:43 PM PDT 24
Finished Jun 28 06:49:58 PM PDT 24
Peak memory 251148 kb
Host smart-6daa0686-0f0f-4054-8f52-d4c202b30143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278812994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2278812994
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1005540218
Short name T595
Test name
Test status
Simulation time 820194968 ps
CPU time 6.81 seconds
Started Jun 28 06:49:10 PM PDT 24
Finished Jun 28 06:50:59 PM PDT 24
Peak memory 250564 kb
Host smart-61bc1f3f-a9fb-472e-bd37-e9b0517753a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005540218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1005540218
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.4081139360
Short name T59
Test name
Test status
Simulation time 9668491824 ps
CPU time 282.79 seconds
Started Jun 28 06:48:19 PM PDT 24
Finished Jun 28 06:55:03 PM PDT 24
Peak memory 226308 kb
Host smart-b7273c68-4ded-42e6-b396-a7f0e4ccd366
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081139360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.4081139360
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1342578475
Short name T243
Test name
Test status
Simulation time 56821856 ps
CPU time 0.92 seconds
Started Jun 28 06:49:04 PM PDT 24
Finished Jun 28 06:50:47 PM PDT 24
Peak memory 212108 kb
Host smart-7f5880df-433d-400d-a7fe-771c40659ce9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342578475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1342578475
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.2152611939
Short name T808
Test name
Test status
Simulation time 60358629 ps
CPU time 0.97 seconds
Started Jun 28 06:48:29 PM PDT 24
Finished Jun 28 06:50:21 PM PDT 24
Peak memory 209232 kb
Host smart-cc41a389-186f-46ef-b303-e161a660475a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152611939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.2152611939
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.1474413212
Short name T40
Test name
Test status
Simulation time 278787282 ps
CPU time 14.44 seconds
Started Jun 28 06:48:18 PM PDT 24
Finished Jun 28 06:50:27 PM PDT 24
Peak memory 218520 kb
Host smart-4f114a73-fc79-4571-b6db-65ccbb422995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474413212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1474413212
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.601384768
Short name T430
Test name
Test status
Simulation time 562295695 ps
CPU time 1.94 seconds
Started Jun 28 06:48:29 PM PDT 24
Finished Jun 28 06:50:22 PM PDT 24
Peak memory 217296 kb
Host smart-c8cc55d4-98ae-44d6-b34c-e1c93eb94321
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601384768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.601384768
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.964379942
Short name T501
Test name
Test status
Simulation time 38473007 ps
CPU time 2.73 seconds
Started Jun 28 06:48:19 PM PDT 24
Finished Jun 28 06:50:23 PM PDT 24
Peak memory 222656 kb
Host smart-a92147e2-02e6-49b9-88b0-5d4698fb603c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964379942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.964379942
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.2015859701
Short name T631
Test name
Test status
Simulation time 1174141755 ps
CPU time 14.16 seconds
Started Jun 28 06:48:29 PM PDT 24
Finished Jun 28 06:50:34 PM PDT 24
Peak memory 226232 kb
Host smart-88cfb0f4-3eb1-41e5-ac16-d755ca8407ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015859701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.2015859701
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3989417187
Short name T349
Test name
Test status
Simulation time 10041818519 ps
CPU time 11.76 seconds
Started Jun 28 06:48:35 PM PDT 24
Finished Jun 28 06:50:37 PM PDT 24
Peak memory 218496 kb
Host smart-dda34b30-12c3-4a3c-8673-a77666009bdd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989417187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.3989417187
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.431266050
Short name T394
Test name
Test status
Simulation time 338641250 ps
CPU time 8.07 seconds
Started Jun 28 06:48:29 PM PDT 24
Finished Jun 28 06:50:28 PM PDT 24
Peak memory 226248 kb
Host smart-a8d40165-3aaf-40ee-9f51-c8659152f06c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431266050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.431266050
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2332921564
Short name T354
Test name
Test status
Simulation time 311826973 ps
CPU time 10.5 seconds
Started Jun 28 06:48:19 PM PDT 24
Finished Jun 28 06:50:24 PM PDT 24
Peak memory 218504 kb
Host smart-a341d0fc-bc9d-4a07-b019-a16586ac3d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332921564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2332921564
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.1483907042
Short name T602
Test name
Test status
Simulation time 105975864 ps
CPU time 3.62 seconds
Started Jun 28 06:48:21 PM PDT 24
Finished Jun 28 06:50:25 PM PDT 24
Peak memory 217936 kb
Host smart-067bcde9-079b-466e-97ae-ba1e15b8b15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483907042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.1483907042
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.394138155
Short name T88
Test name
Test status
Simulation time 552619257 ps
CPU time 28.28 seconds
Started Jun 28 06:48:19 PM PDT 24
Finished Jun 28 06:50:41 PM PDT 24
Peak memory 251104 kb
Host smart-dbca05ae-af94-4387-9f15-e5390d2a0bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394138155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.394138155
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2491388353
Short name T805
Test name
Test status
Simulation time 48292307 ps
CPU time 2.4 seconds
Started Jun 28 06:48:20 PM PDT 24
Finished Jun 28 06:50:16 PM PDT 24
Peak memory 218420 kb
Host smart-ae28bf6f-eafe-4e3b-be08-3bc837ecc406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491388353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2491388353
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.2517242420
Short name T818
Test name
Test status
Simulation time 13014066964 ps
CPU time 75.1 seconds
Started Jun 28 06:48:33 PM PDT 24
Finished Jun 28 06:51:36 PM PDT 24
Peak memory 277524 kb
Host smart-8e94ee98-e72b-486a-9e98-7b3642a089eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517242420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.2517242420
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.2558380995
Short name T743
Test name
Test status
Simulation time 21905985624 ps
CPU time 766.41 seconds
Started Jun 28 06:48:29 PM PDT 24
Finished Jun 28 07:03:07 PM PDT 24
Peak memory 316824 kb
Host smart-f98213eb-e08a-4c45-83e9-488e0a440a79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2558380995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.2558380995
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1576356310
Short name T106
Test name
Test status
Simulation time 16287067 ps
CPU time 0.97 seconds
Started Jun 28 06:48:20 PM PDT 24
Finished Jun 28 06:50:22 PM PDT 24
Peak memory 212152 kb
Host smart-2f81ef1b-df2a-4091-a92f-2b19c3d7ac33
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576356310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.1576356310
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.2556720985
Short name T581
Test name
Test status
Simulation time 15608249 ps
CPU time 1.12 seconds
Started Jun 28 06:48:41 PM PDT 24
Finished Jun 28 06:50:28 PM PDT 24
Peak memory 209120 kb
Host smart-8db7b259-0884-4a47-93bd-13ce9843a0c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556720985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.2556720985
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.2519486252
Short name T666
Test name
Test status
Simulation time 442352056 ps
CPU time 12.83 seconds
Started Jun 28 06:48:30 PM PDT 24
Finished Jun 28 06:50:33 PM PDT 24
Peak memory 218460 kb
Host smart-7e372e9d-d5bf-4ef1-9a9c-580221a8b386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519486252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2519486252
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.662710565
Short name T608
Test name
Test status
Simulation time 874959977 ps
CPU time 9.76 seconds
Started Jun 28 06:48:31 PM PDT 24
Finished Jun 28 06:50:30 PM PDT 24
Peak memory 217600 kb
Host smart-199525e5-e54e-4298-92bb-1bf6ade6a2f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662710565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.662710565
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.3417059220
Short name T298
Test name
Test status
Simulation time 177163701 ps
CPU time 6.19 seconds
Started Jun 28 06:48:31 PM PDT 24
Finished Jun 28 06:50:27 PM PDT 24
Peak memory 222980 kb
Host smart-093a1465-4d8f-4837-94a4-d4614974a1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417059220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3417059220
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3249684330
Short name T587
Test name
Test status
Simulation time 942862942 ps
CPU time 13.22 seconds
Started Jun 28 06:48:29 PM PDT 24
Finished Jun 28 06:50:33 PM PDT 24
Peak memory 226268 kb
Host smart-52c9f876-a0e7-4418-859b-197774c2fc1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249684330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3249684330
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3779047097
Short name T636
Test name
Test status
Simulation time 1007083107 ps
CPU time 12.27 seconds
Started Jun 28 06:48:30 PM PDT 24
Finished Jun 28 06:50:33 PM PDT 24
Peak memory 218532 kb
Host smart-b8df1e51-257d-44f6-957f-74ae42751c11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779047097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3779047097
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2048335086
Short name T55
Test name
Test status
Simulation time 918710774 ps
CPU time 6.37 seconds
Started Jun 28 06:48:29 PM PDT 24
Finished Jun 28 06:50:27 PM PDT 24
Peak memory 218436 kb
Host smart-7870453c-a53c-402d-993c-7dad7666d25b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048335086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2048335086
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.1148603054
Short name T691
Test name
Test status
Simulation time 2293253477 ps
CPU time 7.8 seconds
Started Jun 28 06:48:31 PM PDT 24
Finished Jun 28 06:50:28 PM PDT 24
Peak memory 218568 kb
Host smart-3a241630-e200-45ef-ac61-1d88f22c82e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148603054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.1148603054
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.2447561789
Short name T232
Test name
Test status
Simulation time 128556153 ps
CPU time 3.27 seconds
Started Jun 28 06:48:31 PM PDT 24
Finished Jun 28 06:50:24 PM PDT 24
Peak memory 217928 kb
Host smart-8f8979fb-4185-4790-89ad-6320479a884d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447561789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.2447561789
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.246947475
Short name T371
Test name
Test status
Simulation time 1254108083 ps
CPU time 26.29 seconds
Started Jun 28 06:48:30 PM PDT 24
Finished Jun 28 06:50:47 PM PDT 24
Peak memory 251132 kb
Host smart-8c55d2c4-c348-44de-b1d3-74f33f92ef01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246947475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.246947475
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.3982555213
Short name T778
Test name
Test status
Simulation time 112634782 ps
CPU time 2.79 seconds
Started Jun 28 06:48:30 PM PDT 24
Finished Jun 28 06:50:23 PM PDT 24
Peak memory 222356 kb
Host smart-6ef6a1ef-b2e9-4fdf-be3d-2d320d59ad27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982555213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3982555213
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1693827104
Short name T593
Test name
Test status
Simulation time 2877691310 ps
CPU time 93.29 seconds
Started Jun 28 06:48:42 PM PDT 24
Finished Jun 28 06:52:18 PM PDT 24
Peak memory 273548 kb
Host smart-af98ca59-83a0-4d0c-84f8-0c550cbc73d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693827104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1693827104
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3135497086
Short name T353
Test name
Test status
Simulation time 25804534 ps
CPU time 1.09 seconds
Started Jun 28 06:48:33 PM PDT 24
Finished Jun 28 06:50:22 PM PDT 24
Peak memory 213176 kb
Host smart-cad5cdc7-c591-450b-80ae-abe5796ea5de
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135497086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.3135497086
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.474028639
Short name T461
Test name
Test status
Simulation time 93481810 ps
CPU time 1.4 seconds
Started Jun 28 06:37:54 PM PDT 24
Finished Jun 28 06:38:03 PM PDT 24
Peak memory 209240 kb
Host smart-8ba133d6-74a1-4428-9d82-8c718d4ac8c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474028639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.474028639
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3221041131
Short name T484
Test name
Test status
Simulation time 14041568 ps
CPU time 0.96 seconds
Started Jun 28 06:37:26 PM PDT 24
Finished Jun 28 06:37:30 PM PDT 24
Peak memory 209196 kb
Host smart-ecfdc29d-f9d6-418d-b009-5c85ce8de4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221041131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3221041131
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1763858687
Short name T345
Test name
Test status
Simulation time 367944888 ps
CPU time 16.23 seconds
Started Jun 28 06:37:31 PM PDT 24
Finished Jun 28 06:37:56 PM PDT 24
Peak memory 218460 kb
Host smart-b6b32e98-58b6-4ff5-9c12-0a3fb1116675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763858687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1763858687
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.4273633299
Short name T65
Test name
Test status
Simulation time 62483964 ps
CPU time 1.57 seconds
Started Jun 28 06:37:36 PM PDT 24
Finished Jun 28 06:37:44 PM PDT 24
Peak memory 217252 kb
Host smart-7ff2043e-45dc-4854-9d16-b01aac0dbd84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273633299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.4273633299
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1869096100
Short name T635
Test name
Test status
Simulation time 9048115575 ps
CPU time 50.53 seconds
Started Jun 28 06:37:36 PM PDT 24
Finished Jun 28 06:38:33 PM PDT 24
Peak memory 220176 kb
Host smart-a1482bfa-d7af-434b-b80c-47869261b2bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869096100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1869096100
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.3567240092
Short name T114
Test name
Test status
Simulation time 4013488538 ps
CPU time 9.03 seconds
Started Jun 28 06:37:36 PM PDT 24
Finished Jun 28 06:37:51 PM PDT 24
Peak memory 218056 kb
Host smart-b85769c2-21a0-40d3-af5d-579240cfcfe2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567240092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.3
567240092
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.4086171710
Short name T567
Test name
Test status
Simulation time 633205169 ps
CPU time 18.72 seconds
Started Jun 28 06:37:35 PM PDT 24
Finished Jun 28 06:38:01 PM PDT 24
Peak memory 218420 kb
Host smart-2cd68178-b9cf-4d0b-b1a5-b567ff81f7c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086171710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.4086171710
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1968431254
Short name T281
Test name
Test status
Simulation time 3328493202 ps
CPU time 13.97 seconds
Started Jun 28 06:37:36 PM PDT 24
Finished Jun 28 06:37:56 PM PDT 24
Peak memory 217908 kb
Host smart-1f94c0f7-7ad1-42f9-ae2e-50413de4584d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968431254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1968431254
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.999605479
Short name T375
Test name
Test status
Simulation time 195380319 ps
CPU time 1.69 seconds
Started Jun 28 06:37:25 PM PDT 24
Finished Jun 28 06:37:28 PM PDT 24
Peak memory 217932 kb
Host smart-a48883da-9778-4ab1-b75c-5a31193d83d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999605479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.999605479
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2277739822
Short name T700
Test name
Test status
Simulation time 2680407588 ps
CPU time 56.39 seconds
Started Jun 28 06:37:35 PM PDT 24
Finished Jun 28 06:38:38 PM PDT 24
Peak memory 267548 kb
Host smart-cfb2058b-2c9b-4700-a5d1-a7972fd127dc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277739822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2277739822
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.4090181564
Short name T527
Test name
Test status
Simulation time 491585799 ps
CPU time 21.74 seconds
Started Jun 28 06:37:35 PM PDT 24
Finished Jun 28 06:38:03 PM PDT 24
Peak memory 251044 kb
Host smart-b12552e0-60cb-4fff-8dd4-6cc224ae8fb4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090181564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.4090181564
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.1203632958
Short name T775
Test name
Test status
Simulation time 39397160 ps
CPU time 2.04 seconds
Started Jun 28 06:37:24 PM PDT 24
Finished Jun 28 06:37:27 PM PDT 24
Peak memory 218432 kb
Host smart-4e517d3c-833b-4ebe-b7ae-26d2bb1bddca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203632958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.1203632958
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.4257549784
Short name T81
Test name
Test status
Simulation time 778219418 ps
CPU time 7.74 seconds
Started Jun 28 06:37:24 PM PDT 24
Finished Jun 28 06:37:33 PM PDT 24
Peak memory 217952 kb
Host smart-a1cb4c3c-29aa-4ee9-a85e-d48048c0d6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257549784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.4257549784
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3306253797
Short name T49
Test name
Test status
Simulation time 434590101 ps
CPU time 33.62 seconds
Started Jun 28 06:37:53 PM PDT 24
Finished Jun 28 06:38:31 PM PDT 24
Peak memory 269860 kb
Host smart-c8d5fc46-1543-4b16-befd-6258fbaabc87
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306253797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3306253797
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.2894539994
Short name T559
Test name
Test status
Simulation time 3678692582 ps
CPU time 12.71 seconds
Started Jun 28 06:37:36 PM PDT 24
Finished Jun 28 06:37:55 PM PDT 24
Peak memory 226304 kb
Host smart-1ea34be8-1d64-434e-88bb-060f466d0406
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894539994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.2894539994
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2554600457
Short name T574
Test name
Test status
Simulation time 967669390 ps
CPU time 9.62 seconds
Started Jun 28 06:37:36 PM PDT 24
Finished Jun 28 06:37:52 PM PDT 24
Peak memory 218444 kb
Host smart-555a470c-1dc9-4c0d-a6f6-7cf931396aa5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554600457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.2554600457
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.675086497
Short name T187
Test name
Test status
Simulation time 882943640 ps
CPU time 9.33 seconds
Started Jun 28 06:37:36 PM PDT 24
Finished Jun 28 06:37:52 PM PDT 24
Peak memory 218356 kb
Host smart-2c608fa7-9d7a-4e0a-be6a-2098e27cd22f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675086497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.675086497
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.849383717
Short name T479
Test name
Test status
Simulation time 942344675 ps
CPU time 8.04 seconds
Started Jun 28 06:37:28 PM PDT 24
Finished Jun 28 06:37:46 PM PDT 24
Peak memory 218472 kb
Host smart-9c3d24c2-eb43-4718-b1cd-35ba1042cf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849383717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.849383717
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.275790368
Short name T683
Test name
Test status
Simulation time 52800072 ps
CPU time 3.09 seconds
Started Jun 28 06:37:29 PM PDT 24
Finished Jun 28 06:37:42 PM PDT 24
Peak memory 215004 kb
Host smart-fa48d2c2-9084-4df7-8270-39dd2224fd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275790368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.275790368
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.3084835720
Short name T645
Test name
Test status
Simulation time 1702835100 ps
CPU time 29.08 seconds
Started Jun 28 06:37:24 PM PDT 24
Finished Jun 28 06:37:54 PM PDT 24
Peak memory 251144 kb
Host smart-2c723743-e2b2-4110-b654-f5edfcea7ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084835720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3084835720
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.1910094492
Short name T330
Test name
Test status
Simulation time 67429585 ps
CPU time 6.94 seconds
Started Jun 28 06:37:25 PM PDT 24
Finished Jun 28 06:37:33 PM PDT 24
Peak memory 250980 kb
Host smart-53ca4003-45b6-4bd3-98e1-b1de27548c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910094492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.1910094492
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.553536263
Short name T283
Test name
Test status
Simulation time 13940715753 ps
CPU time 361.05 seconds
Started Jun 28 06:37:36 PM PDT 24
Finished Jun 28 06:43:44 PM PDT 24
Peak memory 267472 kb
Host smart-69f29445-15e0-4e06-8683-1be880e9d3e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553536263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.553536263
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.3020804173
Short name T845
Test name
Test status
Simulation time 8223260960 ps
CPU time 176.87 seconds
Started Jun 28 06:37:54 PM PDT 24
Finished Jun 28 06:40:59 PM PDT 24
Peak memory 276656 kb
Host smart-a426ab98-fdaf-4603-bd86-7c0607967f6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3020804173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.3020804173
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1030645515
Short name T307
Test name
Test status
Simulation time 33782444 ps
CPU time 0.84 seconds
Started Jun 28 06:37:26 PM PDT 24
Finished Jun 28 06:37:28 PM PDT 24
Peak memory 212060 kb
Host smart-ef5d271e-01b3-4c1d-9886-3dfcdc2a2fcd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030645515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.1030645515
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.4210106351
Short name T780
Test name
Test status
Simulation time 112558715 ps
CPU time 1.25 seconds
Started Jun 28 06:48:44 PM PDT 24
Finished Jun 28 06:50:40 PM PDT 24
Peak memory 209160 kb
Host smart-7f81483d-51e4-4e2c-9f5f-f68b78af2ac6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210106351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.4210106351
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2793337277
Short name T677
Test name
Test status
Simulation time 260651876 ps
CPU time 10.4 seconds
Started Jun 28 06:48:41 PM PDT 24
Finished Jun 28 06:51:03 PM PDT 24
Peak memory 218444 kb
Host smart-fe401656-c270-4761-b773-c8c75317195a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793337277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2793337277
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.2976191400
Short name T615
Test name
Test status
Simulation time 3686349535 ps
CPU time 10.03 seconds
Started Jun 28 06:48:44 PM PDT 24
Finished Jun 28 06:51:02 PM PDT 24
Peak memory 217912 kb
Host smart-234947d6-c5be-4c38-8afe-5c3dd7a75538
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976191400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.2976191400
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.1390627792
Short name T690
Test name
Test status
Simulation time 124749102 ps
CPU time 2.49 seconds
Started Jun 28 06:48:42 PM PDT 24
Finished Jun 28 06:50:54 PM PDT 24
Peak memory 218424 kb
Host smart-cca53129-2027-4a77-b734-8f1dbf0cc270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390627792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1390627792
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.2626151643
Short name T95
Test name
Test status
Simulation time 2319754378 ps
CPU time 10.46 seconds
Started Jun 28 06:48:40 PM PDT 24
Finished Jun 28 06:50:37 PM PDT 24
Peak memory 226312 kb
Host smart-90442933-6473-41f3-be41-c04b239eed93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626151643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.2626151643
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.4229947470
Short name T19
Test name
Test status
Simulation time 594550367 ps
CPU time 12.62 seconds
Started Jun 28 06:48:43 PM PDT 24
Finished Jun 28 06:51:05 PM PDT 24
Peak memory 218380 kb
Host smart-9141886f-290f-4211-abda-f39494122f19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229947470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.4229947470
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.574323276
Short name T508
Test name
Test status
Simulation time 1653938279 ps
CPU time 14.35 seconds
Started Jun 28 06:48:42 PM PDT 24
Finished Jun 28 06:51:13 PM PDT 24
Peak memory 226240 kb
Host smart-a0426240-221c-4c78-a8ec-08a8604618a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574323276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.574323276
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.3700663641
Short name T221
Test name
Test status
Simulation time 1118186016 ps
CPU time 7.89 seconds
Started Jun 28 06:48:49 PM PDT 24
Finished Jun 28 06:50:47 PM PDT 24
Peak memory 218408 kb
Host smart-1861691a-02ad-42ee-af43-eb8544438684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700663641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3700663641
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.2931524510
Short name T74
Test name
Test status
Simulation time 58481228 ps
CPU time 2.44 seconds
Started Jun 28 06:48:45 PM PDT 24
Finished Jun 28 06:50:43 PM PDT 24
Peak memory 224192 kb
Host smart-b109d32f-bcdf-4ce1-89c5-9ff66945a151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931524510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.2931524510
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3871818460
Short name T565
Test name
Test status
Simulation time 186376758 ps
CPU time 21.15 seconds
Started Jun 28 06:48:42 PM PDT 24
Finished Jun 28 06:51:13 PM PDT 24
Peak memory 251072 kb
Host smart-c5b0744a-4455-4b91-a219-9fb79985fcfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871818460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3871818460
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2850802322
Short name T540
Test name
Test status
Simulation time 286138619 ps
CPU time 8.09 seconds
Started Jun 28 06:48:45 PM PDT 24
Finished Jun 28 06:50:48 PM PDT 24
Peak memory 251080 kb
Host smart-9a8bf1d8-5164-4b2b-b9d2-57093b4da401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850802322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2850802322
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.405301464
Short name T506
Test name
Test status
Simulation time 10886975469 ps
CPU time 69 seconds
Started Jun 28 06:48:42 PM PDT 24
Finished Jun 28 06:51:35 PM PDT 24
Peak memory 267880 kb
Host smart-52f74345-f2ba-402f-bd0b-4b1623f25d7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405301464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.405301464
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1730814326
Short name T603
Test name
Test status
Simulation time 29200831 ps
CPU time 0.94 seconds
Started Jun 28 06:48:42 PM PDT 24
Finished Jun 28 06:50:27 PM PDT 24
Peak memory 212040 kb
Host smart-ad713eaa-a7a0-4fda-9cbc-0c66881ebc0a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730814326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.1730814326
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.1736090544
Short name T374
Test name
Test status
Simulation time 20655819 ps
CPU time 1 seconds
Started Jun 28 06:49:06 PM PDT 24
Finished Jun 28 06:50:53 PM PDT 24
Peak memory 209256 kb
Host smart-c32b0e95-088c-4a32-a60f-dba0c382dd73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736090544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.1736090544
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2155048780
Short name T346
Test name
Test status
Simulation time 316984986 ps
CPU time 14.8 seconds
Started Jun 28 06:48:54 PM PDT 24
Finished Jun 28 06:50:56 PM PDT 24
Peak memory 218412 kb
Host smart-f7ce8ca0-8aa5-4147-b3b0-b1bbb0de2fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155048780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2155048780
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.1221349212
Short name T809
Test name
Test status
Simulation time 752116972 ps
CPU time 5.04 seconds
Started Jun 28 06:48:54 PM PDT 24
Finished Jun 28 06:50:57 PM PDT 24
Peak memory 217592 kb
Host smart-20a08f0e-91c8-4ef4-8557-a7452587733c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221349212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.1221349212
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.4143879294
Short name T511
Test name
Test status
Simulation time 85684806 ps
CPU time 3.25 seconds
Started Jun 28 06:48:58 PM PDT 24
Finished Jun 28 06:50:42 PM PDT 24
Peak memory 218448 kb
Host smart-211829c4-c107-412a-bdfd-321dea00fafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143879294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.4143879294
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.2413885794
Short name T817
Test name
Test status
Simulation time 420108162 ps
CPU time 7.86 seconds
Started Jun 28 06:49:20 PM PDT 24
Finished Jun 28 06:51:07 PM PDT 24
Peak memory 218436 kb
Host smart-1a232aa9-4f60-430f-a47f-01bcb09ba0b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413885794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.2413885794
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.742983626
Short name T692
Test name
Test status
Simulation time 1093567290 ps
CPU time 11.67 seconds
Started Jun 28 06:49:21 PM PDT 24
Finished Jun 28 06:51:11 PM PDT 24
Peak memory 218464 kb
Host smart-3f4f91a2-00c7-4076-bbdd-601d474f23b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742983626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.742983626
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2789903693
Short name T520
Test name
Test status
Simulation time 562958957 ps
CPU time 18.54 seconds
Started Jun 28 06:50:16 PM PDT 24
Finished Jun 28 06:51:42 PM PDT 24
Peak memory 218452 kb
Host smart-97884b7b-7ef1-4818-bc7d-802326e24c7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789903693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
2789903693
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.2584775506
Short name T47
Test name
Test status
Simulation time 2673331669 ps
CPU time 11.36 seconds
Started Jun 28 06:48:53 PM PDT 24
Finished Jun 28 06:50:44 PM PDT 24
Peak memory 218580 kb
Host smart-f5662539-e906-47a3-82ce-21a747a9fe57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584775506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.2584775506
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1123849667
Short name T411
Test name
Test status
Simulation time 199998751 ps
CPU time 3.59 seconds
Started Jun 28 06:48:43 PM PDT 24
Finished Jun 28 06:50:55 PM PDT 24
Peak memory 217920 kb
Host smart-9b9f8922-0a22-4153-9045-7e63bc051691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123849667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1123849667
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2911415959
Short name T89
Test name
Test status
Simulation time 744515279 ps
CPU time 19.95 seconds
Started Jun 28 06:48:53 PM PDT 24
Finished Jun 28 06:50:53 PM PDT 24
Peak memory 251140 kb
Host smart-5e763822-7bdf-4ff3-86f0-e163b18e391d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911415959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2911415959
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3895069837
Short name T185
Test name
Test status
Simulation time 324512104 ps
CPU time 8.53 seconds
Started Jun 28 06:48:58 PM PDT 24
Finished Jun 28 06:51:01 PM PDT 24
Peak memory 251168 kb
Host smart-928f02ad-5226-40d8-8270-609bf6145499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895069837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3895069837
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1295367296
Short name T190
Test name
Test status
Simulation time 1583742967 ps
CPU time 63.96 seconds
Started Jun 28 06:49:08 PM PDT 24
Finished Jun 28 06:51:45 PM PDT 24
Peak memory 251120 kb
Host smart-21996979-21ed-45a2-95ae-53a99d403d15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295367296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1295367296
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.124085732
Short name T564
Test name
Test status
Simulation time 69697810 ps
CPU time 0.86 seconds
Started Jun 28 06:48:49 PM PDT 24
Finished Jun 28 06:50:53 PM PDT 24
Peak memory 212060 kb
Host smart-75822d23-cbfd-444c-87f1-aa2778f55ab4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124085732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ct
rl_volatile_unlock_smoke.124085732
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.2227555407
Short name T301
Test name
Test status
Simulation time 26445603 ps
CPU time 1.21 seconds
Started Jun 28 06:49:44 PM PDT 24
Finished Jun 28 06:51:10 PM PDT 24
Peak memory 209280 kb
Host smart-7f0d65e6-d37e-468d-b43a-4c41a3134b8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227555407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.2227555407
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.1626895680
Short name T431
Test name
Test status
Simulation time 2979333921 ps
CPU time 25.36 seconds
Started Jun 28 06:49:30 PM PDT 24
Finished Jun 28 06:51:25 PM PDT 24
Peak memory 226304 kb
Host smart-03b8a5ae-4c4e-44f9-9ec8-5414014adb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626895680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1626895680
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.572175794
Short name T31
Test name
Test status
Simulation time 865222678 ps
CPU time 5.19 seconds
Started Jun 28 06:49:30 PM PDT 24
Finished Jun 28 06:51:05 PM PDT 24
Peak memory 217280 kb
Host smart-48f2eec0-a585-4c8b-8f5c-adbdcc36fc7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572175794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.572175794
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2983682019
Short name T225
Test name
Test status
Simulation time 74325373 ps
CPU time 1.59 seconds
Started Jun 28 06:49:24 PM PDT 24
Finished Jun 28 06:51:00 PM PDT 24
Peak memory 218420 kb
Host smart-78acb038-f573-44b6-8f08-8994ec3e7a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983682019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2983682019
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.3249922833
Short name T664
Test name
Test status
Simulation time 928788273 ps
CPU time 10.6 seconds
Started Jun 28 06:49:31 PM PDT 24
Finished Jun 28 06:51:14 PM PDT 24
Peak memory 226256 kb
Host smart-3cdd2da1-700f-4e8f-8bfa-c479e45896cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249922833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.3249922833
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1819681483
Short name T17
Test name
Test status
Simulation time 195625078 ps
CPU time 7.61 seconds
Started Jun 28 06:49:43 PM PDT 24
Finished Jun 28 06:51:17 PM PDT 24
Peak memory 218396 kb
Host smart-5768d4a0-9c01-467f-80b6-34b2156cc4be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819681483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.1819681483
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2867214459
Short name T103
Test name
Test status
Simulation time 614962009 ps
CPU time 7.86 seconds
Started Jun 28 06:49:44 PM PDT 24
Finished Jun 28 06:51:17 PM PDT 24
Peak memory 218432 kb
Host smart-9b8f9e2e-de05-4232-aeee-776917e354cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867214459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
2867214459
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.2475943006
Short name T708
Test name
Test status
Simulation time 1150149350 ps
CPU time 6.68 seconds
Started Jun 28 06:49:29 PM PDT 24
Finished Jun 28 06:51:11 PM PDT 24
Peak memory 218420 kb
Host smart-7cad9e93-1e75-4767-9243-874759cc874b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475943006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2475943006
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.3339282059
Short name T389
Test name
Test status
Simulation time 185832191 ps
CPU time 10.8 seconds
Started Jun 28 06:49:20 PM PDT 24
Finished Jun 28 06:51:03 PM PDT 24
Peak memory 217928 kb
Host smart-aceebb46-8806-4bc7-b15e-5b094529244b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339282059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.3339282059
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.545048211
Short name T115
Test name
Test status
Simulation time 737940251 ps
CPU time 21.94 seconds
Started Jun 28 06:49:20 PM PDT 24
Finished Jun 28 06:51:14 PM PDT 24
Peak memory 251132 kb
Host smart-a411e478-63cd-4467-b6f6-4bba7fc327d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545048211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.545048211
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.1778167857
Short name T546
Test name
Test status
Simulation time 143575329 ps
CPU time 7.29 seconds
Started Jun 28 06:49:20 PM PDT 24
Finished Jun 28 06:51:00 PM PDT 24
Peak memory 250700 kb
Host smart-9bea02e3-8e2e-47f4-9d7e-f54d2b9d3111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778167857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.1778167857
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.1141802474
Short name T504
Test name
Test status
Simulation time 32701772778 ps
CPU time 984.83 seconds
Started Jun 28 06:49:43 PM PDT 24
Finished Jun 28 07:07:34 PM PDT 24
Peak memory 224160 kb
Host smart-3ea98e0f-b561-4185-8027-5b447118f565
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141802474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.1141802474
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2762636424
Short name T360
Test name
Test status
Simulation time 20779115 ps
CPU time 1 seconds
Started Jun 28 06:49:20 PM PDT 24
Finished Jun 28 06:50:54 PM PDT 24
Peak memory 213192 kb
Host smart-a9ad1e85-3d8f-4057-9e7c-32f84f8fc8ae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762636424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2762636424
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.1993248714
Short name T831
Test name
Test status
Simulation time 363093627 ps
CPU time 16.96 seconds
Started Jun 28 06:49:43 PM PDT 24
Finished Jun 28 06:51:26 PM PDT 24
Peak memory 218440 kb
Host smart-bdca45ea-e3b2-4be5-96b7-51bffc0c8b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993248714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.1993248714
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3111338888
Short name T499
Test name
Test status
Simulation time 683056188 ps
CPU time 4.88 seconds
Started Jun 28 06:49:45 PM PDT 24
Finished Jun 28 06:51:14 PM PDT 24
Peak memory 217556 kb
Host smart-42cbb49b-e9e9-414b-8cb1-aa3c8f0223fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111338888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.3111338888
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.1147032512
Short name T414
Test name
Test status
Simulation time 243280307 ps
CPU time 3.43 seconds
Started Jun 28 06:49:45 PM PDT 24
Finished Jun 28 06:51:13 PM PDT 24
Peak memory 218436 kb
Host smart-d76a5a74-e65d-452c-bda8-d51ab1324a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147032512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1147032512
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.1790057078
Short name T459
Test name
Test status
Simulation time 508613440 ps
CPU time 8.97 seconds
Started Jun 28 06:49:43 PM PDT 24
Finished Jun 28 06:51:18 PM PDT 24
Peak memory 226232 kb
Host smart-10deeb9a-63c0-4b70-8913-70333905413c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790057078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.1790057078
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3122141850
Short name T731
Test name
Test status
Simulation time 1248864774 ps
CPU time 14.34 seconds
Started Jun 28 06:49:54 PM PDT 24
Finished Jun 28 06:51:28 PM PDT 24
Peak memory 218460 kb
Host smart-8de884fe-55ea-475b-937c-f996f42ff24c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122141850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3122141850
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2784138088
Short name T738
Test name
Test status
Simulation time 1242539590 ps
CPU time 9.23 seconds
Started Jun 28 06:49:45 PM PDT 24
Finished Jun 28 06:51:18 PM PDT 24
Peak memory 218424 kb
Host smart-d252a070-379e-4ef0-b911-184f1aad2940
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784138088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2784138088
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.1767654748
Short name T800
Test name
Test status
Simulation time 274569927 ps
CPU time 6.15 seconds
Started Jun 28 06:49:47 PM PDT 24
Finished Jun 28 06:51:15 PM PDT 24
Peak memory 218732 kb
Host smart-d95fdaf2-2b86-412a-9052-82a62cb08f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767654748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1767654748
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.1267209670
Short name T75
Test name
Test status
Simulation time 228414089 ps
CPU time 2.68 seconds
Started Jun 28 06:49:47 PM PDT 24
Finished Jun 28 06:51:12 PM PDT 24
Peak memory 215008 kb
Host smart-71e812d8-9be2-4fc6-ac65-67721e9afd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267209670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.1267209670
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.632700515
Short name T597
Test name
Test status
Simulation time 1508542438 ps
CPU time 29.07 seconds
Started Jun 28 06:49:44 PM PDT 24
Finished Jun 28 06:51:38 PM PDT 24
Peak memory 251136 kb
Host smart-f5c8ab2d-a187-4884-ad70-2c76bb21cbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632700515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.632700515
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.1797738362
Short name T365
Test name
Test status
Simulation time 239644270 ps
CPU time 7.87 seconds
Started Jun 28 06:49:48 PM PDT 24
Finished Jun 28 06:51:17 PM PDT 24
Peak memory 251372 kb
Host smart-cc035240-ae57-4d71-9682-a9b850107d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797738362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1797738362
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.4126525756
Short name T193
Test name
Test status
Simulation time 8948384401 ps
CPU time 180.51 seconds
Started Jun 28 06:49:54 PM PDT 24
Finished Jun 28 06:54:14 PM PDT 24
Peak memory 221104 kb
Host smart-6a98177c-84b3-452e-a774-c8d08b75e074
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126525756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.4126525756
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.4292444285
Short name T58
Test name
Test status
Simulation time 197950693221 ps
CPU time 758.27 seconds
Started Jun 28 06:49:56 PM PDT 24
Finished Jun 28 07:03:51 PM PDT 24
Peak memory 447872 kb
Host smart-0ddd776b-adeb-454b-ab7b-a77376fc2cc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4292444285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.4292444285
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1073612352
Short name T521
Test name
Test status
Simulation time 12666598 ps
CPU time 1.01 seconds
Started Jun 28 06:49:44 PM PDT 24
Finished Jun 28 06:51:10 PM PDT 24
Peak memory 212052 kb
Host smart-f39d163e-2b73-4ef6-877b-ad6807dff7b3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073612352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1073612352
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.3970616068
Short name T426
Test name
Test status
Simulation time 33937267 ps
CPU time 1.17 seconds
Started Jun 28 06:50:07 PM PDT 24
Finished Jun 28 06:51:22 PM PDT 24
Peak memory 209152 kb
Host smart-bbfd896b-61cc-4ce1-acf6-6dc6a671a13d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970616068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.3970616068
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2864566568
Short name T791
Test name
Test status
Simulation time 388395975 ps
CPU time 15.81 seconds
Started Jun 28 06:50:07 PM PDT 24
Finished Jun 28 06:51:36 PM PDT 24
Peak memory 218344 kb
Host smart-957e5a18-3f61-4f06-8929-c85c7b14c9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864566568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2864566568
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.2774614884
Short name T67
Test name
Test status
Simulation time 500691554 ps
CPU time 1.89 seconds
Started Jun 28 06:50:06 PM PDT 24
Finished Jun 28 06:51:22 PM PDT 24
Peak memory 217368 kb
Host smart-fe82e953-5695-495f-938d-b4dc10b0ffd0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774614884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.2774614884
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.1902243638
Short name T370
Test name
Test status
Simulation time 185574967 ps
CPU time 2.36 seconds
Started Jun 28 06:49:54 PM PDT 24
Finished Jun 28 06:51:16 PM PDT 24
Peak memory 218492 kb
Host smart-7f70f194-ceb7-475f-be15-e2fbf69070b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902243638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1902243638
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.3189299730
Short name T790
Test name
Test status
Simulation time 846557918 ps
CPU time 12.54 seconds
Started Jun 28 06:50:09 PM PDT 24
Finished Jun 28 06:51:33 PM PDT 24
Peak memory 219092 kb
Host smart-34584d8f-cb09-49f9-8b0d-8c9d42c60f24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189299730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3189299730
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2142464777
Short name T276
Test name
Test status
Simulation time 5341109500 ps
CPU time 12.47 seconds
Started Jun 28 06:50:07 PM PDT 24
Finished Jun 28 06:51:33 PM PDT 24
Peak memory 218596 kb
Host smart-2e3788ed-3856-4cb0-86bd-95986d7914d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142464777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2142464777
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1539672741
Short name T586
Test name
Test status
Simulation time 711465414 ps
CPU time 5.62 seconds
Started Jun 28 06:50:07 PM PDT 24
Finished Jun 28 06:51:26 PM PDT 24
Peak memory 218440 kb
Host smart-bbff427a-b3bf-4a39-88f0-7357e4d7e099
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539672741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1539672741
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2786264170
Short name T481
Test name
Test status
Simulation time 2081249763 ps
CPU time 10.48 seconds
Started Jun 28 06:50:07 PM PDT 24
Finished Jun 28 06:51:31 PM PDT 24
Peak memory 218596 kb
Host smart-6dfd3590-f745-488b-988a-0b8018d104b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786264170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2786264170
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.4084476828
Short name T338
Test name
Test status
Simulation time 23896251 ps
CPU time 1.99 seconds
Started Jun 28 06:49:55 PM PDT 24
Finished Jun 28 06:51:16 PM PDT 24
Peak memory 214204 kb
Host smart-bd40de7b-6e75-4074-97ab-a86409f9a6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084476828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.4084476828
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.612122071
Short name T331
Test name
Test status
Simulation time 203138262 ps
CPU time 23.44 seconds
Started Jun 28 06:49:55 PM PDT 24
Finished Jun 28 06:51:37 PM PDT 24
Peak memory 251200 kb
Host smart-48983285-2b0a-4d20-9873-45483cf1c52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612122071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.612122071
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3973473930
Short name T773
Test name
Test status
Simulation time 334869993 ps
CPU time 7.29 seconds
Started Jun 28 06:49:55 PM PDT 24
Finished Jun 28 06:51:21 PM PDT 24
Peak memory 247484 kb
Host smart-67ed0fff-60bd-4da8-8085-b3b8a9aa18ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973473930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3973473930
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.53716342
Short name T821
Test name
Test status
Simulation time 3071892338 ps
CPU time 30.73 seconds
Started Jun 28 06:50:06 PM PDT 24
Finished Jun 28 06:51:51 PM PDT 24
Peak memory 226300 kb
Host smart-db95a0cd-c8d4-4a9c-b66b-bf3a7ce50646
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53716342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.lc_ctrl_stress_all.53716342
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.129647909
Short name T851
Test name
Test status
Simulation time 18779696 ps
CPU time 0.97 seconds
Started Jun 28 06:49:57 PM PDT 24
Finished Jun 28 06:51:13 PM PDT 24
Peak memory 217920 kb
Host smart-e4cbfd2c-aa14-431d-bb80-8f49b327b0ff
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129647909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ct
rl_volatile_unlock_smoke.129647909
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.3158142575
Short name T348
Test name
Test status
Simulation time 38130897 ps
CPU time 0.98 seconds
Started Jun 28 06:50:22 PM PDT 24
Finished Jun 28 06:51:29 PM PDT 24
Peak memory 209260 kb
Host smart-fff1d5b8-4eaf-4d07-aa82-db26630deb37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158142575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.3158142575
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.442570002
Short name T443
Test name
Test status
Simulation time 376312391 ps
CPU time 13.22 seconds
Started Jun 28 06:50:23 PM PDT 24
Finished Jun 28 06:51:43 PM PDT 24
Peak memory 218424 kb
Host smart-2c48c6bb-2f82-4f7a-9945-c15ca5c75193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442570002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.442570002
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.642916925
Short name T579
Test name
Test status
Simulation time 1704710819 ps
CPU time 5.7 seconds
Started Jun 28 06:50:23 PM PDT 24
Finished Jun 28 06:51:35 PM PDT 24
Peak memory 217540 kb
Host smart-5ec445f6-caed-475d-91ee-4983bec387bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642916925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.642916925
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.3108834556
Short name T752
Test name
Test status
Simulation time 234912519 ps
CPU time 2.65 seconds
Started Jun 28 06:50:22 PM PDT 24
Finished Jun 28 06:51:30 PM PDT 24
Peak memory 218432 kb
Host smart-e6419049-c34e-4c7f-a17e-96c8aafed281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108834556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.3108834556
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.1602422227
Short name T316
Test name
Test status
Simulation time 389049091 ps
CPU time 17.02 seconds
Started Jun 28 06:50:22 PM PDT 24
Finished Jun 28 06:51:45 PM PDT 24
Peak memory 226264 kb
Host smart-127b8c5d-297b-4755-80c5-a32eca89ce67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602422227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1602422227
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3253943642
Short name T647
Test name
Test status
Simulation time 542699012 ps
CPU time 13.02 seconds
Started Jun 28 06:50:23 PM PDT 24
Finished Jun 28 06:51:43 PM PDT 24
Peak memory 218460 kb
Host smart-0a07b32d-0187-40a9-a681-a10fcb19b162
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253943642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3253943642
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.1242401980
Short name T291
Test name
Test status
Simulation time 2200312316 ps
CPU time 12.12 seconds
Started Jun 28 06:50:24 PM PDT 24
Finished Jun 28 06:51:42 PM PDT 24
Peak memory 218480 kb
Host smart-e4b9e8b6-18a5-43c3-922c-d001747bbcab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242401980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
1242401980
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.2516869169
Short name T657
Test name
Test status
Simulation time 251773433 ps
CPU time 8.45 seconds
Started Jun 28 06:50:26 PM PDT 24
Finished Jun 28 06:51:38 PM PDT 24
Peak memory 218504 kb
Host smart-27f36f45-e2ad-4fb8-940e-a7dd91d473ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516869169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2516869169
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.1254046089
Short name T302
Test name
Test status
Simulation time 46400240 ps
CPU time 1.29 seconds
Started Jun 28 06:50:07 PM PDT 24
Finished Jun 28 06:51:22 PM PDT 24
Peak memory 213884 kb
Host smart-5715db22-fd7f-4fc0-add6-adb02dde7262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254046089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.1254046089
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.881895796
Short name T514
Test name
Test status
Simulation time 821982153 ps
CPU time 24.79 seconds
Started Jun 28 06:50:08 PM PDT 24
Finished Jun 28 06:51:45 PM PDT 24
Peak memory 251152 kb
Host smart-901fed72-a79a-4f69-a255-6726941ba893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881895796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.881895796
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.215730201
Short name T329
Test name
Test status
Simulation time 1451789263 ps
CPU time 7.41 seconds
Started Jun 28 06:50:07 PM PDT 24
Finished Jun 28 06:51:28 PM PDT 24
Peak memory 246704 kb
Host smart-d8aedeba-31f7-4585-85a7-5e4eeece7f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215730201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.215730201
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.907855501
Short name T347
Test name
Test status
Simulation time 216253848827 ps
CPU time 689.31 seconds
Started Jun 28 06:50:21 PM PDT 24
Finished Jun 28 07:02:57 PM PDT 24
Peak memory 251124 kb
Host smart-3de14f14-63e8-4413-95f0-e1d8bfa58995
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907855501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.907855501
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3062121710
Short name T241
Test name
Test status
Simulation time 23804654 ps
CPU time 0.97 seconds
Started Jun 28 06:50:37 PM PDT 24
Finished Jun 28 06:51:37 PM PDT 24
Peak memory 209176 kb
Host smart-2826b205-a551-47ed-af1b-f0de5b2a9fea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062121710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3062121710
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.1430004297
Short name T698
Test name
Test status
Simulation time 646658316 ps
CPU time 11.58 seconds
Started Jun 28 06:50:22 PM PDT 24
Finished Jun 28 06:51:40 PM PDT 24
Peak memory 226248 kb
Host smart-da17c5bf-3695-4340-a2cd-bf4155291159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430004297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1430004297
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.3451978305
Short name T616
Test name
Test status
Simulation time 978495515 ps
CPU time 7.67 seconds
Started Jun 28 06:50:21 PM PDT 24
Finished Jun 28 06:51:36 PM PDT 24
Peak memory 217472 kb
Host smart-525a916a-d699-48ef-bdeb-88a6d323b6cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451978305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.3451978305
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3994279017
Short name T228
Test name
Test status
Simulation time 82167199 ps
CPU time 2.57 seconds
Started Jun 28 06:50:21 PM PDT 24
Finished Jun 28 06:51:30 PM PDT 24
Peak memory 218356 kb
Host smart-4e7d9258-0a3d-4625-bd34-62e31d4f8622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994279017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3994279017
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3052067562
Short name T600
Test name
Test status
Simulation time 349162888 ps
CPU time 10.98 seconds
Started Jun 28 06:50:34 PM PDT 24
Finished Jun 28 06:51:47 PM PDT 24
Peak memory 226236 kb
Host smart-5f266bec-5f2c-461c-8f78-460d512d6c49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052067562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3052067562
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1855877239
Short name T247
Test name
Test status
Simulation time 1707227891 ps
CPU time 12.83 seconds
Started Jun 28 06:50:35 PM PDT 24
Finished Jun 28 06:51:49 PM PDT 24
Peak memory 218464 kb
Host smart-c3ddd444-afd8-4f02-9181-0262918b0d8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855877239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.1855877239
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.2678310840
Short name T825
Test name
Test status
Simulation time 194315718 ps
CPU time 8.6 seconds
Started Jun 28 06:50:36 PM PDT 24
Finished Jun 28 06:51:45 PM PDT 24
Peak memory 218436 kb
Host smart-9e8286e6-1b7b-419d-aeed-8a8a12c039ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678310840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
2678310840
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1907851660
Short name T109
Test name
Test status
Simulation time 675871028 ps
CPU time 12.22 seconds
Started Jun 28 06:50:24 PM PDT 24
Finished Jun 28 06:51:42 PM PDT 24
Peak memory 218492 kb
Host smart-138895d8-d247-4028-97cd-be30a8dc5c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907851660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1907851660
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.515589814
Short name T181
Test name
Test status
Simulation time 98468974 ps
CPU time 2.93 seconds
Started Jun 28 06:50:22 PM PDT 24
Finished Jun 28 06:51:30 PM PDT 24
Peak memory 215096 kb
Host smart-a7418102-2e53-4ce8-bf1e-5a751d8862c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515589814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.515589814
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.2198282359
Short name T252
Test name
Test status
Simulation time 659767099 ps
CPU time 29.11 seconds
Started Jun 28 06:50:22 PM PDT 24
Finished Jun 28 06:51:57 PM PDT 24
Peak memory 251220 kb
Host smart-d3ecdadb-b708-4a70-9335-55a8f613c57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198282359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.2198282359
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.713552879
Short name T726
Test name
Test status
Simulation time 214382941 ps
CPU time 6.21 seconds
Started Jun 28 06:50:25 PM PDT 24
Finished Jun 28 06:51:36 PM PDT 24
Peak memory 250540 kb
Host smart-2a82a9e5-4798-48d7-b1b4-ec658becd0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713552879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.713552879
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.3555829435
Short name T72
Test name
Test status
Simulation time 27601704844 ps
CPU time 239.62 seconds
Started Jun 28 06:50:37 PM PDT 24
Finished Jun 28 06:55:36 PM PDT 24
Peak memory 421808 kb
Host smart-10b521b8-ba0d-4a46-b1dd-41960b1efefd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555829435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.3555829435
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.2260381207
Short name T163
Test name
Test status
Simulation time 88907464692 ps
CPU time 306.84 seconds
Started Jun 28 06:50:36 PM PDT 24
Finished Jun 28 06:56:42 PM PDT 24
Peak memory 267672 kb
Host smart-1e032b41-8efd-465c-9885-794717de2306
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2260381207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.2260381207
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3234634447
Short name T284
Test name
Test status
Simulation time 32801909 ps
CPU time 0.91 seconds
Started Jun 28 06:50:24 PM PDT 24
Finished Jun 28 06:51:31 PM PDT 24
Peak memory 212032 kb
Host smart-0898ad93-8962-45f3-843a-813595a3dd8e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234634447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3234634447
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.1138276438
Short name T605
Test name
Test status
Simulation time 15010692 ps
CPU time 1.04 seconds
Started Jun 28 06:50:48 PM PDT 24
Finished Jun 28 06:51:43 PM PDT 24
Peak memory 209180 kb
Host smart-f8bf2e99-6476-4782-8c31-4b79914ec0ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138276438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1138276438
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.3279627445
Short name T382
Test name
Test status
Simulation time 1519324434 ps
CPU time 13.36 seconds
Started Jun 28 06:50:34 PM PDT 24
Finished Jun 28 06:51:47 PM PDT 24
Peak memory 226160 kb
Host smart-5585d5ae-24d6-45b7-a708-78610602e421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279627445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.3279627445
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.2952247728
Short name T8
Test name
Test status
Simulation time 787529871 ps
CPU time 3.19 seconds
Started Jun 28 06:50:35 PM PDT 24
Finished Jun 28 06:51:39 PM PDT 24
Peak memory 217448 kb
Host smart-f59350fe-1541-4a47-a2e5-e32c5694eeec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952247728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.2952247728
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.1991310873
Short name T428
Test name
Test status
Simulation time 135817666 ps
CPU time 2.54 seconds
Started Jun 28 06:50:34 PM PDT 24
Finished Jun 28 06:51:39 PM PDT 24
Peak memory 218428 kb
Host smart-759f0c1a-507d-42aa-97a2-a5caec207403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991310873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1991310873
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.2472385109
Short name T672
Test name
Test status
Simulation time 312157511 ps
CPU time 11 seconds
Started Jun 28 06:50:50 PM PDT 24
Finished Jun 28 06:51:53 PM PDT 24
Peak memory 218424 kb
Host smart-34030273-a812-4fb8-adde-eda0392f9b73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472385109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.2472385109
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.2041274637
Short name T736
Test name
Test status
Simulation time 3947221511 ps
CPU time 12.1 seconds
Started Jun 28 06:50:47 PM PDT 24
Finished Jun 28 06:51:53 PM PDT 24
Peak memory 218524 kb
Host smart-9c590cc9-0b05-4905-a848-71b96632ebd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041274637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.2041274637
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2685827595
Short name T779
Test name
Test status
Simulation time 1512331693 ps
CPU time 15.69 seconds
Started Jun 28 06:50:50 PM PDT 24
Finished Jun 28 06:51:58 PM PDT 24
Peak memory 218420 kb
Host smart-13197886-e51a-4045-a2ff-eeb94bbdf43f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685827595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2685827595
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.386593134
Short name T120
Test name
Test status
Simulation time 611286879 ps
CPU time 9.22 seconds
Started Jun 28 06:50:34 PM PDT 24
Finished Jun 28 06:51:43 PM PDT 24
Peak memory 218504 kb
Host smart-d78f2cf5-9ffb-45f4-913a-7416e2113188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386593134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.386593134
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.739377325
Short name T224
Test name
Test status
Simulation time 71252625 ps
CPU time 2.55 seconds
Started Jun 28 06:50:34 PM PDT 24
Finished Jun 28 06:51:36 PM PDT 24
Peak memory 224180 kb
Host smart-53a5e92f-a978-416c-8818-794ea71f747a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739377325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.739377325
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3280543291
Short name T122
Test name
Test status
Simulation time 1346898911 ps
CPU time 28.8 seconds
Started Jun 28 06:50:36 PM PDT 24
Finished Jun 28 06:52:05 PM PDT 24
Peak memory 251124 kb
Host smart-2aa98530-ca27-4385-80cc-f93532296e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280543291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3280543291
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2032506848
Short name T661
Test name
Test status
Simulation time 93166974 ps
CPU time 6.51 seconds
Started Jun 28 06:50:38 PM PDT 24
Finished Jun 28 06:51:42 PM PDT 24
Peak memory 250980 kb
Host smart-826f00ac-372d-480e-988a-0ec597d9d806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032506848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2032506848
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.2483299728
Short name T695
Test name
Test status
Simulation time 1082082244 ps
CPU time 36.55 seconds
Started Jun 28 06:50:46 PM PDT 24
Finished Jun 28 06:52:18 PM PDT 24
Peak memory 218000 kb
Host smart-10a1fa15-f060-4f61-8669-eb3cf2cc3d3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483299728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.2483299728
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.2013035737
Short name T102
Test name
Test status
Simulation time 36377546609 ps
CPU time 739.44 seconds
Started Jun 28 06:50:45 PM PDT 24
Finished Jun 28 07:04:01 PM PDT 24
Peak memory 290180 kb
Host smart-d34d9941-db2b-4c65-a792-91528d13c885
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2013035737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.2013035737
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1467263959
Short name T684
Test name
Test status
Simulation time 45288222 ps
CPU time 0.81 seconds
Started Jun 28 06:50:36 PM PDT 24
Finished Jun 28 06:51:37 PM PDT 24
Peak memory 212084 kb
Host smart-1b35fba8-1576-4be4-9abc-ed8fa50d09e6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467263959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.1467263959
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.4108207479
Short name T799
Test name
Test status
Simulation time 68825180 ps
CPU time 1.15 seconds
Started Jun 28 06:51:17 PM PDT 24
Finished Jun 28 06:51:58 PM PDT 24
Peak memory 209176 kb
Host smart-85f593a5-4630-4697-84cb-1b943a8e4a15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108207479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.4108207479
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.3901271716
Short name T42
Test name
Test status
Simulation time 1324365932 ps
CPU time 11.03 seconds
Started Jun 28 06:51:00 PM PDT 24
Finished Jun 28 06:51:59 PM PDT 24
Peak memory 218516 kb
Host smart-23f6c103-14fe-416e-b8c3-48bb75c686d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901271716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3901271716
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.752573978
Short name T558
Test name
Test status
Simulation time 1638201456 ps
CPU time 5.31 seconds
Started Jun 28 06:50:59 PM PDT 24
Finished Jun 28 06:51:52 PM PDT 24
Peak memory 217468 kb
Host smart-25cdfad2-5a78-45ab-b3d5-bba943931c7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752573978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.752573978
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.652609744
Short name T841
Test name
Test status
Simulation time 341047426 ps
CPU time 2.87 seconds
Started Jun 28 06:51:00 PM PDT 24
Finished Jun 28 06:51:51 PM PDT 24
Peak memory 222364 kb
Host smart-0569dab3-4abf-4026-a3ae-17f33593ea7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652609744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.652609744
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.371110905
Short name T649
Test name
Test status
Simulation time 507202664 ps
CPU time 14.47 seconds
Started Jun 28 06:51:00 PM PDT 24
Finished Jun 28 06:52:02 PM PDT 24
Peak memory 219108 kb
Host smart-3140bf44-0adc-4baf-b9fa-d6d8c1ae7bfe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371110905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.371110905
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.1917792792
Short name T398
Test name
Test status
Simulation time 1204021804 ps
CPU time 8.49 seconds
Started Jun 28 06:51:13 PM PDT 24
Finished Jun 28 06:52:04 PM PDT 24
Peak memory 218528 kb
Host smart-9b9e6e6d-ad8d-4053-abc0-b953f2cfdcc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917792792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.1917792792
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.2816520456
Short name T363
Test name
Test status
Simulation time 656233025 ps
CPU time 7.21 seconds
Started Jun 28 06:51:00 PM PDT 24
Finished Jun 28 06:51:54 PM PDT 24
Peak memory 226240 kb
Host smart-ea356a1f-55db-4e75-ae10-2ba7f560cd99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816520456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
2816520456
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.152664508
Short name T620
Test name
Test status
Simulation time 288962303 ps
CPU time 8.98 seconds
Started Jun 28 06:50:59 PM PDT 24
Finished Jun 28 06:51:56 PM PDT 24
Peak memory 218572 kb
Host smart-93f0c90a-039b-4bb1-a4c5-53d4cc89cadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152664508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.152664508
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.181813067
Short name T626
Test name
Test status
Simulation time 29627652 ps
CPU time 2.44 seconds
Started Jun 28 06:50:46 PM PDT 24
Finished Jun 28 06:51:44 PM PDT 24
Peak memory 217844 kb
Host smart-580e37f9-9d4d-483c-ad93-bd9b24a42a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181813067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.181813067
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1839895722
Short name T833
Test name
Test status
Simulation time 332223052 ps
CPU time 22.13 seconds
Started Jun 28 06:50:46 PM PDT 24
Finished Jun 28 06:52:03 PM PDT 24
Peak memory 251128 kb
Host smart-a30eff1e-7fe0-4dd9-9004-7a04b46f6c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839895722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1839895722
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3735874570
Short name T630
Test name
Test status
Simulation time 151558798 ps
CPU time 3.67 seconds
Started Jun 28 06:50:46 PM PDT 24
Finished Jun 28 06:51:45 PM PDT 24
Peak memory 218436 kb
Host smart-5c43f907-32f1-41c7-aa08-984247a9a669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735874570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3735874570
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.1765333669
Short name T828
Test name
Test status
Simulation time 9826602205 ps
CPU time 271.17 seconds
Started Jun 28 06:51:15 PM PDT 24
Finished Jun 28 06:56:28 PM PDT 24
Peak memory 283956 kb
Host smart-68c72459-63cc-4b33-b6ad-4419761e412f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765333669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.1765333669
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.1491454716
Short name T38
Test name
Test status
Simulation time 29677452464 ps
CPU time 287.89 seconds
Started Jun 28 06:51:15 PM PDT 24
Finished Jun 28 06:56:44 PM PDT 24
Peak memory 259436 kb
Host smart-6946f454-0fd4-4c20-9231-3cfe152a18ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1491454716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.1491454716
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2828868033
Short name T14
Test name
Test status
Simulation time 13792455 ps
CPU time 1.09 seconds
Started Jun 28 06:50:50 PM PDT 24
Finished Jun 28 06:51:43 PM PDT 24
Peak memory 212032 kb
Host smart-5ec52085-5f02-4fd5-8d99-611606a29551
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828868033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.2828868033
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.187240484
Short name T668
Test name
Test status
Simulation time 14831289 ps
CPU time 0.88 seconds
Started Jun 28 06:51:17 PM PDT 24
Finished Jun 28 06:51:58 PM PDT 24
Peak memory 209180 kb
Host smart-5973df5e-0d5d-431d-9478-a9313d4544c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187240484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.187240484
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2598785608
Short name T706
Test name
Test status
Simulation time 2511761804 ps
CPU time 17.09 seconds
Started Jun 28 06:51:13 PM PDT 24
Finished Jun 28 06:52:12 PM PDT 24
Peak memory 219252 kb
Host smart-74375969-dccd-4860-b475-2dd00dcdd1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598785608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2598785608
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.2807652757
Short name T599
Test name
Test status
Simulation time 1579795334 ps
CPU time 6.12 seconds
Started Jun 28 06:51:13 PM PDT 24
Finished Jun 28 06:52:01 PM PDT 24
Peak memory 217604 kb
Host smart-de15353d-edd5-4fea-a95b-23678749442a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807652757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.2807652757
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.2750574800
Short name T478
Test name
Test status
Simulation time 70068895 ps
CPU time 1.54 seconds
Started Jun 28 06:51:13 PM PDT 24
Finished Jun 28 06:51:57 PM PDT 24
Peak memory 222156 kb
Host smart-bd67c9a0-1137-4761-8f84-85b0730227a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750574800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.2750574800
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.941125924
Short name T770
Test name
Test status
Simulation time 603380283 ps
CPU time 13.64 seconds
Started Jun 28 06:51:12 PM PDT 24
Finished Jun 28 06:52:09 PM PDT 24
Peak memory 226256 kb
Host smart-4cad3d77-5e2c-441c-ab74-d8af12891242
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941125924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.941125924
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2793495772
Short name T611
Test name
Test status
Simulation time 726131763 ps
CPU time 16.8 seconds
Started Jun 28 06:51:13 PM PDT 24
Finished Jun 28 06:52:12 PM PDT 24
Peak memory 218528 kb
Host smart-a8e4800d-b4ac-47a1-abf3-8192f92e3de8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793495772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.2793495772
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.145457681
Short name T393
Test name
Test status
Simulation time 483121585 ps
CPU time 6.98 seconds
Started Jun 28 06:51:15 PM PDT 24
Finished Jun 28 06:52:04 PM PDT 24
Peak memory 218448 kb
Host smart-81bdacaa-32b4-4403-a508-a36272a8d7df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145457681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.145457681
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.474635542
Short name T220
Test name
Test status
Simulation time 650469360 ps
CPU time 9.37 seconds
Started Jun 28 06:51:14 PM PDT 24
Finished Jun 28 06:52:06 PM PDT 24
Peak memory 218552 kb
Host smart-87c83c70-b7e6-45f4-8f3c-0a2dd72d80f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474635542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.474635542
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.93452590
Short name T180
Test name
Test status
Simulation time 60875146 ps
CPU time 2.77 seconds
Started Jun 28 06:51:13 PM PDT 24
Finished Jun 28 06:51:58 PM PDT 24
Peak memory 217956 kb
Host smart-da397ad1-da75-4812-bed1-b71fb8191e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93452590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.93452590
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1426835563
Short name T447
Test name
Test status
Simulation time 281006308 ps
CPU time 24.88 seconds
Started Jun 28 06:51:15 PM PDT 24
Finished Jun 28 06:52:21 PM PDT 24
Peak memory 251132 kb
Host smart-c4781b90-de6b-474d-853e-6262d6e33cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426835563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1426835563
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.161715794
Short name T312
Test name
Test status
Simulation time 342024854 ps
CPU time 4.13 seconds
Started Jun 28 06:51:15 PM PDT 24
Finished Jun 28 06:52:01 PM PDT 24
Peak memory 226572 kb
Host smart-bd72e7a5-5b9d-42ad-900c-f4a1e28f6922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161715794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.161715794
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.4256451805
Short name T408
Test name
Test status
Simulation time 13566956610 ps
CPU time 76.12 seconds
Started Jun 28 06:51:13 PM PDT 24
Finished Jun 28 06:53:11 PM PDT 24
Peak memory 271180 kb
Host smart-a17474f1-b67a-433d-999a-3435d21aac62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256451805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.4256451805
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2174499844
Short name T697
Test name
Test status
Simulation time 33968529 ps
CPU time 0.92 seconds
Started Jun 28 06:51:15 PM PDT 24
Finished Jun 28 06:51:57 PM PDT 24
Peak memory 212096 kb
Host smart-4a287cca-1b5d-4a6c-b131-ceeb8119d483
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174499844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.2174499844
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.743804730
Short name T648
Test name
Test status
Simulation time 66049134 ps
CPU time 0.91 seconds
Started Jun 28 06:38:06 PM PDT 24
Finished Jun 28 06:38:35 PM PDT 24
Peak memory 209240 kb
Host smart-6f04ba89-965d-4d0b-805f-ffa4b5e6cda3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743804730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.743804730
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.1581307300
Short name T688
Test name
Test status
Simulation time 651986193 ps
CPU time 14.6 seconds
Started Jun 28 06:37:54 PM PDT 24
Finished Jun 28 06:38:17 PM PDT 24
Peak memory 218372 kb
Host smart-1bd1a06e-2388-4c73-a8c5-bd6058db4c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581307300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1581307300
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.43604476
Short name T803
Test name
Test status
Simulation time 544436208 ps
CPU time 3.73 seconds
Started Jun 28 06:38:05 PM PDT 24
Finished Jun 28 06:38:35 PM PDT 24
Peak memory 217564 kb
Host smart-0985d750-a6fb-4d64-805d-66907ab7adae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43604476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.43604476
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.2093952054
Short name T681
Test name
Test status
Simulation time 7419500343 ps
CPU time 51.78 seconds
Started Jun 28 06:38:03 PM PDT 24
Finished Jun 28 06:39:16 PM PDT 24
Peak memory 226288 kb
Host smart-cefb0a5c-578c-4c10-bb40-1db2e90fa9c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093952054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.2093952054
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2358053562
Short name T749
Test name
Test status
Simulation time 459161503 ps
CPU time 3.33 seconds
Started Jun 28 06:38:05 PM PDT 24
Finished Jun 28 06:38:31 PM PDT 24
Peak memory 217736 kb
Host smart-ca446350-5844-462a-bbd2-3567ccef4304
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358053562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
358053562
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1265746439
Short name T418
Test name
Test status
Simulation time 1280802171 ps
CPU time 18.27 seconds
Started Jun 28 06:38:05 PM PDT 24
Finished Jun 28 06:38:46 PM PDT 24
Peak memory 218420 kb
Host smart-65d5ef5f-14bd-4b3c-a92f-11dbb9f2cff3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265746439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.1265746439
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1091504091
Short name T580
Test name
Test status
Simulation time 1147393600 ps
CPU time 34.1 seconds
Started Jun 28 06:38:05 PM PDT 24
Finished Jun 28 06:39:02 PM PDT 24
Peak memory 217924 kb
Host smart-0761431d-ae4e-4640-ac58-85ea4ddc1f0c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091504091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.1091504091
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.2940220501
Short name T358
Test name
Test status
Simulation time 89004883 ps
CPU time 3.4 seconds
Started Jun 28 06:38:04 PM PDT 24
Finished Jun 28 06:38:31 PM PDT 24
Peak memory 217900 kb
Host smart-fe7cebdb-2532-4f95-b021-c2177240df54
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940220501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
2940220501
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.4031708847
Short name T182
Test name
Test status
Simulation time 5953914926 ps
CPU time 63.95 seconds
Started Jun 28 06:38:05 PM PDT 24
Finished Jun 28 06:39:35 PM PDT 24
Peak memory 278756 kb
Host smart-e0feb030-18d1-4934-8401-64c3514c6adc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031708847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.4031708847
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2534291195
Short name T638
Test name
Test status
Simulation time 441409606 ps
CPU time 14.89 seconds
Started Jun 28 06:38:03 PM PDT 24
Finished Jun 28 06:38:40 PM PDT 24
Peak memory 251132 kb
Host smart-c4d7db48-dc02-4721-be92-4779f9db513a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534291195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2534291195
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1458800442
Short name T643
Test name
Test status
Simulation time 267146270 ps
CPU time 2.41 seconds
Started Jun 28 06:37:54 PM PDT 24
Finished Jun 28 06:38:05 PM PDT 24
Peak memory 218416 kb
Host smart-5f0ca06d-5a9b-4ad5-a5b8-bce15f7bea46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458800442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1458800442
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.2083451311
Short name T83
Test name
Test status
Simulation time 792401150 ps
CPU time 14.89 seconds
Started Jun 28 06:37:53 PM PDT 24
Finished Jun 28 06:38:14 PM PDT 24
Peak memory 217928 kb
Host smart-c412a990-be37-40d1-88a1-3795ad95ffd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083451311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2083451311
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1252037081
Short name T503
Test name
Test status
Simulation time 1316600273 ps
CPU time 15.35 seconds
Started Jun 28 06:38:03 PM PDT 24
Finished Jun 28 06:38:40 PM PDT 24
Peak memory 226248 kb
Host smart-8f59f4b2-db64-4cb9-9e03-bbfa46ddd581
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252037081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1252037081
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3629696487
Short name T678
Test name
Test status
Simulation time 2592007286 ps
CPU time 15.47 seconds
Started Jun 28 06:38:03 PM PDT 24
Finished Jun 28 06:38:40 PM PDT 24
Peak memory 218500 kb
Host smart-48052211-ea05-49f8-9cac-468951fddde5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629696487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.3629696487
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.1632644855
Short name T455
Test name
Test status
Simulation time 620283538 ps
CPU time 8.56 seconds
Started Jun 28 06:38:05 PM PDT 24
Finished Jun 28 06:38:36 PM PDT 24
Peak memory 218436 kb
Host smart-bbd40812-71b2-41e1-9d99-1db2a5da6d15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632644855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.1
632644855
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.3177745943
Short name T556
Test name
Test status
Simulation time 266056749 ps
CPU time 7.3 seconds
Started Jun 28 06:37:53 PM PDT 24
Finished Jun 28 06:38:05 PM PDT 24
Peak memory 218528 kb
Host smart-e0b259df-9b4e-4fe1-aff6-6a91b35d525c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177745943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.3177745943
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.384874374
Short name T351
Test name
Test status
Simulation time 46116364 ps
CPU time 3.04 seconds
Started Jun 28 06:37:54 PM PDT 24
Finished Jun 28 06:38:07 PM PDT 24
Peak memory 217916 kb
Host smart-5f0537b7-210e-46c3-bc32-aa4bb2580b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384874374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.384874374
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.957610421
Short name T644
Test name
Test status
Simulation time 1644951676 ps
CPU time 30.22 seconds
Started Jun 28 06:37:53 PM PDT 24
Finished Jun 28 06:38:28 PM PDT 24
Peak memory 251208 kb
Host smart-264a8fff-fa12-4ff5-9c36-f8d091c177f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957610421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.957610421
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.3706983525
Short name T577
Test name
Test status
Simulation time 303150131 ps
CPU time 3.48 seconds
Started Jun 28 06:37:54 PM PDT 24
Finished Jun 28 06:38:07 PM PDT 24
Peak memory 218436 kb
Host smart-e7bac1f8-ffc2-4b12-ae7e-c19fd00e3e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706983525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.3706983525
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1955612899
Short name T798
Test name
Test status
Simulation time 12272556218 ps
CPU time 156.86 seconds
Started Jun 28 06:38:04 PM PDT 24
Finished Jun 28 06:41:04 PM PDT 24
Peak memory 283860 kb
Host smart-59295d14-76a0-481b-b8b5-19f57133700f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955612899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1955612899
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.126079831
Short name T167
Test name
Test status
Simulation time 89162344251 ps
CPU time 407.28 seconds
Started Jun 28 06:38:03 PM PDT 24
Finished Jun 28 06:45:12 PM PDT 24
Peak memory 277328 kb
Host smart-d3ea539a-82c9-4e60-9ca8-189dad3033b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=126079831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.126079831
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1169239454
Short name T723
Test name
Test status
Simulation time 11207539 ps
CPU time 0.98 seconds
Started Jun 28 06:37:55 PM PDT 24
Finished Jun 28 06:38:07 PM PDT 24
Peak memory 212064 kb
Host smart-2bab557d-9726-43bc-9bec-f07c9a5e5d93
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169239454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.1169239454
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.4180019105
Short name T569
Test name
Test status
Simulation time 19124428 ps
CPU time 0.94 seconds
Started Jun 28 06:38:20 PM PDT 24
Finished Jun 28 06:39:07 PM PDT 24
Peak memory 209172 kb
Host smart-36481364-4510-4864-9949-f5c4396c201e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180019105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.4180019105
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.162751760
Short name T25
Test name
Test status
Simulation time 15057191 ps
CPU time 0.85 seconds
Started Jun 28 06:38:03 PM PDT 24
Finished Jun 28 06:38:28 PM PDT 24
Peak memory 208964 kb
Host smart-fb70f632-67c6-4b03-b454-5f074f4da8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162751760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.162751760
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.3683733118
Short name T116
Test name
Test status
Simulation time 1352557201 ps
CPU time 11.96 seconds
Started Jun 28 06:38:04 PM PDT 24
Finished Jun 28 06:38:39 PM PDT 24
Peak memory 218428 kb
Host smart-34a3f825-d187-4685-bb92-1f2463bdc4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683733118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3683733118
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.3269936110
Short name T811
Test name
Test status
Simulation time 2997775368 ps
CPU time 7.56 seconds
Started Jun 28 06:38:22 PM PDT 24
Finished Jun 28 06:39:16 PM PDT 24
Peak memory 217916 kb
Host smart-51ef7768-4c41-4508-a7cb-56e226804f7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269936110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.3269936110
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.3424331228
Short name T552
Test name
Test status
Simulation time 5393599259 ps
CPU time 26.47 seconds
Started Jun 28 06:38:21 PM PDT 24
Finished Jun 28 06:39:33 PM PDT 24
Peak memory 219120 kb
Host smart-80554e80-bbbe-4a2d-b272-df3c1ec447bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424331228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.3424331228
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.434050639
Short name T824
Test name
Test status
Simulation time 14807174317 ps
CPU time 43.99 seconds
Started Jun 28 06:38:20 PM PDT 24
Finished Jun 28 06:39:50 PM PDT 24
Peak memory 217936 kb
Host smart-891702bf-c13d-4229-82c6-edbb512ae69b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434050639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.434050639
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.1949286608
Short name T819
Test name
Test status
Simulation time 1443346131 ps
CPU time 3.5 seconds
Started Jun 28 06:38:20 PM PDT 24
Finished Jun 28 06:39:10 PM PDT 24
Peak memory 218408 kb
Host smart-3fc5fcb8-809a-4a0e-a6dc-40db3878ecad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949286608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.1949286608
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2335155336
Short name T85
Test name
Test status
Simulation time 891295685 ps
CPU time 15.74 seconds
Started Jun 28 06:38:21 PM PDT 24
Finished Jun 28 06:39:24 PM PDT 24
Peak memory 217988 kb
Host smart-494b8972-6aed-4f2a-a3cc-80cc9bbd521b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335155336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.2335155336
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.2963272374
Short name T816
Test name
Test status
Simulation time 401492951 ps
CPU time 2.5 seconds
Started Jun 28 06:38:23 PM PDT 24
Finished Jun 28 06:39:13 PM PDT 24
Peak memory 217920 kb
Host smart-5db5bb68-a4d6-4767-b87e-398ba4f52be7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963272374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
2963272374
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2364339987
Short name T754
Test name
Test status
Simulation time 3748578737 ps
CPU time 42.68 seconds
Started Jun 28 06:38:20 PM PDT 24
Finished Jun 28 06:39:49 PM PDT 24
Peak memory 251324 kb
Host smart-a97e8fb9-4eb8-4d04-a0db-6ab3830b91d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364339987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.2364339987
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3690235068
Short name T610
Test name
Test status
Simulation time 352912383 ps
CPU time 16.17 seconds
Started Jun 28 06:38:26 PM PDT 24
Finished Jun 28 06:39:30 PM PDT 24
Peak memory 250464 kb
Host smart-5170b46a-4419-4b4c-9935-a93cf8fc3b3c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690235068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.3690235068
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.930982123
Short name T476
Test name
Test status
Simulation time 311190766 ps
CPU time 3.72 seconds
Started Jun 28 06:38:08 PM PDT 24
Finished Jun 28 06:38:42 PM PDT 24
Peak memory 218432 kb
Host smart-52b19390-21b5-4544-ad0c-ca81d182c273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930982123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.930982123
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2961246575
Short name T77
Test name
Test status
Simulation time 487926908 ps
CPU time 6.09 seconds
Started Jun 28 06:38:05 PM PDT 24
Finished Jun 28 06:38:34 PM PDT 24
Peak memory 222552 kb
Host smart-dbb286e2-6c8c-4e0b-923a-38700a756380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961246575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2961246575
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.1116325869
Short name T223
Test name
Test status
Simulation time 1207305049 ps
CPU time 9.85 seconds
Started Jun 28 06:38:22 PM PDT 24
Finished Jun 28 06:39:19 PM PDT 24
Peak memory 226240 kb
Host smart-41f9ffb0-7db6-4f8b-b9a5-dda111d4a840
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116325869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1116325869
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.3631138758
Short name T253
Test name
Test status
Simulation time 1736673654 ps
CPU time 13.55 seconds
Started Jun 28 06:38:25 PM PDT 24
Finished Jun 28 06:39:27 PM PDT 24
Peak memory 218436 kb
Host smart-6d4b3528-bec3-4068-a32b-7778d9b50426
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631138758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.3631138758
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.917174111
Short name T272
Test name
Test status
Simulation time 982513886 ps
CPU time 9.67 seconds
Started Jun 28 06:38:23 PM PDT 24
Finished Jun 28 06:39:20 PM PDT 24
Peak memory 226248 kb
Host smart-d858758f-e7a0-46f7-8f86-578194b0ece3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917174111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.917174111
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.4208014460
Short name T222
Test name
Test status
Simulation time 976615454 ps
CPU time 6.5 seconds
Started Jun 28 06:38:06 PM PDT 24
Finished Jun 28 06:38:38 PM PDT 24
Peak memory 218488 kb
Host smart-21b9ec89-151f-4594-85c1-978915ad4af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208014460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.4208014460
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.3540385353
Short name T265
Test name
Test status
Simulation time 173847170 ps
CPU time 3.11 seconds
Started Jun 28 06:38:06 PM PDT 24
Finished Jun 28 06:38:34 PM PDT 24
Peak memory 215164 kb
Host smart-6a57f5f9-aa3c-4778-8168-729267ac17d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540385353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3540385353
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.504155340
Short name T806
Test name
Test status
Simulation time 732912686 ps
CPU time 20.41 seconds
Started Jun 28 06:38:07 PM PDT 24
Finished Jun 28 06:38:55 PM PDT 24
Peak memory 251124 kb
Host smart-eeea7b46-dfb6-44a4-b54f-23cec3ac89d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504155340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.504155340
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2820549965
Short name T848
Test name
Test status
Simulation time 92472326 ps
CPU time 3.64 seconds
Started Jun 28 06:38:05 PM PDT 24
Finished Jun 28 06:38:31 PM PDT 24
Peak memory 226552 kb
Host smart-fc3eb5c9-c856-465c-906b-24ba7241b2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820549965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2820549965
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.4103859889
Short name T192
Test name
Test status
Simulation time 3805204307 ps
CPU time 19.88 seconds
Started Jun 28 06:38:21 PM PDT 24
Finished Jun 28 06:39:28 PM PDT 24
Peak memory 221980 kb
Host smart-875d6f93-3a2c-44fa-8ec4-b922da2e5f1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103859889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.4103859889
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2327291461
Short name T255
Test name
Test status
Simulation time 45178176 ps
CPU time 0.87 seconds
Started Jun 28 06:38:03 PM PDT 24
Finished Jun 28 06:38:25 PM PDT 24
Peak memory 212132 kb
Host smart-963e3395-577b-4cc0-af5d-6214613e6ebd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327291461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2327291461
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.300018821
Short name T826
Test name
Test status
Simulation time 82828025 ps
CPU time 1.24 seconds
Started Jun 28 06:38:26 PM PDT 24
Finished Jun 28 06:39:15 PM PDT 24
Peak memory 209220 kb
Host smart-ac5f9faf-326b-4206-953e-ee95fa898acf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300018821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.300018821
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.4081877228
Short name T535
Test name
Test status
Simulation time 25565911 ps
CPU time 0.91 seconds
Started Jun 28 06:38:23 PM PDT 24
Finished Jun 28 06:39:12 PM PDT 24
Peak memory 209180 kb
Host smart-99152ecf-9462-4ac5-a87e-df934951faf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081877228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.4081877228
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1846244352
Short name T100
Test name
Test status
Simulation time 294307939 ps
CPU time 11.43 seconds
Started Jun 28 06:38:23 PM PDT 24
Finished Jun 28 06:39:22 PM PDT 24
Peak memory 218444 kb
Host smart-f57ebe44-230f-46a0-b481-65fa72eadf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846244352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1846244352
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.2951190879
Short name T27
Test name
Test status
Simulation time 1336622007 ps
CPU time 4.41 seconds
Started Jun 28 06:38:25 PM PDT 24
Finished Jun 28 06:39:18 PM PDT 24
Peak memory 217296 kb
Host smart-3ea37aac-6720-45ee-884d-8fe072dc51f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951190879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.2951190879
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.1224561937
Short name T356
Test name
Test status
Simulation time 2255140858 ps
CPU time 32.5 seconds
Started Jun 28 06:38:24 PM PDT 24
Finished Jun 28 06:39:44 PM PDT 24
Peak memory 218472 kb
Host smart-d3704ebd-e67d-4e55-bf42-1ce87b2e2ecc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224561937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.1224561937
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.3337931028
Short name T617
Test name
Test status
Simulation time 2691005031 ps
CPU time 3.95 seconds
Started Jun 28 06:38:22 PM PDT 24
Finished Jun 28 06:39:13 PM PDT 24
Peak memory 218016 kb
Host smart-dd955d2b-0552-4aee-8f60-d29e09bb351b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337931028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.3
337931028
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.3238788215
Short name T534
Test name
Test status
Simulation time 324683457 ps
CPU time 5.64 seconds
Started Jun 28 06:38:22 PM PDT 24
Finished Jun 28 06:39:14 PM PDT 24
Peak memory 218552 kb
Host smart-a93b407b-9ad5-456c-86e7-afb7b53fa656
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238788215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.3238788215
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2153216911
Short name T687
Test name
Test status
Simulation time 727331844 ps
CPU time 12.84 seconds
Started Jun 28 06:38:21 PM PDT 24
Finished Jun 28 06:39:21 PM PDT 24
Peak memory 217920 kb
Host smart-97927bd7-123d-4ef5-9a59-1e44d45a842b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153216911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.2153216911
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.2921635983
Short name T674
Test name
Test status
Simulation time 1270761548 ps
CPU time 1.9 seconds
Started Jun 28 06:38:25 PM PDT 24
Finished Jun 28 06:39:15 PM PDT 24
Peak memory 217932 kb
Host smart-ed62519d-9856-468c-be92-914240ae4fa6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921635983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
2921635983
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1480703989
Short name T642
Test name
Test status
Simulation time 1503864369 ps
CPU time 55.16 seconds
Started Jun 28 06:38:25 PM PDT 24
Finished Jun 28 06:40:08 PM PDT 24
Peak memory 251136 kb
Host smart-bf7df53d-9cb9-4cab-bec5-32aec5830256
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480703989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1480703989
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2396411362
Short name T172
Test name
Test status
Simulation time 1190480230 ps
CPU time 9.78 seconds
Started Jun 28 06:38:22 PM PDT 24
Finished Jun 28 06:39:19 PM PDT 24
Peak memory 250616 kb
Host smart-b2d9a9b3-6df8-40b6-a70b-73e22976ee06
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396411362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2396411362
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.4271162276
Short name T256
Test name
Test status
Simulation time 75405856 ps
CPU time 1.58 seconds
Started Jun 28 06:38:22 PM PDT 24
Finished Jun 28 06:39:10 PM PDT 24
Peak memory 222128 kb
Host smart-df850414-d518-497e-b90b-a6131f8b1c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271162276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.4271162276
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.770208125
Short name T720
Test name
Test status
Simulation time 487333617 ps
CPU time 10.57 seconds
Started Jun 28 06:38:20 PM PDT 24
Finished Jun 28 06:39:17 PM PDT 24
Peak memory 214376 kb
Host smart-7db88933-7f07-46ae-bf71-cb319a365cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770208125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.770208125
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.3735997228
Short name T519
Test name
Test status
Simulation time 256043602 ps
CPU time 9.45 seconds
Started Jun 28 06:38:21 PM PDT 24
Finished Jun 28 06:39:18 PM PDT 24
Peak memory 226232 kb
Host smart-1d872563-a852-430c-a150-08c9b71d6cc7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735997228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.3735997228
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3357069941
Short name T303
Test name
Test status
Simulation time 375330995 ps
CPU time 13.38 seconds
Started Jun 28 06:38:27 PM PDT 24
Finished Jun 28 06:39:28 PM PDT 24
Peak memory 218404 kb
Host smart-c7813be8-cd69-4f87-b520-ff21f8b727fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357069941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3357069941
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2530318752
Short name T495
Test name
Test status
Simulation time 381859492 ps
CPU time 8.73 seconds
Started Jun 28 06:38:28 PM PDT 24
Finished Jun 28 06:39:24 PM PDT 24
Peak memory 218440 kb
Host smart-f1257fbb-a652-4234-bf5c-f0dd90cb51d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530318752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2
530318752
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.290007530
Short name T585
Test name
Test status
Simulation time 544503274 ps
CPU time 8.62 seconds
Started Jun 28 06:38:25 PM PDT 24
Finished Jun 28 06:39:22 PM PDT 24
Peak memory 218564 kb
Host smart-df69c7e1-87cd-472c-ba15-3369885e1b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290007530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.290007530
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.437496789
Short name T84
Test name
Test status
Simulation time 15318819 ps
CPU time 1.23 seconds
Started Jun 28 06:38:21 PM PDT 24
Finished Jun 28 06:39:10 PM PDT 24
Peak memory 217940 kb
Host smart-03381857-82c3-4eb2-80ce-957951d570d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437496789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.437496789
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.533365118
Short name T852
Test name
Test status
Simulation time 209687870 ps
CPU time 23.44 seconds
Started Jun 28 06:38:21 PM PDT 24
Finished Jun 28 06:39:30 PM PDT 24
Peak memory 245724 kb
Host smart-85635945-5afc-4446-bee9-e36b28ce3034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533365118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.533365118
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1263270543
Short name T137
Test name
Test status
Simulation time 343401118 ps
CPU time 7.09 seconds
Started Jun 28 06:38:22 PM PDT 24
Finished Jun 28 06:39:16 PM PDT 24
Peak memory 251140 kb
Host smart-7ec41a1d-41ed-411b-a95e-6108a9fe0ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263270543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1263270543
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.3591606416
Short name T343
Test name
Test status
Simulation time 6857118836 ps
CPU time 174.15 seconds
Started Jun 28 06:38:21 PM PDT 24
Finished Jun 28 06:42:03 PM PDT 24
Peak memory 251300 kb
Host smart-a999c38a-39e4-4564-95ac-2570844879c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591606416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.3591606416
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.1333258905
Short name T129
Test name
Test status
Simulation time 88094978589 ps
CPU time 783.01 seconds
Started Jun 28 06:38:24 PM PDT 24
Finished Jun 28 06:52:16 PM PDT 24
Peak memory 422276 kb
Host smart-79dbe84a-ea66-4a14-80de-13ad2cf07dbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1333258905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.1333258905
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1532759613
Short name T305
Test name
Test status
Simulation time 18415945 ps
CPU time 0.87 seconds
Started Jun 28 06:38:20 PM PDT 24
Finished Jun 28 06:39:07 PM PDT 24
Peak memory 212136 kb
Host smart-c41dd26b-3195-4b30-ab1e-e62a9cad1ebf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532759613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1532759613
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1744234997
Short name T745
Test name
Test status
Simulation time 17514271 ps
CPU time 0.87 seconds
Started Jun 28 06:38:43 PM PDT 24
Finished Jun 28 06:39:22 PM PDT 24
Peak memory 209172 kb
Host smart-28bdd5cd-63a8-4535-9b63-ddf8a3e6cdb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744234997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1744234997
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.923238202
Short name T216
Test name
Test status
Simulation time 16450416 ps
CPU time 0.79 seconds
Started Jun 28 06:38:33 PM PDT 24
Finished Jun 28 06:39:19 PM PDT 24
Peak memory 209148 kb
Host smart-70af6834-066c-4d0e-997a-b7cee35ee393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923238202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.923238202
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.658623762
Short name T401
Test name
Test status
Simulation time 630434289 ps
CPU time 15.17 seconds
Started Jun 28 06:38:30 PM PDT 24
Finished Jun 28 06:39:31 PM PDT 24
Peak memory 218420 kb
Host smart-15605890-e225-46fd-a472-73f228f15bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658623762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.658623762
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.571938074
Short name T29
Test name
Test status
Simulation time 618128841 ps
CPU time 8.91 seconds
Started Jun 28 06:38:34 PM PDT 24
Finished Jun 28 06:39:28 PM PDT 24
Peak memory 217612 kb
Host smart-5e6713de-8dd2-4616-9fdc-df952a5b1591
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571938074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.571938074
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.3798791479
Short name T268
Test name
Test status
Simulation time 9569300992 ps
CPU time 35.91 seconds
Started Jun 28 06:38:35 PM PDT 24
Finished Jun 28 06:39:55 PM PDT 24
Peak memory 226404 kb
Host smart-adb070bd-a53c-4f65-b2a6-953baf54c6fb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798791479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.3798791479
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.159996614
Short name T117
Test name
Test status
Simulation time 462133955 ps
CPU time 2.22 seconds
Started Jun 28 06:38:31 PM PDT 24
Finished Jun 28 06:39:20 PM PDT 24
Peak memory 217604 kb
Host smart-7ac64d07-0877-4e59-b013-5b16bbb98fd1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159996614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.159996614
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2323354020
Short name T787
Test name
Test status
Simulation time 7948565011 ps
CPU time 5.44 seconds
Started Jun 28 06:38:35 PM PDT 24
Finished Jun 28 06:39:25 PM PDT 24
Peak memory 222564 kb
Host smart-4b4c7c96-bab2-4b0a-b2a7-dd366836e6e0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323354020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2323354020
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.120215242
Short name T22
Test name
Test status
Simulation time 1182297646 ps
CPU time 17.93 seconds
Started Jun 28 06:38:35 PM PDT 24
Finished Jun 28 06:39:37 PM PDT 24
Peak memory 217940 kb
Host smart-5134aa85-2ff4-4148-9344-f3cc90117a10
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120215242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_regwen_during_op.120215242
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.4197513628
Short name T440
Test name
Test status
Simulation time 1373586446 ps
CPU time 5.85 seconds
Started Jun 28 06:38:33 PM PDT 24
Finished Jun 28 06:39:24 PM PDT 24
Peak memory 217904 kb
Host smart-6d1680fd-f196-4f91-992a-b7022775b3ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197513628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
4197513628
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2018688968
Short name T391
Test name
Test status
Simulation time 2607511000 ps
CPU time 55.74 seconds
Started Jun 28 06:38:32 PM PDT 24
Finished Jun 28 06:40:13 PM PDT 24
Peak memory 267940 kb
Host smart-ab39412a-ef1e-4012-b073-bd8bfd7e5bc8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018688968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2018688968
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3957592686
Short name T794
Test name
Test status
Simulation time 294466318 ps
CPU time 9.8 seconds
Started Jun 28 06:38:31 PM PDT 24
Finished Jun 28 06:39:27 PM PDT 24
Peak memory 247680 kb
Host smart-d0677ffb-49dc-4588-b707-4d45264a2b4c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957592686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.3957592686
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.657430117
Short name T245
Test name
Test status
Simulation time 181445599 ps
CPU time 2.11 seconds
Started Jun 28 06:38:31 PM PDT 24
Finished Jun 28 06:39:19 PM PDT 24
Peak memory 222448 kb
Host smart-0d15e6f1-1824-4c42-b7ab-7abfcc233f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657430117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.657430117
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.1629296290
Short name T270
Test name
Test status
Simulation time 351055193 ps
CPU time 12.08 seconds
Started Jun 28 06:38:31 PM PDT 24
Finished Jun 28 06:39:29 PM PDT 24
Peak memory 214244 kb
Host smart-5c0ad6fb-7b81-4814-a7d5-1ba28c9e2286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629296290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1629296290
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.2014290509
Short name T543
Test name
Test status
Simulation time 782254001 ps
CPU time 18.19 seconds
Started Jun 28 06:38:31 PM PDT 24
Finished Jun 28 06:39:35 PM PDT 24
Peak memory 226164 kb
Host smart-4de5a9b3-0345-485c-9c46-5748eaadf60b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014290509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.2014290509
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2280258490
Short name T694
Test name
Test status
Simulation time 636385961 ps
CPU time 13.8 seconds
Started Jun 28 06:38:31 PM PDT 24
Finished Jun 28 06:39:31 PM PDT 24
Peak memory 218456 kb
Host smart-ab7ffc87-aa19-460f-bfa2-610e559b60c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280258490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2280258490
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.1251779152
Short name T290
Test name
Test status
Simulation time 3677960529 ps
CPU time 9.45 seconds
Started Jun 28 06:38:32 PM PDT 24
Finished Jun 28 06:39:27 PM PDT 24
Peak memory 226248 kb
Host smart-8eb27edb-eafc-4bac-9067-59062e3ec7c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251779152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.1
251779152
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.3693321124
Short name T390
Test name
Test status
Simulation time 5519132000 ps
CPU time 8.84 seconds
Started Jun 28 06:38:31 PM PDT 24
Finished Jun 28 06:39:27 PM PDT 24
Peak memory 218568 kb
Host smart-6f914b0e-aa41-46a2-a599-eb2acbe17bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693321124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3693321124
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.2556504215
Short name T79
Test name
Test status
Simulation time 64057210 ps
CPU time 1.82 seconds
Started Jun 28 06:38:25 PM PDT 24
Finished Jun 28 06:39:15 PM PDT 24
Peak memory 217908 kb
Host smart-80fb36a4-9630-4327-9b8c-4f9e42630002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556504215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2556504215
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3472563019
Short name T310
Test name
Test status
Simulation time 699396858 ps
CPU time 22.95 seconds
Started Jun 28 06:38:25 PM PDT 24
Finished Jun 28 06:39:36 PM PDT 24
Peak memory 251136 kb
Host smart-c8c70b81-0c30-4420-bce8-8d0c79e8f8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472563019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3472563019
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.2752314805
Short name T807
Test name
Test status
Simulation time 244704180 ps
CPU time 6.61 seconds
Started Jun 28 06:38:25 PM PDT 24
Finished Jun 28 06:39:20 PM PDT 24
Peak memory 250672 kb
Host smart-a98b47d1-639d-4ba3-b8a5-7365caa5d58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752314805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2752314805
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.2872455884
Short name T682
Test name
Test status
Simulation time 12670322870 ps
CPU time 114.55 seconds
Started Jun 28 06:38:33 PM PDT 24
Finished Jun 28 06:41:12 PM PDT 24
Peak memory 223612 kb
Host smart-81bfa8ff-64c2-4896-9a3e-61f32bbdc6df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872455884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.2872455884
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2141007989
Short name T279
Test name
Test status
Simulation time 62701827 ps
CPU time 0.87 seconds
Started Jun 28 06:38:26 PM PDT 24
Finished Jun 28 06:39:14 PM PDT 24
Peak memory 212088 kb
Host smart-854e9b5b-7342-4a55-bedd-c94bb701efa9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141007989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.2141007989
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.2081361058
Short name T318
Test name
Test status
Simulation time 30441830 ps
CPU time 1.38 seconds
Started Jun 28 06:39:02 PM PDT 24
Finished Jun 28 06:39:31 PM PDT 24
Peak memory 209196 kb
Host smart-22b51aff-0ea7-4e7f-bdf2-031a812f227c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081361058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.2081361058
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.1897536160
Short name T667
Test name
Test status
Simulation time 11932405 ps
CPU time 0.95 seconds
Started Jun 28 06:38:43 PM PDT 24
Finished Jun 28 06:39:22 PM PDT 24
Peak memory 209216 kb
Host smart-02240537-a3fa-4183-af46-675865da3bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897536160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1897536160
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1532478316
Short name T242
Test name
Test status
Simulation time 523887888 ps
CPU time 14.73 seconds
Started Jun 28 06:38:44 PM PDT 24
Finished Jun 28 06:39:37 PM PDT 24
Peak memory 218444 kb
Host smart-d75f8e59-40b9-4bfa-9046-bc23ad61cb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532478316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1532478316
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3039025722
Short name T454
Test name
Test status
Simulation time 232858080 ps
CPU time 2.2 seconds
Started Jun 28 06:38:43 PM PDT 24
Finished Jun 28 06:39:24 PM PDT 24
Peak memory 217200 kb
Host smart-c7d283b8-9ab3-4824-a5c0-746f22ab6571
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039025722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3039025722
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1516649472
Short name T35
Test name
Test status
Simulation time 1779553781 ps
CPU time 54.03 seconds
Started Jun 28 06:38:43 PM PDT 24
Finished Jun 28 06:40:15 PM PDT 24
Peak memory 225876 kb
Host smart-40ebdb8a-3832-43f9-a589-a7c6e349d16e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516649472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1516649472
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.1558827235
Short name T655
Test name
Test status
Simulation time 114073564 ps
CPU time 2.27 seconds
Started Jun 28 06:39:04 PM PDT 24
Finished Jun 28 06:39:34 PM PDT 24
Peak memory 218008 kb
Host smart-41fde77f-7649-49da-8232-392fb59624b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558827235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.1
558827235
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2554646748
Short name T240
Test name
Test status
Simulation time 6782792292 ps
CPU time 13.25 seconds
Started Jun 28 06:38:48 PM PDT 24
Finished Jun 28 06:39:36 PM PDT 24
Peak memory 219156 kb
Host smart-069c242c-7f49-4f88-923b-dee163eee784
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554646748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2554646748
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3087855553
Short name T823
Test name
Test status
Simulation time 3314979435 ps
CPU time 22.42 seconds
Started Jun 28 06:39:03 PM PDT 24
Finished Jun 28 06:39:52 PM PDT 24
Peak memory 217956 kb
Host smart-98bd63b3-2add-472c-bfbf-61535f3d17bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087855553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3087855553
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.907971365
Short name T378
Test name
Test status
Simulation time 1925308145 ps
CPU time 3.6 seconds
Started Jun 28 06:38:43 PM PDT 24
Finished Jun 28 06:39:25 PM PDT 24
Peak memory 217912 kb
Host smart-47bfeac7-5e30-4e0e-8eae-f2ceadebaed8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907971365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.907971365
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3786132343
Short name T263
Test name
Test status
Simulation time 3743860901 ps
CPU time 44.58 seconds
Started Jun 28 06:38:44 PM PDT 24
Finished Jun 28 06:40:08 PM PDT 24
Peak memory 275996 kb
Host smart-d2ad3ea9-eb02-4a82-8585-03fa49e09f8a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786132343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3786132343
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3810723170
Short name T727
Test name
Test status
Simulation time 849447820 ps
CPU time 18.91 seconds
Started Jun 28 06:38:45 PM PDT 24
Finished Jun 28 06:39:42 PM PDT 24
Peak memory 250628 kb
Host smart-3f430bf0-f6fa-403f-9421-014707ba6729
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810723170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.3810723170
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.2973699332
Short name T439
Test name
Test status
Simulation time 95885699 ps
CPU time 1.66 seconds
Started Jun 28 06:38:44 PM PDT 24
Finished Jun 28 06:39:25 PM PDT 24
Peak memory 222108 kb
Host smart-ef9e7aeb-3f65-4a37-ad34-74d3eee8bbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973699332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2973699332
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.192930500
Short name T297
Test name
Test status
Simulation time 404101301 ps
CPU time 12.88 seconds
Started Jun 28 06:38:44 PM PDT 24
Finished Jun 28 06:39:36 PM PDT 24
Peak memory 214192 kb
Host smart-0437098f-13c1-407f-821e-a9970e3dcfff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192930500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.192930500
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.1347253206
Short name T815
Test name
Test status
Simulation time 2279471464 ps
CPU time 24.86 seconds
Started Jun 28 06:39:01 PM PDT 24
Finished Jun 28 06:39:53 PM PDT 24
Peak memory 218588 kb
Host smart-f379193a-b517-4b3a-9394-7cbf69a6abf2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347253206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.1347253206
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.197276049
Short name T554
Test name
Test status
Simulation time 1274541475 ps
CPU time 9.04 seconds
Started Jun 28 06:39:02 PM PDT 24
Finished Jun 28 06:39:38 PM PDT 24
Peak memory 218428 kb
Host smart-2dd3c443-b117-4f33-834e-7896ebeb4c21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197276049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.197276049
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.706989521
Short name T311
Test name
Test status
Simulation time 211155499 ps
CPU time 5.55 seconds
Started Jun 28 06:38:43 PM PDT 24
Finished Jun 28 06:39:27 PM PDT 24
Peak memory 218500 kb
Host smart-d2cd83c1-f6f5-4b7e-ac1c-4e5ab8bed5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706989521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.706989521
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1134685745
Short name T341
Test name
Test status
Simulation time 171469212 ps
CPU time 1.31 seconds
Started Jun 28 06:38:51 PM PDT 24
Finished Jun 28 06:39:26 PM PDT 24
Peak memory 217996 kb
Host smart-56d2606b-e94a-49ca-98ed-122675c378dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134685745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1134685745
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.1046061330
Short name T594
Test name
Test status
Simulation time 275043319 ps
CPU time 23.81 seconds
Started Jun 28 06:38:51 PM PDT 24
Finished Jun 28 06:39:49 PM PDT 24
Peak memory 246888 kb
Host smart-8d3d0dd8-1915-4e20-8afc-8572bfc41eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046061330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1046061330
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.3272570426
Short name T741
Test name
Test status
Simulation time 146749774 ps
CPU time 3.87 seconds
Started Jun 28 06:38:51 PM PDT 24
Finished Jun 28 06:39:29 PM PDT 24
Peak memory 226592 kb
Host smart-19ab8b44-c920-4def-a873-114b37270ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272570426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3272570426
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.1140606564
Short name T716
Test name
Test status
Simulation time 331529391 ps
CPU time 5.68 seconds
Started Jun 28 06:39:05 PM PDT 24
Finished Jun 28 06:39:37 PM PDT 24
Peak memory 223548 kb
Host smart-539ef4bf-b6d2-4e52-b1a9-b85a102a28e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140606564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.1140606564
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.2233685359
Short name T730
Test name
Test status
Simulation time 16190354035 ps
CPU time 332.06 seconds
Started Jun 28 06:39:05 PM PDT 24
Finished Jun 28 06:45:03 PM PDT 24
Peak memory 284012 kb
Host smart-a3f57811-df7c-4d60-922c-53d778afd385
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2233685359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.2233685359
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3717049520
Short name T531
Test name
Test status
Simulation time 25532910 ps
CPU time 0.84 seconds
Started Jun 28 06:38:51 PM PDT 24
Finished Jun 28 06:39:26 PM PDT 24
Peak memory 212176 kb
Host smart-ee51d201-9c2a-4961-8328-7fed07420762
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717049520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.3717049520
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%