Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109828850

1

T1

5855

T2

670182

T3

60188

auto[1]

1402228

1

T1

1386

T2

4238

T9

297

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109835515

1

T1

6647

T2

670278

T3

60188

auto[1]

1395563

1

T1

594

T2

4142

T9

1089

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7485457	1			T1	2129		T2	37930		T3	6104
auto[IdleSt]	22188486	1			T1	1271		T2	302364		T3	6233
auto[ClkMuxSt]	35946	1			T1	20		T2	371		T3	68
auto[CntIncrSt]	35670	1			T1	20		T2	371		T3	68
auto[CntProgSt]	1312525	1			T1	40		T2	22420		T3	29662
auto[TransCheckSt]	27671	1			T2	243		T3	68		T10	61
auto[TokenHashSt]	47231568	1			T2	2274		T3	5889		T10	1786
auto[FlashRmaSt]	28467	1			T2	201		T10	22		T5	156
auto[TokenCheck0St]	12795	1			T2	94		T10	22		T5	91
auto[TokenCheck1St]	9500	1			T2	57		T10	13		T5	75
auto[TransProgSt]	382330	1			T2	4692		T10	26		T5	148
auto[PostTransSt]	13072173	1			T1	1245		T2	241103		T3	12096
auto[ScrapSt]	134347	1			T2	506		T5	45		T28	112
auto[EscalateSt]	7028405	1			T1	2516		T2	41908		T9	2015
auto[InvalidSt]	12243814	1			T2	19886		T5	139624		T12	569

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1924	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12243814	1			T2	19886		T5	139624		T12	569
EscalateSt	7028405	1			T1	2516		T2	41908		T9	2015
ScrapSt	134347	1			T2	506		T5	45		T28	112
PostTransSt	13072173	1			T1	1245		T2	241103		T3	12096
TransProgSt	382330	1			T2	4692		T10	26		T5	148
TokenCheck1St	9500	1			T2	57		T10	13		T5	75
TokenCheck0St	12795	1			T2	94		T10	22		T5	91
FlashRmaSt	28467	1			T2	201		T10	22		T5	156
TokenHashSt	47231568	1			T2	2274		T3	5889		T10	1786
TransCheckSt	27671	1			T2	243		T3	68		T10	61
CntProgSt	1312525	1			T1	40		T2	22420		T3	29662
CntIncrSt	35670	1			T1	20		T2	371		T3	68
ClkMuxSt	35946	1			T1	20		T2	371		T3	68
IdleSt	22188486	1			T1	1271		T2	302364		T3	6233
ResetSt	7485457	1			T1	2129		T2	37930		T3	6104
arcs[ResetSt=>IdleSt]	54019	1			T1	21		T2	390		T3	69
arcs[IdleSt=>ScrapSt]	269	1			T2	1		T5	1		T28	3
arcs[IdleSt=>ClkMuxSt]	35732	1			T1	20		T2	371		T3	68
arcs[ClkMuxSt=>CntIncrSt]	35670	1			T1	20		T2	371		T3	68
arcs[CntIncrSt=>PostTransSt]	1863	1			T2	51		T10	14		T5	21
arcs[CntIncrSt=>CntProgSt]	33750	1			T1	20		T2	320		T3	68
arcs[CntProgSt=>PostTransSt]	4982	1			T1	20		T2	77		T9	14
arcs[CntProgSt=>TransCheckSt]	27671	1			T2	243		T3	68		T10	61
arcs[TransCheckSt=>PostTransSt]	3657	1			T2	38		T10	7		T5	21
arcs[TransCheckSt=>TokenHashSt]	23890	1			T2	205		T3	68		T10	54
arcs[TokenHashSt=>PostTransSt]	10276	1			T2	111		T3	68		T10	32
arcs[TokenHashSt=>FlashRmaSt]	12898	1			T2	94		T10	22		T5	91
arcs[FlashRmaSt=>TokenCheck0St]	12795	1			T2	94		T10	22		T5	91
arcs[TokenCheck0St=>PostTransSt]	3261	1			T2	37		T10	9		T5	16
arcs[TokenCheck0St=>TokenCheck1St]	9500	1			T2	57		T10	13		T5	75
arcs[TokenCheck1St=>PostTransSt]	664	1			T2	2		T5	1		T31	1
arcs[TransProgSt=>PostTransSt]	7985	1			T2	55		T10	13		T5	74
arcs[IdleSt=>EscalateSt]	215	1			T51	6		T49	6		T52	4
arcs[ClkMuxSt=>EscalateSt]	62	1			T48	2		T49	1		T50	1
arcs[CntIncrSt=>EscalateSt]	57	1			T48	1		T51	1		T49	2
arcs[CntProgSt=>EscalateSt]	1097	1			T48	27		T51	16		T49	23
arcs[TransCheckSt=>EscalateSt]	124	1			T51	7		T50	1		T56	8
arcs[TokenHashSt=>EscalateSt]	716	1			T48	8		T51	12		T55	1
arcs[FlashRmaSt=>EscalateSt]	103	1			T48	4		T51	1		T49	4
arcs[TokenCheck0St=>EscalateSt]	34	1			T51	1		T50	2		T52	1
arcs[TokenCheck1St=>EscalateSt]	160	1			T48	6		T51	2		T49	1
arcs[TransProgSt=>EscalateSt]	691	1			T48	22		T51	15		T49	16
arcs[PostTransSt=>EscalateSt]	5266	1			T1	20		T2	77		T9	14
arcs[InvalidSt=>EscalateSt]	13775	1			T2	8		T5	333		T12	3

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7485297	1			T1	2129		T2	37930		T3	6104
auto[0]	auto[IdleSt]	22188352	1			T1	1271		T2	302364		T3	6233
auto[0]	auto[ClkMuxSt]	35904	1			T1	20		T2	371		T3	68
auto[0]	auto[CntIncrSt]	35630	1			T1	20		T2	371		T3	68
auto[0]	auto[CntProgSt]	1311779	1			T1	40		T2	22420		T3	29662
auto[0]	auto[TransCheckSt]	27590	1			T2	243		T3	68		T10	61
auto[0]	auto[TokenHashSt]	47231116	1			T2	2274		T3	5889		T10	1786
auto[0]	auto[FlashRmaSt]	28397	1			T2	201		T10	22		T5	156
auto[0]	auto[TokenCheck0St]	12772	1			T2	94		T10	22		T5	91
auto[0]	auto[TokenCheck1St]	9389	1			T2	57		T10	13		T5	75
auto[0]	auto[TransProgSt]	381853	1			T2	4692		T10	26		T5	148
auto[0]	auto[PostTransSt]	13069529	1			T1	1231		T2	241063		T3	12096
auto[0]	auto[ScrapSt]	134303	1			T2	506		T5	45		T28	112
auto[0]	auto[EscalateSt]	5638088	1			T1	1144		T2	37713		T9	1721
auto[0]	auto[InvalidSt]	12236927	1			T2	19883		T5	139456		T12	568
auto[1]	auto[ResetSt]	160	1			T48	1		T51	2		T49	5
auto[1]	auto[IdleSt]	134	1			T51	4		T49	5		T56	6
auto[1]	auto[ClkMuxSt]	42	1			T49	1		T50	1		T52	1
auto[1]	auto[CntIncrSt]	40	1			T48	1		T49	2		T50	3
auto[1]	auto[CntProgSt]	746	1			T48	17		T51	10		T49	15
auto[1]	auto[TransCheckSt]	81	1			T51	3		T56	3		T200	1
auto[1]	auto[TokenHashSt]	452	1			T48	6		T51	6		T55	1
auto[1]	auto[FlashRmaSt]	70	1			T48	1		T51	1		T49	4
auto[1]	auto[TokenCheck0St]	23	1			T51	1		T52	1		T201	2
auto[1]	auto[TokenCheck1St]	111	1			T48	3		T51	2		T49	1
auto[1]	auto[TransProgSt]	477	1			T48	18		T51	10		T49	12
auto[1]	auto[PostTransSt]	2644	1			T1	14		T2	40		T9	3
auto[1]	auto[ScrapSt]	44	1			T49	2		T50	1		T56	1
auto[1]	auto[EscalateSt]	1390317	1			T1	1372		T2	4195		T9	294
auto[1]	auto[InvalidSt]	6887	1			T2	3		T5	168		T12	1

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7485281	1			T1	2129		T2	37930		T3	6104
auto[0]	auto[IdleSt]	22188351	1			T1	1271		T2	302364		T3	6233
auto[0]	auto[ClkMuxSt]	35907	1			T1	20		T2	371		T3	68
auto[0]	auto[CntIncrSt]	35639	1			T1	20		T2	371		T3	68
auto[0]	auto[CntProgSt]	1311817	1			T1	40		T2	22420		T3	29662
auto[0]	auto[TransCheckSt]	27587	1			T2	243		T3	68		T10	61
auto[0]	auto[TokenHashSt]	47231094	1			T2	2274		T3	5889		T10	1786
auto[0]	auto[FlashRmaSt]	28402	1			T2	201		T10	22		T5	156
auto[0]	auto[TokenCheck0St]	12774	1			T2	94		T10	22		T5	91
auto[0]	auto[TokenCheck1St]	9403	1			T2	57		T10	13		T5	75
auto[0]	auto[TransProgSt]	381887	1			T2	4692		T10	26		T5	148
auto[0]	auto[PostTransSt]	13069481	1			T1	1239		T2	241066		T3	12096
auto[0]	auto[ScrapSt]	134308	1			T2	506		T5	45		T28	112
auto[0]	auto[EscalateSt]	5644734	1			T1	1928		T2	37808		T9	937
auto[0]	auto[InvalidSt]	12236926	1			T2	19881		T5	139459		T12	567
auto[1]	auto[ResetSt]	176	1			T48	5		T51	3		T49	4
auto[1]	auto[IdleSt]	135	1			T51	2		T49	2		T52	4
auto[1]	auto[ClkMuxSt]	39	1			T48	2		T49	1		T50	1
auto[1]	auto[CntIncrSt]	31	1			T51	1		T50	4		T52	1
auto[1]	auto[CntProgSt]	708	1			T48	17		T51	10		T49	16
auto[1]	auto[TransCheckSt]	84	1			T51	4		T50	1		T56	6
auto[1]	auto[TokenHashSt]	474	1			T48	4		T51	8		T49	11
auto[1]	auto[FlashRmaSt]	65	1			T48	3		T51	1		T49	1
auto[1]	auto[TokenCheck0St]	21	1			T51	1		T50	2		T52	1
auto[1]	auto[TokenCheck1St]	97	1			T48	4		T49	1		T50	2
auto[1]	auto[TransProgSt]	443	1			T48	14		T51	9		T49	9
auto[1]	auto[PostTransSt]	2692	1			T1	6		T2	37		T9	11
auto[1]	auto[ScrapSt]	39	1			T49	1		T50	1		T52	1
auto[1]	auto[EscalateSt]	1383671	1			T1	588		T2	4100		T9	1078
auto[1]	auto[InvalidSt]	6888	1			T2	5		T5	165		T12	2