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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.98 97.92 96.12 93.38 97.62 98.52 99.00 96.29


Total test records in report: 1000
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T811 /workspace/coverage/default/24.lc_ctrl_stress_all.760102256 Jun 29 05:49:29 PM PDT 24 Jun 29 05:50:45 PM PDT 24 1728266447 ps
T812 /workspace/coverage/default/49.lc_ctrl_state_failure.1304482020 Jun 29 05:51:35 PM PDT 24 Jun 29 05:51:50 PM PDT 24 582357537 ps
T813 /workspace/coverage/default/1.lc_ctrl_sec_token_mux.3079880080 Jun 29 05:45:14 PM PDT 24 Jun 29 05:45:22 PM PDT 24 252406653 ps
T814 /workspace/coverage/default/16.lc_ctrl_smoke.1367884990 Jun 29 05:48:21 PM PDT 24 Jun 29 05:48:23 PM PDT 24 143224309 ps
T815 /workspace/coverage/default/46.lc_ctrl_prog_failure.1713156715 Jun 29 05:51:23 PM PDT 24 Jun 29 05:51:25 PM PDT 24 133831090 ps
T816 /workspace/coverage/default/4.lc_ctrl_jtag_errors.2026599750 Jun 29 05:46:09 PM PDT 24 Jun 29 05:46:47 PM PDT 24 2295214571 ps
T197 /workspace/coverage/default/3.lc_ctrl_claim_transition_if.1403723137 Jun 29 05:45:52 PM PDT 24 Jun 29 05:45:53 PM PDT 24 37852388 ps
T817 /workspace/coverage/default/28.lc_ctrl_jtag_access.1361855906 Jun 29 05:49:48 PM PDT 24 Jun 29 05:49:57 PM PDT 24 3059195658 ps
T818 /workspace/coverage/default/8.lc_ctrl_jtag_access.1822884428 Jun 29 05:47:07 PM PDT 24 Jun 29 05:47:13 PM PDT 24 778013916 ps
T819 /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3316784484 Jun 29 05:47:08 PM PDT 24 Jun 29 05:47:17 PM PDT 24 563007330 ps
T820 /workspace/coverage/default/1.lc_ctrl_jtag_priority.2886362555 Jun 29 05:45:15 PM PDT 24 Jun 29 05:45:31 PM PDT 24 2644242264 ps
T821 /workspace/coverage/default/6.lc_ctrl_stress_all.2601493218 Jun 29 05:46:42 PM PDT 24 Jun 29 05:48:18 PM PDT 24 9003896207 ps
T822 /workspace/coverage/default/4.lc_ctrl_stress_all.477749958 Jun 29 05:46:08 PM PDT 24 Jun 29 05:47:12 PM PDT 24 8531539975 ps
T167 /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.78115108 Jun 29 05:49:21 PM PDT 24 Jun 29 05:55:15 PM PDT 24 9250515297 ps
T823 /workspace/coverage/default/24.lc_ctrl_state_failure.3792961033 Jun 29 05:49:29 PM PDT 24 Jun 29 05:50:00 PM PDT 24 249607537 ps
T824 /workspace/coverage/default/17.lc_ctrl_state_failure.2422866301 Jun 29 05:48:29 PM PDT 24 Jun 29 05:48:58 PM PDT 24 738170713 ps
T825 /workspace/coverage/default/28.lc_ctrl_alert_test.675940163 Jun 29 05:49:52 PM PDT 24 Jun 29 05:49:53 PM PDT 24 45799792 ps
T826 /workspace/coverage/default/49.lc_ctrl_jtag_access.1176565149 Jun 29 05:51:32 PM PDT 24 Jun 29 05:51:45 PM PDT 24 1963352165 ps
T827 /workspace/coverage/default/30.lc_ctrl_sec_token_digest.3981426110 Jun 29 05:50:01 PM PDT 24 Jun 29 05:50:15 PM PDT 24 572108195 ps
T828 /workspace/coverage/default/9.lc_ctrl_jtag_priority.2464687067 Jun 29 05:47:22 PM PDT 24 Jun 29 05:47:27 PM PDT 24 978642478 ps
T829 /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1403359999 Jun 29 05:46:10 PM PDT 24 Jun 29 05:46:21 PM PDT 24 1009643716 ps
T830 /workspace/coverage/default/39.lc_ctrl_state_failure.2206152965 Jun 29 05:50:45 PM PDT 24 Jun 29 05:51:14 PM PDT 24 437958958 ps
T831 /workspace/coverage/default/13.lc_ctrl_state_failure.3606493434 Jun 29 05:47:56 PM PDT 24 Jun 29 05:48:17 PM PDT 24 767926166 ps
T832 /workspace/coverage/default/13.lc_ctrl_stress_all.2083575215 Jun 29 05:48:04 PM PDT 24 Jun 29 05:49:18 PM PDT 24 2992798843 ps
T833 /workspace/coverage/default/6.lc_ctrl_errors.3194694290 Jun 29 05:46:31 PM PDT 24 Jun 29 05:46:47 PM PDT 24 404862023 ps
T834 /workspace/coverage/default/34.lc_ctrl_security_escalation.3257864411 Jun 29 05:50:18 PM PDT 24 Jun 29 05:50:26 PM PDT 24 338080679 ps
T835 /workspace/coverage/default/48.lc_ctrl_state_failure.3828251194 Jun 29 05:51:26 PM PDT 24 Jun 29 05:51:53 PM PDT 24 290325281 ps
T836 /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.683256372 Jun 29 05:48:38 PM PDT 24 Jun 29 05:49:19 PM PDT 24 5740006930 ps
T837 /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2065741256 Jun 29 05:45:14 PM PDT 24 Jun 29 05:45:50 PM PDT 24 2539289101 ps
T838 /workspace/coverage/default/29.lc_ctrl_jtag_access.2932154712 Jun 29 05:49:51 PM PDT 24 Jun 29 05:49:54 PM PDT 24 750480420 ps
T839 /workspace/coverage/default/24.lc_ctrl_alert_test.172789176 Jun 29 05:49:29 PM PDT 24 Jun 29 05:49:31 PM PDT 24 19855352 ps
T840 /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1951576786 Jun 29 05:51:24 PM PDT 24 Jun 29 05:51:25 PM PDT 24 13829590 ps
T841 /workspace/coverage/default/0.lc_ctrl_smoke.312507687 Jun 29 05:44:33 PM PDT 24 Jun 29 05:44:37 PM PDT 24 42349770 ps
T842 /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3263237567 Jun 29 05:45:38 PM PDT 24 Jun 29 05:45:51 PM PDT 24 1125488952 ps
T843 /workspace/coverage/default/27.lc_ctrl_sec_token_digest.3366103683 Jun 29 05:49:44 PM PDT 24 Jun 29 05:50:00 PM PDT 24 1672614895 ps
T844 /workspace/coverage/default/42.lc_ctrl_errors.3340653812 Jun 29 05:51:00 PM PDT 24 Jun 29 05:51:15 PM PDT 24 518900688 ps
T845 /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3182872647 Jun 29 05:45:13 PM PDT 24 Jun 29 05:45:46 PM PDT 24 1571922407 ps
T846 /workspace/coverage/default/24.lc_ctrl_sec_mubi.2408785757 Jun 29 05:49:28 PM PDT 24 Jun 29 05:49:43 PM PDT 24 3671568140 ps
T847 /workspace/coverage/default/32.lc_ctrl_errors.3334074887 Jun 29 05:50:11 PM PDT 24 Jun 29 05:50:21 PM PDT 24 1335889297 ps
T848 /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3373372339 Jun 29 05:48:38 PM PDT 24 Jun 29 05:48:48 PM PDT 24 357642579 ps
T849 /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3086048718 Jun 29 05:50:28 PM PDT 24 Jun 29 05:50:45 PM PDT 24 689184801 ps
T112 /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.3370817060 Jun 29 05:51:06 PM PDT 24 Jun 29 06:00:10 PM PDT 24 85524001985 ps
T850 /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.3348877784 Jun 29 05:48:37 PM PDT 24 Jun 29 05:55:43 PM PDT 24 86400378714 ps
T851 /workspace/coverage/default/29.lc_ctrl_sec_mubi.352582589 Jun 29 05:49:52 PM PDT 24 Jun 29 05:50:08 PM PDT 24 1223956493 ps
T852 /workspace/coverage/default/26.lc_ctrl_state_post_trans.2851414315 Jun 29 05:49:38 PM PDT 24 Jun 29 05:49:41 PM PDT 24 218234215 ps
T853 /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3821574616 Jun 29 05:47:55 PM PDT 24 Jun 29 05:47:56 PM PDT 24 99287586 ps
T854 /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1078345470 Jun 29 05:46:27 PM PDT 24 Jun 29 05:46:31 PM PDT 24 1345888873 ps
T198 /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1529576472 Jun 29 05:46:00 PM PDT 24 Jun 29 05:46:02 PM PDT 24 11254554 ps
T855 /workspace/coverage/default/5.lc_ctrl_sec_token_digest.1140651283 Jun 29 05:46:41 PM PDT 24 Jun 29 05:46:54 PM PDT 24 1038410742 ps
T856 /workspace/coverage/default/33.lc_ctrl_errors.2558123470 Jun 29 05:50:08 PM PDT 24 Jun 29 05:50:18 PM PDT 24 385807964 ps
T857 /workspace/coverage/default/18.lc_ctrl_errors.3764867883 Jun 29 05:48:48 PM PDT 24 Jun 29 05:48:58 PM PDT 24 413392427 ps
T858 /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3128921772 Jun 29 05:47:41 PM PDT 24 Jun 29 05:47:47 PM PDT 24 1738579084 ps
T859 /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.743848070 Jun 29 05:45:50 PM PDT 24 Jun 29 05:45:51 PM PDT 24 34226934 ps
T860 /workspace/coverage/default/22.lc_ctrl_security_escalation.337840731 Jun 29 05:49:13 PM PDT 24 Jun 29 05:49:22 PM PDT 24 440747834 ps
T861 /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3346752403 Jun 29 05:46:52 PM PDT 24 Jun 29 05:46:53 PM PDT 24 12749086 ps
T862 /workspace/coverage/default/37.lc_ctrl_security_escalation.546348825 Jun 29 05:50:35 PM PDT 24 Jun 29 05:50:43 PM PDT 24 689682595 ps
T863 /workspace/coverage/default/2.lc_ctrl_jtag_smoke.3122526844 Jun 29 05:45:29 PM PDT 24 Jun 29 05:45:37 PM PDT 24 1055461216 ps
T864 /workspace/coverage/default/44.lc_ctrl_state_post_trans.193276000 Jun 29 05:51:07 PM PDT 24 Jun 29 05:51:16 PM PDT 24 1335001343 ps
T865 /workspace/coverage/default/14.lc_ctrl_stress_all.3400848998 Jun 29 05:48:15 PM PDT 24 Jun 29 05:48:59 PM PDT 24 12451916246 ps
T866 /workspace/coverage/default/15.lc_ctrl_sec_token_mux.3667377430 Jun 29 05:48:21 PM PDT 24 Jun 29 05:48:34 PM PDT 24 366669572 ps
T867 /workspace/coverage/default/45.lc_ctrl_errors.1580988481 Jun 29 05:51:12 PM PDT 24 Jun 29 05:51:29 PM PDT 24 354320537 ps
T868 /workspace/coverage/default/28.lc_ctrl_security_escalation.3379263673 Jun 29 05:49:47 PM PDT 24 Jun 29 05:49:56 PM PDT 24 560138116 ps
T869 /workspace/coverage/default/13.lc_ctrl_errors.3707899875 Jun 29 05:47:56 PM PDT 24 Jun 29 05:48:08 PM PDT 24 1298532121 ps
T870 /workspace/coverage/default/37.lc_ctrl_errors.1678518569 Jun 29 05:50:37 PM PDT 24 Jun 29 05:51:00 PM PDT 24 499572281 ps
T871 /workspace/coverage/default/11.lc_ctrl_security_escalation.1519584160 Jun 29 05:47:40 PM PDT 24 Jun 29 05:47:49 PM PDT 24 1167777075 ps
T113 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.4255016647 Jun 29 06:31:03 PM PDT 24 Jun 29 06:31:09 PM PDT 24 395931560 ps
T130 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.154719673 Jun 29 06:30:48 PM PDT 24 Jun 29 06:30:50 PM PDT 24 91819977 ps
T117 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.858498702 Jun 29 06:30:55 PM PDT 24 Jun 29 06:30:58 PM PDT 24 178613277 ps
T119 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1611838132 Jun 29 06:31:09 PM PDT 24 Jun 29 06:31:11 PM PDT 24 19646101 ps
T122 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1472912103 Jun 29 06:30:55 PM PDT 24 Jun 29 06:30:57 PM PDT 24 51763513 ps
T114 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3387110765 Jun 29 06:31:04 PM PDT 24 Jun 29 06:31:08 PM PDT 24 130986509 ps
T148 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.712655378 Jun 29 06:30:56 PM PDT 24 Jun 29 06:30:59 PM PDT 24 127050106 ps
T115 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.287866108 Jun 29 06:31:15 PM PDT 24 Jun 29 06:31:18 PM PDT 24 283397391 ps
T121 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1152595893 Jun 29 06:31:18 PM PDT 24 Jun 29 06:31:21 PM PDT 24 30516967 ps
T155 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2423022102 Jun 29 06:30:53 PM PDT 24 Jun 29 06:30:55 PM PDT 24 37599454 ps
T156 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3751916411 Jun 29 06:31:07 PM PDT 24 Jun 29 06:31:09 PM PDT 24 84380698 ps
T183 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2306474271 Jun 29 06:31:20 PM PDT 24 Jun 29 06:31:22 PM PDT 24 149845247 ps
T118 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3273545879 Jun 29 06:31:19 PM PDT 24 Jun 29 06:31:23 PM PDT 24 144558498 ps
T149 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.717014056 Jun 29 06:31:04 PM PDT 24 Jun 29 06:31:29 PM PDT 24 5943645181 ps
T120 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3390690258 Jun 29 06:31:21 PM PDT 24 Jun 29 06:31:25 PM PDT 24 208474452 ps
T145 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2424725429 Jun 29 06:30:50 PM PDT 24 Jun 29 06:31:11 PM PDT 24 3490983572 ps
T157 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3983432330 Jun 29 06:31:09 PM PDT 24 Jun 29 06:31:11 PM PDT 24 57617890 ps
T184 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3976064461 Jun 29 06:31:03 PM PDT 24 Jun 29 06:31:04 PM PDT 24 14895689 ps
T872 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1542716923 Jun 29 06:30:50 PM PDT 24 Jun 29 06:30:54 PM PDT 24 105744063 ps
T873 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3934861268 Jun 29 06:30:50 PM PDT 24 Jun 29 06:30:54 PM PDT 24 257085384 ps
T185 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3444007388 Jun 29 06:31:20 PM PDT 24 Jun 29 06:31:23 PM PDT 24 21840231 ps
T186 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2125321326 Jun 29 06:31:08 PM PDT 24 Jun 29 06:31:10 PM PDT 24 49033026 ps
T132 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.4225237823 Jun 29 06:31:03 PM PDT 24 Jun 29 06:31:05 PM PDT 24 50739583 ps
T168 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3926915004 Jun 29 06:30:57 PM PDT 24 Jun 29 06:31:00 PM PDT 24 174462492 ps
T129 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.531892331 Jun 29 06:30:57 PM PDT 24 Jun 29 06:31:01 PM PDT 24 191879762 ps
T199 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2096849060 Jun 29 06:31:01 PM PDT 24 Jun 29 06:31:04 PM PDT 24 63885805 ps
T874 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.319724115 Jun 29 06:31:09 PM PDT 24 Jun 29 06:31:13 PM PDT 24 372940938 ps
T187 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3038783653 Jun 29 06:30:50 PM PDT 24 Jun 29 06:30:53 PM PDT 24 42581072 ps
T875 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.378562125 Jun 29 06:30:54 PM PDT 24 Jun 29 06:30:56 PM PDT 24 425407650 ps
T174 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1792069173 Jun 29 06:31:11 PM PDT 24 Jun 29 06:31:12 PM PDT 24 24195747 ps
T876 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1841322532 Jun 29 06:31:01 PM PDT 24 Jun 29 06:31:03 PM PDT 24 180668972 ps
T188 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4290029316 Jun 29 06:30:48 PM PDT 24 Jun 29 06:30:50 PM PDT 24 28571552 ps
T124 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1340511192 Jun 29 06:31:12 PM PDT 24 Jun 29 06:31:18 PM PDT 24 202942101 ps
T877 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.286573456 Jun 29 06:30:55 PM PDT 24 Jun 29 06:30:58 PM PDT 24 148224022 ps
T146 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3298886895 Jun 29 06:30:47 PM PDT 24 Jun 29 06:30:48 PM PDT 24 149913860 ps
T878 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3197893493 Jun 29 06:30:56 PM PDT 24 Jun 29 06:30:59 PM PDT 24 49941602 ps
T189 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.545054523 Jun 29 06:31:18 PM PDT 24 Jun 29 06:31:21 PM PDT 24 188412360 ps
T144 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2223143580 Jun 29 06:31:03 PM PDT 24 Jun 29 06:31:06 PM PDT 24 55695653 ps
T879 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2718002989 Jun 29 06:31:19 PM PDT 24 Jun 29 06:31:22 PM PDT 24 60258219 ps
T880 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.484444625 Jun 29 06:31:12 PM PDT 24 Jun 29 06:31:13 PM PDT 24 40000306 ps
T881 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2264458225 Jun 29 06:30:50 PM PDT 24 Jun 29 06:30:52 PM PDT 24 37404607 ps
T142 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3956409967 Jun 29 06:31:10 PM PDT 24 Jun 29 06:31:14 PM PDT 24 338512068 ps
T882 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3266570945 Jun 29 06:31:05 PM PDT 24 Jun 29 06:31:06 PM PDT 24 24046618 ps
T883 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3871423556 Jun 29 06:30:56 PM PDT 24 Jun 29 06:30:57 PM PDT 24 16329573 ps
T884 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1848785432 Jun 29 06:31:03 PM PDT 24 Jun 29 06:31:27 PM PDT 24 1240161496 ps
T125 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3047281547 Jun 29 06:30:55 PM PDT 24 Jun 29 06:30:58 PM PDT 24 114042563 ps
T885 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.365521390 Jun 29 06:31:08 PM PDT 24 Jun 29 06:31:10 PM PDT 24 24937519 ps
T175 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3185550880 Jun 29 06:30:56 PM PDT 24 Jun 29 06:30:57 PM PDT 24 15216125 ps
T147 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1929137803 Jun 29 06:31:00 PM PDT 24 Jun 29 06:31:02 PM PDT 24 205261725 ps
T176 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.85690991 Jun 29 06:31:19 PM PDT 24 Jun 29 06:31:21 PM PDT 24 12738481 ps
T126 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2630947866 Jun 29 06:31:09 PM PDT 24 Jun 29 06:31:11 PM PDT 24 68429283 ps
T886 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1322452028 Jun 29 06:30:48 PM PDT 24 Jun 29 06:30:52 PM PDT 24 77016740 ps
T887 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2733249558 Jun 29 06:30:49 PM PDT 24 Jun 29 06:30:51 PM PDT 24 81119164 ps
T888 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1705439442 Jun 29 06:31:17 PM PDT 24 Jun 29 06:31:18 PM PDT 24 14923237 ps
T137 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1695880736 Jun 29 06:31:21 PM PDT 24 Jun 29 06:31:24 PM PDT 24 125605474 ps
T889 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1459838678 Jun 29 06:30:48 PM PDT 24 Jun 29 06:30:54 PM PDT 24 2344438185 ps
T890 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1230424769 Jun 29 06:31:19 PM PDT 24 Jun 29 06:31:24 PM PDT 24 112917451 ps
T891 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1706015072 Jun 29 06:31:04 PM PDT 24 Jun 29 06:31:06 PM PDT 24 83059875 ps
T892 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2656590488 Jun 29 06:31:14 PM PDT 24 Jun 29 06:31:16 PM PDT 24 49203268 ps
T127 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2217077984 Jun 29 06:31:10 PM PDT 24 Jun 29 06:31:13 PM PDT 24 322051329 ps
T893 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3955183213 Jun 29 06:31:11 PM PDT 24 Jun 29 06:31:13 PM PDT 24 86296821 ps
T894 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.811276553 Jun 29 06:30:49 PM PDT 24 Jun 29 06:30:51 PM PDT 24 23343608 ps
T895 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.162083279 Jun 29 06:31:00 PM PDT 24 Jun 29 06:31:02 PM PDT 24 29058077 ps
T896 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.107905314 Jun 29 06:31:16 PM PDT 24 Jun 29 06:31:19 PM PDT 24 30756002 ps
T897 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.722299732 Jun 29 06:31:03 PM PDT 24 Jun 29 06:31:06 PM PDT 24 88801242 ps
T898 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3464606907 Jun 29 06:30:59 PM PDT 24 Jun 29 06:31:01 PM PDT 24 79372838 ps
T899 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2191747813 Jun 29 06:30:56 PM PDT 24 Jun 29 06:31:06 PM PDT 24 368692275 ps
T900 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2519573311 Jun 29 06:30:59 PM PDT 24 Jun 29 06:31:04 PM PDT 24 395288612 ps
T901 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.327621813 Jun 29 06:31:11 PM PDT 24 Jun 29 06:31:14 PM PDT 24 71420207 ps
T902 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.960913410 Jun 29 06:30:57 PM PDT 24 Jun 29 06:31:00 PM PDT 24 291069456 ps
T177 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2757328262 Jun 29 06:31:08 PM PDT 24 Jun 29 06:31:09 PM PDT 24 12215558 ps
T903 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2637218249 Jun 29 06:31:01 PM PDT 24 Jun 29 06:31:02 PM PDT 24 29237629 ps
T904 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.4118764089 Jun 29 06:31:17 PM PDT 24 Jun 29 06:31:19 PM PDT 24 49833771 ps
T905 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3633930348 Jun 29 06:30:51 PM PDT 24 Jun 29 06:30:53 PM PDT 24 99632498 ps
T906 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.627343553 Jun 29 06:30:56 PM PDT 24 Jun 29 06:30:59 PM PDT 24 219137982 ps
T134 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3950311073 Jun 29 06:31:10 PM PDT 24 Jun 29 06:31:12 PM PDT 24 105338532 ps
T907 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3269348613 Jun 29 06:31:08 PM PDT 24 Jun 29 06:31:10 PM PDT 24 73005939 ps
T908 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2647682700 Jun 29 06:31:26 PM PDT 24 Jun 29 06:31:28 PM PDT 24 16659042 ps
T909 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3272142136 Jun 29 06:31:16 PM PDT 24 Jun 29 06:31:18 PM PDT 24 140243641 ps
T910 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2621383778 Jun 29 06:30:59 PM PDT 24 Jun 29 06:31:06 PM PDT 24 567556427 ps
T911 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2653631813 Jun 29 06:30:49 PM PDT 24 Jun 29 06:30:59 PM PDT 24 3740706661 ps
T912 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.4232118084 Jun 29 06:31:04 PM PDT 24 Jun 29 06:31:07 PM PDT 24 55475709 ps
T143 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3804655144 Jun 29 06:31:19 PM PDT 24 Jun 29 06:31:23 PM PDT 24 189257573 ps
T913 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1755274342 Jun 29 06:30:51 PM PDT 24 Jun 29 06:30:53 PM PDT 24 14130388 ps
T914 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2745879944 Jun 29 06:31:02 PM PDT 24 Jun 29 06:31:08 PM PDT 24 510648067 ps
T915 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2405182968 Jun 29 06:30:59 PM PDT 24 Jun 29 06:31:02 PM PDT 24 269591351 ps
T916 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3814574643 Jun 29 06:31:01 PM PDT 24 Jun 29 06:31:05 PM PDT 24 192942962 ps
T917 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2196902623 Jun 29 06:30:51 PM PDT 24 Jun 29 06:31:04 PM PDT 24 1676939055 ps
T918 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.599796447 Jun 29 06:30:59 PM PDT 24 Jun 29 06:31:01 PM PDT 24 249516569 ps
T919 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3463906058 Jun 29 06:31:01 PM PDT 24 Jun 29 06:31:02 PM PDT 24 12681324 ps
T920 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2150453380 Jun 29 06:30:56 PM PDT 24 Jun 29 06:30:58 PM PDT 24 18535421 ps
T921 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1837663189 Jun 29 06:31:04 PM PDT 24 Jun 29 06:31:08 PM PDT 24 804160853 ps
T178 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.855899987 Jun 29 06:30:57 PM PDT 24 Jun 29 06:31:00 PM PDT 24 38459901 ps
T922 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1488061591 Jun 29 06:30:54 PM PDT 24 Jun 29 06:30:56 PM PDT 24 56646995 ps
T923 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1982086456 Jun 29 06:31:02 PM PDT 24 Jun 29 06:31:03 PM PDT 24 29337652 ps
T924 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.181637207 Jun 29 06:30:46 PM PDT 24 Jun 29 06:30:47 PM PDT 24 22463019 ps
T925 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3492509082 Jun 29 06:30:50 PM PDT 24 Jun 29 06:30:52 PM PDT 24 191108113 ps
T926 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.415414002 Jun 29 06:31:08 PM PDT 24 Jun 29 06:31:44 PM PDT 24 6177366368 ps
T139 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3355690189 Jun 29 06:31:12 PM PDT 24 Jun 29 06:31:15 PM PDT 24 76756454 ps
T927 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1695836751 Jun 29 06:31:18 PM PDT 24 Jun 29 06:31:20 PM PDT 24 29247076 ps
T928 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2428106058 Jun 29 06:31:00 PM PDT 24 Jun 29 06:31:02 PM PDT 24 98903649 ps
T929 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1197308772 Jun 29 06:30:47 PM PDT 24 Jun 29 06:30:49 PM PDT 24 45363887 ps
T930 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3437709181 Jun 29 06:30:55 PM PDT 24 Jun 29 06:30:59 PM PDT 24 94032005 ps
T931 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.749372384 Jun 29 06:31:21 PM PDT 24 Jun 29 06:31:24 PM PDT 24 371844287 ps
T932 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.4016767133 Jun 29 06:31:17 PM PDT 24 Jun 29 06:31:19 PM PDT 24 48977731 ps
T933 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2410452992 Jun 29 06:31:07 PM PDT 24 Jun 29 06:31:09 PM PDT 24 78446442 ps
T934 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1232884726 Jun 29 06:31:04 PM PDT 24 Jun 29 06:31:07 PM PDT 24 80272586 ps
T935 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.182442347 Jun 29 06:30:59 PM PDT 24 Jun 29 06:31:15 PM PDT 24 2769563831 ps
T936 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2173945479 Jun 29 06:31:00 PM PDT 24 Jun 29 06:31:02 PM PDT 24 55155215 ps
T937 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2551337397 Jun 29 06:31:03 PM PDT 24 Jun 29 06:31:04 PM PDT 24 77210217 ps
T133 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2709427033 Jun 29 06:31:05 PM PDT 24 Jun 29 06:31:08 PM PDT 24 126861962 ps
T938 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.496911452 Jun 29 06:31:03 PM PDT 24 Jun 29 06:31:06 PM PDT 24 46866119 ps
T939 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2666344974 Jun 29 06:31:15 PM PDT 24 Jun 29 06:31:18 PM PDT 24 111525935 ps
T940 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2086504395 Jun 29 06:31:03 PM PDT 24 Jun 29 06:31:04 PM PDT 24 65711324 ps
T941 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3965601566 Jun 29 06:30:50 PM PDT 24 Jun 29 06:30:52 PM PDT 24 114885996 ps
T942 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3895329348 Jun 29 06:31:18 PM PDT 24 Jun 29 06:31:22 PM PDT 24 65300666 ps
T943 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1411243750 Jun 29 06:31:17 PM PDT 24 Jun 29 06:31:19 PM PDT 24 190413408 ps
T944 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.585167271 Jun 29 06:31:02 PM PDT 24 Jun 29 06:31:06 PM PDT 24 1066294681 ps
T945 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2837233020 Jun 29 06:30:56 PM PDT 24 Jun 29 06:30:58 PM PDT 24 18067638 ps
T946 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1186867206 Jun 29 06:31:11 PM PDT 24 Jun 29 06:31:13 PM PDT 24 82096634 ps
T947 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.333755611 Jun 29 06:31:03 PM PDT 24 Jun 29 06:31:06 PM PDT 24 35372964 ps
T140 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2855530358 Jun 29 06:30:48 PM PDT 24 Jun 29 06:30:54 PM PDT 24 132210316 ps
T948 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1821575306 Jun 29 06:30:57 PM PDT 24 Jun 29 06:30:59 PM PDT 24 59509157 ps
T949 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.4182950656 Jun 29 06:30:48 PM PDT 24 Jun 29 06:30:50 PM PDT 24 34506481 ps
T950 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1282048505 Jun 29 06:31:16 PM PDT 24 Jun 29 06:31:19 PM PDT 24 48888280 ps
T951 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.995596936 Jun 29 06:30:56 PM PDT 24 Jun 29 06:30:58 PM PDT 24 19873687 ps
T952 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3928368854 Jun 29 06:30:58 PM PDT 24 Jun 29 06:31:00 PM PDT 24 96093682 ps
T953 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3390322701 Jun 29 06:31:03 PM PDT 24 Jun 29 06:31:05 PM PDT 24 25618180 ps
T954 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3234402695 Jun 29 06:31:12 PM PDT 24 Jun 29 06:31:14 PM PDT 24 20139713 ps
T955 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3560772896 Jun 29 06:30:59 PM PDT 24 Jun 29 06:31:01 PM PDT 24 107273838 ps
T179 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1678165541 Jun 29 06:31:19 PM PDT 24 Jun 29 06:31:21 PM PDT 24 15580794 ps
T956 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2500164964 Jun 29 06:31:10 PM PDT 24 Jun 29 06:31:14 PM PDT 24 328646663 ps
T957 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1634472861 Jun 29 06:30:59 PM PDT 24 Jun 29 06:31:01 PM PDT 24 14832165 ps
T958 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.519855660 Jun 29 06:31:04 PM PDT 24 Jun 29 06:31:09 PM PDT 24 199549215 ps
T959 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1039874145 Jun 29 06:30:55 PM PDT 24 Jun 29 06:30:57 PM PDT 24 94339355 ps
T960 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3618339085 Jun 29 06:31:11 PM PDT 24 Jun 29 06:31:13 PM PDT 24 91302857 ps
T961 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3765201473 Jun 29 06:31:03 PM PDT 24 Jun 29 06:31:04 PM PDT 24 56524614 ps
T962 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.370305358 Jun 29 06:31:10 PM PDT 24 Jun 29 06:31:20 PM PDT 24 368039139 ps
T963 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1788440127 Jun 29 06:31:11 PM PDT 24 Jun 29 06:31:14 PM PDT 24 167766947 ps
T964 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.577723415 Jun 29 06:31:15 PM PDT 24 Jun 29 06:31:18 PM PDT 24 72860572 ps
T965 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.23846774 Jun 29 06:30:54 PM PDT 24 Jun 29 06:31:01 PM PDT 24 3612678392 ps
T135 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.4068501341 Jun 29 06:31:18 PM PDT 24 Jun 29 06:31:23 PM PDT 24 89223975 ps
T966 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.161998478 Jun 29 06:31:04 PM PDT 24 Jun 29 06:31:06 PM PDT 24 20624374 ps
T967 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3404864550 Jun 29 06:30:58 PM PDT 24 Jun 29 06:31:00 PM PDT 24 100044145 ps
T968 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3441188255 Jun 29 06:30:47 PM PDT 24 Jun 29 06:30:49 PM PDT 24 53532170 ps
T969 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3677678790 Jun 29 06:30:56 PM PDT 24 Jun 29 06:30:58 PM PDT 24 133825343 ps
T970 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3681150909 Jun 29 06:31:12 PM PDT 24 Jun 29 06:31:16 PM PDT 24 293786883 ps
T971 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3605366765 Jun 29 06:31:15 PM PDT 24 Jun 29 06:31:17 PM PDT 24 27795414 ps
T972 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2016915408 Jun 29 06:30:49 PM PDT 24 Jun 29 06:30:50 PM PDT 24 263793900 ps
T973 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.403621152 Jun 29 06:30:50 PM PDT 24 Jun 29 06:30:52 PM PDT 24 245339163 ps
T974 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.100370622 Jun 29 06:30:54 PM PDT 24 Jun 29 06:30:59 PM PDT 24 365812496 ps
T975 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1737280473 Jun 29 06:30:53 PM PDT 24 Jun 29 06:30:54 PM PDT 24 19804306 ps
T976 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.847246510 Jun 29 06:31:17 PM PDT 24 Jun 29 06:31:19 PM PDT 24 56706947 ps
T141 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1166788518 Jun 29 06:30:58 PM PDT 24 Jun 29 06:31:02 PM PDT 24 111137037 ps
T977 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2652435673 Jun 29 06:31:09 PM PDT 24 Jun 29 06:31:13 PM PDT 24 254022636 ps
T978 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.4155293104 Jun 29 06:31:04 PM PDT 24 Jun 29 06:31:30 PM PDT 24 1925029139 ps
T180 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.524692675 Jun 29 06:31:19 PM PDT 24 Jun 29 06:31:22 PM PDT 24 189301876 ps
T979 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2610041180 Jun 29 06:31:11 PM PDT 24 Jun 29 06:31:13 PM PDT 24 46313649 ps
T980 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.412367612 Jun 29 06:31:26 PM PDT 24 Jun 29 06:31:28 PM PDT 24 44969725 ps
T981 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1704484095 Jun 29 06:31:09 PM PDT 24 Jun 29 06:31:11 PM PDT 24 45008055 ps
T982 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.321648962 Jun 29 06:31:06 PM PDT 24 Jun 29 06:31:08 PM PDT 24 24005031 ps
T983 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.410405596 Jun 29 06:30:55 PM PDT 24 Jun 29 06:30:56 PM PDT 24 434830340 ps
T984 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2142013175 Jun 29 06:31:14 PM PDT 24 Jun 29 06:31:16 PM PDT 24 81318247 ps
T138 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1617308568 Jun 29 06:31:18 PM PDT 24 Jun 29 06:31:21 PM PDT 24 43482817 ps
T985 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3552971681 Jun 29 06:31:17 PM PDT 24 Jun 29 06:31:18 PM PDT 24 32889151 ps
T986 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3699680645 Jun 29 06:30:56 PM PDT 24 Jun 29 06:31:09 PM PDT 24 5043301878 ps
T131 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3319451997 Jun 29 06:31:12 PM PDT 24 Jun 29 06:31:15 PM PDT 24 286567077 ps
T987 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3911722348 Jun 29 06:30:59 PM PDT 24 Jun 29 06:31:01 PM PDT 24 114481415 ps
T988 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1786577461 Jun 29 06:30:54 PM PDT 24 Jun 29 06:31:12 PM PDT 24 690989790 ps
T989 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1509896617 Jun 29 06:31:10 PM PDT 24 Jun 29 06:31:13 PM PDT 24 244895596 ps
T990 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2512728911 Jun 29 06:31:09 PM PDT 24 Jun 29 06:31:11 PM PDT 24 36688816 ps
T991 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3454203947 Jun 29 06:31:00 PM PDT 24 Jun 29 06:31:02 PM PDT 24 17706216 ps
T992 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1762597044 Jun 29 06:31:20 PM PDT 24 Jun 29 06:31:22 PM PDT 24 52263338 ps
T993 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1778420741 Jun 29 06:31:17 PM PDT 24 Jun 29 06:31:20 PM PDT 24 125184689 ps
T994 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1694077980 Jun 29 06:30:56 PM PDT 24 Jun 29 06:31:21 PM PDT 24 965317285 ps
T181 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1211179679 Jun 29 06:31:01 PM PDT 24 Jun 29 06:31:02 PM PDT 24 22206971 ps
T995 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2542345188 Jun 29 06:31:03 PM PDT 24 Jun 29 06:31:08 PM PDT 24 2796961616 ps
T128 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1757192943 Jun 29 06:30:58 PM PDT 24 Jun 29 06:31:02 PM PDT 24 109981226 ps
T996 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.375341368 Jun 29 06:31:03 PM PDT 24 Jun 29 06:31:09 PM PDT 24 626675488 ps
T182 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.66866630 Jun 29 06:31:05 PM PDT 24 Jun 29 06:31:06 PM PDT 24 84282666 ps
T997 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2800653882 Jun 29 06:31:10 PM PDT 24 Jun 29 06:31:11 PM PDT 24 14920562 ps
T998 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2562717443 Jun 29 06:30:54 PM PDT 24 Jun 29 06:30:55 PM PDT 24 15082689 ps
T999 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3868738091 Jun 29 06:31:11 PM PDT 24 Jun 29 06:31:13 PM PDT 24 294689769 ps
T1000 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1249867862 Jun 29 06:30:50 PM PDT 24 Jun 29 06:30:52 PM PDT 24 415002099 ps
T136 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1334836342 Jun 29 06:31:19 PM PDT 24 Jun 29 06:31:27 PM PDT 24 1034997717 ps

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.108801491
Short name T5
Test name
Test status
Simulation time 12080574052 ps
CPU time 342.99 seconds
Started Jun 29 05:49:06 PM PDT 24
Finished Jun 29 05:54:49 PM PDT 24
Peak memory 405716 kb
Host smart-837ceaad-1ccc-4af5-b9fe-0fe3ca7cb3af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=108801491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.108801491
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.2415741826
Short name T50
Test name
Test status
Simulation time 297978033 ps
CPU time 12.7 seconds
Started Jun 29 05:50:50 PM PDT 24
Finished Jun 29 05:51:04 PM PDT 24
Peak memory 218496 kb
Host smart-c9996de2-f8fa-421c-80de-292268efcc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415741826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.2415741826
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.2679188933
Short name T39
Test name
Test status
Simulation time 1201654763 ps
CPU time 14.55 seconds
Started Jun 29 05:51:07 PM PDT 24
Finished Jun 29 05:51:22 PM PDT 24
Peak memory 226188 kb
Host smart-1541d9d6-fd68-44bd-a1c1-cfb497506b2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679188933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2679188933
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3861752029
Short name T28
Test name
Test status
Simulation time 501128707 ps
CPU time 21.97 seconds
Started Jun 29 05:45:48 PM PDT 24
Finished Jun 29 05:46:10 PM PDT 24
Peak memory 282464 kb
Host smart-06c63a61-e010-41ef-baae-d171ee92e988
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861752029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3861752029
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.601693008
Short name T47
Test name
Test status
Simulation time 73701702250 ps
CPU time 1242.84 seconds
Started Jun 29 05:50:26 PM PDT 24
Finished Jun 29 06:11:09 PM PDT 24
Peak memory 333204 kb
Host smart-371b011a-74fb-4fa5-9269-0aed93ccb4cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=601693008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.601693008
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.287866108
Short name T115
Test name
Test status
Simulation time 283397391 ps
CPU time 2.87 seconds
Started Jun 29 06:31:15 PM PDT 24
Finished Jun 29 06:31:18 PM PDT 24
Peak memory 222428 kb
Host smart-af1822a2-f2d9-41ac-8ab9-ebe198627e05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287866108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg_
err.287866108
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.1272250158
Short name T6
Test name
Test status
Simulation time 1595551667 ps
CPU time 10.56 seconds
Started Jun 29 05:49:21 PM PDT 24
Finished Jun 29 05:49:32 PM PDT 24
Peak memory 217556 kb
Host smart-864597a6-9898-4db4-86b5-0a4b5b213cad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272250158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1272250158
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.517279504
Short name T51
Test name
Test status
Simulation time 1231546805 ps
CPU time 8.53 seconds
Started Jun 29 05:50:27 PM PDT 24
Finished Jun 29 05:50:36 PM PDT 24
Peak memory 218492 kb
Host smart-654d2858-4de4-4c2f-b9c1-db4dc908656e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517279504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.517279504
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.2725551686
Short name T18
Test name
Test status
Simulation time 207960997 ps
CPU time 24.72 seconds
Started Jun 29 05:45:22 PM PDT 24
Finished Jun 29 05:45:47 PM PDT 24
Peak memory 251072 kb
Host smart-d5010207-5b49-43b1-9d2b-cfbab3d20187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725551686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.2725551686
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.858498702
Short name T117
Test name
Test status
Simulation time 178613277 ps
CPU time 2.89 seconds
Started Jun 29 06:30:55 PM PDT 24
Finished Jun 29 06:30:58 PM PDT 24
Peak memory 218628 kb
Host smart-8da487c7-6f23-4165-ae6c-e91eb28df303
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858498
702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.858498702
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.517232616
Short name T63
Test name
Test status
Simulation time 1580206467 ps
CPU time 10.35 seconds
Started Jun 29 05:51:31 PM PDT 24
Finished Jun 29 05:51:42 PM PDT 24
Peak memory 226188 kb
Host smart-b2a2c164-fa91-4b62-8f2a-866df58e94db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517232616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.517232616
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3895856399
Short name T85
Test name
Test status
Simulation time 235957950 ps
CPU time 0.9 seconds
Started Jun 29 05:47:56 PM PDT 24
Finished Jun 29 05:47:57 PM PDT 24
Peak memory 209124 kb
Host smart-42ad1118-c093-4160-a1ab-f74941922508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895856399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3895856399
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2423022102
Short name T155
Test name
Test status
Simulation time 37599454 ps
CPU time 1.82 seconds
Started Jun 29 06:30:53 PM PDT 24
Finished Jun 29 06:30:55 PM PDT 24
Peak memory 217592 kb
Host smart-21379063-63c9-44a4-83b9-d2fead053948
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423022102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.2423022102
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1340511192
Short name T124
Test name
Test status
Simulation time 202942101 ps
CPU time 5.37 seconds
Started Jun 29 06:31:12 PM PDT 24
Finished Jun 29 06:31:18 PM PDT 24
Peak memory 217532 kb
Host smart-ab1f5eab-b77d-4956-b465-05dc530093b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340511192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1340511192
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.2687386455
Short name T55
Test name
Test status
Simulation time 19089456817 ps
CPU time 194.22 seconds
Started Jun 29 05:50:00 PM PDT 24
Finished Jun 29 05:53:15 PM PDT 24
Peak memory 283928 kb
Host smart-e72e256b-ffe9-47a0-8abf-1f19d2bd5e70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687386455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.2687386455
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2508459036
Short name T35
Test name
Test status
Simulation time 27722884202 ps
CPU time 67.41 seconds
Started Jun 29 05:48:00 PM PDT 24
Finished Jun 29 05:49:07 PM PDT 24
Peak memory 251288 kb
Host smart-af3abc2f-bd25-4a01-b1ae-4629c09ab5c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508459036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2508459036
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.184471282
Short name T13
Test name
Test status
Simulation time 1090559057 ps
CPU time 16.36 seconds
Started Jun 29 05:49:44 PM PDT 24
Finished Jun 29 05:50:01 PM PDT 24
Peak memory 250836 kb
Host smart-599a273e-cc96-421f-97fc-29d4f5a29c6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184471282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.184471282
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3047281547
Short name T125
Test name
Test status
Simulation time 114042563 ps
CPU time 2.95 seconds
Started Jun 29 06:30:55 PM PDT 24
Finished Jun 29 06:30:58 PM PDT 24
Peak memory 222448 kb
Host smart-2472a020-bea3-4d45-9f6d-34298f2f9953
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047281547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3047281547
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.4068501341
Short name T135
Test name
Test status
Simulation time 89223975 ps
CPU time 3.58 seconds
Started Jun 29 06:31:18 PM PDT 24
Finished Jun 29 06:31:23 PM PDT 24
Peak memory 222432 kb
Host smart-f204ebc5-9071-4137-9ddf-7ace775891d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068501341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.4068501341
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3390690258
Short name T120
Test name
Test status
Simulation time 208474452 ps
CPU time 2.96 seconds
Started Jun 29 06:31:21 PM PDT 24
Finished Jun 29 06:31:25 PM PDT 24
Peak memory 221760 kb
Host smart-97bac164-4768-4a1b-b741-65ec153346c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390690258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3390690258
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.4255016647
Short name T113
Test name
Test status
Simulation time 395931560 ps
CPU time 4.14 seconds
Started Jun 29 06:31:03 PM PDT 24
Finished Jun 29 06:31:09 PM PDT 24
Peak memory 217520 kb
Host smart-ac01acd8-8f8b-461b-8713-ecedaa7465b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255016647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.4255016647
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3038783653
Short name T187
Test name
Test status
Simulation time 42581072 ps
CPU time 1.06 seconds
Started Jun 29 06:30:50 PM PDT 24
Finished Jun 29 06:30:53 PM PDT 24
Peak memory 209328 kb
Host smart-9b5a8d9a-b981-4aca-af81-9abf93656deb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038783653 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.3038783653
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.1036453457
Short name T90
Test name
Test status
Simulation time 73238219587 ps
CPU time 558.66 seconds
Started Jun 29 05:48:05 PM PDT 24
Finished Jun 29 05:57:24 PM PDT 24
Peak memory 333196 kb
Host smart-5c6d3054-727c-4f56-ac38-d32dd0e8df20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1036453457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.1036453457
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.11411719
Short name T190
Test name
Test status
Simulation time 36695712 ps
CPU time 0.97 seconds
Started Jun 29 05:50:36 PM PDT 24
Finished Jun 29 05:50:38 PM PDT 24
Peak memory 212048 kb
Host smart-6b96bddb-7681-48ed-ba1a-39debb950a28
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11411719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctr
l_volatile_unlock_smoke.11411719
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2855530358
Short name T140
Test name
Test status
Simulation time 132210316 ps
CPU time 4.49 seconds
Started Jun 29 06:30:48 PM PDT 24
Finished Jun 29 06:30:54 PM PDT 24
Peak memory 217580 kb
Host smart-29757997-95e0-4e0c-b9fc-233cc21ec355
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855530358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2855530358
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1695880736
Short name T137
Test name
Test status
Simulation time 125605474 ps
CPU time 2.65 seconds
Started Jun 29 06:31:21 PM PDT 24
Finished Jun 29 06:31:24 PM PDT 24
Peak memory 217564 kb
Host smart-ff920d11-3454-47db-bed0-bbed13c7418c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695880736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1695880736
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.359613823
Short name T195
Test name
Test status
Simulation time 12469925 ps
CPU time 0.99 seconds
Started Jun 29 05:45:29 PM PDT 24
Finished Jun 29 05:45:30 PM PDT 24
Peak memory 209208 kb
Host smart-f3c4ffec-fe25-4258-8312-f520f43d46d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359613823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.359613823
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.1403723137
Short name T197
Test name
Test status
Simulation time 37852388 ps
CPU time 0.97 seconds
Started Jun 29 05:45:52 PM PDT 24
Finished Jun 29 05:45:53 PM PDT 24
Peak memory 209212 kb
Host smart-cf95f2a1-b0ef-4d5e-80a7-526171b4610d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403723137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1403723137
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.1742546396
Short name T194
Test name
Test status
Simulation time 39761061 ps
CPU time 0.84 seconds
Started Jun 29 05:46:57 PM PDT 24
Finished Jun 29 05:46:59 PM PDT 24
Peak memory 209164 kb
Host smart-147c2d6c-dac4-4228-ae82-53b60e358837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742546396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.1742546396
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2722171551
Short name T196
Test name
Test status
Simulation time 32021916 ps
CPU time 0.8 seconds
Started Jun 29 05:47:15 PM PDT 24
Finished Jun 29 05:47:16 PM PDT 24
Peak memory 209144 kb
Host smart-d32adc62-4325-44d9-8246-3f833f5afc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722171551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2722171551
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.2365568937
Short name T30
Test name
Test status
Simulation time 546698876 ps
CPU time 24.31 seconds
Started Jun 29 05:48:49 PM PDT 24
Finished Jun 29 05:49:13 PM PDT 24
Peak memory 251204 kb
Host smart-f472ca82-6e8b-48dc-b1b0-2dc0797b3587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365568937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2365568937
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2196902623
Short name T917
Test name
Test status
Simulation time 1676939055 ps
CPU time 11.22 seconds
Started Jun 29 06:30:51 PM PDT 24
Finished Jun 29 06:31:04 PM PDT 24
Peak memory 217112 kb
Host smart-9dc03771-77c8-47bc-a686-42a5896f342a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196902623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.2196902623
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3355690189
Short name T139
Test name
Test status
Simulation time 76756454 ps
CPU time 2.2 seconds
Started Jun 29 06:31:12 PM PDT 24
Finished Jun 29 06:31:15 PM PDT 24
Peak memory 213000 kb
Host smart-3404522f-6f11-4c50-b534-bb06313bdc77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355690189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.3355690189
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3950311073
Short name T134
Test name
Test status
Simulation time 105338532 ps
CPU time 2.1 seconds
Started Jun 29 06:31:10 PM PDT 24
Finished Jun 29 06:31:12 PM PDT 24
Peak memory 222284 kb
Host smart-23d5caee-aac0-49b2-9fae-edb4118727fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950311073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3950311073
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3956409967
Short name T142
Test name
Test status
Simulation time 338512068 ps
CPU time 2.88 seconds
Started Jun 29 06:31:10 PM PDT 24
Finished Jun 29 06:31:14 PM PDT 24
Peak memory 217580 kb
Host smart-47d50751-36eb-4f41-a7de-68d505b8e307
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956409967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.3956409967
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1334836342
Short name T136
Test name
Test status
Simulation time 1034997717 ps
CPU time 7.04 seconds
Started Jun 29 06:31:19 PM PDT 24
Finished Jun 29 06:31:27 PM PDT 24
Peak memory 217536 kb
Host smart-fdc02473-eab7-4c89-abab-824b8656286e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334836342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1334836342
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2709427033
Short name T133
Test name
Test status
Simulation time 126861962 ps
CPU time 2.91 seconds
Started Jun 29 06:31:05 PM PDT 24
Finished Jun 29 06:31:08 PM PDT 24
Peak memory 222124 kb
Host smart-9e085b15-d9a8-4f05-afa3-2afac9e7e08d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709427033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2709427033
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3319451997
Short name T131
Test name
Test status
Simulation time 286567077 ps
CPU time 2.9 seconds
Started Jun 29 06:31:12 PM PDT 24
Finished Jun 29 06:31:15 PM PDT 24
Peak memory 217624 kb
Host smart-b51bd801-a7e4-4d75-8674-d8fbfc45b52d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319451997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3319451997
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.302010506
Short name T43
Test name
Test status
Simulation time 111744339092 ps
CPU time 354.94 seconds
Started Jun 29 05:49:28 PM PDT 24
Finished Jun 29 05:55:23 PM PDT 24
Peak memory 316912 kb
Host smart-4933199a-7000-4889-b2d8-62a0d7f149f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=302010506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.302010506
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.1375684497
Short name T10
Test name
Test status
Simulation time 551395560 ps
CPU time 11.9 seconds
Started Jun 29 05:48:12 PM PDT 24
Finished Jun 29 05:48:25 PM PDT 24
Peak memory 218260 kb
Host smart-d1d41ee4-0bf8-4d5a-acc4-88364a05ffb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375684497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.1375684497
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3818302085
Short name T32
Test name
Test status
Simulation time 602826639 ps
CPU time 14.29 seconds
Started Jun 29 05:48:57 PM PDT 24
Finished Jun 29 05:49:12 PM PDT 24
Peak memory 218464 kb
Host smart-e6fb8e3b-5aa9-48f2-ad7d-df1d942fa002
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818302085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3818302085
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2733249558
Short name T887
Test name
Test status
Simulation time 81119164 ps
CPU time 1.77 seconds
Started Jun 29 06:30:49 PM PDT 24
Finished Jun 29 06:30:51 PM PDT 24
Peak memory 209112 kb
Host smart-12a21f6d-3bb0-4f8e-8807-d9829390e6cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733249558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.2733249558
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2264458225
Short name T881
Test name
Test status
Simulation time 37404607 ps
CPU time 1.09 seconds
Started Jun 29 06:30:50 PM PDT 24
Finished Jun 29 06:30:52 PM PDT 24
Peak memory 217928 kb
Host smart-7cc845f0-884a-41f6-b92c-82866feed234
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264458225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2264458225
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1488061591
Short name T922
Test name
Test status
Simulation time 56646995 ps
CPU time 1.33 seconds
Started Jun 29 06:30:54 PM PDT 24
Finished Jun 29 06:30:56 PM PDT 24
Peak memory 222820 kb
Host smart-db8c9bba-3e17-4c68-9a09-cdd3c02cbab4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488061591 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1488061591
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3633930348
Short name T905
Test name
Test status
Simulation time 99632498 ps
CPU time 1.08 seconds
Started Jun 29 06:30:51 PM PDT 24
Finished Jun 29 06:30:53 PM PDT 24
Peak memory 209076 kb
Host smart-bfd692ef-8b89-4687-b32a-b638927cc9d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633930348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3633930348
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3441188255
Short name T968
Test name
Test status
Simulation time 53532170 ps
CPU time 1.27 seconds
Started Jun 29 06:30:47 PM PDT 24
Finished Jun 29 06:30:49 PM PDT 24
Peak memory 209212 kb
Host smart-63299a9b-0dca-409f-8101-f6ee976041d2
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441188255 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3441188255
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2653631813
Short name T911
Test name
Test status
Simulation time 3740706661 ps
CPU time 9.92 seconds
Started Jun 29 06:30:49 PM PDT 24
Finished Jun 29 06:30:59 PM PDT 24
Peak memory 209276 kb
Host smart-60ad00e6-f7bb-4498-b865-7f844edd2f03
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653631813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2653631813
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2016915408
Short name T972
Test name
Test status
Simulation time 263793900 ps
CPU time 1.34 seconds
Started Jun 29 06:30:49 PM PDT 24
Finished Jun 29 06:30:50 PM PDT 24
Peak memory 210352 kb
Host smart-76b44f4b-81ce-49a4-8ae6-a4f9479e45e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016915408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2016915408
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.403621152
Short name T973
Test name
Test status
Simulation time 245339163 ps
CPU time 1.66 seconds
Started Jun 29 06:30:50 PM PDT 24
Finished Jun 29 06:30:52 PM PDT 24
Peak memory 218500 kb
Host smart-fb3f4a05-3bc1-4a4b-8fa5-857b9ff7abe3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403621
152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.403621152
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3298886895
Short name T146
Test name
Test status
Simulation time 149913860 ps
CPU time 1.11 seconds
Started Jun 29 06:30:47 PM PDT 24
Finished Jun 29 06:30:48 PM PDT 24
Peak memory 217144 kb
Host smart-88f195d5-518e-4bd8-97f9-aa2b69c07414
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298886895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3298886895
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4290029316
Short name T188
Test name
Test status
Simulation time 28571552 ps
CPU time 1.41 seconds
Started Jun 29 06:30:48 PM PDT 24
Finished Jun 29 06:30:50 PM PDT 24
Peak memory 217512 kb
Host smart-e7a2d4ba-198d-4260-afe2-e0bf19ab71a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290029316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.4290029316
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3492509082
Short name T925
Test name
Test status
Simulation time 191108113 ps
CPU time 2.2 seconds
Started Jun 29 06:30:50 PM PDT 24
Finished Jun 29 06:30:52 PM PDT 24
Peak memory 217548 kb
Host smart-181e5916-593b-4433-beae-3a6b8cd45f9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492509082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3492509082
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.154719673
Short name T130
Test name
Test status
Simulation time 91819977 ps
CPU time 1.34 seconds
Started Jun 29 06:30:48 PM PDT 24
Finished Jun 29 06:30:50 PM PDT 24
Peak memory 209272 kb
Host smart-d886d8a0-b45f-46f2-9515-f6229d664bfb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154719673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.154719673
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3934861268
Short name T873
Test name
Test status
Simulation time 257085384 ps
CPU time 2.76 seconds
Started Jun 29 06:30:50 PM PDT 24
Finished Jun 29 06:30:54 PM PDT 24
Peak memory 217360 kb
Host smart-643222fa-c7ff-45e7-8ee4-59f65cfe196d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934861268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3934861268
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.181637207
Short name T924
Test name
Test status
Simulation time 22463019 ps
CPU time 1 seconds
Started Jun 29 06:30:46 PM PDT 24
Finished Jun 29 06:30:47 PM PDT 24
Peak memory 209948 kb
Host smart-48e7d2dc-726a-4287-9aab-fff996f85550
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181637207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset
.181637207
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1755274342
Short name T913
Test name
Test status
Simulation time 14130388 ps
CPU time 1.04 seconds
Started Jun 29 06:30:51 PM PDT 24
Finished Jun 29 06:30:53 PM PDT 24
Peak memory 217548 kb
Host smart-74fdda79-1231-45de-8fd9-c84fdccf2de6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755274342 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1755274342
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1737280473
Short name T975
Test name
Test status
Simulation time 19804306 ps
CPU time 0.91 seconds
Started Jun 29 06:30:53 PM PDT 24
Finished Jun 29 06:30:54 PM PDT 24
Peak memory 209320 kb
Host smart-0efb15b1-b3c7-4108-a35f-36cce00e0ba5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737280473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1737280473
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1197308772
Short name T929
Test name
Test status
Simulation time 45363887 ps
CPU time 1.37 seconds
Started Jun 29 06:30:47 PM PDT 24
Finished Jun 29 06:30:49 PM PDT 24
Peak memory 209240 kb
Host smart-8b0c22ce-d80f-4708-b457-ce578d95ee0c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197308772 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1197308772
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2424725429
Short name T145
Test name
Test status
Simulation time 3490983572 ps
CPU time 20.49 seconds
Started Jun 29 06:30:50 PM PDT 24
Finished Jun 29 06:31:11 PM PDT 24
Peak memory 209312 kb
Host smart-4f07f873-493a-4ba6-8ef0-fbbc6d39678a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424725429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2424725429
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1459838678
Short name T889
Test name
Test status
Simulation time 2344438185 ps
CPU time 6.12 seconds
Started Jun 29 06:30:48 PM PDT 24
Finished Jun 29 06:30:54 PM PDT 24
Peak memory 209208 kb
Host smart-0c0a8890-945d-484f-bda9-ed11a408f0da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459838678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1459838678
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3437709181
Short name T930
Test name
Test status
Simulation time 94032005 ps
CPU time 3.07 seconds
Started Jun 29 06:30:55 PM PDT 24
Finished Jun 29 06:30:59 PM PDT 24
Peak memory 211148 kb
Host smart-d6879341-eb3c-4a14-9927-4c3caf9e46f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437709181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.3437709181
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.286573456
Short name T877
Test name
Test status
Simulation time 148224022 ps
CPU time 2.82 seconds
Started Jun 29 06:30:55 PM PDT 24
Finished Jun 29 06:30:58 PM PDT 24
Peak memory 218856 kb
Host smart-43ea08ba-2f8f-4ef4-bdad-70ca982c6666
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286573
456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.286573456
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.4182950656
Short name T949
Test name
Test status
Simulation time 34506481 ps
CPU time 1.69 seconds
Started Jun 29 06:30:48 PM PDT 24
Finished Jun 29 06:30:50 PM PDT 24
Peak memory 209184 kb
Host smart-d688e7de-50da-44c6-8a29-e912ad53d70e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182950656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.4182950656
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3965601566
Short name T941
Test name
Test status
Simulation time 114885996 ps
CPU time 1.16 seconds
Started Jun 29 06:30:50 PM PDT 24
Finished Jun 29 06:30:52 PM PDT 24
Peak memory 209384 kb
Host smart-8e67e090-b6f5-4b18-9ac7-35d7588bea06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965601566 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.3965601566
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.811276553
Short name T894
Test name
Test status
Simulation time 23343608 ps
CPU time 1.11 seconds
Started Jun 29 06:30:49 PM PDT 24
Finished Jun 29 06:30:51 PM PDT 24
Peak memory 217568 kb
Host smart-25c560a7-a152-49d5-8352-380085031379
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811276553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.811276553
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1322452028
Short name T886
Test name
Test status
Simulation time 77016740 ps
CPU time 3.5 seconds
Started Jun 29 06:30:48 PM PDT 24
Finished Jun 29 06:30:52 PM PDT 24
Peak memory 217524 kb
Host smart-7c15c6a4-67b0-4aab-9b7c-43fce78218af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322452028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1322452028
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3955183213
Short name T893
Test name
Test status
Simulation time 86296821 ps
CPU time 1.54 seconds
Started Jun 29 06:31:11 PM PDT 24
Finished Jun 29 06:31:13 PM PDT 24
Peak memory 222744 kb
Host smart-45f6e29f-893b-4f12-bc6d-c26988286c50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955183213 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.3955183213
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3983432330
Short name T157
Test name
Test status
Simulation time 57617890 ps
CPU time 0.95 seconds
Started Jun 29 06:31:09 PM PDT 24
Finished Jun 29 06:31:11 PM PDT 24
Peak memory 209312 kb
Host smart-d88032d9-28f1-4794-99be-f88f28d4bbd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983432330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3983432330
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3751916411
Short name T156
Test name
Test status
Simulation time 84380698 ps
CPU time 1.03 seconds
Started Jun 29 06:31:07 PM PDT 24
Finished Jun 29 06:31:09 PM PDT 24
Peak memory 209288 kb
Host smart-237de474-6c86-421c-87f6-d5c2cb90bfd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751916411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3751916411
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3681150909
Short name T970
Test name
Test status
Simulation time 293786883 ps
CPU time 3.4 seconds
Started Jun 29 06:31:12 PM PDT 24
Finished Jun 29 06:31:16 PM PDT 24
Peak memory 217440 kb
Host smart-4f4595ac-ccae-4b8d-8fd4-a571cbd07781
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681150909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3681150909
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2656590488
Short name T892
Test name
Test status
Simulation time 49203268 ps
CPU time 1.59 seconds
Started Jun 29 06:31:14 PM PDT 24
Finished Jun 29 06:31:16 PM PDT 24
Peak memory 217732 kb
Host smart-ec155df3-e17a-4712-a756-ca15043eca9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656590488 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.2656590488
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1792069173
Short name T174
Test name
Test status
Simulation time 24195747 ps
CPU time 0.92 seconds
Started Jun 29 06:31:11 PM PDT 24
Finished Jun 29 06:31:12 PM PDT 24
Peak memory 209316 kb
Host smart-060e43f3-0863-481d-9064-dee5aea2453a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792069173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1792069173
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2610041180
Short name T979
Test name
Test status
Simulation time 46313649 ps
CPU time 1.48 seconds
Started Jun 29 06:31:11 PM PDT 24
Finished Jun 29 06:31:13 PM PDT 24
Peak memory 209396 kb
Host smart-7158ec3b-5829-4792-8b85-113bac78e1e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610041180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.2610041180
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1762597044
Short name T992
Test name
Test status
Simulation time 52263338 ps
CPU time 1.2 seconds
Started Jun 29 06:31:20 PM PDT 24
Finished Jun 29 06:31:22 PM PDT 24
Peak memory 217728 kb
Host smart-cfa7238a-8f5d-4941-90b0-32a20855d902
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762597044 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.1762597044
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.484444625
Short name T880
Test name
Test status
Simulation time 40000306 ps
CPU time 0.82 seconds
Started Jun 29 06:31:12 PM PDT 24
Finished Jun 29 06:31:13 PM PDT 24
Peak memory 209196 kb
Host smart-a695b9c5-3865-439b-ad94-16719664da32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484444625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.484444625
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2125321326
Short name T186
Test name
Test status
Simulation time 49033026 ps
CPU time 1.99 seconds
Started Jun 29 06:31:08 PM PDT 24
Finished Jun 29 06:31:10 PM PDT 24
Peak memory 209380 kb
Host smart-875c9908-8f48-4d6b-9bea-af64afb04e64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125321326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.2125321326
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3618339085
Short name T960
Test name
Test status
Simulation time 91302857 ps
CPU time 1.97 seconds
Started Jun 29 06:31:11 PM PDT 24
Finished Jun 29 06:31:13 PM PDT 24
Peak memory 217740 kb
Host smart-e874e63d-7ca3-470c-b38f-0b8028d3a1ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618339085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3618339085
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1778420741
Short name T993
Test name
Test status
Simulation time 125184689 ps
CPU time 1.95 seconds
Started Jun 29 06:31:17 PM PDT 24
Finished Jun 29 06:31:20 PM PDT 24
Peak memory 217644 kb
Host smart-6b1e3657-e485-4b76-948a-1999da5bdd76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778420741 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1778420741
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.524692675
Short name T180
Test name
Test status
Simulation time 189301876 ps
CPU time 0.98 seconds
Started Jun 29 06:31:19 PM PDT 24
Finished Jun 29 06:31:22 PM PDT 24
Peak memory 209244 kb
Host smart-5cd504ab-f24d-4fba-ac42-05a43f5f19cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524692675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.524692675
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2647682700
Short name T908
Test name
Test status
Simulation time 16659042 ps
CPU time 1.14 seconds
Started Jun 29 06:31:26 PM PDT 24
Finished Jun 29 06:31:28 PM PDT 24
Peak memory 209596 kb
Host smart-50754052-404f-4a18-b250-7a50e5799b2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647682700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2647682700
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1282048505
Short name T950
Test name
Test status
Simulation time 48888280 ps
CPU time 2.89 seconds
Started Jun 29 06:31:16 PM PDT 24
Finished Jun 29 06:31:19 PM PDT 24
Peak memory 217532 kb
Host smart-27ec73b4-2dfe-4962-8e6a-fa9f5d5d9b2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282048505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.1282048505
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3804655144
Short name T143
Test name
Test status
Simulation time 189257573 ps
CPU time 2.82 seconds
Started Jun 29 06:31:19 PM PDT 24
Finished Jun 29 06:31:23 PM PDT 24
Peak memory 222452 kb
Host smart-9df3815b-6a21-4090-90a4-df3557ddc44a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804655144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.3804655144
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3605366765
Short name T971
Test name
Test status
Simulation time 27795414 ps
CPU time 1.28 seconds
Started Jun 29 06:31:15 PM PDT 24
Finished Jun 29 06:31:17 PM PDT 24
Peak memory 217580 kb
Host smart-69548ca0-2e93-47c9-9b40-e484b2b584e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605366765 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.3605366765
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3552971681
Short name T985
Test name
Test status
Simulation time 32889151 ps
CPU time 0.83 seconds
Started Jun 29 06:31:17 PM PDT 24
Finished Jun 29 06:31:18 PM PDT 24
Peak memory 208668 kb
Host smart-6ff82fad-41c2-4cfe-9350-bfbfb8719b0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552971681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3552971681
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1411243750
Short name T943
Test name
Test status
Simulation time 190413408 ps
CPU time 1.1 seconds
Started Jun 29 06:31:17 PM PDT 24
Finished Jun 29 06:31:19 PM PDT 24
Peak memory 217532 kb
Host smart-b6813b99-280a-45e6-8800-954941d151cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411243750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.1411243750
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1230424769
Short name T890
Test name
Test status
Simulation time 112917451 ps
CPU time 3.5 seconds
Started Jun 29 06:31:19 PM PDT 24
Finished Jun 29 06:31:24 PM PDT 24
Peak memory 217684 kb
Host smart-2853b4aa-0092-4dc3-a9b4-c942a925be26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230424769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.1230424769
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1705439442
Short name T888
Test name
Test status
Simulation time 14923237 ps
CPU time 1.14 seconds
Started Jun 29 06:31:17 PM PDT 24
Finished Jun 29 06:31:18 PM PDT 24
Peak memory 217644 kb
Host smart-5317727f-b5c7-4312-8a6f-035e72ca4a61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705439442 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.1705439442
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1678165541
Short name T179
Test name
Test status
Simulation time 15580794 ps
CPU time 0.9 seconds
Started Jun 29 06:31:19 PM PDT 24
Finished Jun 29 06:31:21 PM PDT 24
Peak memory 209068 kb
Host smart-998020c0-41b5-462b-9d3d-ce9431a2123b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678165541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.1678165541
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3444007388
Short name T185
Test name
Test status
Simulation time 21840231 ps
CPU time 1.49 seconds
Started Jun 29 06:31:20 PM PDT 24
Finished Jun 29 06:31:23 PM PDT 24
Peak memory 209500 kb
Host smart-6918865a-92b2-4780-82e5-288e633961e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444007388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.3444007388
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3895329348
Short name T942
Test name
Test status
Simulation time 65300666 ps
CPU time 2.3 seconds
Started Jun 29 06:31:18 PM PDT 24
Finished Jun 29 06:31:22 PM PDT 24
Peak memory 217608 kb
Host smart-cdbb062a-e350-4685-9a4b-e4b03c46ccfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895329348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.3895329348
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2666344974
Short name T939
Test name
Test status
Simulation time 111525935 ps
CPU time 2.32 seconds
Started Jun 29 06:31:15 PM PDT 24
Finished Jun 29 06:31:18 PM PDT 24
Peak memory 217668 kb
Host smart-7b5bf1de-abbe-46e2-9719-96e172e1f418
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666344974 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2666344974
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2718002989
Short name T879
Test name
Test status
Simulation time 60258219 ps
CPU time 1.12 seconds
Started Jun 29 06:31:19 PM PDT 24
Finished Jun 29 06:31:22 PM PDT 24
Peak memory 209092 kb
Host smart-d81baf6c-0e52-46c7-b0a9-7582fcfc5ec5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718002989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.2718002989
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2306474271
Short name T183
Test name
Test status
Simulation time 149845247 ps
CPU time 1.37 seconds
Started Jun 29 06:31:20 PM PDT 24
Finished Jun 29 06:31:22 PM PDT 24
Peak memory 217568 kb
Host smart-9a5fc7f8-5bd3-402e-ae33-acae4a3881fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306474271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2306474271
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.577723415
Short name T964
Test name
Test status
Simulation time 72860572 ps
CPU time 2.28 seconds
Started Jun 29 06:31:15 PM PDT 24
Finished Jun 29 06:31:18 PM PDT 24
Peak memory 217516 kb
Host smart-33da737b-7c6e-4e33-908c-f8ea8cfea783
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577723415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.577723415
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1152595893
Short name T121
Test name
Test status
Simulation time 30516967 ps
CPU time 1.36 seconds
Started Jun 29 06:31:18 PM PDT 24
Finished Jun 29 06:31:21 PM PDT 24
Peak memory 217788 kb
Host smart-e1da071b-d36b-4854-95f7-913ee3a0f5cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152595893 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1152595893
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.85690991
Short name T176
Test name
Test status
Simulation time 12738481 ps
CPU time 0.86 seconds
Started Jun 29 06:31:19 PM PDT 24
Finished Jun 29 06:31:21 PM PDT 24
Peak memory 208816 kb
Host smart-8c13141f-1d78-4c3f-8574-531dc913a2b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85690991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.85690991
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3272142136
Short name T909
Test name
Test status
Simulation time 140243641 ps
CPU time 1.81 seconds
Started Jun 29 06:31:16 PM PDT 24
Finished Jun 29 06:31:18 PM PDT 24
Peak memory 217564 kb
Host smart-a77c46b9-baa2-42cd-b80f-8ec3034462d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272142136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.3272142136
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.107905314
Short name T896
Test name
Test status
Simulation time 30756002 ps
CPU time 2.3 seconds
Started Jun 29 06:31:16 PM PDT 24
Finished Jun 29 06:31:19 PM PDT 24
Peak memory 217780 kb
Host smart-286083ea-88c3-4543-91b5-0f633e7ac72a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107905314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.107905314
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.4016767133
Short name T932
Test name
Test status
Simulation time 48977731 ps
CPU time 0.96 seconds
Started Jun 29 06:31:17 PM PDT 24
Finished Jun 29 06:31:19 PM PDT 24
Peak memory 217700 kb
Host smart-341b67db-6721-4041-b81d-10b1ec81123a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016767133 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.4016767133
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1695836751
Short name T927
Test name
Test status
Simulation time 29247076 ps
CPU time 0.95 seconds
Started Jun 29 06:31:18 PM PDT 24
Finished Jun 29 06:31:20 PM PDT 24
Peak memory 209268 kb
Host smart-3c0866d8-0c2a-407c-b823-a5ffa120a65d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695836751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.1695836751
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.4118764089
Short name T904
Test name
Test status
Simulation time 49833771 ps
CPU time 0.98 seconds
Started Jun 29 06:31:17 PM PDT 24
Finished Jun 29 06:31:19 PM PDT 24
Peak memory 217540 kb
Host smart-d6215158-73be-4b44-b76d-83ffb45a7b44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118764089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.4118764089
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.749372384
Short name T931
Test name
Test status
Simulation time 371844287 ps
CPU time 2.02 seconds
Started Jun 29 06:31:21 PM PDT 24
Finished Jun 29 06:31:24 PM PDT 24
Peak memory 217720 kb
Host smart-cf6200b5-327a-4086-acda-76ad4cc743b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749372384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.749372384
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.847246510
Short name T976
Test name
Test status
Simulation time 56706947 ps
CPU time 1.15 seconds
Started Jun 29 06:31:17 PM PDT 24
Finished Jun 29 06:31:19 PM PDT 24
Peak memory 217644 kb
Host smart-a77ba9f6-cecc-48d9-b45f-75ab5db74885
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847246510 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.847246510
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.412367612
Short name T980
Test name
Test status
Simulation time 44969725 ps
CPU time 0.96 seconds
Started Jun 29 06:31:26 PM PDT 24
Finished Jun 29 06:31:28 PM PDT 24
Peak memory 209464 kb
Host smart-2a5bdba2-74da-4d41-9e0d-e44f8c74d5f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412367612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.412367612
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.545054523
Short name T189
Test name
Test status
Simulation time 188412360 ps
CPU time 1.87 seconds
Started Jun 29 06:31:18 PM PDT 24
Finished Jun 29 06:31:21 PM PDT 24
Peak memory 209432 kb
Host smart-5d0ef9d0-a420-463c-ac87-db1c976fa1f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545054523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_same_csr_outstanding.545054523
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3273545879
Short name T118
Test name
Test status
Simulation time 144558498 ps
CPU time 2.58 seconds
Started Jun 29 06:31:19 PM PDT 24
Finished Jun 29 06:31:23 PM PDT 24
Peak memory 217508 kb
Host smart-a279ea13-09e2-48f6-ac14-9cc0f9e65aa3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273545879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3273545879
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1617308568
Short name T138
Test name
Test status
Simulation time 43482817 ps
CPU time 2 seconds
Started Jun 29 06:31:18 PM PDT 24
Finished Jun 29 06:31:21 PM PDT 24
Peak memory 222092 kb
Host smart-ebb19bad-945a-40be-8473-411e2d73260c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617308568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1617308568
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1634472861
Short name T957
Test name
Test status
Simulation time 14832165 ps
CPU time 1.06 seconds
Started Jun 29 06:30:59 PM PDT 24
Finished Jun 29 06:31:01 PM PDT 24
Peak memory 209320 kb
Host smart-09c65453-7d3e-48d0-a3fb-b8102f1b10c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634472861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.1634472861
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3560772896
Short name T955
Test name
Test status
Simulation time 107273838 ps
CPU time 1.49 seconds
Started Jun 29 06:30:59 PM PDT 24
Finished Jun 29 06:31:01 PM PDT 24
Peak memory 209296 kb
Host smart-dabae79f-8c14-49d3-a804-2ab9d8901330
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560772896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.3560772896
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3463906058
Short name T919
Test name
Test status
Simulation time 12681324 ps
CPU time 0.94 seconds
Started Jun 29 06:31:01 PM PDT 24
Finished Jun 29 06:31:02 PM PDT 24
Peak memory 209744 kb
Host smart-dfe0b027-cea9-466b-a66c-071e92b4b293
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463906058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3463906058
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3197893493
Short name T878
Test name
Test status
Simulation time 49941602 ps
CPU time 1.67 seconds
Started Jun 29 06:30:56 PM PDT 24
Finished Jun 29 06:30:59 PM PDT 24
Peak memory 218868 kb
Host smart-849f0ae3-e8ef-4873-aa89-68180d297c52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197893493 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3197893493
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3871423556
Short name T883
Test name
Test status
Simulation time 16329573 ps
CPU time 1.06 seconds
Started Jun 29 06:30:56 PM PDT 24
Finished Jun 29 06:30:57 PM PDT 24
Peak memory 208880 kb
Host smart-2a8a54f1-3cb6-4c4f-8a80-f7c70ecc077a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871423556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3871423556
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3911722348
Short name T987
Test name
Test status
Simulation time 114481415 ps
CPU time 1.39 seconds
Started Jun 29 06:30:59 PM PDT 24
Finished Jun 29 06:31:01 PM PDT 24
Peak memory 209220 kb
Host smart-64e69a95-3bff-463e-ad9d-e48f688644c0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911722348 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3911722348
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2191747813
Short name T899
Test name
Test status
Simulation time 368692275 ps
CPU time 9.65 seconds
Started Jun 29 06:30:56 PM PDT 24
Finished Jun 29 06:31:06 PM PDT 24
Peak memory 208940 kb
Host smart-ce5cf217-6e07-45a4-b174-868c903b0910
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191747813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.2191747813
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1786577461
Short name T988
Test name
Test status
Simulation time 690989790 ps
CPU time 17.13 seconds
Started Jun 29 06:30:54 PM PDT 24
Finished Jun 29 06:31:12 PM PDT 24
Peak memory 209156 kb
Host smart-bd94d6c5-9c65-4cfc-b026-9eb0c9e55804
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786577461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1786577461
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1542716923
Short name T872
Test name
Test status
Simulation time 105744063 ps
CPU time 3.02 seconds
Started Jun 29 06:30:50 PM PDT 24
Finished Jun 29 06:30:54 PM PDT 24
Peak memory 210720 kb
Host smart-e5cce9c0-914c-4917-858c-4fea48d678d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542716923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.1542716923
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.960913410
Short name T902
Test name
Test status
Simulation time 291069456 ps
CPU time 2.8 seconds
Started Jun 29 06:30:57 PM PDT 24
Finished Jun 29 06:31:00 PM PDT 24
Peak memory 217728 kb
Host smart-2dfab770-1ec7-479a-bf60-93615ed5f45f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960913
410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.960913410
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1249867862
Short name T1000
Test name
Test status
Simulation time 415002099 ps
CPU time 1.72 seconds
Started Jun 29 06:30:50 PM PDT 24
Finished Jun 29 06:30:52 PM PDT 24
Peak memory 217240 kb
Host smart-344da335-d4bd-46a3-a927-41840c57c0a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249867862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.1249867862
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1472912103
Short name T122
Test name
Test status
Simulation time 51763513 ps
CPU time 1.56 seconds
Started Jun 29 06:30:55 PM PDT 24
Finished Jun 29 06:30:57 PM PDT 24
Peak memory 211536 kb
Host smart-cff59e3f-a392-455b-9d46-5d087b23acbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472912103 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1472912103
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2562717443
Short name T998
Test name
Test status
Simulation time 15082689 ps
CPU time 1.14 seconds
Started Jun 29 06:30:54 PM PDT 24
Finished Jun 29 06:30:55 PM PDT 24
Peak memory 209436 kb
Host smart-b50c2846-3489-4324-a3bc-464fa46c430e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562717443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.2562717443
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2519573311
Short name T900
Test name
Test status
Simulation time 395288612 ps
CPU time 4.29 seconds
Started Jun 29 06:30:59 PM PDT 24
Finished Jun 29 06:31:04 PM PDT 24
Peak memory 217524 kb
Host smart-1e195ada-6023-4cf4-988a-177dbd0dcaeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519573311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2519573311
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1166788518
Short name T141
Test name
Test status
Simulation time 111137037 ps
CPU time 3.17 seconds
Started Jun 29 06:30:58 PM PDT 24
Finished Jun 29 06:31:02 PM PDT 24
Peak memory 222392 kb
Host smart-cca7f118-e55c-4e14-991c-c2b448ec42b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166788518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1166788518
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3454203947
Short name T991
Test name
Test status
Simulation time 17706216 ps
CPU time 1.01 seconds
Started Jun 29 06:31:00 PM PDT 24
Finished Jun 29 06:31:02 PM PDT 24
Peak memory 209236 kb
Host smart-f73aa9cc-476a-4163-8f61-1a4836147ae1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454203947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.3454203947
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1821575306
Short name T948
Test name
Test status
Simulation time 59509157 ps
CPU time 1.16 seconds
Started Jun 29 06:30:57 PM PDT 24
Finished Jun 29 06:30:59 PM PDT 24
Peak memory 209308 kb
Host smart-ad23bcbc-66e9-45d8-bdfe-4956d04171e8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821575306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.1821575306
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2150453380
Short name T920
Test name
Test status
Simulation time 18535421 ps
CPU time 1.06 seconds
Started Jun 29 06:30:56 PM PDT 24
Finished Jun 29 06:30:58 PM PDT 24
Peak memory 218044 kb
Host smart-f30e35fd-1541-4337-a462-547b15654f19
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150453380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.2150453380
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1039874145
Short name T959
Test name
Test status
Simulation time 94339355 ps
CPU time 1.41 seconds
Started Jun 29 06:30:55 PM PDT 24
Finished Jun 29 06:30:57 PM PDT 24
Peak memory 219532 kb
Host smart-06eb9352-cf6b-4ba6-ba13-c75bcfc42aec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039874145 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.1039874145
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.995596936
Short name T951
Test name
Test status
Simulation time 19873687 ps
CPU time 0.86 seconds
Started Jun 29 06:30:56 PM PDT 24
Finished Jun 29 06:30:58 PM PDT 24
Peak memory 209192 kb
Host smart-04a06e13-6a91-404a-9a59-95c2b50612f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995596936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.995596936
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.599796447
Short name T918
Test name
Test status
Simulation time 249516569 ps
CPU time 1.32 seconds
Started Jun 29 06:30:59 PM PDT 24
Finished Jun 29 06:31:01 PM PDT 24
Peak memory 209184 kb
Host smart-f027d728-21fc-4597-862f-de6edd15c3c4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599796447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.lc_ctrl_jtag_alert_test.599796447
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.182442347
Short name T935
Test name
Test status
Simulation time 2769563831 ps
CPU time 14.9 seconds
Started Jun 29 06:30:59 PM PDT 24
Finished Jun 29 06:31:15 PM PDT 24
Peak memory 209252 kb
Host smart-c1bf4cd4-f4f9-4f10-9cc6-d5e5100a4a16
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182442347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.182442347
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.23846774
Short name T965
Test name
Test status
Simulation time 3612678392 ps
CPU time 6.84 seconds
Started Jun 29 06:30:54 PM PDT 24
Finished Jun 29 06:31:01 PM PDT 24
Peak memory 209328 kb
Host smart-81303af9-ee53-41c8-a935-e40b470fbb2d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23846774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.23846774
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1841322532
Short name T876
Test name
Test status
Simulation time 180668972 ps
CPU time 1.62 seconds
Started Jun 29 06:31:01 PM PDT 24
Finished Jun 29 06:31:03 PM PDT 24
Peak memory 210660 kb
Host smart-98508021-9a7d-4ac4-ac7d-8e791c634799
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841322532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.1841322532
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3928368854
Short name T952
Test name
Test status
Simulation time 96093682 ps
CPU time 1.86 seconds
Started Jun 29 06:30:58 PM PDT 24
Finished Jun 29 06:31:00 PM PDT 24
Peak memory 217372 kb
Host smart-29c69c58-356a-42c9-9db0-0247159d7260
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928368854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.3928368854
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.627343553
Short name T906
Test name
Test status
Simulation time 219137982 ps
CPU time 1.54 seconds
Started Jun 29 06:30:56 PM PDT 24
Finished Jun 29 06:30:59 PM PDT 24
Peak memory 217608 kb
Host smart-b62eb51c-af0f-4d04-8201-578ba0451ab0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627343553 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.627343553
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2428106058
Short name T928
Test name
Test status
Simulation time 98903649 ps
CPU time 1.33 seconds
Started Jun 29 06:31:00 PM PDT 24
Finished Jun 29 06:31:02 PM PDT 24
Peak memory 217596 kb
Host smart-67487808-6734-4559-ad00-fa75cd24349e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428106058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.2428106058
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.519855660
Short name T958
Test name
Test status
Simulation time 199549215 ps
CPU time 4.6 seconds
Started Jun 29 06:31:04 PM PDT 24
Finished Jun 29 06:31:09 PM PDT 24
Peak memory 217464 kb
Host smart-d33aefcb-248e-41bc-9e89-fdad0db298c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519855660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.519855660
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.855899987
Short name T178
Test name
Test status
Simulation time 38459901 ps
CPU time 1.85 seconds
Started Jun 29 06:30:57 PM PDT 24
Finished Jun 29 06:31:00 PM PDT 24
Peak memory 209320 kb
Host smart-b1da4745-47f8-4ae1-9254-3e53f202820d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855899987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasing
.855899987
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2837233020
Short name T945
Test name
Test status
Simulation time 18067638 ps
CPU time 1.16 seconds
Started Jun 29 06:30:56 PM PDT 24
Finished Jun 29 06:30:58 PM PDT 24
Peak memory 209180 kb
Host smart-360b0431-69cf-4879-b64c-e03fbfa33034
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837233020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2837233020
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3185550880
Short name T175
Test name
Test status
Simulation time 15216125 ps
CPU time 0.95 seconds
Started Jun 29 06:30:56 PM PDT 24
Finished Jun 29 06:30:57 PM PDT 24
Peak memory 209784 kb
Host smart-5efd4a0e-ca95-4f76-9bb5-fcf445535b49
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185550880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.3185550880
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.162083279
Short name T895
Test name
Test status
Simulation time 29058077 ps
CPU time 1.74 seconds
Started Jun 29 06:31:00 PM PDT 24
Finished Jun 29 06:31:02 PM PDT 24
Peak memory 217644 kb
Host smart-da272d4a-2c61-427d-8433-3e352ad12112
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162083279 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.162083279
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2637218249
Short name T903
Test name
Test status
Simulation time 29237629 ps
CPU time 1.07 seconds
Started Jun 29 06:31:01 PM PDT 24
Finished Jun 29 06:31:02 PM PDT 24
Peak memory 209444 kb
Host smart-f2bcda79-adf7-4b5d-8d4f-4bdc6fa014be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637218249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2637218249
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.378562125
Short name T875
Test name
Test status
Simulation time 425407650 ps
CPU time 1.3 seconds
Started Jun 29 06:30:54 PM PDT 24
Finished Jun 29 06:30:56 PM PDT 24
Peak memory 209288 kb
Host smart-c23dacab-2a0d-41d6-8d14-7e4b1bc38337
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378562125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_alert_test.378562125
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.100370622
Short name T974
Test name
Test status
Simulation time 365812496 ps
CPU time 3.95 seconds
Started Jun 29 06:30:54 PM PDT 24
Finished Jun 29 06:30:59 PM PDT 24
Peak memory 208924 kb
Host smart-f89f058d-079f-4598-8499-40fa58910b54
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100370622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.100370622
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1694077980
Short name T994
Test name
Test status
Simulation time 965317285 ps
CPU time 23.64 seconds
Started Jun 29 06:30:56 PM PDT 24
Finished Jun 29 06:31:21 PM PDT 24
Peak memory 208884 kb
Host smart-8009eb08-9772-47ee-bad9-d37e77730beb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694077980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.1694077980
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.410405596
Short name T983
Test name
Test status
Simulation time 434830340 ps
CPU time 1.21 seconds
Started Jun 29 06:30:55 PM PDT 24
Finished Jun 29 06:30:56 PM PDT 24
Peak memory 217404 kb
Host smart-af33829d-ef42-401a-ba77-bca5b59d965d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410405596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.410405596
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3926915004
Short name T168
Test name
Test status
Simulation time 174462492 ps
CPU time 2.12 seconds
Started Jun 29 06:30:57 PM PDT 24
Finished Jun 29 06:31:00 PM PDT 24
Peak memory 218864 kb
Host smart-a5b8356d-2f9a-4a66-8f2b-c579ff9baef0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392691
5004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3926915004
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3464606907
Short name T898
Test name
Test status
Simulation time 79372838 ps
CPU time 1.27 seconds
Started Jun 29 06:30:59 PM PDT 24
Finished Jun 29 06:31:01 PM PDT 24
Peak memory 209224 kb
Host smart-2db8f429-3837-454c-957e-fe0ced1c65d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464606907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.3464606907
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3404864550
Short name T967
Test name
Test status
Simulation time 100044145 ps
CPU time 1.48 seconds
Started Jun 29 06:30:58 PM PDT 24
Finished Jun 29 06:31:00 PM PDT 24
Peak memory 209376 kb
Host smart-c1eddd2e-2539-4ae1-af88-68fe2a744f85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404864550 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.3404864550
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.722299732
Short name T897
Test name
Test status
Simulation time 88801242 ps
CPU time 1.33 seconds
Started Jun 29 06:31:03 PM PDT 24
Finished Jun 29 06:31:06 PM PDT 24
Peak memory 209316 kb
Host smart-9c415898-654a-48d2-9aff-4a8cf2278d4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722299732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
same_csr_outstanding.722299732
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2405182968
Short name T915
Test name
Test status
Simulation time 269591351 ps
CPU time 2.43 seconds
Started Jun 29 06:30:59 PM PDT 24
Finished Jun 29 06:31:02 PM PDT 24
Peak memory 217672 kb
Host smart-ebfc6e2b-6933-478d-a13a-35cdf2590cb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405182968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2405182968
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1757192943
Short name T128
Test name
Test status
Simulation time 109981226 ps
CPU time 3.17 seconds
Started Jun 29 06:30:58 PM PDT 24
Finished Jun 29 06:31:02 PM PDT 24
Peak memory 222584 kb
Host smart-984386c1-92d2-49fe-b420-718ee14a1ed6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757192943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1757192943
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1611838132
Short name T119
Test name
Test status
Simulation time 19646101 ps
CPU time 1.58 seconds
Started Jun 29 06:31:09 PM PDT 24
Finished Jun 29 06:31:11 PM PDT 24
Peak memory 217680 kb
Host smart-d534d4fa-2c43-4b5c-92ad-a5474a50caaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611838132 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1611838132
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.66866630
Short name T182
Test name
Test status
Simulation time 84282666 ps
CPU time 0.84 seconds
Started Jun 29 06:31:05 PM PDT 24
Finished Jun 29 06:31:06 PM PDT 24
Peak memory 208636 kb
Host smart-493a9891-2dc3-4de4-9477-c9bec44ca329
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66866630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.66866630
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2173945479
Short name T936
Test name
Test status
Simulation time 55155215 ps
CPU time 2.1 seconds
Started Jun 29 06:31:00 PM PDT 24
Finished Jun 29 06:31:02 PM PDT 24
Peak memory 209232 kb
Host smart-2e55dddb-6bdf-4b7b-906e-1f0dd9cded9f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173945479 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2173945479
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3699680645
Short name T986
Test name
Test status
Simulation time 5043301878 ps
CPU time 12.46 seconds
Started Jun 29 06:30:56 PM PDT 24
Finished Jun 29 06:31:09 PM PDT 24
Peak memory 217268 kb
Host smart-e2c49187-1ad1-4f4b-99f5-e1904d9ccfab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699680645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3699680645
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2621383778
Short name T910
Test name
Test status
Simulation time 567556427 ps
CPU time 6.04 seconds
Started Jun 29 06:30:59 PM PDT 24
Finished Jun 29 06:31:06 PM PDT 24
Peak memory 209204 kb
Host smart-12e5a45f-8729-4cb7-a9cd-1ce6bba6823f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621383778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2621383778
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.712655378
Short name T148
Test name
Test status
Simulation time 127050106 ps
CPU time 1.82 seconds
Started Jun 29 06:30:56 PM PDT 24
Finished Jun 29 06:30:59 PM PDT 24
Peak memory 210980 kb
Host smart-989248a9-6b5b-4a0d-8d89-2121d9239b47
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712655378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.712655378
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.531892331
Short name T129
Test name
Test status
Simulation time 191879762 ps
CPU time 3 seconds
Started Jun 29 06:30:57 PM PDT 24
Finished Jun 29 06:31:01 PM PDT 24
Peak memory 217716 kb
Host smart-2c01697c-6e23-4449-8c44-617e79945acd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531892
331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.531892331
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1929137803
Short name T147
Test name
Test status
Simulation time 205261725 ps
CPU time 1.92 seconds
Started Jun 29 06:31:00 PM PDT 24
Finished Jun 29 06:31:02 PM PDT 24
Peak memory 209192 kb
Host smart-3edf2267-3b49-4f6f-a59f-f033b48e8f63
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929137803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.1929137803
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1706015072
Short name T891
Test name
Test status
Simulation time 83059875 ps
CPU time 1.41 seconds
Started Jun 29 06:31:04 PM PDT 24
Finished Jun 29 06:31:06 PM PDT 24
Peak memory 209444 kb
Host smart-7176a172-daf4-4588-9bca-7e67bf697c8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706015072 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.1706015072
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3269348613
Short name T907
Test name
Test status
Simulation time 73005939 ps
CPU time 1.24 seconds
Started Jun 29 06:31:08 PM PDT 24
Finished Jun 29 06:31:10 PM PDT 24
Peak memory 211480 kb
Host smart-e7e4e9a8-d40b-4527-85ca-9bd9e681b0da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269348613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.3269348613
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3677678790
Short name T969
Test name
Test status
Simulation time 133825343 ps
CPU time 1.62 seconds
Started Jun 29 06:30:56 PM PDT 24
Finished Jun 29 06:30:58 PM PDT 24
Peak memory 218544 kb
Host smart-dc66ff35-237e-42e2-84e7-fe05cf3fdd3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677678790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3677678790
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2096849060
Short name T199
Test name
Test status
Simulation time 63885805 ps
CPU time 2.08 seconds
Started Jun 29 06:31:01 PM PDT 24
Finished Jun 29 06:31:04 PM PDT 24
Peak memory 221740 kb
Host smart-eece9394-d5d5-4048-bf15-bfc00296db40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096849060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.2096849060
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.321648962
Short name T982
Test name
Test status
Simulation time 24005031 ps
CPU time 1.48 seconds
Started Jun 29 06:31:06 PM PDT 24
Finished Jun 29 06:31:08 PM PDT 24
Peak memory 217612 kb
Host smart-794635a5-a8af-441e-bc86-65d8a542cffc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321648962 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.321648962
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1211179679
Short name T181
Test name
Test status
Simulation time 22206971 ps
CPU time 0.96 seconds
Started Jun 29 06:31:01 PM PDT 24
Finished Jun 29 06:31:02 PM PDT 24
Peak memory 209324 kb
Host smart-b853f894-2bc4-4df5-8073-34a5b7f23455
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211179679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1211179679
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2551337397
Short name T937
Test name
Test status
Simulation time 77210217 ps
CPU time 1.5 seconds
Started Jun 29 06:31:03 PM PDT 24
Finished Jun 29 06:31:04 PM PDT 24
Peak memory 208656 kb
Host smart-1295c248-b3b0-41f3-958b-aa4af8bf8030
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551337397 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2551337397
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2745879944
Short name T914
Test name
Test status
Simulation time 510648067 ps
CPU time 5.64 seconds
Started Jun 29 06:31:02 PM PDT 24
Finished Jun 29 06:31:08 PM PDT 24
Peak memory 208908 kb
Host smart-ec7fca1b-6ab8-45f4-884d-ba21b8aab556
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745879944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2745879944
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1848785432
Short name T884
Test name
Test status
Simulation time 1240161496 ps
CPU time 22.52 seconds
Started Jun 29 06:31:03 PM PDT 24
Finished Jun 29 06:31:27 PM PDT 24
Peak memory 217012 kb
Host smart-9278e02d-128a-4be7-84e5-dc507f26c29b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848785432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1848785432
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.319724115
Short name T874
Test name
Test status
Simulation time 372940938 ps
CPU time 3.02 seconds
Started Jun 29 06:31:09 PM PDT 24
Finished Jun 29 06:31:13 PM PDT 24
Peak memory 210680 kb
Host smart-26177008-b538-4522-9a79-9f8e32a1545f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319724115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.319724115
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.375341368
Short name T996
Test name
Test status
Simulation time 626675488 ps
CPU time 4.37 seconds
Started Jun 29 06:31:03 PM PDT 24
Finished Jun 29 06:31:09 PM PDT 24
Peak memory 217720 kb
Host smart-3cbf0382-cae1-4cad-8a25-b189940fb299
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375341
368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.375341368
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3765201473
Short name T961
Test name
Test status
Simulation time 56524614 ps
CPU time 1.31 seconds
Started Jun 29 06:31:03 PM PDT 24
Finished Jun 29 06:31:04 PM PDT 24
Peak memory 209248 kb
Host smart-73bd2313-e484-40fc-b2b3-3af1715aab5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765201473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.3765201473
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.161998478
Short name T966
Test name
Test status
Simulation time 20624374 ps
CPU time 1.43 seconds
Started Jun 29 06:31:04 PM PDT 24
Finished Jun 29 06:31:06 PM PDT 24
Peak memory 209296 kb
Host smart-8ad12845-bbe5-45e6-96ba-9033d958034c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161998478 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.161998478
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3390322701
Short name T953
Test name
Test status
Simulation time 25618180 ps
CPU time 1.07 seconds
Started Jun 29 06:31:03 PM PDT 24
Finished Jun 29 06:31:05 PM PDT 24
Peak memory 209308 kb
Host smart-6e33f52a-4945-41ea-8b09-3fe586ce0345
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390322701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.3390322701
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3387110765
Short name T114
Test name
Test status
Simulation time 130986509 ps
CPU time 3.09 seconds
Started Jun 29 06:31:04 PM PDT 24
Finished Jun 29 06:31:08 PM PDT 24
Peak memory 217624 kb
Host smart-2e22827e-445f-4e57-858c-c6484a3a3bd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387110765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.3387110765
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2223143580
Short name T144
Test name
Test status
Simulation time 55695653 ps
CPU time 1.9 seconds
Started Jun 29 06:31:03 PM PDT 24
Finished Jun 29 06:31:06 PM PDT 24
Peak memory 222040 kb
Host smart-10eb120e-0b2f-4ea4-b3cf-c7895265cc01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223143580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.2223143580
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2086504395
Short name T940
Test name
Test status
Simulation time 65711324 ps
CPU time 1.12 seconds
Started Jun 29 06:31:03 PM PDT 24
Finished Jun 29 06:31:04 PM PDT 24
Peak memory 218736 kb
Host smart-9aa129c3-db6d-4e7a-a672-46c0413819aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086504395 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.2086504395
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2757328262
Short name T177
Test name
Test status
Simulation time 12215558 ps
CPU time 0.92 seconds
Started Jun 29 06:31:08 PM PDT 24
Finished Jun 29 06:31:09 PM PDT 24
Peak memory 209284 kb
Host smart-e624088c-62f4-46b6-9203-0c6496a00c13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757328262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2757328262
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1837663189
Short name T921
Test name
Test status
Simulation time 804160853 ps
CPU time 3.2 seconds
Started Jun 29 06:31:04 PM PDT 24
Finished Jun 29 06:31:08 PM PDT 24
Peak memory 209200 kb
Host smart-b756bbad-e630-4523-af78-597b89d3947e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837663189 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1837663189
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2542345188
Short name T995
Test name
Test status
Simulation time 2796961616 ps
CPU time 3.66 seconds
Started Jun 29 06:31:03 PM PDT 24
Finished Jun 29 06:31:08 PM PDT 24
Peak memory 217256 kb
Host smart-f7e96a87-6301-40f0-9437-ff92aaa0052e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542345188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2542345188
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.717014056
Short name T149
Test name
Test status
Simulation time 5943645181 ps
CPU time 23.76 seconds
Started Jun 29 06:31:04 PM PDT 24
Finished Jun 29 06:31:29 PM PDT 24
Peak memory 209216 kb
Host smart-033649d9-579a-4053-81e8-fd9a5453d76f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717014056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.717014056
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1232884726
Short name T934
Test name
Test status
Simulation time 80272586 ps
CPU time 2.8 seconds
Started Jun 29 06:31:04 PM PDT 24
Finished Jun 29 06:31:07 PM PDT 24
Peak memory 217456 kb
Host smart-8bbd7ba6-b60d-473c-81f8-cf266bda4906
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232884726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1232884726
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3814574643
Short name T916
Test name
Test status
Simulation time 192942962 ps
CPU time 3.22 seconds
Started Jun 29 06:31:01 PM PDT 24
Finished Jun 29 06:31:05 PM PDT 24
Peak memory 218668 kb
Host smart-bfa811df-015f-48fd-8248-f6825de3e2ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381457
4643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3814574643
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.4232118084
Short name T912
Test name
Test status
Simulation time 55475709 ps
CPU time 2.09 seconds
Started Jun 29 06:31:04 PM PDT 24
Finished Jun 29 06:31:07 PM PDT 24
Peak memory 217240 kb
Host smart-cf3dee78-a645-4d04-b244-8613121685a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232118084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.4232118084
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3266570945
Short name T882
Test name
Test status
Simulation time 24046618 ps
CPU time 1 seconds
Started Jun 29 06:31:05 PM PDT 24
Finished Jun 29 06:31:06 PM PDT 24
Peak memory 209440 kb
Host smart-6f9a91d3-3fc9-4ea2-8392-8d842af7985b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266570945 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.3266570945
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1982086456
Short name T923
Test name
Test status
Simulation time 29337652 ps
CPU time 1.24 seconds
Started Jun 29 06:31:02 PM PDT 24
Finished Jun 29 06:31:03 PM PDT 24
Peak memory 209316 kb
Host smart-405143f0-19d8-44c1-84b7-a9cbeed4622f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982086456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.1982086456
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.4225237823
Short name T132
Test name
Test status
Simulation time 50739583 ps
CPU time 2.43 seconds
Started Jun 29 06:31:03 PM PDT 24
Finished Jun 29 06:31:05 PM PDT 24
Peak memory 217444 kb
Host smart-4fc928a8-5766-4056-a5b1-22a79324b551
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225237823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.4225237823
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3234402695
Short name T954
Test name
Test status
Simulation time 20139713 ps
CPU time 1.36 seconds
Started Jun 29 06:31:12 PM PDT 24
Finished Jun 29 06:31:14 PM PDT 24
Peak memory 217644 kb
Host smart-0b2b29e4-263a-4ce3-a0a7-d5bbb5621113
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234402695 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3234402695
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2800653882
Short name T997
Test name
Test status
Simulation time 14920562 ps
CPU time 0.87 seconds
Started Jun 29 06:31:10 PM PDT 24
Finished Jun 29 06:31:11 PM PDT 24
Peak memory 208888 kb
Host smart-285e6d52-ca35-4f23-80c1-f2e27f2bb1a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800653882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2800653882
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1704484095
Short name T981
Test name
Test status
Simulation time 45008055 ps
CPU time 1.12 seconds
Started Jun 29 06:31:09 PM PDT 24
Finished Jun 29 06:31:11 PM PDT 24
Peak memory 209220 kb
Host smart-6bc786a6-f34b-4414-ae98-3fce2c678cf4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704484095 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.1704484095
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.585167271
Short name T944
Test name
Test status
Simulation time 1066294681 ps
CPU time 3.57 seconds
Started Jun 29 06:31:02 PM PDT 24
Finished Jun 29 06:31:06 PM PDT 24
Peak memory 208888 kb
Host smart-c86ec2d0-8006-41a7-acf6-f286987678a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585167271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.585167271
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.4155293104
Short name T978
Test name
Test status
Simulation time 1925029139 ps
CPU time 25.28 seconds
Started Jun 29 06:31:04 PM PDT 24
Finished Jun 29 06:31:30 PM PDT 24
Peak memory 208892 kb
Host smart-e01a8d0f-bdc0-4c5f-b959-1c796ea9c43c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155293104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.4155293104
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.496911452
Short name T938
Test name
Test status
Simulation time 46866119 ps
CPU time 1.22 seconds
Started Jun 29 06:31:03 PM PDT 24
Finished Jun 29 06:31:06 PM PDT 24
Peak memory 210676 kb
Host smart-2057147b-25bb-4779-b445-d6eeed795367
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496911452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.496911452
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2410452992
Short name T933
Test name
Test status
Simulation time 78446442 ps
CPU time 1.68 seconds
Started Jun 29 06:31:07 PM PDT 24
Finished Jun 29 06:31:09 PM PDT 24
Peak memory 217980 kb
Host smart-c4d2b95a-b14f-43fb-99a1-d53d1c6d1f25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241045
2992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2410452992
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.333755611
Short name T947
Test name
Test status
Simulation time 35372964 ps
CPU time 1.54 seconds
Started Jun 29 06:31:03 PM PDT 24
Finished Jun 29 06:31:06 PM PDT 24
Peak memory 217452 kb
Host smart-fdd72e0e-6c7c-4387-9324-c4c6e852e2b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333755611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.333755611
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3976064461
Short name T184
Test name
Test status
Simulation time 14895689 ps
CPU time 0.98 seconds
Started Jun 29 06:31:03 PM PDT 24
Finished Jun 29 06:31:04 PM PDT 24
Peak memory 209388 kb
Host smart-55585b40-0fcb-451e-8eec-47b116a045c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976064461 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3976064461
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.365521390
Short name T885
Test name
Test status
Simulation time 24937519 ps
CPU time 1.03 seconds
Started Jun 29 06:31:08 PM PDT 24
Finished Jun 29 06:31:10 PM PDT 24
Peak memory 209384 kb
Host smart-5b4d8049-fa16-4ab7-9d68-5407d6c259c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365521390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
same_csr_outstanding.365521390
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1788440127
Short name T963
Test name
Test status
Simulation time 167766947 ps
CPU time 3.2 seconds
Started Jun 29 06:31:11 PM PDT 24
Finished Jun 29 06:31:14 PM PDT 24
Peak memory 218988 kb
Host smart-2ae774cd-f4e2-44ab-b950-b18e4cf3973a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788440127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1788440127
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1186867206
Short name T946
Test name
Test status
Simulation time 82096634 ps
CPU time 1.22 seconds
Started Jun 29 06:31:11 PM PDT 24
Finished Jun 29 06:31:13 PM PDT 24
Peak memory 217664 kb
Host smart-89252ded-b64c-451b-be71-3babe8db9298
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186867206 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1186867206
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2512728911
Short name T990
Test name
Test status
Simulation time 36688816 ps
CPU time 1.01 seconds
Started Jun 29 06:31:09 PM PDT 24
Finished Jun 29 06:31:11 PM PDT 24
Peak memory 209312 kb
Host smart-f0613c73-60e0-4969-ab16-65a76ffed0f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512728911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.2512728911
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1509896617
Short name T989
Test name
Test status
Simulation time 244895596 ps
CPU time 2.15 seconds
Started Jun 29 06:31:10 PM PDT 24
Finished Jun 29 06:31:13 PM PDT 24
Peak memory 209240 kb
Host smart-59252dfa-0707-4376-84c0-09f5013218db
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509896617 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1509896617
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.370305358
Short name T962
Test name
Test status
Simulation time 368039139 ps
CPU time 10.14 seconds
Started Jun 29 06:31:10 PM PDT 24
Finished Jun 29 06:31:20 PM PDT 24
Peak memory 209020 kb
Host smart-fd825945-7329-45d9-a5f9-8a2c9078268e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370305358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.370305358
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.415414002
Short name T926
Test name
Test status
Simulation time 6177366368 ps
CPU time 35.63 seconds
Started Jun 29 06:31:08 PM PDT 24
Finished Jun 29 06:31:44 PM PDT 24
Peak memory 209268 kb
Host smart-0530be89-f5a2-404a-bc3e-4c7baef3fd71
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415414002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.415414002
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2652435673
Short name T977
Test name
Test status
Simulation time 254022636 ps
CPU time 3.49 seconds
Started Jun 29 06:31:09 PM PDT 24
Finished Jun 29 06:31:13 PM PDT 24
Peak memory 210736 kb
Host smart-2011b304-07fe-4e61-b9ff-4f1aca19203b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652435673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2652435673
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2500164964
Short name T956
Test name
Test status
Simulation time 328646663 ps
CPU time 2.76 seconds
Started Jun 29 06:31:10 PM PDT 24
Finished Jun 29 06:31:14 PM PDT 24
Peak memory 217664 kb
Host smart-063e6b29-8728-4f75-b1bd-c44214a88308
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250016
4964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2500164964
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3868738091
Short name T999
Test name
Test status
Simulation time 294689769 ps
CPU time 1.57 seconds
Started Jun 29 06:31:11 PM PDT 24
Finished Jun 29 06:31:13 PM PDT 24
Peak memory 209224 kb
Host smart-f001ab36-f8dc-4fde-8b0e-9227c24fe049
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868738091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3868738091
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2142013175
Short name T984
Test name
Test status
Simulation time 81318247 ps
CPU time 1.56 seconds
Started Jun 29 06:31:14 PM PDT 24
Finished Jun 29 06:31:16 PM PDT 24
Peak memory 217704 kb
Host smart-c38f8982-87a6-44fc-9611-166e107df0ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142013175 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2142013175
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.327621813
Short name T901
Test name
Test status
Simulation time 71420207 ps
CPU time 1.92 seconds
Started Jun 29 06:31:11 PM PDT 24
Finished Jun 29 06:31:14 PM PDT 24
Peak memory 217580 kb
Host smart-41ad2ff1-227b-4fec-b795-8752dd668128
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327621813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
same_csr_outstanding.327621813
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2630947866
Short name T126
Test name
Test status
Simulation time 68429283 ps
CPU time 1.45 seconds
Started Jun 29 06:31:09 PM PDT 24
Finished Jun 29 06:31:11 PM PDT 24
Peak memory 217524 kb
Host smart-bc44c44a-e580-4f93-9b20-a3f6ac9d2116
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630947866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.2630947866
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2217077984
Short name T127
Test name
Test status
Simulation time 322051329 ps
CPU time 2.28 seconds
Started Jun 29 06:31:10 PM PDT 24
Finished Jun 29 06:31:13 PM PDT 24
Peak memory 217660 kb
Host smart-f6d85fab-a746-4582-89af-deb990f304c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217077984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.2217077984
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.1536130001
Short name T615
Test name
Test status
Simulation time 21742307 ps
CPU time 0.9 seconds
Started Jun 29 05:44:56 PM PDT 24
Finished Jun 29 05:44:57 PM PDT 24
Peak memory 209144 kb
Host smart-293b0a52-04a8-4af5-9099-f55205f25a37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536130001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1536130001
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.1593376324
Short name T515
Test name
Test status
Simulation time 17013237 ps
CPU time 0.9 seconds
Started Jun 29 05:44:40 PM PDT 24
Finished Jun 29 05:44:41 PM PDT 24
Peak memory 209196 kb
Host smart-235a30e7-5a2e-45f4-9e3c-3c84b872e69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593376324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1593376324
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1761952133
Short name T100
Test name
Test status
Simulation time 1710946494 ps
CPU time 14.11 seconds
Started Jun 29 05:44:33 PM PDT 24
Finished Jun 29 05:44:48 PM PDT 24
Peak memory 218432 kb
Host smart-78ad34d5-da25-40ea-bc07-0518f105a0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761952133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1761952133
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3294836480
Short name T337
Test name
Test status
Simulation time 80232708 ps
CPU time 2.63 seconds
Started Jun 29 05:44:49 PM PDT 24
Finished Jun 29 05:44:52 PM PDT 24
Peak memory 217276 kb
Host smart-cd6bc5f9-bee5-4878-ac27-f49b625563fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294836480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3294836480
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3401009279
Short name T739
Test name
Test status
Simulation time 4617290558 ps
CPU time 41.33 seconds
Started Jun 29 05:44:49 PM PDT 24
Finished Jun 29 05:45:31 PM PDT 24
Peak memory 219324 kb
Host smart-88d031b4-6a19-46b7-98c4-fe011f47fe92
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401009279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3401009279
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.3970784506
Short name T631
Test name
Test status
Simulation time 350382024 ps
CPU time 3.11 seconds
Started Jun 29 05:44:48 PM PDT 24
Finished Jun 29 05:44:51 PM PDT 24
Peak memory 217716 kb
Host smart-09b879c5-dd40-4125-bbf8-11840758f044
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970784506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.3
970784506
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.219979206
Short name T280
Test name
Test status
Simulation time 1357851160 ps
CPU time 11.07 seconds
Started Jun 29 05:44:39 PM PDT 24
Finished Jun 29 05:44:50 PM PDT 24
Peak memory 218312 kb
Host smart-c640a8ae-3de0-422c-980d-6f61ae5756ee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219979206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
prog_failure.219979206
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.93477539
Short name T164
Test name
Test status
Simulation time 1094490074 ps
CPU time 15.7 seconds
Started Jun 29 05:44:55 PM PDT 24
Finished Jun 29 05:45:12 PM PDT 24
Peak memory 217928 kb
Host smart-3a6271ac-392b-48e1-921e-456ee7d9a8f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93477539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jt
ag_regwen_during_op.93477539
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.4249132342
Short name T105
Test name
Test status
Simulation time 216935916 ps
CPU time 7.19 seconds
Started Jun 29 05:44:39 PM PDT 24
Finished Jun 29 05:44:47 PM PDT 24
Peak memory 217908 kb
Host smart-b64c3b09-12c9-45fb-bfa8-d3b40c6808d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249132342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
4249132342
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.348229616
Short name T665
Test name
Test status
Simulation time 10952288176 ps
CPU time 57.49 seconds
Started Jun 29 05:44:39 PM PDT 24
Finished Jun 29 05:45:37 PM PDT 24
Peak memory 284040 kb
Host smart-f1b13c34-3493-4587-8760-5e7c3b4ad10c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348229616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_state_failure.348229616
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.172458016
Short name T286
Test name
Test status
Simulation time 1399150250 ps
CPU time 11.98 seconds
Started Jun 29 05:44:39 PM PDT 24
Finished Jun 29 05:44:51 PM PDT 24
Peak memory 223360 kb
Host smart-d596b9bc-38ad-460d-86a4-f81c6c59be2c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172458016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.172458016
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.4135208857
Short name T603
Test name
Test status
Simulation time 609873195 ps
CPU time 4.29 seconds
Started Jun 29 05:44:31 PM PDT 24
Finished Jun 29 05:44:36 PM PDT 24
Peak memory 218416 kb
Host smart-f9f838a0-3e35-4ef1-a883-4e0948a52b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135208857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.4135208857
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.2325429938
Short name T702
Test name
Test status
Simulation time 1380691256 ps
CPU time 9.54 seconds
Started Jun 29 05:44:39 PM PDT 24
Finished Jun 29 05:44:49 PM PDT 24
Peak memory 214856 kb
Host smart-35d02310-0bc5-42ad-9a15-2d831c672477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325429938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2325429938
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.3981912676
Short name T53
Test name
Test status
Simulation time 237744882 ps
CPU time 39.64 seconds
Started Jun 29 05:44:55 PM PDT 24
Finished Jun 29 05:45:36 PM PDT 24
Peak memory 283636 kb
Host smart-4b209b45-8fe2-47dd-a888-46a3ff28d0f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981912676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3981912676
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.2143632517
Short name T202
Test name
Test status
Simulation time 580419520 ps
CPU time 15.33 seconds
Started Jun 29 05:44:55 PM PDT 24
Finished Jun 29 05:45:11 PM PDT 24
Peak memory 218432 kb
Host smart-46224d9c-3ade-4a13-ab96-4cd7d794aaed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143632517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2143632517
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3444918525
Short name T253
Test name
Test status
Simulation time 295818869 ps
CPU time 9.97 seconds
Started Jun 29 05:44:56 PM PDT 24
Finished Jun 29 05:45:06 PM PDT 24
Peak memory 218452 kb
Host smart-ddcbdd48-005e-4615-ab62-a49a6508aee5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444918525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.3444918525
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2838384087
Short name T276
Test name
Test status
Simulation time 233314258 ps
CPU time 8.34 seconds
Started Jun 29 05:44:55 PM PDT 24
Finished Jun 29 05:45:04 PM PDT 24
Peak memory 218432 kb
Host smart-7d81861a-5b63-4682-b07a-f4a717445b73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838384087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
838384087
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.2135590910
Short name T685
Test name
Test status
Simulation time 586098017 ps
CPU time 11.22 seconds
Started Jun 29 05:44:32 PM PDT 24
Finished Jun 29 05:44:44 PM PDT 24
Peak memory 218564 kb
Host smart-123fc877-456a-4c7c-8517-01c7740a814e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135590910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2135590910
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.312507687
Short name T841
Test name
Test status
Simulation time 42349770 ps
CPU time 3.02 seconds
Started Jun 29 05:44:33 PM PDT 24
Finished Jun 29 05:44:37 PM PDT 24
Peak memory 215072 kb
Host smart-9e18f0ef-a416-492d-a3be-c2b1e8023e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312507687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.312507687
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.4155636607
Short name T492
Test name
Test status
Simulation time 2555395270 ps
CPU time 22.2 seconds
Started Jun 29 05:44:31 PM PDT 24
Finished Jun 29 05:44:54 PM PDT 24
Peak memory 251196 kb
Host smart-d9c1a9ce-4a9f-43be-bbf8-f1dc536e0cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155636607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.4155636607
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.3188958393
Short name T123
Test name
Test status
Simulation time 234302120 ps
CPU time 7.26 seconds
Started Jun 29 05:44:33 PM PDT 24
Finished Jun 29 05:44:41 PM PDT 24
Peak memory 250636 kb
Host smart-0d636678-fb12-48a0-bbff-2f4efa6422ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188958393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3188958393
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.543073756
Short name T79
Test name
Test status
Simulation time 10577820415 ps
CPU time 201.47 seconds
Started Jun 29 05:44:57 PM PDT 24
Finished Jun 29 05:48:19 PM PDT 24
Peak memory 251152 kb
Host smart-260b8f04-2c39-434c-b2f5-c8830212e49d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543073756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.543073756
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.503615029
Short name T670
Test name
Test status
Simulation time 35305567 ps
CPU time 1.04 seconds
Started Jun 29 05:44:31 PM PDT 24
Finished Jun 29 05:44:32 PM PDT 24
Peak memory 213152 kb
Host smart-385f6415-1a5a-4b7c-8655-91fb2eccef0b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503615029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr
l_volatile_unlock_smoke.503615029
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.2080127520
Short name T380
Test name
Test status
Simulation time 23226697 ps
CPU time 0.9 seconds
Started Jun 29 05:45:21 PM PDT 24
Finished Jun 29 05:45:22 PM PDT 24
Peak memory 209028 kb
Host smart-fcad6805-1cb2-49d7-9ebc-93a7f78966d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080127520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.2080127520
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.4259382193
Short name T192
Test name
Test status
Simulation time 15668483 ps
CPU time 0.9 seconds
Started Jun 29 05:45:12 PM PDT 24
Finished Jun 29 05:45:14 PM PDT 24
Peak memory 209228 kb
Host smart-d941104f-0fb4-423c-9de4-2b3a93cc6aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259382193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.4259382193
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.3013675932
Short name T701
Test name
Test status
Simulation time 1749615004 ps
CPU time 12.46 seconds
Started Jun 29 05:45:03 PM PDT 24
Finished Jun 29 05:45:16 PM PDT 24
Peak memory 218372 kb
Host smart-47588a5c-fcb2-4d89-8abc-c2c000f78d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013675932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.3013675932
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1656378826
Short name T24
Test name
Test status
Simulation time 3663172065 ps
CPU time 21.28 seconds
Started Jun 29 05:45:12 PM PDT 24
Finished Jun 29 05:45:34 PM PDT 24
Peak memory 217980 kb
Host smart-6f7f3540-4351-4aec-a207-9c1984992483
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656378826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1656378826
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.1393710117
Short name T682
Test name
Test status
Simulation time 29661086937 ps
CPU time 71.45 seconds
Started Jun 29 05:45:13 PM PDT 24
Finished Jun 29 05:46:25 PM PDT 24
Peak memory 219180 kb
Host smart-098c9828-782c-4446-b59f-d23e83502028
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393710117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.1393710117
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2886362555
Short name T820
Test name
Test status
Simulation time 2644242264 ps
CPU time 15.83 seconds
Started Jun 29 05:45:15 PM PDT 24
Finished Jun 29 05:45:31 PM PDT 24
Peak memory 218056 kb
Host smart-066d0383-3e78-414d-8633-d2b32f20b727
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886362555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
886362555
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3513845667
Short name T776
Test name
Test status
Simulation time 480527054 ps
CPU time 13.35 seconds
Started Jun 29 05:45:12 PM PDT 24
Finished Jun 29 05:45:26 PM PDT 24
Peak memory 224272 kb
Host smart-784ef87c-cb2e-4f18-8bb6-173d3e9979b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513845667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.3513845667
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2065741256
Short name T837
Test name
Test status
Simulation time 2539289101 ps
CPU time 35.72 seconds
Started Jun 29 05:45:14 PM PDT 24
Finished Jun 29 05:45:50 PM PDT 24
Peak memory 217976 kb
Host smart-de80018e-e8ac-4d2a-b099-8dd5e8f425ca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065741256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.2065741256
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.4242903064
Short name T354
Test name
Test status
Simulation time 294683640 ps
CPU time 8.45 seconds
Started Jun 29 05:45:12 PM PDT 24
Finished Jun 29 05:45:21 PM PDT 24
Peak memory 217904 kb
Host smart-16031972-ba4b-40e0-8c4d-38eb242bd261
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242903064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
4242903064
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3182872647
Short name T845
Test name
Test status
Simulation time 1571922407 ps
CPU time 32.81 seconds
Started Jun 29 05:45:13 PM PDT 24
Finished Jun 29 05:45:46 PM PDT 24
Peak memory 275712 kb
Host smart-958bf947-9907-407e-8103-6fbd9dc96f51
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182872647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3182872647
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.2469692658
Short name T792
Test name
Test status
Simulation time 494197240 ps
CPU time 17.32 seconds
Started Jun 29 05:45:12 PM PDT 24
Finished Jun 29 05:45:29 PM PDT 24
Peak memory 250936 kb
Host smart-998b3059-f2ed-4bb9-8d78-ce3e7d61bd99
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469692658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.2469692658
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.2418625259
Short name T9
Test name
Test status
Simulation time 79480958 ps
CPU time 2.95 seconds
Started Jun 29 05:45:06 PM PDT 24
Finished Jun 29 05:45:09 PM PDT 24
Peak memory 218640 kb
Host smart-853a5e9a-fc52-4c16-a03f-7d34a31276d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418625259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.2418625259
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.1280299240
Short name T703
Test name
Test status
Simulation time 316335339 ps
CPU time 20.55 seconds
Started Jun 29 05:45:14 PM PDT 24
Finished Jun 29 05:45:35 PM PDT 24
Peak memory 217868 kb
Host smart-6053bde5-a9a0-403d-879d-81bd73a8fd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280299240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.1280299240
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.4015970998
Short name T110
Test name
Test status
Simulation time 228371489 ps
CPU time 23.3 seconds
Started Jun 29 05:45:21 PM PDT 24
Finished Jun 29 05:45:44 PM PDT 24
Peak memory 282204 kb
Host smart-d2d1ec19-0555-4550-9f0b-80ac581af54e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015970998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.4015970998
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.4071826819
Short name T677
Test name
Test status
Simulation time 759005220 ps
CPU time 8.57 seconds
Started Jun 29 05:45:12 PM PDT 24
Finished Jun 29 05:45:21 PM PDT 24
Peak memory 226236 kb
Host smart-98df7cb8-78dd-440e-bd46-6b8a17b42460
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071826819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.4071826819
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.3474446196
Short name T746
Test name
Test status
Simulation time 391567543 ps
CPU time 15.65 seconds
Started Jun 29 05:45:14 PM PDT 24
Finished Jun 29 05:45:30 PM PDT 24
Peak memory 218460 kb
Host smart-9a61f26e-faa9-4ce1-8e9a-662fdba8ef6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474446196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.3474446196
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.3079880080
Short name T813
Test name
Test status
Simulation time 252406653 ps
CPU time 8.21 seconds
Started Jun 29 05:45:14 PM PDT 24
Finished Jun 29 05:45:22 PM PDT 24
Peak memory 218432 kb
Host smart-5919b0c3-2039-4ea4-b098-e323a82dbab7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079880080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.3
079880080
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.904761675
Short name T443
Test name
Test status
Simulation time 884206229 ps
CPU time 10.4 seconds
Started Jun 29 05:45:04 PM PDT 24
Finished Jun 29 05:45:14 PM PDT 24
Peak memory 218440 kb
Host smart-57d8bdb4-3a07-4732-832f-b72aac35a405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904761675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.904761675
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.2124947818
Short name T447
Test name
Test status
Simulation time 207745904 ps
CPU time 3.02 seconds
Started Jun 29 05:44:55 PM PDT 24
Finished Jun 29 05:44:58 PM PDT 24
Peak memory 217904 kb
Host smart-e7e34699-0d97-4ef7-9fc8-a3357c6d1320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124947818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2124947818
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.868640874
Short name T95
Test name
Test status
Simulation time 443038225 ps
CPU time 18.63 seconds
Started Jun 29 05:45:03 PM PDT 24
Finished Jun 29 05:45:22 PM PDT 24
Peak memory 245192 kb
Host smart-ef110a0e-8711-4232-bd5b-743658db0066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868640874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.868640874
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.906905574
Short name T652
Test name
Test status
Simulation time 67821264 ps
CPU time 7.38 seconds
Started Jun 29 05:45:04 PM PDT 24
Finished Jun 29 05:45:11 PM PDT 24
Peak memory 251016 kb
Host smart-c93af1f7-28e2-4d36-b14f-1f6c4c3521e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906905574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.906905574
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.1371582910
Short name T452
Test name
Test status
Simulation time 26418442464 ps
CPU time 166.96 seconds
Started Jun 29 05:45:21 PM PDT 24
Finished Jun 29 05:48:08 PM PDT 24
Peak memory 267568 kb
Host smart-87b9d5bb-761d-44e5-9d31-768daa6b48fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371582910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.1371582910
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2527972871
Short name T442
Test name
Test status
Simulation time 12843238 ps
CPU time 0.88 seconds
Started Jun 29 05:44:57 PM PDT 24
Finished Jun 29 05:44:58 PM PDT 24
Peak memory 212140 kb
Host smart-7e6add85-e648-4481-8128-d537eaee4446
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527972871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2527972871
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.356363500
Short name T499
Test name
Test status
Simulation time 111213766 ps
CPU time 1.07 seconds
Started Jun 29 05:47:34 PM PDT 24
Finished Jun 29 05:47:35 PM PDT 24
Peak memory 209144 kb
Host smart-f08da368-3219-40ec-a533-944d8b7b6ae1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356363500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.356363500
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.2012088592
Short name T787
Test name
Test status
Simulation time 1895498314 ps
CPU time 14.58 seconds
Started Jun 29 05:47:24 PM PDT 24
Finished Jun 29 05:47:39 PM PDT 24
Peak memory 226180 kb
Host smart-794f5838-9df3-4672-856f-0a954488f98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012088592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.2012088592
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.3581118350
Short name T27
Test name
Test status
Simulation time 423486818 ps
CPU time 5.36 seconds
Started Jun 29 05:47:34 PM PDT 24
Finished Jun 29 05:47:40 PM PDT 24
Peak memory 217472 kb
Host smart-4b005859-f2fb-463c-891b-37231733fcd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581118350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.3581118350
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1209567056
Short name T490
Test name
Test status
Simulation time 6733826526 ps
CPU time 19.37 seconds
Started Jun 29 05:47:35 PM PDT 24
Finished Jun 29 05:47:54 PM PDT 24
Peak memory 226264 kb
Host smart-d1121e28-4a55-4ecc-9173-471ac8f8dde1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209567056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1209567056
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1707027060
Short name T444
Test name
Test status
Simulation time 3631893149 ps
CPU time 11 seconds
Started Jun 29 05:47:31 PM PDT 24
Finished Jun 29 05:47:42 PM PDT 24
Peak memory 218472 kb
Host smart-cfa8fde0-427f-48ad-8f1b-a7e7bc52c391
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707027060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1707027060
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.1727046060
Short name T81
Test name
Test status
Simulation time 223624917 ps
CPU time 2.8 seconds
Started Jun 29 05:47:25 PM PDT 24
Finished Jun 29 05:47:28 PM PDT 24
Peak memory 217916 kb
Host smart-95a72145-dae8-4f36-a55f-8970a630c153
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727046060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.1727046060
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1712134909
Short name T579
Test name
Test status
Simulation time 8858296663 ps
CPU time 75.91 seconds
Started Jun 29 05:47:24 PM PDT 24
Finished Jun 29 05:48:41 PM PDT 24
Peak memory 270728 kb
Host smart-93ad020a-1df4-4c88-ba46-ebc043f21fef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712134909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1712134909
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.823057169
Short name T521
Test name
Test status
Simulation time 767313204 ps
CPU time 11.57 seconds
Started Jun 29 05:47:23 PM PDT 24
Finished Jun 29 05:47:35 PM PDT 24
Peak memory 226532 kb
Host smart-cb901f6f-a589-4de3-9b69-1b89bff2368a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823057169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
jtag_state_post_trans.823057169
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.570482843
Short name T778
Test name
Test status
Simulation time 91808596 ps
CPU time 2.78 seconds
Started Jun 29 05:47:23 PM PDT 24
Finished Jun 29 05:47:27 PM PDT 24
Peak memory 218428 kb
Host smart-396a1841-4d31-446f-8de4-0e7a53b18dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570482843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.570482843
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.911547141
Short name T708
Test name
Test status
Simulation time 233426454 ps
CPU time 11.22 seconds
Started Jun 29 05:47:31 PM PDT 24
Finished Jun 29 05:47:42 PM PDT 24
Peak memory 226244 kb
Host smart-ce903029-1410-43e2-a48b-8dbc14588ceb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911547141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.911547141
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1645712792
Short name T257
Test name
Test status
Simulation time 3587725519 ps
CPU time 10.51 seconds
Started Jun 29 05:47:34 PM PDT 24
Finished Jun 29 05:47:45 PM PDT 24
Peak memory 219100 kb
Host smart-42556507-a852-4fb7-855e-f882936cf672
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645712792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1645712792
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.3596343129
Short name T558
Test name
Test status
Simulation time 2069199151 ps
CPU time 5.99 seconds
Started Jun 29 05:47:32 PM PDT 24
Finished Jun 29 05:47:38 PM PDT 24
Peak memory 225172 kb
Host smart-0d81683f-3db2-46f4-a974-deb0a0b32ee9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596343129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
3596343129
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.3310764673
Short name T486
Test name
Test status
Simulation time 307119835 ps
CPU time 11.84 seconds
Started Jun 29 05:47:26 PM PDT 24
Finished Jun 29 05:47:38 PM PDT 24
Peak memory 226236 kb
Host smart-2f1a87fe-5a78-4e9d-a8c0-197aa0c25912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310764673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.3310764673
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.1025047987
Short name T797
Test name
Test status
Simulation time 104770267 ps
CPU time 2.07 seconds
Started Jun 29 05:47:23 PM PDT 24
Finished Jun 29 05:47:25 PM PDT 24
Peak memory 214380 kb
Host smart-e082c814-7126-4f9e-bdbb-ff18e1ed5440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025047987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1025047987
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.1260873427
Short name T529
Test name
Test status
Simulation time 2878563181 ps
CPU time 32.99 seconds
Started Jun 29 05:47:23 PM PDT 24
Finished Jun 29 05:47:56 PM PDT 24
Peak memory 247820 kb
Host smart-d67c2775-d2c0-465a-b1ad-81daba0aa124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260873427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1260873427
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2843598233
Short name T391
Test name
Test status
Simulation time 61099551 ps
CPU time 7.19 seconds
Started Jun 29 05:47:24 PM PDT 24
Finished Jun 29 05:47:31 PM PDT 24
Peak memory 251044 kb
Host smart-1ab4debd-5e46-49d3-b72d-1948c45d193e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843598233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2843598233
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.2455565920
Short name T780
Test name
Test status
Simulation time 1314279042 ps
CPU time 27.78 seconds
Started Jun 29 05:47:33 PM PDT 24
Finished Jun 29 05:48:01 PM PDT 24
Peak memory 246044 kb
Host smart-d6b66f1d-205c-4285-b124-7fe735ae4e2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455565920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.2455565920
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1739250454
Short name T531
Test name
Test status
Simulation time 13697247 ps
CPU time 0.89 seconds
Started Jun 29 05:47:23 PM PDT 24
Finished Jun 29 05:47:25 PM PDT 24
Peak memory 212092 kb
Host smart-4c2ddc8f-54c1-4bc2-8019-6b059846feb9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739250454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.1739250454
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.3026956030
Short name T364
Test name
Test status
Simulation time 38347319 ps
CPU time 1.24 seconds
Started Jun 29 05:47:40 PM PDT 24
Finished Jun 29 05:47:41 PM PDT 24
Peak memory 209232 kb
Host smart-b97ee2a0-15c8-4e89-9ed0-365f5b0bee45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026956030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3026956030
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.4165158411
Short name T519
Test name
Test status
Simulation time 725497543 ps
CPU time 15.93 seconds
Started Jun 29 05:47:34 PM PDT 24
Finished Jun 29 05:47:50 PM PDT 24
Peak memory 218432 kb
Host smart-b93517a9-70c7-435d-9ba5-c014a9de6f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165158411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.4165158411
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.3083088463
Short name T720
Test name
Test status
Simulation time 372895688 ps
CPU time 5.06 seconds
Started Jun 29 05:47:39 PM PDT 24
Finished Jun 29 05:47:45 PM PDT 24
Peak memory 217524 kb
Host smart-46d1881b-4941-46ee-ad1b-bbf367a9c62c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083088463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.3083088463
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.3564940286
Short name T245
Test name
Test status
Simulation time 10556404854 ps
CPU time 43.25 seconds
Started Jun 29 05:47:41 PM PDT 24
Finished Jun 29 05:48:24 PM PDT 24
Peak memory 219144 kb
Host smart-1e2cbea2-242c-4044-9ef9-c7c30812f3fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564940286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.3564940286
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.3382812501
Short name T471
Test name
Test status
Simulation time 588597110 ps
CPU time 11.05 seconds
Started Jun 29 05:47:41 PM PDT 24
Finished Jun 29 05:47:52 PM PDT 24
Peak memory 218412 kb
Host smart-87a88491-0170-4486-b743-aeb2fef11b5b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382812501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.3382812501
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3128921772
Short name T858
Test name
Test status
Simulation time 1738579084 ps
CPU time 6.15 seconds
Started Jun 29 05:47:41 PM PDT 24
Finished Jun 29 05:47:47 PM PDT 24
Peak memory 217940 kb
Host smart-8cf43607-a5e9-4a41-be98-8891b3bf869d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128921772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.3128921772
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3884041611
Short name T366
Test name
Test status
Simulation time 832722328 ps
CPU time 36.39 seconds
Started Jun 29 05:47:39 PM PDT 24
Finished Jun 29 05:48:16 PM PDT 24
Peak memory 275704 kb
Host smart-c84227be-f16f-4f36-95b1-edccb109c69e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884041611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3884041611
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.170466389
Short name T764
Test name
Test status
Simulation time 863846466 ps
CPU time 18.07 seconds
Started Jun 29 05:47:38 PM PDT 24
Finished Jun 29 05:47:57 PM PDT 24
Peak memory 251116 kb
Host smart-369ebe8a-65d9-4840-9ef7-46807ba3f060
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170466389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_
jtag_state_post_trans.170466389
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.3977702712
Short name T379
Test name
Test status
Simulation time 73595799 ps
CPU time 2.49 seconds
Started Jun 29 05:47:31 PM PDT 24
Finished Jun 29 05:47:34 PM PDT 24
Peak memory 222508 kb
Host smart-bce1bfad-5662-4ca0-9acc-1590d4292d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977702712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3977702712
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.3316424935
Short name T284
Test name
Test status
Simulation time 327099773 ps
CPU time 12.48 seconds
Started Jun 29 05:47:40 PM PDT 24
Finished Jun 29 05:47:53 PM PDT 24
Peak memory 226248 kb
Host smart-51adcb26-fe3a-45db-b7f9-fabb1f54df17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316424935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.3316424935
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2547323342
Short name T560
Test name
Test status
Simulation time 1038993160 ps
CPU time 16.09 seconds
Started Jun 29 05:47:39 PM PDT 24
Finished Jun 29 05:47:56 PM PDT 24
Peak memory 218444 kb
Host smart-78622278-9c5d-4990-93e1-c312a7843dd1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547323342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2547323342
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3232666296
Short name T345
Test name
Test status
Simulation time 383266755 ps
CPU time 9.96 seconds
Started Jun 29 05:47:40 PM PDT 24
Finished Jun 29 05:47:50 PM PDT 24
Peak memory 218436 kb
Host smart-f827b7bb-43f5-49b6-8f6a-e6b214370fde
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232666296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3232666296
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1519584160
Short name T871
Test name
Test status
Simulation time 1167777075 ps
CPU time 8.68 seconds
Started Jun 29 05:47:40 PM PDT 24
Finished Jun 29 05:47:49 PM PDT 24
Peak memory 218396 kb
Host smart-43e4e172-7d06-4df3-af11-f1cd4d1cf581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519584160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1519584160
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2516434665
Short name T277
Test name
Test status
Simulation time 20080043 ps
CPU time 1.54 seconds
Started Jun 29 05:47:34 PM PDT 24
Finished Jun 29 05:47:35 PM PDT 24
Peak memory 217928 kb
Host smart-e6fbfd20-b58c-48a5-8d3b-0805dba5b555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516434665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2516434665
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3379362120
Short name T459
Test name
Test status
Simulation time 545289268 ps
CPU time 32.5 seconds
Started Jun 29 05:47:32 PM PDT 24
Finished Jun 29 05:48:05 PM PDT 24
Peak memory 245216 kb
Host smart-6f5ccd83-32f8-48b5-9da0-87e24da8f7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379362120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3379362120
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.2666926561
Short name T511
Test name
Test status
Simulation time 217206997 ps
CPU time 5.91 seconds
Started Jun 29 05:47:32 PM PDT 24
Finished Jun 29 05:47:38 PM PDT 24
Peak memory 247164 kb
Host smart-2231b4c4-7c17-46e8-9308-1c51ad9495d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666926561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.2666926561
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.844642770
Short name T232
Test name
Test status
Simulation time 35071932363 ps
CPU time 280.5 seconds
Started Jun 29 05:47:39 PM PDT 24
Finished Jun 29 05:52:20 PM PDT 24
Peak memory 278884 kb
Host smart-7a9f9b62-b86c-4d2c-8d70-c49e146ecb9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844642770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.844642770
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1761052823
Short name T104
Test name
Test status
Simulation time 174517290 ps
CPU time 0.92 seconds
Started Jun 29 05:47:34 PM PDT 24
Finished Jun 29 05:47:35 PM PDT 24
Peak memory 217916 kb
Host smart-a002c8af-9392-42c4-b266-34a7dba16a73
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761052823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.1761052823
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.3842337217
Short name T472
Test name
Test status
Simulation time 2040374524 ps
CPU time 15.22 seconds
Started Jun 29 05:47:49 PM PDT 24
Finished Jun 29 05:48:05 PM PDT 24
Peak memory 218432 kb
Host smart-afd3063d-c4d6-4f5b-aae2-4cffd46b53bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842337217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3842337217
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.4243040346
Short name T565
Test name
Test status
Simulation time 2182345183 ps
CPU time 6.88 seconds
Started Jun 29 05:47:48 PM PDT 24
Finished Jun 29 05:47:56 PM PDT 24
Peak memory 217564 kb
Host smart-201c6208-c54e-4f64-87ff-cc45d2376147
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243040346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.4243040346
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3009579934
Short name T204
Test name
Test status
Simulation time 1877634347 ps
CPU time 27.8 seconds
Started Jun 29 05:47:50 PM PDT 24
Finished Jun 29 05:48:18 PM PDT 24
Peak memory 218424 kb
Host smart-e8496bc6-9975-4aa8-ade0-8645a1bf6333
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009579934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3009579934
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1925427458
Short name T799
Test name
Test status
Simulation time 444306975 ps
CPU time 5.06 seconds
Started Jun 29 05:47:48 PM PDT 24
Finished Jun 29 05:47:53 PM PDT 24
Peak memory 223284 kb
Host smart-2d2e6da4-db42-494c-a282-fb689e5258c3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925427458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1925427458
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2147481462
Short name T275
Test name
Test status
Simulation time 675926733 ps
CPU time 4.98 seconds
Started Jun 29 05:47:48 PM PDT 24
Finished Jun 29 05:47:54 PM PDT 24
Peak memory 217916 kb
Host smart-024f01f3-9cea-44b2-ba4f-1bcdb761ed15
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147481462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2147481462
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.807428920
Short name T679
Test name
Test status
Simulation time 4545500651 ps
CPU time 76.45 seconds
Started Jun 29 05:47:49 PM PDT 24
Finished Jun 29 05:49:06 PM PDT 24
Peak memory 283900 kb
Host smart-2adb6779-186a-42f6-8421-d8a350b56b90
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807428920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_state_failure.807428920
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.821458538
Short name T394
Test name
Test status
Simulation time 5617395449 ps
CPU time 13.45 seconds
Started Jun 29 05:47:49 PM PDT 24
Finished Jun 29 05:48:02 PM PDT 24
Peak memory 244128 kb
Host smart-0b5d59b8-d777-400e-b4f0-ae494c1f9f8e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821458538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_
jtag_state_post_trans.821458538
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.838155031
Short name T93
Test name
Test status
Simulation time 81066295 ps
CPU time 2.12 seconds
Started Jun 29 05:47:47 PM PDT 24
Finished Jun 29 05:47:50 PM PDT 24
Peak memory 222124 kb
Host smart-6c5aa389-66a3-42d1-a067-58b1d94d65d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838155031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.838155031
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.972912737
Short name T352
Test name
Test status
Simulation time 243963131 ps
CPU time 8.74 seconds
Started Jun 29 05:47:57 PM PDT 24
Finished Jun 29 05:48:06 PM PDT 24
Peak memory 226244 kb
Host smart-d314bfd7-1f7b-4433-aaa3-bb47e7d5d3af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972912737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.972912737
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.677086117
Short name T508
Test name
Test status
Simulation time 2020116298 ps
CPU time 10.68 seconds
Started Jun 29 05:47:57 PM PDT 24
Finished Jun 29 05:48:08 PM PDT 24
Peak memory 218404 kb
Host smart-f3d6da9d-5614-486a-bbf5-c3c59cd1a58d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677086117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_di
gest.677086117
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.4268778813
Short name T407
Test name
Test status
Simulation time 351666212 ps
CPU time 12.29 seconds
Started Jun 29 05:47:58 PM PDT 24
Finished Jun 29 05:48:11 PM PDT 24
Peak memory 226252 kb
Host smart-daa86082-a3a9-4a65-953c-73bff5e3ffc7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268778813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
4268778813
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.662251974
Short name T502
Test name
Test status
Simulation time 1448667495 ps
CPU time 11.34 seconds
Started Jun 29 05:47:48 PM PDT 24
Finished Jun 29 05:47:59 PM PDT 24
Peak memory 218484 kb
Host smart-06ee0ae9-9df7-4848-9903-41a0dca8a4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662251974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.662251974
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.2966408977
Short name T710
Test name
Test status
Simulation time 15763280 ps
CPU time 1.33 seconds
Started Jun 29 05:47:39 PM PDT 24
Finished Jun 29 05:47:41 PM PDT 24
Peak memory 217928 kb
Host smart-8f62542e-d6d8-4d8d-aaac-8b6b7d08c15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966408977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2966408977
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.3766695159
Short name T418
Test name
Test status
Simulation time 268829912 ps
CPU time 29.46 seconds
Started Jun 29 05:47:49 PM PDT 24
Finished Jun 29 05:48:19 PM PDT 24
Peak memory 251096 kb
Host smart-263bed39-ddfb-4719-b1c8-9e3e98f0d45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766695159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.3766695159
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.3146179804
Short name T225
Test name
Test status
Simulation time 120541673 ps
CPU time 8.15 seconds
Started Jun 29 05:47:49 PM PDT 24
Finished Jun 29 05:47:57 PM PDT 24
Peak memory 251132 kb
Host smart-509189d8-a6cb-4c50-a7e4-3ac84ef84ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146179804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3146179804
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.3984616163
Short name T152
Test name
Test status
Simulation time 136163528801 ps
CPU time 7317.89 seconds
Started Jun 29 05:47:59 PM PDT 24
Finished Jun 29 07:49:58 PM PDT 24
Peak memory 1168848 kb
Host smart-658da223-e1f8-4916-a01b-4110b6d8ef41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3984616163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.3984616163
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3212419315
Short name T474
Test name
Test status
Simulation time 80124243 ps
CPU time 0.85 seconds
Started Jun 29 05:47:49 PM PDT 24
Finished Jun 29 05:47:51 PM PDT 24
Peak memory 212148 kb
Host smart-9ad7df07-3fc1-4b28-b8c9-75fb524c35e1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212419315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3212419315
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.1679929303
Short name T694
Test name
Test status
Simulation time 58361858 ps
CPU time 1.17 seconds
Started Jun 29 05:48:06 PM PDT 24
Finished Jun 29 05:48:07 PM PDT 24
Peak memory 209236 kb
Host smart-e8e46565-d5c1-4e73-a2a3-0aac93be59f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679929303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.1679929303
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.3707899875
Short name T869
Test name
Test status
Simulation time 1298532121 ps
CPU time 11.49 seconds
Started Jun 29 05:47:56 PM PDT 24
Finished Jun 29 05:48:08 PM PDT 24
Peak memory 218432 kb
Host smart-87d9131e-39a9-4f62-92d8-0036dddc3c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707899875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.3707899875
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3523537256
Short name T22
Test name
Test status
Simulation time 5583819243 ps
CPU time 6.23 seconds
Started Jun 29 05:47:58 PM PDT 24
Finished Jun 29 05:48:04 PM PDT 24
Peak memory 217948 kb
Host smart-4dc89955-fefc-4aa3-8ff9-c02b7a06c20d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523537256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3523537256
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.4253253016
Short name T696
Test name
Test status
Simulation time 27530780665 ps
CPU time 58.23 seconds
Started Jun 29 05:47:58 PM PDT 24
Finished Jun 29 05:48:57 PM PDT 24
Peak memory 226308 kb
Host smart-5435390e-e682-4b69-bd3f-25a6cb5e1e9c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253253016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.4253253016
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.158296653
Short name T693
Test name
Test status
Simulation time 5305950570 ps
CPU time 7.9 seconds
Started Jun 29 05:47:56 PM PDT 24
Finished Jun 29 05:48:04 PM PDT 24
Peak memory 218460 kb
Host smart-642d318f-058b-4e0e-aade-5816310a62fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158296653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag
_prog_failure.158296653
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.3374771246
Short name T11
Test name
Test status
Simulation time 444484942 ps
CPU time 1.41 seconds
Started Jun 29 05:48:00 PM PDT 24
Finished Jun 29 05:48:02 PM PDT 24
Peak memory 217928 kb
Host smart-0bbe37f8-cdf8-49e4-9f11-30caab3b9690
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374771246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.3374771246
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.37833699
Short name T537
Test name
Test status
Simulation time 1161035724 ps
CPU time 47.38 seconds
Started Jun 29 05:47:56 PM PDT 24
Finished Jun 29 05:48:43 PM PDT 24
Peak memory 253960 kb
Host smart-d7427cba-90ba-4e23-b82b-5d33143994f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37833699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag
_state_failure.37833699
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.2294702017
Short name T348
Test name
Test status
Simulation time 303462077 ps
CPU time 10.55 seconds
Started Jun 29 05:47:57 PM PDT 24
Finished Jun 29 05:48:08 PM PDT 24
Peak memory 226220 kb
Host smart-48c7c23b-2ee8-4e29-a2c6-a452137b9cb0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294702017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.2294702017
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.3132243260
Short name T491
Test name
Test status
Simulation time 129855552 ps
CPU time 2.82 seconds
Started Jun 29 05:47:59 PM PDT 24
Finished Jun 29 05:48:02 PM PDT 24
Peak memory 218428 kb
Host smart-49f8dba8-7df9-4e67-8bf2-df890645f55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132243260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3132243260
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3789865959
Short name T681
Test name
Test status
Simulation time 239264063 ps
CPU time 8.87 seconds
Started Jun 29 05:47:56 PM PDT 24
Finished Jun 29 05:48:05 PM PDT 24
Peak memory 226212 kb
Host smart-88b7247e-c161-404a-82d5-f6c7148ee2f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789865959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3789865959
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.16783842
Short name T633
Test name
Test status
Simulation time 320931425 ps
CPU time 10.38 seconds
Started Jun 29 05:47:57 PM PDT 24
Finished Jun 29 05:48:07 PM PDT 24
Peak memory 218440 kb
Host smart-672e5a52-ab30-41f7-a43e-2fb9046b4921
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16783842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_dig
est.16783842
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2719755320
Short name T476
Test name
Test status
Simulation time 512095742 ps
CPU time 11.07 seconds
Started Jun 29 05:47:56 PM PDT 24
Finished Jun 29 05:48:08 PM PDT 24
Peak memory 218504 kb
Host smart-aa5a3cf5-bb86-4fe6-8bf2-22c16668d17a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719755320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
2719755320
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.1874382153
Short name T458
Test name
Test status
Simulation time 264477110 ps
CPU time 10.59 seconds
Started Jun 29 05:47:58 PM PDT 24
Finished Jun 29 05:48:09 PM PDT 24
Peak memory 225172 kb
Host smart-995ee1c1-54c0-4c3c-8a42-f3d84f14ab25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874382153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.1874382153
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.3951529911
Short name T237
Test name
Test status
Simulation time 745311339 ps
CPU time 4.07 seconds
Started Jun 29 05:47:56 PM PDT 24
Finished Jun 29 05:48:01 PM PDT 24
Peak memory 217924 kb
Host smart-c40891be-205e-4fd5-b829-4ee2c9e2e9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951529911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.3951529911
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.3606493434
Short name T831
Test name
Test status
Simulation time 767926166 ps
CPU time 19.96 seconds
Started Jun 29 05:47:56 PM PDT 24
Finished Jun 29 05:48:17 PM PDT 24
Peak memory 251124 kb
Host smart-2d74b5bf-3e0f-4b0e-9f78-cfa6a86de81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606493434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.3606493434
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.3340269470
Short name T721
Test name
Test status
Simulation time 71383771 ps
CPU time 9.29 seconds
Started Jun 29 05:47:55 PM PDT 24
Finished Jun 29 05:48:05 PM PDT 24
Peak memory 251132 kb
Host smart-3837433e-3040-4d79-ace1-c32c7c335b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340269470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.3340269470
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.2083575215
Short name T832
Test name
Test status
Simulation time 2992798843 ps
CPU time 73.01 seconds
Started Jun 29 05:48:04 PM PDT 24
Finished Jun 29 05:49:18 PM PDT 24
Peak memory 271856 kb
Host smart-b30116df-f357-4927-984d-96ae02866a47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083575215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.2083575215
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3821574616
Short name T853
Test name
Test status
Simulation time 99287586 ps
CPU time 0.84 seconds
Started Jun 29 05:47:55 PM PDT 24
Finished Jun 29 05:47:56 PM PDT 24
Peak memory 211968 kb
Host smart-15b75ee7-eae9-4ba4-addc-cdaeffeb87fe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821574616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.3821574616
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.1365637659
Short name T719
Test name
Test status
Simulation time 65476975 ps
CPU time 0.98 seconds
Started Jun 29 05:48:12 PM PDT 24
Finished Jun 29 05:48:13 PM PDT 24
Peak memory 209256 kb
Host smart-312d6045-f6e1-46aa-9d66-3779605ed68c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365637659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.1365637659
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2136003211
Short name T435
Test name
Test status
Simulation time 913263958 ps
CPU time 9.09 seconds
Started Jun 29 05:48:05 PM PDT 24
Finished Jun 29 05:48:15 PM PDT 24
Peak memory 218428 kb
Host smart-be2635fc-a20a-4222-ae79-beb67a9a53b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136003211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2136003211
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.357996749
Short name T303
Test name
Test status
Simulation time 623002129 ps
CPU time 14.69 seconds
Started Jun 29 05:48:06 PM PDT 24
Finished Jun 29 05:48:21 PM PDT 24
Peak memory 217484 kb
Host smart-a6c7110f-8a89-46e5-9a64-48790033b63e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357996749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.357996749
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.209158483
Short name T424
Test name
Test status
Simulation time 7558242888 ps
CPU time 68.35 seconds
Started Jun 29 05:48:05 PM PDT 24
Finished Jun 29 05:49:13 PM PDT 24
Peak memory 219148 kb
Host smart-10cc0eff-3dd7-48cd-a616-2b2743b67638
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209158483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_er
rors.209158483
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2193224136
Short name T717
Test name
Test status
Simulation time 224208379 ps
CPU time 4.33 seconds
Started Jun 29 05:48:06 PM PDT 24
Finished Jun 29 05:48:10 PM PDT 24
Peak memory 223040 kb
Host smart-a116ad4f-726c-47a1-853a-0af03c23bd18
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193224136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2193224136
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.212018274
Short name T66
Test name
Test status
Simulation time 1703181724 ps
CPU time 7.14 seconds
Started Jun 29 05:48:04 PM PDT 24
Finished Jun 29 05:48:12 PM PDT 24
Peak memory 218044 kb
Host smart-d8c0c501-1f25-40a5-879e-fe9c93637962
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212018274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.
212018274
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.1971255545
Short name T264
Test name
Test status
Simulation time 6535909719 ps
CPU time 49.65 seconds
Started Jun 29 05:48:06 PM PDT 24
Finished Jun 29 05:48:56 PM PDT 24
Peak memory 275772 kb
Host smart-c5766011-6bfe-4e4e-80e2-896a6db02825
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971255545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.1971255545
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2519311079
Short name T805
Test name
Test status
Simulation time 493872996 ps
CPU time 14.53 seconds
Started Jun 29 05:48:08 PM PDT 24
Finished Jun 29 05:48:23 PM PDT 24
Peak memory 251144 kb
Host smart-1015d1d4-6283-45a5-bee0-25ff42e6966e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519311079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.2519311079
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2948538149
Short name T809
Test name
Test status
Simulation time 290003676 ps
CPU time 3.85 seconds
Started Jun 29 05:48:05 PM PDT 24
Finished Jun 29 05:48:09 PM PDT 24
Peak memory 218424 kb
Host smart-3a8b5b2c-2359-4acc-99e3-cb4720a08cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948538149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2948538149
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.859797357
Short name T597
Test name
Test status
Simulation time 1304685158 ps
CPU time 10.83 seconds
Started Jun 29 05:48:04 PM PDT 24
Finished Jun 29 05:48:15 PM PDT 24
Peak memory 226192 kb
Host smart-fce336a3-a596-4921-985d-39e1c3cca3a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859797357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.859797357
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.4269767601
Short name T618
Test name
Test status
Simulation time 1790667678 ps
CPU time 23.14 seconds
Started Jun 29 05:48:12 PM PDT 24
Finished Jun 29 05:48:35 PM PDT 24
Peak memory 218528 kb
Host smart-a5871192-e04f-4223-9e47-3d67d90a3483
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269767601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.4269767601
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1010017043
Short name T604
Test name
Test status
Simulation time 827369923 ps
CPU time 9.02 seconds
Started Jun 29 05:48:12 PM PDT 24
Finished Jun 29 05:48:22 PM PDT 24
Peak memory 218432 kb
Host smart-cf8fc6c6-63e5-4f14-997d-9c87c467181c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010017043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
1010017043
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2890083212
Short name T56
Test name
Test status
Simulation time 311545867 ps
CPU time 12.94 seconds
Started Jun 29 05:48:05 PM PDT 24
Finished Jun 29 05:48:18 PM PDT 24
Peak memory 226156 kb
Host smart-9925c34c-65e3-461f-bca6-8123b539f0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890083212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2890083212
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3038463157
Short name T263
Test name
Test status
Simulation time 76976880 ps
CPU time 2.02 seconds
Started Jun 29 05:48:05 PM PDT 24
Finished Jun 29 05:48:08 PM PDT 24
Peak memory 222692 kb
Host smart-cbe03c71-3d48-48f5-8201-ab47b29adeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038463157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3038463157
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2727624876
Short name T259
Test name
Test status
Simulation time 911370560 ps
CPU time 21.07 seconds
Started Jun 29 05:48:06 PM PDT 24
Finished Jun 29 05:48:28 PM PDT 24
Peak memory 251124 kb
Host smart-fc1975d5-3507-4fb4-9f65-0fdcc348a44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727624876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2727624876
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.264232066
Short name T802
Test name
Test status
Simulation time 97100696 ps
CPU time 4.49 seconds
Started Jun 29 05:48:06 PM PDT 24
Finished Jun 29 05:48:11 PM PDT 24
Peak memory 222624 kb
Host smart-b8de0759-4b6d-4c32-86e3-513f9cdde483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264232066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.264232066
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.3400848998
Short name T865
Test name
Test status
Simulation time 12451916246 ps
CPU time 43.18 seconds
Started Jun 29 05:48:15 PM PDT 24
Finished Jun 29 05:48:59 PM PDT 24
Peak memory 226292 kb
Host smart-c542505e-506e-4d21-9474-47897f253722
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400848998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.3400848998
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.2478855457
Short name T153
Test name
Test status
Simulation time 44223610514 ps
CPU time 777.07 seconds
Started Jun 29 05:48:11 PM PDT 24
Finished Jun 29 06:01:09 PM PDT 24
Peak memory 291060 kb
Host smart-dc1c28bb-dd2e-49c5-935d-a59620a99138
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2478855457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.2478855457
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1180698800
Short name T307
Test name
Test status
Simulation time 29352688 ps
CPU time 1.04 seconds
Started Jun 29 05:48:06 PM PDT 24
Finished Jun 29 05:48:08 PM PDT 24
Peak memory 218036 kb
Host smart-5bfe5bc6-464e-41db-8a06-2ef62558b57a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180698800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1180698800
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.681019006
Short name T319
Test name
Test status
Simulation time 22347403 ps
CPU time 0.93 seconds
Started Jun 29 05:48:24 PM PDT 24
Finished Jun 29 05:48:26 PM PDT 24
Peak memory 209116 kb
Host smart-781c6b03-0586-434c-a5ef-192f93d3f8c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681019006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.681019006
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.4055818222
Short name T397
Test name
Test status
Simulation time 91474321 ps
CPU time 2.15 seconds
Started Jun 29 05:48:21 PM PDT 24
Finished Jun 29 05:48:24 PM PDT 24
Peak memory 217276 kb
Host smart-69b2d494-da8b-46fa-bde2-c1c5bbb0c9be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055818222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.4055818222
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2650090173
Short name T456
Test name
Test status
Simulation time 16400799105 ps
CPU time 57.92 seconds
Started Jun 29 05:48:23 PM PDT 24
Finished Jun 29 05:49:21 PM PDT 24
Peak memory 218996 kb
Host smart-eccd569a-da86-4d68-a5ae-1c184a2977d7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650090173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2650090173
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2875845871
Short name T4
Test name
Test status
Simulation time 187460911 ps
CPU time 2.4 seconds
Started Jun 29 05:48:21 PM PDT 24
Finished Jun 29 05:48:24 PM PDT 24
Peak memory 221628 kb
Host smart-fd17b952-f8a9-47e2-bd61-1f2a6f1fc563
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875845871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.2875845871
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1831583987
Short name T289
Test name
Test status
Simulation time 190549800 ps
CPU time 6.64 seconds
Started Jun 29 05:48:12 PM PDT 24
Finished Jun 29 05:48:19 PM PDT 24
Peak memory 217932 kb
Host smart-849eacb6-4962-49e5-a3de-92cdc0e076a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831583987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1831583987
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3496405663
Short name T158
Test name
Test status
Simulation time 1790764370 ps
CPU time 42.86 seconds
Started Jun 29 05:48:15 PM PDT 24
Finished Jun 29 05:48:58 PM PDT 24
Peak memory 268080 kb
Host smart-83073568-be00-429e-ada2-a273f7b5b0d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496405663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3496405663
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2524272520
Short name T755
Test name
Test status
Simulation time 913591056 ps
CPU time 11.49 seconds
Started Jun 29 05:48:12 PM PDT 24
Finished Jun 29 05:48:24 PM PDT 24
Peak memory 251120 kb
Host smart-fb6d3e3e-8b63-4d57-9dbd-984f60d325dc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524272520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.2524272520
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.3677959145
Short name T290
Test name
Test status
Simulation time 188316075 ps
CPU time 1.75 seconds
Started Jun 29 05:48:16 PM PDT 24
Finished Jun 29 05:48:18 PM PDT 24
Peak memory 218428 kb
Host smart-6feabc56-c4fb-45dc-9383-e659429c478d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677959145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.3677959145
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.74842517
Short name T678
Test name
Test status
Simulation time 318182709 ps
CPU time 16.52 seconds
Started Jun 29 05:48:22 PM PDT 24
Finished Jun 29 05:48:39 PM PDT 24
Peak memory 226232 kb
Host smart-3abbf8ab-7b5c-4f8e-b0d8-f92cfad074f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74842517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.74842517
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2092968396
Short name T487
Test name
Test status
Simulation time 1375867984 ps
CPU time 14.07 seconds
Started Jun 29 05:48:21 PM PDT 24
Finished Jun 29 05:48:36 PM PDT 24
Peak memory 218528 kb
Host smart-00e30115-e9ee-4979-be00-730a9782fd8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092968396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2092968396
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.3667377430
Short name T866
Test name
Test status
Simulation time 366669572 ps
CPU time 12.96 seconds
Started Jun 29 05:48:21 PM PDT 24
Finished Jun 29 05:48:34 PM PDT 24
Peak memory 218440 kb
Host smart-92d1ecd0-a0d6-4cba-b4b1-9b3ac71b3fd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667377430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
3667377430
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2369187342
Short name T200
Test name
Test status
Simulation time 1817531592 ps
CPU time 10.85 seconds
Started Jun 29 05:48:12 PM PDT 24
Finished Jun 29 05:48:24 PM PDT 24
Peak memory 218496 kb
Host smart-a45afa38-5f73-44bb-8688-7f8b348875e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369187342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2369187342
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1575974903
Short name T706
Test name
Test status
Simulation time 27899514 ps
CPU time 1.94 seconds
Started Jun 29 05:48:12 PM PDT 24
Finished Jun 29 05:48:14 PM PDT 24
Peak memory 217952 kb
Host smart-65379278-ac8d-43c5-9a58-fce8bc8292a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575974903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1575974903
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.2496971866
Short name T241
Test name
Test status
Simulation time 850314454 ps
CPU time 21.11 seconds
Started Jun 29 05:48:12 PM PDT 24
Finished Jun 29 05:48:33 PM PDT 24
Peak memory 251124 kb
Host smart-1e4ef1f2-b75c-47e8-8cff-612450445c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496971866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2496971866
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1657811805
Short name T517
Test name
Test status
Simulation time 122678695 ps
CPU time 6.3 seconds
Started Jun 29 05:48:12 PM PDT 24
Finished Jun 29 05:48:19 PM PDT 24
Peak memory 246968 kb
Host smart-51d04287-9126-4cd0-b2e7-3001115ec826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657811805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1657811805
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.1716962374
Short name T725
Test name
Test status
Simulation time 3861178947 ps
CPU time 125.36 seconds
Started Jun 29 05:48:21 PM PDT 24
Finished Jun 29 05:50:27 PM PDT 24
Peak memory 251140 kb
Host smart-dab8d2c6-9d20-4691-8f20-049741438ca0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716962374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.1716962374
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1743263472
Short name T266
Test name
Test status
Simulation time 18671941 ps
CPU time 0.76 seconds
Started Jun 29 05:48:13 PM PDT 24
Finished Jun 29 05:48:14 PM PDT 24
Peak memory 207296 kb
Host smart-1e350d55-fe93-4805-ba22-0d0cde518964
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743263472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.1743263472
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.773215715
Short name T426
Test name
Test status
Simulation time 57371103 ps
CPU time 1.1 seconds
Started Jun 29 05:48:31 PM PDT 24
Finished Jun 29 05:48:33 PM PDT 24
Peak memory 209184 kb
Host smart-6240e24d-7f13-42a5-be5d-c91a66d99f70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773215715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.773215715
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.647136665
Short name T637
Test name
Test status
Simulation time 250083337 ps
CPU time 13.36 seconds
Started Jun 29 05:48:21 PM PDT 24
Finished Jun 29 05:48:35 PM PDT 24
Peak memory 226252 kb
Host smart-4c36f896-6f37-4399-9c37-c8e64208ecf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647136665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.647136665
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1599335812
Short name T338
Test name
Test status
Simulation time 748147487 ps
CPU time 5.71 seconds
Started Jun 29 05:48:30 PM PDT 24
Finished Jun 29 05:48:36 PM PDT 24
Peak memory 217592 kb
Host smart-84d54ce0-f0d2-4e81-8875-2ddc0dcc74a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599335812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.1599335812
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.2052645321
Short name T427
Test name
Test status
Simulation time 1269982653 ps
CPU time 40.01 seconds
Started Jun 29 05:48:30 PM PDT 24
Finished Jun 29 05:49:11 PM PDT 24
Peak memory 218420 kb
Host smart-22c9e189-92c8-4e0c-8442-d30ce4d11685
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052645321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.2052645321
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.2688297668
Short name T285
Test name
Test status
Simulation time 75393870 ps
CPU time 3.11 seconds
Started Jun 29 05:48:31 PM PDT 24
Finished Jun 29 05:48:34 PM PDT 24
Peak memory 218412 kb
Host smart-d5053b42-4592-406a-9dc2-9fcf9a887893
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688297668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.2688297668
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.808046234
Short name T349
Test name
Test status
Simulation time 568384941 ps
CPU time 14.19 seconds
Started Jun 29 05:48:21 PM PDT 24
Finished Jun 29 05:48:36 PM PDT 24
Peak memory 217876 kb
Host smart-48729d28-c628-43b4-b42a-9762c61d7786
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808046234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke.
808046234
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.270470904
Short name T590
Test name
Test status
Simulation time 2412597580 ps
CPU time 86.47 seconds
Started Jun 29 05:48:21 PM PDT 24
Finished Jun 29 05:49:48 PM PDT 24
Peak memory 283944 kb
Host smart-80f100d8-dcf9-4009-a33b-47af4468983f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270470904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_state_failure.270470904
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3482451312
Short name T783
Test name
Test status
Simulation time 1068745994 ps
CPU time 19.54 seconds
Started Jun 29 05:48:24 PM PDT 24
Finished Jun 29 05:48:44 PM PDT 24
Peak memory 251116 kb
Host smart-6ca4733d-be0e-4ae1-8130-fddd6841a865
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482451312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3482451312
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.376155234
Short name T291
Test name
Test status
Simulation time 140614442 ps
CPU time 1.96 seconds
Started Jun 29 05:48:20 PM PDT 24
Finished Jun 29 05:48:23 PM PDT 24
Peak memory 222264 kb
Host smart-3bfaef8c-84d3-4fb9-b2da-3e19ab78f2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376155234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.376155234
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1274899472
Short name T94
Test name
Test status
Simulation time 358180407 ps
CPU time 11.77 seconds
Started Jun 29 05:48:28 PM PDT 24
Finished Jun 29 05:48:40 PM PDT 24
Peak memory 225860 kb
Host smart-d991e93c-7d65-433a-8956-00bdea7948b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274899472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1274899472
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2560122696
Short name T309
Test name
Test status
Simulation time 672834584 ps
CPU time 8.96 seconds
Started Jun 29 05:48:27 PM PDT 24
Finished Jun 29 05:48:37 PM PDT 24
Peak memory 218524 kb
Host smart-6688d1b6-409f-4de3-9c60-a5921a79f6d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560122696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2560122696
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3978500346
Short name T730
Test name
Test status
Simulation time 285627069 ps
CPU time 8.81 seconds
Started Jun 29 05:48:31 PM PDT 24
Finished Jun 29 05:48:40 PM PDT 24
Peak memory 226248 kb
Host smart-06cba8c4-9e31-4e50-a480-b4e64a740535
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978500346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
3978500346
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.3270400834
Short name T48
Test name
Test status
Simulation time 389512713 ps
CPU time 8.6 seconds
Started Jun 29 05:48:22 PM PDT 24
Finished Jun 29 05:48:31 PM PDT 24
Peak memory 218496 kb
Host smart-46605f85-4ff7-488d-b212-cc5b82c8be26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270400834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.3270400834
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.1367884990
Short name T814
Test name
Test status
Simulation time 143224309 ps
CPU time 2.36 seconds
Started Jun 29 05:48:21 PM PDT 24
Finished Jun 29 05:48:23 PM PDT 24
Peak memory 222776 kb
Host smart-a27be7fc-01b1-475e-9a05-e0af5d956113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367884990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.1367884990
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2832130246
Short name T561
Test name
Test status
Simulation time 453985102 ps
CPU time 28.23 seconds
Started Jun 29 05:48:24 PM PDT 24
Finished Jun 29 05:48:53 PM PDT 24
Peak memory 251064 kb
Host smart-1d299b73-aef5-4f28-b4d6-247cb7807c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832130246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2832130246
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.750390866
Short name T350
Test name
Test status
Simulation time 337671213 ps
CPU time 6.17 seconds
Started Jun 29 05:48:24 PM PDT 24
Finished Jun 29 05:48:31 PM PDT 24
Peak memory 247092 kb
Host smart-27ddea16-e65c-40bc-a26f-7bb4b7862f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750390866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.750390866
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.2895295583
Short name T150
Test name
Test status
Simulation time 26290964397 ps
CPU time 806.21 seconds
Started Jun 29 05:48:30 PM PDT 24
Finished Jun 29 06:01:57 PM PDT 24
Peak memory 284016 kb
Host smart-24a2f7e8-21b9-4ad8-91f4-f5f653c0caf8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2895295583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.2895295583
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1158954845
Short name T311
Test name
Test status
Simulation time 20079423 ps
CPU time 0.86 seconds
Started Jun 29 05:48:22 PM PDT 24
Finished Jun 29 05:48:23 PM PDT 24
Peak memory 212136 kb
Host smart-bcd076c5-7d38-4af8-b5e0-9e3a5f670f2c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158954845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.1158954845
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.3811303393
Short name T297
Test name
Test status
Simulation time 28418605 ps
CPU time 0.88 seconds
Started Jun 29 05:48:38 PM PDT 24
Finished Jun 29 05:48:40 PM PDT 24
Peak memory 208964 kb
Host smart-5ecb7f44-db27-4880-aa7b-05a64938fbe1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811303393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.3811303393
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.34511471
Short name T262
Test name
Test status
Simulation time 479333305 ps
CPU time 15.65 seconds
Started Jun 29 05:48:39 PM PDT 24
Finished Jun 29 05:48:55 PM PDT 24
Peak memory 218412 kb
Host smart-9f867ca6-3ac8-4f26-bea5-ea39c11a9602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34511471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.34511471
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.595220243
Short name T69
Test name
Test status
Simulation time 901781472 ps
CPU time 20.61 seconds
Started Jun 29 05:48:38 PM PDT 24
Finished Jun 29 05:48:59 PM PDT 24
Peak memory 217616 kb
Host smart-42e7b599-e5c8-4705-a7cd-f2e70078d86e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595220243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.595220243
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.1500898786
Short name T496
Test name
Test status
Simulation time 4130791613 ps
CPU time 38.34 seconds
Started Jun 29 05:48:38 PM PDT 24
Finished Jun 29 05:49:17 PM PDT 24
Peak memory 226288 kb
Host smart-22c4c6b1-bed5-458f-9f79-71d7696c2f3c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500898786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.1500898786
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2015422469
Short name T513
Test name
Test status
Simulation time 1274619469 ps
CPU time 17.29 seconds
Started Jun 29 05:48:37 PM PDT 24
Finished Jun 29 05:48:54 PM PDT 24
Peak memory 218400 kb
Host smart-da60c757-d8d7-410b-b21d-db8fcc975396
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015422469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.2015422469
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.3772113246
Short name T731
Test name
Test status
Simulation time 399248458 ps
CPU time 11.15 seconds
Started Jun 29 05:48:39 PM PDT 24
Finished Jun 29 05:48:51 PM PDT 24
Peak memory 217916 kb
Host smart-83dcd4af-e80c-42fc-94f3-94b3af9057dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772113246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.3772113246
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.683256372
Short name T836
Test name
Test status
Simulation time 5740006930 ps
CPU time 40.59 seconds
Started Jun 29 05:48:38 PM PDT 24
Finished Jun 29 05:49:19 PM PDT 24
Peak memory 275756 kb
Host smart-65fe523e-920b-4971-b214-fcf991c4425c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683256372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.683256372
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3373372339
Short name T848
Test name
Test status
Simulation time 357642579 ps
CPU time 10.33 seconds
Started Jun 29 05:48:38 PM PDT 24
Finished Jun 29 05:48:48 PM PDT 24
Peak memory 245964 kb
Host smart-b0dd441a-faa1-4378-808c-bb6a63452d6a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373372339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.3373372339
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1140829259
Short name T102
Test name
Test status
Simulation time 218636338 ps
CPU time 3.12 seconds
Started Jun 29 05:48:37 PM PDT 24
Finished Jun 29 05:48:40 PM PDT 24
Peak memory 218372 kb
Host smart-31387ec3-e72c-4767-9b5c-d7acc20cf224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140829259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1140829259
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.530131395
Short name T641
Test name
Test status
Simulation time 373707508 ps
CPU time 17.79 seconds
Started Jun 29 05:48:37 PM PDT 24
Finished Jun 29 05:48:55 PM PDT 24
Peak memory 219100 kb
Host smart-bc571d68-9698-4a6f-ae55-90a9b423bcd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530131395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.530131395
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.2471322875
Short name T370
Test name
Test status
Simulation time 1661255417 ps
CPU time 11.44 seconds
Started Jun 29 05:48:38 PM PDT 24
Finished Jun 29 05:48:50 PM PDT 24
Peak memory 218460 kb
Host smart-84e450c5-a7c7-4ece-a8ff-57908ddc2e67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471322875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.2471322875
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2486798519
Short name T227
Test name
Test status
Simulation time 633820963 ps
CPU time 12.6 seconds
Started Jun 29 05:48:39 PM PDT 24
Finished Jun 29 05:48:52 PM PDT 24
Peak memory 218436 kb
Host smart-1302d103-4f17-4a39-9b7f-b7bf5d01a63f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486798519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2486798519
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.2261439655
Short name T684
Test name
Test status
Simulation time 242576704 ps
CPU time 9.53 seconds
Started Jun 29 05:48:38 PM PDT 24
Finished Jun 29 05:48:48 PM PDT 24
Peak memory 218484 kb
Host smart-1692d7d1-cb78-4ea9-a15e-713752114660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261439655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2261439655
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2777391528
Short name T312
Test name
Test status
Simulation time 89036674 ps
CPU time 2.2 seconds
Started Jun 29 05:48:28 PM PDT 24
Finished Jun 29 05:48:30 PM PDT 24
Peak memory 217928 kb
Host smart-35f8e837-07dc-46c5-b1d8-8bbd5be6e639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777391528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2777391528
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2422866301
Short name T824
Test name
Test status
Simulation time 738170713 ps
CPU time 29.17 seconds
Started Jun 29 05:48:29 PM PDT 24
Finished Jun 29 05:48:58 PM PDT 24
Peak memory 251144 kb
Host smart-fc524c3c-276c-4cd9-b90c-c29c256af71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422866301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2422866301
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.4012131735
Short name T593
Test name
Test status
Simulation time 58140843 ps
CPU time 7.38 seconds
Started Jun 29 05:48:30 PM PDT 24
Finished Jun 29 05:48:38 PM PDT 24
Peak memory 251032 kb
Host smart-e97e0596-3f97-4553-a03f-6e20e896b802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012131735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.4012131735
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.3583347773
Short name T555
Test name
Test status
Simulation time 3987292123 ps
CPU time 25.89 seconds
Started Jun 29 05:48:38 PM PDT 24
Finished Jun 29 05:49:04 PM PDT 24
Peak memory 234712 kb
Host smart-cf6dedef-082f-4a3e-a0cd-ab391bddd588
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583347773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.3583347773
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.3348877784
Short name T850
Test name
Test status
Simulation time 86400378714 ps
CPU time 425.09 seconds
Started Jun 29 05:48:37 PM PDT 24
Finished Jun 29 05:55:43 PM PDT 24
Peak memory 313412 kb
Host smart-259508fe-d093-4912-81b4-aeadcca5a2e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3348877784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.3348877784
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2402150658
Short name T29
Test name
Test status
Simulation time 41815490 ps
CPU time 0.78 seconds
Started Jun 29 05:48:29 PM PDT 24
Finished Jun 29 05:48:30 PM PDT 24
Peak memory 208652 kb
Host smart-a0eceb24-8e7d-4b54-8bda-fb44a3576c6e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402150658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.2402150658
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3449150668
Short name T541
Test name
Test status
Simulation time 21034557 ps
CPU time 0.97 seconds
Started Jun 29 05:48:49 PM PDT 24
Finished Jun 29 05:48:51 PM PDT 24
Peak memory 209172 kb
Host smart-cb3e5960-0fd3-471f-9c23-596ff5cc2da5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449150668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3449150668
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3764867883
Short name T857
Test name
Test status
Simulation time 413392427 ps
CPU time 9.88 seconds
Started Jun 29 05:48:48 PM PDT 24
Finished Jun 29 05:48:58 PM PDT 24
Peak memory 218432 kb
Host smart-871377d8-afaa-4100-b63b-506fabb84ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764867883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3764867883
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3166383170
Short name T500
Test name
Test status
Simulation time 771196756 ps
CPU time 5.83 seconds
Started Jun 29 05:48:49 PM PDT 24
Finished Jun 29 05:48:56 PM PDT 24
Peak memory 217636 kb
Host smart-5e495468-a90d-4543-94b1-b54502c29043
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166383170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3166383170
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.3743552499
Short name T369
Test name
Test status
Simulation time 3410853223 ps
CPU time 71.33 seconds
Started Jun 29 05:48:50 PM PDT 24
Finished Jun 29 05:50:02 PM PDT 24
Peak memory 219476 kb
Host smart-abfc2e35-16cd-4ba8-9ea7-55b15ba0496f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743552499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.3743552499
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3267002308
Short name T270
Test name
Test status
Simulation time 1408120867 ps
CPU time 8.24 seconds
Started Jun 29 05:48:49 PM PDT 24
Finished Jun 29 05:48:58 PM PDT 24
Peak memory 223412 kb
Host smart-8eebabe4-da93-4031-8ff1-9ea949cfcd4f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267002308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3267002308
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2520227015
Short name T292
Test name
Test status
Simulation time 542356088 ps
CPU time 3.67 seconds
Started Jun 29 05:48:48 PM PDT 24
Finished Jun 29 05:48:52 PM PDT 24
Peak memory 217912 kb
Host smart-fbb8ade4-d9c7-4cd8-8d0f-51b205cd7d31
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520227015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2520227015
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.2035235856
Short name T411
Test name
Test status
Simulation time 2924156930 ps
CPU time 45.79 seconds
Started Jun 29 05:48:49 PM PDT 24
Finished Jun 29 05:49:35 PM PDT 24
Peak memory 275772 kb
Host smart-ba1e0164-fca3-4c89-b744-e53078420fcb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035235856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.2035235856
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.369732009
Short name T409
Test name
Test status
Simulation time 2131993128 ps
CPU time 21.03 seconds
Started Jun 29 05:48:50 PM PDT 24
Finished Jun 29 05:49:12 PM PDT 24
Peak memory 251116 kb
Host smart-bd2cf2c9-70fc-4656-b16c-9fc93733a6a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369732009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_
jtag_state_post_trans.369732009
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3691276536
Short name T654
Test name
Test status
Simulation time 48655967 ps
CPU time 1.49 seconds
Started Jun 29 05:48:47 PM PDT 24
Finished Jun 29 05:48:49 PM PDT 24
Peak memory 218388 kb
Host smart-8f4787b5-b3a9-4ab3-b630-c34c0a2a19d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691276536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3691276536
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.147205778
Short name T159
Test name
Test status
Simulation time 980872223 ps
CPU time 12.31 seconds
Started Jun 29 05:48:50 PM PDT 24
Finished Jun 29 05:49:03 PM PDT 24
Peak memory 218436 kb
Host smart-dfca142a-b001-49c9-9cd2-2731eef941eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147205778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.147205778
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.3987328626
Short name T234
Test name
Test status
Simulation time 843670857 ps
CPU time 17.1 seconds
Started Jun 29 05:48:48 PM PDT 24
Finished Jun 29 05:49:06 PM PDT 24
Peak memory 218424 kb
Host smart-445c4b8e-a0d7-4d92-a815-656363f8d851
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987328626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.3987328626
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1551346905
Short name T483
Test name
Test status
Simulation time 227159395 ps
CPU time 8.02 seconds
Started Jun 29 05:48:47 PM PDT 24
Finished Jun 29 05:48:55 PM PDT 24
Peak memory 226264 kb
Host smart-2ed0f569-afb9-4b86-bbb4-c3ba249c4782
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551346905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1551346905
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.1189269627
Short name T769
Test name
Test status
Simulation time 413404635 ps
CPU time 11.84 seconds
Started Jun 29 05:48:47 PM PDT 24
Finished Jun 29 05:49:00 PM PDT 24
Peak memory 218400 kb
Host smart-8177fb8f-111e-4df7-b9d4-6ac79a31b93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189269627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.1189269627
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.3073562947
Short name T65
Test name
Test status
Simulation time 143855521 ps
CPU time 1.76 seconds
Started Jun 29 05:48:38 PM PDT 24
Finished Jun 29 05:48:41 PM PDT 24
Peak memory 214224 kb
Host smart-de6aabcd-24a1-4422-b59e-be6eebea806c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073562947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.3073562947
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2063969280
Short name T251
Test name
Test status
Simulation time 1685755994 ps
CPU time 31.08 seconds
Started Jun 29 05:48:49 PM PDT 24
Finished Jun 29 05:49:20 PM PDT 24
Peak memory 251100 kb
Host smart-43b7cf9d-3e7a-4c48-a2bd-76277b70378c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063969280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2063969280
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2081135207
Short name T768
Test name
Test status
Simulation time 312007685 ps
CPU time 6.73 seconds
Started Jun 29 05:48:49 PM PDT 24
Finished Jun 29 05:48:56 PM PDT 24
Peak memory 242944 kb
Host smart-2eb7b342-7832-4c8a-8db7-181e155934d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081135207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2081135207
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.819614655
Short name T217
Test name
Test status
Simulation time 2650762250 ps
CPU time 78.02 seconds
Started Jun 29 05:48:50 PM PDT 24
Finished Jun 29 05:50:09 PM PDT 24
Peak memory 248800 kb
Host smart-e9ae07cc-aece-4249-a31e-eda77d9b481a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819614655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.819614655
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.1039714518
Short name T445
Test name
Test status
Simulation time 50272206605 ps
CPU time 485.28 seconds
Started Jun 29 05:48:49 PM PDT 24
Finished Jun 29 05:56:55 PM PDT 24
Peak memory 338344 kb
Host smart-ae16b326-94f5-4d4d-a925-782bc57e9d93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1039714518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.1039714518
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.4090970174
Short name T247
Test name
Test status
Simulation time 46376741 ps
CPU time 0.9 seconds
Started Jun 29 05:48:50 PM PDT 24
Finished Jun 29 05:48:51 PM PDT 24
Peak memory 212160 kb
Host smart-b3ecb313-20c3-468b-946c-61509c29fca5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090970174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.4090970174
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.75874244
Short name T656
Test name
Test status
Simulation time 43628623 ps
CPU time 0.95 seconds
Started Jun 29 05:48:58 PM PDT 24
Finished Jun 29 05:48:59 PM PDT 24
Peak memory 209112 kb
Host smart-0844ad52-d1b5-4a19-b02a-792e9c987e37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75874244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.75874244
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.182971899
Short name T692
Test name
Test status
Simulation time 1483138919 ps
CPU time 17.26 seconds
Started Jun 29 05:48:49 PM PDT 24
Finished Jun 29 05:49:07 PM PDT 24
Peak memory 226248 kb
Host smart-4372c994-6ebc-4ee7-8a78-9884ef7eeb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182971899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.182971899
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.3207277555
Short name T384
Test name
Test status
Simulation time 698606753 ps
CPU time 7.71 seconds
Started Jun 29 05:48:56 PM PDT 24
Finished Jun 29 05:49:04 PM PDT 24
Peak memory 217652 kb
Host smart-936955c2-7403-413b-96e4-fcf97ed21b67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207277555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.3207277555
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.5477826
Short name T233
Test name
Test status
Simulation time 1844618928 ps
CPU time 58.8 seconds
Started Jun 29 05:48:57 PM PDT 24
Finished Jun 29 05:49:56 PM PDT 24
Peak memory 218432 kb
Host smart-51875c08-a3c9-412a-b834-c8b760c23f96
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5477826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc
_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_erro
rs.5477826
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1729056800
Short name T304
Test name
Test status
Simulation time 1335605895 ps
CPU time 6.16 seconds
Started Jun 29 05:48:57 PM PDT 24
Finished Jun 29 05:49:04 PM PDT 24
Peak memory 218500 kb
Host smart-d766e468-c5a2-4d26-b503-c430fa49cc4c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729056800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.1729056800
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.4014380314
Short name T586
Test name
Test status
Simulation time 105541906 ps
CPU time 2.55 seconds
Started Jun 29 05:48:47 PM PDT 24
Finished Jun 29 05:48:50 PM PDT 24
Peak memory 217940 kb
Host smart-0b6341c6-185d-4e3c-9866-201d4176ad52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014380314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.4014380314
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3382960079
Short name T651
Test name
Test status
Simulation time 8597968632 ps
CPU time 90.01 seconds
Started Jun 29 05:48:47 PM PDT 24
Finished Jun 29 05:50:18 PM PDT 24
Peak memory 280584 kb
Host smart-cbb6ed43-cdfd-4663-90e2-7877c6cdf83b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382960079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3382960079
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.120197827
Short name T249
Test name
Test status
Simulation time 930820959 ps
CPU time 19.76 seconds
Started Jun 29 05:48:59 PM PDT 24
Finished Jun 29 05:49:19 PM PDT 24
Peak memory 251116 kb
Host smart-ba56d8ab-66ef-43bc-8f23-62e24692c444
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120197827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_
jtag_state_post_trans.120197827
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.1489408414
Short name T403
Test name
Test status
Simulation time 110507119 ps
CPU time 1.92 seconds
Started Jun 29 05:48:49 PM PDT 24
Finished Jun 29 05:48:52 PM PDT 24
Peak memory 218428 kb
Host smart-dcd0e71e-d05e-4855-b92c-3985dca87806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489408414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.1489408414
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.567403058
Short name T698
Test name
Test status
Simulation time 670373957 ps
CPU time 10.13 seconds
Started Jun 29 05:48:55 PM PDT 24
Finished Jun 29 05:49:06 PM PDT 24
Peak memory 219168 kb
Host smart-2d44b08d-e938-4ad2-940d-8544c95640dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567403058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.567403058
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3754393889
Short name T413
Test name
Test status
Simulation time 762604921 ps
CPU time 9.48 seconds
Started Jun 29 05:48:57 PM PDT 24
Finished Jun 29 05:49:07 PM PDT 24
Peak memory 218400 kb
Host smart-46ed34c7-aa1b-48cd-982e-1d74c39e628a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754393889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.3754393889
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.3152536242
Short name T762
Test name
Test status
Simulation time 1111006827 ps
CPU time 8.17 seconds
Started Jun 29 05:48:55 PM PDT 24
Finished Jun 29 05:49:03 PM PDT 24
Peak memory 218436 kb
Host smart-c362bd74-5556-4d02-9bcc-3d71d4661f93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152536242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
3152536242
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.358569702
Short name T465
Test name
Test status
Simulation time 1194781092 ps
CPU time 8.94 seconds
Started Jun 29 05:48:49 PM PDT 24
Finished Jun 29 05:48:59 PM PDT 24
Peak memory 218496 kb
Host smart-631551fb-109a-41f1-8642-d923d3e19a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358569702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.358569702
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.2847598380
Short name T78
Test name
Test status
Simulation time 73185785 ps
CPU time 2.44 seconds
Started Jun 29 05:48:47 PM PDT 24
Finished Jun 29 05:48:50 PM PDT 24
Peak memory 217932 kb
Host smart-df3eb6d6-a151-4434-8273-c03114ad9abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847598380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2847598380
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.1709663928
Short name T536
Test name
Test status
Simulation time 105449597 ps
CPU time 3.8 seconds
Started Jun 29 05:48:47 PM PDT 24
Finished Jun 29 05:48:52 PM PDT 24
Peak memory 222844 kb
Host smart-3c6167d0-a7a9-487e-aa3c-5a0e1b07ee80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709663928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1709663928
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.2591621874
Short name T336
Test name
Test status
Simulation time 23929858484 ps
CPU time 233.64 seconds
Started Jun 29 05:48:58 PM PDT 24
Finished Jun 29 05:52:52 PM PDT 24
Peak memory 226148 kb
Host smart-0566c1b8-b254-4074-a1dc-e92395b573c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591621874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.2591621874
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.2678852440
Short name T274
Test name
Test status
Simulation time 77245881141 ps
CPU time 407.27 seconds
Started Jun 29 05:48:57 PM PDT 24
Finished Jun 29 05:55:44 PM PDT 24
Peak memory 333204 kb
Host smart-8d38fee9-c025-42dd-9eeb-231e3139707c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2678852440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.2678852440
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.476980604
Short name T690
Test name
Test status
Simulation time 15517415 ps
CPU time 0.91 seconds
Started Jun 29 05:48:49 PM PDT 24
Finished Jun 29 05:48:50 PM PDT 24
Peak memory 212056 kb
Host smart-c4233e77-a549-4d05-acaf-8afc5276a95d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476980604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct
rl_volatile_unlock_smoke.476980604
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.468073334
Short name T480
Test name
Test status
Simulation time 54952398 ps
CPU time 0.93 seconds
Started Jun 29 05:45:49 PM PDT 24
Finished Jun 29 05:45:50 PM PDT 24
Peak memory 208988 kb
Host smart-663260a3-972c-4199-8518-976b8bf54a49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468073334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.468073334
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2893221241
Short name T646
Test name
Test status
Simulation time 4274158556 ps
CPU time 9.75 seconds
Started Jun 29 05:45:23 PM PDT 24
Finished Jun 29 05:45:33 PM PDT 24
Peak memory 219160 kb
Host smart-d377d835-03be-4ab3-ad89-4cd645b96dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893221241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2893221241
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.2458552616
Short name T26
Test name
Test status
Simulation time 173391116 ps
CPU time 3.21 seconds
Started Jun 29 05:45:29 PM PDT 24
Finished Jun 29 05:45:33 PM PDT 24
Peak memory 217396 kb
Host smart-c20a7062-38a3-4168-b879-03ca8697fdcb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458552616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.2458552616
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.3864644155
Short name T344
Test name
Test status
Simulation time 3072743647 ps
CPU time 78.99 seconds
Started Jun 29 05:45:29 PM PDT 24
Finished Jun 29 05:46:48 PM PDT 24
Peak memory 219152 kb
Host smart-c7877244-cddb-480c-8b79-88ffc78dc240
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864644155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.3864644155
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2514714401
Short name T743
Test name
Test status
Simulation time 822444245 ps
CPU time 7.42 seconds
Started Jun 29 05:45:31 PM PDT 24
Finished Jun 29 05:45:39 PM PDT 24
Peak memory 218428 kb
Host smart-61084c62-eee2-4c78-9a2d-c989098ec888
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514714401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2514714401
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.359229979
Short name T774
Test name
Test status
Simulation time 2801455050 ps
CPU time 20.11 seconds
Started Jun 29 05:45:38 PM PDT 24
Finished Jun 29 05:45:58 PM PDT 24
Peak memory 217976 kb
Host smart-eb606dd9-0777-4d64-bcc2-cf1adbe3ef63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359229979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_regwen_during_op.359229979
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.3122526844
Short name T863
Test name
Test status
Simulation time 1055461216 ps
CPU time 7.64 seconds
Started Jun 29 05:45:29 PM PDT 24
Finished Jun 29 05:45:37 PM PDT 24
Peak memory 217916 kb
Host smart-bebdb56b-0b67-4bbe-b312-8516fc95df92
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122526844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
3122526844
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.3264094484
Short name T434
Test name
Test status
Simulation time 3705525547 ps
CPU time 59.06 seconds
Started Jun 29 05:45:30 PM PDT 24
Finished Jun 29 05:46:29 PM PDT 24
Peak memory 251180 kb
Host smart-64881d91-812a-46ac-8ee1-059f495756f8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264094484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.3264094484
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3027168510
Short name T385
Test name
Test status
Simulation time 3925081721 ps
CPU time 13 seconds
Started Jun 29 05:45:30 PM PDT 24
Finished Jun 29 05:45:43 PM PDT 24
Peak memory 225880 kb
Host smart-c7d57606-e9fa-451a-8fb4-0c44c507085a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027168510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.3027168510
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2126647111
Short name T524
Test name
Test status
Simulation time 348053477 ps
CPU time 2.59 seconds
Started Jun 29 05:45:22 PM PDT 24
Finished Jun 29 05:45:25 PM PDT 24
Peak memory 218428 kb
Host smart-c5b5856c-20b3-4b68-bd0e-e3210c30282d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126647111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2126647111
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.3251018817
Short name T169
Test name
Test status
Simulation time 950179414 ps
CPU time 8.98 seconds
Started Jun 29 05:45:30 PM PDT 24
Finished Jun 29 05:45:39 PM PDT 24
Peak memory 217872 kb
Host smart-56538a64-574f-4494-bff4-41beea0058f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251018817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3251018817
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.2675579137
Short name T454
Test name
Test status
Simulation time 604146735 ps
CPU time 13.36 seconds
Started Jun 29 05:45:37 PM PDT 24
Finished Jun 29 05:45:51 PM PDT 24
Peak memory 226240 kb
Host smart-1a8ae3f2-b4fd-4e9e-b408-edace7b406cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675579137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2675579137
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3263237567
Short name T842
Test name
Test status
Simulation time 1125488952 ps
CPU time 13.11 seconds
Started Jun 29 05:45:38 PM PDT 24
Finished Jun 29 05:45:51 PM PDT 24
Peak memory 218452 kb
Host smart-e7984ee6-afc6-404d-a291-4ec0255fe286
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263237567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.3263237567
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1919090806
Short name T252
Test name
Test status
Simulation time 773950164 ps
CPU time 8.21 seconds
Started Jun 29 05:45:37 PM PDT 24
Finished Jun 29 05:45:45 PM PDT 24
Peak memory 218416 kb
Host smart-e79aad66-1440-44dc-a0cb-a369e2ea0c10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919090806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.1
919090806
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.1670504441
Short name T340
Test name
Test status
Simulation time 5467020734 ps
CPU time 11.99 seconds
Started Jun 29 05:45:23 PM PDT 24
Finished Jun 29 05:45:35 PM PDT 24
Peak memory 218680 kb
Host smart-cca56852-0de0-4ec9-8896-92df18361d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670504441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1670504441
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.4065974545
Short name T564
Test name
Test status
Simulation time 162427970 ps
CPU time 2.2 seconds
Started Jun 29 05:45:20 PM PDT 24
Finished Jun 29 05:45:23 PM PDT 24
Peak memory 214376 kb
Host smart-5dbfe087-d8e8-44f0-b402-83307746a120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065974545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.4065974545
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.3957627108
Short name T242
Test name
Test status
Simulation time 45330577 ps
CPU time 6.36 seconds
Started Jun 29 05:45:21 PM PDT 24
Finished Jun 29 05:45:28 PM PDT 24
Peak memory 250584 kb
Host smart-5db96a70-43af-421a-b51f-9b3a8f6f082c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957627108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3957627108
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1288158772
Short name T430
Test name
Test status
Simulation time 76776709253 ps
CPU time 139.06 seconds
Started Jun 29 05:45:48 PM PDT 24
Finished Jun 29 05:48:07 PM PDT 24
Peak memory 316648 kb
Host smart-dcff6f8d-63d7-4d16-b021-14e767f3bf67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288158772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1288158772
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2719937218
Short name T549
Test name
Test status
Simulation time 20498241 ps
CPU time 1 seconds
Started Jun 29 05:45:21 PM PDT 24
Finished Jun 29 05:45:22 PM PDT 24
Peak memory 212084 kb
Host smart-7af9e2af-a4fc-450c-bf43-f14bc37ba4d1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719937218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.2719937218
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.304257443
Short name T540
Test name
Test status
Simulation time 38556732 ps
CPU time 1.2 seconds
Started Jun 29 05:49:04 PM PDT 24
Finished Jun 29 05:49:06 PM PDT 24
Peak memory 209264 kb
Host smart-93a2e15f-b928-47f4-8639-8195d061d058
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304257443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.304257443
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3410632657
Short name T734
Test name
Test status
Simulation time 1020394487 ps
CPU time 12.7 seconds
Started Jun 29 05:48:56 PM PDT 24
Finished Jun 29 05:49:09 PM PDT 24
Peak memory 218276 kb
Host smart-e6ab1dba-1a83-4d95-83fb-af809bc7bf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410632657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3410632657
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.838010722
Short name T737
Test name
Test status
Simulation time 9200540625 ps
CPU time 12.62 seconds
Started Jun 29 05:48:57 PM PDT 24
Finished Jun 29 05:49:11 PM PDT 24
Peak memory 217936 kb
Host smart-fd9031f1-a3e1-42b0-84ac-fa5e73dbbe08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838010722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.838010722
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.1287934438
Short name T728
Test name
Test status
Simulation time 200628002 ps
CPU time 2.28 seconds
Started Jun 29 05:48:59 PM PDT 24
Finished Jun 29 05:49:02 PM PDT 24
Peak memory 222472 kb
Host smart-ebd5466f-9629-4866-8b52-9c129fbeba26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287934438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1287934438
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.2247633949
Short name T320
Test name
Test status
Simulation time 707595059 ps
CPU time 15.36 seconds
Started Jun 29 05:48:56 PM PDT 24
Finished Jun 29 05:49:12 PM PDT 24
Peak memory 226356 kb
Host smart-0b105c7d-78d4-480c-8da5-3a377c5b729e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247633949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2247633949
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.828656463
Short name T707
Test name
Test status
Simulation time 920069907 ps
CPU time 7.47 seconds
Started Jun 29 05:48:59 PM PDT 24
Finished Jun 29 05:49:07 PM PDT 24
Peak memory 218332 kb
Host smart-46dd1c8a-503a-496b-a595-ef1c1a4dd2ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828656463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.828656463
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.4130172839
Short name T351
Test name
Test status
Simulation time 332589971 ps
CPU time 8.57 seconds
Started Jun 29 05:48:56 PM PDT 24
Finished Jun 29 05:49:05 PM PDT 24
Peak memory 218500 kb
Host smart-b8d18e7d-a91f-4fc9-b480-729226b552e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130172839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.4130172839
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.2865225918
Short name T724
Test name
Test status
Simulation time 1272832010 ps
CPU time 10.52 seconds
Started Jun 29 05:48:58 PM PDT 24
Finished Jun 29 05:49:09 PM PDT 24
Peak memory 217972 kb
Host smart-23a5567c-a9e6-4041-91ec-0ff3b9199716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865225918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.2865225918
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.1893973019
Short name T722
Test name
Test status
Simulation time 150543009 ps
CPU time 16.74 seconds
Started Jun 29 05:48:56 PM PDT 24
Finished Jun 29 05:49:13 PM PDT 24
Peak memory 251200 kb
Host smart-81509b1d-13eb-47e5-8e83-6c95930fe5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893973019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1893973019
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.2234504485
Short name T416
Test name
Test status
Simulation time 49891805 ps
CPU time 7.39 seconds
Started Jun 29 05:48:58 PM PDT 24
Finished Jun 29 05:49:05 PM PDT 24
Peak memory 251116 kb
Host smart-f97df801-1b11-4d2d-ac93-9a68f3f65f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234504485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2234504485
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2990385259
Short name T614
Test name
Test status
Simulation time 59988826474 ps
CPU time 296.84 seconds
Started Jun 29 05:49:05 PM PDT 24
Finished Jun 29 05:54:02 PM PDT 24
Peak memory 283120 kb
Host smart-f4dd805d-bfa8-4c39-beb0-427bbdf40aca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990385259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2990385259
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2223120966
Short name T220
Test name
Test status
Simulation time 161402488 ps
CPU time 0.99 seconds
Started Jun 29 05:48:57 PM PDT 24
Finished Jun 29 05:48:58 PM PDT 24
Peak memory 212220 kb
Host smart-7dc06b0b-d1f0-4440-b0ec-312d65bd9e83
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223120966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2223120966
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.2842945122
Short name T331
Test name
Test status
Simulation time 45070313 ps
CPU time 1 seconds
Started Jun 29 05:49:04 PM PDT 24
Finished Jun 29 05:49:05 PM PDT 24
Peak memory 209168 kb
Host smart-de7aa9c9-20e0-4773-96c1-1b953ac03f48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842945122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2842945122
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.4065659711
Short name T785
Test name
Test status
Simulation time 363378191 ps
CPU time 16.33 seconds
Started Jun 29 05:49:04 PM PDT 24
Finished Jun 29 05:49:20 PM PDT 24
Peak memory 218336 kb
Host smart-03ecd846-9628-4a77-9427-f55c7a97d22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065659711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.4065659711
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.2680274306
Short name T8
Test name
Test status
Simulation time 308770598 ps
CPU time 2.55 seconds
Started Jun 29 05:49:03 PM PDT 24
Finished Jun 29 05:49:06 PM PDT 24
Peak memory 217232 kb
Host smart-0634a72b-732c-4841-bc5a-7b6d5485f436
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680274306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.2680274306
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3379716290
Short name T791
Test name
Test status
Simulation time 201938000 ps
CPU time 2.74 seconds
Started Jun 29 05:49:06 PM PDT 24
Finished Jun 29 05:49:09 PM PDT 24
Peak memory 218404 kb
Host smart-b06ffc20-66f6-4940-8e3e-f48b8a5f4159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379716290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3379716290
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1273448203
Short name T592
Test name
Test status
Simulation time 656541264 ps
CPU time 11.98 seconds
Started Jun 29 05:49:05 PM PDT 24
Finished Jun 29 05:49:17 PM PDT 24
Peak memory 226240 kb
Host smart-235c7733-b4a4-47f3-a50f-651139c3b3bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273448203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1273448203
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.3621875971
Short name T231
Test name
Test status
Simulation time 343698590 ps
CPU time 14.68 seconds
Started Jun 29 05:49:04 PM PDT 24
Finished Jun 29 05:49:19 PM PDT 24
Peak memory 218464 kb
Host smart-aca37713-2c67-496a-845b-ff27de83d40f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621875971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.3621875971
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.1755045317
Short name T395
Test name
Test status
Simulation time 1186788554 ps
CPU time 10.37 seconds
Started Jun 29 05:49:05 PM PDT 24
Finished Jun 29 05:49:16 PM PDT 24
Peak memory 218452 kb
Host smart-615ef82b-3185-4d2e-9abe-2b971739e7e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755045317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
1755045317
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2076276457
Short name T438
Test name
Test status
Simulation time 813607926 ps
CPU time 11.17 seconds
Started Jun 29 05:49:05 PM PDT 24
Finished Jun 29 05:49:16 PM PDT 24
Peak memory 226252 kb
Host smart-83356a9f-a960-4338-bfb1-5c9c0af3c9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076276457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2076276457
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1518222824
Short name T80
Test name
Test status
Simulation time 188049614 ps
CPU time 3.64 seconds
Started Jun 29 05:49:08 PM PDT 24
Finished Jun 29 05:49:12 PM PDT 24
Peak memory 217820 kb
Host smart-29218085-898a-4d50-9016-266ee324b895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518222824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1518222824
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.2092751971
Short name T377
Test name
Test status
Simulation time 267684550 ps
CPU time 22.25 seconds
Started Jun 29 05:49:06 PM PDT 24
Finished Jun 29 05:49:28 PM PDT 24
Peak memory 251100 kb
Host smart-010008a9-f6b2-4363-b5bc-b46bac26ba89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092751971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2092751971
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.2627044350
Short name T687
Test name
Test status
Simulation time 1165699539 ps
CPU time 4.59 seconds
Started Jun 29 05:49:07 PM PDT 24
Finished Jun 29 05:49:12 PM PDT 24
Peak memory 226440 kb
Host smart-f4f6f17c-f538-47f2-ae9c-ff1d090c1b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627044350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2627044350
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.857697434
Short name T365
Test name
Test status
Simulation time 60798813032 ps
CPU time 147.19 seconds
Started Jun 29 05:49:03 PM PDT 24
Finished Jun 29 05:51:31 PM PDT 24
Peak memory 259264 kb
Host smart-98af8f16-bfe1-40ed-9296-a3b6d766c4b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857697434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.857697434
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1712866449
Short name T97
Test name
Test status
Simulation time 27828927 ps
CPU time 0.86 seconds
Started Jun 29 05:49:03 PM PDT 24
Finished Jun 29 05:49:04 PM PDT 24
Peak memory 212068 kb
Host smart-888ff4b7-008e-443b-9223-1cde225109ac
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712866449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.1712866449
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2762555050
Short name T87
Test name
Test status
Simulation time 19902768 ps
CPU time 1.17 seconds
Started Jun 29 05:49:12 PM PDT 24
Finished Jun 29 05:49:13 PM PDT 24
Peak memory 209180 kb
Host smart-0b33d58d-3b5a-4c28-b73b-ae56c3b9c318
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762555050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2762555050
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.3588864186
Short name T206
Test name
Test status
Simulation time 1101437544 ps
CPU time 14.68 seconds
Started Jun 29 05:49:13 PM PDT 24
Finished Jun 29 05:49:28 PM PDT 24
Peak memory 218432 kb
Host smart-7b276404-3caa-49b3-ab27-47de7ed4c778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588864186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3588864186
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.511272721
Short name T23
Test name
Test status
Simulation time 675457811 ps
CPU time 7.17 seconds
Started Jun 29 05:49:12 PM PDT 24
Finished Jun 29 05:49:20 PM PDT 24
Peak memory 217596 kb
Host smart-a5fd408b-01f1-4971-8d86-85fdf1398036
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511272721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.511272721
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.47654958
Short name T664
Test name
Test status
Simulation time 127465989 ps
CPU time 2.79 seconds
Started Jun 29 05:49:12 PM PDT 24
Finished Jun 29 05:49:15 PM PDT 24
Peak memory 218428 kb
Host smart-2f81ad1c-8672-471d-a36b-0823796913ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47654958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.47654958
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.1890028738
Short name T376
Test name
Test status
Simulation time 418463611 ps
CPU time 19.29 seconds
Started Jun 29 05:49:15 PM PDT 24
Finished Jun 29 05:49:34 PM PDT 24
Peak memory 218992 kb
Host smart-ce18810a-f3cb-45b7-b31b-8b1954d80e0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890028738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.1890028738
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3340652443
Short name T317
Test name
Test status
Simulation time 246532420 ps
CPU time 7.52 seconds
Started Jun 29 05:49:14 PM PDT 24
Finished Jun 29 05:49:21 PM PDT 24
Peak memory 218492 kb
Host smart-e1333ea0-f771-435a-aa43-997ad07aab90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340652443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3340652443
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2340840677
Short name T398
Test name
Test status
Simulation time 372658998 ps
CPU time 10.41 seconds
Started Jun 29 05:49:11 PM PDT 24
Finished Jun 29 05:49:21 PM PDT 24
Peak memory 218440 kb
Host smart-f8f8ae7b-6a4f-41d0-a528-e58d31c93f57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340840677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2340840677
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.337840731
Short name T860
Test name
Test status
Simulation time 440747834 ps
CPU time 8.81 seconds
Started Jun 29 05:49:13 PM PDT 24
Finished Jun 29 05:49:22 PM PDT 24
Peak memory 218492 kb
Host smart-f21ba9c5-e86f-4042-9b10-856b7e76901b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337840731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.337840731
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.4069646141
Short name T103
Test name
Test status
Simulation time 204866843 ps
CPU time 1.17 seconds
Started Jun 29 05:49:14 PM PDT 24
Finished Jun 29 05:49:16 PM PDT 24
Peak memory 217892 kb
Host smart-636ae1ea-a7c4-4cee-a7e9-68cfcfcb6e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069646141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.4069646141
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.1712221947
Short name T109
Test name
Test status
Simulation time 329929166 ps
CPU time 19.23 seconds
Started Jun 29 05:49:12 PM PDT 24
Finished Jun 29 05:49:31 PM PDT 24
Peak memory 251132 kb
Host smart-aa26cd68-1b14-491e-992b-5b85f4843678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712221947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1712221947
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.356615559
Short name T208
Test name
Test status
Simulation time 251600394 ps
CPU time 6.51 seconds
Started Jun 29 05:49:10 PM PDT 24
Finished Jun 29 05:49:17 PM PDT 24
Peak memory 251060 kb
Host smart-b33af0d3-901d-4006-ab72-b3db04e5941d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356615559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.356615559
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3352240723
Short name T392
Test name
Test status
Simulation time 11205912479 ps
CPU time 107.21 seconds
Started Jun 29 05:49:14 PM PDT 24
Finished Jun 29 05:51:01 PM PDT 24
Peak memory 267812 kb
Host smart-49d9671f-300a-47c4-a424-7cb0617e80c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352240723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3352240723
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.1727699777
Short name T42
Test name
Test status
Simulation time 139633942237 ps
CPU time 700.64 seconds
Started Jun 29 05:49:13 PM PDT 24
Finished Jun 29 06:00:53 PM PDT 24
Peak memory 447888 kb
Host smart-79ae3e19-460f-4e1e-b8c3-f99aca6276c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1727699777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.1727699777
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.1154370798
Short name T191
Test name
Test status
Simulation time 39157967 ps
CPU time 0.9 seconds
Started Jun 29 05:49:11 PM PDT 24
Finished Jun 29 05:49:13 PM PDT 24
Peak memory 213276 kb
Host smart-8f2baa16-4f65-4fad-ba66-66886723b054
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154370798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.1154370798
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1388323773
Short name T727
Test name
Test status
Simulation time 69772194 ps
CPU time 0.99 seconds
Started Jun 29 05:49:20 PM PDT 24
Finished Jun 29 05:49:21 PM PDT 24
Peak memory 209232 kb
Host smart-263429eb-e491-4236-9efb-b167478cd6e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388323773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1388323773
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3545160441
Short name T489
Test name
Test status
Simulation time 769069288 ps
CPU time 10.46 seconds
Started Jun 29 05:49:20 PM PDT 24
Finished Jun 29 05:49:31 PM PDT 24
Peak memory 218432 kb
Host smart-76e70452-77a1-4dca-99ec-ac1fd63f9d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545160441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3545160441
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2600664312
Short name T510
Test name
Test status
Simulation time 238908020 ps
CPU time 3.56 seconds
Started Jun 29 05:49:20 PM PDT 24
Finished Jun 29 05:49:24 PM PDT 24
Peak memory 218428 kb
Host smart-6c9a84b2-c39f-4ab8-b4fc-62ac056655da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600664312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2600664312
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.1968619901
Short name T203
Test name
Test status
Simulation time 220817257 ps
CPU time 9.52 seconds
Started Jun 29 05:49:19 PM PDT 24
Finished Jun 29 05:49:29 PM PDT 24
Peak memory 226236 kb
Host smart-81349377-beda-487c-8a4e-4bbe4cc972cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968619901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1968619901
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.328172160
Short name T623
Test name
Test status
Simulation time 4214635107 ps
CPU time 17.7 seconds
Started Jun 29 05:49:22 PM PDT 24
Finished Jun 29 05:49:40 PM PDT 24
Peak memory 219096 kb
Host smart-db50b582-0a54-448d-bdd3-b52cfbb2c353
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328172160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di
gest.328172160
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3758420137
Short name T612
Test name
Test status
Simulation time 185637642 ps
CPU time 6.1 seconds
Started Jun 29 05:49:19 PM PDT 24
Finished Jun 29 05:49:26 PM PDT 24
Peak memory 226196 kb
Host smart-4701f0ea-a3ba-414d-bb03-c4339726b389
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758420137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
3758420137
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.563939179
Short name T475
Test name
Test status
Simulation time 837526925 ps
CPU time 8.46 seconds
Started Jun 29 05:49:21 PM PDT 24
Finished Jun 29 05:49:30 PM PDT 24
Peak memory 218564 kb
Host smart-1fa1d390-84ad-4e98-87c6-150cfc86719a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563939179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.563939179
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.163664239
Short name T674
Test name
Test status
Simulation time 313664125 ps
CPU time 1.88 seconds
Started Jun 29 05:49:11 PM PDT 24
Finished Jun 29 05:49:14 PM PDT 24
Peak memory 217888 kb
Host smart-ea2a73a4-93d2-43e4-89ae-3d1bef355453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163664239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.163664239
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.3759114119
Short name T310
Test name
Test status
Simulation time 570129586 ps
CPU time 17.22 seconds
Started Jun 29 05:49:21 PM PDT 24
Finished Jun 29 05:49:39 PM PDT 24
Peak memory 251132 kb
Host smart-726a7e8f-6fa3-4e4c-89bc-f49ce3c20782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759114119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3759114119
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2927030295
Short name T417
Test name
Test status
Simulation time 53479121 ps
CPU time 6.48 seconds
Started Jun 29 05:49:19 PM PDT 24
Finished Jun 29 05:49:26 PM PDT 24
Peak memory 250696 kb
Host smart-f3fc7377-0b79-4346-9a8e-624eec17c408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927030295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2927030295
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.791711474
Short name T36
Test name
Test status
Simulation time 10748919822 ps
CPU time 83.94 seconds
Started Jun 29 05:49:21 PM PDT 24
Finished Jun 29 05:50:45 PM PDT 24
Peak memory 251912 kb
Host smart-7ca32bd8-ac2f-4456-afa4-e7e6b0a47765
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791711474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.791711474
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.78115108
Short name T167
Test name
Test status
Simulation time 9250515297 ps
CPU time 353.41 seconds
Started Jun 29 05:49:21 PM PDT 24
Finished Jun 29 05:55:15 PM PDT 24
Peak memory 497004 kb
Host smart-3706575e-4ff9-4ac4-84b5-4a62bfdf9882
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=78115108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.78115108
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1338127928
Short name T658
Test name
Test status
Simulation time 15836457 ps
CPU time 1 seconds
Started Jun 29 05:49:21 PM PDT 24
Finished Jun 29 05:49:22 PM PDT 24
Peak memory 213268 kb
Host smart-019a5410-1c87-42b4-acfe-7f4e7ce0b760
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338127928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.1338127928
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.172789176
Short name T839
Test name
Test status
Simulation time 19855352 ps
CPU time 0.92 seconds
Started Jun 29 05:49:29 PM PDT 24
Finished Jun 29 05:49:31 PM PDT 24
Peak memory 209128 kb
Host smart-bb45b17a-720a-4f58-b766-35df67d66ac4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172789176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.172789176
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2743285895
Short name T648
Test name
Test status
Simulation time 711197992 ps
CPU time 24.95 seconds
Started Jun 29 05:49:30 PM PDT 24
Finished Jun 29 05:49:55 PM PDT 24
Peak memory 226188 kb
Host smart-399b812c-1ce7-424b-88f9-aeb5733776b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743285895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2743285895
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.210302910
Short name T744
Test name
Test status
Simulation time 408582903 ps
CPU time 5.92 seconds
Started Jun 29 05:49:27 PM PDT 24
Finished Jun 29 05:49:33 PM PDT 24
Peak memory 217548 kb
Host smart-178b2748-3cbc-4bd3-8dc4-c68ba2b75982
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210302910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.210302910
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.2491405712
Short name T789
Test name
Test status
Simulation time 583928121 ps
CPU time 2.69 seconds
Started Jun 29 05:49:28 PM PDT 24
Finished Jun 29 05:49:31 PM PDT 24
Peak memory 218428 kb
Host smart-2e25efdb-1c3a-40fc-b949-1a566fb1753c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491405712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.2491405712
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2408785757
Short name T846
Test name
Test status
Simulation time 3671568140 ps
CPU time 14.03 seconds
Started Jun 29 05:49:28 PM PDT 24
Finished Jun 29 05:49:43 PM PDT 24
Peak memory 226312 kb
Host smart-c171db74-a058-407f-85c5-4da33a68ef42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408785757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2408785757
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2579842397
Short name T554
Test name
Test status
Simulation time 1766097525 ps
CPU time 11.51 seconds
Started Jun 29 05:49:28 PM PDT 24
Finished Jun 29 05:49:40 PM PDT 24
Peak memory 218460 kb
Host smart-e830e694-3152-4364-a742-2cb726bdcbbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579842397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.2579842397
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3977954671
Short name T598
Test name
Test status
Simulation time 284851935 ps
CPU time 12.05 seconds
Started Jun 29 05:49:29 PM PDT 24
Finished Jun 29 05:49:41 PM PDT 24
Peak memory 218432 kb
Host smart-47a104ec-ba52-43da-96aa-db656681a0c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977954671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3977954671
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.2645872857
Short name T504
Test name
Test status
Simulation time 1147403174 ps
CPU time 8.07 seconds
Started Jun 29 05:49:29 PM PDT 24
Finished Jun 29 05:49:38 PM PDT 24
Peak memory 218560 kb
Host smart-8335183c-6f16-4d99-b375-cd0f364a80c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645872857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.2645872857
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.1464785418
Short name T457
Test name
Test status
Simulation time 114139199 ps
CPU time 2.09 seconds
Started Jun 29 05:49:21 PM PDT 24
Finished Jun 29 05:49:23 PM PDT 24
Peak memory 217928 kb
Host smart-231fa4e8-2bb8-4716-80ad-f5d1e7978862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464785418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1464785418
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.3792961033
Short name T823
Test name
Test status
Simulation time 249607537 ps
CPU time 30.63 seconds
Started Jun 29 05:49:29 PM PDT 24
Finished Jun 29 05:50:00 PM PDT 24
Peak memory 251096 kb
Host smart-ef41a77d-87fd-4a57-b4fb-6cbf68ca8d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792961033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.3792961033
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.3514992524
Short name T299
Test name
Test status
Simulation time 111515783 ps
CPU time 7.69 seconds
Started Jun 29 05:49:28 PM PDT 24
Finished Jun 29 05:49:36 PM PDT 24
Peak memory 251136 kb
Host smart-21d5c945-4f57-4aea-ad0c-7c79fe2dbbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514992524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.3514992524
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.760102256
Short name T811
Test name
Test status
Simulation time 1728266447 ps
CPU time 74.95 seconds
Started Jun 29 05:49:29 PM PDT 24
Finished Jun 29 05:50:45 PM PDT 24
Peak memory 251116 kb
Host smart-8c42f14e-b3a4-414a-ada0-21183cdcff83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760102256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.760102256
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.764035985
Short name T402
Test name
Test status
Simulation time 13249937 ps
CPU time 1.05 seconds
Started Jun 29 05:49:31 PM PDT 24
Finished Jun 29 05:49:32 PM PDT 24
Peak memory 212172 kb
Host smart-e87ef0a6-54aa-48b9-ac8e-3e5797778349
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764035985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ct
rl_volatile_unlock_smoke.764035985
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.718309387
Short name T478
Test name
Test status
Simulation time 52063370 ps
CPU time 1.04 seconds
Started Jun 29 05:49:36 PM PDT 24
Finished Jun 29 05:49:37 PM PDT 24
Peak memory 209168 kb
Host smart-17c8e7b7-02da-4e68-9220-2c8936f46bdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718309387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.718309387
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.735276688
Short name T44
Test name
Test status
Simulation time 864173785 ps
CPU time 12.97 seconds
Started Jun 29 05:49:35 PM PDT 24
Finished Jun 29 05:49:48 PM PDT 24
Peak memory 218436 kb
Host smart-e149cd5b-34b3-4207-baa3-039a73b9f544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735276688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.735276688
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.2868440707
Short name T649
Test name
Test status
Simulation time 471888387 ps
CPU time 2.39 seconds
Started Jun 29 05:49:36 PM PDT 24
Finished Jun 29 05:49:38 PM PDT 24
Peak memory 217196 kb
Host smart-83402c84-0735-40f6-b542-1384d60a5ad4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868440707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.2868440707
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.3154875580
Short name T704
Test name
Test status
Simulation time 32512176 ps
CPU time 2.36 seconds
Started Jun 29 05:49:37 PM PDT 24
Finished Jun 29 05:49:40 PM PDT 24
Peak memory 218408 kb
Host smart-6643ffba-4a5b-40f7-9649-4d2789d026ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154875580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.3154875580
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.2336023143
Short name T318
Test name
Test status
Simulation time 263836436 ps
CPU time 8.59 seconds
Started Jun 29 05:49:36 PM PDT 24
Finished Jun 29 05:49:45 PM PDT 24
Peak memory 226240 kb
Host smart-c8fabe3d-1fd3-407b-a0d2-0571b10155ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336023143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2336023143
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.622566113
Short name T316
Test name
Test status
Simulation time 4775928799 ps
CPU time 11.31 seconds
Started Jun 29 05:49:36 PM PDT 24
Finished Jun 29 05:49:48 PM PDT 24
Peak memory 218516 kb
Host smart-98445afc-11d1-41c0-aff9-20ad3e550327
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622566113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_di
gest.622566113
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.612153542
Short name T506
Test name
Test status
Simulation time 594976118 ps
CPU time 7.2 seconds
Started Jun 29 05:49:35 PM PDT 24
Finished Jun 29 05:49:42 PM PDT 24
Peak memory 226244 kb
Host smart-91934c3f-087c-4b0b-bb2f-ca503630d2fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612153542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.612153542
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.3870996492
Short name T401
Test name
Test status
Simulation time 274476273 ps
CPU time 7.2 seconds
Started Jun 29 05:49:36 PM PDT 24
Finished Jun 29 05:49:44 PM PDT 24
Peak memory 218440 kb
Host smart-a7458ea0-6c7b-4aa6-abfd-c3049c26a365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870996492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.3870996492
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.1376839505
Short name T608
Test name
Test status
Simulation time 28293544 ps
CPU time 2.24 seconds
Started Jun 29 05:49:28 PM PDT 24
Finished Jun 29 05:49:31 PM PDT 24
Peak memory 214620 kb
Host smart-27f5bf73-2ac0-482b-b468-e4a9fca1752c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376839505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.1376839505
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.432427177
Short name T209
Test name
Test status
Simulation time 1040808640 ps
CPU time 26.13 seconds
Started Jun 29 05:49:28 PM PDT 24
Finished Jun 29 05:49:55 PM PDT 24
Peak memory 251132 kb
Host smart-559dfd8f-ce08-4f63-ab0f-d960481f8b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432427177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.432427177
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3116552773
Short name T383
Test name
Test status
Simulation time 113962245 ps
CPU time 3.6 seconds
Started Jun 29 05:49:29 PM PDT 24
Finished Jun 29 05:49:33 PM PDT 24
Peak memory 222616 kb
Host smart-167a7df2-acfe-4a3a-8134-f6700c694d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116552773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3116552773
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.1865784140
Short name T41
Test name
Test status
Simulation time 18889713866 ps
CPU time 307.43 seconds
Started Jun 29 05:49:36 PM PDT 24
Finished Jun 29 05:54:45 PM PDT 24
Peak memory 260404 kb
Host smart-533087cc-5288-420f-bf82-86c841d24de5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865784140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.1865784140
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2568887705
Short name T516
Test name
Test status
Simulation time 12311607 ps
CPU time 0.91 seconds
Started Jun 29 05:49:27 PM PDT 24
Finished Jun 29 05:49:29 PM PDT 24
Peak memory 212068 kb
Host smart-989199cf-72e7-4ff4-a499-01210b340500
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568887705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2568887705
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.2243809881
Short name T617
Test name
Test status
Simulation time 74659164 ps
CPU time 0.9 seconds
Started Jun 29 05:49:36 PM PDT 24
Finished Jun 29 05:49:37 PM PDT 24
Peak memory 209168 kb
Host smart-90d4b14f-d781-4a4d-bfd1-6d9e13a3e2ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243809881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2243809881
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.3394531057
Short name T31
Test name
Test status
Simulation time 1198245694 ps
CPU time 13.19 seconds
Started Jun 29 05:49:36 PM PDT 24
Finished Jun 29 05:49:50 PM PDT 24
Peak memory 218444 kb
Host smart-573c4ed9-c570-47f8-9551-f12919e28e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394531057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3394531057
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.2372943355
Short name T735
Test name
Test status
Simulation time 11769465502 ps
CPU time 27.47 seconds
Started Jun 29 05:49:35 PM PDT 24
Finished Jun 29 05:50:03 PM PDT 24
Peak memory 217884 kb
Host smart-2049b591-d1d2-4542-957f-2a486091ce28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372943355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.2372943355
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.2976048028
Short name T557
Test name
Test status
Simulation time 217298181 ps
CPU time 3.34 seconds
Started Jun 29 05:49:37 PM PDT 24
Finished Jun 29 05:49:41 PM PDT 24
Peak memory 222660 kb
Host smart-4b8be2a6-923e-4157-b8e5-4c398ffd95ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976048028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.2976048028
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.2093472707
Short name T733
Test name
Test status
Simulation time 597483556 ps
CPU time 15.68 seconds
Started Jun 29 05:49:36 PM PDT 24
Finished Jun 29 05:49:52 PM PDT 24
Peak memory 226244 kb
Host smart-d4ad934f-95ac-43e6-9d51-871413d74fbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093472707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.2093472707
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.429398698
Short name T34
Test name
Test status
Simulation time 288200620 ps
CPU time 11.59 seconds
Started Jun 29 05:49:37 PM PDT 24
Finished Jun 29 05:49:49 PM PDT 24
Peak memory 218468 kb
Host smart-9d2a82f8-2b76-44c2-af1e-2e1b443cc3b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429398698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_di
gest.429398698
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.4086408885
Short name T405
Test name
Test status
Simulation time 2384576065 ps
CPU time 11.51 seconds
Started Jun 29 05:49:36 PM PDT 24
Finished Jun 29 05:49:48 PM PDT 24
Peak memory 226304 kb
Host smart-daa031e3-ae32-4f67-87a2-7c3edcb05d9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086408885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
4086408885
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3206348124
Short name T599
Test name
Test status
Simulation time 1780950256 ps
CPU time 14.79 seconds
Started Jun 29 05:49:37 PM PDT 24
Finished Jun 29 05:49:52 PM PDT 24
Peak memory 218476 kb
Host smart-03fb4b70-7718-48b6-8601-f7e914fc9475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206348124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3206348124
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.471915733
Short name T566
Test name
Test status
Simulation time 174131063 ps
CPU time 5.4 seconds
Started Jun 29 05:49:36 PM PDT 24
Finished Jun 29 05:49:42 PM PDT 24
Peak memory 217932 kb
Host smart-769be35a-d0d3-4f55-a5cb-9768c0e97693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471915733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.471915733
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3933314636
Short name T482
Test name
Test status
Simulation time 151473491 ps
CPU time 17.39 seconds
Started Jun 29 05:49:35 PM PDT 24
Finished Jun 29 05:49:53 PM PDT 24
Peak memory 244672 kb
Host smart-8f60394d-2dde-426c-bbab-4f6eab3087c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933314636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3933314636
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.2851414315
Short name T852
Test name
Test status
Simulation time 218234215 ps
CPU time 3.05 seconds
Started Jun 29 05:49:38 PM PDT 24
Finished Jun 29 05:49:41 PM PDT 24
Peak memory 222696 kb
Host smart-a525a301-795b-4208-97ca-fc6be4572163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851414315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.2851414315
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1078172546
Short name T588
Test name
Test status
Simulation time 523011871 ps
CPU time 14.06 seconds
Started Jun 29 05:49:36 PM PDT 24
Finished Jun 29 05:49:51 PM PDT 24
Peak memory 226856 kb
Host smart-36539242-7630-4060-a239-6df6ecaa7445
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078172546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1078172546
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.4036319739
Short name T584
Test name
Test status
Simulation time 17358262 ps
CPU time 0.91 seconds
Started Jun 29 05:49:35 PM PDT 24
Finished Jun 29 05:49:36 PM PDT 24
Peak memory 212048 kb
Host smart-4c6042cb-917a-4c12-8c67-b90014ea184e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036319739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.4036319739
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.3241543444
Short name T371
Test name
Test status
Simulation time 178204657 ps
CPU time 1.08 seconds
Started Jun 29 05:49:44 PM PDT 24
Finished Jun 29 05:49:46 PM PDT 24
Peak memory 209300 kb
Host smart-2f98d820-9365-4313-9b1b-a92a12dbd831
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241543444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3241543444
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.2517877914
Short name T574
Test name
Test status
Simulation time 313533499 ps
CPU time 11.74 seconds
Started Jun 29 05:49:43 PM PDT 24
Finished Jun 29 05:49:56 PM PDT 24
Peak memory 218344 kb
Host smart-917842bd-3786-4638-a9d0-c08cff24be72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517877914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2517877914
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.537159483
Short name T68
Test name
Test status
Simulation time 407306084 ps
CPU time 5.99 seconds
Started Jun 29 05:49:45 PM PDT 24
Finished Jun 29 05:49:51 PM PDT 24
Peak memory 217564 kb
Host smart-d98ebb78-ec79-43ea-ab99-d394da1199fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537159483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.537159483
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.2977881030
Short name T495
Test name
Test status
Simulation time 53382926 ps
CPU time 3.05 seconds
Started Jun 29 05:49:47 PM PDT 24
Finished Jun 29 05:49:51 PM PDT 24
Peak memory 218428 kb
Host smart-4ac8f4b4-2cb0-4210-8fbf-41cf73818dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977881030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.2977881030
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.3964853759
Short name T570
Test name
Test status
Simulation time 354154626 ps
CPU time 16.47 seconds
Started Jun 29 05:49:45 PM PDT 24
Finished Jun 29 05:50:02 PM PDT 24
Peak memory 226244 kb
Host smart-cacb0443-ba3d-4afc-8ed3-a13a9e76cd29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964853759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3964853759
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.3366103683
Short name T843
Test name
Test status
Simulation time 1672614895 ps
CPU time 15.6 seconds
Started Jun 29 05:49:44 PM PDT 24
Finished Jun 29 05:50:00 PM PDT 24
Peak memory 218460 kb
Host smart-30c7b959-e51d-42cc-85f4-6d75a64077d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366103683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.3366103683
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.4083811244
Short name T580
Test name
Test status
Simulation time 347689855 ps
CPU time 8.49 seconds
Started Jun 29 05:49:45 PM PDT 24
Finished Jun 29 05:49:54 PM PDT 24
Peak memory 226192 kb
Host smart-c8d33441-b075-43cd-a76c-8892472165d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083811244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
4083811244
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.3890223175
Short name T298
Test name
Test status
Simulation time 2222192853 ps
CPU time 10.35 seconds
Started Jun 29 05:49:47 PM PDT 24
Finished Jun 29 05:49:58 PM PDT 24
Peak memory 226104 kb
Host smart-c0961961-fdee-48e1-9a8a-0520670078ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890223175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3890223175
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3043228785
Short name T386
Test name
Test status
Simulation time 40557288 ps
CPU time 2.91 seconds
Started Jun 29 05:49:36 PM PDT 24
Finished Jun 29 05:49:40 PM PDT 24
Peak memory 215204 kb
Host smart-6d9fb08b-4b99-4a8e-a880-bd8ea65686e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043228785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3043228785
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.654308349
Short name T92
Test name
Test status
Simulation time 461304180 ps
CPU time 15.31 seconds
Started Jun 29 05:49:45 PM PDT 24
Finished Jun 29 05:50:01 PM PDT 24
Peak memory 251028 kb
Host smart-650a0533-d4fb-4d33-8d2d-fa519639039f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654308349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.654308349
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.553176718
Short name T788
Test name
Test status
Simulation time 555312565 ps
CPU time 10.04 seconds
Started Jun 29 05:49:45 PM PDT 24
Finished Jun 29 05:49:56 PM PDT 24
Peak memory 251120 kb
Host smart-32d30b93-459a-4cae-abc2-457683db7211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553176718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.553176718
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.2005684685
Short name T2
Test name
Test status
Simulation time 6744221959 ps
CPU time 207.67 seconds
Started Jun 29 05:49:44 PM PDT 24
Finished Jun 29 05:53:13 PM PDT 24
Peak memory 251176 kb
Host smart-5400d657-0355-424b-96f0-3e5a4858bd5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005684685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.2005684685
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1645909554
Short name T534
Test name
Test status
Simulation time 20386402 ps
CPU time 0.9 seconds
Started Jun 29 05:49:44 PM PDT 24
Finished Jun 29 05:49:45 PM PDT 24
Peak memory 212120 kb
Host smart-c7c5a57e-4492-4e0f-a6e1-e2ad83379b12
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645909554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.1645909554
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.675940163
Short name T825
Test name
Test status
Simulation time 45799792 ps
CPU time 0.83 seconds
Started Jun 29 05:49:52 PM PDT 24
Finished Jun 29 05:49:53 PM PDT 24
Peak memory 209196 kb
Host smart-f9e6b994-8ca2-4305-9762-23c7c21da6e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675940163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.675940163
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.621266535
Short name T781
Test name
Test status
Simulation time 334478762 ps
CPU time 17.28 seconds
Started Jun 29 05:49:43 PM PDT 24
Finished Jun 29 05:50:01 PM PDT 24
Peak memory 218436 kb
Host smart-19bcaf8e-1934-4dc3-8f4e-20ec34958720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621266535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.621266535
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1361855906
Short name T817
Test name
Test status
Simulation time 3059195658 ps
CPU time 7.71 seconds
Started Jun 29 05:49:48 PM PDT 24
Finished Jun 29 05:49:57 PM PDT 24
Peak memory 217876 kb
Host smart-d44150ed-0cb6-4448-82c9-c5f22190c086
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361855906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1361855906
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.511873309
Short name T239
Test name
Test status
Simulation time 92805933 ps
CPU time 3.38 seconds
Started Jun 29 05:49:47 PM PDT 24
Finished Jun 29 05:49:51 PM PDT 24
Peak memory 218552 kb
Host smart-326bacea-ccac-4ec7-9b8f-dcd4373b4032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511873309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.511873309
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.143521293
Short name T422
Test name
Test status
Simulation time 665631854 ps
CPU time 8.53 seconds
Started Jun 29 05:49:45 PM PDT 24
Finished Jun 29 05:49:54 PM PDT 24
Peak memory 226200 kb
Host smart-a4e6bad3-6304-484e-9b79-84e6196e47fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143521293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.143521293
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1993854989
Short name T248
Test name
Test status
Simulation time 16754724372 ps
CPU time 26.16 seconds
Started Jun 29 05:49:44 PM PDT 24
Finished Jun 29 05:50:10 PM PDT 24
Peak memory 218540 kb
Host smart-8ec54b5c-01bd-4248-a11d-13a4af58b040
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993854989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.1993854989
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3083504914
Short name T58
Test name
Test status
Simulation time 1082168388 ps
CPU time 7.41 seconds
Started Jun 29 05:49:48 PM PDT 24
Finished Jun 29 05:49:56 PM PDT 24
Peak memory 218328 kb
Host smart-170badcb-940e-4c91-bd1d-dc4e3c4bfeba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083504914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3083504914
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.3379263673
Short name T868
Test name
Test status
Simulation time 560138116 ps
CPU time 8.02 seconds
Started Jun 29 05:49:47 PM PDT 24
Finished Jun 29 05:49:56 PM PDT 24
Peak memory 218392 kb
Host smart-3476307f-9b7f-409b-ab83-db69f3b2b1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379263673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.3379263673
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2371490321
Short name T235
Test name
Test status
Simulation time 50465987 ps
CPU time 2.26 seconds
Started Jun 29 05:49:42 PM PDT 24
Finished Jun 29 05:49:44 PM PDT 24
Peak memory 214576 kb
Host smart-ec31dd90-08af-48ab-8846-7626de099b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371490321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2371490321
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.1464310894
Short name T325
Test name
Test status
Simulation time 1061224626 ps
CPU time 18.28 seconds
Started Jun 29 05:49:45 PM PDT 24
Finished Jun 29 05:50:04 PM PDT 24
Peak memory 251072 kb
Host smart-c145657f-b25e-45a5-ac05-7a4efd515e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464310894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.1464310894
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.3885511014
Short name T329
Test name
Test status
Simulation time 102118051 ps
CPU time 6.93 seconds
Started Jun 29 05:49:46 PM PDT 24
Finished Jun 29 05:49:53 PM PDT 24
Peak memory 250700 kb
Host smart-b5e9e297-7227-4915-8a6c-0271adb7abe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885511014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3885511014
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.471135390
Short name T193
Test name
Test status
Simulation time 41568251 ps
CPU time 0.83 seconds
Started Jun 29 05:49:46 PM PDT 24
Finished Jun 29 05:49:47 PM PDT 24
Peak memory 212080 kb
Host smart-f89bbee6-b0c3-4279-9483-0f171da09ce5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471135390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ct
rl_volatile_unlock_smoke.471135390
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.4265121730
Short name T355
Test name
Test status
Simulation time 16923269 ps
CPU time 1 seconds
Started Jun 29 05:49:53 PM PDT 24
Finished Jun 29 05:49:54 PM PDT 24
Peak memory 209168 kb
Host smart-c22ba1ac-da21-4ec7-b459-ecaadc9513b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265121730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.4265121730
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.2114092240
Short name T798
Test name
Test status
Simulation time 952398229 ps
CPU time 10.85 seconds
Started Jun 29 05:49:51 PM PDT 24
Finished Jun 29 05:50:03 PM PDT 24
Peak memory 226244 kb
Host smart-2a6510cc-4d1f-43f1-96e0-aa2100585e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114092240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2114092240
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2932154712
Short name T838
Test name
Test status
Simulation time 750480420 ps
CPU time 2.29 seconds
Started Jun 29 05:49:51 PM PDT 24
Finished Jun 29 05:49:54 PM PDT 24
Peak memory 217344 kb
Host smart-845a37d8-d56e-47ac-916a-682dacfc031b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932154712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2932154712
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.3362456556
Short name T399
Test name
Test status
Simulation time 1128264844 ps
CPU time 3.75 seconds
Started Jun 29 05:49:51 PM PDT 24
Finished Jun 29 05:49:55 PM PDT 24
Peak memory 222444 kb
Host smart-8b6f6fda-b226-4acd-bf87-5cda57513411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362456556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3362456556
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.352582589
Short name T851
Test name
Test status
Simulation time 1223956493 ps
CPU time 15.45 seconds
Started Jun 29 05:49:52 PM PDT 24
Finished Jun 29 05:50:08 PM PDT 24
Peak memory 219100 kb
Host smart-9be84141-2989-4169-b5c9-380e82bb6f3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352582589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.352582589
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2147591085
Short name T666
Test name
Test status
Simulation time 2131720630 ps
CPU time 20.72 seconds
Started Jun 29 05:49:52 PM PDT 24
Finished Jun 29 05:50:13 PM PDT 24
Peak memory 218408 kb
Host smart-1505cf01-932e-4b97-97d7-fb32cfbd0e2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147591085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.2147591085
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.2302003239
Short name T437
Test name
Test status
Simulation time 1609179651 ps
CPU time 14.68 seconds
Started Jun 29 05:49:52 PM PDT 24
Finished Jun 29 05:50:07 PM PDT 24
Peak memory 218424 kb
Host smart-2339eae9-034d-4c20-a10a-960886b9f5db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302003239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
2302003239
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.3937396059
Short name T52
Test name
Test status
Simulation time 413052573 ps
CPU time 8.22 seconds
Started Jun 29 05:49:53 PM PDT 24
Finished Jun 29 05:50:02 PM PDT 24
Peak memory 218464 kb
Host smart-36e3d6c1-941d-4e6e-900b-7eb68b70c3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937396059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3937396059
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.4163880246
Short name T522
Test name
Test status
Simulation time 17400540 ps
CPU time 1.43 seconds
Started Jun 29 05:49:51 PM PDT 24
Finished Jun 29 05:49:52 PM PDT 24
Peak memory 217924 kb
Host smart-41254fa3-3972-4579-a8ac-57bfb57606df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163880246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.4163880246
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.439477468
Short name T236
Test name
Test status
Simulation time 872898949 ps
CPU time 22.52 seconds
Started Jun 29 05:49:53 PM PDT 24
Finished Jun 29 05:50:15 PM PDT 24
Peak memory 251264 kb
Host smart-d7a2f2cd-9c08-4107-b183-93533ad0d143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439477468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.439477468
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2719162868
Short name T279
Test name
Test status
Simulation time 94707403 ps
CPU time 6.6 seconds
Started Jun 29 05:49:54 PM PDT 24
Finished Jun 29 05:50:01 PM PDT 24
Peak memory 250684 kb
Host smart-753dce32-e406-4784-8a3a-1805ad777d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719162868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2719162868
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.2768391549
Short name T689
Test name
Test status
Simulation time 14028044284 ps
CPU time 74.41 seconds
Started Jun 29 05:49:53 PM PDT 24
Finished Jun 29 05:51:07 PM PDT 24
Peak memory 251088 kb
Host smart-8128a5ec-80b2-42e5-84b4-169d4eaecf4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768391549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.2768391549
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.1915626984
Short name T116
Test name
Test status
Simulation time 63818877010 ps
CPU time 325.95 seconds
Started Jun 29 05:49:52 PM PDT 24
Finished Jun 29 05:55:19 PM PDT 24
Peak memory 333220 kb
Host smart-2c6c6044-dffd-4f37-979b-2d0fe13ddaec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1915626984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.1915626984
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.623165057
Short name T451
Test name
Test status
Simulation time 43304392 ps
CPU time 0.88 seconds
Started Jun 29 05:49:54 PM PDT 24
Finished Jun 29 05:49:55 PM PDT 24
Peak memory 212080 kb
Host smart-5dc62b2a-3a36-441a-add5-e07056924c96
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623165057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct
rl_volatile_unlock_smoke.623165057
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.2168933398
Short name T356
Test name
Test status
Simulation time 22880967 ps
CPU time 1 seconds
Started Jun 29 05:46:00 PM PDT 24
Finished Jun 29 05:46:02 PM PDT 24
Peak memory 209252 kb
Host smart-d5180773-dcd5-4a41-acdd-e4fa7a0740c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168933398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2168933398
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.366842360
Short name T576
Test name
Test status
Simulation time 745567819 ps
CPU time 10.48 seconds
Started Jun 29 05:45:48 PM PDT 24
Finished Jun 29 05:45:59 PM PDT 24
Peak memory 218436 kb
Host smart-56b79662-93c8-4eb2-97fb-3524693fd3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366842360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.366842360
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3291148526
Short name T440
Test name
Test status
Simulation time 959954306 ps
CPU time 6.38 seconds
Started Jun 29 05:45:57 PM PDT 24
Finished Jun 29 05:46:04 PM PDT 24
Peak memory 217304 kb
Host smart-7726fad1-4bbb-4f53-ab4d-ee1633d7ea2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291148526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3291148526
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.1569462503
Short name T300
Test name
Test status
Simulation time 19625352455 ps
CPU time 57.43 seconds
Started Jun 29 05:45:54 PM PDT 24
Finished Jun 29 05:46:51 PM PDT 24
Peak memory 226260 kb
Host smart-54c003d9-aca3-4f70-97f4-b8ffe66e2c57
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569462503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.1569462503
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.3137421433
Short name T295
Test name
Test status
Simulation time 5851914885 ps
CPU time 33.98 seconds
Started Jun 29 05:45:54 PM PDT 24
Finished Jun 29 05:46:28 PM PDT 24
Peak memory 217980 kb
Host smart-e459ce2b-0faa-417b-8c69-1323f34509dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137421433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.3
137421433
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.3960078840
Short name T754
Test name
Test status
Simulation time 797398004 ps
CPU time 4.41 seconds
Started Jun 29 05:45:52 PM PDT 24
Finished Jun 29 05:45:57 PM PDT 24
Peak memory 218296 kb
Host smart-11abc33e-7d07-40b1-a4e2-87780fe01886
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960078840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.3960078840
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1820357152
Short name T629
Test name
Test status
Simulation time 7294968217 ps
CPU time 18.29 seconds
Started Jun 29 05:45:52 PM PDT 24
Finished Jun 29 05:46:11 PM PDT 24
Peak memory 217972 kb
Host smart-74c51c41-310b-4c3d-a8ff-2b61710bbc19
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820357152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1820357152
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2264913831
Short name T695
Test name
Test status
Simulation time 964445624 ps
CPU time 7.24 seconds
Started Jun 29 05:45:53 PM PDT 24
Finished Jun 29 05:46:00 PM PDT 24
Peak memory 217920 kb
Host smart-707d96e7-82f5-430f-b965-a679ecb156b9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264913831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2264913831
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1766164093
Short name T653
Test name
Test status
Simulation time 4294585613 ps
CPU time 46.74 seconds
Started Jun 29 05:45:57 PM PDT 24
Finished Jun 29 05:46:44 PM PDT 24
Peak memory 251144 kb
Host smart-3b231eba-293f-4146-88bb-87302b5aa76f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766164093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.1766164093
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.149687630
Short name T583
Test name
Test status
Simulation time 1865327990 ps
CPU time 20.7 seconds
Started Jun 29 05:45:57 PM PDT 24
Finished Jun 29 05:46:18 PM PDT 24
Peak memory 251068 kb
Host smart-5295641b-056d-4807-8140-d4976d314064
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149687630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.149687630
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.2266583671
Short name T771
Test name
Test status
Simulation time 166796727 ps
CPU time 2.04 seconds
Started Jun 29 05:45:47 PM PDT 24
Finished Jun 29 05:45:49 PM PDT 24
Peak memory 218428 kb
Host smart-e2f7088f-7491-42e5-ac5b-2ca750810710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266583671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.2266583671
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1920067497
Short name T432
Test name
Test status
Simulation time 291406518 ps
CPU time 7.44 seconds
Started Jun 29 05:45:49 PM PDT 24
Finished Jun 29 05:45:57 PM PDT 24
Peak memory 214736 kb
Host smart-9c71e343-a48d-4f3a-8a0d-c274e3a785d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920067497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1920067497
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.3453407135
Short name T54
Test name
Test status
Simulation time 150984337 ps
CPU time 23.75 seconds
Started Jun 29 05:46:02 PM PDT 24
Finished Jun 29 05:46:26 PM PDT 24
Peak memory 284200 kb
Host smart-6d17b4dc-637d-41a6-afd2-eac73ff1cadf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453407135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.3453407135
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.4066727591
Short name T423
Test name
Test status
Simulation time 976180867 ps
CPU time 9.34 seconds
Started Jun 29 05:45:57 PM PDT 24
Finished Jun 29 05:46:07 PM PDT 24
Peak memory 219036 kb
Host smart-8ec020bf-3edc-4f4b-aa53-07768e301a86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066727591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.4066727591
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.4101769089
Short name T736
Test name
Test status
Simulation time 336687279 ps
CPU time 13.85 seconds
Started Jun 29 05:46:00 PM PDT 24
Finished Jun 29 05:46:14 PM PDT 24
Peak memory 218524 kb
Host smart-614bb4bf-ee8a-4d7f-be05-92c42264c1a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101769089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.4101769089
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.2710619740
Short name T15
Test name
Test status
Simulation time 1019941318 ps
CPU time 11.6 seconds
Started Jun 29 05:46:03 PM PDT 24
Finished Jun 29 05:46:15 PM PDT 24
Peak memory 218428 kb
Host smart-56691b0b-6a8a-4ab0-8342-d775099fdcf2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710619740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.2
710619740
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.3142424217
Short name T288
Test name
Test status
Simulation time 752342750 ps
CPU time 8.09 seconds
Started Jun 29 05:45:48 PM PDT 24
Finished Jun 29 05:45:57 PM PDT 24
Peak memory 225424 kb
Host smart-24d05ec6-86b1-4f86-ac48-b3cad2ef952a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142424217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3142424217
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.1393905586
Short name T507
Test name
Test status
Simulation time 830675599 ps
CPU time 5.57 seconds
Started Jun 29 05:45:35 PM PDT 24
Finished Jun 29 05:45:41 PM PDT 24
Peak memory 217932 kb
Host smart-a340ac3c-4b01-47a6-ae50-deeb59cf838c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393905586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1393905586
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.1709013017
Short name T672
Test name
Test status
Simulation time 3013688238 ps
CPU time 28.25 seconds
Started Jun 29 05:45:48 PM PDT 24
Finished Jun 29 05:46:17 PM PDT 24
Peak memory 251192 kb
Host smart-1f62897e-5b23-4ecf-b4ec-a1c0d553204b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709013017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1709013017
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1971043194
Short name T729
Test name
Test status
Simulation time 74968238 ps
CPU time 7.56 seconds
Started Jun 29 05:45:49 PM PDT 24
Finished Jun 29 05:45:57 PM PDT 24
Peak memory 251076 kb
Host smart-d888e1a0-714c-4887-a673-cc3af5026c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971043194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1971043194
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1668180540
Short name T624
Test name
Test status
Simulation time 12681868238 ps
CPU time 209.14 seconds
Started Jun 29 05:46:02 PM PDT 24
Finished Jun 29 05:49:31 PM PDT 24
Peak memory 284828 kb
Host smart-936139ef-75eb-4c70-928c-34a233f3618d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668180540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1668180540
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.2861299430
Short name T594
Test name
Test status
Simulation time 24024311954 ps
CPU time 418.96 seconds
Started Jun 29 05:46:02 PM PDT 24
Finished Jun 29 05:53:01 PM PDT 24
Peak memory 313020 kb
Host smart-8d1dc492-e095-4559-87bf-06cd6b8f4ddd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2861299430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.2861299430
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.743848070
Short name T859
Test name
Test status
Simulation time 34226934 ps
CPU time 0.95 seconds
Started Jun 29 05:45:50 PM PDT 24
Finished Jun 29 05:45:51 PM PDT 24
Peak memory 211984 kb
Host smart-fa49685e-48bf-4cc9-968c-96033b3dcab1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743848070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctr
l_volatile_unlock_smoke.743848070
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.35681047
Short name T795
Test name
Test status
Simulation time 15485578 ps
CPU time 0.89 seconds
Started Jun 29 05:50:02 PM PDT 24
Finished Jun 29 05:50:04 PM PDT 24
Peak memory 208980 kb
Host smart-6ca763b7-e6bc-4550-8280-0c6b326ecf18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35681047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.35681047
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.3765957257
Short name T759
Test name
Test status
Simulation time 903346898 ps
CPU time 12.23 seconds
Started Jun 29 05:49:53 PM PDT 24
Finished Jun 29 05:50:05 PM PDT 24
Peak memory 218448 kb
Host smart-930f7403-64f0-4636-b120-f8a314c7f964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765957257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3765957257
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.490426928
Short name T683
Test name
Test status
Simulation time 491498815 ps
CPU time 6.58 seconds
Started Jun 29 05:50:02 PM PDT 24
Finished Jun 29 05:50:09 PM PDT 24
Peak memory 217400 kb
Host smart-1605febe-1274-4b21-a8bc-66bb2e8b5b52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490426928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.490426928
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.2232104111
Short name T525
Test name
Test status
Simulation time 33927544 ps
CPU time 2.58 seconds
Started Jun 29 05:49:52 PM PDT 24
Finished Jun 29 05:49:55 PM PDT 24
Peak memory 218324 kb
Host smart-9ba2353e-0986-478e-b45e-31f19d87a407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232104111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.2232104111
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.304109322
Short name T773
Test name
Test status
Simulation time 720170865 ps
CPU time 10.95 seconds
Started Jun 29 05:50:00 PM PDT 24
Finished Jun 29 05:50:11 PM PDT 24
Peak memory 219100 kb
Host smart-f3ea2b5f-c13a-4a93-9a98-4ee5a02ed9cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304109322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.304109322
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.3981426110
Short name T827
Test name
Test status
Simulation time 572108195 ps
CPU time 13.4 seconds
Started Jun 29 05:50:01 PM PDT 24
Finished Jun 29 05:50:15 PM PDT 24
Peak memory 218528 kb
Host smart-3e364370-cbee-42cd-99ad-18184537c1d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981426110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.3981426110
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.2643491290
Short name T589
Test name
Test status
Simulation time 2655284874 ps
CPU time 10.02 seconds
Started Jun 29 05:50:01 PM PDT 24
Finished Jun 29 05:50:12 PM PDT 24
Peak memory 226308 kb
Host smart-2c3bb1fc-3687-4479-865e-964bed1d76a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643491290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
2643491290
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1354758949
Short name T265
Test name
Test status
Simulation time 346972098 ps
CPU time 12.8 seconds
Started Jun 29 05:50:01 PM PDT 24
Finished Jun 29 05:50:15 PM PDT 24
Peak memory 218500 kb
Host smart-296e95fa-473c-44ec-bad8-53a8ffb281b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354758949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1354758949
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.988518156
Short name T767
Test name
Test status
Simulation time 78710708 ps
CPU time 3.3 seconds
Started Jun 29 05:49:53 PM PDT 24
Finished Jun 29 05:49:56 PM PDT 24
Peak memory 215008 kb
Host smart-0f4fd44c-8ae9-48de-90da-41b540471870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988518156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.988518156
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.912509342
Short name T770
Test name
Test status
Simulation time 1504917209 ps
CPU time 21.08 seconds
Started Jun 29 05:49:52 PM PDT 24
Finished Jun 29 05:50:13 PM PDT 24
Peak memory 251124 kb
Host smart-e0364a2f-cfee-4c9c-bd94-6f6cdb9b6caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912509342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.912509342
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.1231911018
Short name T575
Test name
Test status
Simulation time 222749627 ps
CPU time 7.29 seconds
Started Jun 29 05:49:52 PM PDT 24
Finished Jun 29 05:49:59 PM PDT 24
Peak memory 251120 kb
Host smart-d139c379-5deb-4c7f-874c-6b96e0b245fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231911018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.1231911018
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.1780317832
Short name T84
Test name
Test status
Simulation time 2827872466 ps
CPU time 16.81 seconds
Started Jun 29 05:50:01 PM PDT 24
Finished Jun 29 05:50:18 PM PDT 24
Peak memory 227216 kb
Host smart-902b10eb-421a-40ff-966c-616639ec074d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780317832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.1780317832
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.2197118611
Short name T37
Test name
Test status
Simulation time 5880861897 ps
CPU time 271.37 seconds
Started Jun 29 05:50:00 PM PDT 24
Finished Jun 29 05:54:32 PM PDT 24
Peak memory 422300 kb
Host smart-3ea47d75-a749-46d0-ab3b-2cd48b64ef62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2197118611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.2197118611
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3959707723
Short name T436
Test name
Test status
Simulation time 22790931 ps
CPU time 0.94 seconds
Started Jun 29 05:49:51 PM PDT 24
Finished Jun 29 05:49:52 PM PDT 24
Peak memory 212168 kb
Host smart-0ed266c1-211a-4287-bc98-6f225eef228b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959707723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3959707723
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3763749007
Short name T229
Test name
Test status
Simulation time 40847829 ps
CPU time 0.93 seconds
Started Jun 29 05:49:59 PM PDT 24
Finished Jun 29 05:50:01 PM PDT 24
Peak memory 209152 kb
Host smart-72beeba9-2af7-4af1-a86f-ee5ba3bc4c87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763749007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3763749007
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.2040633202
Short name T667
Test name
Test status
Simulation time 861420989 ps
CPU time 10.72 seconds
Started Jun 29 05:50:00 PM PDT 24
Finished Jun 29 05:50:11 PM PDT 24
Peak memory 226244 kb
Host smart-8e93ec2a-ec71-430b-b93a-3bf811cdc572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040633202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.2040633202
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.324408303
Short name T453
Test name
Test status
Simulation time 225849626 ps
CPU time 5.7 seconds
Started Jun 29 05:50:01 PM PDT 24
Finished Jun 29 05:50:07 PM PDT 24
Peak memory 217292 kb
Host smart-f2309ba3-1fe1-4c13-9d0d-dbe85d7855f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324408303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.324408303
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.2734819306
Short name T400
Test name
Test status
Simulation time 533607713 ps
CPU time 3.11 seconds
Started Jun 29 05:50:01 PM PDT 24
Finished Jun 29 05:50:05 PM PDT 24
Peak memory 218404 kb
Host smart-fe5e24c0-a2b9-4d60-9bac-2548547814cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734819306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.2734819306
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.1395356587
Short name T341
Test name
Test status
Simulation time 1329732277 ps
CPU time 15.71 seconds
Started Jun 29 05:50:02 PM PDT 24
Finished Jun 29 05:50:18 PM PDT 24
Peak memory 226140 kb
Host smart-7e7ee92b-d8c1-48c9-88fd-263735da865a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395356587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.1395356587
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.253224566
Short name T387
Test name
Test status
Simulation time 546351395 ps
CPU time 9.77 seconds
Started Jun 29 05:50:01 PM PDT 24
Finished Jun 29 05:50:11 PM PDT 24
Peak memory 218452 kb
Host smart-9286e496-4d37-4f99-9c38-4b487727f03d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253224566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_di
gest.253224566
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1007647608
Short name T634
Test name
Test status
Simulation time 1248925059 ps
CPU time 7.83 seconds
Started Jun 29 05:50:00 PM PDT 24
Finished Jun 29 05:50:09 PM PDT 24
Peak memory 218376 kb
Host smart-ee26c3a4-3b8c-4877-a36f-789e989de67a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007647608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
1007647608
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.790245699
Short name T381
Test name
Test status
Simulation time 1130676245 ps
CPU time 9.05 seconds
Started Jun 29 05:50:00 PM PDT 24
Finished Jun 29 05:50:09 PM PDT 24
Peak memory 218476 kb
Host smart-09b09c6e-0d0f-482f-833c-2c4d53ca0c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790245699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.790245699
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.958790876
Short name T572
Test name
Test status
Simulation time 62611311 ps
CPU time 2.69 seconds
Started Jun 29 05:50:01 PM PDT 24
Finished Jun 29 05:50:04 PM PDT 24
Peak memory 214868 kb
Host smart-ca796d77-4b05-46c8-830b-dbf22f0395af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958790876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.958790876
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.2141470996
Short name T212
Test name
Test status
Simulation time 558811942 ps
CPU time 28.92 seconds
Started Jun 29 05:50:01 PM PDT 24
Finished Jun 29 05:50:31 PM PDT 24
Peak memory 251036 kb
Host smart-fca9cfb1-e725-4569-ad9b-1e9db69a0a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141470996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.2141470996
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.2883272385
Short name T12
Test name
Test status
Simulation time 383053476 ps
CPU time 3.03 seconds
Started Jun 29 05:50:04 PM PDT 24
Finished Jun 29 05:50:07 PM PDT 24
Peak memory 222420 kb
Host smart-dd0d2d05-efc4-4897-a662-e056eb76ce13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883272385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.2883272385
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2197407890
Short name T714
Test name
Test status
Simulation time 37847328 ps
CPU time 1.02 seconds
Started Jun 29 05:50:02 PM PDT 24
Finished Jun 29 05:50:04 PM PDT 24
Peak memory 213140 kb
Host smart-1c8ca5a5-5e64-4df2-90f8-7ad9515a3ace
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197407890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2197407890
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1144177300
Short name T498
Test name
Test status
Simulation time 20543145 ps
CPU time 1 seconds
Started Jun 29 05:50:09 PM PDT 24
Finished Jun 29 05:50:10 PM PDT 24
Peak memory 209112 kb
Host smart-0d976d34-fa29-474b-8f0d-683630554451
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144177300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1144177300
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.3334074887
Short name T847
Test name
Test status
Simulation time 1335889297 ps
CPU time 10.19 seconds
Started Jun 29 05:50:11 PM PDT 24
Finished Jun 29 05:50:21 PM PDT 24
Peak memory 218580 kb
Host smart-88ba7199-4c46-4234-946e-5bc45ab6ddd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334074887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3334074887
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.3206929950
Short name T479
Test name
Test status
Simulation time 2286040185 ps
CPU time 8.98 seconds
Started Jun 29 05:50:08 PM PDT 24
Finished Jun 29 05:50:17 PM PDT 24
Peak memory 217424 kb
Host smart-a5b31383-ff8a-465f-bfa6-cc4f6f49ea83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206929950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.3206929950
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.1973574403
Short name T493
Test name
Test status
Simulation time 40239954 ps
CPU time 1.63 seconds
Started Jun 29 05:50:12 PM PDT 24
Finished Jun 29 05:50:14 PM PDT 24
Peak memory 218392 kb
Host smart-7e646b08-1f45-48fc-b39d-00fe9ade70c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973574403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1973574403
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.2086334670
Short name T494
Test name
Test status
Simulation time 1774287525 ps
CPU time 11.32 seconds
Started Jun 29 05:50:08 PM PDT 24
Finished Jun 29 05:50:20 PM PDT 24
Peak memory 226232 kb
Host smart-f62e9151-7f9c-41f6-a72a-22f57f750367
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086334670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.2086334670
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2103013334
Short name T261
Test name
Test status
Simulation time 1251516184 ps
CPU time 8.8 seconds
Started Jun 29 05:50:07 PM PDT 24
Finished Jun 29 05:50:16 PM PDT 24
Peak memory 218420 kb
Host smart-75472bb7-d426-403a-a211-b2e51954de24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103013334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2103013334
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1285973093
Short name T306
Test name
Test status
Simulation time 254136751 ps
CPU time 10.13 seconds
Started Jun 29 05:50:08 PM PDT 24
Finished Jun 29 05:50:19 PM PDT 24
Peak memory 218440 kb
Host smart-6e4fa206-5594-4298-9054-39b9903189b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285973093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1285973093
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3286874822
Short name T620
Test name
Test status
Simulation time 296848079 ps
CPU time 14.11 seconds
Started Jun 29 05:50:08 PM PDT 24
Finished Jun 29 05:50:22 PM PDT 24
Peak memory 218636 kb
Host smart-6d4d2b71-97d3-45dc-84b2-7957d168f60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286874822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3286874822
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.1585099477
Short name T61
Test name
Test status
Simulation time 42847296 ps
CPU time 3.37 seconds
Started Jun 29 05:50:01 PM PDT 24
Finished Jun 29 05:50:05 PM PDT 24
Peak memory 215148 kb
Host smart-909633eb-7f94-42e0-b302-ab658ae7852f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585099477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.1585099477
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.865967162
Short name T205
Test name
Test status
Simulation time 272165511 ps
CPU time 25.69 seconds
Started Jun 29 05:50:10 PM PDT 24
Finished Jun 29 05:50:36 PM PDT 24
Peak memory 251184 kb
Host smart-7ba6cee4-496c-4e4b-ae34-ca9868c45557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865967162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.865967162
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.2119077563
Short name T246
Test name
Test status
Simulation time 137818542 ps
CPU time 2.85 seconds
Started Jun 29 05:50:08 PM PDT 24
Finished Jun 29 05:50:11 PM PDT 24
Peak memory 226548 kb
Host smart-0f567009-89d1-4a2b-ae87-a79d87b24e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119077563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.2119077563
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1286249587
Short name T484
Test name
Test status
Simulation time 19004761126 ps
CPU time 166.15 seconds
Started Jun 29 05:50:11 PM PDT 24
Finished Jun 29 05:52:57 PM PDT 24
Peak memory 251144 kb
Host smart-0a711159-2104-45fb-80ae-840fe8e31f22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286249587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1286249587
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.904399528
Short name T568
Test name
Test status
Simulation time 15434112 ps
CPU time 0.89 seconds
Started Jun 29 05:50:09 PM PDT 24
Finished Jun 29 05:50:10 PM PDT 24
Peak memory 212136 kb
Host smart-49973f35-1427-4132-bf8f-ceed3501452a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904399528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ct
rl_volatile_unlock_smoke.904399528
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1549808487
Short name T163
Test name
Test status
Simulation time 14771221 ps
CPU time 1.05 seconds
Started Jun 29 05:50:17 PM PDT 24
Finished Jun 29 05:50:18 PM PDT 24
Peak memory 209232 kb
Host smart-340b05e4-cb70-43ed-8c1b-3523e3a395be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549808487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1549808487
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.2558123470
Short name T856
Test name
Test status
Simulation time 385807964 ps
CPU time 10.42 seconds
Started Jun 29 05:50:08 PM PDT 24
Finished Jun 29 05:50:18 PM PDT 24
Peak memory 218428 kb
Host smart-73b09acb-002c-422f-8737-4ab893a9cca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558123470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2558123470
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.2707865224
Short name T750
Test name
Test status
Simulation time 350811978 ps
CPU time 4.84 seconds
Started Jun 29 05:50:19 PM PDT 24
Finished Jun 29 05:50:24 PM PDT 24
Peak memory 217608 kb
Host smart-8c502d26-7e80-4236-ab51-50199cd576a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707865224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.2707865224
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2378719445
Short name T535
Test name
Test status
Simulation time 257338919 ps
CPU time 3.17 seconds
Started Jun 29 05:50:09 PM PDT 24
Finished Jun 29 05:50:13 PM PDT 24
Peak memory 218424 kb
Host smart-78ad44a2-3dd7-464a-a679-24c752306b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378719445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2378719445
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.110008436
Short name T619
Test name
Test status
Simulation time 593338493 ps
CPU time 16.3 seconds
Started Jun 29 05:50:18 PM PDT 24
Finished Jun 29 05:50:35 PM PDT 24
Peak memory 226244 kb
Host smart-a9881f4e-bd54-40c0-b251-7f61162661ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110008436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.110008436
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.4055246987
Short name T559
Test name
Test status
Simulation time 202960645 ps
CPU time 8.84 seconds
Started Jun 29 05:50:18 PM PDT 24
Finished Jun 29 05:50:28 PM PDT 24
Peak memory 218456 kb
Host smart-6351891c-2578-418f-9d89-cbac1cdc1345
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055246987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.4055246987
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2873437220
Short name T419
Test name
Test status
Simulation time 350763596 ps
CPU time 12.1 seconds
Started Jun 29 05:50:18 PM PDT 24
Finished Jun 29 05:50:30 PM PDT 24
Peak memory 218352 kb
Host smart-07b7dc17-1346-4a90-ae18-d39394781358
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873437220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2873437220
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.697726708
Short name T647
Test name
Test status
Simulation time 1447288993 ps
CPU time 9.01 seconds
Started Jun 29 05:50:08 PM PDT 24
Finished Jun 29 05:50:18 PM PDT 24
Peak memory 218508 kb
Host smart-4b43b08c-aeab-47f9-9e2d-0f6c63f72fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697726708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.697726708
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.2034785831
Short name T214
Test name
Test status
Simulation time 184497208 ps
CPU time 1.43 seconds
Started Jun 29 05:50:08 PM PDT 24
Finished Jun 29 05:50:10 PM PDT 24
Peak memory 213944 kb
Host smart-14432286-59a5-4932-b7a0-13b103e6ad46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034785831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2034785831
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.120909998
Short name T373
Test name
Test status
Simulation time 240412660 ps
CPU time 32.08 seconds
Started Jun 29 05:50:09 PM PDT 24
Finished Jun 29 05:50:41 PM PDT 24
Peak memory 251156 kb
Host smart-e2737796-2dbc-4cb8-9e8b-402a07d21658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120909998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.120909998
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3251386456
Short name T221
Test name
Test status
Simulation time 226053968 ps
CPU time 8.05 seconds
Started Jun 29 05:50:08 PM PDT 24
Finished Jun 29 05:50:16 PM PDT 24
Peak memory 251132 kb
Host smart-795cce82-ab7c-43a0-9239-716277c1ceb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251386456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3251386456
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.3489678840
Short name T161
Test name
Test status
Simulation time 8098581259 ps
CPU time 129.07 seconds
Started Jun 29 05:50:18 PM PDT 24
Finished Jun 29 05:52:28 PM PDT 24
Peak memory 333072 kb
Host smart-346469a3-203a-48e6-b925-91704981bd29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489678840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.3489678840
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.3708766445
Short name T45
Test name
Test status
Simulation time 114083217156 ps
CPU time 625.9 seconds
Started Jun 29 05:50:18 PM PDT 24
Finished Jun 29 06:00:45 PM PDT 24
Peak memory 284080 kb
Host smart-bbeae5d0-0d03-4658-81d1-19466c02a71a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3708766445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.3708766445
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.33051737
Short name T700
Test name
Test status
Simulation time 42927974 ps
CPU time 1.01 seconds
Started Jun 29 05:50:08 PM PDT 24
Finished Jun 29 05:50:10 PM PDT 24
Peak memory 213152 kb
Host smart-437b5750-7dec-4393-8125-25dfe654861b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33051737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctr
l_volatile_unlock_smoke.33051737
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.3791434814
Short name T660
Test name
Test status
Simulation time 55050217 ps
CPU time 1.09 seconds
Started Jun 29 05:50:27 PM PDT 24
Finished Jun 29 05:50:29 PM PDT 24
Peak memory 209180 kb
Host smart-c5759d3e-a736-472b-95a2-e31a5bc9d7fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791434814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3791434814
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.426446028
Short name T569
Test name
Test status
Simulation time 596077373 ps
CPU time 12.96 seconds
Started Jun 29 05:50:17 PM PDT 24
Finished Jun 29 05:50:31 PM PDT 24
Peak memory 218432 kb
Host smart-884ecb22-dafb-4d8b-8f26-10cf5b2c0f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426446028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.426446028
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.446433254
Short name T466
Test name
Test status
Simulation time 2286767963 ps
CPU time 15.77 seconds
Started Jun 29 05:50:17 PM PDT 24
Finished Jun 29 05:50:33 PM PDT 24
Peak memory 217808 kb
Host smart-88655777-8db1-4dfd-b746-f594874ddfc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446433254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.446433254
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.3814418415
Short name T713
Test name
Test status
Simulation time 677109882 ps
CPU time 4.25 seconds
Started Jun 29 05:50:19 PM PDT 24
Finished Jun 29 05:50:24 PM PDT 24
Peak memory 222472 kb
Host smart-7999e3db-de42-4c24-a656-b7bb4a0d294c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814418415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3814418415
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.3728860448
Short name T627
Test name
Test status
Simulation time 225114595 ps
CPU time 10.99 seconds
Started Jun 29 05:50:18 PM PDT 24
Finished Jun 29 05:50:30 PM PDT 24
Peak memory 226240 kb
Host smart-dc31a23f-04ed-4d0c-85b7-d1e1b41fb82b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728860448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.3728860448
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3086048718
Short name T849
Test name
Test status
Simulation time 689184801 ps
CPU time 16.55 seconds
Started Jun 29 05:50:28 PM PDT 24
Finished Jun 29 05:50:45 PM PDT 24
Peak memory 218396 kb
Host smart-66f35952-16c9-4b5e-8487-a829c649b0ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086048718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3086048718
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3594516681
Short name T539
Test name
Test status
Simulation time 983249158 ps
CPU time 10.19 seconds
Started Jun 29 05:50:19 PM PDT 24
Finished Jun 29 05:50:30 PM PDT 24
Peak memory 226248 kb
Host smart-98e008ac-0f81-4143-ba12-47cfbfe06d31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594516681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3594516681
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.3257864411
Short name T834
Test name
Test status
Simulation time 338080679 ps
CPU time 8.08 seconds
Started Jun 29 05:50:18 PM PDT 24
Finished Jun 29 05:50:26 PM PDT 24
Peak memory 225792 kb
Host smart-b3db470d-08df-46bc-aae6-41e048da0310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257864411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3257864411
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.1793570942
Short name T83
Test name
Test status
Simulation time 59574683 ps
CPU time 3.94 seconds
Started Jun 29 05:50:18 PM PDT 24
Finished Jun 29 05:50:23 PM PDT 24
Peak memory 215200 kb
Host smart-0ba9f705-bad1-4228-93ad-70894c005b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793570942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.1793570942
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.3726202953
Short name T378
Test name
Test status
Simulation time 228884919 ps
CPU time 17.76 seconds
Started Jun 29 05:50:18 PM PDT 24
Finished Jun 29 05:50:36 PM PDT 24
Peak memory 250996 kb
Host smart-e880c48e-0786-4e8e-b762-0d46f8f785c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726202953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.3726202953
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2615432565
Short name T751
Test name
Test status
Simulation time 424260738 ps
CPU time 8.03 seconds
Started Jun 29 05:50:19 PM PDT 24
Finished Jun 29 05:50:27 PM PDT 24
Peak memory 251196 kb
Host smart-d868ec9c-8e94-4788-a15e-78995f8ac638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615432565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2615432565
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1160136463
Short name T305
Test name
Test status
Simulation time 60605480 ps
CPU time 1.03 seconds
Started Jun 29 05:50:19 PM PDT 24
Finished Jun 29 05:50:20 PM PDT 24
Peak memory 212116 kb
Host smart-df090200-342d-4ad0-b0d7-32e1a489a7cb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160136463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1160136463
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.3953425693
Short name T577
Test name
Test status
Simulation time 62040751 ps
CPU time 1.09 seconds
Started Jun 29 05:50:26 PM PDT 24
Finished Jun 29 05:50:28 PM PDT 24
Peak memory 209244 kb
Host smart-8a85fd0c-c61c-4822-8174-c9f4f0594bc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953425693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3953425693
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.2703239731
Short name T57
Test name
Test status
Simulation time 740426526 ps
CPU time 14.73 seconds
Started Jun 29 05:50:29 PM PDT 24
Finished Jun 29 05:50:44 PM PDT 24
Peak memory 218428 kb
Host smart-01408f0e-7c6f-4c14-a61a-7f06bb90d5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703239731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.2703239731
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.4196686954
Short name T7
Test name
Test status
Simulation time 1850830288 ps
CPU time 12.35 seconds
Started Jun 29 05:50:27 PM PDT 24
Finished Jun 29 05:50:40 PM PDT 24
Peak memory 217668 kb
Host smart-24f52a0b-01fd-4681-8840-c0338fba0c8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196686954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.4196686954
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.1688907990
Short name T269
Test name
Test status
Simulation time 371151693 ps
CPU time 4.07 seconds
Started Jun 29 05:50:27 PM PDT 24
Finished Jun 29 05:50:32 PM PDT 24
Peak memory 218436 kb
Host smart-bad230a0-4262-45a6-a7f7-bb7a5045c54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688907990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1688907990
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.1305898716
Short name T302
Test name
Test status
Simulation time 791293137 ps
CPU time 14.28 seconds
Started Jun 29 05:50:27 PM PDT 24
Finished Jun 29 05:50:42 PM PDT 24
Peak memory 226208 kb
Host smart-64bd447c-8534-4713-9fa8-0d7341d75c7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305898716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.1305898716
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3917690333
Short name T591
Test name
Test status
Simulation time 5772409125 ps
CPU time 26.08 seconds
Started Jun 29 05:50:26 PM PDT 24
Finished Jun 29 05:50:53 PM PDT 24
Peak memory 218552 kb
Host smart-6404aded-117d-415e-bdb5-7a5f153f06aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917690333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3917690333
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.2037127633
Short name T367
Test name
Test status
Simulation time 258256599 ps
CPU time 10.08 seconds
Started Jun 29 05:50:27 PM PDT 24
Finished Jun 29 05:50:38 PM PDT 24
Peak memory 226248 kb
Host smart-d42b720a-bf77-4957-9e7c-753513d3f1e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037127633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
2037127633
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.2237967649
Short name T82
Test name
Test status
Simulation time 34338766 ps
CPU time 1.68 seconds
Started Jun 29 05:50:27 PM PDT 24
Finished Jun 29 05:50:29 PM PDT 24
Peak memory 214032 kb
Host smart-e1c9c713-0d3a-40d8-8b5c-7a0700229228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237967649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.2237967649
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.793036818
Short name T585
Test name
Test status
Simulation time 333097227 ps
CPU time 35.08 seconds
Started Jun 29 05:50:26 PM PDT 24
Finished Jun 29 05:51:01 PM PDT 24
Peak memory 251136 kb
Host smart-d6fd7389-0591-4da0-b442-49ef9a087d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793036818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.793036818
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.1598019524
Short name T467
Test name
Test status
Simulation time 312735944 ps
CPU time 7.74 seconds
Started Jun 29 05:50:26 PM PDT 24
Finished Jun 29 05:50:34 PM PDT 24
Peak memory 250644 kb
Host smart-6430032b-f81d-4f5f-978d-1ba9b2d76afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598019524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1598019524
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.1047967910
Short name T548
Test name
Test status
Simulation time 4009052859 ps
CPU time 46.06 seconds
Started Jun 29 05:50:26 PM PDT 24
Finished Jun 29 05:51:13 PM PDT 24
Peak memory 267564 kb
Host smart-2bbeb528-9f67-432f-893e-c4505417b35c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047967910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.1047967910
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.4085798169
Short name T715
Test name
Test status
Simulation time 19673129 ps
CPU time 0.87 seconds
Started Jun 29 05:50:26 PM PDT 24
Finished Jun 29 05:50:28 PM PDT 24
Peak memory 213148 kb
Host smart-7f73f03d-ae38-4482-8984-aafb8ddaf089
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085798169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.4085798169
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.910149171
Short name T761
Test name
Test status
Simulation time 112649544 ps
CPU time 1.14 seconds
Started Jun 29 05:50:32 PM PDT 24
Finished Jun 29 05:50:34 PM PDT 24
Peak memory 209168 kb
Host smart-f6369995-9c40-4067-8654-0fc6009e015b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910149171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.910149171
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.1978859358
Short name T216
Test name
Test status
Simulation time 625566509 ps
CPU time 14.61 seconds
Started Jun 29 05:50:34 PM PDT 24
Finished Jun 29 05:50:50 PM PDT 24
Peak memory 218344 kb
Host smart-640815f4-6cb8-4fb3-b9ff-350871f89c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978859358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.1978859358
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1362811069
Short name T172
Test name
Test status
Simulation time 924993589 ps
CPU time 6.11 seconds
Started Jun 29 05:50:36 PM PDT 24
Finished Jun 29 05:50:42 PM PDT 24
Peak memory 217640 kb
Host smart-cd08e10d-b659-4c18-98c2-95872cd779b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362811069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1362811069
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.769933736
Short name T796
Test name
Test status
Simulation time 64154668 ps
CPU time 1.53 seconds
Started Jun 29 05:50:26 PM PDT 24
Finished Jun 29 05:50:28 PM PDT 24
Peak memory 218428 kb
Host smart-fec7c853-6659-4f57-aaaa-49f8014f0004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769933736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.769933736
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.2558777087
Short name T38
Test name
Test status
Simulation time 602229154 ps
CPU time 11.51 seconds
Started Jun 29 05:50:33 PM PDT 24
Finished Jun 29 05:50:45 PM PDT 24
Peak memory 226216 kb
Host smart-bd47510c-42ba-4364-8b1a-ceb30b191cf3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558777087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.2558777087
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.2254194880
Short name T334
Test name
Test status
Simulation time 449470884 ps
CPU time 14.46 seconds
Started Jun 29 05:50:38 PM PDT 24
Finished Jun 29 05:50:53 PM PDT 24
Peak memory 218324 kb
Host smart-e89ffe18-d441-47ef-81f1-04ce4995ab95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254194880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.2254194880
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.128222396
Short name T533
Test name
Test status
Simulation time 659245691 ps
CPU time 7.2 seconds
Started Jun 29 05:50:33 PM PDT 24
Finished Jun 29 05:50:41 PM PDT 24
Peak memory 218432 kb
Host smart-184c497c-fe4d-4ac2-bcff-c4a3e3d44ed8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128222396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.128222396
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.391413684
Short name T630
Test name
Test status
Simulation time 889478851 ps
CPU time 10.31 seconds
Started Jun 29 05:50:34 PM PDT 24
Finished Jun 29 05:50:45 PM PDT 24
Peak memory 218496 kb
Host smart-d2b42331-e71f-485f-baa5-975bf80c6621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391413684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.391413684
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.801437720
Short name T793
Test name
Test status
Simulation time 29885069 ps
CPU time 1.43 seconds
Started Jun 29 05:50:28 PM PDT 24
Finished Jun 29 05:50:29 PM PDT 24
Peak memory 214036 kb
Host smart-712c653b-f76a-4143-b837-bec99a48f74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801437720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.801437720
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.4192581907
Short name T512
Test name
Test status
Simulation time 228202126 ps
CPU time 25.92 seconds
Started Jun 29 05:50:27 PM PDT 24
Finished Jun 29 05:50:53 PM PDT 24
Peak memory 251204 kb
Host smart-6fce5928-4b9e-4909-bb27-72eafb3398c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192581907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.4192581907
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3197630032
Short name T544
Test name
Test status
Simulation time 502438602 ps
CPU time 3.69 seconds
Started Jun 29 05:50:27 PM PDT 24
Finished Jun 29 05:50:31 PM PDT 24
Peak memory 226540 kb
Host smart-85f27d93-addf-426b-a5d6-75e8059b5f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197630032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3197630032
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.4189309607
Short name T243
Test name
Test status
Simulation time 2207202507 ps
CPU time 37.62 seconds
Started Jun 29 05:50:37 PM PDT 24
Finished Jun 29 05:51:15 PM PDT 24
Peak memory 218076 kb
Host smart-23684615-6005-4cc6-88c2-7d450e607198
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189309607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.4189309607
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.3392708121
Short name T88
Test name
Test status
Simulation time 11196355974 ps
CPU time 205.73 seconds
Started Jun 29 05:50:34 PM PDT 24
Finished Jun 29 05:54:00 PM PDT 24
Peak memory 314856 kb
Host smart-1a7db99e-bf49-433a-9e16-dbe3ab802f24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3392708121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.3392708121
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2257903953
Short name T625
Test name
Test status
Simulation time 29801558 ps
CPU time 0.72 seconds
Started Jun 29 05:50:27 PM PDT 24
Finished Jun 29 05:50:28 PM PDT 24
Peak memory 207296 kb
Host smart-6a5573f3-8eea-44a8-a23e-fb86b0307ff7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257903953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.2257903953
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3173971637
Short name T258
Test name
Test status
Simulation time 18602776 ps
CPU time 0.98 seconds
Started Jun 29 05:50:35 PM PDT 24
Finished Jun 29 05:50:36 PM PDT 24
Peak memory 209168 kb
Host smart-0d624d3b-45f5-42b1-b5de-036cf5061c9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173971637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3173971637
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1678518569
Short name T870
Test name
Test status
Simulation time 499572281 ps
CPU time 21.73 seconds
Started Jun 29 05:50:37 PM PDT 24
Finished Jun 29 05:51:00 PM PDT 24
Peak memory 218364 kb
Host smart-a2856588-a6c2-42b6-abfb-358221156fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678518569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1678518569
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.2618476696
Short name T321
Test name
Test status
Simulation time 4767698842 ps
CPU time 10 seconds
Started Jun 29 05:50:34 PM PDT 24
Finished Jun 29 05:50:45 PM PDT 24
Peak memory 217964 kb
Host smart-484f125c-b8fa-41a2-a3fb-9cb4711cc2f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618476696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.2618476696
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.302108767
Short name T396
Test name
Test status
Simulation time 84390074 ps
CPU time 3.2 seconds
Started Jun 29 05:50:36 PM PDT 24
Finished Jun 29 05:50:40 PM PDT 24
Peak memory 222960 kb
Host smart-c30296ca-cd05-4a90-bf97-5efbb9be4a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302108767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.302108767
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2777428003
Short name T449
Test name
Test status
Simulation time 813209411 ps
CPU time 19.64 seconds
Started Jun 29 05:50:38 PM PDT 24
Finished Jun 29 05:50:58 PM PDT 24
Peak memory 226160 kb
Host smart-d09f79a7-386d-486b-aef1-4e1b84befe47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777428003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2777428003
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.3734306203
Short name T412
Test name
Test status
Simulation time 3003802007 ps
CPU time 15.45 seconds
Started Jun 29 05:50:35 PM PDT 24
Finished Jun 29 05:50:51 PM PDT 24
Peak memory 218520 kb
Host smart-a443fbb3-5463-4b78-aca4-25a3c3868bda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734306203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.3734306203
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2563408248
Short name T775
Test name
Test status
Simulation time 1201723041 ps
CPU time 12.04 seconds
Started Jun 29 05:50:35 PM PDT 24
Finished Jun 29 05:50:47 PM PDT 24
Peak memory 218412 kb
Host smart-c245d6a3-c54c-4167-ac32-9f49e02b0407
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563408248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2563408248
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.546348825
Short name T862
Test name
Test status
Simulation time 689682595 ps
CPU time 8.13 seconds
Started Jun 29 05:50:35 PM PDT 24
Finished Jun 29 05:50:43 PM PDT 24
Peak memory 226148 kb
Host smart-cf2f0084-d1bb-4b23-8147-404a6d59d223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546348825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.546348825
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.981106205
Short name T323
Test name
Test status
Simulation time 385811723 ps
CPU time 3.52 seconds
Started Jun 29 05:50:34 PM PDT 24
Finished Jun 29 05:50:38 PM PDT 24
Peak memory 217928 kb
Host smart-76f5cbd1-4386-477e-aa22-d9e1cd31ec38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981106205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.981106205
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.303915646
Short name T747
Test name
Test status
Simulation time 157317707 ps
CPU time 15.56 seconds
Started Jun 29 05:50:35 PM PDT 24
Finished Jun 29 05:50:51 PM PDT 24
Peak memory 251120 kb
Host smart-3c9bf49f-6d83-4afc-b486-066c2f783da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303915646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.303915646
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1254659469
Short name T408
Test name
Test status
Simulation time 141931877 ps
CPU time 7.42 seconds
Started Jun 29 05:50:34 PM PDT 24
Finished Jun 29 05:50:42 PM PDT 24
Peak memory 251132 kb
Host smart-488772f7-c64a-4895-b686-f9920619ba10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254659469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1254659469
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.1253974587
Short name T582
Test name
Test status
Simulation time 59709671219 ps
CPU time 132 seconds
Started Jun 29 05:50:36 PM PDT 24
Finished Jun 29 05:52:48 PM PDT 24
Peak memory 267688 kb
Host smart-ce3e6b38-04c7-48b5-8fb4-375822026654
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1253974587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.1253974587
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3914287366
Short name T375
Test name
Test status
Simulation time 11799122 ps
CPU time 0.91 seconds
Started Jun 29 05:50:38 PM PDT 24
Finished Jun 29 05:50:40 PM PDT 24
Peak memory 213144 kb
Host smart-9f9fbbce-cf0e-4dd8-b9e9-dd22d4118d9e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914287366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3914287366
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.1711238752
Short name T86
Test name
Test status
Simulation time 24578810 ps
CPU time 1.01 seconds
Started Jun 29 05:50:42 PM PDT 24
Finished Jun 29 05:50:43 PM PDT 24
Peak memory 209156 kb
Host smart-9fae918b-5ab1-4b94-91ab-1299eaa502af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711238752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1711238752
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.1966218281
Short name T578
Test name
Test status
Simulation time 1375319050 ps
CPU time 11.94 seconds
Started Jun 29 05:50:38 PM PDT 24
Finished Jun 29 05:50:50 PM PDT 24
Peak memory 218432 kb
Host smart-b03f193f-d45a-40b4-a7c4-274090e7e5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966218281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1966218281
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.2421409841
Short name T779
Test name
Test status
Simulation time 1486778724 ps
CPU time 4.97 seconds
Started Jun 29 05:50:36 PM PDT 24
Finished Jun 29 05:50:41 PM PDT 24
Peak memory 217536 kb
Host smart-14124c6b-d869-4bad-ae8f-6978b7c235dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421409841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.2421409841
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1115635592
Short name T613
Test name
Test status
Simulation time 170682959 ps
CPU time 3.29 seconds
Started Jun 29 05:50:35 PM PDT 24
Finished Jun 29 05:50:39 PM PDT 24
Peak memory 218480 kb
Host smart-41c50334-2b9d-4be6-aa3f-32b5eceb3a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115635592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1115635592
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1732057827
Short name T545
Test name
Test status
Simulation time 275940081 ps
CPU time 8.87 seconds
Started Jun 29 05:50:43 PM PDT 24
Finished Jun 29 05:50:52 PM PDT 24
Peak memory 219032 kb
Host smart-3dd10601-1ac5-4608-a231-ff0e384adf65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732057827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1732057827
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3723954665
Short name T420
Test name
Test status
Simulation time 9478562178 ps
CPU time 25.7 seconds
Started Jun 29 05:50:41 PM PDT 24
Finished Jun 29 05:51:07 PM PDT 24
Peak memory 218548 kb
Host smart-55e013d4-ffa4-4617-9696-e575e68fe263
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723954665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.3723954665
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3694553775
Short name T581
Test name
Test status
Simulation time 521160290 ps
CPU time 7.1 seconds
Started Jun 29 05:50:42 PM PDT 24
Finished Jun 29 05:50:50 PM PDT 24
Peak memory 218404 kb
Host smart-40bb6f03-3d3c-4c6e-8b0b-96d3d434c0b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694553775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3694553775
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.1590220747
Short name T313
Test name
Test status
Simulation time 1395898638 ps
CPU time 8.83 seconds
Started Jun 29 05:50:34 PM PDT 24
Finished Jun 29 05:50:43 PM PDT 24
Peak memory 218392 kb
Host smart-e475c7d0-02c8-4151-a18a-52b3475fd7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590220747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1590220747
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.1574313487
Short name T742
Test name
Test status
Simulation time 31002282 ps
CPU time 2.42 seconds
Started Jun 29 05:50:33 PM PDT 24
Finished Jun 29 05:50:36 PM PDT 24
Peak memory 218048 kb
Host smart-8f0e7174-77c6-42dd-95e8-412556d91764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574313487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.1574313487
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3403539694
Short name T661
Test name
Test status
Simulation time 249368158 ps
CPU time 26.06 seconds
Started Jun 29 05:50:33 PM PDT 24
Finished Jun 29 05:51:00 PM PDT 24
Peak memory 246548 kb
Host smart-66fd4637-0afa-4924-a5e6-64fc14a0dabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403539694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3403539694
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3250590232
Short name T240
Test name
Test status
Simulation time 181203687 ps
CPU time 7.86 seconds
Started Jun 29 05:50:37 PM PDT 24
Finished Jun 29 05:50:45 PM PDT 24
Peak memory 246156 kb
Host smart-8cc48ac6-e7c5-4dd8-b13d-feba6109622d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250590232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3250590232
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.1177441782
Short name T786
Test name
Test status
Simulation time 70927658864 ps
CPU time 404.15 seconds
Started Jun 29 05:50:50 PM PDT 24
Finished Jun 29 05:57:35 PM PDT 24
Peak memory 242988 kb
Host smart-a2d0c953-343d-42f1-9552-80e7c00d9563
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177441782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.1177441782
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.3173433353
Short name T357
Test name
Test status
Simulation time 18796129 ps
CPU time 0.92 seconds
Started Jun 29 05:50:45 PM PDT 24
Finished Jun 29 05:50:47 PM PDT 24
Peak memory 209040 kb
Host smart-a873bab3-81f4-4361-8d01-7bd4e43e28cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173433353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3173433353
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.2231088506
Short name T680
Test name
Test status
Simulation time 2270259038 ps
CPU time 15.33 seconds
Started Jun 29 05:50:42 PM PDT 24
Finished Jun 29 05:50:57 PM PDT 24
Peak memory 218484 kb
Host smart-e92960b5-ffe1-48fe-896d-523dd74280ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231088506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2231088506
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.1660212637
Short name T470
Test name
Test status
Simulation time 2625953977 ps
CPU time 4.3 seconds
Started Jun 29 05:50:42 PM PDT 24
Finished Jun 29 05:50:46 PM PDT 24
Peak memory 217780 kb
Host smart-fb66ebab-91c8-42e2-988b-6d394ca8542d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660212637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.1660212637
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.3035339031
Short name T162
Test name
Test status
Simulation time 267389521 ps
CPU time 3.61 seconds
Started Jun 29 05:50:45 PM PDT 24
Finished Jun 29 05:50:49 PM PDT 24
Peak memory 218428 kb
Host smart-2faa05e3-57eb-4e7b-9ee9-206a02491b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035339031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3035339031
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.2246167375
Short name T527
Test name
Test status
Simulation time 1707356260 ps
CPU time 14.63 seconds
Started Jun 29 05:50:50 PM PDT 24
Finished Jun 29 05:51:05 PM PDT 24
Peak memory 226236 kb
Host smart-2585dfe9-308e-4edd-a461-230dea8d72a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246167375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.2246167375
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3389071431
Short name T528
Test name
Test status
Simulation time 2098203294 ps
CPU time 9.79 seconds
Started Jun 29 05:50:44 PM PDT 24
Finished Jun 29 05:50:54 PM PDT 24
Peak memory 218460 kb
Host smart-a27f52a5-ce54-4bd1-828d-8af45941c1d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389071431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3389071431
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.382194853
Short name T296
Test name
Test status
Simulation time 323953699 ps
CPU time 12.25 seconds
Started Jun 29 05:50:45 PM PDT 24
Finished Jun 29 05:50:58 PM PDT 24
Peak memory 226248 kb
Host smart-73e27a28-b18a-41de-86d4-8769d3b1c295
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382194853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.382194853
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3662426666
Short name T546
Test name
Test status
Simulation time 805362082 ps
CPU time 9.83 seconds
Started Jun 29 05:50:41 PM PDT 24
Finished Jun 29 05:50:51 PM PDT 24
Peak memory 218544 kb
Host smart-e06a93ca-e54a-4beb-b539-c564cda1a13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662426666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3662426666
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.3542668310
Short name T73
Test name
Test status
Simulation time 59618278 ps
CPU time 2.67 seconds
Started Jun 29 05:50:42 PM PDT 24
Finished Jun 29 05:50:45 PM PDT 24
Peak memory 214860 kb
Host smart-96e6d351-56b4-415f-97e2-d9831ca9a5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542668310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3542668310
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.2206152965
Short name T830
Test name
Test status
Simulation time 437958958 ps
CPU time 28.59 seconds
Started Jun 29 05:50:45 PM PDT 24
Finished Jun 29 05:51:14 PM PDT 24
Peak memory 251032 kb
Host smart-aeb21ff6-a966-47e9-814e-ef8d39f81530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206152965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2206152965
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.3387448518
Short name T497
Test name
Test status
Simulation time 243171391 ps
CPU time 3.7 seconds
Started Jun 29 05:50:42 PM PDT 24
Finished Jun 29 05:50:46 PM PDT 24
Peak memory 222868 kb
Host smart-d9941852-7793-4780-a5cd-2907878476b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387448518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3387448518
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.2938139006
Short name T532
Test name
Test status
Simulation time 9696615886 ps
CPU time 111.11 seconds
Started Jun 29 05:50:41 PM PDT 24
Finished Jun 29 05:52:33 PM PDT 24
Peak memory 281272 kb
Host smart-18a90af7-4ffc-4c02-a5bf-d9559c6185f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938139006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.2938139006
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1182967600
Short name T106
Test name
Test status
Simulation time 20982214 ps
CPU time 0.96 seconds
Started Jun 29 05:50:44 PM PDT 24
Finished Jun 29 05:50:45 PM PDT 24
Peak memory 213360 kb
Host smart-72999a95-2e99-45d9-a21e-8be4ad3daa3d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182967600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1182967600
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.681832240
Short name T530
Test name
Test status
Simulation time 20896580 ps
CPU time 0.98 seconds
Started Jun 29 05:46:16 PM PDT 24
Finished Jun 29 05:46:17 PM PDT 24
Peak memory 209140 kb
Host smart-ae0e2627-2271-4297-812a-6fb201eb28b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681832240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.681832240
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1529576472
Short name T198
Test name
Test status
Simulation time 11254554 ps
CPU time 0.78 seconds
Started Jun 29 05:46:00 PM PDT 24
Finished Jun 29 05:46:02 PM PDT 24
Peak memory 208988 kb
Host smart-b9ee0a18-2f31-4e56-bf6c-660922146533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529576472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1529576472
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1485216765
Short name T808
Test name
Test status
Simulation time 267914980 ps
CPU time 12.15 seconds
Started Jun 29 05:46:01 PM PDT 24
Finished Jun 29 05:46:13 PM PDT 24
Peak memory 218436 kb
Host smart-f08194d7-549d-40db-85e7-c4a0166bff0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485216765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1485216765
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.142617798
Short name T421
Test name
Test status
Simulation time 1506755074 ps
CPU time 5.41 seconds
Started Jun 29 05:46:09 PM PDT 24
Finished Jun 29 05:46:15 PM PDT 24
Peak memory 217600 kb
Host smart-e6331965-db91-4c12-a08d-846ac8c74325
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142617798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.142617798
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.2026599750
Short name T816
Test name
Test status
Simulation time 2295214571 ps
CPU time 37.01 seconds
Started Jun 29 05:46:09 PM PDT 24
Finished Jun 29 05:46:47 PM PDT 24
Peak memory 219144 kb
Host smart-f857f741-c222-416f-bf1d-e8a2ec179b17
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026599750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.2026599750
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.858511833
Short name T763
Test name
Test status
Simulation time 221897575 ps
CPU time 2.31 seconds
Started Jun 29 05:46:08 PM PDT 24
Finished Jun 29 05:46:11 PM PDT 24
Peak memory 217632 kb
Host smart-03151591-a4ec-41fa-bfb4-5c8cbed18235
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858511833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.858511833
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.2730036624
Short name T256
Test name
Test status
Simulation time 1084639797 ps
CPU time 5.34 seconds
Started Jun 29 05:46:07 PM PDT 24
Finished Jun 29 05:46:13 PM PDT 24
Peak memory 218404 kb
Host smart-a66ae9ad-d93b-4f28-ba25-fa81e40cb776
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730036624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.2730036624
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3860274755
Short name T218
Test name
Test status
Simulation time 1810882189 ps
CPU time 12.06 seconds
Started Jun 29 05:46:08 PM PDT 24
Finished Jun 29 05:46:21 PM PDT 24
Peak memory 217912 kb
Host smart-c081e622-4526-4a93-9d5a-82c6be3207db
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860274755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3860274755
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2460565410
Short name T19
Test name
Test status
Simulation time 172457078 ps
CPU time 5.34 seconds
Started Jun 29 05:46:08 PM PDT 24
Finished Jun 29 05:46:14 PM PDT 24
Peak memory 217912 kb
Host smart-e05e04ac-29fb-47a8-9326-59900da81877
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460565410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2460565410
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2260337996
Short name T628
Test name
Test status
Simulation time 1853644184 ps
CPU time 32.95 seconds
Started Jun 29 05:46:09 PM PDT 24
Finished Jun 29 05:46:42 PM PDT 24
Peak memory 250840 kb
Host smart-14aa5f66-501b-4580-a10b-8b293dd5a226
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260337996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2260337996
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2378634591
Short name T16
Test name
Test status
Simulation time 241328965 ps
CPU time 12.2 seconds
Started Jun 29 05:46:08 PM PDT 24
Finished Jun 29 05:46:20 PM PDT 24
Peak memory 245660 kb
Host smart-665cd2f0-ba66-4626-99fc-88ab6c465964
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378634591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.2378634591
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.713632985
Short name T757
Test name
Test status
Simulation time 436852842 ps
CPU time 3.96 seconds
Started Jun 29 05:46:00 PM PDT 24
Finished Jun 29 05:46:04 PM PDT 24
Peak memory 218428 kb
Host smart-957315ff-083e-409a-af77-bb372a9476a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713632985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.713632985
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.40717187
Short name T64
Test name
Test status
Simulation time 1501608914 ps
CPU time 14.33 seconds
Started Jun 29 05:46:00 PM PDT 24
Finished Jun 29 05:46:14 PM PDT 24
Peak memory 215036 kb
Host smart-ce0b4537-7187-4290-aa4d-0732702279a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40717187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.40717187
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.694592353
Short name T111
Test name
Test status
Simulation time 120004910 ps
CPU time 26.2 seconds
Started Jun 29 05:46:09 PM PDT 24
Finished Jun 29 05:46:36 PM PDT 24
Peak memory 269388 kb
Host smart-e74643c9-7d93-4054-8767-cfc666927763
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694592353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.694592353
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.804006001
Short name T657
Test name
Test status
Simulation time 282806849 ps
CPU time 12.38 seconds
Started Jun 29 05:46:07 PM PDT 24
Finished Jun 29 05:46:20 PM PDT 24
Peak memory 226176 kb
Host smart-461922b3-77ac-4fe5-b12e-44a6ec5f5fb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804006001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.804006001
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2151013291
Short name T346
Test name
Test status
Simulation time 612975696 ps
CPU time 12.34 seconds
Started Jun 29 05:46:09 PM PDT 24
Finished Jun 29 05:46:22 PM PDT 24
Peak memory 218524 kb
Host smart-69507d37-ecf6-46c5-90d1-07cbe90a997b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151013291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.2151013291
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1403359999
Short name T829
Test name
Test status
Simulation time 1009643716 ps
CPU time 10.64 seconds
Started Jun 29 05:46:10 PM PDT 24
Finished Jun 29 05:46:21 PM PDT 24
Peak memory 218348 kb
Host smart-2d749922-0b8c-4152-a087-36f570d0bf56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403359999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.1
403359999
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.4029925056
Short name T268
Test name
Test status
Simulation time 1554164562 ps
CPU time 10.54 seconds
Started Jun 29 05:46:00 PM PDT 24
Finished Jun 29 05:46:11 PM PDT 24
Peak memory 218684 kb
Host smart-5ce06706-14f4-4f4d-bfff-549107f1f764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029925056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.4029925056
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3595091671
Short name T282
Test name
Test status
Simulation time 185113426 ps
CPU time 2.52 seconds
Started Jun 29 05:46:03 PM PDT 24
Finished Jun 29 05:46:06 PM PDT 24
Peak memory 214648 kb
Host smart-0f6083ab-2139-45b4-a253-1d45663c8582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595091671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3595091671
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1489396603
Short name T332
Test name
Test status
Simulation time 474137265 ps
CPU time 28.36 seconds
Started Jun 29 05:46:02 PM PDT 24
Finished Jun 29 05:46:30 PM PDT 24
Peak memory 251116 kb
Host smart-a719939d-b117-4de2-985d-befd26b7a5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489396603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1489396603
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.1483952431
Short name T211
Test name
Test status
Simulation time 340815802 ps
CPU time 7.47 seconds
Started Jun 29 05:46:00 PM PDT 24
Finished Jun 29 05:46:08 PM PDT 24
Peak memory 251136 kb
Host smart-e2340d42-08e1-46a4-98aa-de92c0f0b746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483952431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.1483952431
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.477749958
Short name T822
Test name
Test status
Simulation time 8531539975 ps
CPU time 63.71 seconds
Started Jun 29 05:46:08 PM PDT 24
Finished Jun 29 05:47:12 PM PDT 24
Peak memory 272856 kb
Host smart-cd362abe-9d4e-4b44-bc5e-e49bac5ffbe7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477749958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.477749958
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.3997703914
Short name T151
Test name
Test status
Simulation time 20844389391 ps
CPU time 565.83 seconds
Started Jun 29 05:46:08 PM PDT 24
Finished Jun 29 05:55:34 PM PDT 24
Peak memory 265624 kb
Host smart-b84a876c-5552-4099-b5da-bb27887fd600
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3997703914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.3997703914
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3814377773
Short name T228
Test name
Test status
Simulation time 38326257 ps
CPU time 0.99 seconds
Started Jun 29 05:46:01 PM PDT 24
Finished Jun 29 05:46:02 PM PDT 24
Peak memory 212044 kb
Host smart-a68dc402-5ab3-432b-b395-2adff579eee8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814377773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.3814377773
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.2940250475
Short name T607
Test name
Test status
Simulation time 17044084 ps
CPU time 1.16 seconds
Started Jun 29 05:50:50 PM PDT 24
Finished Jun 29 05:50:52 PM PDT 24
Peak memory 209240 kb
Host smart-ac0b78bc-16f5-4fe3-9d29-ce9a722201ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940250475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.2940250475
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.4196157260
Short name T675
Test name
Test status
Simulation time 1443478074 ps
CPU time 15.58 seconds
Started Jun 29 05:50:50 PM PDT 24
Finished Jun 29 05:51:06 PM PDT 24
Peak memory 226244 kb
Host smart-024d8c78-57be-4bdc-a2ff-c5920a64cb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196157260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.4196157260
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.2670364546
Short name T170
Test name
Test status
Simulation time 1081794401 ps
CPU time 7.22 seconds
Started Jun 29 05:50:52 PM PDT 24
Finished Jun 29 05:51:00 PM PDT 24
Peak memory 217532 kb
Host smart-58437fa4-b82e-430a-b088-a72ea63c1fbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670364546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.2670364546
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3397822876
Short name T709
Test name
Test status
Simulation time 284192028 ps
CPU time 2.95 seconds
Started Jun 29 05:50:52 PM PDT 24
Finished Jun 29 05:50:55 PM PDT 24
Peak memory 222844 kb
Host smart-e84445de-3190-4e5f-b0f0-7e24f8e70208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397822876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3397822876
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1108722670
Short name T801
Test name
Test status
Simulation time 4252479209 ps
CPU time 10.52 seconds
Started Jun 29 05:50:51 PM PDT 24
Finished Jun 29 05:51:02 PM PDT 24
Peak memory 226272 kb
Host smart-278392fc-5cfc-407b-93da-1f8acef3792c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108722670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1108722670
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2349314189
Short name T469
Test name
Test status
Simulation time 1483479594 ps
CPU time 18.14 seconds
Started Jun 29 05:50:53 PM PDT 24
Finished Jun 29 05:51:11 PM PDT 24
Peak memory 218460 kb
Host smart-15b977f5-7c28-4305-b5aa-426803f6895d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349314189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2349314189
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.519362063
Short name T807
Test name
Test status
Simulation time 1693082299 ps
CPU time 12.43 seconds
Started Jun 29 05:50:49 PM PDT 24
Finished Jun 29 05:51:02 PM PDT 24
Peak memory 218452 kb
Host smart-e02b77e5-78a5-4488-8181-7c86df1690e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519362063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.519362063
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.2074732530
Short name T101
Test name
Test status
Simulation time 34456341 ps
CPU time 1.31 seconds
Started Jun 29 05:50:43 PM PDT 24
Finished Jun 29 05:50:45 PM PDT 24
Peak memory 213860 kb
Host smart-1c08a709-eb0f-4d2c-b057-30817bb6fbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074732530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.2074732530
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.207776169
Short name T501
Test name
Test status
Simulation time 238196495 ps
CPU time 37.48 seconds
Started Jun 29 05:50:50 PM PDT 24
Finished Jun 29 05:51:28 PM PDT 24
Peak memory 251132 kb
Host smart-b7311d0c-2796-44cf-aaf8-a401c31d993d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207776169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.207776169
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.1088912180
Short name T33
Test name
Test status
Simulation time 200678532 ps
CPU time 6.64 seconds
Started Jun 29 05:50:51 PM PDT 24
Finished Jun 29 05:50:58 PM PDT 24
Peak memory 251124 kb
Host smart-71ccb99f-819e-499e-bde6-ceeafdb4258d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088912180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.1088912180
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1942971242
Short name T77
Test name
Test status
Simulation time 122031387949 ps
CPU time 284.74 seconds
Started Jun 29 05:50:50 PM PDT 24
Finished Jun 29 05:55:36 PM PDT 24
Peak memory 316688 kb
Host smart-39b05778-c629-49bd-9ca5-7ecffdf17de7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942971242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1942971242
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2606257128
Short name T663
Test name
Test status
Simulation time 31720887 ps
CPU time 0.86 seconds
Started Jun 29 05:50:50 PM PDT 24
Finished Jun 29 05:50:51 PM PDT 24
Peak memory 212144 kb
Host smart-7d2a399d-f918-4b0f-a423-3fd98e70a52d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606257128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.2606257128
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.1486125555
Short name T99
Test name
Test status
Simulation time 25598350 ps
CPU time 1 seconds
Started Jun 29 05:50:51 PM PDT 24
Finished Jun 29 05:50:52 PM PDT 24
Peak memory 209168 kb
Host smart-ff670fe1-3f2f-4648-be2f-f2f5b40bb2e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486125555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.1486125555
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.3365705274
Short name T213
Test name
Test status
Simulation time 290315734 ps
CPU time 12.97 seconds
Started Jun 29 05:50:50 PM PDT 24
Finished Jun 29 05:51:03 PM PDT 24
Peak memory 226260 kb
Host smart-9c793fab-a2cc-43c6-bdf6-6ac5db51d845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365705274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3365705274
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3627643600
Short name T705
Test name
Test status
Simulation time 1689798410 ps
CPU time 5.5 seconds
Started Jun 29 05:50:51 PM PDT 24
Finished Jun 29 05:50:57 PM PDT 24
Peak memory 217252 kb
Host smart-343f45db-386c-4a0a-82ff-e460ac82c5a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627643600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.3627643600
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.4008624920
Short name T1
Test name
Test status
Simulation time 289685535 ps
CPU time 3.04 seconds
Started Jun 29 05:50:50 PM PDT 24
Finished Jun 29 05:50:54 PM PDT 24
Peak memory 218416 kb
Host smart-302afee5-4c51-40d5-a921-1aa6b52f518f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008624920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.4008624920
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.2484331705
Short name T632
Test name
Test status
Simulation time 1302916331 ps
CPU time 17.19 seconds
Started Jun 29 05:50:50 PM PDT 24
Finished Jun 29 05:51:08 PM PDT 24
Peak memory 219096 kb
Host smart-943694fe-c4d8-4ab4-b53e-850f811e73c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484331705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.2484331705
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.1280091696
Short name T790
Test name
Test status
Simulation time 4685448852 ps
CPU time 10.27 seconds
Started Jun 29 05:50:54 PM PDT 24
Finished Jun 29 05:51:05 PM PDT 24
Peak memory 218692 kb
Host smart-464d3b9c-3a53-41f9-a5c8-1a352b009913
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280091696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.1280091696
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.239787996
Short name T450
Test name
Test status
Simulation time 2999304066 ps
CPU time 12.21 seconds
Started Jun 29 05:50:50 PM PDT 24
Finished Jun 29 05:51:02 PM PDT 24
Peak memory 226312 kb
Host smart-07064cd0-f6e3-41af-a6a7-f1afbbd65dfa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239787996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.239787996
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3593867924
Short name T697
Test name
Test status
Simulation time 1710712385 ps
CPU time 7.8 seconds
Started Jun 29 05:50:53 PM PDT 24
Finished Jun 29 05:51:01 PM PDT 24
Peak memory 225412 kb
Host smart-c93aff3e-3527-4fb2-b0d4-8f524befe8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593867924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3593867924
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.410320947
Short name T368
Test name
Test status
Simulation time 41154987 ps
CPU time 1.61 seconds
Started Jun 29 05:50:52 PM PDT 24
Finished Jun 29 05:50:54 PM PDT 24
Peak memory 217920 kb
Host smart-694fc0c9-401b-43a1-84fe-83f6809d9890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410320947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.410320947
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.1876083530
Short name T70
Test name
Test status
Simulation time 401997450 ps
CPU time 20.15 seconds
Started Jun 29 05:50:50 PM PDT 24
Finished Jun 29 05:51:11 PM PDT 24
Peak memory 251104 kb
Host smart-f334353d-305c-4b03-95e8-83ee3f1bf7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876083530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1876083530
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.883694115
Short name T784
Test name
Test status
Simulation time 119209071 ps
CPU time 3.67 seconds
Started Jun 29 05:50:52 PM PDT 24
Finished Jun 29 05:50:56 PM PDT 24
Peak memory 222628 kb
Host smart-2091078e-08fd-4782-bba3-1b6194f42706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883694115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.883694115
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1366099448
Short name T224
Test name
Test status
Simulation time 10524589329 ps
CPU time 229.08 seconds
Started Jun 29 05:50:53 PM PDT 24
Finished Jun 29 05:54:43 PM PDT 24
Peak memory 251176 kb
Host smart-3504f745-c0c6-4cb6-88aa-328df7e36bcf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366099448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1366099448
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3790161550
Short name T803
Test name
Test status
Simulation time 10703315 ps
CPU time 0.87 seconds
Started Jun 29 05:50:54 PM PDT 24
Finished Jun 29 05:50:56 PM PDT 24
Peak memory 208496 kb
Host smart-71f9793f-e511-47fe-8c88-1eec90706e53
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790161550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.3790161550
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.3815355514
Short name T718
Test name
Test status
Simulation time 38887530 ps
CPU time 0.97 seconds
Started Jun 29 05:51:00 PM PDT 24
Finished Jun 29 05:51:01 PM PDT 24
Peak memory 209084 kb
Host smart-126e873a-15af-4cf5-a26b-e7c6f1540def
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815355514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3815355514
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3340653812
Short name T844
Test name
Test status
Simulation time 518900688 ps
CPU time 14.82 seconds
Started Jun 29 05:51:00 PM PDT 24
Finished Jun 29 05:51:15 PM PDT 24
Peak memory 226260 kb
Host smart-91affcd7-a246-4f73-8945-71e62b915bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340653812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3340653812
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.2087138050
Short name T596
Test name
Test status
Simulation time 1038901634 ps
CPU time 12.44 seconds
Started Jun 29 05:51:00 PM PDT 24
Finished Jun 29 05:51:14 PM PDT 24
Peak memory 217432 kb
Host smart-82e4cef8-6b33-45f9-8f78-bfb584d739cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087138050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.2087138050
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2307246291
Short name T460
Test name
Test status
Simulation time 226735777 ps
CPU time 2.98 seconds
Started Jun 29 05:51:00 PM PDT 24
Finished Jun 29 05:51:04 PM PDT 24
Peak memory 222692 kb
Host smart-2a922a81-8615-4936-9c83-85ccd1f32e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307246291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2307246291
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.4010196430
Short name T390
Test name
Test status
Simulation time 1033090147 ps
CPU time 12.58 seconds
Started Jun 29 05:50:59 PM PDT 24
Finished Jun 29 05:51:12 PM PDT 24
Peak memory 226240 kb
Host smart-404b275f-6dad-4bdc-b7f8-f5bf6034d2fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010196430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.4010196430
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1763357346
Short name T215
Test name
Test status
Simulation time 1252583943 ps
CPU time 11.35 seconds
Started Jun 29 05:51:00 PM PDT 24
Finished Jun 29 05:51:12 PM PDT 24
Peak memory 218408 kb
Host smart-c7695d15-35d3-402f-ae83-3176dee52039
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763357346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.1763357346
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.1831180237
Short name T800
Test name
Test status
Simulation time 704818728 ps
CPU time 14.11 seconds
Started Jun 29 05:50:58 PM PDT 24
Finished Jun 29 05:51:13 PM PDT 24
Peak memory 226248 kb
Host smart-906bf5b3-f52b-4b34-89f4-b054e1cad781
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831180237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
1831180237
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.35802645
Short name T255
Test name
Test status
Simulation time 347132633 ps
CPU time 9.52 seconds
Started Jun 29 05:51:02 PM PDT 24
Finished Jun 29 05:51:12 PM PDT 24
Peak memory 218496 kb
Host smart-eda9bcde-e27e-47ae-963c-ffdf287259b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35802645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.35802645
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.4098003632
Short name T602
Test name
Test status
Simulation time 84895167 ps
CPU time 2.69 seconds
Started Jun 29 05:51:00 PM PDT 24
Finished Jun 29 05:51:04 PM PDT 24
Peak memory 214804 kb
Host smart-15adf21f-595b-45d2-a411-18af18a7c719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098003632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.4098003632
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.4046810270
Short name T611
Test name
Test status
Simulation time 286995303 ps
CPU time 27.31 seconds
Started Jun 29 05:51:04 PM PDT 24
Finished Jun 29 05:51:31 PM PDT 24
Peak memory 251132 kb
Host smart-3e0b08d3-64b5-4092-9589-f48bc5680440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046810270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.4046810270
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.2293086415
Short name T626
Test name
Test status
Simulation time 77379058 ps
CPU time 6.11 seconds
Started Jun 29 05:50:58 PM PDT 24
Finished Jun 29 05:51:04 PM PDT 24
Peak memory 246796 kb
Host smart-70e72f1f-b937-4daf-aaf9-41ca5c9b8267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293086415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2293086415
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.1328675611
Short name T726
Test name
Test status
Simulation time 18665930830 ps
CPU time 79.26 seconds
Started Jun 29 05:50:59 PM PDT 24
Finished Jun 29 05:52:19 PM PDT 24
Peak memory 267556 kb
Host smart-1919c8cf-4ed6-4aae-8b79-c20377e49e95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328675611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.1328675611
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.4211187835
Short name T723
Test name
Test status
Simulation time 11699179 ps
CPU time 1.03 seconds
Started Jun 29 05:51:00 PM PDT 24
Finished Jun 29 05:51:02 PM PDT 24
Peak memory 212076 kb
Host smart-660a5bca-f215-4b27-9cb6-586e0bf25046
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211187835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.4211187835
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.1520532349
Short name T315
Test name
Test status
Simulation time 28597697 ps
CPU time 0.96 seconds
Started Jun 29 05:51:07 PM PDT 24
Finished Jun 29 05:51:08 PM PDT 24
Peak memory 209256 kb
Host smart-72a0f5d3-49fa-4dea-8e21-10826040657c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520532349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.1520532349
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.3245444440
Short name T745
Test name
Test status
Simulation time 374083681 ps
CPU time 12.18 seconds
Started Jun 29 05:51:00 PM PDT 24
Finished Jun 29 05:51:13 PM PDT 24
Peak memory 226244 kb
Host smart-9f6223cd-22df-4891-98f2-5c172f51b4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245444440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3245444440
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.1344161986
Short name T322
Test name
Test status
Simulation time 293309733 ps
CPU time 7.2 seconds
Started Jun 29 05:51:00 PM PDT 24
Finished Jun 29 05:51:08 PM PDT 24
Peak memory 217516 kb
Host smart-e4a4dfd1-28da-4f76-87a2-0f624a170195
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344161986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.1344161986
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.2332131048
Short name T642
Test name
Test status
Simulation time 29959711 ps
CPU time 1.77 seconds
Started Jun 29 05:51:01 PM PDT 24
Finished Jun 29 05:51:04 PM PDT 24
Peak memory 218428 kb
Host smart-6190556f-e871-4114-b97e-bec54409d56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332131048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.2332131048
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1936121060
Short name T372
Test name
Test status
Simulation time 513490103 ps
CPU time 7.75 seconds
Started Jun 29 05:51:06 PM PDT 24
Finished Jun 29 05:51:15 PM PDT 24
Peak memory 218520 kb
Host smart-ab6f92e7-0759-4436-8a0e-89c8d34f5472
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936121060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.1936121060
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2900610186
Short name T518
Test name
Test status
Simulation time 1237822544 ps
CPU time 9.61 seconds
Started Jun 29 05:51:06 PM PDT 24
Finished Jun 29 05:51:16 PM PDT 24
Peak memory 218416 kb
Host smart-f4f58f2b-5e9c-45af-a92f-e3468f133ec9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900610186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2900610186
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.3641625911
Short name T668
Test name
Test status
Simulation time 1539531685 ps
CPU time 14.82 seconds
Started Jun 29 05:51:00 PM PDT 24
Finished Jun 29 05:51:16 PM PDT 24
Peak memory 226456 kb
Host smart-5074c4ee-f734-4b39-b0f5-7dd5187036d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641625911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3641625911
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.1801783682
Short name T359
Test name
Test status
Simulation time 447867934 ps
CPU time 5.97 seconds
Started Jun 29 05:50:58 PM PDT 24
Finished Jun 29 05:51:05 PM PDT 24
Peak memory 217932 kb
Host smart-f5461609-28b1-474d-ad6d-2ba6ea9be900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801783682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.1801783682
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.852256191
Short name T89
Test name
Test status
Simulation time 321643407 ps
CPU time 29.8 seconds
Started Jun 29 05:50:59 PM PDT 24
Finished Jun 29 05:51:29 PM PDT 24
Peak memory 251084 kb
Host smart-af9a6531-158e-4bf1-af83-b2162df0cf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852256191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.852256191
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2924954569
Short name T676
Test name
Test status
Simulation time 81404329 ps
CPU time 9.82 seconds
Started Jun 29 05:51:00 PM PDT 24
Finished Jun 29 05:51:11 PM PDT 24
Peak memory 251080 kb
Host smart-1351412e-4b23-45b9-b24c-0925a36263d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924954569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2924954569
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.2098325813
Short name T173
Test name
Test status
Simulation time 22352544788 ps
CPU time 313.38 seconds
Started Jun 29 05:51:07 PM PDT 24
Finished Jun 29 05:56:21 PM PDT 24
Peak memory 288308 kb
Host smart-d5e04494-bec6-4991-964a-f9103e7c0274
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098325813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.2098325813
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.3370817060
Short name T112
Test name
Test status
Simulation time 85524001985 ps
CPU time 543.17 seconds
Started Jun 29 05:51:06 PM PDT 24
Finished Jun 29 06:00:10 PM PDT 24
Peak memory 332328 kb
Host smart-5e95236a-7138-48ca-9208-e1ee7b9cab58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3370817060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.3370817060
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.814219694
Short name T362
Test name
Test status
Simulation time 12536955 ps
CPU time 1.04 seconds
Started Jun 29 05:50:59 PM PDT 24
Finished Jun 29 05:51:01 PM PDT 24
Peak memory 211948 kb
Host smart-b4b22cf9-214b-4ca4-980b-c31ba5cb4950
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814219694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ct
rl_volatile_unlock_smoke.814219694
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1980531486
Short name T75
Test name
Test status
Simulation time 15689135 ps
CPU time 1 seconds
Started Jun 29 05:51:10 PM PDT 24
Finished Jun 29 05:51:12 PM PDT 24
Peak memory 209128 kb
Host smart-48d3ad12-0efa-4da8-aebb-6d57b696b3e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980531486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1980531486
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2234384711
Short name T226
Test name
Test status
Simulation time 390043796 ps
CPU time 15.5 seconds
Started Jun 29 05:51:05 PM PDT 24
Finished Jun 29 05:51:20 PM PDT 24
Peak memory 218348 kb
Host smart-5624060f-a4f0-4b65-9380-fba868a76f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234384711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2234384711
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.1437732044
Short name T431
Test name
Test status
Simulation time 4926916096 ps
CPU time 26.83 seconds
Started Jun 29 05:51:07 PM PDT 24
Finished Jun 29 05:51:34 PM PDT 24
Peak memory 217976 kb
Host smart-4976d669-534f-4b4e-ac6f-d3a8e1892270
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437732044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.1437732044
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2664699853
Short name T414
Test name
Test status
Simulation time 37385937 ps
CPU time 1.87 seconds
Started Jun 29 05:51:06 PM PDT 24
Finished Jun 29 05:51:08 PM PDT 24
Peak memory 222132 kb
Host smart-cf3e7ac6-2384-40dd-ae15-6a2c3d01f136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664699853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2664699853
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.2605575927
Short name T749
Test name
Test status
Simulation time 6102132863 ps
CPU time 17.5 seconds
Started Jun 29 05:51:06 PM PDT 24
Finished Jun 29 05:51:24 PM PDT 24
Peak memory 226296 kb
Host smart-92f8f077-24df-4514-a458-8179ebe90d02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605575927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2605575927
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2349388193
Short name T406
Test name
Test status
Simulation time 385853091 ps
CPU time 15.36 seconds
Started Jun 29 05:51:09 PM PDT 24
Finished Jun 29 05:51:25 PM PDT 24
Peak memory 218424 kb
Host smart-ab2c3980-7566-473f-bac9-5017709114b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349388193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2349388193
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.2791819679
Short name T244
Test name
Test status
Simulation time 276536414 ps
CPU time 9.73 seconds
Started Jun 29 05:51:06 PM PDT 24
Finished Jun 29 05:51:16 PM PDT 24
Peak memory 218388 kb
Host smart-0f2df77e-ad7d-4392-99a3-daf4f2fa60a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791819679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
2791819679
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.840606916
Short name T659
Test name
Test status
Simulation time 366026849 ps
CPU time 13.52 seconds
Started Jun 29 05:51:05 PM PDT 24
Finished Jun 29 05:51:19 PM PDT 24
Peak memory 218488 kb
Host smart-2e6b5417-870a-4eda-bbc1-5a0fc9632ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840606916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.840606916
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.1893167771
Short name T488
Test name
Test status
Simulation time 518230142 ps
CPU time 3.14 seconds
Started Jun 29 05:51:07 PM PDT 24
Finished Jun 29 05:51:10 PM PDT 24
Peak memory 215248 kb
Host smart-ebc468f4-7f11-43ea-976a-eaf9c87a105d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893167771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.1893167771
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3713422547
Short name T339
Test name
Test status
Simulation time 592692451 ps
CPU time 25.48 seconds
Started Jun 29 05:51:07 PM PDT 24
Finished Jun 29 05:51:33 PM PDT 24
Peak memory 251132 kb
Host smart-1f00baa2-5301-4130-9e89-3b30ab3ca0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713422547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3713422547
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.193276000
Short name T864
Test name
Test status
Simulation time 1335001343 ps
CPU time 8.77 seconds
Started Jun 29 05:51:07 PM PDT 24
Finished Jun 29 05:51:16 PM PDT 24
Peak memory 251128 kb
Host smart-4827dc60-ef9b-4b18-9e1f-e4e150d647dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193276000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.193276000
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.3476098578
Short name T17
Test name
Test status
Simulation time 16306717387 ps
CPU time 77.91 seconds
Started Jun 29 05:51:06 PM PDT 24
Finished Jun 29 05:52:24 PM PDT 24
Peak memory 236204 kb
Host smart-41c4b1e2-78c2-455a-881b-1ca0545e25e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476098578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.3476098578
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2097954399
Short name T271
Test name
Test status
Simulation time 21395971 ps
CPU time 0.91 seconds
Started Jun 29 05:51:09 PM PDT 24
Finished Jun 29 05:51:10 PM PDT 24
Peak memory 212092 kb
Host smart-d0e025b0-e32c-4d1d-9d18-7bbff336cda5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097954399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.2097954399
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.2836243083
Short name T468
Test name
Test status
Simulation time 122699863 ps
CPU time 1.08 seconds
Started Jun 29 05:51:15 PM PDT 24
Finished Jun 29 05:51:17 PM PDT 24
Peak memory 209220 kb
Host smart-03c6ec7b-d629-4ae3-b5d0-b8b4414dc926
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836243083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2836243083
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1580988481
Short name T867
Test name
Test status
Simulation time 354320537 ps
CPU time 16.04 seconds
Started Jun 29 05:51:12 PM PDT 24
Finished Jun 29 05:51:29 PM PDT 24
Peak memory 218256 kb
Host smart-5a05abce-6dd7-40b7-92a9-93896cda489b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580988481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1580988481
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.2809772753
Short name T25
Test name
Test status
Simulation time 2200995081 ps
CPU time 6.16 seconds
Started Jun 29 05:51:12 PM PDT 24
Finished Jun 29 05:51:19 PM PDT 24
Peak memory 217548 kb
Host smart-805d3a06-840d-470e-8627-55f4a6210259
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809772753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.2809772753
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2225901619
Short name T477
Test name
Test status
Simulation time 103371956 ps
CPU time 3.41 seconds
Started Jun 29 05:51:14 PM PDT 24
Finished Jun 29 05:51:18 PM PDT 24
Peak memory 218444 kb
Host smart-e3f9840f-82f8-4735-b369-aa00618732eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225901619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2225901619
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.3470904468
Short name T473
Test name
Test status
Simulation time 228900344 ps
CPU time 11.93 seconds
Started Jun 29 05:51:15 PM PDT 24
Finished Jun 29 05:51:27 PM PDT 24
Peak memory 226308 kb
Host smart-f0d6693c-7e4e-4c11-8265-6130a615b950
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470904468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.3470904468
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1502131700
Short name T777
Test name
Test status
Simulation time 492992562 ps
CPU time 12.61 seconds
Started Jun 29 05:51:15 PM PDT 24
Finished Jun 29 05:51:28 PM PDT 24
Peak memory 218464 kb
Host smart-9a1bca1a-4369-452f-848e-ef88a1b3ae38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502131700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.1502131700
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2328297688
Short name T609
Test name
Test status
Simulation time 374818142 ps
CPU time 9.26 seconds
Started Jun 29 05:51:14 PM PDT 24
Finished Jun 29 05:51:23 PM PDT 24
Peak memory 226248 kb
Host smart-ed99955b-c611-4830-b76a-4429a94a21dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328297688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
2328297688
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.3445580362
Short name T662
Test name
Test status
Simulation time 501779537 ps
CPU time 8.79 seconds
Started Jun 29 05:51:13 PM PDT 24
Finished Jun 29 05:51:23 PM PDT 24
Peak memory 224816 kb
Host smart-dc156e93-c9e0-4f8b-833e-843ba0b8a3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445580362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.3445580362
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.1419690844
Short name T756
Test name
Test status
Simulation time 74438350 ps
CPU time 3.69 seconds
Started Jun 29 05:51:09 PM PDT 24
Finished Jun 29 05:51:13 PM PDT 24
Peak memory 217928 kb
Host smart-eff93d7d-f88a-44df-ae52-6974a8a90154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419690844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.1419690844
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.3608651158
Short name T448
Test name
Test status
Simulation time 339896566 ps
CPU time 29.26 seconds
Started Jun 29 05:51:15 PM PDT 24
Finished Jun 29 05:51:44 PM PDT 24
Peak memory 251120 kb
Host smart-f0439353-d755-4791-a61c-7255927a9b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608651158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.3608651158
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.4000619832
Short name T553
Test name
Test status
Simulation time 82350970 ps
CPU time 7.54 seconds
Started Jun 29 05:51:13 PM PDT 24
Finished Jun 29 05:51:21 PM PDT 24
Peak memory 251200 kb
Host smart-4ca7adfd-8aaa-43a3-b83f-c4624dcfc126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000619832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.4000619832
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.1851139209
Short name T514
Test name
Test status
Simulation time 4659555247 ps
CPU time 161.8 seconds
Started Jun 29 05:51:13 PM PDT 24
Finished Jun 29 05:53:56 PM PDT 24
Peak memory 496432 kb
Host smart-8ceb82ad-5d32-471f-b2dc-d7f3b3103880
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851139209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.1851139209
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.3847111690
Short name T308
Test name
Test status
Simulation time 12713164 ps
CPU time 0.95 seconds
Started Jun 29 05:51:13 PM PDT 24
Finished Jun 29 05:51:15 PM PDT 24
Peak memory 212172 kb
Host smart-83ded2c3-f8ff-41df-934e-e8c165826aaa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847111690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.3847111690
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.1576869985
Short name T272
Test name
Test status
Simulation time 145374405 ps
CPU time 1.01 seconds
Started Jun 29 05:51:23 PM PDT 24
Finished Jun 29 05:51:24 PM PDT 24
Peak memory 209276 kb
Host smart-041f3c0b-aca5-4958-ac81-7cd3aa11071b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576869985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1576869985
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2001356152
Short name T505
Test name
Test status
Simulation time 668170013 ps
CPU time 10.17 seconds
Started Jun 29 05:51:23 PM PDT 24
Finished Jun 29 05:51:34 PM PDT 24
Peak memory 226320 kb
Host smart-448f757b-3a91-4d65-8e5e-2558efd446bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001356152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2001356152
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1000811354
Short name T552
Test name
Test status
Simulation time 197947113 ps
CPU time 5.26 seconds
Started Jun 29 05:51:23 PM PDT 24
Finished Jun 29 05:51:29 PM PDT 24
Peak memory 217308 kb
Host smart-b962824a-0063-459e-bda1-bb3619edc2c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000811354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.1000811354
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.1713156715
Short name T815
Test name
Test status
Simulation time 133831090 ps
CPU time 2.19 seconds
Started Jun 29 05:51:23 PM PDT 24
Finished Jun 29 05:51:25 PM PDT 24
Peak memory 218412 kb
Host smart-7f719fdb-8fee-434e-a1bc-373bc87ed7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713156715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1713156715
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.865198914
Short name T314
Test name
Test status
Simulation time 300286681 ps
CPU time 15.01 seconds
Started Jun 29 05:51:23 PM PDT 24
Finished Jun 29 05:51:38 PM PDT 24
Peak memory 226140 kb
Host smart-8ffae8fb-5889-4ced-987b-c6cf6fad80bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865198914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.865198914
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1455609098
Short name T640
Test name
Test status
Simulation time 723581148 ps
CPU time 15.16 seconds
Started Jun 29 05:51:23 PM PDT 24
Finished Jun 29 05:51:39 PM PDT 24
Peak memory 218400 kb
Host smart-3308a57c-0a61-4504-8918-2bfb043576a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455609098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.1455609098
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3660422980
Short name T388
Test name
Test status
Simulation time 328557457 ps
CPU time 11.35 seconds
Started Jun 29 05:51:23 PM PDT 24
Finished Jun 29 05:51:35 PM PDT 24
Peak memory 226252 kb
Host smart-6719ebb5-d56f-428c-a7ab-3fef64a2352b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660422980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3660422980
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1080767807
Short name T49
Test name
Test status
Simulation time 1286968666 ps
CPU time 8.69 seconds
Started Jun 29 05:51:25 PM PDT 24
Finished Jun 29 05:51:34 PM PDT 24
Peak memory 218560 kb
Host smart-b58d4142-af36-4b16-8aed-9a2efc9feb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080767807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1080767807
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1960139965
Short name T363
Test name
Test status
Simulation time 105572286 ps
CPU time 1.42 seconds
Started Jun 29 05:51:14 PM PDT 24
Finished Jun 29 05:51:16 PM PDT 24
Peak memory 217924 kb
Host smart-d9830dbc-dfe4-4fa2-be3b-48ecb50c8f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960139965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1960139965
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3231231433
Short name T250
Test name
Test status
Simulation time 291045290 ps
CPU time 26.37 seconds
Started Jun 29 05:51:23 PM PDT 24
Finished Jun 29 05:51:50 PM PDT 24
Peak memory 251140 kb
Host smart-ed5ccbe7-0fcb-4103-b40e-a7040b9b987a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231231433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3231231433
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.1164269333
Short name T573
Test name
Test status
Simulation time 97729634 ps
CPU time 7.18 seconds
Started Jun 29 05:51:26 PM PDT 24
Finished Jun 29 05:51:33 PM PDT 24
Peak memory 244600 kb
Host smart-d512240f-ce6b-4973-a63a-ddfc124f3e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164269333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1164269333
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.925591486
Short name T283
Test name
Test status
Simulation time 1711913283 ps
CPU time 29.41 seconds
Started Jun 29 05:51:27 PM PDT 24
Finished Jun 29 05:51:56 PM PDT 24
Peak memory 245684 kb
Host smart-d1f24cae-8a19-4ebf-a2be-52f41ee0e334
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925591486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.925591486
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.2490786349
Short name T644
Test name
Test status
Simulation time 381521453839 ps
CPU time 886.89 seconds
Started Jun 29 05:51:24 PM PDT 24
Finished Jun 29 06:06:11 PM PDT 24
Peak memory 389556 kb
Host smart-4aa7704d-d86d-4f51-81d1-a71880f34cad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2490786349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.2490786349
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3117957539
Short name T688
Test name
Test status
Simulation time 162755436 ps
CPU time 1.02 seconds
Started Jun 29 05:51:13 PM PDT 24
Finished Jun 29 05:51:15 PM PDT 24
Peak memory 211964 kb
Host smart-52347435-2379-48d6-a18c-ceb4ff2d81bf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117957539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3117957539
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.3426443801
Short name T621
Test name
Test status
Simulation time 76992347 ps
CPU time 0.98 seconds
Started Jun 29 05:51:24 PM PDT 24
Finished Jun 29 05:51:25 PM PDT 24
Peak memory 209156 kb
Host smart-9f9ec768-2d92-4f76-9357-6881108091b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426443801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.3426443801
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.2992345571
Short name T794
Test name
Test status
Simulation time 1083632117 ps
CPU time 7.72 seconds
Started Jun 29 05:51:23 PM PDT 24
Finished Jun 29 05:51:31 PM PDT 24
Peak memory 226216 kb
Host smart-1c8d30b4-d505-4d6a-b2e1-dc5ec1b67fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992345571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.2992345571
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.1361945800
Short name T324
Test name
Test status
Simulation time 172677677 ps
CPU time 2.82 seconds
Started Jun 29 05:51:22 PM PDT 24
Finished Jun 29 05:51:25 PM PDT 24
Peak memory 217264 kb
Host smart-9e695507-53f4-4043-bc87-b767c3e45d79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361945800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.1361945800
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.3158896390
Short name T415
Test name
Test status
Simulation time 95544848 ps
CPU time 3.22 seconds
Started Jun 29 05:51:23 PM PDT 24
Finished Jun 29 05:51:27 PM PDT 24
Peak memory 222868 kb
Host smart-88d67444-46b3-4da6-9350-44461e2ce8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158896390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.3158896390
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.1614703698
Short name T752
Test name
Test status
Simulation time 224861395 ps
CPU time 10.67 seconds
Started Jun 29 05:51:24 PM PDT 24
Finished Jun 29 05:51:35 PM PDT 24
Peak memory 219088 kb
Host smart-22f30849-8f41-4102-bad5-ddda5eba448f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614703698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.1614703698
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.2319412789
Short name T160
Test name
Test status
Simulation time 424086180 ps
CPU time 12.75 seconds
Started Jun 29 05:51:23 PM PDT 24
Finished Jun 29 05:51:37 PM PDT 24
Peak memory 218456 kb
Host smart-4b0e8494-b396-4ba3-8a7c-e1415c972587
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319412789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.2319412789
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1994298776
Short name T267
Test name
Test status
Simulation time 1356241072 ps
CPU time 11.78 seconds
Started Jun 29 05:51:23 PM PDT 24
Finished Jun 29 05:51:36 PM PDT 24
Peak memory 218424 kb
Host smart-29bbc27d-914d-49f6-8840-e5c8d2ad65cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994298776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1994298776
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.1625100086
Short name T636
Test name
Test status
Simulation time 1076657908 ps
CPU time 10.5 seconds
Started Jun 29 05:51:24 PM PDT 24
Finished Jun 29 05:51:35 PM PDT 24
Peak memory 218464 kb
Host smart-3243864e-f215-49e2-a926-67b0aaa676c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625100086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.1625100086
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.789941522
Short name T293
Test name
Test status
Simulation time 47218404 ps
CPU time 2.97 seconds
Started Jun 29 05:51:22 PM PDT 24
Finished Jun 29 05:51:25 PM PDT 24
Peak memory 223828 kb
Host smart-c5aff0c8-af1d-4641-8c26-9c54d2a9892a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789941522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.789941522
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3716785613
Short name T404
Test name
Test status
Simulation time 273541319 ps
CPU time 29.53 seconds
Started Jun 29 05:51:23 PM PDT 24
Finished Jun 29 05:51:54 PM PDT 24
Peak memory 251136 kb
Host smart-9e603c70-1f40-41e1-9252-e7ceab05bebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716785613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3716785613
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2608300270
Short name T219
Test name
Test status
Simulation time 79867730 ps
CPU time 7.31 seconds
Started Jun 29 05:51:23 PM PDT 24
Finished Jun 29 05:51:31 PM PDT 24
Peak memory 250604 kb
Host smart-28a3f59a-2658-4eb8-ba9f-b185de434b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608300270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2608300270
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.2585260073
Short name T96
Test name
Test status
Simulation time 73123211887 ps
CPU time 375.62 seconds
Started Jun 29 05:51:26 PM PDT 24
Finished Jun 29 05:57:42 PM PDT 24
Peak memory 283828 kb
Host smart-45f56cf5-c958-4583-ba5c-1b06061422b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585260073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.2585260073
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1951576786
Short name T840
Test name
Test status
Simulation time 13829590 ps
CPU time 1.09 seconds
Started Jun 29 05:51:24 PM PDT 24
Finished Jun 29 05:51:25 PM PDT 24
Peak memory 212156 kb
Host smart-230d7629-0c3e-4f09-ab74-0aab8a466895
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951576786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.1951576786
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1011097960
Short name T254
Test name
Test status
Simulation time 52162892 ps
CPU time 1.04 seconds
Started Jun 29 05:51:30 PM PDT 24
Finished Jun 29 05:51:32 PM PDT 24
Peak memory 209188 kb
Host smart-cd6367bd-12a2-4f95-abad-be6e63a2d84b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011097960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1011097960
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1224055973
Short name T342
Test name
Test status
Simulation time 382464254 ps
CPU time 14.07 seconds
Started Jun 29 05:51:32 PM PDT 24
Finished Jun 29 05:51:47 PM PDT 24
Peak memory 226464 kb
Host smart-d3460be5-9a52-496c-bcbc-ef1c55685383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224055973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1224055973
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.3438251409
Short name T165
Test name
Test status
Simulation time 562551484 ps
CPU time 4.6 seconds
Started Jun 29 05:51:30 PM PDT 24
Finished Jun 29 05:51:35 PM PDT 24
Peak memory 217596 kb
Host smart-c9b08bc5-388d-432b-91ee-1c2bc2cec258
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438251409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.3438251409
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.1841505429
Short name T223
Test name
Test status
Simulation time 430258676 ps
CPU time 4.76 seconds
Started Jun 29 05:51:35 PM PDT 24
Finished Jun 29 05:51:40 PM PDT 24
Peak memory 218440 kb
Host smart-ed5271db-f34a-4072-9cdf-1ea7336f6fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841505429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.1841505429
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.443613821
Short name T550
Test name
Test status
Simulation time 967027346 ps
CPU time 16.15 seconds
Started Jun 29 05:51:32 PM PDT 24
Finished Jun 29 05:51:49 PM PDT 24
Peak memory 226244 kb
Host smart-cdb4a955-5cd3-4297-93db-2cdb1f4cb346
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443613821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.443613821
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.2096663074
Short name T542
Test name
Test status
Simulation time 277181825 ps
CPU time 7.49 seconds
Started Jun 29 05:51:31 PM PDT 24
Finished Jun 29 05:51:39 PM PDT 24
Peak memory 218468 kb
Host smart-d8ea89ff-bc48-47af-a8e9-99bb85da4bdd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096663074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.2096663074
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.3362099999
Short name T806
Test name
Test status
Simulation time 1708100639 ps
CPU time 8.66 seconds
Started Jun 29 05:51:32 PM PDT 24
Finished Jun 29 05:51:41 PM PDT 24
Peak memory 218564 kb
Host smart-a869b1f7-442c-4e06-a497-e5b4283b1bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362099999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3362099999
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.4109081671
Short name T425
Test name
Test status
Simulation time 43646015 ps
CPU time 3.17 seconds
Started Jun 29 05:51:23 PM PDT 24
Finished Jun 29 05:51:27 PM PDT 24
Peak memory 217944 kb
Host smart-604ff221-678f-4003-94b3-bd31814e11e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109081671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.4109081671
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3828251194
Short name T835
Test name
Test status
Simulation time 290325281 ps
CPU time 26.82 seconds
Started Jun 29 05:51:26 PM PDT 24
Finished Jun 29 05:51:53 PM PDT 24
Peak memory 251028 kb
Host smart-bc9bbad0-fbbc-4f1b-ac28-7fed270b332d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828251194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3828251194
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.1945944155
Short name T358
Test name
Test status
Simulation time 218634871 ps
CPU time 7.49 seconds
Started Jun 29 05:51:23 PM PDT 24
Finished Jun 29 05:51:30 PM PDT 24
Peak memory 251132 kb
Host smart-7f722380-652d-4443-833a-e8945c1090d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945944155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.1945944155
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.2968004807
Short name T287
Test name
Test status
Simulation time 71415171785 ps
CPU time 97.71 seconds
Started Jun 29 05:51:31 PM PDT 24
Finished Jun 29 05:53:09 PM PDT 24
Peak memory 280084 kb
Host smart-93a5c3b5-7ebd-41e6-aa76-8521012e3b7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968004807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.2968004807
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.731490585
Short name T166
Test name
Test status
Simulation time 19943228 ps
CPU time 0.98 seconds
Started Jun 29 05:51:23 PM PDT 24
Finished Jun 29 05:51:25 PM PDT 24
Peak memory 212056 kb
Host smart-d624a144-6808-4df3-8f41-6238ca8caff6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731490585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ct
rl_volatile_unlock_smoke.731490585
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.4046744046
Short name T429
Test name
Test status
Simulation time 61122932 ps
CPU time 0.89 seconds
Started Jun 29 05:51:41 PM PDT 24
Finished Jun 29 05:51:42 PM PDT 24
Peak memory 209112 kb
Host smart-f72acfc7-b995-4476-a420-9aa8b40cbcbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046744046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.4046744046
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.1091561517
Short name T46
Test name
Test status
Simulation time 4482590094 ps
CPU time 8.55 seconds
Started Jun 29 05:51:32 PM PDT 24
Finished Jun 29 05:51:41 PM PDT 24
Peak memory 218424 kb
Host smart-c749d5b3-0e40-43bd-8efb-10bb73558ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091561517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.1091561517
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1176565149
Short name T826
Test name
Test status
Simulation time 1963352165 ps
CPU time 12.72 seconds
Started Jun 29 05:51:32 PM PDT 24
Finished Jun 29 05:51:45 PM PDT 24
Peak memory 217748 kb
Host smart-33ca4261-5905-4e59-9c4c-6ab302e0780f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176565149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.1176565149
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3657894801
Short name T601
Test name
Test status
Simulation time 126930175 ps
CPU time 2.48 seconds
Started Jun 29 05:51:31 PM PDT 24
Finished Jun 29 05:51:34 PM PDT 24
Peak memory 222424 kb
Host smart-393e366d-5386-44bf-9c99-67273f2bee8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657894801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3657894801
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.828913477
Short name T571
Test name
Test status
Simulation time 1639584248 ps
CPU time 11.48 seconds
Started Jun 29 05:51:31 PM PDT 24
Finished Jun 29 05:51:43 PM PDT 24
Peak memory 218400 kb
Host smart-36a7a40e-2e99-42fe-98a0-2796a4a97219
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828913477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.828913477
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2073943367
Short name T669
Test name
Test status
Simulation time 3307420892 ps
CPU time 12.36 seconds
Started Jun 29 05:51:31 PM PDT 24
Finished Jun 29 05:51:44 PM PDT 24
Peak memory 219160 kb
Host smart-8935be68-3b24-4b8b-81cb-efb0a9a9f104
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073943367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.2073943367
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2409039736
Short name T353
Test name
Test status
Simulation time 365587354 ps
CPU time 8.74 seconds
Started Jun 29 05:51:32 PM PDT 24
Finished Jun 29 05:51:41 PM PDT 24
Peak memory 218432 kb
Host smart-2a140d8a-030e-4a78-b19c-a9ad1dc46487
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409039736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2409039736
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.2840319686
Short name T485
Test name
Test status
Simulation time 734828184 ps
CPU time 9.48 seconds
Started Jun 29 05:51:31 PM PDT 24
Finished Jun 29 05:51:41 PM PDT 24
Peak memory 218500 kb
Host smart-75525ef3-0e63-41af-9ed2-fe8bb5ef94a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840319686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.2840319686
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.772620786
Short name T260
Test name
Test status
Simulation time 260602166 ps
CPU time 3.15 seconds
Started Jun 29 05:51:34 PM PDT 24
Finished Jun 29 05:51:38 PM PDT 24
Peak memory 215092 kb
Host smart-84731214-3677-4165-9ca7-1176b0665780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772620786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.772620786
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1304482020
Short name T812
Test name
Test status
Simulation time 582357537 ps
CPU time 14.28 seconds
Started Jun 29 05:51:35 PM PDT 24
Finished Jun 29 05:51:50 PM PDT 24
Peak memory 251220 kb
Host smart-4e1c2cf8-b83d-409d-a8ed-59a8bbce9736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304482020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1304482020
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.3738708601
Short name T526
Test name
Test status
Simulation time 73472408 ps
CPU time 4.04 seconds
Started Jun 29 05:51:30 PM PDT 24
Finished Jun 29 05:51:35 PM PDT 24
Peak memory 222628 kb
Host smart-fd81c410-1c03-49c6-bf7d-e3d3748fc97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738708601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3738708601
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.662374057
Short name T732
Test name
Test status
Simulation time 38222344632 ps
CPU time 227.89 seconds
Started Jun 29 05:51:35 PM PDT 24
Finished Jun 29 05:55:23 PM PDT 24
Peak memory 270420 kb
Host smart-ba8e114e-f7c2-4171-a96d-927153e68bf6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662374057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.662374057
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.4254487185
Short name T154
Test name
Test status
Simulation time 16375970532 ps
CPU time 586.18 seconds
Started Jun 29 05:51:40 PM PDT 24
Finished Jun 29 06:01:26 PM PDT 24
Peak memory 284024 kb
Host smart-da62a479-5356-499b-8252-69b9738355a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4254487185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.4254487185
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.821789381
Short name T686
Test name
Test status
Simulation time 20453739 ps
CPU time 0.77 seconds
Started Jun 29 05:51:32 PM PDT 24
Finished Jun 29 05:51:33 PM PDT 24
Peak memory 208328 kb
Host smart-9857a17e-0dd4-4fbc-b632-7410985842da
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821789381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ct
rl_volatile_unlock_smoke.821789381
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.2955171067
Short name T538
Test name
Test status
Simulation time 41854693 ps
CPU time 0.89 seconds
Started Jun 29 05:46:34 PM PDT 24
Finished Jun 29 05:46:35 PM PDT 24
Peak memory 208964 kb
Host smart-97e1b451-a993-49b3-a9bf-a93619c28379
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955171067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.2955171067
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1392044787
Short name T600
Test name
Test status
Simulation time 36525803 ps
CPU time 0.93 seconds
Started Jun 29 05:46:18 PM PDT 24
Finished Jun 29 05:46:20 PM PDT 24
Peak memory 209172 kb
Host smart-d9fa6f18-b8f2-4982-9356-b03f6b0a5c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392044787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1392044787
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.1802783415
Short name T562
Test name
Test status
Simulation time 289229709 ps
CPU time 8.66 seconds
Started Jun 29 05:46:16 PM PDT 24
Finished Jun 29 05:46:25 PM PDT 24
Peak memory 218380 kb
Host smart-43d23e90-962e-452c-977e-d51785733d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802783415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1802783415
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2496348034
Short name T740
Test name
Test status
Simulation time 1284254518 ps
CPU time 5.88 seconds
Started Jun 29 05:46:25 PM PDT 24
Finished Jun 29 05:46:31 PM PDT 24
Peak memory 217308 kb
Host smart-cacd4efc-7dc3-4592-a9aa-08ed4cd868a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496348034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2496348034
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1751329609
Short name T14
Test name
Test status
Simulation time 1273366411 ps
CPU time 26.92 seconds
Started Jun 29 05:46:26 PM PDT 24
Finished Jun 29 05:46:53 PM PDT 24
Peak memory 218472 kb
Host smart-ee540a96-0e86-488a-8428-c799cb2efc64
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751329609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1751329609
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.3298501631
Short name T67
Test name
Test status
Simulation time 12727870526 ps
CPU time 21.11 seconds
Started Jun 29 05:46:26 PM PDT 24
Finished Jun 29 05:46:47 PM PDT 24
Peak memory 218052 kb
Host smart-116f65c7-e197-46e1-8d42-219dbceafc85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298501631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.3
298501631
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.8726123
Short name T595
Test name
Test status
Simulation time 482592054 ps
CPU time 14.5 seconds
Started Jun 29 05:46:25 PM PDT 24
Finished Jun 29 05:46:40 PM PDT 24
Peak memory 218308 kb
Host smart-b7bf7317-c3b6-4f85-af10-9466078f3cbb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8726123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_pr
og_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_pr
og_failure.8726123
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2935386838
Short name T753
Test name
Test status
Simulation time 4281626346 ps
CPU time 15.84 seconds
Started Jun 29 05:46:26 PM PDT 24
Finished Jun 29 05:46:42 PM PDT 24
Peak memory 218088 kb
Host smart-a41383f9-aa68-4adb-8893-6ba5fbbf16a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935386838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.2935386838
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1078345470
Short name T854
Test name
Test status
Simulation time 1345888873 ps
CPU time 4.24 seconds
Started Jun 29 05:46:27 PM PDT 24
Finished Jun 29 05:46:31 PM PDT 24
Peak memory 217908 kb
Host smart-8dc044bf-6f14-4438-aaaf-b77c8cb2869c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078345470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1078345470
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3524783913
Short name T327
Test name
Test status
Simulation time 2838449492 ps
CPU time 44.64 seconds
Started Jun 29 05:46:24 PM PDT 24
Finished Jun 29 05:47:09 PM PDT 24
Peak memory 267576 kb
Host smart-401ccb7b-5579-4044-82f5-e3956bb0a8b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524783913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3524783913
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.982203445
Short name T410
Test name
Test status
Simulation time 3419978079 ps
CPU time 18.04 seconds
Started Jun 29 05:46:25 PM PDT 24
Finished Jun 29 05:46:44 PM PDT 24
Peak memory 251092 kb
Host smart-53e2f8e7-9533-4354-9287-bd85306a488f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982203445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_state_post_trans.982203445
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.898867319
Short name T446
Test name
Test status
Simulation time 104053158 ps
CPU time 3.73 seconds
Started Jun 29 05:46:16 PM PDT 24
Finished Jun 29 05:46:20 PM PDT 24
Peak memory 218372 kb
Host smart-2f86a063-1c70-41d4-94c4-22310efd28eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898867319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.898867319
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.2872333248
Short name T760
Test name
Test status
Simulation time 392452621 ps
CPU time 14.19 seconds
Started Jun 29 05:46:16 PM PDT 24
Finished Jun 29 05:46:31 PM PDT 24
Peak memory 214800 kb
Host smart-efdcaa8d-24da-4188-850a-645aa926679c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872333248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2872333248
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.3086833228
Short name T655
Test name
Test status
Simulation time 392436911 ps
CPU time 18.34 seconds
Started Jun 29 05:46:32 PM PDT 24
Finished Jun 29 05:46:51 PM PDT 24
Peak memory 219236 kb
Host smart-c9938609-b6e2-4d17-b6c6-74d9f3b0a5ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086833228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.3086833228
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.1140651283
Short name T855
Test name
Test status
Simulation time 1038410742 ps
CPU time 13.15 seconds
Started Jun 29 05:46:41 PM PDT 24
Finished Jun 29 05:46:54 PM PDT 24
Peak memory 218464 kb
Host smart-11bbfb85-f36d-4313-8724-ef5ace22be4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140651283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.1140651283
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.2147134441
Short name T765
Test name
Test status
Simulation time 349769353 ps
CPU time 13.83 seconds
Started Jun 29 05:46:33 PM PDT 24
Finished Jun 29 05:46:47 PM PDT 24
Peak memory 218432 kb
Host smart-9b28c029-d295-41ab-9b8a-aa37a0c59aea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147134441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.2
147134441
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.257499370
Short name T273
Test name
Test status
Simulation time 403062153 ps
CPU time 15.82 seconds
Started Jun 29 05:46:14 PM PDT 24
Finished Jun 29 05:46:30 PM PDT 24
Peak memory 218492 kb
Host smart-dfd4e5a1-60c0-4ac7-be69-b4c52dc60a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257499370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.257499370
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2278299912
Short name T639
Test name
Test status
Simulation time 362496756 ps
CPU time 2.73 seconds
Started Jun 29 05:46:17 PM PDT 24
Finished Jun 29 05:46:21 PM PDT 24
Peak memory 214464 kb
Host smart-ffcce8df-8a63-4a28-9223-0792af3db940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278299912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2278299912
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1933600852
Short name T716
Test name
Test status
Simulation time 1003100548 ps
CPU time 20.67 seconds
Started Jun 29 05:46:18 PM PDT 24
Finished Jun 29 05:46:39 PM PDT 24
Peak memory 244660 kb
Host smart-fb07a05c-ad8e-4fbe-9446-fc007d5f75d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933600852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1933600852
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.3963262406
Short name T711
Test name
Test status
Simulation time 73082942 ps
CPU time 6.37 seconds
Started Jun 29 05:46:16 PM PDT 24
Finished Jun 29 05:46:23 PM PDT 24
Peak memory 242948 kb
Host smart-fcb73cdc-4272-4af9-a461-93879457753f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963262406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.3963262406
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.3587391558
Short name T712
Test name
Test status
Simulation time 2282479153 ps
CPU time 47.11 seconds
Started Jun 29 05:46:39 PM PDT 24
Finished Jun 29 05:47:26 PM PDT 24
Peak memory 251180 kb
Host smart-792b0953-19cb-4c8e-a278-2a0b249c841c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587391558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.3587391558
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3724283857
Short name T691
Test name
Test status
Simulation time 35598610 ps
CPU time 1.02 seconds
Started Jun 29 05:46:17 PM PDT 24
Finished Jun 29 05:46:19 PM PDT 24
Peak memory 212196 kb
Host smart-6ed350e7-962f-4a5f-8bc7-32ce25e8c749
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724283857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.3724283857
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.2623920582
Short name T606
Test name
Test status
Simulation time 46665617 ps
CPU time 0.96 seconds
Started Jun 29 05:46:50 PM PDT 24
Finished Jun 29 05:46:51 PM PDT 24
Peak memory 209232 kb
Host smart-71c31e5d-00d6-451b-9332-1f50858b230d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623920582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2623920582
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.1216292856
Short name T433
Test name
Test status
Simulation time 122859066 ps
CPU time 0.82 seconds
Started Jun 29 05:46:39 PM PDT 24
Finished Jun 29 05:46:40 PM PDT 24
Peak memory 209080 kb
Host smart-f0569291-aa5b-4491-adf3-280f8e2c0529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216292856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.1216292856
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.3194694290
Short name T833
Test name
Test status
Simulation time 404862023 ps
CPU time 14.91 seconds
Started Jun 29 05:46:31 PM PDT 24
Finished Jun 29 05:46:47 PM PDT 24
Peak memory 226236 kb
Host smart-db36a98a-752e-43c0-a7f7-60fa2008d290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194694290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3194694290
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.4233500189
Short name T21
Test name
Test status
Simulation time 59143718 ps
CPU time 2.31 seconds
Started Jun 29 05:46:44 PM PDT 24
Finished Jun 29 05:46:47 PM PDT 24
Peak memory 217272 kb
Host smart-59582a51-bcb9-47c0-a4e3-c078d41504c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233500189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.4233500189
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.1786764524
Short name T59
Test name
Test status
Simulation time 14049528780 ps
CPU time 96.85 seconds
Started Jun 29 05:46:42 PM PDT 24
Finished Jun 29 05:48:20 PM PDT 24
Peak memory 219148 kb
Host smart-daa93ca5-d3ab-48ec-9b04-d82f19adeffd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786764524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.1786764524
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.3119469068
Short name T638
Test name
Test status
Simulation time 4223814142 ps
CPU time 8.5 seconds
Started Jun 29 05:46:42 PM PDT 24
Finished Jun 29 05:46:51 PM PDT 24
Peak memory 217952 kb
Host smart-8b1b0057-6167-4432-807e-a7a033c83c34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119469068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.3
119469068
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.1023991506
Short name T616
Test name
Test status
Simulation time 365842145 ps
CPU time 7.07 seconds
Started Jun 29 05:46:42 PM PDT 24
Finished Jun 29 05:46:50 PM PDT 24
Peak memory 218436 kb
Host smart-f4ea1267-e37b-4cc3-9e57-5ae4d91d4da4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023991506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.1023991506
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2657841053
Short name T76
Test name
Test status
Simulation time 2913903672 ps
CPU time 20.54 seconds
Started Jun 29 05:46:40 PM PDT 24
Finished Jun 29 05:47:01 PM PDT 24
Peak memory 217972 kb
Host smart-eeffc20b-adfe-43f9-a5e9-d63d1c89a279
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657841053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.2657841053
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.1091778420
Short name T748
Test name
Test status
Simulation time 260475778 ps
CPU time 7.6 seconds
Started Jun 29 05:46:33 PM PDT 24
Finished Jun 29 05:46:41 PM PDT 24
Peak memory 217856 kb
Host smart-7588fe4d-2259-400b-b79f-2446f20cb756
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091778420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
1091778420
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.1442014325
Short name T439
Test name
Test status
Simulation time 1366055846 ps
CPU time 41.01 seconds
Started Jun 29 05:46:42 PM PDT 24
Finished Jun 29 05:47:23 PM PDT 24
Peak memory 251120 kb
Host smart-8e1896be-e5c6-41d2-961b-71e0a24614cc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442014325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.1442014325
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3817968447
Short name T772
Test name
Test status
Simulation time 992254053 ps
CPU time 13.33 seconds
Started Jun 29 05:46:41 PM PDT 24
Finished Jun 29 05:46:55 PM PDT 24
Peak memory 251112 kb
Host smart-f67b1820-c34e-4b2d-9097-21f7a4e64b0e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817968447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.3817968447
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3537807208
Short name T98
Test name
Test status
Simulation time 207392242 ps
CPU time 2.81 seconds
Started Jun 29 05:46:33 PM PDT 24
Finished Jun 29 05:46:37 PM PDT 24
Peak memory 218428 kb
Host smart-24eadeef-4643-437e-98c1-3116243f69b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537807208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3537807208
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.719141915
Short name T361
Test name
Test status
Simulation time 274939213 ps
CPU time 10.11 seconds
Started Jun 29 05:46:32 PM PDT 24
Finished Jun 29 05:46:42 PM PDT 24
Peak memory 214916 kb
Host smart-22c239b7-dab4-4379-a318-33e169245c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719141915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.719141915
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.1207661724
Short name T481
Test name
Test status
Simulation time 321248661 ps
CPU time 12.52 seconds
Started Jun 29 05:46:41 PM PDT 24
Finished Jun 29 05:46:54 PM PDT 24
Peak memory 219096 kb
Host smart-2ccd85c4-8148-4a83-8da0-b20b26b9bccd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207661724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1207661724
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.509938531
Short name T326
Test name
Test status
Simulation time 511066433 ps
CPU time 12.59 seconds
Started Jun 29 05:46:44 PM PDT 24
Finished Jun 29 05:46:57 PM PDT 24
Peak memory 218460 kb
Host smart-29d8211c-ff7d-423f-b706-6dbc8c6ed5d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509938531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dig
est.509938531
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.1421450953
Short name T343
Test name
Test status
Simulation time 930849836 ps
CPU time 11.9 seconds
Started Jun 29 05:46:42 PM PDT 24
Finished Jun 29 05:46:55 PM PDT 24
Peak memory 218436 kb
Host smart-15fc97b7-1247-4956-9e87-45baf9130470
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421450953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.1
421450953
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.4188157414
Short name T201
Test name
Test status
Simulation time 206036805 ps
CPU time 9.09 seconds
Started Jun 29 05:46:34 PM PDT 24
Finished Jun 29 05:46:43 PM PDT 24
Peak memory 218492 kb
Host smart-f583c073-0e02-49aa-b591-42ce81c8ee7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188157414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.4188157414
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.4044902414
Short name T810
Test name
Test status
Simulation time 284350690 ps
CPU time 2.38 seconds
Started Jun 29 05:46:39 PM PDT 24
Finished Jun 29 05:46:42 PM PDT 24
Peak memory 217912 kb
Host smart-19cda659-06e0-42ce-92ab-f05d0c9060cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044902414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.4044902414
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.1136123075
Short name T673
Test name
Test status
Simulation time 853664067 ps
CPU time 25.82 seconds
Started Jun 29 05:46:33 PM PDT 24
Finished Jun 29 05:46:59 PM PDT 24
Peak memory 251132 kb
Host smart-048d9045-70f1-4d95-92ac-ef235d08b82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136123075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1136123075
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.1685406185
Short name T461
Test name
Test status
Simulation time 768355976 ps
CPU time 2.96 seconds
Started Jun 29 05:46:31 PM PDT 24
Finished Jun 29 05:46:35 PM PDT 24
Peak memory 222748 kb
Host smart-4f012a5e-b62e-451b-ba19-cd445bed26a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685406185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.1685406185
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.2601493218
Short name T821
Test name
Test status
Simulation time 9003896207 ps
CPU time 94.74 seconds
Started Jun 29 05:46:42 PM PDT 24
Finished Jun 29 05:48:18 PM PDT 24
Peak memory 277912 kb
Host smart-1f50e75f-747b-420b-ab0b-bcd05a311106
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601493218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.2601493218
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.2080179260
Short name T91
Test name
Test status
Simulation time 91048537536 ps
CPU time 593.29 seconds
Started Jun 29 05:46:42 PM PDT 24
Finished Jun 29 05:56:36 PM PDT 24
Peak memory 275908 kb
Host smart-ec2778bd-e135-4658-a496-6a9d5afc7628
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2080179260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.2080179260
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2188382383
Short name T556
Test name
Test status
Simulation time 68262174 ps
CPU time 0.86 seconds
Started Jun 29 05:46:32 PM PDT 24
Finished Jun 29 05:46:33 PM PDT 24
Peak memory 208484 kb
Host smart-d216e857-7f21-4a79-9802-ffe168c0bf06
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188382383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2188382383
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.2896112201
Short name T107
Test name
Test status
Simulation time 61175784 ps
CPU time 0.88 seconds
Started Jun 29 05:46:58 PM PDT 24
Finished Jun 29 05:47:00 PM PDT 24
Peak memory 209164 kb
Host smart-49f40efd-6bbc-4107-bcbe-379470fe2104
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896112201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.2896112201
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2484842021
Short name T72
Test name
Test status
Simulation time 21426824 ps
CPU time 0.89 seconds
Started Jun 29 05:46:54 PM PDT 24
Finished Jun 29 05:46:55 PM PDT 24
Peak memory 209096 kb
Host smart-b33a272c-c24a-4e8a-80c9-0651efcc3836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484842021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2484842021
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1337512192
Short name T462
Test name
Test status
Simulation time 338530054 ps
CPU time 14.96 seconds
Started Jun 29 05:46:50 PM PDT 24
Finished Jun 29 05:47:05 PM PDT 24
Peak memory 218436 kb
Host smart-8bb2068a-a217-438b-a059-1153f1801a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337512192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1337512192
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.1902690791
Short name T464
Test name
Test status
Simulation time 670149860 ps
CPU time 4.89 seconds
Started Jun 29 05:46:58 PM PDT 24
Finished Jun 29 05:47:03 PM PDT 24
Peak memory 217352 kb
Host smart-b59283e4-e34c-4e63-9096-2d807a9a3ab0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902690791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.1902690791
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.403171870
Short name T635
Test name
Test status
Simulation time 898012038 ps
CPU time 18.66 seconds
Started Jun 29 05:46:56 PM PDT 24
Finished Jun 29 05:47:15 PM PDT 24
Peak memory 218424 kb
Host smart-b33044f7-aa61-4987-8a9f-59cf56d581f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403171870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_err
ors.403171870
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.1932544030
Short name T650
Test name
Test status
Simulation time 313453921 ps
CPU time 8.5 seconds
Started Jun 29 05:46:58 PM PDT 24
Finished Jun 29 05:47:07 PM PDT 24
Peak memory 217748 kb
Host smart-e85d7d8e-16d6-4719-86b8-df3134190a2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932544030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.1
932544030
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.3285529735
Short name T281
Test name
Test status
Simulation time 1477231898 ps
CPU time 11.56 seconds
Started Jun 29 05:46:58 PM PDT 24
Finished Jun 29 05:47:10 PM PDT 24
Peak memory 218416 kb
Host smart-d7cb0915-07a5-4d60-a654-10a30cb1dd02
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285529735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.3285529735
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2224113339
Short name T360
Test name
Test status
Simulation time 12185959648 ps
CPU time 16.72 seconds
Started Jun 29 05:46:58 PM PDT 24
Finished Jun 29 05:47:15 PM PDT 24
Peak memory 217972 kb
Host smart-2c73efd9-1685-40e0-938d-620e902dd9c1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224113339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.2224113339
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.2727832841
Short name T20
Test name
Test status
Simulation time 2305308488 ps
CPU time 4.2 seconds
Started Jun 29 05:46:50 PM PDT 24
Finished Jun 29 05:46:55 PM PDT 24
Peak memory 217972 kb
Host smart-aaec219a-3fef-4edf-858b-c8620ce50483
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727832841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
2727832841
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2374891091
Short name T622
Test name
Test status
Simulation time 5084785746 ps
CPU time 28.25 seconds
Started Jun 29 05:46:55 PM PDT 24
Finished Jun 29 05:47:23 PM PDT 24
Peak memory 251188 kb
Host smart-b80d6422-ade9-455f-9edd-21f15bd3d57b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374891091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2374891091
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2396825907
Short name T610
Test name
Test status
Simulation time 6065083074 ps
CPU time 15.76 seconds
Started Jun 29 05:46:57 PM PDT 24
Finished Jun 29 05:47:13 PM PDT 24
Peak memory 250964 kb
Host smart-253938d8-90e9-43c8-ba71-45d22c656433
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396825907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2396825907
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.707677027
Short name T503
Test name
Test status
Simulation time 177458555 ps
CPU time 3 seconds
Started Jun 29 05:46:54 PM PDT 24
Finished Jun 29 05:46:57 PM PDT 24
Peak memory 218324 kb
Host smart-5f6a68ec-c28e-4757-a23f-3e68e74950b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707677027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.707677027
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3398441656
Short name T328
Test name
Test status
Simulation time 1223932310 ps
CPU time 8.61 seconds
Started Jun 29 05:46:50 PM PDT 24
Finished Jun 29 05:47:00 PM PDT 24
Peak memory 214776 kb
Host smart-b2e05e9f-6588-47f5-abee-fadcc188bd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398441656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3398441656
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.1216102593
Short name T758
Test name
Test status
Simulation time 4071176347 ps
CPU time 14.02 seconds
Started Jun 29 05:46:58 PM PDT 24
Finished Jun 29 05:47:13 PM PDT 24
Peak memory 226312 kb
Host smart-2e839218-f554-46ae-9ee5-5ce3eda918c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216102593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.1216102593
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.1899793479
Short name T738
Test name
Test status
Simulation time 1327177382 ps
CPU time 11.85 seconds
Started Jun 29 05:46:58 PM PDT 24
Finished Jun 29 05:47:11 PM PDT 24
Peak memory 218456 kb
Host smart-41e8b064-83da-478d-a19d-789d1b6e2f62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899793479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.1899793479
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1946710280
Short name T441
Test name
Test status
Simulation time 232705503 ps
CPU time 9.46 seconds
Started Jun 29 05:47:03 PM PDT 24
Finished Jun 29 05:47:12 PM PDT 24
Peak memory 218432 kb
Host smart-3ff5c466-fec3-4798-be82-50cf43f8606a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946710280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
946710280
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.1447376267
Short name T335
Test name
Test status
Simulation time 314886572 ps
CPU time 8.6 seconds
Started Jun 29 05:46:50 PM PDT 24
Finished Jun 29 05:46:59 PM PDT 24
Peak memory 218564 kb
Host smart-742c59bf-0988-4d48-8f44-0a25f3ade1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447376267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1447376267
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1332424635
Short name T71
Test name
Test status
Simulation time 57204698 ps
CPU time 3.22 seconds
Started Jun 29 05:46:49 PM PDT 24
Finished Jun 29 05:46:53 PM PDT 24
Peak memory 215016 kb
Host smart-6cfcb635-0c77-4823-bdbb-fbcceb01e14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332424635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1332424635
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3112013679
Short name T645
Test name
Test status
Simulation time 361230891 ps
CPU time 26.73 seconds
Started Jun 29 05:46:54 PM PDT 24
Finished Jun 29 05:47:21 PM PDT 24
Peak memory 246532 kb
Host smart-15151bc7-5ce5-4c9a-afa7-c68e0c08167a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112013679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3112013679
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1290556397
Short name T207
Test name
Test status
Simulation time 221572673 ps
CPU time 8.62 seconds
Started Jun 29 05:46:50 PM PDT 24
Finished Jun 29 05:46:59 PM PDT 24
Peak memory 251100 kb
Host smart-abe65e14-b80f-414c-b04c-f615fa1bf922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290556397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1290556397
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.4081983872
Short name T62
Test name
Test status
Simulation time 13567776762 ps
CPU time 143.39 seconds
Started Jun 29 05:46:58 PM PDT 24
Finished Jun 29 05:49:22 PM PDT 24
Peak memory 273724 kb
Host smart-c416f184-ae30-4090-a35d-b6c9c1fcfb53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081983872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.4081983872
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.1388682948
Short name T60
Test name
Test status
Simulation time 136438403486 ps
CPU time 1573.99 seconds
Started Jun 29 05:47:03 PM PDT 24
Finished Jun 29 06:13:17 PM PDT 24
Peak memory 333100 kb
Host smart-d0637552-8192-4651-ae18-fed48a7ce38f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1388682948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.1388682948
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3346752403
Short name T861
Test name
Test status
Simulation time 12749086 ps
CPU time 1.03 seconds
Started Jun 29 05:46:52 PM PDT 24
Finished Jun 29 05:46:53 PM PDT 24
Peak memory 212040 kb
Host smart-aef8e07b-3008-4034-be44-3ef0f713ae7f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346752403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.3346752403
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.53485678
Short name T294
Test name
Test status
Simulation time 29920583 ps
CPU time 1.11 seconds
Started Jun 29 05:47:16 PM PDT 24
Finished Jun 29 05:47:17 PM PDT 24
Peak memory 209148 kb
Host smart-649bf089-3d9f-4aeb-8a7e-2d1a4da8ba45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53485678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.53485678
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.3156042860
Short name T330
Test name
Test status
Simulation time 1992746482 ps
CPU time 23.3 seconds
Started Jun 29 05:47:02 PM PDT 24
Finished Jun 29 05:47:26 PM PDT 24
Peak memory 218432 kb
Host smart-ed64a75f-3f8e-4f8d-bd46-7df0ae5faf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156042860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3156042860
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1822884428
Short name T818
Test name
Test status
Simulation time 778013916 ps
CPU time 5.6 seconds
Started Jun 29 05:47:07 PM PDT 24
Finished Jun 29 05:47:13 PM PDT 24
Peak memory 217948 kb
Host smart-97b6da3a-1578-4ff3-a6f8-2485d388ca0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822884428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1822884428
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.2209363239
Short name T393
Test name
Test status
Simulation time 7919738171 ps
CPU time 76.15 seconds
Started Jun 29 05:47:09 PM PDT 24
Finished Jun 29 05:48:26 PM PDT 24
Peak memory 219112 kb
Host smart-a919d978-4d09-4be7-8086-9b456a8bd189
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209363239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.2209363239
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.717453648
Short name T428
Test name
Test status
Simulation time 298708507 ps
CPU time 2.5 seconds
Started Jun 29 05:47:07 PM PDT 24
Finished Jun 29 05:47:10 PM PDT 24
Peak memory 217760 kb
Host smart-75a2bb90-6635-4d42-afaf-003465d5c6b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717453648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.717453648
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3316784484
Short name T819
Test name
Test status
Simulation time 563007330 ps
CPU time 9.51 seconds
Started Jun 29 05:47:08 PM PDT 24
Finished Jun 29 05:47:17 PM PDT 24
Peak memory 218348 kb
Host smart-403e5f0d-1911-4026-b0f2-c44c423fefc7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316784484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3316784484
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1585428501
Short name T333
Test name
Test status
Simulation time 1378103572 ps
CPU time 11.37 seconds
Started Jun 29 05:47:08 PM PDT 24
Finished Jun 29 05:47:19 PM PDT 24
Peak memory 217912 kb
Host smart-79140698-3ce1-4571-a970-66ab1dff3d1f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585428501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.1585428501
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.389645335
Short name T74
Test name
Test status
Simulation time 471566921 ps
CPU time 7.6 seconds
Started Jun 29 05:47:04 PM PDT 24
Finished Jun 29 05:47:12 PM PDT 24
Peak memory 217912 kb
Host smart-504b4943-0c12-4a84-ad04-481e09f4a529
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389645335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.389645335
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.1121475395
Short name T523
Test name
Test status
Simulation time 1751511445 ps
CPU time 40.45 seconds
Started Jun 29 05:47:05 PM PDT 24
Finished Jun 29 05:47:46 PM PDT 24
Peak memory 276964 kb
Host smart-7baefb6a-1894-4322-8ff3-b2f89a542fa5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121475395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.1121475395
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3633426438
Short name T563
Test name
Test status
Simulation time 2414779331 ps
CPU time 10.3 seconds
Started Jun 29 05:47:06 PM PDT 24
Finished Jun 29 05:47:17 PM PDT 24
Peak memory 226288 kb
Host smart-8286f311-4917-4f35-8d44-d63dac3dab9a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633426438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.3633426438
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.438382889
Short name T278
Test name
Test status
Simulation time 177217094 ps
CPU time 3.84 seconds
Started Jun 29 05:46:58 PM PDT 24
Finished Jun 29 05:47:03 PM PDT 24
Peak memory 222956 kb
Host smart-6b51b1c1-caf2-4f55-8ab2-ff68e7c6ca69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438382889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.438382889
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.511761248
Short name T543
Test name
Test status
Simulation time 595529131 ps
CPU time 12.48 seconds
Started Jun 29 05:46:57 PM PDT 24
Finished Jun 29 05:47:10 PM PDT 24
Peak memory 214968 kb
Host smart-1e40135f-92b7-4e2a-aa7b-eba036031d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511761248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.511761248
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3046229259
Short name T40
Test name
Test status
Simulation time 795784729 ps
CPU time 9.95 seconds
Started Jun 29 05:47:06 PM PDT 24
Finished Jun 29 05:47:17 PM PDT 24
Peak memory 226244 kb
Host smart-d295181d-54e9-4155-8415-37cea1e26107
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046229259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3046229259
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2706254039
Short name T210
Test name
Test status
Simulation time 1030842218 ps
CPU time 9.81 seconds
Started Jun 29 05:47:06 PM PDT 24
Finished Jun 29 05:47:16 PM PDT 24
Peak memory 218464 kb
Host smart-303ac69f-b44b-4fa8-bd9f-ccff18e81140
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706254039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2706254039
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.1394561987
Short name T551
Test name
Test status
Simulation time 355726876 ps
CPU time 8.33 seconds
Started Jun 29 05:47:06 PM PDT 24
Finished Jun 29 05:47:14 PM PDT 24
Peak memory 218436 kb
Host smart-ae59db54-1a1c-4e39-8d35-dbdb9f7a797e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394561987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.1
394561987
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.1409905513
Short name T587
Test name
Test status
Simulation time 447437782 ps
CPU time 9.5 seconds
Started Jun 29 05:46:57 PM PDT 24
Finished Jun 29 05:47:07 PM PDT 24
Peak memory 218492 kb
Host smart-7609b76d-f0b4-45e1-9a25-d68f064674d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409905513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.1409905513
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.1571247271
Short name T347
Test name
Test status
Simulation time 76659227 ps
CPU time 2.39 seconds
Started Jun 29 05:47:02 PM PDT 24
Finished Jun 29 05:47:05 PM PDT 24
Peak memory 217924 kb
Host smart-8e5348a3-85f5-4c1d-8306-f18554f3840e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571247271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.1571247271
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.134608723
Short name T520
Test name
Test status
Simulation time 216446864 ps
CPU time 30.94 seconds
Started Jun 29 05:46:58 PM PDT 24
Finished Jun 29 05:47:30 PM PDT 24
Peak memory 251216 kb
Host smart-c9742618-106c-48f2-8979-c373014107c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134608723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.134608723
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.966697216
Short name T455
Test name
Test status
Simulation time 88970607 ps
CPU time 7.59 seconds
Started Jun 29 05:46:57 PM PDT 24
Finished Jun 29 05:47:05 PM PDT 24
Peak memory 251136 kb
Host smart-e88c0e86-4f5a-4eac-af1d-e9476e635264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966697216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.966697216
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.1310422788
Short name T509
Test name
Test status
Simulation time 48315344691 ps
CPU time 435.73 seconds
Started Jun 29 05:47:08 PM PDT 24
Finished Jun 29 05:54:24 PM PDT 24
Peak memory 226232 kb
Host smart-33aedf55-2be1-4cc8-9e59-1d9f6cbbec02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310422788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.1310422788
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1202002862
Short name T605
Test name
Test status
Simulation time 26425396 ps
CPU time 0.88 seconds
Started Jun 29 05:46:57 PM PDT 24
Finished Jun 29 05:46:58 PM PDT 24
Peak memory 213100 kb
Host smart-daf2c674-cb68-465b-96df-16a337f6b2b1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202002862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.1202002862
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.2973839601
Short name T230
Test name
Test status
Simulation time 18740608 ps
CPU time 0.91 seconds
Started Jun 29 05:47:25 PM PDT 24
Finished Jun 29 05:47:26 PM PDT 24
Peak memory 209140 kb
Host smart-4bf8bfb6-d8e7-47e3-9cf1-fefe718ca089
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973839601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.2973839601
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.143801756
Short name T374
Test name
Test status
Simulation time 228916022 ps
CPU time 7.95 seconds
Started Jun 29 05:47:17 PM PDT 24
Finished Jun 29 05:47:25 PM PDT 24
Peak memory 218372 kb
Host smart-0b775296-2bf8-4adc-96b4-ecc9480c0e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143801756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.143801756
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3866413118
Short name T171
Test name
Test status
Simulation time 4831969296 ps
CPU time 18.86 seconds
Started Jun 29 05:47:22 PM PDT 24
Finished Jun 29 05:47:41 PM PDT 24
Peak memory 217972 kb
Host smart-ec2d30e7-2cd1-4d94-a152-aa81f3467803
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866413118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3866413118
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.312522001
Short name T238
Test name
Test status
Simulation time 3647562352 ps
CPU time 99.21 seconds
Started Jun 29 05:47:16 PM PDT 24
Finished Jun 29 05:48:55 PM PDT 24
Peak memory 226296 kb
Host smart-dfcf9f57-fa64-4f7c-bca1-af08c68ea10f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312522001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_err
ors.312522001
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2464687067
Short name T828
Test name
Test status
Simulation time 978642478 ps
CPU time 4.3 seconds
Started Jun 29 05:47:22 PM PDT 24
Finished Jun 29 05:47:27 PM PDT 24
Peak memory 217512 kb
Host smart-0401cdae-4a4d-41e1-9a0b-4ab3b0144fb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464687067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
464687067
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2535898727
Short name T382
Test name
Test status
Simulation time 478132915 ps
CPU time 4.6 seconds
Started Jun 29 05:47:14 PM PDT 24
Finished Jun 29 05:47:19 PM PDT 24
Peak memory 218416 kb
Host smart-983d3db2-64e4-4419-8e74-ac03b70358bc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535898727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2535898727
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2330114213
Short name T389
Test name
Test status
Simulation time 752733792 ps
CPU time 9.77 seconds
Started Jun 29 05:47:23 PM PDT 24
Finished Jun 29 05:47:33 PM PDT 24
Peak memory 217912 kb
Host smart-32f74d43-7f27-49ed-8dcf-7a27abff93bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330114213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.2330114213
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.4105821249
Short name T671
Test name
Test status
Simulation time 451706950 ps
CPU time 11.39 seconds
Started Jun 29 05:47:14 PM PDT 24
Finished Jun 29 05:47:26 PM PDT 24
Peak memory 217916 kb
Host smart-57dca761-f10b-4df6-a3d1-e5f18a503280
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105821249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
4105821249
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.2680236190
Short name T222
Test name
Test status
Simulation time 2145933694 ps
CPU time 48.98 seconds
Started Jun 29 05:47:16 PM PDT 24
Finished Jun 29 05:48:06 PM PDT 24
Peak memory 267508 kb
Host smart-f3567171-e1d1-4404-9b15-24e0dd0d85c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680236190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.2680236190
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.234595299
Short name T547
Test name
Test status
Simulation time 711252919 ps
CPU time 15.17 seconds
Started Jun 29 05:47:17 PM PDT 24
Finished Jun 29 05:47:32 PM PDT 24
Peak memory 251136 kb
Host smart-3fabb18b-baf2-49db-b195-deed5301d23d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234595299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_state_post_trans.234595299
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.390766898
Short name T766
Test name
Test status
Simulation time 81783861 ps
CPU time 1.82 seconds
Started Jun 29 05:47:16 PM PDT 24
Finished Jun 29 05:47:18 PM PDT 24
Peak memory 218360 kb
Host smart-6da50c4a-ae24-4311-bb76-a38bfec874ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390766898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.390766898
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.345547702
Short name T804
Test name
Test status
Simulation time 234856413 ps
CPU time 15.7 seconds
Started Jun 29 05:47:15 PM PDT 24
Finished Jun 29 05:47:31 PM PDT 24
Peak memory 214900 kb
Host smart-ec5873f2-a4b0-4e24-beed-34073871e2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345547702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.345547702
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1806080446
Short name T567
Test name
Test status
Simulation time 1263845287 ps
CPU time 15.84 seconds
Started Jun 29 05:47:23 PM PDT 24
Finished Jun 29 05:47:39 PM PDT 24
Peak memory 226240 kb
Host smart-5c61ca94-9a3f-4c69-8685-6d12396b1b89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806080446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1806080446
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2461875933
Short name T3
Test name
Test status
Simulation time 1253926412 ps
CPU time 14.52 seconds
Started Jun 29 05:47:22 PM PDT 24
Finished Jun 29 05:47:37 PM PDT 24
Peak memory 218456 kb
Host smart-dd05edbe-c37a-44af-a3be-eba092dce9d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461875933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2461875933
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1238191566
Short name T741
Test name
Test status
Simulation time 703090841 ps
CPU time 6.33 seconds
Started Jun 29 05:47:23 PM PDT 24
Finished Jun 29 05:47:30 PM PDT 24
Peak memory 218344 kb
Host smart-8290f4b6-37a0-47a1-b53d-2d2c362aabc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238191566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.1
238191566
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.2561769038
Short name T782
Test name
Test status
Simulation time 253940892 ps
CPU time 11.2 seconds
Started Jun 29 05:47:16 PM PDT 24
Finished Jun 29 05:47:28 PM PDT 24
Peak memory 218500 kb
Host smart-e1f56fad-db26-4120-83b9-c3a6b40b3d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561769038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2561769038
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.2767077556
Short name T643
Test name
Test status
Simulation time 219485425 ps
CPU time 3.88 seconds
Started Jun 29 05:47:16 PM PDT 24
Finished Jun 29 05:47:21 PM PDT 24
Peak memory 217920 kb
Host smart-6d102230-a0f2-47f8-be27-b504a3c47bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767077556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.2767077556
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.1215450766
Short name T108
Test name
Test status
Simulation time 591963209 ps
CPU time 29.9 seconds
Started Jun 29 05:47:17 PM PDT 24
Finished Jun 29 05:47:47 PM PDT 24
Peak memory 251124 kb
Host smart-8d97fede-7385-42bd-ad07-f78802ca540a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215450766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1215450766
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.4220002717
Short name T301
Test name
Test status
Simulation time 236307415 ps
CPU time 8.41 seconds
Started Jun 29 05:47:15 PM PDT 24
Finished Jun 29 05:47:24 PM PDT 24
Peak memory 251216 kb
Host smart-e2941884-7930-4177-87b5-8ebc833e4189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220002717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.4220002717
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.2102674564
Short name T699
Test name
Test status
Simulation time 10387459183 ps
CPU time 112.67 seconds
Started Jun 29 05:47:24 PM PDT 24
Finished Jun 29 05:49:17 PM PDT 24
Peak memory 332956 kb
Host smart-1793bf64-8c57-4294-b4d8-858d2acd88aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102674564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.2102674564
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3480511325
Short name T463
Test name
Test status
Simulation time 49142001 ps
CPU time 0.89 seconds
Started Jun 29 05:47:15 PM PDT 24
Finished Jun 29 05:47:16 PM PDT 24
Peak memory 217920 kb
Host smart-922fbd58-a14f-46e1-a8bc-740ffec841ac
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480511325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.3480511325
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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