Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

85690048

1

T1

1312

T2

25517

T3

153670

auto[1]

1278545

1

T3

197

T4

792

T9

396

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

85705404

1

T1

1312

T2

25517

T3

152979

auto[1]

1263189

1

T3

888

T4

1089

T9

198

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6407827	1			T1	117		T2	6189		T3	9501
auto[IdleSt]	19856654	1			T1	72		T2	5046		T3	56426
auto[ClkMuxSt]	31912	1			T1	1		T2	60		T3	87
auto[CntIncrSt]	31623	1			T1	1		T2	60		T3	87
auto[CntProgSt]	1368928	1			T1	20		T2	2392		T3	362
auto[TransCheckSt]	24840	1			T1	1		T2	60		T3	70
auto[TokenHashSt]	31194496	1			T1	20		T2	1253		T3	13197
auto[FlashRmaSt]	25511	1			T3	93		T4	88		T9	8
auto[TokenCheck0St]	11415	1			T3	33		T4	43		T9	8
auto[TokenCheck1St]	8439	1			T3	24		T4	33		T9	8
auto[TransProgSt]	393162	1			T3	102		T4	491		T9	1007
auto[PostTransSt]	11367443	1			T1	1080		T2	10457		T3	43750
auto[ScrapSt]	120540	1			T3	668		T21	7986		T32	6
auto[EscalateSt]	5965935	1			T3	12124		T4	12002		T9	1567
auto[InvalidSt]	10158220	1			T3	17343		T9	804		T12	589

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1648	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10158220	1			T3	17343		T9	804		T12	589
EscalateSt	5965935	1			T3	12124		T4	12002		T9	1567
ScrapSt	120540	1			T3	668		T21	7986		T32	6
PostTransSt	11367443	1			T1	1080		T2	10457		T3	43750
TransProgSt	393162	1			T3	102		T4	491		T9	1007
TokenCheck1St	8439	1			T3	24		T4	33		T9	8
TokenCheck0St	11415	1			T3	33		T4	43		T9	8
FlashRmaSt	25511	1			T3	93		T4	88		T9	8
TokenHashSt	31194496	1			T1	20		T2	1253		T3	13197
TransCheckSt	24840	1			T1	1		T2	60		T3	70
CntProgSt	1368928	1			T1	20		T2	2392		T3	362
CntIncrSt	31623	1			T1	1		T2	60		T3	87
ClkMuxSt	31912	1			T1	1		T2	60		T3	87
IdleSt	19856654	1			T1	72		T2	5046		T3	56426
ResetSt	6407827	1			T1	117		T2	6189		T3	9501
arcs[ResetSt=>IdleSt]	48068	1			T1	1		T2	61		T3	98
arcs[IdleSt=>ScrapSt]	253	1			T3	1		T21	2		T32	2
arcs[IdleSt=>ClkMuxSt]	31693	1			T1	1		T2	60		T3	87
arcs[ClkMuxSt=>CntIncrSt]	31623	1			T1	1		T2	60		T3	87
arcs[CntIncrSt=>PostTransSt]	1494	1			T3	10		T4	22		T10	13
arcs[CntIncrSt=>CntProgSt]	30060	1			T1	1		T2	60		T3	77
arcs[CntProgSt=>PostTransSt]	4094	1			T3	7		T4	19		T10	11
arcs[CntProgSt=>TransCheckSt]	24840	1			T1	1		T2	60		T3	70
arcs[TransCheckSt=>PostTransSt]	3253	1			T3	9		T4	15		T10	11
arcs[TransCheckSt=>TokenHashSt]	21451	1			T1	1		T2	60		T3	61
arcs[TokenHashSt=>PostTransSt]	9274	1			T1	1		T2	60		T3	28
arcs[TokenHashSt=>FlashRmaSt]	11516	1			T3	33		T4	43		T9	8
arcs[FlashRmaSt=>TokenCheck0St]	11415	1			T3	33		T4	43		T9	8
arcs[TokenCheck0St=>PostTransSt]	2943	1			T3	9		T4	10		T10	9
arcs[TokenCheck0St=>TokenCheck1St]	8439	1			T3	24		T4	33		T9	8
arcs[TokenCheck1St=>PostTransSt]	655	1			T4	1		T10	1		T11	17
arcs[TransProgSt=>PostTransSt]	6938	1			T3	24		T4	32		T9	8
arcs[IdleSt=>EscalateSt]	187	1			T43	13		T45	4		T46	7
arcs[ClkMuxSt=>EscalateSt]	70	1			T32	1		T16	2		T43	1
arcs[CntIncrSt=>EscalateSt]	69	1			T32	4		T16	3		T43	1
arcs[CntProgSt=>EscalateSt]	1126	1			T32	40		T16	41		T43	5
arcs[TransCheckSt=>EscalateSt]	136	1			T43	10		T45	3		T46	1
arcs[TokenHashSt=>EscalateSt]	661	1			T32	15		T16	7		T43	13
arcs[FlashRmaSt=>EscalateSt]	101	1			T32	4		T43	7		T44	1
arcs[TokenCheck0St=>EscalateSt]	33	1			T32	1		T16	1		T43	1
arcs[TokenCheck1St=>EscalateSt]	143	1			T32	5		T16	2		T43	5
arcs[TransProgSt=>EscalateSt]	703	1			T32	20		T16	21		T43	4
arcs[PostTransSt=>EscalateSt]	4342	1			T3	7		T4	19		T10	11
arcs[InvalidSt=>EscalateSt]	12248	1			T3	4		T9	6		T12	8

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6407652	1			T1	117		T2	6189		T3	9501
auto[0]	auto[IdleSt]	19856536	1			T1	72		T2	5046		T3	56426
auto[0]	auto[ClkMuxSt]	31859	1			T1	1		T2	60		T3	87
auto[0]	auto[CntIncrSt]	31580	1			T1	1		T2	60		T3	87
auto[0]	auto[CntProgSt]	1368181	1			T1	20		T2	2392		T3	362
auto[0]	auto[TransCheckSt]	24753	1			T1	1		T2	60		T3	70
auto[0]	auto[TokenHashSt]	31194066	1			T1	20		T2	1253		T3	13197
auto[0]	auto[FlashRmaSt]	25446	1			T3	93		T4	88		T9	8
auto[0]	auto[TokenCheck0St]	11392	1			T3	33		T4	43		T9	8
auto[0]	auto[TokenCheck1St]	8347	1			T3	24		T4	33		T9	8
auto[0]	auto[TransProgSt]	392694	1			T3	102		T4	491		T9	1007
auto[0]	auto[PostTransSt]	11365185	1			T1	1080		T2	10457		T3	43749
auto[0]	auto[ScrapSt]	120493	1			T3	668		T21	7986		T32	4
auto[0]	auto[EscalateSt]	4698188	1			T3	11929		T4	11218		T9	1175
auto[0]	auto[InvalidSt]	10152028	1			T3	17342		T9	800		T12	585
auto[1]	auto[ResetSt]	175	1			T32	4		T16	3		T43	2
auto[1]	auto[IdleSt]	118	1			T43	7		T45	4		T46	4
auto[1]	auto[ClkMuxSt]	53	1			T32	1		T16	2		T43	1
auto[1]	auto[CntIncrSt]	43	1			T32	3		T16	1		T45	2
auto[1]	auto[CntProgSt]	747	1			T32	28		T16	25		T43	5
auto[1]	auto[TransCheckSt]	87	1			T43	8		T45	2		T46	1
auto[1]	auto[TokenHashSt]	430	1			T32	8		T16	6		T43	6
auto[1]	auto[FlashRmaSt]	65	1			T32	4		T43	3		T44	1
auto[1]	auto[TokenCheck0St]	23	1			T32	1		T44	1		T46	1
auto[1]	auto[TokenCheck1St]	92	1			T32	2		T16	1		T43	2
auto[1]	auto[TransProgSt]	468	1			T32	16		T16	16		T43	3
auto[1]	auto[PostTransSt]	2258	1			T3	1		T4	8		T10	4
auto[1]	auto[ScrapSt]	47	1			T32	2		T43	1		T45	1
auto[1]	auto[EscalateSt]	1267747	1			T3	195		T4	784		T9	392
auto[1]	auto[InvalidSt]	6192	1			T3	1		T9	4		T12	4

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6407645	1			T1	117		T2	6189		T3	9501
auto[0]	auto[IdleSt]	19856531	1			T1	72		T2	5046		T3	56426
auto[0]	auto[ClkMuxSt]	31865	1			T1	1		T2	60		T3	87
auto[0]	auto[CntIncrSt]	31574	1			T1	1		T2	60		T3	87
auto[0]	auto[CntProgSt]	1368194	1			T1	20		T2	2392		T3	362
auto[0]	auto[TransCheckSt]	24750	1			T1	1		T2	60		T3	70
auto[0]	auto[TokenHashSt]	31194048	1			T1	20		T2	1253		T3	13197
auto[0]	auto[FlashRmaSt]	25442	1			T3	93		T4	88		T9	8
auto[0]	auto[TokenCheck0St]	11394	1			T3	33		T4	43		T9	8
auto[0]	auto[TokenCheck1St]	8343	1			T3	24		T4	33		T9	8
auto[0]	auto[TransProgSt]	392682	1			T3	102		T4	491		T9	1007
auto[0]	auto[PostTransSt]	11365289	1			T1	1080		T2	10457		T3	43744
auto[0]	auto[ScrapSt]	120493	1			T3	668		T21	7986		T32	5
auto[0]	auto[EscalateSt]	4713342	1			T3	11245		T4	10924		T9	1371
auto[0]	auto[InvalidSt]	10152164	1			T3	17340		T9	802		T12	585
auto[1]	auto[ResetSt]	182	1			T32	3		T16	4		T43	5
auto[1]	auto[IdleSt]	123	1			T43	10		T45	1		T46	5
auto[1]	auto[ClkMuxSt]	47	1			T32	1		T16	1		T45	2
auto[1]	auto[CntIncrSt]	49	1			T32	3		T16	2		T43	1
auto[1]	auto[CntProgSt]	734	1			T32	25		T16	27		T43	3
auto[1]	auto[TransCheckSt]	90	1			T43	6		T45	2		T46	1
auto[1]	auto[TokenHashSt]	448	1			T32	11		T16	6		T43	10
auto[1]	auto[FlashRmaSt]	69	1			T32	3		T43	6		T44	1
auto[1]	auto[TokenCheck0St]	21	1			T16	1		T43	1		T46	1
auto[1]	auto[TokenCheck1St]	96	1			T32	3		T16	2		T43	5
auto[1]	auto[TransProgSt]	480	1			T32	10		T16	12		T43	4
auto[1]	auto[PostTransSt]	2154	1			T3	6		T4	11		T10	7
auto[1]	auto[ScrapSt]	47	1			T32	1		T16	1		T45	1
auto[1]	auto[EscalateSt]	1252593	1			T3	879		T4	1078		T9	196
auto[1]	auto[InvalidSt]	6056	1			T3	3		T9	2		T12	4