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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.87 97.92 95.84 93.38 97.62 98.52 98.51 96.29


Total test records in report: 994
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T814 /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.652772873 Jun 30 06:46:36 PM PDT 24 Jun 30 06:46:40 PM PDT 24 398711847 ps
T815 /workspace/coverage/default/38.lc_ctrl_stress_all.55009162 Jun 30 06:47:57 PM PDT 24 Jun 30 06:50:16 PM PDT 24 53006855902 ps
T816 /workspace/coverage/default/18.lc_ctrl_jtag_access.2569775849 Jun 30 06:47:04 PM PDT 24 Jun 30 06:47:17 PM PDT 24 406216654 ps
T205 /workspace/coverage/default/0.lc_ctrl_claim_transition_if.382907992 Jun 30 06:45:59 PM PDT 24 Jun 30 06:46:01 PM PDT 24 11223805 ps
T817 /workspace/coverage/default/7.lc_ctrl_jtag_priority.3317947860 Jun 30 06:46:23 PM PDT 24 Jun 30 06:46:35 PM PDT 24 4876136634 ps
T818 /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3226638425 Jun 30 06:46:51 PM PDT 24 Jun 30 06:46:53 PM PDT 24 32206382 ps
T819 /workspace/coverage/default/47.lc_ctrl_smoke.1357559915 Jun 30 06:48:16 PM PDT 24 Jun 30 06:48:20 PM PDT 24 119085933 ps
T820 /workspace/coverage/default/22.lc_ctrl_alert_test.4249190905 Jun 30 06:47:14 PM PDT 24 Jun 30 06:47:16 PM PDT 24 18295471 ps
T821 /workspace/coverage/default/6.lc_ctrl_stress_all.1092627556 Jun 30 06:46:17 PM PDT 24 Jun 30 06:52:44 PM PDT 24 12721740841 ps
T822 /workspace/coverage/default/16.lc_ctrl_jtag_access.2122450726 Jun 30 06:47:03 PM PDT 24 Jun 30 06:47:13 PM PDT 24 4177215871 ps
T823 /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1330570299 Jun 30 06:47:07 PM PDT 24 Jun 30 06:47:16 PM PDT 24 1818763642 ps
T824 /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.4096631278 Jun 30 06:46:47 PM PDT 24 Jun 30 06:46:48 PM PDT 24 17016756 ps
T825 /workspace/coverage/default/5.lc_ctrl_prog_failure.3841337971 Jun 30 06:46:12 PM PDT 24 Jun 30 06:46:16 PM PDT 24 142520984 ps
T826 /workspace/coverage/default/28.lc_ctrl_alert_test.3931228210 Jun 30 06:47:35 PM PDT 24 Jun 30 06:47:36 PM PDT 24 16600844 ps
T827 /workspace/coverage/default/10.lc_ctrl_smoke.3561119753 Jun 30 06:46:33 PM PDT 24 Jun 30 06:46:36 PM PDT 24 360254793 ps
T828 /workspace/coverage/default/30.lc_ctrl_jtag_access.118521065 Jun 30 06:47:39 PM PDT 24 Jun 30 06:48:02 PM PDT 24 951814504 ps
T829 /workspace/coverage/default/21.lc_ctrl_state_failure.60138600 Jun 30 06:47:09 PM PDT 24 Jun 30 06:47:35 PM PDT 24 239139074 ps
T830 /workspace/coverage/default/49.lc_ctrl_errors.2239969681 Jun 30 06:48:21 PM PDT 24 Jun 30 06:48:32 PM PDT 24 808547172 ps
T831 /workspace/coverage/default/10.lc_ctrl_jtag_access.3573798390 Jun 30 06:46:38 PM PDT 24 Jun 30 06:46:43 PM PDT 24 669992664 ps
T832 /workspace/coverage/default/15.lc_ctrl_sec_mubi.1144108623 Jun 30 06:47:07 PM PDT 24 Jun 30 06:47:23 PM PDT 24 1028463493 ps
T833 /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1406991804 Jun 30 06:48:27 PM PDT 24 Jun 30 06:48:40 PM PDT 24 393741606 ps
T834 /workspace/coverage/default/29.lc_ctrl_alert_test.3591063376 Jun 30 06:47:36 PM PDT 24 Jun 30 06:47:38 PM PDT 24 22555720 ps
T835 /workspace/coverage/default/29.lc_ctrl_smoke.2701120832 Jun 30 06:47:33 PM PDT 24 Jun 30 06:47:35 PM PDT 24 35575419 ps
T836 /workspace/coverage/default/35.lc_ctrl_sec_token_digest.4290343222 Jun 30 06:47:55 PM PDT 24 Jun 30 06:48:05 PM PDT 24 598727955 ps
T837 /workspace/coverage/default/15.lc_ctrl_jtag_errors.3496560207 Jun 30 06:46:54 PM PDT 24 Jun 30 06:47:23 PM PDT 24 5539867890 ps
T838 /workspace/coverage/default/27.lc_ctrl_state_post_trans.1116262945 Jun 30 06:47:28 PM PDT 24 Jun 30 06:47:38 PM PDT 24 87390683 ps
T839 /workspace/coverage/default/10.lc_ctrl_security_escalation.1449857074 Jun 30 06:46:34 PM PDT 24 Jun 30 06:46:44 PM PDT 24 884125840 ps
T840 /workspace/coverage/default/12.lc_ctrl_state_failure.2056783979 Jun 30 06:46:39 PM PDT 24 Jun 30 06:47:14 PM PDT 24 984786009 ps
T841 /workspace/coverage/default/7.lc_ctrl_sec_token_digest.353503064 Jun 30 06:46:22 PM PDT 24 Jun 30 06:46:30 PM PDT 24 443281973 ps
T842 /workspace/coverage/default/43.lc_ctrl_errors.4048502104 Jun 30 06:48:11 PM PDT 24 Jun 30 06:48:22 PM PDT 24 1130327961 ps
T843 /workspace/coverage/default/32.lc_ctrl_security_escalation.2936199545 Jun 30 06:47:48 PM PDT 24 Jun 30 06:47:59 PM PDT 24 3184205849 ps
T844 /workspace/coverage/default/22.lc_ctrl_sec_token_digest.296981505 Jun 30 06:47:16 PM PDT 24 Jun 30 06:47:34 PM PDT 24 777121173 ps
T845 /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1075124141 Jun 30 06:46:14 PM PDT 24 Jun 30 06:46:23 PM PDT 24 272313551 ps
T846 /workspace/coverage/default/47.lc_ctrl_stress_all.3662847575 Jun 30 06:48:14 PM PDT 24 Jun 30 06:49:13 PM PDT 24 4001509785 ps
T847 /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.2432001664 Jun 30 06:46:49 PM PDT 24 Jun 30 06:47:00 PM PDT 24 1478058164 ps
T848 /workspace/coverage/default/6.lc_ctrl_security_escalation.1409378293 Jun 30 06:46:18 PM PDT 24 Jun 30 06:46:31 PM PDT 24 512714794 ps
T849 /workspace/coverage/default/26.lc_ctrl_stress_all.4077268624 Jun 30 06:47:21 PM PDT 24 Jun 30 06:48:51 PM PDT 24 4300578941 ps
T850 /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3279730191 Jun 30 06:46:35 PM PDT 24 Jun 30 06:46:37 PM PDT 24 46084622 ps
T851 /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1736740392 Jun 30 06:46:42 PM PDT 24 Jun 30 06:47:00 PM PDT 24 385965760 ps
T852 /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2219272136 Jun 30 06:47:07 PM PDT 24 Jun 30 06:47:09 PM PDT 24 35400646 ps
T853 /workspace/coverage/default/16.lc_ctrl_sec_mubi.681965643 Jun 30 06:46:59 PM PDT 24 Jun 30 06:47:15 PM PDT 24 1527831296 ps
T854 /workspace/coverage/default/13.lc_ctrl_jtag_smoke.937082754 Jun 30 06:46:47 PM PDT 24 Jun 30 06:46:58 PM PDT 24 1314967520 ps
T855 /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2271838926 Jun 30 06:47:04 PM PDT 24 Jun 30 06:47:10 PM PDT 24 154677292 ps
T856 /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1424854306 Jun 30 06:46:02 PM PDT 24 Jun 30 06:46:30 PM PDT 24 710977608 ps
T857 /workspace/coverage/default/13.lc_ctrl_stress_all.3087787416 Jun 30 06:46:47 PM PDT 24 Jun 30 06:48:55 PM PDT 24 22816819990 ps
T858 /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2095859431 Jun 30 06:45:59 PM PDT 24 Jun 30 06:46:09 PM PDT 24 324357615 ps
T859 /workspace/coverage/default/9.lc_ctrl_smoke.307402328 Jun 30 06:46:34 PM PDT 24 Jun 30 06:46:40 PM PDT 24 314036323 ps
T860 /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2017080508 Jun 30 06:48:15 PM PDT 24 Jun 30 06:48:19 PM PDT 24 36800294 ps
T861 /workspace/coverage/default/28.lc_ctrl_prog_failure.397144034 Jun 30 06:47:27 PM PDT 24 Jun 30 06:47:32 PM PDT 24 184758081 ps
T862 /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2149300719 Jun 30 06:46:36 PM PDT 24 Jun 30 06:46:51 PM PDT 24 897416101 ps
T863 /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3224488379 Jun 30 06:47:57 PM PDT 24 Jun 30 06:48:10 PM PDT 24 376937520 ps
T864 /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2931538787 Jun 30 06:47:42 PM PDT 24 Jun 30 06:47:43 PM PDT 24 33966967 ps
T865 /workspace/coverage/default/27.lc_ctrl_jtag_access.2248632230 Jun 30 06:47:25 PM PDT 24 Jun 30 06:47:35 PM PDT 24 711694011 ps
T866 /workspace/coverage/default/8.lc_ctrl_sec_mubi.3113302022 Jun 30 06:46:33 PM PDT 24 Jun 30 06:46:46 PM PDT 24 1593905361 ps
T867 /workspace/coverage/default/33.lc_ctrl_security_escalation.3491124604 Jun 30 06:47:46 PM PDT 24 Jun 30 06:47:56 PM PDT 24 380962630 ps
T868 /workspace/coverage/default/4.lc_ctrl_smoke.3654818774 Jun 30 06:46:12 PM PDT 24 Jun 30 06:46:20 PM PDT 24 90663150 ps
T869 /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1444854365 Jun 30 06:47:04 PM PDT 24 Jun 30 06:47:12 PM PDT 24 1692755916 ps
T870 /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2691838701 Jun 30 06:47:09 PM PDT 24 Jun 30 06:47:21 PM PDT 24 848647735 ps
T871 /workspace/coverage/default/10.lc_ctrl_errors.521799472 Jun 30 06:46:33 PM PDT 24 Jun 30 06:46:46 PM PDT 24 345663779 ps
T113 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1528322830 Jun 30 06:41:28 PM PDT 24 Jun 30 06:41:39 PM PDT 24 355186376 ps
T114 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3647476363 Jun 30 06:41:41 PM PDT 24 Jun 30 06:41:43 PM PDT 24 163895977 ps
T115 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.775367115 Jun 30 06:41:28 PM PDT 24 Jun 30 06:41:30 PM PDT 24 1393919060 ps
T102 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.28304621 Jun 30 06:41:54 PM PDT 24 Jun 30 06:41:58 PM PDT 24 462402706 ps
T108 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1194421102 Jun 30 06:41:43 PM PDT 24 Jun 30 06:41:44 PM PDT 24 28380345 ps
T103 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.4099084364 Jun 30 06:42:11 PM PDT 24 Jun 30 06:42:14 PM PDT 24 99832065 ps
T109 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1621459030 Jun 30 06:41:49 PM PDT 24 Jun 30 06:41:51 PM PDT 24 235546520 ps
T132 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2542580446 Jun 30 06:41:41 PM PDT 24 Jun 30 06:41:42 PM PDT 24 41533184 ps
T872 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2398741411 Jun 30 06:41:29 PM PDT 24 Jun 30 06:41:32 PM PDT 24 312915385 ps
T110 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.866730645 Jun 30 06:41:34 PM PDT 24 Jun 30 06:41:36 PM PDT 24 38463877 ps
T147 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.969736941 Jun 30 06:41:28 PM PDT 24 Jun 30 06:41:30 PM PDT 24 80955353 ps
T104 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2629817140 Jun 30 06:41:47 PM PDT 24 Jun 30 06:41:50 PM PDT 24 220913647 ps
T156 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.878076216 Jun 30 06:41:54 PM PDT 24 Jun 30 06:41:55 PM PDT 24 43143714 ps
T192 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2901621459 Jun 30 06:41:53 PM PDT 24 Jun 30 06:41:55 PM PDT 24 24512680 ps
T148 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.134726129 Jun 30 06:41:28 PM PDT 24 Jun 30 06:41:29 PM PDT 24 40452333 ps
T873 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3192496482 Jun 30 06:41:33 PM PDT 24 Jun 30 06:41:36 PM PDT 24 64342992 ps
T107 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2335114471 Jun 30 06:42:11 PM PDT 24 Jun 30 06:42:14 PM PDT 24 587563786 ps
T157 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2477921627 Jun 30 06:42:05 PM PDT 24 Jun 30 06:42:07 PM PDT 24 39384672 ps
T181 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3383584576 Jun 30 06:41:42 PM PDT 24 Jun 30 06:41:44 PM PDT 24 32873541 ps
T874 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3050787366 Jun 30 06:41:20 PM PDT 24 Jun 30 06:41:22 PM PDT 24 20940072 ps
T875 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1268092028 Jun 30 06:42:01 PM PDT 24 Jun 30 06:42:03 PM PDT 24 163201343 ps
T126 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1183507615 Jun 30 06:41:48 PM PDT 24 Jun 30 06:41:50 PM PDT 24 26993199 ps
T158 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.866756404 Jun 30 06:41:47 PM PDT 24 Jun 30 06:41:49 PM PDT 24 152596132 ps
T193 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1377976004 Jun 30 06:42:05 PM PDT 24 Jun 30 06:42:07 PM PDT 24 22424802 ps
T202 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1499392310 Jun 30 06:41:33 PM PDT 24 Jun 30 06:42:17 PM PDT 24 11721032483 ps
T876 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2060897388 Jun 30 06:41:22 PM PDT 24 Jun 30 06:41:24 PM PDT 24 64643237 ps
T111 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3390588878 Jun 30 06:41:43 PM PDT 24 Jun 30 06:41:45 PM PDT 24 155807044 ps
T877 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.826294934 Jun 30 06:41:41 PM PDT 24 Jun 30 06:41:43 PM PDT 24 40403542 ps
T878 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2328168365 Jun 30 06:41:40 PM PDT 24 Jun 30 06:41:43 PM PDT 24 67551962 ps
T149 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3983227686 Jun 30 06:42:05 PM PDT 24 Jun 30 06:42:06 PM PDT 24 55623500 ps
T105 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1069867241 Jun 30 06:42:06 PM PDT 24 Jun 30 06:42:09 PM PDT 24 135675074 ps
T119 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.975589608 Jun 30 06:41:44 PM PDT 24 Jun 30 06:41:47 PM PDT 24 375944326 ps
T194 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3455241572 Jun 30 06:41:47 PM PDT 24 Jun 30 06:41:48 PM PDT 24 23666726 ps
T182 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3848561153 Jun 30 06:42:08 PM PDT 24 Jun 30 06:42:09 PM PDT 24 12992122 ps
T150 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.775815784 Jun 30 06:42:07 PM PDT 24 Jun 30 06:42:09 PM PDT 24 27897815 ps
T120 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.4013755735 Jun 30 06:42:07 PM PDT 24 Jun 30 06:42:09 PM PDT 24 48906031 ps
T151 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2969341164 Jun 30 06:41:48 PM PDT 24 Jun 30 06:41:50 PM PDT 24 26396791 ps
T879 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2255319349 Jun 30 06:42:13 PM PDT 24 Jun 30 06:42:14 PM PDT 24 15583440 ps
T880 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2174656828 Jun 30 06:41:23 PM PDT 24 Jun 30 06:41:26 PM PDT 24 410908455 ps
T881 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3522116680 Jun 30 06:42:13 PM PDT 24 Jun 30 06:42:15 PM PDT 24 16498956 ps
T195 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1675648550 Jun 30 06:41:30 PM PDT 24 Jun 30 06:41:31 PM PDT 24 37700417 ps
T106 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2390918121 Jun 30 06:41:43 PM PDT 24 Jun 30 06:41:47 PM PDT 24 84577525 ps
T882 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3740368466 Jun 30 06:41:43 PM PDT 24 Jun 30 06:41:45 PM PDT 24 36444773 ps
T883 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.102564176 Jun 30 06:41:41 PM PDT 24 Jun 30 06:41:43 PM PDT 24 71155840 ps
T884 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4251650471 Jun 30 06:41:44 PM PDT 24 Jun 30 06:41:47 PM PDT 24 1212992594 ps
T124 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.4032778439 Jun 30 06:42:12 PM PDT 24 Jun 30 06:42:15 PM PDT 24 483533981 ps
T885 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.598423135 Jun 30 06:42:05 PM PDT 24 Jun 30 06:42:07 PM PDT 24 31918158 ps
T886 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.493655842 Jun 30 06:42:08 PM PDT 24 Jun 30 06:42:10 PM PDT 24 84620404 ps
T133 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1078042396 Jun 30 06:41:46 PM PDT 24 Jun 30 06:41:48 PM PDT 24 52295352 ps
T183 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.835183346 Jun 30 06:41:57 PM PDT 24 Jun 30 06:41:58 PM PDT 24 39104845 ps
T887 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2124526120 Jun 30 06:41:21 PM PDT 24 Jun 30 06:42:06 PM PDT 24 2061069696 ps
T888 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1606822859 Jun 30 06:42:08 PM PDT 24 Jun 30 06:42:10 PM PDT 24 272364059 ps
T889 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.47855903 Jun 30 06:42:12 PM PDT 24 Jun 30 06:42:15 PM PDT 24 205478312 ps
T890 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2989738811 Jun 30 06:41:59 PM PDT 24 Jun 30 06:42:19 PM PDT 24 3181211808 ps
T891 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.940320314 Jun 30 06:41:49 PM PDT 24 Jun 30 06:41:52 PM PDT 24 65647460 ps
T892 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2295800535 Jun 30 06:42:12 PM PDT 24 Jun 30 06:42:13 PM PDT 24 21761959 ps
T893 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3035566496 Jun 30 06:41:21 PM PDT 24 Jun 30 06:41:23 PM PDT 24 375872609 ps
T196 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.263127703 Jun 30 06:41:49 PM PDT 24 Jun 30 06:41:52 PM PDT 24 108403772 ps
T894 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.498512825 Jun 30 06:41:34 PM PDT 24 Jun 30 06:41:36 PM PDT 24 30748294 ps
T117 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1890058555 Jun 30 06:41:22 PM PDT 24 Jun 30 06:41:29 PM PDT 24 592832250 ps
T197 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1166479680 Jun 30 06:41:38 PM PDT 24 Jun 30 06:41:40 PM PDT 24 191153016 ps
T198 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2393725358 Jun 30 06:41:47 PM PDT 24 Jun 30 06:41:49 PM PDT 24 43273819 ps
T112 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1479333426 Jun 30 06:42:08 PM PDT 24 Jun 30 06:42:10 PM PDT 24 47690245 ps
T129 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2268860531 Jun 30 06:41:38 PM PDT 24 Jun 30 06:41:40 PM PDT 24 68342100 ps
T125 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1895556338 Jun 30 06:42:01 PM PDT 24 Jun 30 06:42:06 PM PDT 24 109315078 ps
T895 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3268459339 Jun 30 06:42:14 PM PDT 24 Jun 30 06:42:15 PM PDT 24 38751159 ps
T896 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.116346736 Jun 30 06:41:55 PM PDT 24 Jun 30 06:41:58 PM PDT 24 155700214 ps
T199 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3903599492 Jun 30 06:41:27 PM PDT 24 Jun 30 06:41:28 PM PDT 24 13991484 ps
T897 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2283751040 Jun 30 06:41:30 PM PDT 24 Jun 30 06:41:31 PM PDT 24 15718168 ps
T898 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1332396669 Jun 30 06:42:13 PM PDT 24 Jun 30 06:42:14 PM PDT 24 83276147 ps
T899 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.623379821 Jun 30 06:41:26 PM PDT 24 Jun 30 06:41:32 PM PDT 24 377416787 ps
T900 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.184972751 Jun 30 06:42:05 PM PDT 24 Jun 30 06:42:08 PM PDT 24 128885980 ps
T184 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.672926915 Jun 30 06:41:27 PM PDT 24 Jun 30 06:41:29 PM PDT 24 49006821 ps
T901 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1117885161 Jun 30 06:41:20 PM PDT 24 Jun 30 06:41:28 PM PDT 24 304955725 ps
T902 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.329545332 Jun 30 06:42:10 PM PDT 24 Jun 30 06:42:12 PM PDT 24 31743068 ps
T134 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2495308617 Jun 30 06:42:01 PM PDT 24 Jun 30 06:42:08 PM PDT 24 1309260973 ps
T903 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2736335148 Jun 30 06:41:58 PM PDT 24 Jun 30 06:42:00 PM PDT 24 49908932 ps
T904 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2263774161 Jun 30 06:42:09 PM PDT 24 Jun 30 06:42:10 PM PDT 24 201032454 ps
T121 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2643211026 Jun 30 06:42:12 PM PDT 24 Jun 30 06:42:17 PM PDT 24 447035756 ps
T905 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.246371961 Jun 30 06:42:11 PM PDT 24 Jun 30 06:42:14 PM PDT 24 58317317 ps
T906 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2265773821 Jun 30 06:42:11 PM PDT 24 Jun 30 06:42:13 PM PDT 24 20705133 ps
T907 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2857880484 Jun 30 06:41:59 PM PDT 24 Jun 30 06:42:00 PM PDT 24 123458211 ps
T908 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1496041593 Jun 30 06:42:08 PM PDT 24 Jun 30 06:42:09 PM PDT 24 57767886 ps
T909 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1720903195 Jun 30 06:42:12 PM PDT 24 Jun 30 06:42:13 PM PDT 24 77217065 ps
T910 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.4044508157 Jun 30 06:41:55 PM PDT 24 Jun 30 06:42:07 PM PDT 24 552080564 ps
T911 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2594771475 Jun 30 06:41:42 PM PDT 24 Jun 30 06:41:54 PM PDT 24 1540541041 ps
T912 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1533329093 Jun 30 06:42:09 PM PDT 24 Jun 30 06:42:10 PM PDT 24 19585308 ps
T913 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1528523069 Jun 30 06:42:01 PM PDT 24 Jun 30 06:42:03 PM PDT 24 112320124 ps
T914 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.716538610 Jun 30 06:41:55 PM PDT 24 Jun 30 06:41:58 PM PDT 24 215874707 ps
T915 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2966946747 Jun 30 06:42:00 PM PDT 24 Jun 30 06:42:02 PM PDT 24 57144321 ps
T916 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3612842117 Jun 30 06:41:32 PM PDT 24 Jun 30 06:41:37 PM PDT 24 1524638729 ps
T917 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3390490448 Jun 30 06:41:34 PM PDT 24 Jun 30 06:41:39 PM PDT 24 269025899 ps
T918 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3831373977 Jun 30 06:41:48 PM PDT 24 Jun 30 06:42:05 PM PDT 24 2796450523 ps
T919 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1832117270 Jun 30 06:42:13 PM PDT 24 Jun 30 06:42:15 PM PDT 24 67789190 ps
T920 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3909663786 Jun 30 06:41:30 PM PDT 24 Jun 30 06:41:34 PM PDT 24 389556616 ps
T921 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1833181619 Jun 30 06:42:17 PM PDT 24 Jun 30 06:42:19 PM PDT 24 53276401 ps
T922 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1525472805 Jun 30 06:42:00 PM PDT 24 Jun 30 06:42:02 PM PDT 24 52656501 ps
T923 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.336266292 Jun 30 06:41:49 PM PDT 24 Jun 30 06:41:51 PM PDT 24 338126179 ps
T122 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2450973156 Jun 30 06:41:29 PM PDT 24 Jun 30 06:41:34 PM PDT 24 496541455 ps
T185 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1189652524 Jun 30 06:41:42 PM PDT 24 Jun 30 06:41:44 PM PDT 24 16605843 ps
T924 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1633040560 Jun 30 06:41:34 PM PDT 24 Jun 30 06:41:36 PM PDT 24 69342896 ps
T925 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1921073774 Jun 30 06:41:55 PM PDT 24 Jun 30 06:42:00 PM PDT 24 149349232 ps
T186 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3913948178 Jun 30 06:41:27 PM PDT 24 Jun 30 06:41:28 PM PDT 24 24793732 ps
T926 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.47574016 Jun 30 06:41:48 PM PDT 24 Jun 30 06:41:50 PM PDT 24 47656281 ps
T927 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1500974789 Jun 30 06:42:06 PM PDT 24 Jun 30 06:42:08 PM PDT 24 71728472 ps
T187 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3330343510 Jun 30 06:42:06 PM PDT 24 Jun 30 06:42:08 PM PDT 24 16538831 ps
T928 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1787068128 Jun 30 06:41:41 PM PDT 24 Jun 30 06:41:45 PM PDT 24 51673638 ps
T929 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3867069561 Jun 30 06:41:57 PM PDT 24 Jun 30 06:42:00 PM PDT 24 73783119 ps
T930 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2891507427 Jun 30 06:41:54 PM PDT 24 Jun 30 06:42:17 PM PDT 24 3846930486 ps
T128 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2391740059 Jun 30 06:42:02 PM PDT 24 Jun 30 06:42:04 PM PDT 24 57961154 ps
T931 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2289407122 Jun 30 06:41:44 PM PDT 24 Jun 30 06:41:47 PM PDT 24 88895638 ps
T932 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1489589333 Jun 30 06:41:53 PM PDT 24 Jun 30 06:41:55 PM PDT 24 131492553 ps
T127 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2808042050 Jun 30 06:42:06 PM PDT 24 Jun 30 06:42:09 PM PDT 24 63049333 ps
T933 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2713706909 Jun 30 06:42:07 PM PDT 24 Jun 30 06:42:09 PM PDT 24 27472968 ps
T934 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.834136794 Jun 30 06:41:58 PM PDT 24 Jun 30 06:42:00 PM PDT 24 36327778 ps
T935 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.227590695 Jun 30 06:41:38 PM PDT 24 Jun 30 06:41:40 PM PDT 24 25255971 ps
T188 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.68179333 Jun 30 06:41:41 PM PDT 24 Jun 30 06:41:43 PM PDT 24 38651951 ps
T936 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3670469396 Jun 30 06:41:34 PM PDT 24 Jun 30 06:41:38 PM PDT 24 1699936898 ps
T937 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3159207995 Jun 30 06:41:42 PM PDT 24 Jun 30 06:41:51 PM PDT 24 1390244051 ps
T938 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3272122683 Jun 30 06:41:34 PM PDT 24 Jun 30 06:41:37 PM PDT 24 490162030 ps
T939 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3216706835 Jun 30 06:41:33 PM PDT 24 Jun 30 06:41:35 PM PDT 24 168788763 ps
T118 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2610720970 Jun 30 06:42:07 PM PDT 24 Jun 30 06:42:12 PM PDT 24 245365639 ps
T940 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2886370473 Jun 30 06:42:12 PM PDT 24 Jun 30 06:42:14 PM PDT 24 21239209 ps
T941 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2812558464 Jun 30 06:41:37 PM PDT 24 Jun 30 06:41:38 PM PDT 24 71620326 ps
T942 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2724867769 Jun 30 06:41:29 PM PDT 24 Jun 30 06:41:30 PM PDT 24 34899002 ps
T943 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2311061106 Jun 30 06:42:05 PM PDT 24 Jun 30 06:42:07 PM PDT 24 16650746 ps
T123 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1013524700 Jun 30 06:42:12 PM PDT 24 Jun 30 06:42:15 PM PDT 24 125111725 ps
T944 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.184854671 Jun 30 06:42:09 PM PDT 24 Jun 30 06:42:11 PM PDT 24 127699441 ps
T945 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1446303381 Jun 30 06:42:05 PM PDT 24 Jun 30 06:42:07 PM PDT 24 103049326 ps
T946 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.59993186 Jun 30 06:41:54 PM PDT 24 Jun 30 06:42:03 PM PDT 24 894629491 ps
T947 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.4129300936 Jun 30 06:41:55 PM PDT 24 Jun 30 06:41:57 PM PDT 24 56731463 ps
T948 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.877113878 Jun 30 06:42:00 PM PDT 24 Jun 30 06:42:02 PM PDT 24 16663318 ps
T949 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.677697423 Jun 30 06:41:59 PM PDT 24 Jun 30 06:42:01 PM PDT 24 50144110 ps
T950 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2574036208 Jun 30 06:42:00 PM PDT 24 Jun 30 06:42:02 PM PDT 24 766717852 ps
T951 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1608464505 Jun 30 06:41:27 PM PDT 24 Jun 30 06:41:28 PM PDT 24 143225517 ps
T952 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.327559836 Jun 30 06:41:41 PM PDT 24 Jun 30 06:41:43 PM PDT 24 51362195 ps
T953 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3559082362 Jun 30 06:42:13 PM PDT 24 Jun 30 06:42:16 PM PDT 24 580371478 ps
T954 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3505921988 Jun 30 06:42:09 PM PDT 24 Jun 30 06:42:12 PM PDT 24 76671075 ps
T955 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1606937990 Jun 30 06:41:28 PM PDT 24 Jun 30 06:41:31 PM PDT 24 343086816 ps
T956 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2515344311 Jun 30 06:41:49 PM PDT 24 Jun 30 06:41:57 PM PDT 24 1359706905 ps
T957 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.698489799 Jun 30 06:41:22 PM PDT 24 Jun 30 06:41:24 PM PDT 24 154806306 ps
T958 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.819190361 Jun 30 06:41:28 PM PDT 24 Jun 30 06:41:29 PM PDT 24 110155357 ps
T959 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1938924072 Jun 30 06:42:01 PM PDT 24 Jun 30 06:42:05 PM PDT 24 274385125 ps
T960 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2338722172 Jun 30 06:41:59 PM PDT 24 Jun 30 06:42:01 PM PDT 24 53131058 ps
T961 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2242249712 Jun 30 06:42:11 PM PDT 24 Jun 30 06:42:13 PM PDT 24 48612167 ps
T962 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3323279012 Jun 30 06:41:43 PM PDT 24 Jun 30 06:41:45 PM PDT 24 140690178 ps
T963 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1134676130 Jun 30 06:41:42 PM PDT 24 Jun 30 06:41:45 PM PDT 24 207880667 ps
T191 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.581475427 Jun 30 06:42:07 PM PDT 24 Jun 30 06:42:08 PM PDT 24 11988719 ps
T964 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.400330884 Jun 30 06:42:10 PM PDT 24 Jun 30 06:42:13 PM PDT 24 176625951 ps
T965 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.10096494 Jun 30 06:41:34 PM PDT 24 Jun 30 06:41:36 PM PDT 24 112899912 ps
T966 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.798785695 Jun 30 06:42:07 PM PDT 24 Jun 30 06:42:09 PM PDT 24 86393241 ps
T967 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2139718623 Jun 30 06:41:55 PM PDT 24 Jun 30 06:41:57 PM PDT 24 50385071 ps
T968 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1528800099 Jun 30 06:41:40 PM PDT 24 Jun 30 06:41:47 PM PDT 24 1307242709 ps
T969 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1228103226 Jun 30 06:42:13 PM PDT 24 Jun 30 06:42:15 PM PDT 24 57970399 ps
T970 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.4121898131 Jun 30 06:41:49 PM PDT 24 Jun 30 06:41:52 PM PDT 24 39672115 ps
T971 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2332675169 Jun 30 06:42:00 PM PDT 24 Jun 30 06:42:07 PM PDT 24 226159703 ps
T972 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1935790540 Jun 30 06:41:41 PM PDT 24 Jun 30 06:41:42 PM PDT 24 16000118 ps
T189 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1203426927 Jun 30 06:41:34 PM PDT 24 Jun 30 06:41:36 PM PDT 24 92980710 ps
T973 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1975230802 Jun 30 06:42:00 PM PDT 24 Jun 30 06:42:17 PM PDT 24 693570397 ps
T974 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2953297578 Jun 30 06:41:47 PM PDT 24 Jun 30 06:41:53 PM PDT 24 1263201739 ps
T975 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.148980449 Jun 30 06:42:08 PM PDT 24 Jun 30 06:42:10 PM PDT 24 89752398 ps
T976 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.233924374 Jun 30 06:41:33 PM PDT 24 Jun 30 06:41:34 PM PDT 24 72252966 ps
T977 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.567255227 Jun 30 06:41:33 PM PDT 24 Jun 30 06:41:34 PM PDT 24 20235913 ps
T978 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3146516301 Jun 30 06:42:07 PM PDT 24 Jun 30 06:42:09 PM PDT 24 25358496 ps
T211 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2990026675 Jun 30 06:42:12 PM PDT 24 Jun 30 06:42:16 PM PDT 24 67121219 ps
T979 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3689522496 Jun 30 06:41:30 PM PDT 24 Jun 30 06:41:31 PM PDT 24 38044797 ps
T131 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3883596363 Jun 30 06:41:47 PM PDT 24 Jun 30 06:41:50 PM PDT 24 43576267 ps
T980 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1857135586 Jun 30 06:41:58 PM PDT 24 Jun 30 06:41:59 PM PDT 24 163750001 ps
T981 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.4228814985 Jun 30 06:42:06 PM PDT 24 Jun 30 06:42:07 PM PDT 24 19510477 ps
T982 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1899274148 Jun 30 06:41:43 PM PDT 24 Jun 30 06:41:45 PM PDT 24 141972179 ps
T983 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.123894610 Jun 30 06:41:59 PM PDT 24 Jun 30 06:42:01 PM PDT 24 37920157 ps
T984 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1841809100 Jun 30 06:41:43 PM PDT 24 Jun 30 06:41:44 PM PDT 24 114553618 ps
T985 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1957114792 Jun 30 06:41:48 PM PDT 24 Jun 30 06:41:51 PM PDT 24 279479319 ps
T986 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.4269206488 Jun 30 06:41:59 PM PDT 24 Jun 30 06:42:03 PM PDT 24 1822412329 ps
T987 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2522436003 Jun 30 06:41:59 PM PDT 24 Jun 30 06:42:02 PM PDT 24 99260105 ps
T116 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.986924565 Jun 30 06:41:20 PM PDT 24 Jun 30 06:41:23 PM PDT 24 1407397475 ps
T988 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.4262551939 Jun 30 06:41:41 PM PDT 24 Jun 30 06:41:43 PM PDT 24 34292273 ps
T190 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2077391414 Jun 30 06:41:49 PM PDT 24 Jun 30 06:41:51 PM PDT 24 25199759 ps
T989 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1190102187 Jun 30 06:42:00 PM PDT 24 Jun 30 06:42:03 PM PDT 24 277133440 ps
T990 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2776430267 Jun 30 06:41:41 PM PDT 24 Jun 30 06:41:43 PM PDT 24 47301504 ps
T130 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.879793144 Jun 30 06:42:06 PM PDT 24 Jun 30 06:42:10 PM PDT 24 405762674 ps
T991 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3302113160 Jun 30 06:41:33 PM PDT 24 Jun 30 06:41:45 PM PDT 24 1249006650 ps
T992 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2568289712 Jun 30 06:41:59 PM PDT 24 Jun 30 06:42:06 PM PDT 24 505079667 ps
T993 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3329662150 Jun 30 06:41:48 PM PDT 24 Jun 30 06:41:51 PM PDT 24 126361559 ps
T994 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.58658978 Jun 30 06:42:00 PM PDT 24 Jun 30 06:42:03 PM PDT 24 413616741 ps

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.4217982909
Short name T3
Test name
Test status
Simulation time 1586238040 ps
CPU time 27 seconds
Started Jun 30 06:46:40 PM PDT 24
Finished Jun 30 06:47:08 PM PDT 24
Peak memory 228416 kb
Host smart-71c5f4ca-fe39-402c-aab1-c144d0e4bbc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217982909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.4217982909
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.4281623028
Short name T45
Test name
Test status
Simulation time 823450909 ps
CPU time 9.04 seconds
Started Jun 30 06:47:23 PM PDT 24
Finished Jun 30 06:47:33 PM PDT 24
Peak memory 218436 kb
Host smart-60027353-022d-4b44-9456-bde555670ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281623028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.4281623028
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1339239649
Short name T13
Test name
Test status
Simulation time 482854675 ps
CPU time 17.18 seconds
Started Jun 30 06:46:13 PM PDT 24
Finished Jun 30 06:46:32 PM PDT 24
Peak memory 219076 kb
Host smart-172affc3-ceb5-48a0-b217-0be7b4e736fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339239649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1339239649
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.982060107
Short name T77
Test name
Test status
Simulation time 8561221718 ps
CPU time 150 seconds
Started Jun 30 06:48:16 PM PDT 24
Finished Jun 30 06:50:48 PM PDT 24
Peak memory 284000 kb
Host smart-d2ceba06-e87f-48e5-a617-6191762012cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=982060107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.982060107
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.28304621
Short name T102
Test name
Test status
Simulation time 462402706 ps
CPU time 3.38 seconds
Started Jun 30 06:41:54 PM PDT 24
Finished Jun 30 06:41:58 PM PDT 24
Peak memory 217600 kb
Host smart-f121ac6b-ddda-4ea0-978f-99631b3eb687
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28304621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.28304621
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.4171273083
Short name T51
Test name
Test status
Simulation time 42935237215 ps
CPU time 523.99 seconds
Started Jun 30 06:48:04 PM PDT 24
Finished Jun 30 06:56:50 PM PDT 24
Peak memory 497060 kb
Host smart-0c3dac22-de1b-485d-846b-8d09177fb985
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4171273083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.4171273083
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.2501247817
Short name T11
Test name
Test status
Simulation time 1899632392 ps
CPU time 9.97 seconds
Started Jun 30 06:48:01 PM PDT 24
Finished Jun 30 06:48:13 PM PDT 24
Peak memory 226248 kb
Host smart-9efd7a4d-fffd-4ae0-aaee-aa7bcd0f526f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501247817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
2501247817
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.4155596084
Short name T49
Test name
Test status
Simulation time 222798883 ps
CPU time 38.47 seconds
Started Jun 30 06:46:00 PM PDT 24
Finished Jun 30 06:46:39 PM PDT 24
Peak memory 270708 kb
Host smart-7815481f-7f9a-43d1-9b3f-ec14b21402a1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155596084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.4155596084
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.1925013099
Short name T5
Test name
Test status
Simulation time 1356641161 ps
CPU time 4.58 seconds
Started Jun 30 06:48:08 PM PDT 24
Finished Jun 30 06:48:15 PM PDT 24
Peak memory 217348 kb
Host smart-ec9cfd81-b9bd-4814-95ee-31a2ed405a5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925013099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.1925013099
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3893192648
Short name T16
Test name
Test status
Simulation time 662839002 ps
CPU time 10.07 seconds
Started Jun 30 06:48:10 PM PDT 24
Finished Jun 30 06:48:23 PM PDT 24
Peak memory 218544 kb
Host smart-9eaf4d1a-52f0-4f84-b0ff-397c3c897fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893192648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3893192648
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1194421102
Short name T108
Test name
Test status
Simulation time 28380345 ps
CPU time 0.95 seconds
Started Jun 30 06:41:43 PM PDT 24
Finished Jun 30 06:41:44 PM PDT 24
Peak memory 209392 kb
Host smart-20bf89e4-197b-4e6a-ba79-db3d7b329687
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194421102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.1194421102
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.2057380113
Short name T41
Test name
Test status
Simulation time 123982671341 ps
CPU time 829.41 seconds
Started Jun 30 06:46:48 PM PDT 24
Finished Jun 30 07:00:38 PM PDT 24
Peak memory 316820 kb
Host smart-23a3379a-4682-4054-b2fa-d730dafd5398
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2057380113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.2057380113
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.3078714690
Short name T80
Test name
Test status
Simulation time 44217643 ps
CPU time 0.82 seconds
Started Jun 30 06:48:10 PM PDT 24
Finished Jun 30 06:48:13 PM PDT 24
Peak memory 208896 kb
Host smart-2e3d4e75-0d50-4bf9-ad59-65fb348a2741
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078714690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.3078714690
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1895556338
Short name T125
Test name
Test status
Simulation time 109315078 ps
CPU time 4.43 seconds
Started Jun 30 06:42:01 PM PDT 24
Finished Jun 30 06:42:06 PM PDT 24
Peak memory 217572 kb
Host smart-ed32f1a3-1c3f-402e-9afd-ac126c8a7094
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895556338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.1895556338
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1621459030
Short name T109
Test name
Test status
Simulation time 235546520 ps
CPU time 1.25 seconds
Started Jun 30 06:41:49 PM PDT 24
Finished Jun 30 06:41:51 PM PDT 24
Peak memory 210676 kb
Host smart-f8ef56d5-6f90-4a96-ac95-42b81517fef4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621459030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.1621459030
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.2622959448
Short name T34
Test name
Test status
Simulation time 6602624047 ps
CPU time 197.56 seconds
Started Jun 30 06:47:16 PM PDT 24
Finished Jun 30 06:50:34 PM PDT 24
Peak memory 497004 kb
Host smart-28c1dc94-4992-48cd-b10b-5153bb354e87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622959448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.2622959448
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1034377877
Short name T4
Test name
Test status
Simulation time 6886770437 ps
CPU time 145.1 seconds
Started Jun 30 06:47:54 PM PDT 24
Finished Jun 30 06:50:20 PM PDT 24
Peak memory 228544 kb
Host smart-49c74cae-dc93-421a-bb90-fbdb8f2aefd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034377877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1034377877
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2450973156
Short name T122
Test name
Test status
Simulation time 496541455 ps
CPU time 4.62 seconds
Started Jun 30 06:41:29 PM PDT 24
Finished Jun 30 06:41:34 PM PDT 24
Peak memory 217532 kb
Host smart-31f3521c-a6f9-4123-8095-e5b7d084f783
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450973156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2450973156
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1286500440
Short name T17
Test name
Test status
Simulation time 501628445 ps
CPU time 12.76 seconds
Started Jun 30 06:45:58 PM PDT 24
Finished Jun 30 06:46:11 PM PDT 24
Peak memory 226172 kb
Host smart-66bc7c43-b9df-480c-ae4d-adb77de3d9a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286500440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1286500440
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3564338113
Short name T42
Test name
Test status
Simulation time 464852264 ps
CPU time 16.9 seconds
Started Jun 30 06:47:02 PM PDT 24
Finished Jun 30 06:47:19 PM PDT 24
Peak memory 218440 kb
Host smart-468cbc72-5edc-438d-9474-f9aea756e35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564338113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3564338113
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1479333426
Short name T112
Test name
Test status
Simulation time 47690245 ps
CPU time 1.75 seconds
Started Jun 30 06:42:08 PM PDT 24
Finished Jun 30 06:42:10 PM PDT 24
Peak memory 221880 kb
Host smart-b391ee53-6699-49cf-aa74-0087ff381b10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479333426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1479333426
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2391740059
Short name T128
Test name
Test status
Simulation time 57961154 ps
CPU time 1.94 seconds
Started Jun 30 06:42:02 PM PDT 24
Finished Jun 30 06:42:04 PM PDT 24
Peak memory 222012 kb
Host smart-1e82c790-4782-4952-b998-50b61743c8fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391740059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2391740059
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.986924565
Short name T116
Test name
Test status
Simulation time 1407397475 ps
CPU time 2.83 seconds
Started Jun 30 06:41:20 PM PDT 24
Finished Jun 30 06:41:23 PM PDT 24
Peak memory 222308 kb
Host smart-35ca3bdc-3700-4c5e-bae2-d13842736ad4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986924565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.986924565
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.196533117
Short name T56
Test name
Test status
Simulation time 75655681 ps
CPU time 3.74 seconds
Started Jun 30 06:46:34 PM PDT 24
Finished Jun 30 06:46:39 PM PDT 24
Peak memory 222512 kb
Host smart-40dd7a16-db6c-49a8-88b9-783b30117926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196533117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.196533117
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3903599492
Short name T199
Test name
Test status
Simulation time 13991484 ps
CPU time 0.93 seconds
Started Jun 30 06:41:27 PM PDT 24
Finished Jun 30 06:41:28 PM PDT 24
Peak memory 209300 kb
Host smart-3bbe403d-def1-4083-8c0b-35478a42a63f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903599492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3903599492
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.204502914
Short name T180
Test name
Test status
Simulation time 312777949 ps
CPU time 8.94 seconds
Started Jun 30 06:45:57 PM PDT 24
Finished Jun 30 06:46:06 PM PDT 24
Peak memory 217784 kb
Host smart-f76b55fc-931b-4d9d-9cb3-d6dc18360ade
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204502914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.204502914
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2998007079
Short name T22
Test name
Test status
Simulation time 15527548 ps
CPU time 0.91 seconds
Started Jun 30 06:47:27 PM PDT 24
Finished Jun 30 06:47:28 PM PDT 24
Peak memory 212116 kb
Host smart-5c744f8e-cd18-49ba-a204-c23c2c0be6da
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998007079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2998007079
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2872873378
Short name T32
Test name
Test status
Simulation time 984124629 ps
CPU time 15.28 seconds
Started Jun 30 06:47:14 PM PDT 24
Finished Jun 30 06:47:30 PM PDT 24
Peak memory 218472 kb
Host smart-b79efa88-8e8e-4f94-92b4-41d14fefd578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872873378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2872873378
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.879793144
Short name T130
Test name
Test status
Simulation time 405762674 ps
CPU time 2.98 seconds
Started Jun 30 06:42:06 PM PDT 24
Finished Jun 30 06:42:10 PM PDT 24
Peak memory 222152 kb
Host smart-13cb8cd0-db13-4b36-9c51-bd99b6617b46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879793144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_
err.879793144
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2643211026
Short name T121
Test name
Test status
Simulation time 447035756 ps
CPU time 4.41 seconds
Started Jun 30 06:42:12 PM PDT 24
Finished Jun 30 06:42:17 PM PDT 24
Peak memory 217536 kb
Host smart-856021b3-1db2-49a2-a637-302feb8549d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643211026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.2643211026
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2390918121
Short name T106
Test name
Test status
Simulation time 84577525 ps
CPU time 3.06 seconds
Started Jun 30 06:41:43 PM PDT 24
Finished Jun 30 06:41:47 PM PDT 24
Peak memory 221224 kb
Host smart-11d0e754-b5dd-479e-9141-88755f9de90b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390918121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.2390918121
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.382907992
Short name T205
Test name
Test status
Simulation time 11223805 ps
CPU time 0.82 seconds
Started Jun 30 06:45:59 PM PDT 24
Finished Jun 30 06:46:01 PM PDT 24
Peak memory 208916 kb
Host smart-f723efb4-33e0-4fdf-a12c-e4f15745ca53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382907992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.382907992
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.3659266588
Short name T210
Test name
Test status
Simulation time 12058755 ps
CPU time 1.01 seconds
Started Jun 30 06:46:01 PM PDT 24
Finished Jun 30 06:46:03 PM PDT 24
Peak memory 209160 kb
Host smart-75b34880-b2da-4882-b6ea-483e4030fea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659266588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.3659266588
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1712709249
Short name T207
Test name
Test status
Simulation time 14092052 ps
CPU time 0.99 seconds
Started Jun 30 06:46:10 PM PDT 24
Finished Jun 30 06:46:13 PM PDT 24
Peak memory 209220 kb
Host smart-60954589-bfb6-4495-ae4a-a29568d5ba9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712709249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1712709249
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.762623330
Short name T209
Test name
Test status
Simulation time 39168397 ps
CPU time 0.94 seconds
Started Jun 30 06:46:29 PM PDT 24
Finished Jun 30 06:46:30 PM PDT 24
Peak memory 209192 kb
Host smart-5ac426be-f72f-43b5-a900-428871db2897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762623330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.762623330
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3909663786
Short name T920
Test name
Test status
Simulation time 389556616 ps
CPU time 3.96 seconds
Started Jun 30 06:41:30 PM PDT 24
Finished Jun 30 06:41:34 PM PDT 24
Peak memory 217508 kb
Host smart-25426fc8-54cc-41af-8d81-8896233e91e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909663786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.3909663786
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2610720970
Short name T118
Test name
Test status
Simulation time 245365639 ps
CPU time 4.54 seconds
Started Jun 30 06:42:07 PM PDT 24
Finished Jun 30 06:42:12 PM PDT 24
Peak memory 217560 kb
Host smart-81eedae6-9372-4df3-8dec-de8c28a6166b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610720970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.2610720970
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.4032778439
Short name T124
Test name
Test status
Simulation time 483533981 ps
CPU time 3.13 seconds
Started Jun 30 06:42:12 PM PDT 24
Finished Jun 30 06:42:15 PM PDT 24
Peak memory 222272 kb
Host smart-05c0705b-001e-42fe-9e80-7c23650a7dc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032778439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.4032778439
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2268860531
Short name T129
Test name
Test status
Simulation time 68342100 ps
CPU time 2.08 seconds
Started Jun 30 06:41:38 PM PDT 24
Finished Jun 30 06:41:40 PM PDT 24
Peak memory 221768 kb
Host smart-e07a8697-266b-4fdc-a85a-f632f69a6d52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268860531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2268860531
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2532100839
Short name T213
Test name
Test status
Simulation time 133117302 ps
CPU time 2.03 seconds
Started Jun 30 06:47:16 PM PDT 24
Finished Jun 30 06:47:19 PM PDT 24
Peak memory 218432 kb
Host smart-298f2f31-dcfb-47ef-a3db-fb765046ee2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532100839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2532100839
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.819190361
Short name T958
Test name
Test status
Simulation time 110155357 ps
CPU time 0.99 seconds
Started Jun 30 06:41:28 PM PDT 24
Finished Jun 30 06:41:29 PM PDT 24
Peak memory 209296 kb
Host smart-d5517c67-98c5-4573-ad16-b2f1ac8b0698
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819190361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing
.819190361
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2724867769
Short name T942
Test name
Test status
Simulation time 34899002 ps
CPU time 1.38 seconds
Started Jun 30 06:41:29 PM PDT 24
Finished Jun 30 06:41:30 PM PDT 24
Peak memory 209228 kb
Host smart-f96b7d8f-855d-4592-82fc-4ca65f9b1e09
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724867769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.2724867769
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3913948178
Short name T186
Test name
Test status
Simulation time 24793732 ps
CPU time 1.01 seconds
Started Jun 30 06:41:27 PM PDT 24
Finished Jun 30 06:41:28 PM PDT 24
Peak memory 209852 kb
Host smart-441c2932-7512-4ec9-b350-0a8d7f58c219
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913948178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.3913948178
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.969736941
Short name T147
Test name
Test status
Simulation time 80955353 ps
CPU time 1.38 seconds
Started Jun 30 06:41:28 PM PDT 24
Finished Jun 30 06:41:30 PM PDT 24
Peak memory 220320 kb
Host smart-4b810e79-2b5f-47cf-b984-e5aa56a2b760
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969736941 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.969736941
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3050787366
Short name T874
Test name
Test status
Simulation time 20940072 ps
CPU time 0.96 seconds
Started Jun 30 06:41:20 PM PDT 24
Finished Jun 30 06:41:22 PM PDT 24
Peak memory 209160 kb
Host smart-8782005f-b062-4a2b-822a-740e5ac368b1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050787366 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3050787366
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1117885161
Short name T901
Test name
Test status
Simulation time 304955725 ps
CPU time 7.5 seconds
Started Jun 30 06:41:20 PM PDT 24
Finished Jun 30 06:41:28 PM PDT 24
Peak memory 208956 kb
Host smart-5f1887c4-6ece-48f5-ab98-f95ced070bda
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117885161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1117885161
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2124526120
Short name T887
Test name
Test status
Simulation time 2061069696 ps
CPU time 44.92 seconds
Started Jun 30 06:41:21 PM PDT 24
Finished Jun 30 06:42:06 PM PDT 24
Peak memory 217108 kb
Host smart-a9ec29e5-456c-4987-b9eb-17afa1aef003
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124526120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2124526120
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3035566496
Short name T893
Test name
Test status
Simulation time 375872609 ps
CPU time 1.85 seconds
Started Jun 30 06:41:21 PM PDT 24
Finished Jun 30 06:41:23 PM PDT 24
Peak memory 210840 kb
Host smart-ff610c6c-a9c5-481b-9860-6bb5f18cd06c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035566496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3035566496
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2174656828
Short name T880
Test name
Test status
Simulation time 410908455 ps
CPU time 2.41 seconds
Started Jun 30 06:41:23 PM PDT 24
Finished Jun 30 06:41:26 PM PDT 24
Peak memory 217636 kb
Host smart-2e79cfc2-3ef5-42e4-a912-2782147fc0cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217465
6828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2174656828
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2060897388
Short name T876
Test name
Test status
Simulation time 64643237 ps
CPU time 1.47 seconds
Started Jun 30 06:41:22 PM PDT 24
Finished Jun 30 06:41:24 PM PDT 24
Peak memory 209156 kb
Host smart-ed052f34-61f6-4c89-874d-c72624b9ba6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060897388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2060897388
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.698489799
Short name T957
Test name
Test status
Simulation time 154806306 ps
CPU time 1.38 seconds
Started Jun 30 06:41:22 PM PDT 24
Finished Jun 30 06:41:24 PM PDT 24
Peak memory 217540 kb
Host smart-079aad91-0ef4-4298-ab6e-46fb32c874f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698489799 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.698489799
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1675648550
Short name T195
Test name
Test status
Simulation time 37700417 ps
CPU time 1.07 seconds
Started Jun 30 06:41:30 PM PDT 24
Finished Jun 30 06:41:31 PM PDT 24
Peak memory 209364 kb
Host smart-7823ac5f-f94c-4e82-8a83-280629c1078a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675648550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.1675648550
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1890058555
Short name T117
Test name
Test status
Simulation time 592832250 ps
CPU time 5.94 seconds
Started Jun 30 06:41:22 PM PDT 24
Finished Jun 30 06:41:29 PM PDT 24
Peak memory 217456 kb
Host smart-c65135ad-b929-462a-8d4d-015b1bcf2498
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890058555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1890058555
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.672926915
Short name T184
Test name
Test status
Simulation time 49006821 ps
CPU time 1.3 seconds
Started Jun 30 06:41:27 PM PDT 24
Finished Jun 30 06:41:29 PM PDT 24
Peak memory 209372 kb
Host smart-729daa78-64a2-45de-8bb4-ca3199085656
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672926915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.672926915
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3689522496
Short name T979
Test name
Test status
Simulation time 38044797 ps
CPU time 1.25 seconds
Started Jun 30 06:41:30 PM PDT 24
Finished Jun 30 06:41:31 PM PDT 24
Peak memory 209244 kb
Host smart-4b106588-3b41-418a-83e5-373f92095b2a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689522496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3689522496
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2283751040
Short name T897
Test name
Test status
Simulation time 15718168 ps
CPU time 1.16 seconds
Started Jun 30 06:41:30 PM PDT 24
Finished Jun 30 06:41:31 PM PDT 24
Peak memory 209868 kb
Host smart-8a514656-03ca-437b-b524-37cb5a73b32f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283751040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.2283751040
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.498512825
Short name T894
Test name
Test status
Simulation time 30748294 ps
CPU time 1.33 seconds
Started Jun 30 06:41:34 PM PDT 24
Finished Jun 30 06:41:36 PM PDT 24
Peak memory 217820 kb
Host smart-640b1a99-df85-4690-ae38-c05daad38327
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498512825 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.498512825
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.134726129
Short name T148
Test name
Test status
Simulation time 40452333 ps
CPU time 0.88 seconds
Started Jun 30 06:41:28 PM PDT 24
Finished Jun 30 06:41:29 PM PDT 24
Peak memory 208944 kb
Host smart-0a306fd4-4dcc-4505-9ccd-620692ea3707
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134726129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.134726129
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2398741411
Short name T872
Test name
Test status
Simulation time 312915385 ps
CPU time 2.54 seconds
Started Jun 30 06:41:29 PM PDT 24
Finished Jun 30 06:41:32 PM PDT 24
Peak memory 209256 kb
Host smart-2ae43d7c-154c-4040-b99e-be61eda524c4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398741411 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2398741411
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.623379821
Short name T899
Test name
Test status
Simulation time 377416787 ps
CPU time 5.5 seconds
Started Jun 30 06:41:26 PM PDT 24
Finished Jun 30 06:41:32 PM PDT 24
Peak memory 209096 kb
Host smart-546a6824-37f8-4f6f-8cce-9a7314faa72a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623379821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.623379821
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1528322830
Short name T113
Test name
Test status
Simulation time 355186376 ps
CPU time 9.9 seconds
Started Jun 30 06:41:28 PM PDT 24
Finished Jun 30 06:41:39 PM PDT 24
Peak memory 209216 kb
Host smart-8f625ad4-e7bc-4281-94db-fbad884f47a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528322830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1528322830
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.775367115
Short name T115
Test name
Test status
Simulation time 1393919060 ps
CPU time 2.12 seconds
Started Jun 30 06:41:28 PM PDT 24
Finished Jun 30 06:41:30 PM PDT 24
Peak memory 210864 kb
Host smart-7a41a64f-05a9-426d-b11a-22163b4e0ae3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775367115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.775367115
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1606937990
Short name T955
Test name
Test status
Simulation time 343086816 ps
CPU time 2.04 seconds
Started Jun 30 06:41:28 PM PDT 24
Finished Jun 30 06:41:31 PM PDT 24
Peak memory 217732 kb
Host smart-44c2abab-9cad-44f5-b3d3-4ca7c245fefd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160693
7990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1606937990
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1608464505
Short name T951
Test name
Test status
Simulation time 143225517 ps
CPU time 1.08 seconds
Started Jun 30 06:41:27 PM PDT 24
Finished Jun 30 06:41:28 PM PDT 24
Peak memory 209256 kb
Host smart-a22c0eef-73da-4802-8bb4-fe86e9e8a0a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608464505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1608464505
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2812558464
Short name T941
Test name
Test status
Simulation time 71620326 ps
CPU time 0.97 seconds
Started Jun 30 06:41:37 PM PDT 24
Finished Jun 30 06:41:38 PM PDT 24
Peak memory 209392 kb
Host smart-929f3db3-b262-4f5b-8ea3-2bf107ba3117
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812558464 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.2812558464
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1166479680
Short name T197
Test name
Test status
Simulation time 191153016 ps
CPU time 1.41 seconds
Started Jun 30 06:41:38 PM PDT 24
Finished Jun 30 06:41:40 PM PDT 24
Peak memory 209364 kb
Host smart-f1b28783-a0cc-47f6-9172-fce2eb4e0bd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166479680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.1166479680
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1496041593
Short name T908
Test name
Test status
Simulation time 57767886 ps
CPU time 1.24 seconds
Started Jun 30 06:42:08 PM PDT 24
Finished Jun 30 06:42:09 PM PDT 24
Peak memory 217712 kb
Host smart-d3fafc32-19c0-4d7e-8746-13e7ca290c61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496041593 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1496041593
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3330343510
Short name T187
Test name
Test status
Simulation time 16538831 ps
CPU time 0.99 seconds
Started Jun 30 06:42:06 PM PDT 24
Finished Jun 30 06:42:08 PM PDT 24
Peak memory 209320 kb
Host smart-b0d908cb-8447-48bf-a58e-73e3b88411a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330343510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3330343510
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2311061106
Short name T943
Test name
Test status
Simulation time 16650746 ps
CPU time 1.05 seconds
Started Jun 30 06:42:05 PM PDT 24
Finished Jun 30 06:42:07 PM PDT 24
Peak memory 217532 kb
Host smart-3e48e41e-408a-467e-81f7-2c037d014dad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311061106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2311061106
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1606822859
Short name T888
Test name
Test status
Simulation time 272364059 ps
CPU time 2.03 seconds
Started Jun 30 06:42:08 PM PDT 24
Finished Jun 30 06:42:10 PM PDT 24
Peak memory 217624 kb
Host smart-48187f4d-8843-455b-ba0a-3697e901d3fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606822859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1606822859
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.775815784
Short name T150
Test name
Test status
Simulation time 27897815 ps
CPU time 1.28 seconds
Started Jun 30 06:42:07 PM PDT 24
Finished Jun 30 06:42:09 PM PDT 24
Peak memory 217672 kb
Host smart-8f151783-484b-4da0-8eb6-107d011fdc49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775815784 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.775815784
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3848561153
Short name T182
Test name
Test status
Simulation time 12992122 ps
CPU time 0.86 seconds
Started Jun 30 06:42:08 PM PDT 24
Finished Jun 30 06:42:09 PM PDT 24
Peak memory 209112 kb
Host smart-04f80e0c-08ff-4dcd-a31e-adb5b526b9c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848561153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3848561153
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1377976004
Short name T193
Test name
Test status
Simulation time 22424802 ps
CPU time 1.15 seconds
Started Jun 30 06:42:05 PM PDT 24
Finished Jun 30 06:42:07 PM PDT 24
Peak memory 217856 kb
Host smart-e38453c6-137f-4743-88c1-911e8cee1117
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377976004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1377976004
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.4013755735
Short name T120
Test name
Test status
Simulation time 48906031 ps
CPU time 2.02 seconds
Started Jun 30 06:42:07 PM PDT 24
Finished Jun 30 06:42:09 PM PDT 24
Peak memory 217724 kb
Host smart-3698e737-c3b0-43de-a8e1-0c390c27d78a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013755735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.4013755735
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.493655842
Short name T886
Test name
Test status
Simulation time 84620404 ps
CPU time 1.42 seconds
Started Jun 30 06:42:08 PM PDT 24
Finished Jun 30 06:42:10 PM PDT 24
Peak memory 217696 kb
Host smart-e6b47e74-0266-4e8c-99b5-8c7ebf2a11ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493655842 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.493655842
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.598423135
Short name T885
Test name
Test status
Simulation time 31918158 ps
CPU time 0.85 seconds
Started Jun 30 06:42:05 PM PDT 24
Finished Jun 30 06:42:07 PM PDT 24
Peak memory 209024 kb
Host smart-012bb8da-6e92-4025-8217-bed7cd1b1ba0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598423135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.598423135
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1500974789
Short name T927
Test name
Test status
Simulation time 71728472 ps
CPU time 1.07 seconds
Started Jun 30 06:42:06 PM PDT 24
Finished Jun 30 06:42:08 PM PDT 24
Peak memory 217600 kb
Host smart-7ec4c4a3-9a3c-43f9-84fc-941f9c5b235a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500974789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.1500974789
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.148980449
Short name T975
Test name
Test status
Simulation time 89752398 ps
CPU time 1.77 seconds
Started Jun 30 06:42:08 PM PDT 24
Finished Jun 30 06:42:10 PM PDT 24
Peak memory 217540 kb
Host smart-67e84a97-c50e-4a1f-83cd-3b9b8da4bb68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148980449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.148980449
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.4228814985
Short name T981
Test name
Test status
Simulation time 19510477 ps
CPU time 1.29 seconds
Started Jun 30 06:42:06 PM PDT 24
Finished Jun 30 06:42:07 PM PDT 24
Peak memory 219248 kb
Host smart-8d4df98b-b023-4089-ba02-e74b77f35670
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228814985 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.4228814985
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.581475427
Short name T191
Test name
Test status
Simulation time 11988719 ps
CPU time 1.03 seconds
Started Jun 30 06:42:07 PM PDT 24
Finished Jun 30 06:42:08 PM PDT 24
Peak memory 209160 kb
Host smart-70959b7c-512f-4d03-953d-4186938c17f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581475427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.581475427
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2263774161
Short name T904
Test name
Test status
Simulation time 201032454 ps
CPU time 1.46 seconds
Started Jun 30 06:42:09 PM PDT 24
Finished Jun 30 06:42:10 PM PDT 24
Peak memory 209388 kb
Host smart-f62b50ba-b0dd-4837-9099-67b19fb3ff86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263774161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2263774161
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.184972751
Short name T900
Test name
Test status
Simulation time 128885980 ps
CPU time 1.73 seconds
Started Jun 30 06:42:05 PM PDT 24
Finished Jun 30 06:42:08 PM PDT 24
Peak memory 219516 kb
Host smart-d24c3156-3f1d-4cc4-b286-74275aab6f93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184972751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.184972751
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1069867241
Short name T105
Test name
Test status
Simulation time 135675074 ps
CPU time 2.16 seconds
Started Jun 30 06:42:06 PM PDT 24
Finished Jun 30 06:42:09 PM PDT 24
Peak memory 221944 kb
Host smart-c9e9bf9a-b462-4ee4-9e8c-959d0501ed7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069867241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.1069867241
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1446303381
Short name T945
Test name
Test status
Simulation time 103049326 ps
CPU time 1.67 seconds
Started Jun 30 06:42:05 PM PDT 24
Finished Jun 30 06:42:07 PM PDT 24
Peak memory 224312 kb
Host smart-9a8c3a2d-987c-4b03-a4f6-105fb0b20710
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446303381 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1446303381
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3983227686
Short name T149
Test name
Test status
Simulation time 55623500 ps
CPU time 0.91 seconds
Started Jun 30 06:42:05 PM PDT 24
Finished Jun 30 06:42:06 PM PDT 24
Peak memory 209320 kb
Host smart-008a6d21-b51e-47b0-bbfd-e1029da0e67a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983227686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3983227686
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2713706909
Short name T933
Test name
Test status
Simulation time 27472968 ps
CPU time 1.05 seconds
Started Jun 30 06:42:07 PM PDT 24
Finished Jun 30 06:42:09 PM PDT 24
Peak memory 209492 kb
Host smart-af8375ad-a442-48e7-b6a7-fa5609c2418e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713706909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2713706909
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3505921988
Short name T954
Test name
Test status
Simulation time 76671075 ps
CPU time 3.31 seconds
Started Jun 30 06:42:09 PM PDT 24
Finished Jun 30 06:42:12 PM PDT 24
Peak memory 217532 kb
Host smart-6ab03725-9963-47ab-8f77-eac1416ff86a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505921988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3505921988
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2808042050
Short name T127
Test name
Test status
Simulation time 63049333 ps
CPU time 2.61 seconds
Started Jun 30 06:42:06 PM PDT 24
Finished Jun 30 06:42:09 PM PDT 24
Peak memory 217716 kb
Host smart-b4ce1da5-9ebe-44d5-8211-b95e0eea5c3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808042050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2808042050
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2886370473
Short name T940
Test name
Test status
Simulation time 21239209 ps
CPU time 1.42 seconds
Started Jun 30 06:42:12 PM PDT 24
Finished Jun 30 06:42:14 PM PDT 24
Peak memory 217840 kb
Host smart-610b6cfb-9c46-46e6-b8c4-701baecfbe11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886370473 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2886370473
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1720903195
Short name T909
Test name
Test status
Simulation time 77217065 ps
CPU time 0.83 seconds
Started Jun 30 06:42:12 PM PDT 24
Finished Jun 30 06:42:13 PM PDT 24
Peak memory 208724 kb
Host smart-08dc4083-8ac7-475a-98de-4cc9db1b484c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720903195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.1720903195
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2242249712
Short name T961
Test name
Test status
Simulation time 48612167 ps
CPU time 1.5 seconds
Started Jun 30 06:42:11 PM PDT 24
Finished Jun 30 06:42:13 PM PDT 24
Peak memory 217604 kb
Host smart-7f544883-17e5-4d5b-9911-8f2d72150dcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242249712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.2242249712
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.798785695
Short name T966
Test name
Test status
Simulation time 86393241 ps
CPU time 1.74 seconds
Started Jun 30 06:42:07 PM PDT 24
Finished Jun 30 06:42:09 PM PDT 24
Peak memory 219204 kb
Host smart-0c3cbb19-8cbc-4823-9f43-2510350f1fe1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798785695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.798785695
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.246371961
Short name T905
Test name
Test status
Simulation time 58317317 ps
CPU time 2.69 seconds
Started Jun 30 06:42:11 PM PDT 24
Finished Jun 30 06:42:14 PM PDT 24
Peak memory 217644 kb
Host smart-d6551a13-26e1-40ec-9360-914e412bb6d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246371961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg_
err.246371961
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1332396669
Short name T898
Test name
Test status
Simulation time 83276147 ps
CPU time 1.17 seconds
Started Jun 30 06:42:13 PM PDT 24
Finished Jun 30 06:42:14 PM PDT 24
Peak memory 219340 kb
Host smart-d35b0c3f-7b9d-4edd-a3d9-c5059e5b547f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332396669 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.1332396669
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1228103226
Short name T969
Test name
Test status
Simulation time 57970399 ps
CPU time 0.96 seconds
Started Jun 30 06:42:13 PM PDT 24
Finished Jun 30 06:42:15 PM PDT 24
Peak memory 209320 kb
Host smart-d6c690bd-5ef1-429f-bf6a-5434d9f90a41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228103226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1228103226
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2265773821
Short name T906
Test name
Test status
Simulation time 20705133 ps
CPU time 1.48 seconds
Started Jun 30 06:42:11 PM PDT 24
Finished Jun 30 06:42:13 PM PDT 24
Peak memory 211516 kb
Host smart-a440586b-721a-473a-982a-edd03ac139c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265773821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2265773821
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.400330884
Short name T964
Test name
Test status
Simulation time 176625951 ps
CPU time 2.74 seconds
Started Jun 30 06:42:10 PM PDT 24
Finished Jun 30 06:42:13 PM PDT 24
Peak memory 218864 kb
Host smart-d5ceaf40-98ad-4e56-9bdc-045109d001da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400330884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.400330884
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3268459339
Short name T895
Test name
Test status
Simulation time 38751159 ps
CPU time 1.06 seconds
Started Jun 30 06:42:14 PM PDT 24
Finished Jun 30 06:42:15 PM PDT 24
Peak memory 218596 kb
Host smart-c75f7d20-b8ee-4d54-a7e2-7c7dd6fc03b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268459339 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3268459339
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2295800535
Short name T892
Test name
Test status
Simulation time 21761959 ps
CPU time 0.82 seconds
Started Jun 30 06:42:12 PM PDT 24
Finished Jun 30 06:42:13 PM PDT 24
Peak memory 208592 kb
Host smart-a443cbf9-252b-468f-9ab2-5aae137fee62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295800535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2295800535
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.184854671
Short name T944
Test name
Test status
Simulation time 127699441 ps
CPU time 1.29 seconds
Started Jun 30 06:42:09 PM PDT 24
Finished Jun 30 06:42:11 PM PDT 24
Peak memory 217588 kb
Host smart-58b1d369-f037-4402-833e-33c89c8571df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184854671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_same_csr_outstanding.184854671
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.4099084364
Short name T103
Test name
Test status
Simulation time 99832065 ps
CPU time 1.66 seconds
Started Jun 30 06:42:11 PM PDT 24
Finished Jun 30 06:42:14 PM PDT 24
Peak memory 219064 kb
Host smart-bc1f5648-c9fc-4e49-a09c-d8f20e77e37a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099084364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.4099084364
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1013524700
Short name T123
Test name
Test status
Simulation time 125111725 ps
CPU time 2.72 seconds
Started Jun 30 06:42:12 PM PDT 24
Finished Jun 30 06:42:15 PM PDT 24
Peak memory 217628 kb
Host smart-e8a2bd9c-4c85-47f7-8fe0-37ff9ce2408e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013524700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1013524700
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1832117270
Short name T919
Test name
Test status
Simulation time 67789190 ps
CPU time 1.57 seconds
Started Jun 30 06:42:13 PM PDT 24
Finished Jun 30 06:42:15 PM PDT 24
Peak memory 218008 kb
Host smart-f46d6990-781e-4881-a6a8-be5f3247cb58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832117270 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1832117270
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2255319349
Short name T879
Test name
Test status
Simulation time 15583440 ps
CPU time 0.87 seconds
Started Jun 30 06:42:13 PM PDT 24
Finished Jun 30 06:42:14 PM PDT 24
Peak memory 209184 kb
Host smart-08c25928-e274-4efe-9ca2-b724cf416b65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255319349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2255319349
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3559082362
Short name T953
Test name
Test status
Simulation time 580371478 ps
CPU time 1.98 seconds
Started Jun 30 06:42:13 PM PDT 24
Finished Jun 30 06:42:16 PM PDT 24
Peak memory 211356 kb
Host smart-689586ce-5e6a-4b10-b5b0-38d86fe539cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559082362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3559082362
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2335114471
Short name T107
Test name
Test status
Simulation time 587563786 ps
CPU time 1.83 seconds
Started Jun 30 06:42:11 PM PDT 24
Finished Jun 30 06:42:14 PM PDT 24
Peak memory 217600 kb
Host smart-521e1ef5-df2d-4925-a954-247effceee98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335114471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.2335114471
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1833181619
Short name T921
Test name
Test status
Simulation time 53276401 ps
CPU time 1.26 seconds
Started Jun 30 06:42:17 PM PDT 24
Finished Jun 30 06:42:19 PM PDT 24
Peak memory 218696 kb
Host smart-f3a047f5-3024-4efb-9774-b43f276eea43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833181619 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.1833181619
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3522116680
Short name T881
Test name
Test status
Simulation time 16498956 ps
CPU time 1.12 seconds
Started Jun 30 06:42:13 PM PDT 24
Finished Jun 30 06:42:15 PM PDT 24
Peak memory 209400 kb
Host smart-dcd31ca2-936a-4b14-aec7-0873254d49a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522116680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.3522116680
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.329545332
Short name T902
Test name
Test status
Simulation time 31743068 ps
CPU time 1.03 seconds
Started Jun 30 06:42:10 PM PDT 24
Finished Jun 30 06:42:12 PM PDT 24
Peak memory 217688 kb
Host smart-71dc3333-2bc9-47f6-8d13-98c62621662e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329545332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_same_csr_outstanding.329545332
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.47855903
Short name T889
Test name
Test status
Simulation time 205478312 ps
CPU time 2.74 seconds
Started Jun 30 06:42:12 PM PDT 24
Finished Jun 30 06:42:15 PM PDT 24
Peak memory 217532 kb
Host smart-d542de28-9557-48fb-ac01-5823068c0ab1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47855903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.47855903
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2990026675
Short name T211
Test name
Test status
Simulation time 67121219 ps
CPU time 2.82 seconds
Started Jun 30 06:42:12 PM PDT 24
Finished Jun 30 06:42:16 PM PDT 24
Peak memory 217580 kb
Host smart-e0df2d23-b475-4a05-9e1d-b6f48232bee0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990026675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.2990026675
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1203426927
Short name T189
Test name
Test status
Simulation time 92980710 ps
CPU time 1.33 seconds
Started Jun 30 06:41:34 PM PDT 24
Finished Jun 30 06:41:36 PM PDT 24
Peak memory 209284 kb
Host smart-08a248c4-620c-4ac0-b3fc-d842c578ff12
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203426927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.1203426927
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.10096494
Short name T965
Test name
Test status
Simulation time 112899912 ps
CPU time 1.81 seconds
Started Jun 30 06:41:34 PM PDT 24
Finished Jun 30 06:41:36 PM PDT 24
Peak memory 217236 kb
Host smart-5bcb2090-e4a6-4907-9e38-065c47de77e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10096494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bash.10096494
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.567255227
Short name T977
Test name
Test status
Simulation time 20235913 ps
CPU time 0.89 seconds
Started Jun 30 06:41:33 PM PDT 24
Finished Jun 30 06:41:34 PM PDT 24
Peak memory 208632 kb
Host smart-0230607e-71df-4dfe-a901-5c1f7d63106d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567255227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_reset
.567255227
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.227590695
Short name T935
Test name
Test status
Simulation time 25255971 ps
CPU time 1.91 seconds
Started Jun 30 06:41:38 PM PDT 24
Finished Jun 30 06:41:40 PM PDT 24
Peak memory 223876 kb
Host smart-68aee990-0093-40db-bf0a-33a836286681
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227590695 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.227590695
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1935790540
Short name T972
Test name
Test status
Simulation time 16000118 ps
CPU time 0.93 seconds
Started Jun 30 06:41:41 PM PDT 24
Finished Jun 30 06:41:42 PM PDT 24
Peak memory 209236 kb
Host smart-2876a937-dd7a-46bc-b77c-599a6662be85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935790540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1935790540
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3192496482
Short name T873
Test name
Test status
Simulation time 64342992 ps
CPU time 2.32 seconds
Started Jun 30 06:41:33 PM PDT 24
Finished Jun 30 06:41:36 PM PDT 24
Peak memory 209332 kb
Host smart-5aee4e17-a270-4436-9997-80fcb2b00199
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192496482 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3192496482
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3612842117
Short name T916
Test name
Test status
Simulation time 1524638729 ps
CPU time 4.68 seconds
Started Jun 30 06:41:32 PM PDT 24
Finished Jun 30 06:41:37 PM PDT 24
Peak memory 209076 kb
Host smart-8ae51da2-1dc4-464a-a8df-1fb289b5b17a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612842117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.3612842117
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1499392310
Short name T202
Test name
Test status
Simulation time 11721032483 ps
CPU time 43.68 seconds
Started Jun 30 06:41:33 PM PDT 24
Finished Jun 30 06:42:17 PM PDT 24
Peak memory 209268 kb
Host smart-883a5c9c-0ca2-466e-8f6b-068b561fe400
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499392310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1499392310
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3272122683
Short name T938
Test name
Test status
Simulation time 490162030 ps
CPU time 1.86 seconds
Started Jun 30 06:41:34 PM PDT 24
Finished Jun 30 06:41:37 PM PDT 24
Peak memory 210624 kb
Host smart-9c40a13b-c033-48fe-84d8-f232070da36b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272122683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3272122683
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3216706835
Short name T939
Test name
Test status
Simulation time 168788763 ps
CPU time 1.26 seconds
Started Jun 30 06:41:33 PM PDT 24
Finished Jun 30 06:41:35 PM PDT 24
Peak memory 217648 kb
Host smart-723caf12-1093-4e35-9a2d-6ac53bb7ff85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321670
6835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3216706835
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3390490448
Short name T917
Test name
Test status
Simulation time 269025899 ps
CPU time 3.82 seconds
Started Jun 30 06:41:34 PM PDT 24
Finished Jun 30 06:41:39 PM PDT 24
Peak memory 209248 kb
Host smart-fedd4f2a-0ad6-4540-a2fd-6b73bd619a82
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390490448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3390490448
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.233924374
Short name T976
Test name
Test status
Simulation time 72252966 ps
CPU time 1.09 seconds
Started Jun 30 06:41:33 PM PDT 24
Finished Jun 30 06:41:34 PM PDT 24
Peak memory 217564 kb
Host smart-144a7c2c-84ac-4df7-b9ba-a68d005dd0ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233924374 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.233924374
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.866730645
Short name T110
Test name
Test status
Simulation time 38463877 ps
CPU time 1.4 seconds
Started Jun 30 06:41:34 PM PDT 24
Finished Jun 30 06:41:36 PM PDT 24
Peak memory 209388 kb
Host smart-fd04f903-46d4-4368-9d8c-5485c826b710
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866730645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
same_csr_outstanding.866730645
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1787068128
Short name T928
Test name
Test status
Simulation time 51673638 ps
CPU time 3.32 seconds
Started Jun 30 06:41:41 PM PDT 24
Finished Jun 30 06:41:45 PM PDT 24
Peak memory 217588 kb
Host smart-906e86fa-45b9-402f-9b7d-21fbd7262b1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787068128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1787068128
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.327559836
Short name T952
Test name
Test status
Simulation time 51362195 ps
CPU time 1.49 seconds
Started Jun 30 06:41:41 PM PDT 24
Finished Jun 30 06:41:43 PM PDT 24
Peak memory 209268 kb
Host smart-fe9f920a-8b56-47f2-9000-e15f280e968a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327559836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bash
.327559836
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1189652524
Short name T185
Test name
Test status
Simulation time 16605843 ps
CPU time 0.93 seconds
Started Jun 30 06:41:42 PM PDT 24
Finished Jun 30 06:41:44 PM PDT 24
Peak memory 209776 kb
Host smart-1d4df483-ac00-4e52-b0fe-6ed4bf0dacdf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189652524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.1189652524
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.102564176
Short name T883
Test name
Test status
Simulation time 71155840 ps
CPU time 1.58 seconds
Started Jun 30 06:41:41 PM PDT 24
Finished Jun 30 06:41:43 PM PDT 24
Peak memory 217692 kb
Host smart-573a5ce5-ca06-435f-9da7-bec97f2ca08b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102564176 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.102564176
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2542580446
Short name T132
Test name
Test status
Simulation time 41533184 ps
CPU time 0.84 seconds
Started Jun 30 06:41:41 PM PDT 24
Finished Jun 30 06:41:42 PM PDT 24
Peak memory 208808 kb
Host smart-e0f27a52-042b-4492-8b36-70aed50af159
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542580446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2542580446
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3740368466
Short name T882
Test name
Test status
Simulation time 36444773 ps
CPU time 1.56 seconds
Started Jun 30 06:41:43 PM PDT 24
Finished Jun 30 06:41:45 PM PDT 24
Peak memory 209244 kb
Host smart-5eb9267b-90e6-4a5f-bbfc-d2921e120671
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740368466 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3740368466
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2594771475
Short name T911
Test name
Test status
Simulation time 1540541041 ps
CPU time 10.86 seconds
Started Jun 30 06:41:42 PM PDT 24
Finished Jun 30 06:41:54 PM PDT 24
Peak memory 209024 kb
Host smart-22078e94-a857-4cd9-8f0c-3978cee63aad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594771475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2594771475
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3302113160
Short name T991
Test name
Test status
Simulation time 1249006650 ps
CPU time 11.69 seconds
Started Jun 30 06:41:33 PM PDT 24
Finished Jun 30 06:41:45 PM PDT 24
Peak memory 208816 kb
Host smart-a0f007ae-a883-4687-b896-4022ee91e939
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302113160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3302113160
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3670469396
Short name T936
Test name
Test status
Simulation time 1699936898 ps
CPU time 3.3 seconds
Started Jun 30 06:41:34 PM PDT 24
Finished Jun 30 06:41:38 PM PDT 24
Peak memory 210700 kb
Host smart-96b05a61-6da6-4130-a61a-324b6a765489
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670469396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3670469396
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.975589608
Short name T119
Test name
Test status
Simulation time 375944326 ps
CPU time 2.67 seconds
Started Jun 30 06:41:44 PM PDT 24
Finished Jun 30 06:41:47 PM PDT 24
Peak memory 219216 kb
Host smart-9aa78229-2254-4812-81c3-53a3f544bf8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975589
608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.975589608
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1633040560
Short name T924
Test name
Test status
Simulation time 69342896 ps
CPU time 1.45 seconds
Started Jun 30 06:41:34 PM PDT 24
Finished Jun 30 06:41:36 PM PDT 24
Peak memory 209212 kb
Host smart-831acd92-0c09-4944-a516-540dcb41491d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633040560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.1633040560
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1899274148
Short name T982
Test name
Test status
Simulation time 141972179 ps
CPU time 1.45 seconds
Started Jun 30 06:41:43 PM PDT 24
Finished Jun 30 06:41:45 PM PDT 24
Peak memory 211456 kb
Host smart-3a210c4a-230f-43f2-a26d-537be85382cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899274148 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1899274148
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2776430267
Short name T990
Test name
Test status
Simulation time 47301504 ps
CPU time 1.43 seconds
Started Jun 30 06:41:41 PM PDT 24
Finished Jun 30 06:41:43 PM PDT 24
Peak memory 211696 kb
Host smart-3490707c-a187-4cf9-b7a8-66f86b8d9721
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776430267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.2776430267
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3390588878
Short name T111
Test name
Test status
Simulation time 155807044 ps
CPU time 1.46 seconds
Started Jun 30 06:41:43 PM PDT 24
Finished Jun 30 06:41:45 PM PDT 24
Peak memory 218200 kb
Host smart-dcf77d92-655f-4e76-ad31-800959897c4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390588878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.3390588878
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1134676130
Short name T963
Test name
Test status
Simulation time 207880667 ps
CPU time 2.01 seconds
Started Jun 30 06:41:42 PM PDT 24
Finished Jun 30 06:41:45 PM PDT 24
Peak memory 221932 kb
Host smart-4a7dbad6-4fab-4782-b68a-313eb45c592f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134676130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.1134676130
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3383584576
Short name T181
Test name
Test status
Simulation time 32873541 ps
CPU time 1.38 seconds
Started Jun 30 06:41:42 PM PDT 24
Finished Jun 30 06:41:44 PM PDT 24
Peak memory 209324 kb
Host smart-05f7816c-7b54-41b7-bc27-2f3ddfaf3a0a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383584576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.3383584576
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3323279012
Short name T962
Test name
Test status
Simulation time 140690178 ps
CPU time 1.16 seconds
Started Jun 30 06:41:43 PM PDT 24
Finished Jun 30 06:41:45 PM PDT 24
Peak memory 209264 kb
Host smart-56b8ee17-e201-41ef-9680-31fb744c4397
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323279012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.3323279012
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.4262551939
Short name T988
Test name
Test status
Simulation time 34292273 ps
CPU time 1.25 seconds
Started Jun 30 06:41:41 PM PDT 24
Finished Jun 30 06:41:43 PM PDT 24
Peak memory 211628 kb
Host smart-67e3885b-0ce8-435f-a8a1-6eacf435cbda
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262551939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.4262551939
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.866756404
Short name T158
Test name
Test status
Simulation time 152596132 ps
CPU time 1.29 seconds
Started Jun 30 06:41:47 PM PDT 24
Finished Jun 30 06:41:49 PM PDT 24
Peak memory 217464 kb
Host smart-2058339b-456f-4ecc-95a8-0639e9bc6261
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866756404 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.866756404
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.68179333
Short name T188
Test name
Test status
Simulation time 38651951 ps
CPU time 0.95 seconds
Started Jun 30 06:41:41 PM PDT 24
Finished Jun 30 06:41:43 PM PDT 24
Peak memory 208640 kb
Host smart-19cc99af-c5c5-46b7-9ee7-b4f62879eab8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68179333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.68179333
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.826294934
Short name T877
Test name
Test status
Simulation time 40403542 ps
CPU time 1.12 seconds
Started Jun 30 06:41:41 PM PDT 24
Finished Jun 30 06:41:43 PM PDT 24
Peak memory 208584 kb
Host smart-d623c84e-8302-4d41-b4bd-4b68590ab0f5
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826294934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_alert_test.826294934
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1528800099
Short name T968
Test name
Test status
Simulation time 1307242709 ps
CPU time 6.22 seconds
Started Jun 30 06:41:40 PM PDT 24
Finished Jun 30 06:41:47 PM PDT 24
Peak memory 208884 kb
Host smart-9faab7f0-a122-47e9-8c67-2efe182461bc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528800099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.1528800099
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3159207995
Short name T937
Test name
Test status
Simulation time 1390244051 ps
CPU time 7.49 seconds
Started Jun 30 06:41:42 PM PDT 24
Finished Jun 30 06:41:51 PM PDT 24
Peak memory 217004 kb
Host smart-703b1d53-6ac5-4943-9026-147a22f1034d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159207995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3159207995
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2328168365
Short name T878
Test name
Test status
Simulation time 67551962 ps
CPU time 2.23 seconds
Started Jun 30 06:41:40 PM PDT 24
Finished Jun 30 06:41:43 PM PDT 24
Peak memory 210672 kb
Host smart-1a1298df-05ab-4f99-956c-48b3e4dde8c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328168365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2328168365
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4251650471
Short name T884
Test name
Test status
Simulation time 1212992594 ps
CPU time 2.32 seconds
Started Jun 30 06:41:44 PM PDT 24
Finished Jun 30 06:41:47 PM PDT 24
Peak memory 217616 kb
Host smart-bede6709-b8fc-4dea-8c5e-51156f7c870c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425165
0471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4251650471
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3647476363
Short name T114
Test name
Test status
Simulation time 163895977 ps
CPU time 1.2 seconds
Started Jun 30 06:41:41 PM PDT 24
Finished Jun 30 06:41:43 PM PDT 24
Peak memory 209240 kb
Host smart-f26f16d5-7b3b-4689-b0c0-052693bcca84
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647476363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.3647476363
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1841809100
Short name T984
Test name
Test status
Simulation time 114553618 ps
CPU time 1.06 seconds
Started Jun 30 06:41:43 PM PDT 24
Finished Jun 30 06:41:44 PM PDT 24
Peak memory 209388 kb
Host smart-ffadd37f-cb23-4388-adff-614cc944957d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841809100 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1841809100
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2393725358
Short name T198
Test name
Test status
Simulation time 43273819 ps
CPU time 1.42 seconds
Started Jun 30 06:41:47 PM PDT 24
Finished Jun 30 06:41:49 PM PDT 24
Peak memory 209380 kb
Host smart-285d40fb-5338-4e39-81a0-9816d68bf1c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393725358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.2393725358
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2289407122
Short name T931
Test name
Test status
Simulation time 88895638 ps
CPU time 2.94 seconds
Started Jun 30 06:41:44 PM PDT 24
Finished Jun 30 06:41:47 PM PDT 24
Peak memory 217532 kb
Host smart-4f47db02-e448-4eb6-ba89-8431ee1536b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289407122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2289407122
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1183507615
Short name T126
Test name
Test status
Simulation time 26993199 ps
CPU time 2.03 seconds
Started Jun 30 06:41:48 PM PDT 24
Finished Jun 30 06:41:50 PM PDT 24
Peak memory 217672 kb
Host smart-657ff036-b4c3-468e-97be-7faeddab7fa8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183507615 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1183507615
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2077391414
Short name T190
Test name
Test status
Simulation time 25199759 ps
CPU time 0.89 seconds
Started Jun 30 06:41:49 PM PDT 24
Finished Jun 30 06:41:51 PM PDT 24
Peak memory 209260 kb
Host smart-11675f30-6d74-49a6-9319-337b29272309
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077391414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2077391414
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1957114792
Short name T985
Test name
Test status
Simulation time 279479319 ps
CPU time 1.19 seconds
Started Jun 30 06:41:48 PM PDT 24
Finished Jun 30 06:41:51 PM PDT 24
Peak memory 209204 kb
Host smart-f623cc24-f47b-4019-9b85-2d2eac9aa12b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957114792 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1957114792
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2953297578
Short name T974
Test name
Test status
Simulation time 1263201739 ps
CPU time 6.53 seconds
Started Jun 30 06:41:47 PM PDT 24
Finished Jun 30 06:41:53 PM PDT 24
Peak memory 217064 kb
Host smart-0883c617-5a94-4d96-9b33-ce10944fa91f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953297578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2953297578
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3831373977
Short name T918
Test name
Test status
Simulation time 2796450523 ps
CPU time 15.75 seconds
Started Jun 30 06:41:48 PM PDT 24
Finished Jun 30 06:42:05 PM PDT 24
Peak memory 217132 kb
Host smart-9f08bc2e-da70-440c-9cca-2ea1a3e01cc7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831373977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3831373977
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1078042396
Short name T133
Test name
Test status
Simulation time 52295352 ps
CPU time 1.44 seconds
Started Jun 30 06:41:46 PM PDT 24
Finished Jun 30 06:41:48 PM PDT 24
Peak memory 218664 kb
Host smart-da2532c3-0892-47d5-b8be-3cd114b085cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107804
2396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1078042396
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3329662150
Short name T993
Test name
Test status
Simulation time 126361559 ps
CPU time 2.11 seconds
Started Jun 30 06:41:48 PM PDT 24
Finished Jun 30 06:41:51 PM PDT 24
Peak memory 209212 kb
Host smart-4a796f06-4aa5-4dbe-a282-8f06bd36b859
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329662150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3329662150
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.4121898131
Short name T970
Test name
Test status
Simulation time 39672115 ps
CPU time 1.58 seconds
Started Jun 30 06:41:49 PM PDT 24
Finished Jun 30 06:41:52 PM PDT 24
Peak memory 217612 kb
Host smart-b1309c97-180e-443b-b7f5-5e71eebbe359
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121898131 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.4121898131
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3455241572
Short name T194
Test name
Test status
Simulation time 23666726 ps
CPU time 1.32 seconds
Started Jun 30 06:41:47 PM PDT 24
Finished Jun 30 06:41:48 PM PDT 24
Peak memory 211452 kb
Host smart-b1fdeaba-9c3a-438e-bd76-1ab50336c1c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455241572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.3455241572
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.4269206488
Short name T986
Test name
Test status
Simulation time 1822412329 ps
CPU time 4.01 seconds
Started Jun 30 06:41:59 PM PDT 24
Finished Jun 30 06:42:03 PM PDT 24
Peak memory 217564 kb
Host smart-a17c25a9-66be-4724-99f2-051be6601af2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269206488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.4269206488
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2629817140
Short name T104
Test name
Test status
Simulation time 220913647 ps
CPU time 2.13 seconds
Started Jun 30 06:41:47 PM PDT 24
Finished Jun 30 06:41:50 PM PDT 24
Peak memory 221864 kb
Host smart-b00e5d77-99df-4f34-b203-09982b716620
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629817140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.2629817140
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.336266292
Short name T923
Test name
Test status
Simulation time 338126179 ps
CPU time 1.33 seconds
Started Jun 30 06:41:49 PM PDT 24
Finished Jun 30 06:41:51 PM PDT 24
Peak memory 217884 kb
Host smart-ab6eea2d-83fa-441c-82c1-34538cae60cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336266292 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.336266292
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2969341164
Short name T151
Test name
Test status
Simulation time 26396791 ps
CPU time 1.07 seconds
Started Jun 30 06:41:48 PM PDT 24
Finished Jun 30 06:41:50 PM PDT 24
Peak memory 209260 kb
Host smart-ec9e5c12-51e1-4a7d-9a00-62c0959edb9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969341164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.2969341164
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.47574016
Short name T926
Test name
Test status
Simulation time 47656281 ps
CPU time 1.26 seconds
Started Jun 30 06:41:48 PM PDT 24
Finished Jun 30 06:41:50 PM PDT 24
Peak memory 209180 kb
Host smart-7a42ec5f-5934-4977-a9db-93824d964d42
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47574016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_alert_test.47574016
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2515344311
Short name T956
Test name
Test status
Simulation time 1359706905 ps
CPU time 7.17 seconds
Started Jun 30 06:41:49 PM PDT 24
Finished Jun 30 06:41:57 PM PDT 24
Peak memory 209028 kb
Host smart-a7a26276-a824-47f6-8398-5aeecee15176
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515344311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2515344311
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2989738811
Short name T890
Test name
Test status
Simulation time 3181211808 ps
CPU time 20.42 seconds
Started Jun 30 06:41:59 PM PDT 24
Finished Jun 30 06:42:19 PM PDT 24
Peak memory 217300 kb
Host smart-58e2d23a-dc81-4a2b-942a-48d9430681e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989738811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.2989738811
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.940320314
Short name T891
Test name
Test status
Simulation time 65647460 ps
CPU time 2.34 seconds
Started Jun 30 06:41:49 PM PDT 24
Finished Jun 30 06:41:52 PM PDT 24
Peak memory 210744 kb
Host smart-4267c60c-8330-4278-9ea8-b7f44979a4ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940320314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.940320314
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2568289712
Short name T992
Test name
Test status
Simulation time 505079667 ps
CPU time 7.35 seconds
Started Jun 30 06:41:59 PM PDT 24
Finished Jun 30 06:42:06 PM PDT 24
Peak memory 218728 kb
Host smart-d530eba7-51b5-4321-8644-3470ed2b044e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256828
9712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2568289712
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2736335148
Short name T903
Test name
Test status
Simulation time 49908932 ps
CPU time 1.32 seconds
Started Jun 30 06:41:58 PM PDT 24
Finished Jun 30 06:42:00 PM PDT 24
Peak memory 209240 kb
Host smart-125f12ce-aef9-4c2a-bc81-b0563d6a5d7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736335148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.2736335148
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.834136794
Short name T934
Test name
Test status
Simulation time 36327778 ps
CPU time 1.39 seconds
Started Jun 30 06:41:58 PM PDT 24
Finished Jun 30 06:42:00 PM PDT 24
Peak memory 217568 kb
Host smart-c34cf5d9-fcb2-472f-8f8d-cc6d5c96905e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834136794 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.834136794
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.263127703
Short name T196
Test name
Test status
Simulation time 108403772 ps
CPU time 1.51 seconds
Started Jun 30 06:41:49 PM PDT 24
Finished Jun 30 06:41:52 PM PDT 24
Peak memory 217636 kb
Host smart-7dafc0d1-e50f-47cd-abee-b62fe5cf1cfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263127703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
same_csr_outstanding.263127703
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2338722172
Short name T960
Test name
Test status
Simulation time 53131058 ps
CPU time 1.96 seconds
Started Jun 30 06:41:59 PM PDT 24
Finished Jun 30 06:42:01 PM PDT 24
Peak memory 217884 kb
Host smart-4189b031-f9e1-4e4a-a048-9b701fd0a0d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338722172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2338722172
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3883596363
Short name T131
Test name
Test status
Simulation time 43576267 ps
CPU time 2.25 seconds
Started Jun 30 06:41:47 PM PDT 24
Finished Jun 30 06:41:50 PM PDT 24
Peak memory 222040 kb
Host smart-08962a1c-1ffa-4935-b111-e6629725676c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883596363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.3883596363
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.878076216
Short name T156
Test name
Test status
Simulation time 43143714 ps
CPU time 1.17 seconds
Started Jun 30 06:41:54 PM PDT 24
Finished Jun 30 06:41:55 PM PDT 24
Peak memory 219376 kb
Host smart-f0d3df0e-a5ae-4ccb-b4d3-ed62f0a6ab7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878076216 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.878076216
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.835183346
Short name T183
Test name
Test status
Simulation time 39104845 ps
CPU time 0.96 seconds
Started Jun 30 06:41:57 PM PDT 24
Finished Jun 30 06:41:58 PM PDT 24
Peak memory 209264 kb
Host smart-6197dfd2-51b4-421d-8ca8-1b52c603b922
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835183346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.835183346
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1857135586
Short name T980
Test name
Test status
Simulation time 163750001 ps
CPU time 1.1 seconds
Started Jun 30 06:41:58 PM PDT 24
Finished Jun 30 06:41:59 PM PDT 24
Peak memory 208752 kb
Host smart-907d2a36-394e-47ac-9e86-a66b0f103aa9
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857135586 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1857135586
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.59993186
Short name T946
Test name
Test status
Simulation time 894629491 ps
CPU time 8.88 seconds
Started Jun 30 06:41:54 PM PDT 24
Finished Jun 30 06:42:03 PM PDT 24
Peak memory 217116 kb
Host smart-84b504ed-6cae-4db3-8284-4c6c7e47dffe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59993186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.lc_ctrl_jtag_csr_aliasing.59993186
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2891507427
Short name T930
Test name
Test status
Simulation time 3846930486 ps
CPU time 22.11 seconds
Started Jun 30 06:41:54 PM PDT 24
Finished Jun 30 06:42:17 PM PDT 24
Peak memory 209300 kb
Host smart-822ca09c-1a98-4d5d-aed0-85e28173ba20
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891507427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2891507427
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1921073774
Short name T925
Test name
Test status
Simulation time 149349232 ps
CPU time 3.96 seconds
Started Jun 30 06:41:55 PM PDT 24
Finished Jun 30 06:42:00 PM PDT 24
Peak memory 210916 kb
Host smart-308835a0-4ba6-4f7b-8ca5-38fc93fb7833
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921073774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1921073774
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.716538610
Short name T914
Test name
Test status
Simulation time 215874707 ps
CPU time 1.82 seconds
Started Jun 30 06:41:55 PM PDT 24
Finished Jun 30 06:41:58 PM PDT 24
Peak memory 217628 kb
Host smart-0a6e8d46-d137-4dcb-a098-a815ab68fe16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716538
610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.716538610
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1489589333
Short name T932
Test name
Test status
Simulation time 131492553 ps
CPU time 1.1 seconds
Started Jun 30 06:41:53 PM PDT 24
Finished Jun 30 06:41:55 PM PDT 24
Peak memory 209200 kb
Host smart-053d6c08-a608-4bed-ba07-deec779e3be4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489589333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.1489589333
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2139718623
Short name T967
Test name
Test status
Simulation time 50385071 ps
CPU time 2.09 seconds
Started Jun 30 06:41:55 PM PDT 24
Finished Jun 30 06:41:57 PM PDT 24
Peak memory 211384 kb
Host smart-d2f1b87a-96fd-4944-ad48-da92d2bb2dfd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139718623 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2139718623
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2901621459
Short name T192
Test name
Test status
Simulation time 24512680 ps
CPU time 1 seconds
Started Jun 30 06:41:53 PM PDT 24
Finished Jun 30 06:41:55 PM PDT 24
Peak memory 209388 kb
Host smart-ae863ab5-e7b5-4627-9e64-588d084d11ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901621459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.2901621459
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.116346736
Short name T896
Test name
Test status
Simulation time 155700214 ps
CPU time 2.67 seconds
Started Jun 30 06:41:55 PM PDT 24
Finished Jun 30 06:41:58 PM PDT 24
Peak memory 217624 kb
Host smart-4a611400-8ec9-45fe-934e-b35d566ef611
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116346736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.116346736
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1525472805
Short name T922
Test name
Test status
Simulation time 52656501 ps
CPU time 1.37 seconds
Started Jun 30 06:42:00 PM PDT 24
Finished Jun 30 06:42:02 PM PDT 24
Peak memory 217776 kb
Host smart-8def785b-f219-4596-898f-06995b8535d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525472805 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1525472805
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2966946747
Short name T915
Test name
Test status
Simulation time 57144321 ps
CPU time 0.88 seconds
Started Jun 30 06:42:00 PM PDT 24
Finished Jun 30 06:42:02 PM PDT 24
Peak memory 209268 kb
Host smart-bbeb60a5-7a0f-4028-8ccd-b21c9ca778e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966946747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2966946747
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2857880484
Short name T907
Test name
Test status
Simulation time 123458211 ps
CPU time 1.03 seconds
Started Jun 30 06:41:59 PM PDT 24
Finished Jun 30 06:42:00 PM PDT 24
Peak memory 209220 kb
Host smart-ebe0a0a2-7b22-47b2-9199-e7e1516709ed
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857880484 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2857880484
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2332675169
Short name T971
Test name
Test status
Simulation time 226159703 ps
CPU time 6.14 seconds
Started Jun 30 06:42:00 PM PDT 24
Finished Jun 30 06:42:07 PM PDT 24
Peak memory 209232 kb
Host smart-220ba2f6-4699-4939-9d6a-7ff63f8b1100
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332675169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2332675169
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.4044508157
Short name T910
Test name
Test status
Simulation time 552080564 ps
CPU time 11.04 seconds
Started Jun 30 06:41:55 PM PDT 24
Finished Jun 30 06:42:07 PM PDT 24
Peak memory 209220 kb
Host smart-0d7187f8-1fab-4865-859f-4597e3efca73
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044508157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.4044508157
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3867069561
Short name T929
Test name
Test status
Simulation time 73783119 ps
CPU time 2.33 seconds
Started Jun 30 06:41:57 PM PDT 24
Finished Jun 30 06:42:00 PM PDT 24
Peak memory 217400 kb
Host smart-b3b456ff-3e1c-4884-ac10-5a1825b4bd81
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867069561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3867069561
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.58658978
Short name T994
Test name
Test status
Simulation time 413616741 ps
CPU time 2.46 seconds
Started Jun 30 06:42:00 PM PDT 24
Finished Jun 30 06:42:03 PM PDT 24
Peak memory 223488 kb
Host smart-f28775c5-4647-459e-9784-478c0854dd23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586589
78 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.58658978
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.4129300936
Short name T947
Test name
Test status
Simulation time 56731463 ps
CPU time 1.31 seconds
Started Jun 30 06:41:55 PM PDT 24
Finished Jun 30 06:41:57 PM PDT 24
Peak memory 209224 kb
Host smart-789c5da3-7601-4ee0-a024-194f608d6233
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129300936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.4129300936
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.123894610
Short name T983
Test name
Test status
Simulation time 37920157 ps
CPU time 1.35 seconds
Started Jun 30 06:41:59 PM PDT 24
Finished Jun 30 06:42:01 PM PDT 24
Peak memory 211632 kb
Host smart-625624cd-6435-4410-a9f8-694ed3e928b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123894610 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.123894610
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.877113878
Short name T948
Test name
Test status
Simulation time 16663318 ps
CPU time 1.07 seconds
Started Jun 30 06:42:00 PM PDT 24
Finished Jun 30 06:42:02 PM PDT 24
Peak memory 209388 kb
Host smart-bd3ad5ae-2e82-4134-a244-8413f6b33ce2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877113878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
same_csr_outstanding.877113878
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1938924072
Short name T959
Test name
Test status
Simulation time 274385125 ps
CPU time 2.49 seconds
Started Jun 30 06:42:01 PM PDT 24
Finished Jun 30 06:42:05 PM PDT 24
Peak memory 217516 kb
Host smart-c9acf814-e82c-447d-9000-a4def4308a63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938924072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1938924072
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2477921627
Short name T157
Test name
Test status
Simulation time 39384672 ps
CPU time 1.33 seconds
Started Jun 30 06:42:05 PM PDT 24
Finished Jun 30 06:42:07 PM PDT 24
Peak memory 218528 kb
Host smart-bdb63773-abbc-4ec9-bdce-d38cc32e366d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477921627 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2477921627
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1533329093
Short name T912
Test name
Test status
Simulation time 19585308 ps
CPU time 1.02 seconds
Started Jun 30 06:42:09 PM PDT 24
Finished Jun 30 06:42:10 PM PDT 24
Peak memory 209072 kb
Host smart-659a835d-d6bd-4dee-8ed2-4f8f847fe94c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533329093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1533329093
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1268092028
Short name T875
Test name
Test status
Simulation time 163201343 ps
CPU time 1.12 seconds
Started Jun 30 06:42:01 PM PDT 24
Finished Jun 30 06:42:03 PM PDT 24
Peak memory 208668 kb
Host smart-523d3613-5988-4e55-900c-dfdcc9bf4afa
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268092028 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1268092028
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2495308617
Short name T134
Test name
Test status
Simulation time 1309260973 ps
CPU time 6.7 seconds
Started Jun 30 06:42:01 PM PDT 24
Finished Jun 30 06:42:08 PM PDT 24
Peak memory 216984 kb
Host smart-6c9fa6fb-47a8-4cb4-8cfd-eabae80382d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495308617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2495308617
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1975230802
Short name T973
Test name
Test status
Simulation time 693570397 ps
CPU time 16.64 seconds
Started Jun 30 06:42:00 PM PDT 24
Finished Jun 30 06:42:17 PM PDT 24
Peak memory 208980 kb
Host smart-20c70f63-ec4b-46f8-9f2c-465a0c4a7484
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975230802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1975230802
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2574036208
Short name T950
Test name
Test status
Simulation time 766717852 ps
CPU time 1.54 seconds
Started Jun 30 06:42:00 PM PDT 24
Finished Jun 30 06:42:02 PM PDT 24
Peak memory 217448 kb
Host smart-e104b72a-bb6a-405d-97a4-23168066af18
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574036208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2574036208
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1190102187
Short name T989
Test name
Test status
Simulation time 277133440 ps
CPU time 1.81 seconds
Started Jun 30 06:42:00 PM PDT 24
Finished Jun 30 06:42:03 PM PDT 24
Peak memory 218688 kb
Host smart-2cdcf728-082a-4a07-99dc-498ecb53b40c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119010
2187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1190102187
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1528523069
Short name T913
Test name
Test status
Simulation time 112320124 ps
CPU time 1.19 seconds
Started Jun 30 06:42:01 PM PDT 24
Finished Jun 30 06:42:03 PM PDT 24
Peak memory 209240 kb
Host smart-26395f7a-1350-4ec6-8403-8e5dcb817b27
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528523069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1528523069
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.677697423
Short name T949
Test name
Test status
Simulation time 50144110 ps
CPU time 1.48 seconds
Started Jun 30 06:41:59 PM PDT 24
Finished Jun 30 06:42:01 PM PDT 24
Peak memory 217532 kb
Host smart-f66e5a91-256d-490b-af6a-f935a7266598
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677697423 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.677697423
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3146516301
Short name T978
Test name
Test status
Simulation time 25358496 ps
CPU time 1.38 seconds
Started Jun 30 06:42:07 PM PDT 24
Finished Jun 30 06:42:09 PM PDT 24
Peak memory 217584 kb
Host smart-cb6b0851-381b-44eb-904a-d8e764b3cffb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146516301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.3146516301
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2522436003
Short name T987
Test name
Test status
Simulation time 99260105 ps
CPU time 2.09 seconds
Started Jun 30 06:41:59 PM PDT 24
Finished Jun 30 06:42:02 PM PDT 24
Peak memory 218980 kb
Host smart-a95d055d-2173-4f9f-8656-f27299103326
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522436003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.2522436003
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.1792481735
Short name T143
Test name
Test status
Simulation time 82467908 ps
CPU time 0.88 seconds
Started Jun 30 06:46:00 PM PDT 24
Finished Jun 30 06:46:02 PM PDT 24
Peak memory 209148 kb
Host smart-3672e1c0-9783-4984-8020-f14eab8b45b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792481735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1792481735
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1848514199
Short name T358
Test name
Test status
Simulation time 1553535201 ps
CPU time 17.72 seconds
Started Jun 30 06:45:53 PM PDT 24
Finished Jun 30 06:46:11 PM PDT 24
Peak memory 218424 kb
Host smart-cee77f61-b863-4175-85f5-3af0eecadfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848514199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1848514199
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2784511118
Short name T733
Test name
Test status
Simulation time 1740359851 ps
CPU time 3.74 seconds
Started Jun 30 06:45:58 PM PDT 24
Finished Jun 30 06:46:02 PM PDT 24
Peak memory 217380 kb
Host smart-cf752ea5-13a6-4284-8620-ecea521d57ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784511118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2784511118
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.1159452484
Short name T706
Test name
Test status
Simulation time 5589823346 ps
CPU time 23.11 seconds
Started Jun 30 06:45:57 PM PDT 24
Finished Jun 30 06:46:21 PM PDT 24
Peak memory 219156 kb
Host smart-c350547e-c666-486e-a61f-7368bbd7a649
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159452484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.1159452484
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1127484800
Short name T433
Test name
Test status
Simulation time 152991279 ps
CPU time 4.81 seconds
Started Jun 30 06:45:57 PM PDT 24
Finished Jun 30 06:46:02 PM PDT 24
Peak memory 217972 kb
Host smart-00d45e69-fb11-40e2-8b60-d5a3ec1a02ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127484800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
127484800
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2968539864
Short name T522
Test name
Test status
Simulation time 103675430 ps
CPU time 2.48 seconds
Started Jun 30 06:45:59 PM PDT 24
Finished Jun 30 06:46:02 PM PDT 24
Peak memory 221692 kb
Host smart-1ef31581-b6a0-46a3-85cc-c6ea097a120d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968539864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.2968539864
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2135374242
Short name T478
Test name
Test status
Simulation time 3961517223 ps
CPU time 12.6 seconds
Started Jun 30 06:45:59 PM PDT 24
Finished Jun 30 06:46:12 PM PDT 24
Peak memory 217984 kb
Host smart-c4a4e8ce-ae1a-45c3-9bd4-80f0080fe051
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135374242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.2135374242
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1980545768
Short name T682
Test name
Test status
Simulation time 174861942 ps
CPU time 2.17 seconds
Started Jun 30 06:45:59 PM PDT 24
Finished Jun 30 06:46:02 PM PDT 24
Peak memory 217908 kb
Host smart-37efcf9e-78f6-4d84-8cd4-523e9816365f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980545768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
1980545768
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1205509885
Short name T401
Test name
Test status
Simulation time 4719634766 ps
CPU time 39.54 seconds
Started Jun 30 06:46:02 PM PDT 24
Finished Jun 30 06:46:43 PM PDT 24
Peak memory 251188 kb
Host smart-ebaea1f3-1f1f-4e7a-9cb4-ea853b7bac94
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205509885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1205509885
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2475711912
Short name T513
Test name
Test status
Simulation time 3790761889 ps
CPU time 34.27 seconds
Started Jun 30 06:45:57 PM PDT 24
Finished Jun 30 06:46:32 PM PDT 24
Peak memory 250792 kb
Host smart-9d810b02-03b8-4ae1-a774-0d3f01bdc501
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475711912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.2475711912
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.2012222017
Short name T301
Test name
Test status
Simulation time 92341874 ps
CPU time 3.11 seconds
Started Jun 30 06:45:52 PM PDT 24
Finished Jun 30 06:45:56 PM PDT 24
Peak memory 218404 kb
Host smart-8e44ae8a-17dc-4d55-bc2b-8a7bf3da32ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012222017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.2012222017
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.233794861
Short name T75
Test name
Test status
Simulation time 579382835 ps
CPU time 21.21 seconds
Started Jun 30 06:45:54 PM PDT 24
Finished Jun 30 06:46:16 PM PDT 24
Peak memory 214996 kb
Host smart-85a8431a-30f3-4b50-896f-b7f2262bba0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233794861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.233794861
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.2064122909
Short name T761
Test name
Test status
Simulation time 278755698 ps
CPU time 12.11 seconds
Started Jun 30 06:46:00 PM PDT 24
Finished Jun 30 06:46:13 PM PDT 24
Peak memory 219104 kb
Host smart-ca6436f3-1a82-47fc-a6ba-0eab4e0ee15f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064122909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2064122909
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3863283879
Short name T650
Test name
Test status
Simulation time 5473802616 ps
CPU time 7.74 seconds
Started Jun 30 06:46:02 PM PDT 24
Finished Jun 30 06:46:11 PM PDT 24
Peak memory 218520 kb
Host smart-b0cd5ef2-9189-4ac8-9e1f-e45b68e7fa6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863283879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.3863283879
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.967535674
Short name T555
Test name
Test status
Simulation time 478921694 ps
CPU time 9.74 seconds
Started Jun 30 06:46:01 PM PDT 24
Finished Jun 30 06:46:12 PM PDT 24
Peak memory 226136 kb
Host smart-ed9fc199-f192-4dfc-a62c-d0e52c71127c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967535674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.967535674
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.2584021638
Short name T654
Test name
Test status
Simulation time 605286766 ps
CPU time 11.36 seconds
Started Jun 30 06:45:54 PM PDT 24
Finished Jun 30 06:46:06 PM PDT 24
Peak memory 226424 kb
Host smart-560e81ca-ead7-47c4-b64a-aba9c682269b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584021638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2584021638
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1024573158
Short name T387
Test name
Test status
Simulation time 116483309 ps
CPU time 3.06 seconds
Started Jun 30 06:45:55 PM PDT 24
Finished Jun 30 06:45:59 PM PDT 24
Peak memory 215188 kb
Host smart-1e255a1a-3c53-40f4-9f8b-de6cb677d8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024573158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1024573158
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.3069399718
Short name T702
Test name
Test status
Simulation time 1120912163 ps
CPU time 25.61 seconds
Started Jun 30 06:45:52 PM PDT 24
Finished Jun 30 06:46:18 PM PDT 24
Peak memory 251144 kb
Host smart-85c9ed9a-6dad-492a-b68a-b108091fac56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069399718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3069399718
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2362606514
Short name T727
Test name
Test status
Simulation time 1723969366 ps
CPU time 3.95 seconds
Started Jun 30 06:45:53 PM PDT 24
Finished Jun 30 06:45:58 PM PDT 24
Peak memory 222452 kb
Host smart-218e255a-e6a5-4c0a-a731-1820a84c8d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362606514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2362606514
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.3678502506
Short name T730
Test name
Test status
Simulation time 23757398974 ps
CPU time 224.68 seconds
Started Jun 30 06:45:58 PM PDT 24
Finished Jun 30 06:49:43 PM PDT 24
Peak memory 273392 kb
Host smart-6de5a822-8741-447b-9988-7dd21bd2345f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678502506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.3678502506
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1449860571
Short name T240
Test name
Test status
Simulation time 24664973 ps
CPU time 1.03 seconds
Started Jun 30 06:45:55 PM PDT 24
Finished Jun 30 06:45:57 PM PDT 24
Peak memory 212060 kb
Host smart-63890b2e-36a2-4647-bb6c-9003b83ff51f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449860571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.1449860571
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1341402378
Short name T414
Test name
Test status
Simulation time 22529154 ps
CPU time 1.26 seconds
Started Jun 30 06:45:59 PM PDT 24
Finished Jun 30 06:46:02 PM PDT 24
Peak memory 209308 kb
Host smart-ebfcbc4d-307b-4354-bd64-0fa13fc1efca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341402378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1341402378
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.3766665553
Short name T366
Test name
Test status
Simulation time 13854320315 ps
CPU time 24.97 seconds
Started Jun 30 06:46:02 PM PDT 24
Finished Jun 30 06:46:28 PM PDT 24
Peak memory 226312 kb
Host smart-c1863d0c-184d-4dee-be5c-bd04ce89c4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766665553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.3766665553
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1648176275
Short name T801
Test name
Test status
Simulation time 2789833246 ps
CPU time 5.07 seconds
Started Jun 30 06:45:58 PM PDT 24
Finished Jun 30 06:46:04 PM PDT 24
Peak memory 217860 kb
Host smart-eb7fbf06-d1f2-4786-88fd-febfbb65b41b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648176275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1648176275
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2904622385
Short name T297
Test name
Test status
Simulation time 11833574168 ps
CPU time 85.97 seconds
Started Jun 30 06:46:01 PM PDT 24
Finished Jun 30 06:47:28 PM PDT 24
Peak memory 226276 kb
Host smart-989b3934-1674-4496-ad19-8a9f697e5086
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904622385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2904622385
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1603701848
Short name T769
Test name
Test status
Simulation time 1623091455 ps
CPU time 5.31 seconds
Started Jun 30 06:45:58 PM PDT 24
Finished Jun 30 06:46:04 PM PDT 24
Peak memory 218424 kb
Host smart-9fc80247-e376-4534-8b6f-05985732646b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603701848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.1603701848
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3851795044
Short name T604
Test name
Test status
Simulation time 5543585714 ps
CPU time 28.69 seconds
Started Jun 30 06:46:02 PM PDT 24
Finished Jun 30 06:46:32 PM PDT 24
Peak memory 217976 kb
Host smart-1d91659f-5cc0-4a10-85a1-d52d06a02a8d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851795044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3851795044
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.2559482307
Short name T8
Test name
Test status
Simulation time 186508046 ps
CPU time 5.98 seconds
Started Jun 30 06:45:57 PM PDT 24
Finished Jun 30 06:46:03 PM PDT 24
Peak memory 217888 kb
Host smart-aa50e210-ffcd-4fca-af93-a8b20d4ec9bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559482307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
2559482307
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.782075126
Short name T648
Test name
Test status
Simulation time 1937757511 ps
CPU time 29.07 seconds
Started Jun 30 06:46:01 PM PDT 24
Finished Jun 30 06:46:32 PM PDT 24
Peak memory 250996 kb
Host smart-e7e33b97-1af5-4136-a900-3783098295e5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782075126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.782075126
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1424854306
Short name T856
Test name
Test status
Simulation time 710977608 ps
CPU time 26.36 seconds
Started Jun 30 06:46:02 PM PDT 24
Finished Jun 30 06:46:30 PM PDT 24
Peak memory 251076 kb
Host smart-2dedb1a4-23a5-4928-afa5-6b8a8e253c1e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424854306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1424854306
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.2724713965
Short name T524
Test name
Test status
Simulation time 153247231 ps
CPU time 2.43 seconds
Started Jun 30 06:45:59 PM PDT 24
Finished Jun 30 06:46:02 PM PDT 24
Peak memory 218424 kb
Host smart-c3f84e05-5f03-49ba-bcb5-7cee25a4a818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724713965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.2724713965
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2095859431
Short name T858
Test name
Test status
Simulation time 324357615 ps
CPU time 8.16 seconds
Started Jun 30 06:45:59 PM PDT 24
Finished Jun 30 06:46:09 PM PDT 24
Peak memory 218012 kb
Host smart-97d563ed-fe93-4dfc-b509-9763c995871d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095859431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2095859431
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.1081923529
Short name T79
Test name
Test status
Simulation time 1053575989 ps
CPU time 20.01 seconds
Started Jun 30 06:45:58 PM PDT 24
Finished Jun 30 06:46:19 PM PDT 24
Peak memory 268748 kb
Host smart-b3e15faf-ab4e-4409-804f-4b125974adbf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081923529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.1081923529
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.379390021
Short name T677
Test name
Test status
Simulation time 1070716064 ps
CPU time 8.34 seconds
Started Jun 30 06:46:01 PM PDT 24
Finished Jun 30 06:46:10 PM PDT 24
Peak memory 218476 kb
Host smart-e46292df-bedb-48d2-a7d0-ae8b54ca9c90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379390021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dig
est.379390021
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.1253463492
Short name T345
Test name
Test status
Simulation time 935981425 ps
CPU time 6.44 seconds
Started Jun 30 06:46:01 PM PDT 24
Finished Jun 30 06:46:09 PM PDT 24
Peak memory 218412 kb
Host smart-a9c9314c-eb64-419b-9b64-0d2587524033
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253463492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.1
253463492
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3611251540
Short name T583
Test name
Test status
Simulation time 213181354 ps
CPU time 8.58 seconds
Started Jun 30 06:46:00 PM PDT 24
Finished Jun 30 06:46:10 PM PDT 24
Peak memory 218392 kb
Host smart-112c23ee-3b2a-45a7-8bbb-eb3bffbfeef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611251540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3611251540
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.1557789063
Short name T377
Test name
Test status
Simulation time 33356817 ps
CPU time 2.18 seconds
Started Jun 30 06:45:57 PM PDT 24
Finished Jun 30 06:46:00 PM PDT 24
Peak memory 214440 kb
Host smart-5171973e-f570-41c7-a349-eedb7f8bbbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557789063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1557789063
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3411329396
Short name T260
Test name
Test status
Simulation time 324363130 ps
CPU time 18.67 seconds
Started Jun 30 06:45:58 PM PDT 24
Finished Jun 30 06:46:18 PM PDT 24
Peak memory 245900 kb
Host smart-381157fd-6bc5-4bdf-b4b6-15b3cea86649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411329396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3411329396
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.2959257020
Short name T659
Test name
Test status
Simulation time 723498941 ps
CPU time 7.46 seconds
Started Jun 30 06:46:00 PM PDT 24
Finished Jun 30 06:46:09 PM PDT 24
Peak memory 251068 kb
Host smart-0af9b2d3-ff87-45c8-9bf0-a8993652be96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959257020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2959257020
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.577818075
Short name T78
Test name
Test status
Simulation time 6373991478 ps
CPU time 92.64 seconds
Started Jun 30 06:45:59 PM PDT 24
Finished Jun 30 06:47:33 PM PDT 24
Peak memory 249432 kb
Host smart-5ff980d5-c5f5-438f-96e0-06d079e10409
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577818075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.577818075
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2232938115
Short name T408
Test name
Test status
Simulation time 20253473 ps
CPU time 1.02 seconds
Started Jun 30 06:45:58 PM PDT 24
Finished Jun 30 06:46:00 PM PDT 24
Peak memory 213276 kb
Host smart-16e1fbc6-d357-4b46-adbb-3a241334eaa9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232938115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2232938115
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.657974717
Short name T712
Test name
Test status
Simulation time 26483830 ps
CPU time 1.31 seconds
Started Jun 30 06:46:34 PM PDT 24
Finished Jun 30 06:46:37 PM PDT 24
Peak memory 209324 kb
Host smart-1d07d4c1-15f4-49a5-8d63-86abe3d39675
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657974717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.657974717
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.521799472
Short name T871
Test name
Test status
Simulation time 345663779 ps
CPU time 12.18 seconds
Started Jun 30 06:46:33 PM PDT 24
Finished Jun 30 06:46:46 PM PDT 24
Peak memory 218428 kb
Host smart-bb9b3b13-833e-4ee3-9715-b37d7b6d9249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521799472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.521799472
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.3573798390
Short name T831
Test name
Test status
Simulation time 669992664 ps
CPU time 4.36 seconds
Started Jun 30 06:46:38 PM PDT 24
Finished Jun 30 06:46:43 PM PDT 24
Peak memory 217312 kb
Host smart-bf2a8810-759b-4ff1-b9bc-2de9dea8e8c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573798390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.3573798390
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1182382947
Short name T537
Test name
Test status
Simulation time 14051385705 ps
CPU time 47.31 seconds
Started Jun 30 06:46:35 PM PDT 24
Finished Jun 30 06:47:23 PM PDT 24
Peak memory 226288 kb
Host smart-3f83ee4f-1cbf-41bc-a209-5971d54263af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182382947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1182382947
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3304544057
Short name T20
Test name
Test status
Simulation time 111145260 ps
CPU time 1.92 seconds
Started Jun 30 06:46:35 PM PDT 24
Finished Jun 30 06:46:38 PM PDT 24
Peak memory 221660 kb
Host smart-d90f5cc8-92ec-480d-9382-8ddd9c3f3bcb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304544057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.3304544057
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3997360144
Short name T242
Test name
Test status
Simulation time 249620302 ps
CPU time 2.4 seconds
Started Jun 30 06:46:34 PM PDT 24
Finished Jun 30 06:46:38 PM PDT 24
Peak memory 217884 kb
Host smart-a38d4051-55be-462e-9034-6f15dca03675
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997360144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.3997360144
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.641621812
Short name T707
Test name
Test status
Simulation time 1322858879 ps
CPU time 60.98 seconds
Started Jun 30 06:46:38 PM PDT 24
Finished Jun 30 06:47:39 PM PDT 24
Peak memory 267524 kb
Host smart-b22c64e8-9f07-4f4e-86cf-637467a01472
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641621812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_state_failure.641621812
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2149300719
Short name T862
Test name
Test status
Simulation time 897416101 ps
CPU time 13.93 seconds
Started Jun 30 06:46:36 PM PDT 24
Finished Jun 30 06:46:51 PM PDT 24
Peak memory 226556 kb
Host smart-4ed720ad-162d-4102-b3d3-609b279593e7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149300719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.2149300719
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2654643229
Short name T500
Test name
Test status
Simulation time 58540001 ps
CPU time 2.6 seconds
Started Jun 30 06:46:35 PM PDT 24
Finished Jun 30 06:46:38 PM PDT 24
Peak memory 218440 kb
Host smart-fd05e3ce-2c6f-4077-adfb-807a8eac4857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654643229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2654643229
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.1995724801
Short name T267
Test name
Test status
Simulation time 1105113522 ps
CPU time 9.19 seconds
Started Jun 30 06:46:38 PM PDT 24
Finished Jun 30 06:46:48 PM PDT 24
Peak memory 226252 kb
Host smart-d95444a2-7c8f-4b41-b684-e61fd86f615e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995724801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.1995724801
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1057817874
Short name T594
Test name
Test status
Simulation time 1203462552 ps
CPU time 7.95 seconds
Started Jun 30 06:46:33 PM PDT 24
Finished Jun 30 06:46:41 PM PDT 24
Peak memory 218536 kb
Host smart-531fe354-6bb2-4aa0-a8d5-ce2d5fa334f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057817874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1057817874
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2705591346
Short name T533
Test name
Test status
Simulation time 2040756205 ps
CPU time 9.67 seconds
Started Jun 30 06:46:34 PM PDT 24
Finished Jun 30 06:46:45 PM PDT 24
Peak memory 218404 kb
Host smart-7c1210cd-915b-4e45-b54e-b00b0b92278e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705591346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
2705591346
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1449857074
Short name T839
Test name
Test status
Simulation time 884125840 ps
CPU time 8.97 seconds
Started Jun 30 06:46:34 PM PDT 24
Finished Jun 30 06:46:44 PM PDT 24
Peak memory 226548 kb
Host smart-1f6e686c-5895-4537-8ad5-1ed3b04b911b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449857074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1449857074
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3561119753
Short name T827
Test name
Test status
Simulation time 360254793 ps
CPU time 3.03 seconds
Started Jun 30 06:46:33 PM PDT 24
Finished Jun 30 06:46:36 PM PDT 24
Peak memory 217892 kb
Host smart-6028fc1e-31ec-471d-8572-48fa53be3bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561119753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3561119753
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.202716786
Short name T553
Test name
Test status
Simulation time 926980939 ps
CPU time 35.04 seconds
Started Jun 30 06:46:36 PM PDT 24
Finished Jun 30 06:47:12 PM PDT 24
Peak memory 247408 kb
Host smart-e37e74a1-e717-4f21-831f-df1de404eed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202716786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.202716786
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.790435548
Short name T728
Test name
Test status
Simulation time 59887973 ps
CPU time 5.94 seconds
Started Jun 30 06:46:37 PM PDT 24
Finished Jun 30 06:46:43 PM PDT 24
Peak memory 246980 kb
Host smart-535829b4-cf60-4a2a-b31f-80c4b4512e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790435548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.790435548
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.577279783
Short name T33
Test name
Test status
Simulation time 2536640350 ps
CPU time 43.18 seconds
Started Jun 30 06:46:36 PM PDT 24
Finished Jun 30 06:47:19 PM PDT 24
Peak memory 226172 kb
Host smart-b097018c-1ac1-4615-a0cf-cd7f9601b0a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577279783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.577279783
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3279730191
Short name T850
Test name
Test status
Simulation time 46084622 ps
CPU time 0.97 seconds
Started Jun 30 06:46:35 PM PDT 24
Finished Jun 30 06:46:37 PM PDT 24
Peak memory 212056 kb
Host smart-066f2cfd-e104-4065-8faf-b730226d64f2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279730191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3279730191
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.391240998
Short name T800
Test name
Test status
Simulation time 16106531 ps
CPU time 0.92 seconds
Started Jun 30 06:46:39 PM PDT 24
Finished Jun 30 06:46:41 PM PDT 24
Peak memory 209180 kb
Host smart-40c72cbd-b369-4f6b-966e-b0fcb7d3b461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391240998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.391240998
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.365017937
Short name T268
Test name
Test status
Simulation time 1325861019 ps
CPU time 16.17 seconds
Started Jun 30 06:46:34 PM PDT 24
Finished Jun 30 06:46:52 PM PDT 24
Peak memory 218316 kb
Host smart-ba5ff9d3-8118-4610-b955-9f9beb52dc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365017937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.365017937
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.3373407497
Short name T87
Test name
Test status
Simulation time 695547713 ps
CPU time 2.48 seconds
Started Jun 30 06:46:31 PM PDT 24
Finished Jun 30 06:46:34 PM PDT 24
Peak memory 217288 kb
Host smart-afa8ed7d-00bd-4110-9101-21f4ff04664b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373407497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.3373407497
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2731728985
Short name T686
Test name
Test status
Simulation time 3338606692 ps
CPU time 44.87 seconds
Started Jun 30 06:46:34 PM PDT 24
Finished Jun 30 06:47:20 PM PDT 24
Peak memory 218416 kb
Host smart-5dba6e3f-d869-44fa-a654-0422fe02633d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731728985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2731728985
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.652772873
Short name T814
Test name
Test status
Simulation time 398711847 ps
CPU time 3.66 seconds
Started Jun 30 06:46:36 PM PDT 24
Finished Jun 30 06:46:40 PM PDT 24
Peak memory 218296 kb
Host smart-1622ce85-5be3-4aef-b9dd-c70ab152a696
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652772873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_prog_failure.652772873
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3677566456
Short name T330
Test name
Test status
Simulation time 1043037076 ps
CPU time 5.13 seconds
Started Jun 30 06:46:34 PM PDT 24
Finished Jun 30 06:46:41 PM PDT 24
Peak memory 217884 kb
Host smart-01396b5c-7f45-4c84-a97d-c72e30766345
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677566456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.3677566456
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2108450793
Short name T85
Test name
Test status
Simulation time 1983143853 ps
CPU time 43.96 seconds
Started Jun 30 06:46:37 PM PDT 24
Finished Jun 30 06:47:22 PM PDT 24
Peak memory 278388 kb
Host smart-f7a3d78f-84bd-4755-9a51-94c5e29c9d1b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108450793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.2108450793
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.738208363
Short name T625
Test name
Test status
Simulation time 659926898 ps
CPU time 14.35 seconds
Started Jun 30 06:46:37 PM PDT 24
Finished Jun 30 06:46:52 PM PDT 24
Peak memory 251120 kb
Host smart-309b1c4c-0640-45f1-b12e-d805f2f9ea42
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738208363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_
jtag_state_post_trans.738208363
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2078953033
Short name T466
Test name
Test status
Simulation time 243421372 ps
CPU time 2.16 seconds
Started Jun 30 06:46:38 PM PDT 24
Finished Jun 30 06:46:40 PM PDT 24
Peak memory 222244 kb
Host smart-e29eb692-7e79-4dd4-ab3d-43665de588f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078953033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2078953033
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.17963380
Short name T461
Test name
Test status
Simulation time 3290887583 ps
CPU time 17.65 seconds
Started Jun 30 06:46:37 PM PDT 24
Finished Jun 30 06:46:55 PM PDT 24
Peak memory 226252 kb
Host smart-9d441e3d-d990-4aac-a6df-a9074e3132ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17963380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.17963380
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3282814437
Short name T388
Test name
Test status
Simulation time 1241106361 ps
CPU time 8.76 seconds
Started Jun 30 06:46:41 PM PDT 24
Finished Jun 30 06:46:50 PM PDT 24
Peak memory 218440 kb
Host smart-7b35d9c0-5645-4af3-b8eb-1c0be04520ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282814437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.3282814437
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1294019748
Short name T683
Test name
Test status
Simulation time 291374656 ps
CPU time 6.76 seconds
Started Jun 30 06:46:41 PM PDT 24
Finished Jun 30 06:46:48 PM PDT 24
Peak memory 218448 kb
Host smart-b3d83212-34e3-40c4-b5e9-bda50167735e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294019748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
1294019748
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.225791122
Short name T796
Test name
Test status
Simulation time 290400964 ps
CPU time 10.7 seconds
Started Jun 30 06:46:34 PM PDT 24
Finished Jun 30 06:46:45 PM PDT 24
Peak memory 218496 kb
Host smart-3a3c8f51-7776-42e5-8e4a-0535e5ce893b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225791122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.225791122
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.1960256756
Short name T579
Test name
Test status
Simulation time 77004174 ps
CPU time 1.32 seconds
Started Jun 30 06:46:35 PM PDT 24
Finished Jun 30 06:46:37 PM PDT 24
Peak memory 217912 kb
Host smart-7dff0e21-a4b9-4c61-b2f1-6d30a76044ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960256756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.1960256756
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1030098187
Short name T314
Test name
Test status
Simulation time 368136330 ps
CPU time 17.28 seconds
Started Jun 30 06:46:37 PM PDT 24
Finished Jun 30 06:46:55 PM PDT 24
Peak memory 251112 kb
Host smart-39090226-a1be-49f3-afd5-618818e3b867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030098187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1030098187
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1131681789
Short name T396
Test name
Test status
Simulation time 12079041 ps
CPU time 0.9 seconds
Started Jun 30 06:46:35 PM PDT 24
Finished Jun 30 06:46:37 PM PDT 24
Peak memory 212104 kb
Host smart-16bf4757-bab4-4165-8921-b7b329f75132
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131681789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.1131681789
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3828897699
Short name T658
Test name
Test status
Simulation time 18825133 ps
CPU time 1.15 seconds
Started Jun 30 06:46:47 PM PDT 24
Finished Jun 30 06:46:49 PM PDT 24
Peak memory 209168 kb
Host smart-7a5a05c0-2d3e-434a-a06d-e4ac2e1641c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828897699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3828897699
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1417858898
Short name T427
Test name
Test status
Simulation time 337972950 ps
CPU time 11.22 seconds
Started Jun 30 06:46:40 PM PDT 24
Finished Jun 30 06:46:52 PM PDT 24
Peak memory 218568 kb
Host smart-a6157cd6-a3d6-41a4-a85c-f38b74b54145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417858898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1417858898
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.98469553
Short name T28
Test name
Test status
Simulation time 224137033 ps
CPU time 6.61 seconds
Started Jun 30 06:46:48 PM PDT 24
Finished Jun 30 06:46:55 PM PDT 24
Peak memory 217496 kb
Host smart-047d3b5c-cf94-40b9-970e-ba759c74b9b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98469553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.98469553
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3289423780
Short name T595
Test name
Test status
Simulation time 7877116275 ps
CPU time 53.85 seconds
Started Jun 30 06:46:46 PM PDT 24
Finished Jun 30 06:47:41 PM PDT 24
Peak memory 219112 kb
Host smart-7eb86303-d551-4322-8576-61e1a2bd1ea3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289423780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3289423780
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1553647431
Short name T581
Test name
Test status
Simulation time 1767292058 ps
CPU time 12.85 seconds
Started Jun 30 06:46:40 PM PDT 24
Finished Jun 30 06:46:53 PM PDT 24
Peak memory 224248 kb
Host smart-02e21d10-2cd7-40d8-8ece-e188f7d4209f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553647431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1553647431
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.539621000
Short name T376
Test name
Test status
Simulation time 119081009 ps
CPU time 4.3 seconds
Started Jun 30 06:46:39 PM PDT 24
Finished Jun 30 06:46:44 PM PDT 24
Peak memory 217908 kb
Host smart-c96ab924-af55-4c03-a988-23fe0da1a97e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539621000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke.
539621000
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.87939426
Short name T283
Test name
Test status
Simulation time 2183976179 ps
CPU time 79.26 seconds
Started Jun 30 06:46:40 PM PDT 24
Finished Jun 30 06:47:59 PM PDT 24
Peak memory 267580 kb
Host smart-30ca0626-6892-459e-917c-2046ff40ff79
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87939426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag
_state_failure.87939426
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1736740392
Short name T851
Test name
Test status
Simulation time 385965760 ps
CPU time 18.29 seconds
Started Jun 30 06:46:42 PM PDT 24
Finished Jun 30 06:47:00 PM PDT 24
Peak memory 251104 kb
Host smart-c1791a9a-4e38-4a5d-98aa-b94ea0a6cacf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736740392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.1736740392
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1679949815
Short name T225
Test name
Test status
Simulation time 172640134 ps
CPU time 2.68 seconds
Started Jun 30 06:46:39 PM PDT 24
Finished Jun 30 06:46:42 PM PDT 24
Peak memory 218424 kb
Host smart-89b271a3-f84a-4f12-9127-7e57ac860f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679949815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1679949815
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.1915518073
Short name T630
Test name
Test status
Simulation time 448636712 ps
CPU time 20.31 seconds
Started Jun 30 06:46:47 PM PDT 24
Finished Jun 30 06:47:09 PM PDT 24
Peak memory 219276 kb
Host smart-42edd645-0bda-4e03-ba8c-5366e4615145
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915518073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1915518073
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1085398143
Short name T360
Test name
Test status
Simulation time 776053279 ps
CPU time 12.05 seconds
Started Jun 30 06:46:45 PM PDT 24
Finished Jun 30 06:46:58 PM PDT 24
Peak memory 218700 kb
Host smart-0d12ceb5-5913-42e2-80b2-73be968e6be3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085398143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1085398143
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.2675775574
Short name T647
Test name
Test status
Simulation time 939249663 ps
CPU time 9.1 seconds
Started Jun 30 06:46:45 PM PDT 24
Finished Jun 30 06:46:55 PM PDT 24
Peak memory 218356 kb
Host smart-aed9dd33-a4c6-476a-833e-042de929f795
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675775574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
2675775574
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.4102889052
Short name T731
Test name
Test status
Simulation time 1112900625 ps
CPU time 7.72 seconds
Started Jun 30 06:46:37 PM PDT 24
Finished Jun 30 06:46:46 PM PDT 24
Peak memory 218528 kb
Host smart-3907b9a7-177a-4959-aa42-c0f8dffd69b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102889052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.4102889052
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.110303955
Short name T72
Test name
Test status
Simulation time 48618175 ps
CPU time 1.26 seconds
Started Jun 30 06:46:40 PM PDT 24
Finished Jun 30 06:46:41 PM PDT 24
Peak memory 213984 kb
Host smart-20c6e8c3-d5fc-4f15-bd98-a970f94852f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110303955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.110303955
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2056783979
Short name T840
Test name
Test status
Simulation time 984786009 ps
CPU time 34.64 seconds
Started Jun 30 06:46:39 PM PDT 24
Finished Jun 30 06:47:14 PM PDT 24
Peak memory 251136 kb
Host smart-27294bdb-428f-4a47-a264-07a23c461d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056783979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2056783979
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.1334480060
Short name T597
Test name
Test status
Simulation time 59584474 ps
CPU time 2.91 seconds
Started Jun 30 06:46:39 PM PDT 24
Finished Jun 30 06:46:42 PM PDT 24
Peak memory 224504 kb
Host smart-4cf68c4c-9377-4cad-96be-60de0bc3f28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334480060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1334480060
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.3479703377
Short name T528
Test name
Test status
Simulation time 11884662730 ps
CPU time 58.16 seconds
Started Jun 30 06:46:46 PM PDT 24
Finished Jun 30 06:47:45 PM PDT 24
Peak memory 251164 kb
Host smart-7e4cbd0c-1d22-4b0b-a53c-66755b3e5777
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479703377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.3479703377
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3427193682
Short name T624
Test name
Test status
Simulation time 13059075 ps
CPU time 0.86 seconds
Started Jun 30 06:46:39 PM PDT 24
Finished Jun 30 06:46:40 PM PDT 24
Peak memory 212104 kb
Host smart-d2bfd1ae-715c-403a-b2a5-a4f8eac6492d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427193682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3427193682
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.62198928
Short name T572
Test name
Test status
Simulation time 83193168 ps
CPU time 1.65 seconds
Started Jun 30 06:46:47 PM PDT 24
Finished Jun 30 06:46:50 PM PDT 24
Peak memory 209272 kb
Host smart-ae44dfaa-2899-4368-a9fc-a0c95506479c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62198928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.62198928
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1184313405
Short name T312
Test name
Test status
Simulation time 306506577 ps
CPU time 11.89 seconds
Started Jun 30 06:46:46 PM PDT 24
Finished Jun 30 06:46:59 PM PDT 24
Peak memory 226200 kb
Host smart-079783af-0147-4f1a-ad4d-359385a2a37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184313405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1184313405
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.4076077499
Short name T531
Test name
Test status
Simulation time 3098675757 ps
CPU time 5.53 seconds
Started Jun 30 06:46:53 PM PDT 24
Finished Jun 30 06:46:59 PM PDT 24
Peak memory 217996 kb
Host smart-1c53c452-e6a3-4502-a6e6-ca95f088337d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076077499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.4076077499
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.2421667284
Short name T620
Test name
Test status
Simulation time 3416192499 ps
CPU time 50.13 seconds
Started Jun 30 06:46:46 PM PDT 24
Finished Jun 30 06:47:36 PM PDT 24
Peak memory 220112 kb
Host smart-a79fa309-e232-4a62-9b59-427a52abeef2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421667284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.2421667284
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.3444040435
Short name T590
Test name
Test status
Simulation time 323752591 ps
CPU time 10.66 seconds
Started Jun 30 06:46:47 PM PDT 24
Finished Jun 30 06:46:59 PM PDT 24
Peak memory 223344 kb
Host smart-1a745923-78a4-4572-a27a-555ae15f750c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444040435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.3444040435
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.937082754
Short name T854
Test name
Test status
Simulation time 1314967520 ps
CPU time 9.45 seconds
Started Jun 30 06:46:47 PM PDT 24
Finished Jun 30 06:46:58 PM PDT 24
Peak memory 217920 kb
Host smart-35fd9af2-6b09-4460-9cbf-0e49b3450cc8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937082754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.
937082754
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2654415666
Short name T460
Test name
Test status
Simulation time 4082840430 ps
CPU time 38.99 seconds
Started Jun 30 06:46:47 PM PDT 24
Finished Jun 30 06:47:28 PM PDT 24
Peak memory 251184 kb
Host smart-a1d461e6-940b-451c-84d7-b7daf484c87e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654415666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2654415666
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.2432001664
Short name T847
Test name
Test status
Simulation time 1478058164 ps
CPU time 10.5 seconds
Started Jun 30 06:46:49 PM PDT 24
Finished Jun 30 06:47:00 PM PDT 24
Peak memory 249684 kb
Host smart-08c7bd24-7a1b-4d5b-a505-4ce3e8261cd8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432001664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.2432001664
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.2374752
Short name T489
Test name
Test status
Simulation time 69979912 ps
CPU time 2.98 seconds
Started Jun 30 06:46:47 PM PDT 24
Finished Jun 30 06:46:52 PM PDT 24
Peak memory 222800 kb
Host smart-f1ebcbf5-ce32-4dde-bbd0-41d21b60e252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.2374752
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.2065216416
Short name T335
Test name
Test status
Simulation time 2370457294 ps
CPU time 14.12 seconds
Started Jun 30 06:46:47 PM PDT 24
Finished Jun 30 06:47:02 PM PDT 24
Peak memory 226296 kb
Host smart-e0b06320-45b2-4e14-8ebb-f2e3e00abae0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065216416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.2065216416
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3977513318
Short name T2
Test name
Test status
Simulation time 911348805 ps
CPU time 10.58 seconds
Started Jun 30 06:46:50 PM PDT 24
Finished Jun 30 06:47:01 PM PDT 24
Peak memory 218436 kb
Host smart-ea93b805-8f24-4987-8872-3b85a6522917
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977513318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.3977513318
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1749915604
Short name T777
Test name
Test status
Simulation time 281236440 ps
CPU time 6.41 seconds
Started Jun 30 06:46:47 PM PDT 24
Finished Jun 30 06:46:54 PM PDT 24
Peak memory 218420 kb
Host smart-b01bc9f1-d4c2-4893-bb46-b7d6b55eaf5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749915604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1749915604
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.95952583
Short name T627
Test name
Test status
Simulation time 709389955 ps
CPU time 7.2 seconds
Started Jun 30 06:46:48 PM PDT 24
Finished Jun 30 06:46:56 PM PDT 24
Peak memory 218548 kb
Host smart-ffb9901c-5222-46d5-914f-480f0bba58ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95952583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.95952583
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.251876952
Short name T584
Test name
Test status
Simulation time 164807748 ps
CPU time 1.84 seconds
Started Jun 30 06:46:46 PM PDT 24
Finished Jun 30 06:46:48 PM PDT 24
Peak memory 214076 kb
Host smart-33fd85ba-bfa6-410d-8722-90ee791548bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251876952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.251876952
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.1308546539
Short name T809
Test name
Test status
Simulation time 986313519 ps
CPU time 32.28 seconds
Started Jun 30 06:46:45 PM PDT 24
Finished Jun 30 06:47:18 PM PDT 24
Peak memory 251144 kb
Host smart-977f62b0-3c6d-4019-b75c-62dc414d38be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308546539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.1308546539
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1382248291
Short name T468
Test name
Test status
Simulation time 299023341 ps
CPU time 6.92 seconds
Started Jun 30 06:46:50 PM PDT 24
Finished Jun 30 06:46:58 PM PDT 24
Peak memory 250680 kb
Host smart-c2609650-caa1-41cd-8de1-8d1a8a20d933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382248291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1382248291
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3087787416
Short name T857
Test name
Test status
Simulation time 22816819990 ps
CPU time 126.49 seconds
Started Jun 30 06:46:47 PM PDT 24
Finished Jun 30 06:48:55 PM PDT 24
Peak memory 226292 kb
Host smart-55b5a63f-557e-410e-991c-56decfae4c4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087787416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3087787416
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.716193665
Short name T804
Test name
Test status
Simulation time 78659659088 ps
CPU time 1127.82 seconds
Started Jun 30 06:46:47 PM PDT 24
Finished Jun 30 07:05:35 PM PDT 24
Peak memory 284132 kb
Host smart-96c9b84d-a144-4f93-abbc-f637ecbf4e9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=716193665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.716193665
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.4096631278
Short name T824
Test name
Test status
Simulation time 17016756 ps
CPU time 0.85 seconds
Started Jun 30 06:46:47 PM PDT 24
Finished Jun 30 06:46:48 PM PDT 24
Peak memory 212132 kb
Host smart-43c22e08-8c82-4753-bfa0-d52beb712d82
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096631278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.4096631278
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2322245746
Short name T418
Test name
Test status
Simulation time 125749366 ps
CPU time 1.05 seconds
Started Jun 30 06:46:51 PM PDT 24
Finished Jun 30 06:46:53 PM PDT 24
Peak memory 209100 kb
Host smart-045b1746-ed9b-443d-8d00-8f6ac696598f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322245746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2322245746
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.1267867977
Short name T643
Test name
Test status
Simulation time 2239778121 ps
CPU time 13.87 seconds
Started Jun 30 06:46:49 PM PDT 24
Finished Jun 30 06:47:03 PM PDT 24
Peak memory 226324 kb
Host smart-7705cc29-3d56-4d47-8d8e-19bb934a08ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267867977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1267867977
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.543881333
Short name T564
Test name
Test status
Simulation time 75537820 ps
CPU time 1.69 seconds
Started Jun 30 06:47:07 PM PDT 24
Finished Jun 30 06:47:10 PM PDT 24
Peak memory 217280 kb
Host smart-69f4763d-5c32-4f19-9183-ba2f08df8591
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543881333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.543881333
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.26026205
Short name T379
Test name
Test status
Simulation time 3813198819 ps
CPU time 49.44 seconds
Started Jun 30 06:46:54 PM PDT 24
Finished Jun 30 06:47:45 PM PDT 24
Peak memory 218396 kb
Host smart-cd6b34b8-7c08-4bd1-8bfb-1aa37c22b403
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26026205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_err
ors.26026205
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2453571724
Short name T425
Test name
Test status
Simulation time 660729583 ps
CPU time 17.75 seconds
Started Jun 30 06:46:54 PM PDT 24
Finished Jun 30 06:47:13 PM PDT 24
Peak memory 218408 kb
Host smart-f6b964da-8aa9-4f97-aab8-ab52bbec4b27
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453571724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2453571724
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1687291025
Short name T292
Test name
Test status
Simulation time 121725395 ps
CPU time 4.32 seconds
Started Jun 30 06:46:47 PM PDT 24
Finished Jun 30 06:46:53 PM PDT 24
Peak memory 217924 kb
Host smart-e30c5e24-6233-4a42-a12f-5972263d9784
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687291025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1687291025
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.1516530788
Short name T293
Test name
Test status
Simulation time 2065298032 ps
CPU time 79.66 seconds
Started Jun 30 06:46:53 PM PDT 24
Finished Jun 30 06:48:13 PM PDT 24
Peak memory 279436 kb
Host smart-6c812208-2b62-4132-9c59-eb982a7f9f16
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516530788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.1516530788
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2462568160
Short name T359
Test name
Test status
Simulation time 1354587642 ps
CPU time 10.51 seconds
Started Jun 30 06:47:09 PM PDT 24
Finished Jun 30 06:47:21 PM PDT 24
Peak memory 250696 kb
Host smart-c7d36815-dcf3-457f-817e-1d422c8e1bc0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462568160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.2462568160
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2076568519
Short name T449
Test name
Test status
Simulation time 66255970 ps
CPU time 2.69 seconds
Started Jun 30 06:46:48 PM PDT 24
Finished Jun 30 06:46:51 PM PDT 24
Peak memory 218340 kb
Host smart-a4b8b587-6ce1-48a1-8b70-3d2a864db353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076568519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2076568519
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.1058323232
Short name T714
Test name
Test status
Simulation time 947657893 ps
CPU time 24.57 seconds
Started Jun 30 06:46:53 PM PDT 24
Finished Jun 30 06:47:18 PM PDT 24
Peak memory 226228 kb
Host smart-dd0cb89d-27ea-4b85-a096-353fc39fc8c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058323232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1058323232
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1618030636
Short name T566
Test name
Test status
Simulation time 5735353490 ps
CPU time 13.85 seconds
Started Jun 30 06:46:51 PM PDT 24
Finished Jun 30 06:47:06 PM PDT 24
Peak memory 218568 kb
Host smart-407ac2f7-1c57-41f1-a921-f320e020e9b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618030636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.1618030636
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.330786929
Short name T813
Test name
Test status
Simulation time 1564612024 ps
CPU time 6.32 seconds
Started Jun 30 06:47:09 PM PDT 24
Finished Jun 30 06:47:17 PM PDT 24
Peak memory 218436 kb
Host smart-cb0f15a0-099e-44b3-b0a4-e60112baa59f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330786929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.330786929
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1690501151
Short name T788
Test name
Test status
Simulation time 1233705350 ps
CPU time 13.05 seconds
Started Jun 30 06:46:48 PM PDT 24
Finished Jun 30 06:47:02 PM PDT 24
Peak memory 218512 kb
Host smart-5b9b26a8-c2ca-4b46-9606-b2a7dea97adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690501151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1690501151
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1551450768
Short name T218
Test name
Test status
Simulation time 708260602 ps
CPU time 3.55 seconds
Started Jun 30 06:46:46 PM PDT 24
Finished Jun 30 06:46:50 PM PDT 24
Peak memory 217904 kb
Host smart-d7ce3c66-377b-473d-b86a-7130001ccd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551450768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1551450768
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2947384747
Short name T663
Test name
Test status
Simulation time 204781959 ps
CPU time 21.05 seconds
Started Jun 30 06:46:46 PM PDT 24
Finished Jun 30 06:47:08 PM PDT 24
Peak memory 246632 kb
Host smart-7c5c44ac-9ec9-4dd9-8a1d-b1605420925a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947384747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2947384747
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.3317929610
Short name T475
Test name
Test status
Simulation time 109457909 ps
CPU time 9.7 seconds
Started Jun 30 06:46:50 PM PDT 24
Finished Jun 30 06:47:00 PM PDT 24
Peak memory 251112 kb
Host smart-735e7a7e-074e-459c-bd59-f32b5d559ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317929610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3317929610
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.3907772843
Short name T512
Test name
Test status
Simulation time 12110534323 ps
CPU time 385.23 seconds
Started Jun 30 06:46:52 PM PDT 24
Finished Jun 30 06:53:17 PM PDT 24
Peak memory 283964 kb
Host smart-8e37c5d0-71f9-4a57-9d73-81fdf19a8580
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907772843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.3907772843
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.853694252
Short name T1
Test name
Test status
Simulation time 13271340 ps
CPU time 1.05 seconds
Started Jun 30 06:46:52 PM PDT 24
Finished Jun 30 06:46:53 PM PDT 24
Peak memory 212020 kb
Host smart-a0f5005a-a84d-49a9-9cc1-6562a31a47a4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853694252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ct
rl_volatile_unlock_smoke.853694252
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.859774912
Short name T492
Test name
Test status
Simulation time 53749230 ps
CPU time 1.29 seconds
Started Jun 30 06:46:52 PM PDT 24
Finished Jun 30 06:46:54 PM PDT 24
Peak memory 209152 kb
Host smart-23999be5-0dbf-45d4-8cff-260fe48b3047
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859774912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.859774912
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.3482367438
Short name T536
Test name
Test status
Simulation time 394242127 ps
CPU time 12.57 seconds
Started Jun 30 06:46:52 PM PDT 24
Finished Jun 30 06:47:05 PM PDT 24
Peak memory 218352 kb
Host smart-5d2182c9-361c-45e9-9ebf-4d83aa9022bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482367438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.3482367438
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.415350675
Short name T24
Test name
Test status
Simulation time 593544305 ps
CPU time 3.82 seconds
Started Jun 30 06:47:09 PM PDT 24
Finished Jun 30 06:47:14 PM PDT 24
Peak memory 217432 kb
Host smart-d4c7ab5c-b55f-41fd-9067-6822a2faf53b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415350675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.415350675
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.3496560207
Short name T837
Test name
Test status
Simulation time 5539867890 ps
CPU time 29.01 seconds
Started Jun 30 06:46:54 PM PDT 24
Finished Jun 30 06:47:23 PM PDT 24
Peak memory 219128 kb
Host smart-245146ff-aec6-4e4f-a0fe-a7ec5f70d063
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496560207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.3496560207
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2691838701
Short name T870
Test name
Test status
Simulation time 848647735 ps
CPU time 10.5 seconds
Started Jun 30 06:47:09 PM PDT 24
Finished Jun 30 06:47:21 PM PDT 24
Peak memory 218424 kb
Host smart-6822b28f-3245-4fb8-b990-49aa8153e78f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691838701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.2691838701
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.700565898
Short name T67
Test name
Test status
Simulation time 220358334 ps
CPU time 3.4 seconds
Started Jun 30 06:47:09 PM PDT 24
Finished Jun 30 06:47:14 PM PDT 24
Peak memory 217948 kb
Host smart-53d1c644-8396-47a3-815b-4cdb64c5ee16
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700565898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke.
700565898
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2799706565
Short name T453
Test name
Test status
Simulation time 4703998031 ps
CPU time 50.81 seconds
Started Jun 30 06:46:52 PM PDT 24
Finished Jun 30 06:47:43 PM PDT 24
Peak memory 283520 kb
Host smart-5993a17b-9d16-4334-a0a3-266c650ebbe4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799706565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.2799706565
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1345856656
Short name T435
Test name
Test status
Simulation time 723821717 ps
CPU time 15.48 seconds
Started Jun 30 06:46:54 PM PDT 24
Finished Jun 30 06:47:10 PM PDT 24
Peak memory 250340 kb
Host smart-ff18be65-1dcd-4880-890f-a5c85999682c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345856656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.1345856656
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.3309700043
Short name T545
Test name
Test status
Simulation time 307922540 ps
CPU time 3.51 seconds
Started Jun 30 06:46:53 PM PDT 24
Finished Jun 30 06:46:56 PM PDT 24
Peak memory 218440 kb
Host smart-85f883f3-e47f-4688-9f88-f583299cc979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309700043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.3309700043
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.1144108623
Short name T832
Test name
Test status
Simulation time 1028463493 ps
CPU time 15 seconds
Started Jun 30 06:47:07 PM PDT 24
Finished Jun 30 06:47:23 PM PDT 24
Peak memory 226248 kb
Host smart-f400b082-8cdb-4455-81e0-c09b4c0c8b3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144108623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1144108623
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.3390486094
Short name T300
Test name
Test status
Simulation time 610325538 ps
CPU time 11.57 seconds
Started Jun 30 06:46:53 PM PDT 24
Finished Jun 30 06:47:05 PM PDT 24
Peak memory 218484 kb
Host smart-28beacfe-b163-4a8c-a233-d4f3728b4c2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390486094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.3390486094
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.342065758
Short name T638
Test name
Test status
Simulation time 912116119 ps
CPU time 7.6 seconds
Started Jun 30 06:47:07 PM PDT 24
Finished Jun 30 06:47:16 PM PDT 24
Peak memory 218436 kb
Host smart-2c90c859-1e54-4432-a45b-339e1e442e22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342065758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.342065758
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2579513122
Short name T141
Test name
Test status
Simulation time 358126067 ps
CPU time 8.7 seconds
Started Jun 30 06:46:54 PM PDT 24
Finished Jun 30 06:47:03 PM PDT 24
Peak memory 218516 kb
Host smart-119568ee-2de6-464d-9345-9c15200c6a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579513122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2579513122
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.77605691
Short name T365
Test name
Test status
Simulation time 149566722 ps
CPU time 2.53 seconds
Started Jun 30 06:47:08 PM PDT 24
Finished Jun 30 06:47:11 PM PDT 24
Peak memory 217936 kb
Host smart-27ca1216-4278-4739-a3d6-0171c4a40d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77605691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.77605691
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.482146969
Short name T353
Test name
Test status
Simulation time 302155805 ps
CPU time 20.82 seconds
Started Jun 30 06:46:54 PM PDT 24
Finished Jun 30 06:47:15 PM PDT 24
Peak memory 251112 kb
Host smart-02667008-129a-4e0e-9dcf-5db48fb14422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482146969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.482146969
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.947563370
Short name T328
Test name
Test status
Simulation time 80757921 ps
CPU time 8.52 seconds
Started Jun 30 06:46:51 PM PDT 24
Finished Jun 30 06:46:59 PM PDT 24
Peak memory 251044 kb
Host smart-03db18a0-ad58-4fb3-b809-ce21cf4f52e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947563370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.947563370
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.1480904059
Short name T400
Test name
Test status
Simulation time 3181299929 ps
CPU time 107.48 seconds
Started Jun 30 06:46:54 PM PDT 24
Finished Jun 30 06:48:42 PM PDT 24
Peak memory 251196 kb
Host smart-fa779279-3517-4738-8539-07a0a7aaa007
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480904059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.1480904059
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3226638425
Short name T818
Test name
Test status
Simulation time 32206382 ps
CPU time 0.86 seconds
Started Jun 30 06:46:51 PM PDT 24
Finished Jun 30 06:46:53 PM PDT 24
Peak memory 212072 kb
Host smart-2c35dff4-8d9d-460f-a1e9-c8831d3256a2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226638425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.3226638425
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.1004020508
Short name T459
Test name
Test status
Simulation time 91562930 ps
CPU time 1.12 seconds
Started Jun 30 06:47:00 PM PDT 24
Finished Jun 30 06:47:02 PM PDT 24
Peak memory 209180 kb
Host smart-eee96777-43ae-4395-9af0-49e148b7a45c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004020508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.1004020508
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.261634315
Short name T222
Test name
Test status
Simulation time 627067760 ps
CPU time 14.43 seconds
Started Jun 30 06:46:58 PM PDT 24
Finished Jun 30 06:47:13 PM PDT 24
Peak memory 226196 kb
Host smart-35e8bdd0-a11b-4e40-8424-6fadce5f7a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261634315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.261634315
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.2122450726
Short name T822
Test name
Test status
Simulation time 4177215871 ps
CPU time 8.97 seconds
Started Jun 30 06:47:03 PM PDT 24
Finished Jun 30 06:47:13 PM PDT 24
Peak memory 217980 kb
Host smart-bb05f8af-44d8-42af-a099-b69c7808d96d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122450726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.2122450726
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3415921243
Short name T812
Test name
Test status
Simulation time 11871928864 ps
CPU time 44.54 seconds
Started Jun 30 06:47:00 PM PDT 24
Finished Jun 30 06:47:45 PM PDT 24
Peak memory 226308 kb
Host smart-5623b46c-93e9-4c0e-a778-296179ecb647
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415921243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3415921243
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1456215262
Short name T491
Test name
Test status
Simulation time 1416062795 ps
CPU time 6.04 seconds
Started Jun 30 06:46:58 PM PDT 24
Finished Jun 30 06:47:05 PM PDT 24
Peak memory 218432 kb
Host smart-f58fe3ec-c1f1-4e3c-97e9-ee4d87178d5d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456215262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1456215262
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2111984389
Short name T261
Test name
Test status
Simulation time 253712367 ps
CPU time 4.5 seconds
Started Jun 30 06:46:58 PM PDT 24
Finished Jun 30 06:47:03 PM PDT 24
Peak memory 217908 kb
Host smart-d0966b07-5c29-4ca0-a085-b8ccfe9b5d98
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111984389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2111984389
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1396026524
Short name T346
Test name
Test status
Simulation time 1490800921 ps
CPU time 47.33 seconds
Started Jun 30 06:46:57 PM PDT 24
Finished Jun 30 06:47:45 PM PDT 24
Peak memory 275728 kb
Host smart-d5ddec9f-3aa1-4c0f-9635-c3af96b60f09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396026524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.1396026524
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3344357221
Short name T164
Test name
Test status
Simulation time 296059862 ps
CPU time 9.32 seconds
Started Jun 30 06:47:00 PM PDT 24
Finished Jun 30 06:47:09 PM PDT 24
Peak memory 250684 kb
Host smart-49c040c8-36a0-4526-b0f6-d146e1354fec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344357221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3344357221
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2293921113
Short name T543
Test name
Test status
Simulation time 80041978 ps
CPU time 2.08 seconds
Started Jun 30 06:47:00 PM PDT 24
Finished Jun 30 06:47:03 PM PDT 24
Peak memory 222308 kb
Host smart-aa84a74c-bb7b-4035-affd-27fe1a207d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293921113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2293921113
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.681965643
Short name T853
Test name
Test status
Simulation time 1527831296 ps
CPU time 14.83 seconds
Started Jun 30 06:46:59 PM PDT 24
Finished Jun 30 06:47:15 PM PDT 24
Peak memory 219148 kb
Host smart-1f853ccf-8e94-4776-8bc2-7b6a6bc14b3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681965643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.681965643
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2412289257
Short name T318
Test name
Test status
Simulation time 2689811543 ps
CPU time 12.81 seconds
Started Jun 30 06:46:57 PM PDT 24
Finished Jun 30 06:47:11 PM PDT 24
Peak memory 218524 kb
Host smart-570cccf8-04f3-405e-9355-e1bd9098c0d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412289257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2412289257
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3285497929
Short name T745
Test name
Test status
Simulation time 1038169943 ps
CPU time 9.26 seconds
Started Jun 30 06:46:59 PM PDT 24
Finished Jun 30 06:47:09 PM PDT 24
Peak memory 218456 kb
Host smart-2a9ee01b-a751-48a8-a2b7-524d2a927f6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285497929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
3285497929
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.473288929
Short name T803
Test name
Test status
Simulation time 659832494 ps
CPU time 8.37 seconds
Started Jun 30 06:47:00 PM PDT 24
Finished Jun 30 06:47:09 PM PDT 24
Peak memory 218472 kb
Host smart-72152238-c6b8-493f-a0a6-763eaf9dd6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473288929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.473288929
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.4017499679
Short name T68
Test name
Test status
Simulation time 813494591 ps
CPU time 8.64 seconds
Started Jun 30 06:46:57 PM PDT 24
Finished Jun 30 06:47:06 PM PDT 24
Peak memory 217932 kb
Host smart-b78fbd98-729b-4281-b634-57f0827538ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017499679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.4017499679
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2919608141
Short name T768
Test name
Test status
Simulation time 487636735 ps
CPU time 24.68 seconds
Started Jun 30 06:47:03 PM PDT 24
Finished Jun 30 06:47:28 PM PDT 24
Peak memory 251308 kb
Host smart-7bffa575-ff84-4316-a397-33827095115f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919608141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2919608141
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.2454400120
Short name T386
Test name
Test status
Simulation time 847074746 ps
CPU time 3.39 seconds
Started Jun 30 06:46:59 PM PDT 24
Finished Jun 30 06:47:03 PM PDT 24
Peak memory 222572 kb
Host smart-924e9e2f-c5fe-4cea-86d1-cc81770546a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454400120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.2454400120
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2867889477
Short name T629
Test name
Test status
Simulation time 4771785605 ps
CPU time 109.97 seconds
Started Jun 30 06:46:58 PM PDT 24
Finished Jun 30 06:48:48 PM PDT 24
Peak memory 281080 kb
Host smart-3d7291af-2d51-40c4-8b60-3ed55f4972b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867889477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2867889477
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.476183535
Short name T93
Test name
Test status
Simulation time 21293874040 ps
CPU time 301.86 seconds
Started Jun 30 06:46:57 PM PDT 24
Finished Jun 30 06:52:00 PM PDT 24
Peak memory 276392 kb
Host smart-eb9d278d-30f4-4ac5-a264-4ba745c540fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=476183535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.476183535
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.428612369
Short name T696
Test name
Test status
Simulation time 39253309 ps
CPU time 0.85 seconds
Started Jun 30 06:47:02 PM PDT 24
Finished Jun 30 06:47:04 PM PDT 24
Peak memory 211980 kb
Host smart-1bb4af50-9482-4265-858b-e679164ff062
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428612369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.428612369
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1013014000
Short name T690
Test name
Test status
Simulation time 79367570 ps
CPU time 0.85 seconds
Started Jun 30 06:47:04 PM PDT 24
Finished Jun 30 06:47:06 PM PDT 24
Peak memory 208944 kb
Host smart-4455b3ae-0447-42f7-ab1a-b47cd44c53f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013014000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1013014000
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.1941021463
Short name T50
Test name
Test status
Simulation time 1113580591 ps
CPU time 15.51 seconds
Started Jun 30 06:46:58 PM PDT 24
Finished Jun 30 06:47:14 PM PDT 24
Peak memory 218552 kb
Host smart-c54f2101-6718-44e5-a13f-82c0b73c63f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941021463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1941021463
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.1426674841
Short name T23
Test name
Test status
Simulation time 762798438 ps
CPU time 3.05 seconds
Started Jun 30 06:47:07 PM PDT 24
Finished Jun 30 06:47:11 PM PDT 24
Peak memory 217256 kb
Host smart-ec8f5e8b-0a7a-4da3-9c03-ee599f2085e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426674841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.1426674841
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.1362796379
Short name T713
Test name
Test status
Simulation time 4589683924 ps
CPU time 31.6 seconds
Started Jun 30 06:47:04 PM PDT 24
Finished Jun 30 06:47:36 PM PDT 24
Peak memory 218384 kb
Host smart-f3e68310-820b-43f7-a1eb-1748822a2412
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362796379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.1362796379
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3955286064
Short name T18
Test name
Test status
Simulation time 214800552 ps
CPU time 4.51 seconds
Started Jun 30 06:47:00 PM PDT 24
Finished Jun 30 06:47:05 PM PDT 24
Peak memory 218432 kb
Host smart-cf12a462-31d7-402b-8579-ba51dbfcc60f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955286064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.3955286064
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.2940577486
Short name T65
Test name
Test status
Simulation time 122441514 ps
CPU time 2.59 seconds
Started Jun 30 06:47:00 PM PDT 24
Finished Jun 30 06:47:04 PM PDT 24
Peak memory 218124 kb
Host smart-9f6750c8-a769-476b-90ca-2dafabaed4b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940577486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.2940577486
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3219011795
Short name T163
Test name
Test status
Simulation time 18951818698 ps
CPU time 30.69 seconds
Started Jun 30 06:46:58 PM PDT 24
Finished Jun 30 06:47:30 PM PDT 24
Peak memory 251188 kb
Host smart-056f2d36-5fee-4499-aacb-32ba049c203e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219011795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.3219011795
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1029167595
Short name T477
Test name
Test status
Simulation time 391515931 ps
CPU time 12.53 seconds
Started Jun 30 06:46:58 PM PDT 24
Finished Jun 30 06:47:11 PM PDT 24
Peak memory 251084 kb
Host smart-65371e58-575e-46dc-b94b-eedce6639c9f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029167595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.1029167595
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.4102244131
Short name T692
Test name
Test status
Simulation time 80971302 ps
CPU time 1.81 seconds
Started Jun 30 06:47:00 PM PDT 24
Finished Jun 30 06:47:03 PM PDT 24
Peak memory 218380 kb
Host smart-93aaa3c3-efae-4fbf-9029-7dcf25724890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102244131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.4102244131
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.3082057590
Short name T325
Test name
Test status
Simulation time 392242890 ps
CPU time 17.06 seconds
Started Jun 30 06:47:04 PM PDT 24
Finished Jun 30 06:47:23 PM PDT 24
Peak memory 226252 kb
Host smart-a6960a1b-8767-42c4-91c0-33f1830cfb8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082057590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3082057590
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.2733216220
Short name T752
Test name
Test status
Simulation time 1679560321 ps
CPU time 14.92 seconds
Started Jun 30 06:47:07 PM PDT 24
Finished Jun 30 06:47:23 PM PDT 24
Peak memory 218452 kb
Host smart-2eb7487f-2684-4ff1-b731-156ee89d87e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733216220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.2733216220
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.1913259176
Short name T278
Test name
Test status
Simulation time 4083868924 ps
CPU time 15.62 seconds
Started Jun 30 06:47:07 PM PDT 24
Finished Jun 30 06:47:23 PM PDT 24
Peak memory 219152 kb
Host smart-04dd484c-a9b3-4e30-a504-1f876b71fe58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913259176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
1913259176
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.2705559624
Short name T44
Test name
Test status
Simulation time 355385391 ps
CPU time 8.32 seconds
Started Jun 30 06:47:00 PM PDT 24
Finished Jun 30 06:47:09 PM PDT 24
Peak memory 218512 kb
Host smart-f10557fe-91fe-4501-afb6-d309fcb27640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705559624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2705559624
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.1764652256
Short name T337
Test name
Test status
Simulation time 235426654 ps
CPU time 1.69 seconds
Started Jun 30 06:46:58 PM PDT 24
Finished Jun 30 06:47:00 PM PDT 24
Peak memory 214096 kb
Host smart-d10d6720-ac2f-4aca-923d-e4253280f55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764652256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1764652256
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2556850339
Short name T704
Test name
Test status
Simulation time 787682854 ps
CPU time 24.32 seconds
Started Jun 30 06:47:00 PM PDT 24
Finished Jun 30 06:47:25 PM PDT 24
Peak memory 251128 kb
Host smart-7bd7a2c1-0b69-4bc1-8b57-db3078269a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556850339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2556850339
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.1658050407
Short name T159
Test name
Test status
Simulation time 61365469 ps
CPU time 6.45 seconds
Started Jun 30 06:46:58 PM PDT 24
Finished Jun 30 06:47:05 PM PDT 24
Peak memory 250680 kb
Host smart-8d70b327-57f9-4bce-a9be-c6da3ae1deb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658050407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.1658050407
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.729314954
Short name T201
Test name
Test status
Simulation time 4010703228 ps
CPU time 88.79 seconds
Started Jun 30 06:47:07 PM PDT 24
Finished Jun 30 06:48:37 PM PDT 24
Peak memory 251176 kb
Host smart-60366f12-dbef-4623-922f-e7e89d3aca3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729314954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.729314954
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2473345101
Short name T649
Test name
Test status
Simulation time 54411865 ps
CPU time 1.04 seconds
Started Jun 30 06:47:00 PM PDT 24
Finished Jun 30 06:47:01 PM PDT 24
Peak memory 213176 kb
Host smart-016f52f1-4c3b-4ce0-aeb5-376cd175a2fb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473345101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.2473345101
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.62457626
Short name T367
Test name
Test status
Simulation time 30960144 ps
CPU time 0.9 seconds
Started Jun 30 06:47:03 PM PDT 24
Finished Jun 30 06:47:05 PM PDT 24
Peak memory 208940 kb
Host smart-e20a9005-544c-4bac-baa5-e4e584c47054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62457626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.62457626
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.2569775849
Short name T816
Test name
Test status
Simulation time 406216654 ps
CPU time 11.64 seconds
Started Jun 30 06:47:04 PM PDT 24
Finished Jun 30 06:47:17 PM PDT 24
Peak memory 217568 kb
Host smart-78c382b4-82c7-42d6-8e20-c032bf7363c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569775849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.2569775849
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.13667169
Short name T748
Test name
Test status
Simulation time 13504815555 ps
CPU time 26.75 seconds
Started Jun 30 06:47:04 PM PDT 24
Finished Jun 30 06:47:32 PM PDT 24
Peak memory 218820 kb
Host smart-359f453b-127b-418d-ab34-2c4bebed0d29
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13667169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_err
ors.13667169
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.2982452238
Short name T421
Test name
Test status
Simulation time 1927895379 ps
CPU time 14.42 seconds
Started Jun 30 06:47:06 PM PDT 24
Finished Jun 30 06:47:21 PM PDT 24
Peak memory 218352 kb
Host smart-9faec288-b8ae-4905-a532-19efcb993fc1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982452238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.2982452238
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.4090276042
Short name T617
Test name
Test status
Simulation time 237951029 ps
CPU time 5.06 seconds
Started Jun 30 06:47:04 PM PDT 24
Finished Jun 30 06:47:11 PM PDT 24
Peak memory 217896 kb
Host smart-d6dc38af-7aef-4822-9e9c-b48cae6f5786
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090276042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.4090276042
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.2883813289
Short name T646
Test name
Test status
Simulation time 2766032341 ps
CPU time 93.96 seconds
Started Jun 30 06:47:07 PM PDT 24
Finished Jun 30 06:48:41 PM PDT 24
Peak memory 279852 kb
Host smart-86b9b57b-9cba-4f77-bd1b-2f2a311ccd5a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883813289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.2883813289
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2069954274
Short name T807
Test name
Test status
Simulation time 651160347 ps
CPU time 13.43 seconds
Started Jun 30 06:47:04 PM PDT 24
Finished Jun 30 06:47:18 PM PDT 24
Peak memory 251112 kb
Host smart-b1879287-3d4e-4294-abcf-047cdb673e52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069954274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2069954274
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.4171114255
Short name T523
Test name
Test status
Simulation time 574580132 ps
CPU time 2.46 seconds
Started Jun 30 06:47:06 PM PDT 24
Finished Jun 30 06:47:09 PM PDT 24
Peak memory 218416 kb
Host smart-98709ab0-71a1-44e4-8c92-c1888046abda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171114255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.4171114255
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.218618033
Short name T636
Test name
Test status
Simulation time 4405674722 ps
CPU time 14.93 seconds
Started Jun 30 06:47:05 PM PDT 24
Finished Jun 30 06:47:21 PM PDT 24
Peak memory 226296 kb
Host smart-e02bf4a2-a8d5-4c5e-ac53-2e4e2eb860f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218618033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.218618033
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1555891512
Short name T298
Test name
Test status
Simulation time 733114951 ps
CPU time 9.77 seconds
Started Jun 30 06:47:04 PM PDT 24
Finished Jun 30 06:47:14 PM PDT 24
Peak memory 218456 kb
Host smart-36af0ad6-efac-4563-b84b-bc1cc3b8b2d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555891512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1555891512
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1444854365
Short name T869
Test name
Test status
Simulation time 1692755916 ps
CPU time 7.26 seconds
Started Jun 30 06:47:04 PM PDT 24
Finished Jun 30 06:47:12 PM PDT 24
Peak memory 218392 kb
Host smart-62061096-1bb7-41d3-a6c0-82e3d4696e0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444854365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1444854365
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.794737407
Short name T535
Test name
Test status
Simulation time 1500151248 ps
CPU time 11.18 seconds
Started Jun 30 06:47:05 PM PDT 24
Finished Jun 30 06:47:17 PM PDT 24
Peak memory 218508 kb
Host smart-71595600-d12a-48af-af33-e8183a648eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794737407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.794737407
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.1824773216
Short name T394
Test name
Test status
Simulation time 860400660 ps
CPU time 7.1 seconds
Started Jun 30 06:47:10 PM PDT 24
Finished Jun 30 06:47:19 PM PDT 24
Peak memory 217740 kb
Host smart-38700c27-5d01-4c67-ae97-112319c82e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824773216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1824773216
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.1021541593
Short name T374
Test name
Test status
Simulation time 632780844 ps
CPU time 25.08 seconds
Started Jun 30 06:47:08 PM PDT 24
Finished Jun 30 06:47:34 PM PDT 24
Peak memory 251228 kb
Host smart-cbb83b74-0835-4338-968c-55cd58a2d34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021541593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.1021541593
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3822938162
Short name T409
Test name
Test status
Simulation time 66232538 ps
CPU time 3.66 seconds
Started Jun 30 06:47:10 PM PDT 24
Finished Jun 30 06:47:15 PM PDT 24
Peak memory 218232 kb
Host smart-80a38e8e-9c7d-4f8b-9ea4-23deb8d895e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822938162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3822938162
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2888870947
Short name T179
Test name
Test status
Simulation time 11746311578 ps
CPU time 191.03 seconds
Started Jun 30 06:47:04 PM PDT 24
Finished Jun 30 06:50:16 PM PDT 24
Peak memory 288740 kb
Host smart-efa5677a-6118-46da-8870-1280953d02bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888870947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2888870947
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2219272136
Short name T852
Test name
Test status
Simulation time 35400646 ps
CPU time 0.95 seconds
Started Jun 30 06:47:07 PM PDT 24
Finished Jun 30 06:47:09 PM PDT 24
Peak memory 217892 kb
Host smart-482074d7-4037-443d-b880-a5971889d6f8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219272136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.2219272136
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.3714740493
Short name T165
Test name
Test status
Simulation time 29172813 ps
CPU time 1.06 seconds
Started Jun 30 06:47:12 PM PDT 24
Finished Jun 30 06:47:15 PM PDT 24
Peak memory 209136 kb
Host smart-3cef5c4f-6c4d-435a-9dcb-dbc7728f11b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714740493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.3714740493
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1578916862
Short name T504
Test name
Test status
Simulation time 2882440503 ps
CPU time 12.67 seconds
Started Jun 30 06:47:05 PM PDT 24
Finished Jun 30 06:47:18 PM PDT 24
Peak memory 219144 kb
Host smart-9a32fd29-7487-4d86-bcff-4e66f8c62476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578916862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1578916862
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.1799020323
Short name T511
Test name
Test status
Simulation time 153357023 ps
CPU time 2.99 seconds
Started Jun 30 06:47:12 PM PDT 24
Finished Jun 30 06:47:16 PM PDT 24
Peak memory 217252 kb
Host smart-76c8e9b7-a035-4938-b7fd-e08a5fc2b94d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799020323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.1799020323
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2043925502
Short name T615
Test name
Test status
Simulation time 14640475960 ps
CPU time 49.79 seconds
Started Jun 30 06:47:10 PM PDT 24
Finished Jun 30 06:48:01 PM PDT 24
Peak memory 226292 kb
Host smart-40b67bd0-6c16-473c-8a4a-e930b4bbd648
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043925502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2043925502
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.202635059
Short name T544
Test name
Test status
Simulation time 190014679 ps
CPU time 5.05 seconds
Started Jun 30 06:47:03 PM PDT 24
Finished Jun 30 06:47:08 PM PDT 24
Peak memory 218408 kb
Host smart-8366db96-fcf0-4a06-ac29-165fac2606ca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202635059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.202635059
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2271838926
Short name T855
Test name
Test status
Simulation time 154677292 ps
CPU time 4.67 seconds
Started Jun 30 06:47:04 PM PDT 24
Finished Jun 30 06:47:10 PM PDT 24
Peak memory 217880 kb
Host smart-37ab049f-edc9-4458-9b98-0c64d90e3a07
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271838926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2271838926
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2679222461
Short name T541
Test name
Test status
Simulation time 4103932166 ps
CPU time 50.4 seconds
Started Jun 30 06:47:03 PM PDT 24
Finished Jun 30 06:47:54 PM PDT 24
Peak memory 276784 kb
Host smart-701cc206-b83b-49a5-8205-446d748bd43b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679222461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.2679222461
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1330570299
Short name T823
Test name
Test status
Simulation time 1818763642 ps
CPU time 7.86 seconds
Started Jun 30 06:47:07 PM PDT 24
Finished Jun 30 06:47:16 PM PDT 24
Peak memory 222992 kb
Host smart-f2f1df2e-90fa-4f0c-b6c6-d89aed1cbf5a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330570299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1330570299
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.1601376530
Short name T550
Test name
Test status
Simulation time 172240195 ps
CPU time 4.04 seconds
Started Jun 30 06:47:06 PM PDT 24
Finished Jun 30 06:47:11 PM PDT 24
Peak memory 218348 kb
Host smart-f0e3eb13-a393-44f2-acfb-5ec2e17ae459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601376530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.1601376530
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.1533022761
Short name T759
Test name
Test status
Simulation time 365707986 ps
CPU time 16.93 seconds
Started Jun 30 06:47:10 PM PDT 24
Finished Jun 30 06:47:28 PM PDT 24
Peak memory 226252 kb
Host smart-6132adc4-3f5c-4d9f-8320-bea42bf28436
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533022761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.1533022761
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3122505021
Short name T710
Test name
Test status
Simulation time 1968851528 ps
CPU time 11.17 seconds
Started Jun 30 06:47:10 PM PDT 24
Finished Jun 30 06:47:23 PM PDT 24
Peak memory 218444 kb
Host smart-efd624a0-b4f3-4090-be15-bf1003af5ec7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122505021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.3122505021
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.3490588619
Short name T323
Test name
Test status
Simulation time 699081453 ps
CPU time 9.03 seconds
Started Jun 30 06:47:10 PM PDT 24
Finished Jun 30 06:47:20 PM PDT 24
Peak memory 218692 kb
Host smart-f887096e-9658-43df-906d-5aa5ddb054d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490588619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
3490588619
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.3814829684
Short name T92
Test name
Test status
Simulation time 340662381 ps
CPU time 13.06 seconds
Started Jun 30 06:47:04 PM PDT 24
Finished Jun 30 06:47:18 PM PDT 24
Peak memory 226248 kb
Host smart-703ba771-6a1a-42cd-b056-4ecebc998ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814829684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.3814829684
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.426773878
Short name T52
Test name
Test status
Simulation time 24894184 ps
CPU time 2.14 seconds
Started Jun 30 06:47:06 PM PDT 24
Finished Jun 30 06:47:08 PM PDT 24
Peak memory 214440 kb
Host smart-4bef8b7e-a20d-452b-84c7-325e9ff20c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426773878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.426773878
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.3444663453
Short name T586
Test name
Test status
Simulation time 317712619 ps
CPU time 31.45 seconds
Started Jun 30 06:47:05 PM PDT 24
Finished Jun 30 06:47:38 PM PDT 24
Peak memory 251128 kb
Host smart-0157c1eb-d89a-4d86-ac1c-db684c38daa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444663453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3444663453
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.3178057842
Short name T467
Test name
Test status
Simulation time 695680907 ps
CPU time 10.06 seconds
Started Jun 30 06:47:06 PM PDT 24
Finished Jun 30 06:47:17 PM PDT 24
Peak memory 251124 kb
Host smart-9d1a73e1-2737-439f-a57b-5647a0a8d067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178057842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3178057842
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.243059963
Short name T736
Test name
Test status
Simulation time 13681467453 ps
CPU time 349.97 seconds
Started Jun 30 06:47:11 PM PDT 24
Finished Jun 30 06:53:03 PM PDT 24
Peak memory 283268 kb
Host smart-7629d92d-72bf-47e8-aa75-a193e4a3db35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243059963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.243059963
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.3106689724
Short name T137
Test name
Test status
Simulation time 65582788571 ps
CPU time 1164.59 seconds
Started Jun 30 06:47:12 PM PDT 24
Finished Jun 30 07:06:38 PM PDT 24
Peak memory 446064 kb
Host smart-19c2e195-ce2a-485a-aa11-e0a5a6cbac66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3106689724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.3106689724
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.4138989674
Short name T469
Test name
Test status
Simulation time 17901550 ps
CPU time 0.91 seconds
Started Jun 30 06:47:09 PM PDT 24
Finished Jun 30 06:47:11 PM PDT 24
Peak memory 212136 kb
Host smart-5a3e567c-84fe-4f41-b111-be20c6cd9a4a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138989674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.4138989674
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.1244112616
Short name T497
Test name
Test status
Simulation time 88492247 ps
CPU time 1.94 seconds
Started Jun 30 06:46:04 PM PDT 24
Finished Jun 30 06:46:08 PM PDT 24
Peak memory 209216 kb
Host smart-df9584ea-34cf-419a-990d-075ee7c70a4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244112616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1244112616
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.677507042
Short name T204
Test name
Test status
Simulation time 11386479 ps
CPU time 0.93 seconds
Started Jun 30 06:46:10 PM PDT 24
Finished Jun 30 06:46:12 PM PDT 24
Peak memory 209168 kb
Host smart-6a98d701-3d9e-48ce-b486-b06d4df72026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677507042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.677507042
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.3069273062
Short name T457
Test name
Test status
Simulation time 1383022495 ps
CPU time 11.74 seconds
Started Jun 30 06:46:05 PM PDT 24
Finished Jun 30 06:46:18 PM PDT 24
Peak memory 226244 kb
Host smart-01685fe2-ef72-455c-9443-35ff524b94ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069273062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.3069273062
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.3186361460
Short name T765
Test name
Test status
Simulation time 5136471255 ps
CPU time 15.07 seconds
Started Jun 30 06:46:07 PM PDT 24
Finished Jun 30 06:46:23 PM PDT 24
Peak memory 217948 kb
Host smart-90fa780e-8572-4d73-ba03-c8dcb60fbf24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186361460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.3186361460
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.2439454337
Short name T423
Test name
Test status
Simulation time 4730249618 ps
CPU time 34.39 seconds
Started Jun 30 06:46:04 PM PDT 24
Finished Jun 30 06:46:39 PM PDT 24
Peak memory 220168 kb
Host smart-7323c43f-79a6-481b-b834-292dfab33101
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439454337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.2439454337
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.113850934
Short name T470
Test name
Test status
Simulation time 375909801 ps
CPU time 2.69 seconds
Started Jun 30 06:46:04 PM PDT 24
Finished Jun 30 06:46:08 PM PDT 24
Peak memory 217616 kb
Host smart-4dafa19f-f6f0-4bcf-8604-58c059e17a6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113850934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.113850934
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.95252500
Short name T723
Test name
Test status
Simulation time 647181295 ps
CPU time 5.73 seconds
Started Jun 30 06:46:09 PM PDT 24
Finished Jun 30 06:46:15 PM PDT 24
Peak memory 223268 kb
Host smart-cba9170c-f248-4303-b8bc-4fb1077f7f94
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95252500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_p
rog_failure.95252500
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.408679169
Short name T474
Test name
Test status
Simulation time 2533503990 ps
CPU time 37.99 seconds
Started Jun 30 06:46:06 PM PDT 24
Finished Jun 30 06:46:46 PM PDT 24
Peak memory 218048 kb
Host smart-9683b641-d66e-496e-8b64-3ea991cc1613
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408679169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_regwen_during_op.408679169
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1128343065
Short name T319
Test name
Test status
Simulation time 1429461175 ps
CPU time 6.17 seconds
Started Jun 30 06:46:04 PM PDT 24
Finished Jun 30 06:46:12 PM PDT 24
Peak memory 217932 kb
Host smart-5a6df10d-cc42-4999-a10d-b50393aa019c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128343065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1128343065
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2633307397
Short name T217
Test name
Test status
Simulation time 29944453076 ps
CPU time 97 seconds
Started Jun 30 06:46:03 PM PDT 24
Finished Jun 30 06:47:41 PM PDT 24
Peak memory 283360 kb
Host smart-5d15b19d-f70f-44e8-94f9-67330fc9cf13
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633307397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.2633307397
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.1944499976
Short name T456
Test name
Test status
Simulation time 851521054 ps
CPU time 17.12 seconds
Started Jun 30 06:46:06 PM PDT 24
Finished Jun 30 06:46:25 PM PDT 24
Peak memory 248084 kb
Host smart-5d9d5d3b-6104-4fa5-a512-58f08954bde3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944499976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.1944499976
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.4127845400
Short name T440
Test name
Test status
Simulation time 145390193 ps
CPU time 3.41 seconds
Started Jun 30 06:46:06 PM PDT 24
Finished Jun 30 06:46:11 PM PDT 24
Peak memory 218448 kb
Host smart-06f676af-ac5d-4b68-a081-cb8d750b2ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127845400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.4127845400
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2283245197
Short name T364
Test name
Test status
Simulation time 946153831 ps
CPU time 13.68 seconds
Started Jun 30 06:46:10 PM PDT 24
Finished Jun 30 06:46:25 PM PDT 24
Peak memory 214720 kb
Host smart-1b9587dc-1d04-4c04-8e66-c9acadcaa2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283245197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2283245197
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1480837482
Short name T48
Test name
Test status
Simulation time 850460101 ps
CPU time 37.8 seconds
Started Jun 30 06:46:05 PM PDT 24
Finished Jun 30 06:46:44 PM PDT 24
Peak memory 269756 kb
Host smart-49dacf88-1e1a-4dbd-80ca-fd20911ea3a1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480837482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1480837482
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.2702706714
Short name T485
Test name
Test status
Simulation time 588049684 ps
CPU time 15.03 seconds
Started Jun 30 06:46:07 PM PDT 24
Finished Jun 30 06:46:23 PM PDT 24
Peak memory 226220 kb
Host smart-07c675ff-8918-4283-aca3-928edc488981
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702706714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2702706714
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3546986523
Short name T787
Test name
Test status
Simulation time 776492773 ps
CPU time 19.61 seconds
Started Jun 30 06:46:05 PM PDT 24
Finished Jun 30 06:46:26 PM PDT 24
Peak memory 218464 kb
Host smart-6d1d6edc-03a3-48e9-b19d-e95435fe6be9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546986523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.3546986523
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1756877713
Short name T342
Test name
Test status
Simulation time 264629221 ps
CPU time 11.01 seconds
Started Jun 30 06:46:06 PM PDT 24
Finished Jun 30 06:46:19 PM PDT 24
Peak memory 218440 kb
Host smart-88dc1f6d-b9cb-4e6f-841d-073c2e753183
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756877713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.1
756877713
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.148702304
Short name T640
Test name
Test status
Simulation time 441862533 ps
CPU time 6.83 seconds
Started Jun 30 06:46:03 PM PDT 24
Finished Jun 30 06:46:11 PM PDT 24
Peak memory 218452 kb
Host smart-be3a1771-fc91-42a6-88a6-42d4b2b28b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148702304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.148702304
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.3366207648
Short name T530
Test name
Test status
Simulation time 51007658 ps
CPU time 2.55 seconds
Started Jun 30 06:45:59 PM PDT 24
Finished Jun 30 06:46:03 PM PDT 24
Peak memory 218008 kb
Host smart-fab04aaa-2739-40c6-8677-cf28c20e7522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366207648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3366207648
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.2215579762
Short name T697
Test name
Test status
Simulation time 424744898 ps
CPU time 21.09 seconds
Started Jun 30 06:46:06 PM PDT 24
Finished Jun 30 06:46:28 PM PDT 24
Peak memory 251128 kb
Host smart-26a5322f-65e5-473a-a8b0-4389a4fe79f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215579762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.2215579762
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.1734996904
Short name T275
Test name
Test status
Simulation time 159708490 ps
CPU time 8.37 seconds
Started Jun 30 06:46:04 PM PDT 24
Finished Jun 30 06:46:13 PM PDT 24
Peak memory 247112 kb
Host smart-be5720d2-849e-43c0-8a1d-6e159608a630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734996904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.1734996904
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2849640349
Short name T708
Test name
Test status
Simulation time 24206699097 ps
CPU time 422.57 seconds
Started Jun 30 06:46:05 PM PDT 24
Finished Jun 30 06:53:09 PM PDT 24
Peak memory 274720 kb
Host smart-781081ab-85e0-4ac3-acc8-9ca44c78f618
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849640349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2849640349
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.4288478001
Short name T593
Test name
Test status
Simulation time 13862486 ps
CPU time 1.05 seconds
Started Jun 30 06:46:00 PM PDT 24
Finished Jun 30 06:46:03 PM PDT 24
Peak memory 212116 kb
Host smart-35d4b52b-267e-42c9-8716-b35d6b5f41b5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288478001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.4288478001
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.3961891834
Short name T284
Test name
Test status
Simulation time 47980793 ps
CPU time 1.43 seconds
Started Jun 30 06:47:12 PM PDT 24
Finished Jun 30 06:47:15 PM PDT 24
Peak memory 209280 kb
Host smart-6e65e0b4-38f9-43c2-981c-39acf96f6452
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961891834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.3961891834
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3505634787
Short name T39
Test name
Test status
Simulation time 275242712 ps
CPU time 10.44 seconds
Started Jun 30 06:47:10 PM PDT 24
Finished Jun 30 06:47:22 PM PDT 24
Peak memory 218444 kb
Host smart-2c85c371-f5f2-4e92-bdf3-3293fa6b37cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505634787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3505634787
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.3769334568
Short name T482
Test name
Test status
Simulation time 354083943 ps
CPU time 9.1 seconds
Started Jun 30 06:47:15 PM PDT 24
Finished Jun 30 06:47:25 PM PDT 24
Peak memory 217356 kb
Host smart-282040a2-f6c1-4114-96b0-ec82462f6ef6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769334568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.3769334568
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2405325576
Short name T445
Test name
Test status
Simulation time 41679940 ps
CPU time 1.9 seconds
Started Jun 30 06:47:13 PM PDT 24
Finished Jun 30 06:47:16 PM PDT 24
Peak memory 222260 kb
Host smart-bd948475-1b37-4faf-8f8c-d15d850e4756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405325576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2405325576
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.3432542394
Short name T447
Test name
Test status
Simulation time 854125450 ps
CPU time 12.06 seconds
Started Jun 30 06:47:12 PM PDT 24
Finished Jun 30 06:47:25 PM PDT 24
Peak memory 226224 kb
Host smart-533aa0b5-d3c0-4536-b065-d047159ac612
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432542394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.3432542394
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3121541275
Short name T642
Test name
Test status
Simulation time 338328282 ps
CPU time 13.42 seconds
Started Jun 30 06:47:11 PM PDT 24
Finished Jun 30 06:47:26 PM PDT 24
Peak memory 218460 kb
Host smart-9afa19ef-ef9f-43a9-be6d-93e9d4551c9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121541275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3121541275
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.230211091
Short name T276
Test name
Test status
Simulation time 1670545846 ps
CPU time 9.68 seconds
Started Jun 30 06:47:11 PM PDT 24
Finished Jun 30 06:47:22 PM PDT 24
Peak memory 218420 kb
Host smart-5c300745-e668-4748-aa99-1eb71a08d88c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230211091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.230211091
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3669585668
Short name T247
Test name
Test status
Simulation time 212887040 ps
CPU time 6.47 seconds
Started Jun 30 06:47:10 PM PDT 24
Finished Jun 30 06:47:18 PM PDT 24
Peak memory 218436 kb
Host smart-6b51e59c-bfc9-4216-b7a5-7baac51c30f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669585668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3669585668
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.3958889179
Short name T30
Test name
Test status
Simulation time 86748241 ps
CPU time 3.19 seconds
Started Jun 30 06:47:12 PM PDT 24
Finished Jun 30 06:47:16 PM PDT 24
Peak memory 215056 kb
Host smart-e3637a81-71a2-4c85-b7c1-115b8479f0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958889179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3958889179
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.1589109365
Short name T562
Test name
Test status
Simulation time 199308501 ps
CPU time 22.56 seconds
Started Jun 30 06:47:11 PM PDT 24
Finished Jun 30 06:47:35 PM PDT 24
Peak memory 251128 kb
Host smart-f797280e-1013-42e9-9ee8-6e2cbc07caae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589109365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1589109365
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.670211327
Short name T792
Test name
Test status
Simulation time 123060066 ps
CPU time 7.69 seconds
Started Jun 30 06:47:12 PM PDT 24
Finished Jun 30 06:47:21 PM PDT 24
Peak memory 250944 kb
Host smart-760e6cda-def7-4ae0-afde-4e70036a4a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670211327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.670211327
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.268229332
Short name T76
Test name
Test status
Simulation time 24927898933 ps
CPU time 120.2 seconds
Started Jun 30 06:47:08 PM PDT 24
Finished Jun 30 06:49:09 PM PDT 24
Peak memory 267564 kb
Host smart-17682bcf-8bfc-4b28-84cb-50fde40127de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268229332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.268229332
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1400081908
Short name T738
Test name
Test status
Simulation time 64324460 ps
CPU time 1.11 seconds
Started Jun 30 06:47:09 PM PDT 24
Finished Jun 30 06:47:12 PM PDT 24
Peak memory 217920 kb
Host smart-d246528e-a2f6-43d4-877e-986b499b80bf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400081908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1400081908
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.1388805588
Short name T412
Test name
Test status
Simulation time 135364148 ps
CPU time 0.94 seconds
Started Jun 30 06:47:12 PM PDT 24
Finished Jun 30 06:47:14 PM PDT 24
Peak memory 209180 kb
Host smart-81b9e76d-9b91-42ea-86f3-f982b1ff1b81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388805588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1388805588
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.1095176726
Short name T426
Test name
Test status
Simulation time 1355437406 ps
CPU time 10.22 seconds
Started Jun 30 06:47:12 PM PDT 24
Finished Jun 30 06:47:24 PM PDT 24
Peak memory 218284 kb
Host smart-8f980095-8e63-450c-80b4-75231bf99b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095176726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1095176726
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.2794308353
Short name T744
Test name
Test status
Simulation time 2024437655 ps
CPU time 3.34 seconds
Started Jun 30 06:47:15 PM PDT 24
Finished Jun 30 06:47:19 PM PDT 24
Peak memory 217216 kb
Host smart-75d94c02-06c3-49af-a66d-474a7104aced
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794308353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.2794308353
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.1556349464
Short name T561
Test name
Test status
Simulation time 70650696 ps
CPU time 2.46 seconds
Started Jun 30 06:47:15 PM PDT 24
Finished Jun 30 06:47:18 PM PDT 24
Peak memory 217912 kb
Host smart-f8eef57c-88e9-48e5-85da-9e39714dd995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556349464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1556349464
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.2287828257
Short name T270
Test name
Test status
Simulation time 639386330 ps
CPU time 9.61 seconds
Started Jun 30 06:47:14 PM PDT 24
Finished Jun 30 06:47:25 PM PDT 24
Peak memory 219112 kb
Host smart-ddce536b-560e-433c-a719-6f7a40075e9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287828257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.2287828257
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1809142811
Short name T616
Test name
Test status
Simulation time 2412227115 ps
CPU time 13.03 seconds
Started Jun 30 06:47:12 PM PDT 24
Finished Jun 30 06:47:27 PM PDT 24
Peak memory 219164 kb
Host smart-33521582-6a8b-4ee1-a5b8-1f4deb5ef76f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809142811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1809142811
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.1400728990
Short name T671
Test name
Test status
Simulation time 351686979 ps
CPU time 6.51 seconds
Started Jun 30 06:47:12 PM PDT 24
Finished Jun 30 06:47:20 PM PDT 24
Peak memory 226320 kb
Host smart-5956ce75-d5ed-4f93-a675-04b67f755d3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400728990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
1400728990
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.621282804
Short name T675
Test name
Test status
Simulation time 236743058 ps
CPU time 4.08 seconds
Started Jun 30 06:47:15 PM PDT 24
Finished Jun 30 06:47:20 PM PDT 24
Peak memory 217452 kb
Host smart-3bf9cc0f-2067-45fd-9852-105f9a073696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621282804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.621282804
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.60138600
Short name T829
Test name
Test status
Simulation time 239139074 ps
CPU time 25.71 seconds
Started Jun 30 06:47:09 PM PDT 24
Finished Jun 30 06:47:35 PM PDT 24
Peak memory 251128 kb
Host smart-789ea8cf-a1ac-47aa-b50d-fe55af9af059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60138600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.60138600
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.4151087717
Short name T253
Test name
Test status
Simulation time 449914193 ps
CPU time 7.62 seconds
Started Jun 30 06:47:13 PM PDT 24
Finished Jun 30 06:47:22 PM PDT 24
Peak memory 250556 kb
Host smart-d201b3b4-a145-4abe-9feb-508ebec96f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151087717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.4151087717
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.1323592329
Short name T462
Test name
Test status
Simulation time 16077543504 ps
CPU time 227.57 seconds
Started Jun 30 06:47:11 PM PDT 24
Finished Jun 30 06:50:59 PM PDT 24
Peak memory 284000 kb
Host smart-fe8c4ad3-b6e8-41d0-83d5-ae642eb7f69e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323592329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.1323592329
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.3993935518
Short name T97
Test name
Test status
Simulation time 30647715835 ps
CPU time 599.12 seconds
Started Jun 30 06:47:12 PM PDT 24
Finished Jun 30 06:57:13 PM PDT 24
Peak memory 438692 kb
Host smart-1155fe4c-09e7-48d1-a053-f157ff003200
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3993935518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.3993935518
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.675148894
Short name T701
Test name
Test status
Simulation time 14083866 ps
CPU time 1.02 seconds
Started Jun 30 06:47:12 PM PDT 24
Finished Jun 30 06:47:14 PM PDT 24
Peak memory 213164 kb
Host smart-daf0dd85-894e-44d5-99ef-282047e671b4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675148894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.675148894
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.4249190905
Short name T820
Test name
Test status
Simulation time 18295471 ps
CPU time 1.15 seconds
Started Jun 30 06:47:14 PM PDT 24
Finished Jun 30 06:47:16 PM PDT 24
Peak memory 209244 kb
Host smart-df1633aa-bd31-43f0-a4bb-1f9386b46578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249190905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.4249190905
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.3907996526
Short name T411
Test name
Test status
Simulation time 510584036 ps
CPU time 10.03 seconds
Started Jun 30 06:47:18 PM PDT 24
Finished Jun 30 06:47:29 PM PDT 24
Peak memory 226252 kb
Host smart-93fd9326-c293-4f36-8a87-8ff402b301eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907996526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3907996526
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.2596190802
Short name T766
Test name
Test status
Simulation time 815910156 ps
CPU time 19.35 seconds
Started Jun 30 06:47:21 PM PDT 24
Finished Jun 30 06:47:40 PM PDT 24
Peak memory 217660 kb
Host smart-3471de10-fd42-46a4-b1b8-69680a6da9e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596190802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.2596190802
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3863962469
Short name T302
Test name
Test status
Simulation time 1175840320 ps
CPU time 4.38 seconds
Started Jun 30 06:47:19 PM PDT 24
Finished Jun 30 06:47:24 PM PDT 24
Peak memory 218400 kb
Host smart-06f60606-a762-4292-9e92-a5025d626ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863962469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3863962469
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.4134755901
Short name T36
Test name
Test status
Simulation time 986498900 ps
CPU time 13.7 seconds
Started Jun 30 06:47:17 PM PDT 24
Finished Jun 30 06:47:32 PM PDT 24
Peak memory 226272 kb
Host smart-8cc5e6c5-96cf-409c-a406-e1760c947938
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134755901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.4134755901
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.296981505
Short name T844
Test name
Test status
Simulation time 777121173 ps
CPU time 16.95 seconds
Started Jun 30 06:47:16 PM PDT 24
Finished Jun 30 06:47:34 PM PDT 24
Peak memory 218508 kb
Host smart-c79e8f60-13e1-4755-bbfa-4916132abfa1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296981505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_di
gest.296981505
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.4144329312
Short name T274
Test name
Test status
Simulation time 1038002905 ps
CPU time 10.3 seconds
Started Jun 30 06:47:17 PM PDT 24
Finished Jun 30 06:47:28 PM PDT 24
Peak memory 218444 kb
Host smart-c07fd85e-1946-4184-a192-0afea5c39a5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144329312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
4144329312
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.1115163494
Short name T237
Test name
Test status
Simulation time 344796298 ps
CPU time 6.3 seconds
Started Jun 30 06:47:17 PM PDT 24
Finished Jun 30 06:47:24 PM PDT 24
Peak memory 218412 kb
Host smart-5b45254c-fa58-4bb7-a489-d691da385972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115163494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1115163494
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.600907890
Short name T687
Test name
Test status
Simulation time 73534837 ps
CPU time 1.5 seconds
Started Jun 30 06:47:18 PM PDT 24
Finished Jun 30 06:47:21 PM PDT 24
Peak memory 217956 kb
Host smart-7c139d38-a0e0-4390-aa0c-6f3a0bc80450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600907890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.600907890
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.567617837
Short name T802
Test name
Test status
Simulation time 1910520628 ps
CPU time 28.23 seconds
Started Jun 30 06:47:19 PM PDT 24
Finished Jun 30 06:47:48 PM PDT 24
Peak memory 251148 kb
Host smart-5325137c-cf2d-41bd-bb49-75079f474fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567617837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.567617837
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.4025718645
Short name T539
Test name
Test status
Simulation time 128663619 ps
CPU time 7.31 seconds
Started Jun 30 06:47:20 PM PDT 24
Finished Jun 30 06:47:28 PM PDT 24
Peak memory 251060 kb
Host smart-78ff85d8-e9bb-4093-8975-e286e1c4c890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025718645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.4025718645
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1284867782
Short name T294
Test name
Test status
Simulation time 94858627737 ps
CPU time 290.7 seconds
Started Jun 30 06:47:16 PM PDT 24
Finished Jun 30 06:52:08 PM PDT 24
Peak memory 220916 kb
Host smart-a26c1300-23f6-4f6a-b002-b9226d199a90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284867782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.1284867782
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.2334658790
Short name T83
Test name
Test status
Simulation time 16832947899 ps
CPU time 188.21 seconds
Started Jun 30 06:47:19 PM PDT 24
Finished Jun 30 06:50:28 PM PDT 24
Peak memory 277576 kb
Host smart-3aa74db8-fce2-45a0-b457-919f53f948e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2334658790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.2334658790
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.4271516094
Short name T381
Test name
Test status
Simulation time 107652375 ps
CPU time 0.89 seconds
Started Jun 30 06:47:15 PM PDT 24
Finished Jun 30 06:47:17 PM PDT 24
Peak memory 212128 kb
Host smart-7e7ea5ae-8cd3-4929-b7a9-638e51707b9b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271516094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.4271516094
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.3390134066
Short name T307
Test name
Test status
Simulation time 68272137 ps
CPU time 1.44 seconds
Started Jun 30 06:47:15 PM PDT 24
Finished Jun 30 06:47:17 PM PDT 24
Peak memory 209144 kb
Host smart-aa17ee5c-e514-4374-acf4-6e3a5681d0fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390134066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3390134066
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2802762529
Short name T90
Test name
Test status
Simulation time 321406584 ps
CPU time 10.33 seconds
Started Jun 30 06:47:19 PM PDT 24
Finished Jun 30 06:47:30 PM PDT 24
Peak memory 218408 kb
Host smart-c5c07730-83eb-4e3a-a2fe-d1fbe247e76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802762529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2802762529
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.1444234006
Short name T436
Test name
Test status
Simulation time 3963184420 ps
CPU time 23.76 seconds
Started Jun 30 06:47:16 PM PDT 24
Finished Jun 30 06:47:41 PM PDT 24
Peak memory 217952 kb
Host smart-1b294a23-cde8-4626-b6fa-100b208c4786
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444234006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1444234006
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.4219806887
Short name T592
Test name
Test status
Simulation time 1730873039 ps
CPU time 10.95 seconds
Started Jun 30 06:47:16 PM PDT 24
Finished Jun 30 06:47:28 PM PDT 24
Peak memory 226248 kb
Host smart-09ecb29a-8155-4428-b541-375d5f901293
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219806887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.4219806887
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3107031212
Short name T91
Test name
Test status
Simulation time 471043859 ps
CPU time 18.5 seconds
Started Jun 30 06:47:17 PM PDT 24
Finished Jun 30 06:47:37 PM PDT 24
Peak memory 218368 kb
Host smart-9aef6c7f-accf-4114-a9fc-baba6a6c7a3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107031212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.3107031212
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3953018688
Short name T709
Test name
Test status
Simulation time 319031191 ps
CPU time 11.04 seconds
Started Jun 30 06:47:16 PM PDT 24
Finished Jun 30 06:47:29 PM PDT 24
Peak memory 226180 kb
Host smart-d27b0f4e-bca6-471d-aae2-1dadc34a9f5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953018688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
3953018688
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.3373277582
Short name T793
Test name
Test status
Simulation time 447180528 ps
CPU time 11.11 seconds
Started Jun 30 06:47:15 PM PDT 24
Finished Jun 30 06:47:27 PM PDT 24
Peak memory 218584 kb
Host smart-47ed643b-160b-4fcd-b0da-19cbb8219c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373277582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3373277582
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.2692854759
Short name T397
Test name
Test status
Simulation time 20734867 ps
CPU time 1.63 seconds
Started Jun 30 06:47:16 PM PDT 24
Finished Jun 30 06:47:19 PM PDT 24
Peak memory 217964 kb
Host smart-1a045db5-0078-4747-89fa-780881ed8436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692854759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2692854759
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.459591148
Short name T228
Test name
Test status
Simulation time 2830597140 ps
CPU time 31.34 seconds
Started Jun 30 06:47:19 PM PDT 24
Finished Jun 30 06:47:51 PM PDT 24
Peak memory 251264 kb
Host smart-229ba0ed-318f-4df6-a0bc-ccf9753b43aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459591148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.459591148
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3952792900
Short name T9
Test name
Test status
Simulation time 403635238 ps
CPU time 11.74 seconds
Started Jun 30 06:47:18 PM PDT 24
Finished Jun 30 06:47:31 PM PDT 24
Peak memory 251140 kb
Host smart-d129f94c-4d5f-451e-a6d2-4f5f1ee97fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952792900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3952792900
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3122987015
Short name T98
Test name
Test status
Simulation time 40051411257 ps
CPU time 225.97 seconds
Started Jun 30 06:47:18 PM PDT 24
Finished Jun 30 06:51:05 PM PDT 24
Peak memory 239940 kb
Host smart-3224a503-52d9-4870-b2f5-9f84ec11c592
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122987015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3122987015
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1079223693
Short name T272
Test name
Test status
Simulation time 62283016 ps
CPU time 0.81 seconds
Started Jun 30 06:47:16 PM PDT 24
Finished Jun 30 06:47:18 PM PDT 24
Peak memory 208844 kb
Host smart-29ea3d41-d322-4c12-bd8e-34c2ca68c225
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079223693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.1079223693
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.1577252139
Short name T336
Test name
Test status
Simulation time 34493205 ps
CPU time 0.94 seconds
Started Jun 30 06:47:16 PM PDT 24
Finished Jun 30 06:47:18 PM PDT 24
Peak memory 209148 kb
Host smart-ad12f547-4a5b-4c17-9ae1-a85dddc05186
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577252139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1577252139
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2713646007
Short name T551
Test name
Test status
Simulation time 316762259 ps
CPU time 13.95 seconds
Started Jun 30 06:47:16 PM PDT 24
Finished Jun 30 06:47:32 PM PDT 24
Peak memory 218436 kb
Host smart-b67e3169-6abc-44b8-8d0b-3f155aa374c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713646007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2713646007
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.95691772
Short name T547
Test name
Test status
Simulation time 420179542 ps
CPU time 5.47 seconds
Started Jun 30 06:47:19 PM PDT 24
Finished Jun 30 06:47:26 PM PDT 24
Peak memory 217324 kb
Host smart-c9a51839-1fbd-426a-ae87-5c7f008900fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95691772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.95691772
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1368802290
Short name T774
Test name
Test status
Simulation time 50312979 ps
CPU time 1.51 seconds
Started Jun 30 06:47:20 PM PDT 24
Finished Jun 30 06:47:22 PM PDT 24
Peak memory 218308 kb
Host smart-bb92e3ab-4853-4f81-b5c5-fcacea6094b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368802290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1368802290
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.616203274
Short name T227
Test name
Test status
Simulation time 2325068830 ps
CPU time 14.49 seconds
Started Jun 30 06:47:14 PM PDT 24
Finished Jun 30 06:47:29 PM PDT 24
Peak memory 219160 kb
Host smart-403184ca-2e93-4be2-a923-cd18e387ab13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616203274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.616203274
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.4286527312
Short name T722
Test name
Test status
Simulation time 1165955951 ps
CPU time 10.04 seconds
Started Jun 30 06:47:17 PM PDT 24
Finished Jun 30 06:47:28 PM PDT 24
Peak memory 218484 kb
Host smart-f180393a-b8c9-43d4-97c0-4e3281bd3fc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286527312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.4286527312
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1336169151
Short name T145
Test name
Test status
Simulation time 1413800943 ps
CPU time 11.45 seconds
Started Jun 30 06:47:20 PM PDT 24
Finished Jun 30 06:47:32 PM PDT 24
Peak memory 218372 kb
Host smart-55242488-d35b-4207-89c3-7e768bca369f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336169151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1336169151
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3555670215
Short name T569
Test name
Test status
Simulation time 303703818 ps
CPU time 8.95 seconds
Started Jun 30 06:47:16 PM PDT 24
Finished Jun 30 06:47:26 PM PDT 24
Peak memory 218500 kb
Host smart-c2acb2db-1802-415b-a9fa-9bebb67bb7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555670215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3555670215
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.1868258816
Short name T61
Test name
Test status
Simulation time 177546382 ps
CPU time 2.43 seconds
Started Jun 30 06:47:17 PM PDT 24
Finished Jun 30 06:47:20 PM PDT 24
Peak memory 214636 kb
Host smart-6ed36113-fc83-4a76-b4d5-8280a2124239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868258816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1868258816
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.4169784339
Short name T668
Test name
Test status
Simulation time 345408810 ps
CPU time 40.83 seconds
Started Jun 30 06:47:16 PM PDT 24
Finished Jun 30 06:47:58 PM PDT 24
Peak memory 251112 kb
Host smart-b3bc03db-2cce-42c2-b2de-a23b2288b171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169784339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.4169784339
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.3878273971
Short name T212
Test name
Test status
Simulation time 260764866 ps
CPU time 3.08 seconds
Started Jun 30 06:47:18 PM PDT 24
Finished Jun 30 06:47:22 PM PDT 24
Peak memory 226496 kb
Host smart-73a46fe2-9ad6-414b-8dcb-924b0918e843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878273971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.3878273971
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.526011086
Short name T135
Test name
Test status
Simulation time 125460853883 ps
CPU time 797.6 seconds
Started Jun 30 06:47:20 PM PDT 24
Finished Jun 30 07:00:38 PM PDT 24
Peak memory 504088 kb
Host smart-628158af-5773-46c5-be56-f043e5782ba7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=526011086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.526011086
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1956942294
Short name T591
Test name
Test status
Simulation time 21827423 ps
CPU time 1.04 seconds
Started Jun 30 06:47:17 PM PDT 24
Finished Jun 30 06:47:19 PM PDT 24
Peak memory 212300 kb
Host smart-4fa97ddb-74bd-4a22-856d-71884df24544
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956942294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.1956942294
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.2621461438
Short name T779
Test name
Test status
Simulation time 19595572 ps
CPU time 0.92 seconds
Started Jun 30 06:47:23 PM PDT 24
Finished Jun 30 06:47:24 PM PDT 24
Peak memory 209164 kb
Host smart-53d9a73c-390b-4085-be52-b6008a1e500c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621461438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.2621461438
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.194693174
Short name T15
Test name
Test status
Simulation time 2430378900 ps
CPU time 11.06 seconds
Started Jun 30 06:47:21 PM PDT 24
Finished Jun 30 06:47:32 PM PDT 24
Peak memory 226312 kb
Host smart-50191b96-632e-4179-933f-e78561fda714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194693174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.194693174
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3594502773
Short name T178
Test name
Test status
Simulation time 1797866767 ps
CPU time 11.91 seconds
Started Jun 30 06:47:22 PM PDT 24
Finished Jun 30 06:47:35 PM PDT 24
Peak memory 217604 kb
Host smart-2c1f38c2-a125-4340-97a2-1c92e2e350ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594502773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3594502773
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1117356606
Short name T406
Test name
Test status
Simulation time 313099155 ps
CPU time 2.65 seconds
Started Jun 30 06:47:22 PM PDT 24
Finished Jun 30 06:47:25 PM PDT 24
Peak memory 218424 kb
Host smart-b0dd3641-69b2-46d5-97b1-bca47806854f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117356606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1117356606
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.3634951033
Short name T248
Test name
Test status
Simulation time 1652740195 ps
CPU time 8.26 seconds
Started Jun 30 06:47:22 PM PDT 24
Finished Jun 30 06:47:31 PM PDT 24
Peak memory 218676 kb
Host smart-6edbc5b6-3923-499f-884b-9cc18b8275db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634951033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.3634951033
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.3450586942
Short name T443
Test name
Test status
Simulation time 450322770 ps
CPU time 13.85 seconds
Started Jun 30 06:47:21 PM PDT 24
Finished Jun 30 06:47:36 PM PDT 24
Peak memory 218456 kb
Host smart-f5baa66d-81ac-442c-a923-ca90d1e6abfe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450586942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.3450586942
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.2590813534
Short name T635
Test name
Test status
Simulation time 254677662 ps
CPU time 7.63 seconds
Started Jun 30 06:47:22 PM PDT 24
Finished Jun 30 06:47:31 PM PDT 24
Peak memory 218436 kb
Host smart-72c43857-fc78-430a-9121-e34b58c8032c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590813534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
2590813534
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.119362085
Short name T233
Test name
Test status
Simulation time 203977966 ps
CPU time 1.52 seconds
Started Jun 30 06:47:15 PM PDT 24
Finished Jun 30 06:47:18 PM PDT 24
Peak memory 217916 kb
Host smart-cfa26a99-213a-4e65-8698-fbfd3efdc92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119362085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.119362085
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.2052672998
Short name T578
Test name
Test status
Simulation time 471601045 ps
CPU time 23.21 seconds
Started Jun 30 06:47:16 PM PDT 24
Finished Jun 30 06:47:40 PM PDT 24
Peak memory 251128 kb
Host smart-4401eb1f-8290-47ce-92f5-3efe7659615e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052672998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2052672998
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.534678987
Short name T672
Test name
Test status
Simulation time 163433561 ps
CPU time 10.89 seconds
Started Jun 30 06:47:21 PM PDT 24
Finished Jun 30 06:47:33 PM PDT 24
Peak memory 251132 kb
Host smart-c02428bd-fcfe-4033-87b8-dcc83d6d027e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534678987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.534678987
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.101075906
Short name T487
Test name
Test status
Simulation time 5174700596 ps
CPU time 226.17 seconds
Started Jun 30 06:47:23 PM PDT 24
Finished Jun 30 06:51:10 PM PDT 24
Peak memory 251184 kb
Host smart-c227a509-8058-4a08-918d-47b8e94c5cf0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101075906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.101075906
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3639996627
Short name T596
Test name
Test status
Simulation time 17154576 ps
CPU time 1 seconds
Started Jun 30 06:47:17 PM PDT 24
Finished Jun 30 06:47:20 PM PDT 24
Peak memory 213348 kb
Host smart-48e4526f-4dc5-4bf7-921a-3089c23fd329
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639996627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.3639996627
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1794596675
Short name T698
Test name
Test status
Simulation time 65277913 ps
CPU time 0.97 seconds
Started Jun 30 06:47:28 PM PDT 24
Finished Jun 30 06:47:30 PM PDT 24
Peak memory 209104 kb
Host smart-183ab8be-b0e0-4163-a94b-4177aa3ee378
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794596675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1794596675
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.2336074856
Short name T601
Test name
Test status
Simulation time 446508100 ps
CPU time 13.86 seconds
Started Jun 30 06:47:24 PM PDT 24
Finished Jun 30 06:47:38 PM PDT 24
Peak memory 218368 kb
Host smart-645fac64-6438-400c-8dbf-dfe765bad116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336074856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.2336074856
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.4294895907
Short name T603
Test name
Test status
Simulation time 2701419022 ps
CPU time 16.02 seconds
Started Jun 30 06:47:24 PM PDT 24
Finished Jun 30 06:47:40 PM PDT 24
Peak memory 217724 kb
Host smart-24272c72-1bd4-4c7b-b4bf-66704ebbd06a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294895907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.4294895907
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.941445481
Short name T161
Test name
Test status
Simulation time 24533455 ps
CPU time 1.91 seconds
Started Jun 30 06:47:22 PM PDT 24
Finished Jun 30 06:47:24 PM PDT 24
Peak memory 218428 kb
Host smart-3b469852-3752-4d85-9d57-5ac1a8c271cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941445481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.941445481
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.4225747115
Short name T384
Test name
Test status
Simulation time 1358141655 ps
CPU time 11.92 seconds
Started Jun 30 06:47:20 PM PDT 24
Finished Jun 30 06:47:33 PM PDT 24
Peak memory 226264 kb
Host smart-e64d23d0-aa26-47a3-b0bd-fc0142f468ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225747115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.4225747115
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2330701586
Short name T252
Test name
Test status
Simulation time 3919683415 ps
CPU time 9.97 seconds
Started Jun 30 06:47:23 PM PDT 24
Finished Jun 30 06:47:33 PM PDT 24
Peak memory 218512 kb
Host smart-f554f06c-4bc9-4726-b0a9-2cfea0f57dbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330701586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.2330701586
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1450539519
Short name T329
Test name
Test status
Simulation time 489728872 ps
CPU time 11.8 seconds
Started Jun 30 06:47:24 PM PDT 24
Finished Jun 30 06:47:36 PM PDT 24
Peak memory 226232 kb
Host smart-1a5d62e7-3d14-46c1-96d3-491dd31b6557
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450539519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1450539519
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3602002847
Short name T505
Test name
Test status
Simulation time 362353544 ps
CPU time 9.76 seconds
Started Jun 30 06:47:24 PM PDT 24
Finished Jun 30 06:47:35 PM PDT 24
Peak memory 218544 kb
Host smart-321811de-1cbf-4245-81a3-ae6c746fafd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602002847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3602002847
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.2997174548
Short name T73
Test name
Test status
Simulation time 280307174 ps
CPU time 5.26 seconds
Started Jun 30 06:47:24 PM PDT 24
Finished Jun 30 06:47:30 PM PDT 24
Peak memory 217992 kb
Host smart-c789eec1-38da-4ab9-bed1-cde3e403a794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997174548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.2997174548
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3492490133
Short name T496
Test name
Test status
Simulation time 191030399 ps
CPU time 25.53 seconds
Started Jun 30 06:47:22 PM PDT 24
Finished Jun 30 06:47:48 PM PDT 24
Peak memory 251240 kb
Host smart-b744744b-b53b-4adb-86a2-59bc8163d9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492490133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3492490133
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.4091797744
Short name T232
Test name
Test status
Simulation time 80772765 ps
CPU time 4.34 seconds
Started Jun 30 06:47:23 PM PDT 24
Finished Jun 30 06:47:28 PM PDT 24
Peak memory 222584 kb
Host smart-07634cc0-5be9-44b3-851f-68453319cea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091797744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.4091797744
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.4077268624
Short name T849
Test name
Test status
Simulation time 4300578941 ps
CPU time 89.67 seconds
Started Jun 30 06:47:21 PM PDT 24
Finished Jun 30 06:48:51 PM PDT 24
Peak memory 251088 kb
Host smart-9b9fc91f-1277-4992-ba5c-1819686ecdbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077268624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.4077268624
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1150788421
Short name T669
Test name
Test status
Simulation time 10810766 ps
CPU time 0.86 seconds
Started Jun 30 06:47:22 PM PDT 24
Finished Jun 30 06:47:23 PM PDT 24
Peak memory 212088 kb
Host smart-a42fab18-2e02-4bf3-a884-611a200d3bfb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150788421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1150788421
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2178939283
Short name T286
Test name
Test status
Simulation time 16260342 ps
CPU time 1.11 seconds
Started Jun 30 06:47:32 PM PDT 24
Finished Jun 30 06:47:34 PM PDT 24
Peak memory 209260 kb
Host smart-a6499659-32d0-4d37-84df-1d203e1dc259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178939283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2178939283
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.565666928
Short name T662
Test name
Test status
Simulation time 196765202 ps
CPU time 8.83 seconds
Started Jun 30 06:47:27 PM PDT 24
Finished Jun 30 06:47:37 PM PDT 24
Peak memory 226252 kb
Host smart-2f6dab98-2824-48d2-af88-1c569a12eb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565666928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.565666928
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.2248632230
Short name T865
Test name
Test status
Simulation time 711694011 ps
CPU time 9.22 seconds
Started Jun 30 06:47:25 PM PDT 24
Finished Jun 30 06:47:35 PM PDT 24
Peak memory 217360 kb
Host smart-9937f926-f4ab-4293-80ee-44542b721f12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248632230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.2248632230
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.809948369
Short name T249
Test name
Test status
Simulation time 105284688 ps
CPU time 2.76 seconds
Started Jun 30 06:47:28 PM PDT 24
Finished Jun 30 06:47:32 PM PDT 24
Peak memory 218340 kb
Host smart-68892a8e-15d3-4460-ba55-c45b0f6a6a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809948369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.809948369
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.1866657312
Short name T599
Test name
Test status
Simulation time 1081115015 ps
CPU time 8.82 seconds
Started Jun 30 06:47:27 PM PDT 24
Finished Jun 30 06:47:36 PM PDT 24
Peak memory 218420 kb
Host smart-e8a00a1f-d802-4b53-966e-55c0c4bc6deb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866657312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.1866657312
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1461745444
Short name T215
Test name
Test status
Simulation time 680406104 ps
CPU time 15.48 seconds
Started Jun 30 06:47:26 PM PDT 24
Finished Jun 30 06:47:42 PM PDT 24
Peak memory 218472 kb
Host smart-0db91c77-4551-4cef-b009-915fda091d60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461745444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.1461745444
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2000726220
Short name T269
Test name
Test status
Simulation time 396178835 ps
CPU time 11.43 seconds
Started Jun 30 06:47:26 PM PDT 24
Finished Jun 30 06:47:38 PM PDT 24
Peak memory 218384 kb
Host smart-f198970b-d1e7-45e8-99be-5dd9bce8ff48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000726220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2000726220
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.53140838
Short name T631
Test name
Test status
Simulation time 302365079 ps
CPU time 9.84 seconds
Started Jun 30 06:47:26 PM PDT 24
Finished Jun 30 06:47:36 PM PDT 24
Peak memory 218480 kb
Host smart-71bc2970-2533-4410-a46e-6ca03c57a2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53140838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.53140838
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3388280153
Short name T479
Test name
Test status
Simulation time 450331277 ps
CPU time 3.01 seconds
Started Jun 30 06:47:28 PM PDT 24
Finished Jun 30 06:47:32 PM PDT 24
Peak memory 224552 kb
Host smart-210963d5-237e-4b18-9e0f-579eb816cbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388280153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3388280153
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3305111881
Short name T525
Test name
Test status
Simulation time 284207327 ps
CPU time 24.31 seconds
Started Jun 30 06:47:32 PM PDT 24
Finished Jun 30 06:47:57 PM PDT 24
Peak memory 246492 kb
Host smart-fd94100c-68c0-465e-a668-042816b496be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305111881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3305111881
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.1116262945
Short name T838
Test name
Test status
Simulation time 87390683 ps
CPU time 8.64 seconds
Started Jun 30 06:47:28 PM PDT 24
Finished Jun 30 06:47:38 PM PDT 24
Peak memory 251076 kb
Host smart-2b008802-7345-4d05-812b-19cbe318b1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116262945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1116262945
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.842807412
Short name T739
Test name
Test status
Simulation time 1301069073 ps
CPU time 41.04 seconds
Started Jun 30 06:47:30 PM PDT 24
Finished Jun 30 06:48:11 PM PDT 24
Peak memory 251080 kb
Host smart-459c085d-57a1-4af0-98cc-71ed35af22b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842807412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.842807412
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.3931228210
Short name T826
Test name
Test status
Simulation time 16600844 ps
CPU time 1.09 seconds
Started Jun 30 06:47:35 PM PDT 24
Finished Jun 30 06:47:36 PM PDT 24
Peak memory 209144 kb
Host smart-69c3d78e-624c-444c-9b39-666a94e25499
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931228210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.3931228210
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.1848819995
Short name T368
Test name
Test status
Simulation time 355601953 ps
CPU time 10.64 seconds
Started Jun 30 06:47:26 PM PDT 24
Finished Jun 30 06:47:38 PM PDT 24
Peak memory 218428 kb
Host smart-eb22e0cd-3bf2-426d-96d9-b8367dd15584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848819995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.1848819995
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1222644167
Short name T549
Test name
Test status
Simulation time 106529973 ps
CPU time 1.4 seconds
Started Jun 30 06:47:26 PM PDT 24
Finished Jun 30 06:47:28 PM PDT 24
Peak memory 217260 kb
Host smart-385fc6e7-3562-42b0-b9c7-a1aca4af21e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222644167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1222644167
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.397144034
Short name T861
Test name
Test status
Simulation time 184758081 ps
CPU time 4.26 seconds
Started Jun 30 06:47:27 PM PDT 24
Finished Jun 30 06:47:32 PM PDT 24
Peak memory 218436 kb
Host smart-3493a1f5-b1cb-45fc-8cf7-585eb68bfd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397144034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.397144034
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.1505265011
Short name T254
Test name
Test status
Simulation time 481162571 ps
CPU time 11.65 seconds
Started Jun 30 06:47:32 PM PDT 24
Finished Jun 30 06:47:44 PM PDT 24
Peak memory 226236 kb
Host smart-f31d0992-c091-40ba-94fb-e7884122594c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505265011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1505265011
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1856408707
Short name T542
Test name
Test status
Simulation time 887793688 ps
CPU time 7.78 seconds
Started Jun 30 06:47:28 PM PDT 24
Finished Jun 30 06:47:37 PM PDT 24
Peak memory 218536 kb
Host smart-937a0b03-ad0b-4b10-98ac-e3a269f798c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856408707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.1856408707
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.2324395774
Short name T676
Test name
Test status
Simulation time 292247689 ps
CPU time 8.65 seconds
Started Jun 30 06:47:28 PM PDT 24
Finished Jun 30 06:47:38 PM PDT 24
Peak memory 226244 kb
Host smart-ec010779-cf61-4634-9d9c-92742a360657
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324395774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
2324395774
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.1480292492
Short name T476
Test name
Test status
Simulation time 2145020402 ps
CPU time 10.89 seconds
Started Jun 30 06:47:26 PM PDT 24
Finished Jun 30 06:47:37 PM PDT 24
Peak memory 218416 kb
Host smart-9790ea92-0c39-459c-85df-5309b1dc8147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480292492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1480292492
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.1798225980
Short name T557
Test name
Test status
Simulation time 206784710 ps
CPU time 2.7 seconds
Started Jun 30 06:47:26 PM PDT 24
Finished Jun 30 06:47:29 PM PDT 24
Peak memory 217924 kb
Host smart-528192ed-3f9e-4999-b87e-2144d87f4e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798225980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.1798225980
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.2859926930
Short name T331
Test name
Test status
Simulation time 502242785 ps
CPU time 33.95 seconds
Started Jun 30 06:47:27 PM PDT 24
Finished Jun 30 06:48:02 PM PDT 24
Peak memory 251132 kb
Host smart-4031c3cf-0b3c-44cb-8d7a-71283d62eaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859926930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2859926930
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2338682778
Short name T805
Test name
Test status
Simulation time 81751887 ps
CPU time 2.9 seconds
Started Jun 30 06:47:28 PM PDT 24
Finished Jun 30 06:47:31 PM PDT 24
Peak memory 224156 kb
Host smart-cd798643-432a-4e0d-baf7-d1c6c70e379c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338682778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2338682778
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3855645404
Short name T791
Test name
Test status
Simulation time 8161484065 ps
CPU time 239.85 seconds
Started Jun 30 06:47:33 PM PDT 24
Finished Jun 30 06:51:34 PM PDT 24
Peak memory 293784 kb
Host smart-49c42df6-5550-4b61-a37f-16819b0529f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855645404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3855645404
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1358188917
Short name T514
Test name
Test status
Simulation time 30234850 ps
CPU time 1.09 seconds
Started Jun 30 06:47:26 PM PDT 24
Finished Jun 30 06:47:28 PM PDT 24
Peak memory 218104 kb
Host smart-1ec3c58f-3a2a-4d56-8a92-d1fe567da6e1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358188917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1358188917
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.3591063376
Short name T834
Test name
Test status
Simulation time 22555720 ps
CPU time 1.2 seconds
Started Jun 30 06:47:36 PM PDT 24
Finished Jun 30 06:47:38 PM PDT 24
Peak memory 209196 kb
Host smart-deb870c4-30b3-4f64-8388-f5cf0e574207
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591063376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.3591063376
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3849110916
Short name T262
Test name
Test status
Simulation time 467057555 ps
CPU time 9.24 seconds
Started Jun 30 06:47:37 PM PDT 24
Finished Jun 30 06:47:46 PM PDT 24
Peak memory 218464 kb
Host smart-8bffa764-27e4-435b-8840-38df457c45bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849110916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3849110916
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.3593609776
Short name T417
Test name
Test status
Simulation time 696134384 ps
CPU time 5.52 seconds
Started Jun 30 06:47:32 PM PDT 24
Finished Jun 30 06:47:38 PM PDT 24
Peak memory 217228 kb
Host smart-e6075ae4-3b5c-4cef-b3e0-b017d9ccc326
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593609776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.3593609776
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.3368119362
Short name T637
Test name
Test status
Simulation time 246855969 ps
CPU time 2.46 seconds
Started Jun 30 06:47:33 PM PDT 24
Finished Jun 30 06:47:36 PM PDT 24
Peak memory 218440 kb
Host smart-c2156595-319e-4562-b738-256aaee2079b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368119362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3368119362
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.1874582960
Short name T12
Test name
Test status
Simulation time 233737477 ps
CPU time 11.53 seconds
Started Jun 30 06:47:32 PM PDT 24
Finished Jun 30 06:47:44 PM PDT 24
Peak memory 218404 kb
Host smart-740008f9-a814-4a76-8b90-9e58ce5b6f2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874582960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1874582960
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1799648762
Short name T652
Test name
Test status
Simulation time 415611441 ps
CPU time 17.02 seconds
Started Jun 30 06:47:33 PM PDT 24
Finished Jun 30 06:47:51 PM PDT 24
Peak memory 218408 kb
Host smart-eb6a1ade-2cbe-454d-aaa5-16f8c492fc67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799648762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1799648762
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1368368804
Short name T664
Test name
Test status
Simulation time 672838785 ps
CPU time 12.57 seconds
Started Jun 30 06:47:33 PM PDT 24
Finished Jun 30 06:47:46 PM PDT 24
Peak memory 218676 kb
Host smart-34f508cf-0c13-42e7-8ca0-afb5efa432c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368368804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
1368368804
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.3211991573
Short name T781
Test name
Test status
Simulation time 536142220 ps
CPU time 11.28 seconds
Started Jun 30 06:47:35 PM PDT 24
Finished Jun 30 06:47:46 PM PDT 24
Peak memory 218484 kb
Host smart-e011b43d-1ce1-4b8a-9c77-6089f5217a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211991573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3211991573
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2701120832
Short name T835
Test name
Test status
Simulation time 35575419 ps
CPU time 1.78 seconds
Started Jun 30 06:47:33 PM PDT 24
Finished Jun 30 06:47:35 PM PDT 24
Peak memory 217916 kb
Host smart-3c0285c8-aa9d-4e80-a65c-f6773cb8e265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701120832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2701120832
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.36764
Short name T31
Test name
Test status
Simulation time 310342412 ps
CPU time 26.27 seconds
Started Jun 30 06:47:34 PM PDT 24
Finished Jun 30 06:48:01 PM PDT 24
Peak memory 246172 kb
Host smart-d3d390fa-0235-4c1a-ab0c-65a76fa77192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.36764
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.573504699
Short name T230
Test name
Test status
Simulation time 107873719 ps
CPU time 2.8 seconds
Started Jun 30 06:47:34 PM PDT 24
Finished Jun 30 06:47:37 PM PDT 24
Peak memory 218420 kb
Host smart-ba3e1181-a534-42ce-bded-c2853b565f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573504699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.573504699
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1773558373
Short name T757
Test name
Test status
Simulation time 13734707414 ps
CPU time 213.49 seconds
Started Jun 30 06:47:37 PM PDT 24
Finished Jun 30 06:51:11 PM PDT 24
Peak memory 250464 kb
Host smart-e37db356-1c76-4e05-bf88-968fb22ca6db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773558373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1773558373
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.465097381
Short name T375
Test name
Test status
Simulation time 56293848 ps
CPU time 0.96 seconds
Started Jun 30 06:47:32 PM PDT 24
Finished Jun 30 06:47:33 PM PDT 24
Peak memory 212064 kb
Host smart-6020b2dc-e1ae-4b2c-bd58-fdbe7d57497d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465097381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct
rl_volatile_unlock_smoke.465097381
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.2671247119
Short name T168
Test name
Test status
Simulation time 37705334 ps
CPU time 0.94 seconds
Started Jun 30 06:46:10 PM PDT 24
Finished Jun 30 06:46:12 PM PDT 24
Peak memory 209208 kb
Host smart-f8ce3bc0-07cd-470c-94bf-2d710ad17022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671247119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2671247119
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.2603560849
Short name T288
Test name
Test status
Simulation time 25113644 ps
CPU time 0.82 seconds
Started Jun 30 06:46:10 PM PDT 24
Finished Jun 30 06:46:12 PM PDT 24
Peak memory 209068 kb
Host smart-9700551e-3b66-40f2-8e34-95b4b3ee62a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603560849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2603560849
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.193847731
Short name T576
Test name
Test status
Simulation time 276966186 ps
CPU time 14.44 seconds
Started Jun 30 06:46:05 PM PDT 24
Finished Jun 30 06:46:20 PM PDT 24
Peak memory 226368 kb
Host smart-0f3d46db-f721-4a15-bc7a-6b10725d84c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193847731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.193847731
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.1434105818
Short name T517
Test name
Test status
Simulation time 304622846 ps
CPU time 5.07 seconds
Started Jun 30 06:46:05 PM PDT 24
Finished Jun 30 06:46:12 PM PDT 24
Peak memory 217960 kb
Host smart-4acf8883-6c6c-49f4-980a-59c6c0d26554
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434105818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.1434105818
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.1915714126
Short name T811
Test name
Test status
Simulation time 10172398831 ps
CPU time 20.67 seconds
Started Jun 30 06:46:07 PM PDT 24
Finished Jun 30 06:46:29 PM PDT 24
Peak memory 226276 kb
Host smart-0b155231-5c28-4cf2-9ec2-3d30bf1c700b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915714126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.1915714126
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.1776694930
Short name T372
Test name
Test status
Simulation time 720968632 ps
CPU time 2.45 seconds
Started Jun 30 06:46:11 PM PDT 24
Finished Jun 30 06:46:15 PM PDT 24
Peak memory 217544 kb
Host smart-da2755cc-77f7-4d99-b766-e9cf34eb62b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776694930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.1
776694930
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.2613623996
Short name T626
Test name
Test status
Simulation time 4421930670 ps
CPU time 9.11 seconds
Started Jun 30 06:46:05 PM PDT 24
Finished Jun 30 06:46:15 PM PDT 24
Peak memory 226272 kb
Host smart-9f3ae89c-e71a-427e-b498-14f27834810c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613623996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.2613623996
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1681020281
Short name T573
Test name
Test status
Simulation time 1639554204 ps
CPU time 22.29 seconds
Started Jun 30 06:46:14 PM PDT 24
Finished Jun 30 06:46:37 PM PDT 24
Peak memory 217852 kb
Host smart-c02cb454-e1de-4685-babb-4e9293b921e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681020281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1681020281
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.675640444
Short name T162
Test name
Test status
Simulation time 1033617115 ps
CPU time 3.53 seconds
Started Jun 30 06:46:05 PM PDT 24
Finished Jun 30 06:46:11 PM PDT 24
Peak memory 217928 kb
Host smart-aea69a1d-17a9-4053-9959-382133db33da
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675640444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.675640444
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1539462765
Short name T333
Test name
Test status
Simulation time 38332442521 ps
CPU time 56.82 seconds
Started Jun 30 06:46:08 PM PDT 24
Finished Jun 30 06:47:06 PM PDT 24
Peak memory 275776 kb
Host smart-7ef5c50a-bd51-4f21-bcb7-b2d34f07b908
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539462765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.1539462765
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.2182732362
Short name T471
Test name
Test status
Simulation time 10569744932 ps
CPU time 22 seconds
Started Jun 30 06:46:05 PM PDT 24
Finished Jun 30 06:46:28 PM PDT 24
Peak memory 224112 kb
Host smart-ea334a93-d46c-4603-a1f0-de829dbd6388
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182732362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.2182732362
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.2590577739
Short name T741
Test name
Test status
Simulation time 419071154 ps
CPU time 3.81 seconds
Started Jun 30 06:46:04 PM PDT 24
Finished Jun 30 06:46:08 PM PDT 24
Peak memory 218380 kb
Host smart-0ef54b54-703a-4ced-83d5-0f76be876243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590577739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.2590577739
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.2284944611
Short name T74
Test name
Test status
Simulation time 194371661 ps
CPU time 8.17 seconds
Started Jun 30 06:46:05 PM PDT 24
Finished Jun 30 06:46:15 PM PDT 24
Peak memory 217908 kb
Host smart-27b68965-a50d-461f-83ab-6889f24e1fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284944611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.2284944611
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1260091041
Short name T47
Test name
Test status
Simulation time 109879906 ps
CPU time 23.73 seconds
Started Jun 30 06:46:12 PM PDT 24
Finished Jun 30 06:46:37 PM PDT 24
Peak memory 268220 kb
Host smart-51844d3c-22ab-480e-8afc-9f53fc678b60
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260091041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1260091041
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.4154827043
Short name T493
Test name
Test status
Simulation time 601454384 ps
CPU time 10.71 seconds
Started Jun 30 06:46:09 PM PDT 24
Finished Jun 30 06:46:21 PM PDT 24
Peak memory 226256 kb
Host smart-30ac2dfc-1240-46d3-9d41-bca68746efea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154827043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.4154827043
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.1915649749
Short name T600
Test name
Test status
Simulation time 371162348 ps
CPU time 10.31 seconds
Started Jun 30 06:46:09 PM PDT 24
Finished Jun 30 06:46:20 PM PDT 24
Peak memory 218452 kb
Host smart-ef01d39b-b0e4-40a7-837a-a6169d0c093e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915649749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.1915649749
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1075124141
Short name T845
Test name
Test status
Simulation time 272313551 ps
CPU time 7.89 seconds
Started Jun 30 06:46:14 PM PDT 24
Finished Jun 30 06:46:23 PM PDT 24
Peak memory 218344 kb
Host smart-7f187677-54dc-4eeb-8cad-dd224a2109b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075124141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
075124141
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.1799812535
Short name T717
Test name
Test status
Simulation time 745803907 ps
CPU time 13.63 seconds
Started Jun 30 06:46:06 PM PDT 24
Finished Jun 30 06:46:21 PM PDT 24
Peak memory 218616 kb
Host smart-9d4e7c0f-5784-4571-8aa7-66c57bf88c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799812535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1799812535
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.1510692845
Short name T326
Test name
Test status
Simulation time 76786678 ps
CPU time 3.04 seconds
Started Jun 30 06:46:09 PM PDT 24
Finished Jun 30 06:46:12 PM PDT 24
Peak memory 217840 kb
Host smart-9ee492db-4b8f-4336-a668-a5821cd30a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510692845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1510692845
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3584838108
Short name T244
Test name
Test status
Simulation time 1007172990 ps
CPU time 28.12 seconds
Started Jun 30 06:46:04 PM PDT 24
Finished Jun 30 06:46:34 PM PDT 24
Peak memory 251136 kb
Host smart-a27b12d1-050f-46b2-a715-92b47ac8f894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584838108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3584838108
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.2707247983
Short name T684
Test name
Test status
Simulation time 457171956 ps
CPU time 8.07 seconds
Started Jun 30 06:46:03 PM PDT 24
Finished Jun 30 06:46:12 PM PDT 24
Peak memory 250680 kb
Host smart-eaa0030d-1ce8-449c-ad66-ad5aca1cba89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707247983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.2707247983
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1955062162
Short name T53
Test name
Test status
Simulation time 11014089584 ps
CPU time 189.71 seconds
Started Jun 30 06:46:11 PM PDT 24
Finished Jun 30 06:49:23 PM PDT 24
Peak memory 283792 kb
Host smart-8a14a52f-2e33-4031-8dd4-3c87f6548ca7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955062162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1955062162
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.3949894519
Short name T784
Test name
Test status
Simulation time 25857314 ps
CPU time 0.88 seconds
Started Jun 30 06:46:05 PM PDT 24
Finished Jun 30 06:46:08 PM PDT 24
Peak memory 212200 kb
Host smart-f0193b3e-b44c-4fc2-af5f-b1ea0c2a78f3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949894519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.3949894519
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1502580307
Short name T782
Test name
Test status
Simulation time 52709036 ps
CPU time 1.15 seconds
Started Jun 30 06:47:40 PM PDT 24
Finished Jun 30 06:47:42 PM PDT 24
Peak memory 209468 kb
Host smart-ab78c99a-2250-4fd4-81c8-2fc54c4b5988
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502580307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1502580307
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.4215800288
Short name T666
Test name
Test status
Simulation time 987121201 ps
CPU time 15 seconds
Started Jun 30 06:47:40 PM PDT 24
Finished Jun 30 06:47:56 PM PDT 24
Peak memory 218412 kb
Host smart-d83bd0ad-924b-4aa2-baa8-ef0841fa8519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215800288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.4215800288
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.118521065
Short name T828
Test name
Test status
Simulation time 951814504 ps
CPU time 22.22 seconds
Started Jun 30 06:47:39 PM PDT 24
Finished Jun 30 06:48:02 PM PDT 24
Peak memory 217696 kb
Host smart-7309f5b8-d57f-424b-bfe3-27dee360b45c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118521065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.118521065
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.749559611
Short name T140
Test name
Test status
Simulation time 134862471 ps
CPU time 1.7 seconds
Started Jun 30 06:47:39 PM PDT 24
Finished Jun 30 06:47:41 PM PDT 24
Peak memory 222076 kb
Host smart-8aec535e-f72b-4867-921b-0f447a392a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749559611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.749559611
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.586297344
Short name T495
Test name
Test status
Simulation time 715932793 ps
CPU time 19.22 seconds
Started Jun 30 06:47:39 PM PDT 24
Finished Jun 30 06:47:58 PM PDT 24
Peak memory 219004 kb
Host smart-37035b4d-8838-477c-95fe-67176310943a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586297344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.586297344
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1351926189
Short name T170
Test name
Test status
Simulation time 1784656009 ps
CPU time 11.91 seconds
Started Jun 30 06:47:38 PM PDT 24
Finished Jun 30 06:47:50 PM PDT 24
Peak memory 218548 kb
Host smart-2f6ec48f-a31e-48c5-b503-eb5920c79194
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351926189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1351926189
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.2542232034
Short name T751
Test name
Test status
Simulation time 246877931 ps
CPU time 9.77 seconds
Started Jun 30 06:47:40 PM PDT 24
Finished Jun 30 06:47:50 PM PDT 24
Peak memory 226216 kb
Host smart-396a2dc4-1d03-4b2a-8a64-010fea98b0ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542232034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
2542232034
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.4249797681
Short name T142
Test name
Test status
Simulation time 245652529 ps
CPU time 8.78 seconds
Started Jun 30 06:47:40 PM PDT 24
Finished Jun 30 06:47:49 PM PDT 24
Peak memory 218580 kb
Host smart-9c5d2486-4c39-4a6d-89c0-7399e67bb0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249797681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.4249797681
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.49889742
Short name T507
Test name
Test status
Simulation time 63875907 ps
CPU time 3.45 seconds
Started Jun 30 06:47:34 PM PDT 24
Finished Jun 30 06:47:38 PM PDT 24
Peak memory 215164 kb
Host smart-0b3f8639-ccef-489e-a9ce-2a017a09baae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49889742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.49889742
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.3680012640
Short name T271
Test name
Test status
Simulation time 270989072 ps
CPU time 28.85 seconds
Started Jun 30 06:47:43 PM PDT 24
Finished Jun 30 06:48:13 PM PDT 24
Peak memory 251140 kb
Host smart-08c9eacf-45c9-4bb5-947b-f6a67cf75a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680012640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3680012640
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.1196495307
Short name T146
Test name
Test status
Simulation time 116144318 ps
CPU time 8.65 seconds
Started Jun 30 06:47:39 PM PDT 24
Finished Jun 30 06:47:48 PM PDT 24
Peak memory 251128 kb
Host smart-081eac0c-5e5f-43bf-b9cd-7d40b6d07d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196495307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.1196495307
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.501725696
Short name T501
Test name
Test status
Simulation time 3367655726 ps
CPU time 50.98 seconds
Started Jun 30 06:47:41 PM PDT 24
Finished Jun 30 06:48:33 PM PDT 24
Peak memory 226320 kb
Host smart-f4b60b19-5567-44f2-8096-88ad394613d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501725696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.501725696
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3015095924
Short name T645
Test name
Test status
Simulation time 11624897 ps
CPU time 0.85 seconds
Started Jun 30 06:47:43 PM PDT 24
Finished Jun 30 06:47:44 PM PDT 24
Peak memory 212116 kb
Host smart-a482f3dc-257b-41b7-9c0d-ff2ef584e114
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015095924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3015095924
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.1872065122
Short name T291
Test name
Test status
Simulation time 97777956 ps
CPU time 1.08 seconds
Started Jun 30 06:47:38 PM PDT 24
Finished Jun 30 06:47:39 PM PDT 24
Peak memory 209152 kb
Host smart-b3c03d9e-880d-4776-b894-a506dfec0266
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872065122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1872065122
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1975766023
Short name T515
Test name
Test status
Simulation time 332656855 ps
CPU time 15.85 seconds
Started Jun 30 06:47:46 PM PDT 24
Finished Jun 30 06:48:03 PM PDT 24
Peak memory 226256 kb
Host smart-e9cdee73-d116-4695-8d3b-5f283acf89be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975766023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1975766023
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.468816938
Short name T25
Test name
Test status
Simulation time 1406359081 ps
CPU time 8.31 seconds
Started Jun 30 06:47:40 PM PDT 24
Finished Jun 30 06:47:49 PM PDT 24
Peak memory 217352 kb
Host smart-dc3bdb7c-78f8-4627-ae78-7eb3903bf89b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468816938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.468816938
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3076744447
Short name T699
Test name
Test status
Simulation time 265527335 ps
CPU time 2.68 seconds
Started Jun 30 06:47:38 PM PDT 24
Finished Jun 30 06:47:41 PM PDT 24
Peak memory 218400 kb
Host smart-de002a5b-56cf-4266-967c-270635b03c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076744447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3076744447
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.528261581
Short name T755
Test name
Test status
Simulation time 461821309 ps
CPU time 13.09 seconds
Started Jun 30 06:47:41 PM PDT 24
Finished Jun 30 06:47:55 PM PDT 24
Peak memory 220176 kb
Host smart-83cbbdb9-784a-495a-a9f1-1bae56d8c38c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528261581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.528261581
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1434274826
Short name T749
Test name
Test status
Simulation time 896624360 ps
CPU time 13.16 seconds
Started Jun 30 06:47:40 PM PDT 24
Finished Jun 30 06:47:54 PM PDT 24
Peak memory 218524 kb
Host smart-a5a9b68f-e852-47c7-9cfd-d7d1e1fc6845
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434274826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.1434274826
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.4238274700
Short name T258
Test name
Test status
Simulation time 995014722 ps
CPU time 11.85 seconds
Started Jun 30 06:47:40 PM PDT 24
Finished Jun 30 06:47:52 PM PDT 24
Peak memory 218448 kb
Host smart-99046866-7a89-4bc1-a2c8-627f67a238db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238274700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
4238274700
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.663279425
Short name T458
Test name
Test status
Simulation time 989081167 ps
CPU time 8.96 seconds
Started Jun 30 06:47:41 PM PDT 24
Finished Jun 30 06:47:51 PM PDT 24
Peak memory 226196 kb
Host smart-b7684f97-2a91-4647-8a25-f82b0f5ef1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663279425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.663279425
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.2971913905
Short name T69
Test name
Test status
Simulation time 619172479 ps
CPU time 3.21 seconds
Started Jun 30 06:47:41 PM PDT 24
Finished Jun 30 06:47:45 PM PDT 24
Peak memory 223976 kb
Host smart-e4db4f60-a1a9-4dbd-a604-37fb87e3d3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971913905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2971913905
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1238012061
Short name T681
Test name
Test status
Simulation time 1406763628 ps
CPU time 38.23 seconds
Started Jun 30 06:47:41 PM PDT 24
Finished Jun 30 06:48:20 PM PDT 24
Peak memory 251084 kb
Host smart-8262c302-68b7-490d-a6a8-55570ffe2ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238012061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1238012061
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3851116875
Short name T725
Test name
Test status
Simulation time 126377264 ps
CPU time 7.81 seconds
Started Jun 30 06:47:42 PM PDT 24
Finished Jun 30 06:47:50 PM PDT 24
Peak memory 251164 kb
Host smart-d6fc80ce-04f6-4404-8344-6cdff73ac368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851116875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3851116875
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.964380228
Short name T38
Test name
Test status
Simulation time 9892164496 ps
CPU time 120.6 seconds
Started Jun 30 06:47:43 PM PDT 24
Finished Jun 30 06:49:44 PM PDT 24
Peak memory 270812 kb
Host smart-7629d8cf-2b21-4006-9e55-d1bc882fa514
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964380228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.964380228
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1549330719
Short name T758
Test name
Test status
Simulation time 14464358 ps
CPU time 0.88 seconds
Started Jun 30 06:47:37 PM PDT 24
Finished Jun 30 06:47:38 PM PDT 24
Peak memory 212076 kb
Host smart-f4df401c-34c8-4c95-b3e0-e0d8360a0b4e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549330719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1549330719
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3465757556
Short name T62
Test name
Test status
Simulation time 17258866 ps
CPU time 0.95 seconds
Started Jun 30 06:47:50 PM PDT 24
Finished Jun 30 06:47:52 PM PDT 24
Peak memory 209044 kb
Host smart-dfdd48ff-eed5-43d6-8335-400cabbb3990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465757556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3465757556
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.1417430767
Short name T670
Test name
Test status
Simulation time 730265310 ps
CPU time 22.71 seconds
Started Jun 30 06:47:46 PM PDT 24
Finished Jun 30 06:48:09 PM PDT 24
Peak memory 226252 kb
Host smart-77fee925-187a-40cb-9fdc-4e0d10e83b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417430767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.1417430767
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.3249048498
Short name T693
Test name
Test status
Simulation time 1818578490 ps
CPU time 2.88 seconds
Started Jun 30 06:47:47 PM PDT 24
Finished Jun 30 06:47:51 PM PDT 24
Peak memory 217344 kb
Host smart-6eccc921-9637-48d0-9619-b7fdc1f16982
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249048498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.3249048498
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.1552061629
Short name T570
Test name
Test status
Simulation time 54944272 ps
CPU time 2.09 seconds
Started Jun 30 06:47:45 PM PDT 24
Finished Jun 30 06:47:48 PM PDT 24
Peak memory 218436 kb
Host smart-1badab9d-8f95-472d-a095-33ad81d7097f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552061629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1552061629
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.2371683020
Short name T174
Test name
Test status
Simulation time 1762198176 ps
CPU time 14.2 seconds
Started Jun 30 06:47:47 PM PDT 24
Finished Jun 30 06:48:02 PM PDT 24
Peak memory 226208 kb
Host smart-d85b3c4b-d1f5-401f-b769-b11c4ecc19e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371683020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.2371683020
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.851560448
Short name T173
Test name
Test status
Simulation time 787904694 ps
CPU time 9.97 seconds
Started Jun 30 06:47:54 PM PDT 24
Finished Jun 30 06:48:04 PM PDT 24
Peak memory 218464 kb
Host smart-93ebd20c-5a80-4c8b-bdf2-ade31b138930
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851560448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_di
gest.851560448
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.2963136643
Short name T234
Test name
Test status
Simulation time 1158942461 ps
CPU time 8.28 seconds
Started Jun 30 06:47:47 PM PDT 24
Finished Jun 30 06:47:56 PM PDT 24
Peak memory 226236 kb
Host smart-fb7931eb-e9cf-48e6-bcf7-578b9137a61d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963136643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
2963136643
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.2936199545
Short name T843
Test name
Test status
Simulation time 3184205849 ps
CPU time 10.04 seconds
Started Jun 30 06:47:48 PM PDT 24
Finished Jun 30 06:47:59 PM PDT 24
Peak memory 218660 kb
Host smart-f58e3a9d-8b1b-4d3b-b7f4-d6e85ef9a934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936199545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.2936199545
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.3351813431
Short name T304
Test name
Test status
Simulation time 91494879 ps
CPU time 5.4 seconds
Started Jun 30 06:47:39 PM PDT 24
Finished Jun 30 06:47:45 PM PDT 24
Peak memory 217868 kb
Host smart-8cb8225d-f558-4228-9127-b1156df5c166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351813431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3351813431
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.2795985015
Short name T685
Test name
Test status
Simulation time 1263100409 ps
CPU time 31.65 seconds
Started Jun 30 06:47:40 PM PDT 24
Finished Jun 30 06:48:12 PM PDT 24
Peak memory 251124 kb
Host smart-e954b63f-8737-4ab1-9abf-b401e04dc65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795985015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.2795985015
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1300487120
Short name T327
Test name
Test status
Simulation time 50807126 ps
CPU time 3.25 seconds
Started Jun 30 06:47:48 PM PDT 24
Finished Jun 30 06:47:52 PM PDT 24
Peak memory 226512 kb
Host smart-5ad7756b-7894-4e60-92f8-4cce14d75ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300487120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1300487120
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2931538787
Short name T864
Test name
Test status
Simulation time 33966967 ps
CPU time 0.83 seconds
Started Jun 30 06:47:42 PM PDT 24
Finished Jun 30 06:47:43 PM PDT 24
Peak memory 212124 kb
Host smart-5a7e155b-a3e7-490a-8160-bdf74a94e0e7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931538787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.2931538787
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3731620080
Short name T438
Test name
Test status
Simulation time 23865090 ps
CPU time 1.25 seconds
Started Jun 30 06:47:47 PM PDT 24
Finished Jun 30 06:47:48 PM PDT 24
Peak memory 209168 kb
Host smart-95723a78-fe18-4a54-a157-8e0297ba6771
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731620080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3731620080
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3227372559
Short name T695
Test name
Test status
Simulation time 1233060345 ps
CPU time 8.71 seconds
Started Jun 30 06:47:46 PM PDT 24
Finished Jun 30 06:47:56 PM PDT 24
Peak memory 218436 kb
Host smart-05a528f9-81a5-4346-a675-5edb8ef7ab5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227372559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3227372559
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1503903932
Short name T415
Test name
Test status
Simulation time 229359897 ps
CPU time 2.89 seconds
Started Jun 30 06:47:46 PM PDT 24
Finished Jun 30 06:47:50 PM PDT 24
Peak memory 217544 kb
Host smart-7cc811b1-8c3e-478a-9f2d-f7aa857dc978
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503903932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1503903932
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.490111434
Short name T361
Test name
Test status
Simulation time 831872222 ps
CPU time 3.13 seconds
Started Jun 30 06:47:50 PM PDT 24
Finished Jun 30 06:47:54 PM PDT 24
Peak memory 218440 kb
Host smart-f536bd8d-e992-4e81-b3d0-ad2f6cceadc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490111434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.490111434
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1602960553
Short name T402
Test name
Test status
Simulation time 509859327 ps
CPU time 10.26 seconds
Started Jun 30 06:47:47 PM PDT 24
Finished Jun 30 06:47:58 PM PDT 24
Peak memory 219048 kb
Host smart-3c50da5f-996e-4310-a271-998c941ce6fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602960553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1602960553
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1427897166
Short name T144
Test name
Test status
Simulation time 1748894840 ps
CPU time 11.2 seconds
Started Jun 30 06:47:48 PM PDT 24
Finished Jun 30 06:48:00 PM PDT 24
Peak memory 218468 kb
Host smart-f58415fe-cebe-4106-97e1-599d7f3546e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427897166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.1427897166
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.56322507
Short name T54
Test name
Test status
Simulation time 1203498669 ps
CPU time 11.39 seconds
Started Jun 30 06:47:47 PM PDT 24
Finished Jun 30 06:47:59 PM PDT 24
Peak memory 218452 kb
Host smart-9062d70c-8348-4f48-a01d-a821d241a3bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56322507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.56322507
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.3491124604
Short name T867
Test name
Test status
Simulation time 380962630 ps
CPU time 9.35 seconds
Started Jun 30 06:47:46 PM PDT 24
Finished Jun 30 06:47:56 PM PDT 24
Peak memory 218508 kb
Host smart-de85edae-a3bd-4003-9394-9337024ae52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491124604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3491124604
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.2710583792
Short name T773
Test name
Test status
Simulation time 123248268 ps
CPU time 3.51 seconds
Started Jun 30 06:47:54 PM PDT 24
Finished Jun 30 06:47:58 PM PDT 24
Peak memory 217936 kb
Host smart-6deef8aa-a438-481d-9ec9-7f2fe9999505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710583792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2710583792
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.1156318237
Short name T607
Test name
Test status
Simulation time 445936852 ps
CPU time 26.6 seconds
Started Jun 30 06:47:48 PM PDT 24
Finished Jun 30 06:48:15 PM PDT 24
Peak memory 251116 kb
Host smart-7b75c500-620d-4999-a59a-d2a475d6aa2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156318237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.1156318237
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1481992269
Short name T363
Test name
Test status
Simulation time 76221215 ps
CPU time 6.84 seconds
Started Jun 30 06:47:48 PM PDT 24
Finished Jun 30 06:47:56 PM PDT 24
Peak memory 250492 kb
Host smart-c7ba91ae-9710-40ad-91e0-3c5d76fa4084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481992269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1481992269
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.981038527
Short name T618
Test name
Test status
Simulation time 21486524006 ps
CPU time 376.88 seconds
Started Jun 30 06:47:49 PM PDT 24
Finished Jun 30 06:54:06 PM PDT 24
Peak memory 251272 kb
Host smart-afbcbf34-a969-406d-8a9c-fd4a47e3e2c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981038527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.981038527
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1802682075
Short name T724
Test name
Test status
Simulation time 24644148 ps
CPU time 0.92 seconds
Started Jun 30 06:47:48 PM PDT 24
Finished Jun 30 06:47:50 PM PDT 24
Peak memory 212044 kb
Host smart-ead546de-9f19-4b7e-ba9d-4dd8fbcea00c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802682075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.1802682075
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1654157026
Short name T82
Test name
Test status
Simulation time 28544213 ps
CPU time 0.99 seconds
Started Jun 30 06:47:55 PM PDT 24
Finished Jun 30 06:47:57 PM PDT 24
Peak memory 209172 kb
Host smart-df458254-9079-4eea-835e-48cd42d4baae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654157026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1654157026
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.1899860326
Short name T419
Test name
Test status
Simulation time 346242639 ps
CPU time 15.7 seconds
Started Jun 30 06:47:49 PM PDT 24
Finished Jun 30 06:48:05 PM PDT 24
Peak memory 218448 kb
Host smart-c6f47b63-32d6-40d1-bf90-8fd5438ca375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899860326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1899860326
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.2275716043
Short name T762
Test name
Test status
Simulation time 554758106 ps
CPU time 2.02 seconds
Started Jun 30 06:47:57 PM PDT 24
Finished Jun 30 06:48:01 PM PDT 24
Peak memory 217388 kb
Host smart-257aece9-e14a-41fc-98fa-73cd9001fa93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275716043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.2275716043
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.152428965
Short name T554
Test name
Test status
Simulation time 90665646 ps
CPU time 2.34 seconds
Started Jun 30 06:47:47 PM PDT 24
Finished Jun 30 06:47:50 PM PDT 24
Peak memory 222412 kb
Host smart-2c76b9ea-f982-4b39-985f-b8cca82baf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152428965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.152428965
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.634553906
Short name T216
Test name
Test status
Simulation time 1061872009 ps
CPU time 10.79 seconds
Started Jun 30 06:47:55 PM PDT 24
Finished Jun 30 06:48:07 PM PDT 24
Peak memory 226244 kb
Host smart-ab428d51-7dae-4343-b5b8-f174eeec6472
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634553906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.634553906
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.431763897
Short name T767
Test name
Test status
Simulation time 808670129 ps
CPU time 10.46 seconds
Started Jun 30 06:47:55 PM PDT 24
Finished Jun 30 06:48:06 PM PDT 24
Peak memory 218452 kb
Host smart-84ea438e-be93-45e5-9eef-3a0db3204ee4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431763897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.431763897
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.1397794136
Short name T451
Test name
Test status
Simulation time 524261120 ps
CPU time 9.54 seconds
Started Jun 30 06:47:57 PM PDT 24
Finished Jun 30 06:48:09 PM PDT 24
Peak memory 218424 kb
Host smart-97814d9d-db75-4ae7-bee6-c3a438ccea3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397794136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
1397794136
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.403677291
Short name T46
Test name
Test status
Simulation time 1396817590 ps
CPU time 10.92 seconds
Started Jun 30 06:47:48 PM PDT 24
Finished Jun 30 06:48:00 PM PDT 24
Peak memory 218480 kb
Host smart-0f45398b-ee76-4c07-8198-876d0a06a361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403677291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.403677291
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.3179727723
Short name T472
Test name
Test status
Simulation time 17664649 ps
CPU time 1.2 seconds
Started Jun 30 06:47:48 PM PDT 24
Finished Jun 30 06:47:50 PM PDT 24
Peak memory 213848 kb
Host smart-4a33c253-0e19-4bb2-947d-e7e0e62acb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179727723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3179727723
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.2917955873
Short name T689
Test name
Test status
Simulation time 1556120813 ps
CPU time 16.93 seconds
Started Jun 30 06:47:49 PM PDT 24
Finished Jun 30 06:48:07 PM PDT 24
Peak memory 251148 kb
Host smart-44212e86-3a04-4013-a575-664327176441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917955873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.2917955873
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.3652256861
Short name T344
Test name
Test status
Simulation time 95635437 ps
CPU time 7.8 seconds
Started Jun 30 06:47:47 PM PDT 24
Finished Jun 30 06:47:55 PM PDT 24
Peak memory 250600 kb
Host smart-3d40f5e0-b809-41e4-9c7f-dbd8c34acf80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652256861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3652256861
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3319972409
Short name T429
Test name
Test status
Simulation time 5286791731 ps
CPU time 57.29 seconds
Started Jun 30 06:47:55 PM PDT 24
Finished Jun 30 06:48:54 PM PDT 24
Peak memory 226112 kb
Host smart-d3a88196-247e-427d-a0d0-9cec9df1b9de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319972409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3319972409
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1567629052
Short name T771
Test name
Test status
Simulation time 13372705 ps
CPU time 1.15 seconds
Started Jun 30 06:47:48 PM PDT 24
Finished Jun 30 06:47:50 PM PDT 24
Peak memory 212104 kb
Host smart-15f34d40-0d48-4671-a8fd-0ea9daf41cd3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567629052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1567629052
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.3256097460
Short name T473
Test name
Test status
Simulation time 37474069 ps
CPU time 0.94 seconds
Started Jun 30 06:47:56 PM PDT 24
Finished Jun 30 06:47:58 PM PDT 24
Peak memory 209172 kb
Host smart-cf9d40bb-e571-4c39-a4f2-edaa9066e330
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256097460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3256097460
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.2169089296
Short name T420
Test name
Test status
Simulation time 382599968 ps
CPU time 10.22 seconds
Started Jun 30 06:47:55 PM PDT 24
Finished Jun 30 06:48:06 PM PDT 24
Peak memory 218440 kb
Host smart-145c8d92-c1da-4722-a30d-432be5acb81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169089296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.2169089296
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.3343570661
Short name T29
Test name
Test status
Simulation time 4108127064 ps
CPU time 6.75 seconds
Started Jun 30 06:47:56 PM PDT 24
Finished Jun 30 06:48:04 PM PDT 24
Peak memory 218024 kb
Host smart-6b4f36e7-715a-48d8-9dcd-4e27831c3bec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343570661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.3343570661
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.2192908671
Short name T214
Test name
Test status
Simulation time 87895041 ps
CPU time 4.21 seconds
Started Jun 30 06:47:59 PM PDT 24
Finished Jun 30 06:48:05 PM PDT 24
Peak memory 222788 kb
Host smart-067884af-7880-438d-945d-9ec5c0c4a82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192908671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.2192908671
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.2428270606
Short name T308
Test name
Test status
Simulation time 577439962 ps
CPU time 13.46 seconds
Started Jun 30 06:47:57 PM PDT 24
Finished Jun 30 06:48:13 PM PDT 24
Peak memory 226156 kb
Host smart-b4a9d86c-bcbf-4fe0-9776-631e80222e32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428270606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2428270606
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.4290343222
Short name T836
Test name
Test status
Simulation time 598727955 ps
CPU time 8.46 seconds
Started Jun 30 06:47:55 PM PDT 24
Finished Jun 30 06:48:05 PM PDT 24
Peak memory 218384 kb
Host smart-284833db-f6c7-4f8e-8964-66288076795d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290343222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.4290343222
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1406492289
Short name T287
Test name
Test status
Simulation time 3995739545 ps
CPU time 9.48 seconds
Started Jun 30 06:47:56 PM PDT 24
Finished Jun 30 06:48:06 PM PDT 24
Peak memory 218496 kb
Host smart-584a2cf1-d694-4f8f-bd44-e7449d8eb409
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406492289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
1406492289
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.4066360434
Short name T439
Test name
Test status
Simulation time 2452500250 ps
CPU time 10.79 seconds
Started Jun 30 06:47:57 PM PDT 24
Finished Jun 30 06:48:09 PM PDT 24
Peak memory 218592 kb
Host smart-1f42dd1f-5937-403a-86ba-6eb7fa58dea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066360434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.4066360434
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.197324278
Short name T71
Test name
Test status
Simulation time 242303684 ps
CPU time 1.97 seconds
Started Jun 30 06:47:57 PM PDT 24
Finished Jun 30 06:48:01 PM PDT 24
Peak memory 214632 kb
Host smart-dc2985ab-1557-4178-bf86-1c5b25f8fe3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197324278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.197324278
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.1896181976
Short name T84
Test name
Test status
Simulation time 1551710609 ps
CPU time 21.88 seconds
Started Jun 30 06:48:01 PM PDT 24
Finished Jun 30 06:48:25 PM PDT 24
Peak memory 251036 kb
Host smart-b530025f-b169-4466-8730-bb037edf1237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896181976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.1896181976
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.1617753662
Short name T772
Test name
Test status
Simulation time 248402496 ps
CPU time 7.65 seconds
Started Jun 30 06:47:57 PM PDT 24
Finished Jun 30 06:48:06 PM PDT 24
Peak memory 251120 kb
Host smart-0680eb55-9c13-419e-8e5f-63635dd85b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617753662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1617753662
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.422551673
Short name T567
Test name
Test status
Simulation time 30813340233 ps
CPU time 144.35 seconds
Started Jun 30 06:47:56 PM PDT 24
Finished Jun 30 06:50:22 PM PDT 24
Peak memory 268596 kb
Host smart-b6b63855-4d03-4afd-82bb-16ac743ede6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422551673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.422551673
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1506628174
Short name T101
Test name
Test status
Simulation time 33270402262 ps
CPU time 750.68 seconds
Started Jun 30 06:47:59 PM PDT 24
Finished Jun 30 07:00:31 PM PDT 24
Peak memory 480708 kb
Host smart-c18ef8c3-757d-43c5-9516-a01f9948e307
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1506628174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.1506628174
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3350553164
Short name T518
Test name
Test status
Simulation time 154309548 ps
CPU time 0.93 seconds
Started Jun 30 06:47:54 PM PDT 24
Finished Jun 30 06:47:56 PM PDT 24
Peak memory 212056 kb
Host smart-8893eedc-5219-45af-a94f-9219dea09b8f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350553164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.3350553164
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3360174148
Short name T273
Test name
Test status
Simulation time 24802453 ps
CPU time 0.87 seconds
Started Jun 30 06:48:01 PM PDT 24
Finished Jun 30 06:48:03 PM PDT 24
Peak memory 209212 kb
Host smart-7481cf1d-8419-42dd-9e0b-eea25705faa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360174148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3360174148
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.857314232
Short name T754
Test name
Test status
Simulation time 214110503 ps
CPU time 7.92 seconds
Started Jun 30 06:47:57 PM PDT 24
Finished Jun 30 06:48:07 PM PDT 24
Peak memory 218408 kb
Host smart-aee6af7e-1fe0-4cf6-8d6f-5d0b1aae10d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857314232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.857314232
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1555685632
Short name T498
Test name
Test status
Simulation time 1248687210 ps
CPU time 5.71 seconds
Started Jun 30 06:47:58 PM PDT 24
Finished Jun 30 06:48:06 PM PDT 24
Peak memory 217376 kb
Host smart-f89a2bc7-1284-4d8d-b16e-144c7fe194bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555685632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1555685632
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.94141430
Short name T324
Test name
Test status
Simulation time 82411246 ps
CPU time 3.92 seconds
Started Jun 30 06:47:59 PM PDT 24
Finished Jun 30 06:48:05 PM PDT 24
Peak memory 222808 kb
Host smart-1ee738ec-d3bc-45df-8951-ca370e3fbd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94141430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.94141430
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1637515693
Short name T756
Test name
Test status
Simulation time 1926347950 ps
CPU time 10.37 seconds
Started Jun 30 06:47:57 PM PDT 24
Finished Jun 30 06:48:09 PM PDT 24
Peak memory 226228 kb
Host smart-dcd91072-de29-4dcc-8b3f-c99639734eb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637515693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1637515693
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3309584400
Short name T610
Test name
Test status
Simulation time 1913452793 ps
CPU time 17.13 seconds
Started Jun 30 06:48:05 PM PDT 24
Finished Jun 30 06:48:24 PM PDT 24
Peak memory 218464 kb
Host smart-8f752586-21a0-484f-b9e3-c1db0d8725cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309584400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.3309584400
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.1252185898
Short name T399
Test name
Test status
Simulation time 3435554340 ps
CPU time 16.06 seconds
Started Jun 30 06:47:57 PM PDT 24
Finished Jun 30 06:48:15 PM PDT 24
Peak memory 218476 kb
Host smart-8e56f688-df7d-41d8-a8ab-dcf58eadff63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252185898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
1252185898
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.992731346
Short name T726
Test name
Test status
Simulation time 744544912 ps
CPU time 8.65 seconds
Started Jun 30 06:47:59 PM PDT 24
Finished Jun 30 06:48:09 PM PDT 24
Peak memory 218468 kb
Host smart-f9604a2c-5bdc-400c-839f-9886039a6bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992731346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.992731346
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.1451448286
Short name T316
Test name
Test status
Simulation time 80990749 ps
CPU time 3.13 seconds
Started Jun 30 06:48:01 PM PDT 24
Finished Jun 30 06:48:06 PM PDT 24
Peak memory 217920 kb
Host smart-157b6abf-8dfa-41c0-9cdf-58b1423d46fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451448286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1451448286
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.2810812514
Short name T614
Test name
Test status
Simulation time 1914023286 ps
CPU time 18.86 seconds
Started Jun 30 06:47:58 PM PDT 24
Finished Jun 30 06:48:18 PM PDT 24
Peak memory 251136 kb
Host smart-69fa0b49-54f3-4482-8965-ef85044f4b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810812514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2810812514
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.1224407306
Short name T350
Test name
Test status
Simulation time 91917572 ps
CPU time 7.51 seconds
Started Jun 30 06:47:57 PM PDT 24
Finished Jun 30 06:48:07 PM PDT 24
Peak memory 251132 kb
Host smart-7dc535dd-f0d6-4d42-98b7-df3f846a2865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224407306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.1224407306
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.1296363113
Short name T200
Test name
Test status
Simulation time 1515088574 ps
CPU time 44.7 seconds
Started Jun 30 06:47:55 PM PDT 24
Finished Jun 30 06:48:41 PM PDT 24
Peak memory 248900 kb
Host smart-02f42729-fa71-43d9-b142-6416865fa1ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296363113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.1296363113
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.228088797
Short name T250
Test name
Test status
Simulation time 43548827 ps
CPU time 0.98 seconds
Started Jun 30 06:48:07 PM PDT 24
Finished Jun 30 06:48:10 PM PDT 24
Peak memory 212136 kb
Host smart-6d353116-d0bd-4709-a152-f7ced5e07864
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228088797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ct
rl_volatile_unlock_smoke.228088797
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3869207009
Short name T223
Test name
Test status
Simulation time 17124451 ps
CPU time 1.13 seconds
Started Jun 30 06:47:57 PM PDT 24
Finished Jun 30 06:48:00 PM PDT 24
Peak memory 209164 kb
Host smart-08a1c004-1dfe-4e20-84e2-08547a53026d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869207009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3869207009
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.599688721
Short name T94
Test name
Test status
Simulation time 2622030079 ps
CPU time 16.07 seconds
Started Jun 30 06:47:54 PM PDT 24
Finished Jun 30 06:48:11 PM PDT 24
Peak memory 219144 kb
Host smart-40b41b10-baf5-4b17-a5b2-8bb25199ec2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599688721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.599688721
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.1391322034
Short name T385
Test name
Test status
Simulation time 1333591317 ps
CPU time 4.94 seconds
Started Jun 30 06:47:57 PM PDT 24
Finished Jun 30 06:48:04 PM PDT 24
Peak memory 217612 kb
Host smart-f7d2442a-30b2-4967-b77e-1c11dac139a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391322034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.1391322034
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.257503976
Short name T139
Test name
Test status
Simulation time 17287498 ps
CPU time 1.7 seconds
Started Jun 30 06:47:57 PM PDT 24
Finished Jun 30 06:48:01 PM PDT 24
Peak memory 221888 kb
Host smart-f9406001-8539-442d-b744-7c0a00cb432e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257503976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.257503976
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.148891360
Short name T371
Test name
Test status
Simulation time 3123776021 ps
CPU time 21.49 seconds
Started Jun 30 06:47:56 PM PDT 24
Finished Jun 30 06:48:18 PM PDT 24
Peak memory 226300 kb
Host smart-d922e2a4-a27a-4d6e-a3e5-a19758f10103
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148891360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.148891360
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.3625713419
Short name T334
Test name
Test status
Simulation time 1066294186 ps
CPU time 21.44 seconds
Started Jun 30 06:47:56 PM PDT 24
Finished Jun 30 06:48:19 PM PDT 24
Peak memory 218508 kb
Host smart-add1de20-8916-4577-beb0-306211a75926
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625713419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.3625713419
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3224488379
Short name T863
Test name
Test status
Simulation time 376937520 ps
CPU time 10.9 seconds
Started Jun 30 06:47:57 PM PDT 24
Finished Jun 30 06:48:10 PM PDT 24
Peak memory 226248 kb
Host smart-6e9a18f9-0a97-4e08-9683-a7e0310c783c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224488379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
3224488379
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.4247629832
Short name T43
Test name
Test status
Simulation time 1037963248 ps
CPU time 10.51 seconds
Started Jun 30 06:48:00 PM PDT 24
Finished Jun 30 06:48:12 PM PDT 24
Peak memory 218620 kb
Host smart-19588d13-e1b2-4b97-ac61-44a5bd0e0de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247629832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.4247629832
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.742981810
Short name T306
Test name
Test status
Simulation time 68654965 ps
CPU time 4.28 seconds
Started Jun 30 06:47:57 PM PDT 24
Finished Jun 30 06:48:04 PM PDT 24
Peak memory 217908 kb
Host smart-1f6d55e4-2051-400e-b9de-6987d08515a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742981810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.742981810
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1494533186
Short name T678
Test name
Test status
Simulation time 2277650899 ps
CPU time 34.43 seconds
Started Jun 30 06:47:55 PM PDT 24
Finished Jun 30 06:48:30 PM PDT 24
Peak memory 251192 kb
Host smart-5b4a63d9-6fb0-475b-9d0e-f41d108cadbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494533186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1494533186
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.547213910
Short name T775
Test name
Test status
Simulation time 245658520 ps
CPU time 12.06 seconds
Started Jun 30 06:48:06 PM PDT 24
Finished Jun 30 06:48:21 PM PDT 24
Peak memory 244764 kb
Host smart-db6d0215-4418-4d49-b73e-7e12a744622c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547213910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.547213910
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2321318910
Short name T315
Test name
Test status
Simulation time 69767343610 ps
CPU time 656.01 seconds
Started Jun 30 06:47:59 PM PDT 24
Finished Jun 30 06:58:57 PM PDT 24
Peak memory 275992 kb
Host smart-e9935e62-4dc2-43c0-ba2f-2da3a4f33ecd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321318910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2321318910
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.236831237
Short name T243
Test name
Test status
Simulation time 22449755 ps
CPU time 0.85 seconds
Started Jun 30 06:47:54 PM PDT 24
Finished Jun 30 06:47:56 PM PDT 24
Peak memory 212100 kb
Host smart-80d147d3-7f68-4f9a-a1fb-3b3053580671
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236831237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ct
rl_volatile_unlock_smoke.236831237
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.4083545796
Short name T81
Test name
Test status
Simulation time 33052852 ps
CPU time 1.11 seconds
Started Jun 30 06:48:02 PM PDT 24
Finished Jun 30 06:48:06 PM PDT 24
Peak memory 209144 kb
Host smart-25baffbe-fee7-4c0f-841a-c33dad9d26c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083545796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.4083545796
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.640707048
Short name T431
Test name
Test status
Simulation time 820409613 ps
CPU time 11.57 seconds
Started Jun 30 06:48:02 PM PDT 24
Finished Jun 30 06:48:15 PM PDT 24
Peak memory 218312 kb
Host smart-4d36fb66-34fe-450a-b114-cf8296e213ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640707048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.640707048
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.2194653179
Short name T605
Test name
Test status
Simulation time 621815456 ps
CPU time 4.52 seconds
Started Jun 30 06:48:01 PM PDT 24
Finished Jun 30 06:48:07 PM PDT 24
Peak memory 217344 kb
Host smart-db318491-7cc2-40ac-a3a6-821fb646975c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194653179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.2194653179
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1383964705
Short name T295
Test name
Test status
Simulation time 108807975 ps
CPU time 2.14 seconds
Started Jun 30 06:48:01 PM PDT 24
Finished Jun 30 06:48:05 PM PDT 24
Peak memory 218448 kb
Host smart-da1a0d6d-6503-42ea-9de5-3703c29f2e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383964705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1383964705
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.4025316818
Short name T311
Test name
Test status
Simulation time 1524711938 ps
CPU time 14.07 seconds
Started Jun 30 06:48:02 PM PDT 24
Finished Jun 30 06:48:18 PM PDT 24
Peak memory 219124 kb
Host smart-200b3545-2400-46bc-8940-32ac55647a64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025316818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.4025316818
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3277134769
Short name T575
Test name
Test status
Simulation time 2901475878 ps
CPU time 15.04 seconds
Started Jun 30 06:47:57 PM PDT 24
Finished Jun 30 06:48:14 PM PDT 24
Peak memory 218520 kb
Host smart-636d24b3-7c1c-444f-bebc-32b16a344e7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277134769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.3277134769
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.1157048355
Short name T740
Test name
Test status
Simulation time 743439402 ps
CPU time 8.15 seconds
Started Jun 30 06:47:57 PM PDT 24
Finished Jun 30 06:48:07 PM PDT 24
Peak memory 218360 kb
Host smart-d3942ff7-7a74-4866-a5fb-f0ea93d877b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157048355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
1157048355
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2726093009
Short name T484
Test name
Test status
Simulation time 349853104 ps
CPU time 7.25 seconds
Started Jun 30 06:47:56 PM PDT 24
Finished Jun 30 06:48:05 PM PDT 24
Peak memory 218508 kb
Host smart-3dd3abd5-3ff5-4e6a-907c-e050a07232e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726093009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2726093009
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.3033322687
Short name T64
Test name
Test status
Simulation time 449602945 ps
CPU time 5.66 seconds
Started Jun 30 06:47:58 PM PDT 24
Finished Jun 30 06:48:06 PM PDT 24
Peak memory 217936 kb
Host smart-db7e89ce-cb30-411d-b34a-65a30bc91c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033322687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.3033322687
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3894228982
Short name T251
Test name
Test status
Simulation time 187445456 ps
CPU time 18.96 seconds
Started Jun 30 06:48:01 PM PDT 24
Finished Jun 30 06:48:22 PM PDT 24
Peak memory 251264 kb
Host smart-ccfbe5fa-4414-43f0-8762-5ce338c493ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894228982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3894228982
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.872116253
Short name T540
Test name
Test status
Simulation time 150965005 ps
CPU time 7.42 seconds
Started Jun 30 06:47:57 PM PDT 24
Finished Jun 30 06:48:07 PM PDT 24
Peak memory 247804 kb
Host smart-0e581469-aa18-472b-a32d-031caffc521d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872116253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.872116253
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.55009162
Short name T815
Test name
Test status
Simulation time 53006855902 ps
CPU time 136.98 seconds
Started Jun 30 06:47:57 PM PDT 24
Finished Jun 30 06:50:16 PM PDT 24
Peak memory 269600 kb
Host smart-d357d9c6-d3b0-4d7c-bd45-c200e685d24d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55009162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.lc_ctrl_stress_all.55009162
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3436260824
Short name T444
Test name
Test status
Simulation time 28713648 ps
CPU time 0.73 seconds
Started Jun 30 06:48:01 PM PDT 24
Finished Jun 30 06:48:03 PM PDT 24
Peak memory 207316 kb
Host smart-174fe5e1-4381-4222-a391-84b78a5cde14
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436260824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.3436260824
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1008467394
Short name T718
Test name
Test status
Simulation time 78727458 ps
CPU time 1.13 seconds
Started Jun 30 06:48:02 PM PDT 24
Finished Jun 30 06:48:05 PM PDT 24
Peak memory 209084 kb
Host smart-9c030f54-367c-473a-9394-6e9774343803
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008467394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1008467394
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.21024309
Short name T734
Test name
Test status
Simulation time 541631419 ps
CPU time 16.19 seconds
Started Jun 30 06:48:02 PM PDT 24
Finished Jun 30 06:48:21 PM PDT 24
Peak memory 226256 kb
Host smart-ee6a4c84-1db3-4770-8b53-355dec759645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21024309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.21024309
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.1445966708
Short name T6
Test name
Test status
Simulation time 1637906329 ps
CPU time 4.51 seconds
Started Jun 30 06:48:00 PM PDT 24
Finished Jun 30 06:48:06 PM PDT 24
Peak memory 217520 kb
Host smart-98d57cd8-ecf8-4689-9d48-3ebc061da849
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445966708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.1445966708
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.2616990504
Short name T175
Test name
Test status
Simulation time 127278618 ps
CPU time 2.7 seconds
Started Jun 30 06:48:02 PM PDT 24
Finished Jun 30 06:48:07 PM PDT 24
Peak memory 218412 kb
Host smart-251d4725-029a-4d0f-b5c3-dddceaded5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616990504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.2616990504
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.2740216951
Short name T355
Test name
Test status
Simulation time 352566574 ps
CPU time 14.13 seconds
Started Jun 30 06:48:09 PM PDT 24
Finished Jun 30 06:48:26 PM PDT 24
Peak memory 218424 kb
Host smart-93f37fb1-1d86-4bf8-a754-4a41b4918536
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740216951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.2740216951
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3488284519
Short name T746
Test name
Test status
Simulation time 2493679910 ps
CPU time 15.49 seconds
Started Jun 30 06:48:07 PM PDT 24
Finished Jun 30 06:48:25 PM PDT 24
Peak memory 218448 kb
Host smart-a01f2344-2573-4a8b-b396-7f7642116fd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488284519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3488284519
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.1899639608
Short name T780
Test name
Test status
Simulation time 528249508 ps
CPU time 11.82 seconds
Started Jun 30 06:48:03 PM PDT 24
Finished Jun 30 06:48:17 PM PDT 24
Peak memory 218316 kb
Host smart-05f177f9-159f-4595-bb93-7a837e86a22c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899639608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
1899639608
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.4055408491
Short name T653
Test name
Test status
Simulation time 293465831 ps
CPU time 8.02 seconds
Started Jun 30 06:48:02 PM PDT 24
Finished Jun 30 06:48:12 PM PDT 24
Peak memory 218472 kb
Host smart-e0cef27a-d856-4712-a21b-cf5bc84b020e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055408491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.4055408491
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.520931240
Short name T70
Test name
Test status
Simulation time 183690288 ps
CPU time 3.08 seconds
Started Jun 30 06:47:59 PM PDT 24
Finished Jun 30 06:48:04 PM PDT 24
Peak memory 218012 kb
Host smart-2c4fa4e4-1759-424e-9719-365c1d24942f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520931240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.520931240
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.245384423
Short name T716
Test name
Test status
Simulation time 615346083 ps
CPU time 17.58 seconds
Started Jun 30 06:48:02 PM PDT 24
Finished Jun 30 06:48:23 PM PDT 24
Peak memory 251144 kb
Host smart-d2bb1b8d-5fb6-4ea8-8997-99f7da7b3390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245384423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.245384423
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.3189371353
Short name T303
Test name
Test status
Simulation time 52842950 ps
CPU time 2.98 seconds
Started Jun 30 06:48:01 PM PDT 24
Finished Jun 30 06:48:05 PM PDT 24
Peak memory 222692 kb
Host smart-e66bf37a-9941-4ccf-8d29-73dab7755597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189371353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3189371353
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.2058055401
Short name T351
Test name
Test status
Simulation time 1536852464 ps
CPU time 36.25 seconds
Started Jun 30 06:48:07 PM PDT 24
Finished Jun 30 06:48:45 PM PDT 24
Peak memory 251072 kb
Host smart-ce5ea83a-9be3-4a5e-a2b7-80d6b003dde6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058055401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.2058055401
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.341999039
Short name T354
Test name
Test status
Simulation time 54083254 ps
CPU time 1.06 seconds
Started Jun 30 06:48:04 PM PDT 24
Finished Jun 30 06:48:08 PM PDT 24
Peak memory 213144 kb
Host smart-c66a23c3-4e85-4874-98e2-42a4215d0879
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341999039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ct
rl_volatile_unlock_smoke.341999039
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2899589468
Short name T343
Test name
Test status
Simulation time 68390498 ps
CPU time 0.96 seconds
Started Jun 30 06:46:12 PM PDT 24
Finished Jun 30 06:46:15 PM PDT 24
Peak memory 209044 kb
Host smart-f3422dcd-8bb2-47d1-8050-852a183e36fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899589468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2899589468
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1823051466
Short name T37
Test name
Test status
Simulation time 587160423 ps
CPU time 12.45 seconds
Started Jun 30 06:46:14 PM PDT 24
Finished Jun 30 06:46:28 PM PDT 24
Peak memory 218424 kb
Host smart-4f26aae6-d6fd-4145-8ec6-7135054d146b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823051466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1823051466
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1712838881
Short name T609
Test name
Test status
Simulation time 1742971248 ps
CPU time 4.81 seconds
Started Jun 30 06:46:11 PM PDT 24
Finished Jun 30 06:46:18 PM PDT 24
Peak memory 217888 kb
Host smart-1079f063-479d-43f4-9cf4-3c67649c47d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712838881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1712838881
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.3391580664
Short name T494
Test name
Test status
Simulation time 2575232364 ps
CPU time 23.07 seconds
Started Jun 30 06:46:09 PM PDT 24
Finished Jun 30 06:46:33 PM PDT 24
Peak memory 219396 kb
Host smart-805d7ac9-1419-460d-a3cc-47f56ee645df
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391580664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.3391580664
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.1444741780
Short name T57
Test name
Test status
Simulation time 594168781 ps
CPU time 15.02 seconds
Started Jun 30 06:46:12 PM PDT 24
Finished Jun 30 06:46:29 PM PDT 24
Peak memory 217768 kb
Host smart-79c41a51-ddcf-4f77-a856-6ff313a35f02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444741780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.1
444741780
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.998427484
Short name T641
Test name
Test status
Simulation time 335157536 ps
CPU time 6.22 seconds
Started Jun 30 06:46:13 PM PDT 24
Finished Jun 30 06:46:20 PM PDT 24
Peak memory 218624 kb
Host smart-5a6fae51-8091-49ad-a90e-4a45d29ae9e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998427484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.998427484
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3011333316
Short name T798
Test name
Test status
Simulation time 1068400956 ps
CPU time 13.3 seconds
Started Jun 30 06:46:11 PM PDT 24
Finished Jun 30 06:46:26 PM PDT 24
Peak memory 217916 kb
Host smart-f5e7d873-f273-4388-a9e4-009008e74d1e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011333316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3011333316
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.482972005
Short name T380
Test name
Test status
Simulation time 318137964 ps
CPU time 1.89 seconds
Started Jun 30 06:46:10 PM PDT 24
Finished Jun 30 06:46:13 PM PDT 24
Peak memory 217896 kb
Host smart-35f9f039-46c4-427a-b929-c84a4e6b499a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482972005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.482972005
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.662442759
Short name T694
Test name
Test status
Simulation time 15739277074 ps
CPU time 35.86 seconds
Started Jun 30 06:46:12 PM PDT 24
Finished Jun 30 06:46:49 PM PDT 24
Peak memory 252628 kb
Host smart-820c77d8-4d2c-4286-8491-2d57915892cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662442759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_state_failure.662442759
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.916959248
Short name T393
Test name
Test status
Simulation time 353829555 ps
CPU time 11.6 seconds
Started Jun 30 06:46:10 PM PDT 24
Finished Jun 30 06:46:23 PM PDT 24
Peak memory 243816 kb
Host smart-4c9d3f8b-6ee6-48fd-a87d-ce5e35b3ecca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916959248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_state_post_trans.916959248
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.2842533876
Short name T602
Test name
Test status
Simulation time 508789537 ps
CPU time 5.3 seconds
Started Jun 30 06:46:10 PM PDT 24
Finished Jun 30 06:46:17 PM PDT 24
Peak memory 218440 kb
Host smart-ed4256af-9fc6-4722-9cfe-e8ff7f7b4e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842533876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.2842533876
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.3568077736
Short name T483
Test name
Test status
Simulation time 459568371 ps
CPU time 15.27 seconds
Started Jun 30 06:46:11 PM PDT 24
Finished Jun 30 06:46:28 PM PDT 24
Peak memory 217896 kb
Host smart-2005d428-5891-4115-b170-afb4f8becf50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568077736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.3568077736
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.597741975
Short name T86
Test name
Test status
Simulation time 415248004 ps
CPU time 23.87 seconds
Started Jun 30 06:46:13 PM PDT 24
Finished Jun 30 06:46:38 PM PDT 24
Peak memory 281932 kb
Host smart-f1700291-7522-44be-b29f-687594fafa4c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597741975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.597741975
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1734134937
Short name T700
Test name
Test status
Simulation time 4431172730 ps
CPU time 24.12 seconds
Started Jun 30 06:46:14 PM PDT 24
Finished Jun 30 06:46:39 PM PDT 24
Peak memory 218548 kb
Host smart-380e91e0-1c55-43e3-bb8a-d101c20cbe2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734134937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1734134937
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1934468137
Short name T571
Test name
Test status
Simulation time 1920263820 ps
CPU time 10.05 seconds
Started Jun 30 06:46:11 PM PDT 24
Finished Jun 30 06:46:23 PM PDT 24
Peak memory 218412 kb
Host smart-b3cf52e1-6d73-4ff8-866a-d17c87f7cca5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934468137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.1
934468137
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.834322960
Short name T238
Test name
Test status
Simulation time 568511826 ps
CPU time 11.68 seconds
Started Jun 30 06:46:13 PM PDT 24
Finished Jun 30 06:46:26 PM PDT 24
Peak memory 225980 kb
Host smart-d0631066-b856-4c9b-bb38-d48ef93932a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834322960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.834322960
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3654818774
Short name T868
Test name
Test status
Simulation time 90663150 ps
CPU time 6.56 seconds
Started Jun 30 06:46:12 PM PDT 24
Finished Jun 30 06:46:20 PM PDT 24
Peak memory 217940 kb
Host smart-79e8e7c7-5c47-4d23-bb0f-b88fc0701e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654818774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3654818774
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.309093027
Short name T680
Test name
Test status
Simulation time 387192828 ps
CPU time 21.01 seconds
Started Jun 30 06:46:13 PM PDT 24
Finished Jun 30 06:46:35 PM PDT 24
Peak memory 251140 kb
Host smart-7236e2d9-6019-4c12-9bb1-02c4b1afdf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309093027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.309093027
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3198053716
Short name T339
Test name
Test status
Simulation time 93381836 ps
CPU time 6 seconds
Started Jun 30 06:46:14 PM PDT 24
Finished Jun 30 06:46:21 PM PDT 24
Peak memory 247036 kb
Host smart-30a80f2a-b93f-47ee-9e9e-532874cc320b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198053716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3198053716
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.1743042403
Short name T667
Test name
Test status
Simulation time 67891820186 ps
CPU time 139.41 seconds
Started Jun 30 06:46:10 PM PDT 24
Finished Jun 30 06:48:30 PM PDT 24
Peak memory 232796 kb
Host smart-56a6d684-ed28-4fac-a324-b78bc763d5d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743042403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.1743042403
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.817085037
Short name T96
Test name
Test status
Simulation time 21077779657 ps
CPU time 501.41 seconds
Started Jun 30 06:46:14 PM PDT 24
Finished Jun 30 06:54:36 PM PDT 24
Peak memory 297940 kb
Host smart-fd723d85-975c-41a9-93fa-a8e86ec1ee9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=817085037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.817085037
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.4144889210
Short name T764
Test name
Test status
Simulation time 170772395 ps
CPU time 0.87 seconds
Started Jun 30 06:46:15 PM PDT 24
Finished Jun 30 06:46:17 PM PDT 24
Peak memory 213212 kb
Host smart-4f31704d-19c3-4d80-9b83-1dbbfae30ce3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144889210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.4144889210
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.4097339429
Short name T450
Test name
Test status
Simulation time 23530096 ps
CPU time 0.87 seconds
Started Jun 30 06:48:01 PM PDT 24
Finished Jun 30 06:48:04 PM PDT 24
Peak memory 208920 kb
Host smart-466aba02-6129-4955-9eb3-ac192e58f4f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097339429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.4097339429
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.85035131
Short name T568
Test name
Test status
Simulation time 463529743 ps
CPU time 11.28 seconds
Started Jun 30 06:48:07 PM PDT 24
Finished Jun 30 06:48:21 PM PDT 24
Peak memory 226256 kb
Host smart-0bf16f7d-0f73-4285-80a4-0ec189941843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85035131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.85035131
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1781535
Short name T633
Test name
Test status
Simulation time 370854455 ps
CPU time 5.28 seconds
Started Jun 30 06:48:06 PM PDT 24
Finished Jun 30 06:48:14 PM PDT 24
Peak memory 217384 kb
Host smart-a335e0d6-ca0c-4157-9282-1cd289e5699c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1781535
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3271651262
Short name T786
Test name
Test status
Simulation time 42222077 ps
CPU time 2.06 seconds
Started Jun 30 06:48:03 PM PDT 24
Finished Jun 30 06:48:07 PM PDT 24
Peak memory 218428 kb
Host smart-4afd49a6-5126-43f0-a593-1e7873706c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271651262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3271651262
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.176301530
Short name T241
Test name
Test status
Simulation time 642839289 ps
CPU time 15.5 seconds
Started Jun 30 06:48:07 PM PDT 24
Finished Jun 30 06:48:25 PM PDT 24
Peak memory 226252 kb
Host smart-90988ca4-ebf4-4a25-9bb1-e4eac60d2c03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176301530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.176301530
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1330057973
Short name T229
Test name
Test status
Simulation time 1800972799 ps
CPU time 8.18 seconds
Started Jun 30 06:48:06 PM PDT 24
Finished Jun 30 06:48:17 PM PDT 24
Peak memory 218440 kb
Host smart-b0bfc01e-1eec-439e-8ac6-c5a3b70c569c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330057973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1330057973
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.2411450793
Short name T582
Test name
Test status
Simulation time 1016035890 ps
CPU time 11.18 seconds
Started Jun 30 06:48:01 PM PDT 24
Finished Jun 30 06:48:14 PM PDT 24
Peak memory 218520 kb
Host smart-2f11723f-9823-41ca-bfd6-685372219168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411450793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.2411450793
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1968173312
Short name T546
Test name
Test status
Simulation time 203318288 ps
CPU time 3.64 seconds
Started Jun 30 06:48:02 PM PDT 24
Finished Jun 30 06:48:08 PM PDT 24
Peak memory 217932 kb
Host smart-14e7fe3f-6306-4d77-83b4-b5fb68dbb406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968173312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1968173312
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3383391478
Short name T277
Test name
Test status
Simulation time 2584934372 ps
CPU time 33.04 seconds
Started Jun 30 06:48:02 PM PDT 24
Finished Jun 30 06:48:38 PM PDT 24
Peak memory 251192 kb
Host smart-a44d763a-0a1c-48b9-8a97-e3a01a39c955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383391478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3383391478
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.1805133645
Short name T259
Test name
Test status
Simulation time 259698954 ps
CPU time 9.25 seconds
Started Jun 30 06:48:06 PM PDT 24
Finished Jun 30 06:48:18 PM PDT 24
Peak memory 251136 kb
Host smart-13ac7466-211a-46c4-815e-b0e0669db7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805133645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.1805133645
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1107612556
Short name T776
Test name
Test status
Simulation time 14559175863 ps
CPU time 140.08 seconds
Started Jun 30 06:48:05 PM PDT 24
Finished Jun 30 06:50:28 PM PDT 24
Peak memory 324316 kb
Host smart-6d3fee24-f919-429d-8725-f8d008cd348b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107612556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1107612556
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.2155622986
Short name T679
Test name
Test status
Simulation time 9370023274 ps
CPU time 324.96 seconds
Started Jun 30 06:48:07 PM PDT 24
Finished Jun 30 06:53:34 PM PDT 24
Peak memory 279236 kb
Host smart-eb7d7a00-f5c9-4779-8ada-83cdd8790ec0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2155622986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.2155622986
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.264729138
Short name T203
Test name
Test status
Simulation time 28056949 ps
CPU time 0.9 seconds
Started Jun 30 06:48:10 PM PDT 24
Finished Jun 30 06:48:13 PM PDT 24
Peak memory 212092 kb
Host smart-f0ee356b-4414-4d82-a7ec-8e87784f7a77
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264729138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ct
rl_volatile_unlock_smoke.264729138
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2550542180
Short name T454
Test name
Test status
Simulation time 93239065 ps
CPU time 0.86 seconds
Started Jun 30 06:48:03 PM PDT 24
Finished Jun 30 06:48:07 PM PDT 24
Peak memory 209020 kb
Host smart-02da707c-2c7e-4130-bde7-5c5be9894c47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550542180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2550542180
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.813331709
Short name T14
Test name
Test status
Simulation time 793404689 ps
CPU time 17.52 seconds
Started Jun 30 06:48:05 PM PDT 24
Finished Jun 30 06:48:25 PM PDT 24
Peak memory 218412 kb
Host smart-805bee45-543b-4dd1-bffb-8beac8a2e881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813331709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.813331709
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2423197007
Short name T488
Test name
Test status
Simulation time 823572355 ps
CPU time 18.37 seconds
Started Jun 30 06:48:07 PM PDT 24
Finished Jun 30 06:48:28 PM PDT 24
Peak memory 217592 kb
Host smart-a61eb37c-2027-431a-9b99-9dd0224b8c6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423197007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.2423197007
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.4192985829
Short name T285
Test name
Test status
Simulation time 40341074 ps
CPU time 2.04 seconds
Started Jun 30 06:48:04 PM PDT 24
Finished Jun 30 06:48:08 PM PDT 24
Peak memory 218436 kb
Host smart-5ca9f020-e823-4bfb-9bd4-fd8c37c5568c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192985829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.4192985829
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.2101780449
Short name T737
Test name
Test status
Simulation time 836027996 ps
CPU time 17.09 seconds
Started Jun 30 06:48:03 PM PDT 24
Finished Jun 30 06:48:22 PM PDT 24
Peak memory 226236 kb
Host smart-7dcca70e-71dd-43dd-b440-3327addaa6ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101780449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.2101780449
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2311457165
Short name T280
Test name
Test status
Simulation time 1587162712 ps
CPU time 12.62 seconds
Started Jun 30 06:48:07 PM PDT 24
Finished Jun 30 06:48:22 PM PDT 24
Peak memory 218532 kb
Host smart-c4a09b32-6113-4dd3-b8c6-60cc03c67f9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311457165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2311457165
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.3337733091
Short name T224
Test name
Test status
Simulation time 1023545006 ps
CPU time 6.92 seconds
Started Jun 30 06:48:04 PM PDT 24
Finished Jun 30 06:48:14 PM PDT 24
Peak memory 226240 kb
Host smart-354e90d8-8063-445a-bbc6-bd9993c51000
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337733091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
3337733091
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.1685010954
Short name T527
Test name
Test status
Simulation time 320214916 ps
CPU time 11.5 seconds
Started Jun 30 06:48:03 PM PDT 24
Finished Jun 30 06:48:18 PM PDT 24
Peak memory 218520 kb
Host smart-038c9653-73f3-4248-8db2-cf02ed8bf8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685010954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.1685010954
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1337760805
Short name T705
Test name
Test status
Simulation time 86996568 ps
CPU time 2.61 seconds
Started Jun 30 06:48:10 PM PDT 24
Finished Jun 30 06:48:16 PM PDT 24
Peak memory 217816 kb
Host smart-0024eb91-2fdb-448d-a1d0-eae73088df7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337760805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1337760805
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.3663992964
Short name T673
Test name
Test status
Simulation time 218217004 ps
CPU time 34.72 seconds
Started Jun 30 06:48:10 PM PDT 24
Finished Jun 30 06:48:48 PM PDT 24
Peak memory 251088 kb
Host smart-96396ea3-0feb-4236-a973-50c1957c895b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663992964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.3663992964
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.631000754
Short name T519
Test name
Test status
Simulation time 85566962 ps
CPU time 3.23 seconds
Started Jun 30 06:48:04 PM PDT 24
Finished Jun 30 06:48:10 PM PDT 24
Peak memory 226540 kb
Host smart-1dda7da1-6348-44b3-bae6-a8aeb896c7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631000754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.631000754
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.267908682
Short name T166
Test name
Test status
Simulation time 7986509670 ps
CPU time 179.59 seconds
Started Jun 30 06:48:07 PM PDT 24
Finished Jun 30 06:51:09 PM PDT 24
Peak memory 251204 kb
Host smart-d46545be-5456-48fd-a5d5-da77319da511
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267908682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.267908682
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.1659633994
Short name T138
Test name
Test status
Simulation time 19517239741 ps
CPU time 296.2 seconds
Started Jun 30 06:48:03 PM PDT 24
Finished Jun 30 06:53:01 PM PDT 24
Peak memory 419384 kb
Host smart-3eb9733c-742d-4826-9471-22ea00e0e489
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1659633994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.1659633994
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2130085864
Short name T729
Test name
Test status
Simulation time 38456236 ps
CPU time 0.91 seconds
Started Jun 30 06:48:10 PM PDT 24
Finished Jun 30 06:48:14 PM PDT 24
Peak memory 211964 kb
Host smart-a89d299a-b246-45f0-92e7-11ea3af514f8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130085864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.2130085864
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.151688549
Short name T338
Test name
Test status
Simulation time 66804281 ps
CPU time 0.89 seconds
Started Jun 30 06:48:10 PM PDT 24
Finished Jun 30 06:48:14 PM PDT 24
Peak memory 209200 kb
Host smart-d5bb5b91-5ee9-4836-ba9c-ea699bb4c735
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151688549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.151688549
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.757994728
Short name T221
Test name
Test status
Simulation time 1392559244 ps
CPU time 7.09 seconds
Started Jun 30 06:48:07 PM PDT 24
Finished Jun 30 06:48:17 PM PDT 24
Peak memory 218504 kb
Host smart-caed87d5-8da9-49fc-be9c-43e06d9a82c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757994728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.757994728
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.4211698122
Short name T608
Test name
Test status
Simulation time 64325160 ps
CPU time 1.95 seconds
Started Jun 30 06:48:09 PM PDT 24
Finished Jun 30 06:48:14 PM PDT 24
Peak memory 218420 kb
Host smart-880085ae-43ae-40bc-9c4c-3cc077284a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211698122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.4211698122
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.4050085740
Short name T674
Test name
Test status
Simulation time 215195123 ps
CPU time 9.84 seconds
Started Jun 30 06:48:10 PM PDT 24
Finished Jun 30 06:48:22 PM PDT 24
Peak memory 226212 kb
Host smart-e85b8d0f-7a46-43df-934e-d43b85abb5d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050085740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.4050085740
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1847239322
Short name T282
Test name
Test status
Simulation time 277109177 ps
CPU time 13.02 seconds
Started Jun 30 06:48:11 PM PDT 24
Finished Jun 30 06:48:27 PM PDT 24
Peak memory 218444 kb
Host smart-c17c8eae-2470-4f46-b30a-1d64c5f85c74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847239322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.1847239322
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2986958643
Short name T465
Test name
Test status
Simulation time 1662212082 ps
CPU time 13.9 seconds
Started Jun 30 06:48:07 PM PDT 24
Finished Jun 30 06:48:24 PM PDT 24
Peak memory 218440 kb
Host smart-451cc1f9-51c4-4708-824d-6df47de04f67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986958643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
2986958643
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.224438276
Short name T416
Test name
Test status
Simulation time 29977339 ps
CPU time 1.97 seconds
Started Jun 30 06:48:07 PM PDT 24
Finished Jun 30 06:48:11 PM PDT 24
Peak memory 214232 kb
Host smart-8dfb06b0-2f6c-445d-adf9-8653827f7b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224438276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.224438276
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.926734134
Short name T732
Test name
Test status
Simulation time 1387658715 ps
CPU time 35.54 seconds
Started Jun 30 06:48:03 PM PDT 24
Finished Jun 30 06:48:41 PM PDT 24
Peak memory 251144 kb
Host smart-c14bb3fa-87e2-4ce2-89ea-59f7611943cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926734134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.926734134
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.1907188365
Short name T622
Test name
Test status
Simulation time 87668694 ps
CPU time 7.71 seconds
Started Jun 30 06:48:10 PM PDT 24
Finished Jun 30 06:48:21 PM PDT 24
Peak memory 251040 kb
Host smart-c0069437-542a-445a-acae-175860c15a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907188365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.1907188365
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.2777949856
Short name T40
Test name
Test status
Simulation time 2891176162 ps
CPU time 74.62 seconds
Started Jun 30 06:48:08 PM PDT 24
Finished Jun 30 06:49:25 PM PDT 24
Peak memory 284172 kb
Host smart-f4f0d140-8550-4d24-b676-6e3ab3c0a743
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777949856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.2777949856
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1498067001
Short name T239
Test name
Test status
Simulation time 15428492 ps
CPU time 0.88 seconds
Started Jun 30 06:48:09 PM PDT 24
Finished Jun 30 06:48:12 PM PDT 24
Peak memory 212136 kb
Host smart-fb1dbc85-700b-4cfd-b629-90f976a2bb9b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498067001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.1498067001
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.3558415213
Short name T794
Test name
Test status
Simulation time 30769285 ps
CPU time 0.83 seconds
Started Jun 30 06:48:07 PM PDT 24
Finished Jun 30 06:48:10 PM PDT 24
Peak memory 208992 kb
Host smart-8b8baa1b-c86d-4590-8c1d-64be42090306
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558415213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.3558415213
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.4048502104
Short name T842
Test name
Test status
Simulation time 1130327961 ps
CPU time 8.23 seconds
Started Jun 30 06:48:11 PM PDT 24
Finished Jun 30 06:48:22 PM PDT 24
Peak memory 218276 kb
Host smart-70f8749c-22dd-43ff-99c9-4042ce25f036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048502104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.4048502104
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.4294555780
Short name T520
Test name
Test status
Simulation time 15096263332 ps
CPU time 21.37 seconds
Started Jun 30 06:48:13 PM PDT 24
Finished Jun 30 06:48:37 PM PDT 24
Peak memory 217976 kb
Host smart-9c194dc1-d8fa-401e-a8ee-e46c82be6d43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294555780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.4294555780
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.2444592794
Short name T506
Test name
Test status
Simulation time 252348788 ps
CPU time 3.58 seconds
Started Jun 30 06:48:10 PM PDT 24
Finished Jun 30 06:48:16 PM PDT 24
Peak memory 218412 kb
Host smart-0377e49e-4c12-49f5-8504-436380ff4ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444592794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.2444592794
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.712804807
Short name T296
Test name
Test status
Simulation time 535178910 ps
CPU time 21.11 seconds
Started Jun 30 06:48:09 PM PDT 24
Finished Jun 30 06:48:33 PM PDT 24
Peak memory 220168 kb
Host smart-f8f6d8dc-694d-441e-ae09-66b20ca284a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712804807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.712804807
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2774021514
Short name T310
Test name
Test status
Simulation time 5440782658 ps
CPU time 12.43 seconds
Started Jun 30 06:48:11 PM PDT 24
Finished Jun 30 06:48:26 PM PDT 24
Peak memory 218520 kb
Host smart-aae74bab-a6e0-4cff-add8-e62a23f2edfe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774021514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.2774021514
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.3993665931
Short name T167
Test name
Test status
Simulation time 1486256124 ps
CPU time 8.76 seconds
Started Jun 30 06:48:06 PM PDT 24
Finished Jun 30 06:48:18 PM PDT 24
Peak memory 218384 kb
Host smart-f253156d-699c-45e0-bb7a-8173366e6874
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993665931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
3993665931
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2566360688
Short name T289
Test name
Test status
Simulation time 281646698 ps
CPU time 11.94 seconds
Started Jun 30 06:48:11 PM PDT 24
Finished Jun 30 06:48:26 PM PDT 24
Peak memory 218448 kb
Host smart-7f6d9f6f-7107-4e3f-8817-1dcc2b2b1c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566360688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2566360688
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.781487196
Short name T486
Test name
Test status
Simulation time 619008846 ps
CPU time 2.18 seconds
Started Jun 30 06:48:11 PM PDT 24
Finished Jun 30 06:48:16 PM PDT 24
Peak memory 217932 kb
Host smart-4aa83811-8ff0-45fa-bffa-8bda72f11f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781487196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.781487196
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.3954328487
Short name T220
Test name
Test status
Simulation time 281204384 ps
CPU time 27.42 seconds
Started Jun 30 06:48:10 PM PDT 24
Finished Jun 30 06:48:41 PM PDT 24
Peak memory 251216 kb
Host smart-9e168ca4-9fa3-4da6-81cd-082557e01e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954328487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3954328487
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.550246044
Short name T452
Test name
Test status
Simulation time 317695185 ps
CPU time 3.67 seconds
Started Jun 30 06:48:10 PM PDT 24
Finished Jun 30 06:48:17 PM PDT 24
Peak memory 226532 kb
Host smart-40aeeb55-b6c9-459b-9091-c3c0f2d6e287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550246044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.550246044
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.2755935660
Short name T362
Test name
Test status
Simulation time 11318537705 ps
CPU time 116.43 seconds
Started Jun 30 06:48:09 PM PDT 24
Finished Jun 30 06:50:08 PM PDT 24
Peak memory 226292 kb
Host smart-bf316b5c-1d3b-4b95-8849-afbc9ff267f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755935660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.2755935660
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.1335729422
Short name T100
Test name
Test status
Simulation time 32527752822 ps
CPU time 302.09 seconds
Started Jun 30 06:48:12 PM PDT 24
Finished Jun 30 06:53:17 PM PDT 24
Peak memory 309084 kb
Host smart-1d723aac-d5f7-4888-9f36-399489670ead
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1335729422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.1335729422
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.4257215725
Short name T89
Test name
Test status
Simulation time 31053087 ps
CPU time 0.93 seconds
Started Jun 30 06:48:09 PM PDT 24
Finished Jun 30 06:48:12 PM PDT 24
Peak memory 213356 kb
Host smart-68933fa0-897f-4d3e-816d-ac0b3e2c4ef2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257215725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.4257215725
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2022018775
Short name T612
Test name
Test status
Simulation time 2470264860 ps
CPU time 17.45 seconds
Started Jun 30 06:48:09 PM PDT 24
Finished Jun 30 06:48:29 PM PDT 24
Peak memory 218508 kb
Host smart-c0cf7d93-75bd-4e3e-8761-0fbd1767f493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022018775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2022018775
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.4204872911
Short name T349
Test name
Test status
Simulation time 247657823 ps
CPU time 3.45 seconds
Started Jun 30 06:48:11 PM PDT 24
Finished Jun 30 06:48:17 PM PDT 24
Peak memory 217508 kb
Host smart-a2d2cffc-849a-4436-9078-6bf2b952121b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204872911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.4204872911
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.4180142489
Short name T750
Test name
Test status
Simulation time 149920132 ps
CPU time 3.65 seconds
Started Jun 30 06:48:12 PM PDT 24
Finished Jun 30 06:48:18 PM PDT 24
Peak memory 222640 kb
Host smart-84cde8e8-7f71-4e6c-a01e-7f3864edb2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180142489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.4180142489
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.1739823499
Short name T639
Test name
Test status
Simulation time 904569874 ps
CPU time 8.74 seconds
Started Jun 30 06:48:10 PM PDT 24
Finished Jun 30 06:48:21 PM PDT 24
Peak memory 226172 kb
Host smart-9abc5978-99ae-449a-ac1c-4b0e8250d42e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739823499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1739823499
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.296052929
Short name T356
Test name
Test status
Simulation time 1132010925 ps
CPU time 8.9 seconds
Started Jun 30 06:48:10 PM PDT 24
Finished Jun 30 06:48:22 PM PDT 24
Peak memory 218456 kb
Host smart-d6b096b7-b6f6-4278-a411-697fb2967f2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296052929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_di
gest.296052929
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.46392
Short name T516
Test name
Test status
Simulation time 325320935 ps
CPU time 12.14 seconds
Started Jun 30 06:48:10 PM PDT 24
Finished Jun 30 06:48:24 PM PDT 24
Peak memory 226256 kb
Host smart-4935ef00-0736-498d-8d15-48a5e5d9b642
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.46392
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.3305983495
Short name T580
Test name
Test status
Simulation time 282529707 ps
CPU time 8.28 seconds
Started Jun 30 06:48:09 PM PDT 24
Finished Jun 30 06:48:20 PM PDT 24
Peak memory 218572 kb
Host smart-6b983835-9ba9-4d6f-93ad-b557be8316de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305983495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.3305983495
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.3338856722
Short name T290
Test name
Test status
Simulation time 231230972 ps
CPU time 5.4 seconds
Started Jun 30 06:48:11 PM PDT 24
Finished Jun 30 06:48:19 PM PDT 24
Peak memory 217960 kb
Host smart-96204159-f589-4af7-b27f-5b3188315786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338856722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.3338856722
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2533849246
Short name T799
Test name
Test status
Simulation time 1142534620 ps
CPU time 12.56 seconds
Started Jun 30 06:48:11 PM PDT 24
Finished Jun 30 06:48:26 PM PDT 24
Peak memory 243632 kb
Host smart-f7cea557-54d2-48df-b99e-39fe678f2941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533849246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2533849246
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.1023434989
Short name T88
Test name
Test status
Simulation time 75110073 ps
CPU time 6.15 seconds
Started Jun 30 06:48:11 PM PDT 24
Finished Jun 30 06:48:20 PM PDT 24
Peak memory 250496 kb
Host smart-501e5129-5461-47e6-8423-cc83d3ca33be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023434989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.1023434989
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2163330474
Short name T441
Test name
Test status
Simulation time 3463727170 ps
CPU time 57.27 seconds
Started Jun 30 06:48:11 PM PDT 24
Finished Jun 30 06:49:11 PM PDT 24
Peak memory 219092 kb
Host smart-4ff912e3-bb9b-45fc-8a6e-f3531a5658cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163330474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2163330474
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1778585438
Short name T480
Test name
Test status
Simulation time 12019868 ps
CPU time 0.89 seconds
Started Jun 30 06:48:10 PM PDT 24
Finished Jun 30 06:48:14 PM PDT 24
Peak memory 212088 kb
Host smart-8bdf0903-96f4-464c-b813-be46495a934f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778585438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.1778585438
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.3411966780
Short name T236
Test name
Test status
Simulation time 17878575 ps
CPU time 0.9 seconds
Started Jun 30 06:48:15 PM PDT 24
Finished Jun 30 06:48:19 PM PDT 24
Peak memory 209152 kb
Host smart-f690fe09-24b0-436e-886f-b0ee11acffac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411966780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.3411966780
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1590722420
Short name T790
Test name
Test status
Simulation time 241350391 ps
CPU time 11.04 seconds
Started Jun 30 06:48:15 PM PDT 24
Finished Jun 30 06:48:28 PM PDT 24
Peak memory 226260 kb
Host smart-96d7eb31-9313-44a2-bae1-49517f371314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590722420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1590722420
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.2543518880
Short name T558
Test name
Test status
Simulation time 4534503443 ps
CPU time 4.77 seconds
Started Jun 30 06:48:14 PM PDT 24
Finished Jun 30 06:48:22 PM PDT 24
Peak memory 217912 kb
Host smart-191364f4-ff91-4573-a6ab-be169ea0833d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543518880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.2543518880
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2645286844
Short name T778
Test name
Test status
Simulation time 135655612 ps
CPU time 1.9 seconds
Started Jun 30 06:48:13 PM PDT 24
Finished Jun 30 06:48:18 PM PDT 24
Peak memory 218340 kb
Host smart-0715bbd3-6c69-438c-bac1-52fd4571ce4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645286844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2645286844
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.864342588
Short name T347
Test name
Test status
Simulation time 201199489 ps
CPU time 9.94 seconds
Started Jun 30 06:48:17 PM PDT 24
Finished Jun 30 06:48:29 PM PDT 24
Peak memory 226256 kb
Host smart-a75ada79-504c-4cd1-92e5-989189c6b431
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864342588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.864342588
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.2757618156
Short name T332
Test name
Test status
Simulation time 423379394 ps
CPU time 10.71 seconds
Started Jun 30 06:48:18 PM PDT 24
Finished Jun 30 06:48:30 PM PDT 24
Peak memory 218468 kb
Host smart-6a75feae-94ad-404a-9a2b-90aa00870f12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757618156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.2757618156
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.14016192
Short name T598
Test name
Test status
Simulation time 240048743 ps
CPU time 9 seconds
Started Jun 30 06:48:18 PM PDT 24
Finished Jun 30 06:48:28 PM PDT 24
Peak memory 226184 kb
Host smart-9a760d9e-fefd-48f0-81b8-a4e143886d49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14016192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.14016192
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.335260075
Short name T448
Test name
Test status
Simulation time 373339814 ps
CPU time 15.16 seconds
Started Jun 30 06:48:15 PM PDT 24
Finished Jun 30 06:48:33 PM PDT 24
Peak memory 218508 kb
Host smart-398a09ab-6066-4e19-bd40-731a4962d04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335260075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.335260075
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.3967677413
Short name T742
Test name
Test status
Simulation time 111407811 ps
CPU time 4.68 seconds
Started Jun 30 06:48:10 PM PDT 24
Finished Jun 30 06:48:18 PM PDT 24
Peak memory 217936 kb
Host smart-32127c11-1815-4027-b020-015b455c5a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967677413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3967677413
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1157505073
Short name T219
Test name
Test status
Simulation time 241390060 ps
CPU time 28.19 seconds
Started Jun 30 06:48:11 PM PDT 24
Finished Jun 30 06:48:42 PM PDT 24
Peak memory 251128 kb
Host smart-0eba7657-c06e-41b8-a1c2-3df707c9c84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157505073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1157505073
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2362215743
Short name T665
Test name
Test status
Simulation time 294248511 ps
CPU time 8.34 seconds
Started Jun 30 06:48:10 PM PDT 24
Finished Jun 30 06:48:20 PM PDT 24
Peak memory 251124 kb
Host smart-53c33e76-de9d-4b8f-a1c2-eecd5daca36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362215743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2362215743
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.606423691
Short name T510
Test name
Test status
Simulation time 15084915843 ps
CPU time 120.11 seconds
Started Jun 30 06:48:15 PM PDT 24
Finished Jun 30 06:50:17 PM PDT 24
Peak memory 272348 kb
Host smart-dd483691-7820-4423-8dee-46e45fbafa21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606423691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.606423691
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.3818001620
Short name T413
Test name
Test status
Simulation time 12397448 ps
CPU time 0.78 seconds
Started Jun 30 06:48:11 PM PDT 24
Finished Jun 30 06:48:15 PM PDT 24
Peak memory 208360 kb
Host smart-5d0ea100-51fa-4c8f-92d1-15fa9c0b08a4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818001620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.3818001620
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3635199088
Short name T398
Test name
Test status
Simulation time 18193765 ps
CPU time 1.07 seconds
Started Jun 30 06:48:14 PM PDT 24
Finished Jun 30 06:48:18 PM PDT 24
Peak memory 209264 kb
Host smart-2fcccb5a-7eca-4d16-96eb-100e0adcdca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635199088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3635199088
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.1383760898
Short name T437
Test name
Test status
Simulation time 536264699 ps
CPU time 22.7 seconds
Started Jun 30 06:48:15 PM PDT 24
Finished Jun 30 06:48:40 PM PDT 24
Peak memory 218444 kb
Host smart-1576e7f9-3464-4231-aa53-bf0b7b9b7577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383760898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1383760898
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.340335374
Short name T27
Test name
Test status
Simulation time 877772411 ps
CPU time 2.86 seconds
Started Jun 30 06:48:14 PM PDT 24
Finished Jun 30 06:48:19 PM PDT 24
Peak memory 217908 kb
Host smart-c1c339f1-88ca-46d2-bdb7-dbb5912a68a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340335374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.340335374
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.2062981080
Short name T621
Test name
Test status
Simulation time 83527748 ps
CPU time 3.47 seconds
Started Jun 30 06:48:18 PM PDT 24
Finished Jun 30 06:48:23 PM PDT 24
Peak memory 218364 kb
Host smart-0940eb23-3694-49de-b3b4-48d678b32192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062981080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2062981080
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.2002656859
Short name T619
Test name
Test status
Simulation time 328228506 ps
CPU time 9.59 seconds
Started Jun 30 06:48:16 PM PDT 24
Finished Jun 30 06:48:28 PM PDT 24
Peak memory 226240 kb
Host smart-4fffff64-4603-4d96-8dd2-d719081b952c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002656859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.2002656859
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3832736776
Short name T264
Test name
Test status
Simulation time 2609087328 ps
CPU time 12.2 seconds
Started Jun 30 06:48:14 PM PDT 24
Finished Jun 30 06:48:29 PM PDT 24
Peak memory 219144 kb
Host smart-d9dc4695-c371-48ea-ab13-dacda45761da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832736776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3832736776
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3000655512
Short name T688
Test name
Test status
Simulation time 615565900 ps
CPU time 7.08 seconds
Started Jun 30 06:48:16 PM PDT 24
Finished Jun 30 06:48:25 PM PDT 24
Peak memory 226232 kb
Host smart-f06ee6c7-d5c2-42ca-b60e-6b736799a971
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000655512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3000655512
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.2149914874
Short name T715
Test name
Test status
Simulation time 350405027 ps
CPU time 9.3 seconds
Started Jun 30 06:48:16 PM PDT 24
Finished Jun 30 06:48:27 PM PDT 24
Peak memory 218520 kb
Host smart-509ae5c6-4414-4b8e-8b8b-945b25275557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149914874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.2149914874
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.2873046895
Short name T660
Test name
Test status
Simulation time 57092363 ps
CPU time 1.99 seconds
Started Jun 30 06:48:16 PM PDT 24
Finished Jun 30 06:48:21 PM PDT 24
Peak memory 217876 kb
Host smart-5638d228-d7f3-4995-81bb-eede9a179d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873046895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2873046895
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.488920712
Short name T628
Test name
Test status
Simulation time 918102844 ps
CPU time 28.06 seconds
Started Jun 30 06:48:16 PM PDT 24
Finished Jun 30 06:48:47 PM PDT 24
Peak memory 251132 kb
Host smart-e2dddedf-f2d4-4a14-9a63-fc5046d01c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488920712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.488920712
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2948890445
Short name T808
Test name
Test status
Simulation time 74660050 ps
CPU time 6.42 seconds
Started Jun 30 06:48:19 PM PDT 24
Finished Jun 30 06:48:26 PM PDT 24
Peak memory 247140 kb
Host smart-53089f6c-925f-441d-9db1-67536f8d20ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948890445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2948890445
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.525250317
Short name T154
Test name
Test status
Simulation time 2326303025 ps
CPU time 100.56 seconds
Started Jun 30 06:48:14 PM PDT 24
Finished Jun 30 06:49:57 PM PDT 24
Peak memory 405700 kb
Host smart-a489921b-9736-4b55-845e-e772646b04a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525250317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.525250317
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2017080508
Short name T860
Test name
Test status
Simulation time 36800294 ps
CPU time 0.8 seconds
Started Jun 30 06:48:15 PM PDT 24
Finished Jun 30 06:48:19 PM PDT 24
Peak memory 208308 kb
Host smart-930b3515-2308-490a-845d-bd17aa26c88a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017080508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.2017080508
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.2474947116
Short name T526
Test name
Test status
Simulation time 14723733 ps
CPU time 1.16 seconds
Started Jun 30 06:48:15 PM PDT 24
Finished Jun 30 06:48:18 PM PDT 24
Peak memory 209256 kb
Host smart-e59eefcb-eeab-4d68-bf98-aa73d7759d75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474947116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2474947116
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1512495205
Short name T235
Test name
Test status
Simulation time 1913764587 ps
CPU time 14.41 seconds
Started Jun 30 06:48:16 PM PDT 24
Finished Jun 30 06:48:33 PM PDT 24
Peak memory 226248 kb
Host smart-2dd183ef-1460-48cb-a4d8-5d2aed53dad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512495205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1512495205
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3886197343
Short name T532
Test name
Test status
Simulation time 1054521528 ps
CPU time 23.8 seconds
Started Jun 30 06:48:14 PM PDT 24
Finished Jun 30 06:48:41 PM PDT 24
Peak memory 217720 kb
Host smart-5c2995c1-8e68-4969-90bd-b73cc71420f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886197343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3886197343
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.1401626967
Short name T611
Test name
Test status
Simulation time 123770964 ps
CPU time 2.26 seconds
Started Jun 30 06:48:13 PM PDT 24
Finished Jun 30 06:48:18 PM PDT 24
Peak memory 218396 kb
Host smart-6acce8f9-e3a8-438f-9187-ec1bb09e2345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401626967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1401626967
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.2187481488
Short name T357
Test name
Test status
Simulation time 1704472265 ps
CPU time 19.68 seconds
Started Jun 30 06:48:16 PM PDT 24
Finished Jun 30 06:48:38 PM PDT 24
Peak memory 226220 kb
Host smart-bde5c35f-f03f-4ca6-9780-e5824ff84bf1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187481488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.2187481488
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.2056988590
Short name T309
Test name
Test status
Simulation time 1553015892 ps
CPU time 9.95 seconds
Started Jun 30 06:48:16 PM PDT 24
Finished Jun 30 06:48:28 PM PDT 24
Peak memory 218536 kb
Host smart-6fe5cd13-9a1c-4634-8e1a-cf0d61eec65f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056988590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.2056988590
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.991148268
Short name T266
Test name
Test status
Simulation time 305376082 ps
CPU time 9.44 seconds
Started Jun 30 06:48:13 PM PDT 24
Finished Jun 30 06:48:24 PM PDT 24
Peak memory 218400 kb
Host smart-80dada60-93e5-4761-824b-73efe77cf17a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991148268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.991148268
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3121528262
Short name T256
Test name
Test status
Simulation time 1580936918 ps
CPU time 9.56 seconds
Started Jun 30 06:48:15 PM PDT 24
Finished Jun 30 06:48:27 PM PDT 24
Peak memory 218496 kb
Host smart-b1393e7e-e7e0-4e91-ae07-b9d85edb7854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121528262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3121528262
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.1357559915
Short name T819
Test name
Test status
Simulation time 119085933 ps
CPU time 2.16 seconds
Started Jun 30 06:48:16 PM PDT 24
Finished Jun 30 06:48:20 PM PDT 24
Peak memory 217860 kb
Host smart-ebd82020-b2cc-4989-9768-9ae9ea73b341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357559915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.1357559915
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.388642034
Short name T390
Test name
Test status
Simulation time 898651772 ps
CPU time 15.84 seconds
Started Jun 30 06:48:14 PM PDT 24
Finished Jun 30 06:48:32 PM PDT 24
Peak memory 251140 kb
Host smart-3e6c70ff-bdd5-41f7-803a-60967ba74bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388642034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.388642034
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3790981066
Short name T172
Test name
Test status
Simulation time 193084070 ps
CPU time 7.01 seconds
Started Jun 30 06:48:13 PM PDT 24
Finished Jun 30 06:48:23 PM PDT 24
Peak memory 250596 kb
Host smart-26a22c24-0597-4dc8-aa23-3838cd375f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790981066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3790981066
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.3662847575
Short name T846
Test name
Test status
Simulation time 4001509785 ps
CPU time 56.62 seconds
Started Jun 30 06:48:14 PM PDT 24
Finished Jun 30 06:49:13 PM PDT 24
Peak memory 267220 kb
Host smart-32dc3bcc-c523-451f-ba63-4625b51db3ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662847575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.3662847575
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3369333738
Short name T369
Test name
Test status
Simulation time 15051209 ps
CPU time 1.12 seconds
Started Jun 30 06:48:15 PM PDT 24
Finished Jun 30 06:48:19 PM PDT 24
Peak memory 212008 kb
Host smart-eb39c0d1-3419-4310-af65-6922cb07d044
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369333738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.3369333738
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1821957477
Short name T770
Test name
Test status
Simulation time 165019269 ps
CPU time 1 seconds
Started Jun 30 06:48:21 PM PDT 24
Finished Jun 30 06:48:23 PM PDT 24
Peak memory 209168 kb
Host smart-45ae3087-556c-4988-b07f-7a1f282a645a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821957477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1821957477
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.578601915
Short name T10
Test name
Test status
Simulation time 1721249584 ps
CPU time 17.58 seconds
Started Jun 30 06:48:21 PM PDT 24
Finished Jun 30 06:48:40 PM PDT 24
Peak memory 218404 kb
Host smart-c98a817b-f415-452e-9ef3-150cca63759c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578601915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.578601915
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.3883828392
Short name T455
Test name
Test status
Simulation time 124656583 ps
CPU time 1.54 seconds
Started Jun 30 06:48:21 PM PDT 24
Finished Jun 30 06:48:24 PM PDT 24
Peak memory 217276 kb
Host smart-d940c555-b170-422d-b245-ff50d645d392
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883828392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.3883828392
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.2277988830
Short name T783
Test name
Test status
Simulation time 322043977 ps
CPU time 3.4 seconds
Started Jun 30 06:48:21 PM PDT 24
Finished Jun 30 06:48:25 PM PDT 24
Peak memory 222784 kb
Host smart-6d149873-5dcd-4324-9843-d9bbfbe09a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277988830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2277988830
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.2564187259
Short name T403
Test name
Test status
Simulation time 352296909 ps
CPU time 14.56 seconds
Started Jun 30 06:48:22 PM PDT 24
Finished Jun 30 06:48:37 PM PDT 24
Peak memory 226224 kb
Host smart-d764a133-53d6-4b6b-8d7b-b377b6960078
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564187259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2564187259
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.1342879121
Short name T719
Test name
Test status
Simulation time 1928997401 ps
CPU time 12.57 seconds
Started Jun 30 06:48:22 PM PDT 24
Finished Jun 30 06:48:35 PM PDT 24
Peak memory 218496 kb
Host smart-a6dd0d67-f73f-4298-beb5-6ca6dfb72b79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342879121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.1342879121
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1136031912
Short name T265
Test name
Test status
Simulation time 622257813 ps
CPU time 6.7 seconds
Started Jun 30 06:48:20 PM PDT 24
Finished Jun 30 06:48:28 PM PDT 24
Peak memory 218380 kb
Host smart-4c77a893-a0dc-4f85-bb9d-d4cb048e4755
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136031912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1136031912
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.2302110977
Short name T720
Test name
Test status
Simulation time 265558464 ps
CPU time 9.54 seconds
Started Jun 30 06:48:19 PM PDT 24
Finished Jun 30 06:48:29 PM PDT 24
Peak memory 218688 kb
Host smart-8bd87e63-5347-4362-8172-ccdba0290821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302110977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.2302110977
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.1785363964
Short name T657
Test name
Test status
Simulation time 108853305 ps
CPU time 2.29 seconds
Started Jun 30 06:48:21 PM PDT 24
Finished Jun 30 06:48:24 PM PDT 24
Peak memory 214600 kb
Host smart-389db661-b8d5-4026-a866-199be1adbcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785363964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1785363964
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3847048207
Short name T313
Test name
Test status
Simulation time 580964141 ps
CPU time 31.46 seconds
Started Jun 30 06:48:20 PM PDT 24
Finished Jun 30 06:48:52 PM PDT 24
Peak memory 251376 kb
Host smart-55028f55-0ecd-4efe-aeaa-dc527b35b3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847048207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3847048207
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.4245144913
Short name T373
Test name
Test status
Simulation time 288575356 ps
CPU time 7.59 seconds
Started Jun 30 06:48:21 PM PDT 24
Finished Jun 30 06:48:30 PM PDT 24
Peak memory 251164 kb
Host smart-5073fb75-9e9a-479f-a7a6-e8698cd01111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245144913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.4245144913
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3518932288
Short name T21
Test name
Test status
Simulation time 2399599317 ps
CPU time 97.1 seconds
Started Jun 30 06:48:19 PM PDT 24
Finished Jun 30 06:49:57 PM PDT 24
Peak memory 251092 kb
Host smart-d11b12a3-4b76-4136-945a-a34d59764e9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518932288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3518932288
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3332683283
Short name T735
Test name
Test status
Simulation time 12390893 ps
CPU time 1.04 seconds
Started Jun 30 06:48:19 PM PDT 24
Finished Jun 30 06:48:21 PM PDT 24
Peak memory 212112 kb
Host smart-9cc1d3cc-2a82-41d0-932b-a961275c87ba
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332683283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3332683283
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.827616572
Short name T404
Test name
Test status
Simulation time 31591489 ps
CPU time 0.95 seconds
Started Jun 30 06:48:27 PM PDT 24
Finished Jun 30 06:48:28 PM PDT 24
Peak memory 209140 kb
Host smart-0283c068-9a74-42d7-97db-a83fb3d32881
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827616572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.827616572
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2239969681
Short name T830
Test name
Test status
Simulation time 808547172 ps
CPU time 9.75 seconds
Started Jun 30 06:48:21 PM PDT 24
Finished Jun 30 06:48:32 PM PDT 24
Peak memory 218432 kb
Host smart-b26ea128-9333-4c1c-bcba-e7b4a2c9be27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239969681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2239969681
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.983193206
Short name T446
Test name
Test status
Simulation time 989849680 ps
CPU time 22.74 seconds
Started Jun 30 06:48:28 PM PDT 24
Finished Jun 30 06:48:51 PM PDT 24
Peak memory 217740 kb
Host smart-65bdca8e-f4d9-4434-84be-5102e692c3fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983193206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.983193206
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.1598953859
Short name T502
Test name
Test status
Simulation time 49902863 ps
CPU time 2.14 seconds
Started Jun 30 06:48:22 PM PDT 24
Finished Jun 30 06:48:25 PM PDT 24
Peak memory 222232 kb
Host smart-1466e927-6913-44fc-8261-7b167279d6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598953859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.1598953859
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.3940258654
Short name T661
Test name
Test status
Simulation time 578314438 ps
CPU time 16.47 seconds
Started Jun 30 06:48:26 PM PDT 24
Finished Jun 30 06:48:43 PM PDT 24
Peak memory 226236 kb
Host smart-9c4ac07b-4fbe-4505-aee0-c06f4b2be226
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940258654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.3940258654
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1406991804
Short name T833
Test name
Test status
Simulation time 393741606 ps
CPU time 11.71 seconds
Started Jun 30 06:48:27 PM PDT 24
Finished Jun 30 06:48:40 PM PDT 24
Peak memory 218536 kb
Host smart-d536229d-c717-459f-8b8e-7349c5b6fc75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406991804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1406991804
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.3492143989
Short name T552
Test name
Test status
Simulation time 577897541 ps
CPU time 11.46 seconds
Started Jun 30 06:48:30 PM PDT 24
Finished Jun 30 06:48:42 PM PDT 24
Peak memory 226260 kb
Host smart-4921175f-6ebb-4eb7-8dfd-3f586fd02fae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492143989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
3492143989
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.1514534361
Short name T340
Test name
Test status
Simulation time 801062709 ps
CPU time 7.19 seconds
Started Jun 30 06:48:22 PM PDT 24
Finished Jun 30 06:48:30 PM PDT 24
Peak memory 218652 kb
Host smart-b85535f3-95d3-49e9-a6ff-a0ada3049cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514534361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.1514534361
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.588948213
Short name T623
Test name
Test status
Simulation time 42080838 ps
CPU time 3.11 seconds
Started Jun 30 06:48:21 PM PDT 24
Finished Jun 30 06:48:25 PM PDT 24
Peak memory 215416 kb
Host smart-0b606ea6-d48e-4e7e-8bb8-138601f1e8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588948213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.588948213
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.2618386289
Short name T299
Test name
Test status
Simulation time 769005557 ps
CPU time 25.03 seconds
Started Jun 30 06:48:20 PM PDT 24
Finished Jun 30 06:48:46 PM PDT 24
Peak memory 251104 kb
Host smart-7be1bd78-6b69-4270-ba9d-ec479071c123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618386289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.2618386289
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.2827636541
Short name T789
Test name
Test status
Simulation time 65877244 ps
CPU time 8.9 seconds
Started Jun 30 06:48:21 PM PDT 24
Finished Jun 30 06:48:30 PM PDT 24
Peak memory 245516 kb
Host smart-c42c1e1f-7f0e-4f5d-ad39-1d1be599e4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827636541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.2827636541
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.749517906
Short name T577
Test name
Test status
Simulation time 9916648849 ps
CPU time 166.83 seconds
Started Jun 30 06:48:26 PM PDT 24
Finished Jun 30 06:51:14 PM PDT 24
Peak memory 283676 kb
Host smart-73c80858-da70-4be3-a62a-350c790a576c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749517906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.749517906
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2410220485
Short name T317
Test name
Test status
Simulation time 41648341 ps
CPU time 0.89 seconds
Started Jun 30 06:48:21 PM PDT 24
Finished Jun 30 06:48:23 PM PDT 24
Peak memory 212204 kb
Host smart-3647ad47-d1f1-49a3-af5b-2d91302d9268
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410220485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.2410220485
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.2356523231
Short name T632
Test name
Test status
Simulation time 101695345 ps
CPU time 0.99 seconds
Started Jun 30 06:46:18 PM PDT 24
Finished Jun 30 06:46:20 PM PDT 24
Peak memory 209380 kb
Host smart-8be2e2ea-5179-4146-a8b5-afab23065fa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356523231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.2356523231
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1341136036
Short name T63
Test name
Test status
Simulation time 20019765 ps
CPU time 0.88 seconds
Started Jun 30 06:46:11 PM PDT 24
Finished Jun 30 06:46:13 PM PDT 24
Peak memory 208840 kb
Host smart-f9de4a3f-8a05-4863-8f79-09f403a058d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341136036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1341136036
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2072617421
Short name T587
Test name
Test status
Simulation time 1449989515 ps
CPU time 17.89 seconds
Started Jun 30 06:46:11 PM PDT 24
Finished Jun 30 06:46:31 PM PDT 24
Peak memory 217732 kb
Host smart-cd597ac6-62bd-4e4c-95c1-39710312fdb8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072617421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2072617421
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.3341757125
Short name T795
Test name
Test status
Simulation time 9107593731 ps
CPU time 25.36 seconds
Started Jun 30 06:46:13 PM PDT 24
Finished Jun 30 06:46:40 PM PDT 24
Peak memory 226280 kb
Host smart-36c1912b-0bff-45fd-9f01-263c9ca2532e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341757125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.3341757125
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.411939267
Short name T389
Test name
Test status
Simulation time 21785513634 ps
CPU time 29.77 seconds
Started Jun 30 06:46:12 PM PDT 24
Finished Jun 30 06:46:44 PM PDT 24
Peak memory 218012 kb
Host smart-fe7f9e11-fb58-4ce4-9311-6b1f458a749d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411939267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.411939267
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.2869372411
Short name T263
Test name
Test status
Simulation time 121609314 ps
CPU time 4.32 seconds
Started Jun 30 06:46:13 PM PDT 24
Finished Jun 30 06:46:19 PM PDT 24
Peak memory 221928 kb
Host smart-2bccb2ee-9020-418d-9ae3-3c505a7ad201
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869372411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.2869372411
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1435307527
Short name T503
Test name
Test status
Simulation time 4508231610 ps
CPU time 17.11 seconds
Started Jun 30 06:46:11 PM PDT 24
Finished Jun 30 06:46:30 PM PDT 24
Peak memory 218008 kb
Host smart-53e13f50-31f7-4ed5-b8c9-b18c71c39ac7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435307527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.1435307527
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3194335745
Short name T231
Test name
Test status
Simulation time 131919348 ps
CPU time 2.01 seconds
Started Jun 30 06:46:12 PM PDT 24
Finished Jun 30 06:46:15 PM PDT 24
Peak memory 217912 kb
Host smart-e5dfc509-bb5a-4665-a15d-605a9116c46b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194335745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3194335745
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2346581593
Short name T490
Test name
Test status
Simulation time 4877032974 ps
CPU time 33.45 seconds
Started Jun 30 06:46:11 PM PDT 24
Finished Jun 30 06:46:46 PM PDT 24
Peak memory 251188 kb
Host smart-8d530a75-8a2b-4906-a317-050cd24b4bc6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346581593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2346581593
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2642361448
Short name T257
Test name
Test status
Simulation time 1818453892 ps
CPU time 13.31 seconds
Started Jun 30 06:46:15 PM PDT 24
Finished Jun 30 06:46:29 PM PDT 24
Peak memory 251124 kb
Host smart-2c092920-9cf7-4ebb-b617-ddaba9c6501f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642361448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2642361448
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3841337971
Short name T825
Test name
Test status
Simulation time 142520984 ps
CPU time 2.57 seconds
Started Jun 30 06:46:12 PM PDT 24
Finished Jun 30 06:46:16 PM PDT 24
Peak memory 218408 kb
Host smart-1bdc94a3-fe44-4d55-a1a6-04ea2419c101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841337971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3841337971
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.645906869
Short name T422
Test name
Test status
Simulation time 591425888 ps
CPU time 17.07 seconds
Started Jun 30 06:46:15 PM PDT 24
Finished Jun 30 06:46:33 PM PDT 24
Peak memory 217948 kb
Host smart-bc5def0a-3896-4062-87d9-580d79b80a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645906869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.645906869
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.252917053
Short name T559
Test name
Test status
Simulation time 435553753 ps
CPU time 12.93 seconds
Started Jun 30 06:46:13 PM PDT 24
Finished Jun 30 06:46:28 PM PDT 24
Peak memory 218472 kb
Host smart-3f6c112e-505a-4e50-9050-cd0f02352e4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252917053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.252917053
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.222257776
Short name T169
Test name
Test status
Simulation time 2852938233 ps
CPU time 11.34 seconds
Started Jun 30 06:46:11 PM PDT 24
Finished Jun 30 06:46:24 PM PDT 24
Peak memory 218516 kb
Host smart-e44bc0a0-5f7b-45c3-950b-03a1ef4c02e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222257776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dig
est.222257776
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.1103576339
Short name T352
Test name
Test status
Simulation time 821914810 ps
CPU time 6.75 seconds
Started Jun 30 06:46:12 PM PDT 24
Finished Jun 30 06:46:20 PM PDT 24
Peak memory 218424 kb
Host smart-4905d335-fcbd-49a8-94a5-d93b11e1be90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103576339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.1
103576339
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.3268271260
Short name T395
Test name
Test status
Simulation time 2059076085 ps
CPU time 12.62 seconds
Started Jun 30 06:46:15 PM PDT 24
Finished Jun 30 06:46:28 PM PDT 24
Peak memory 218564 kb
Host smart-48dad591-eff5-4aa6-a0f2-f22eaf2779de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268271260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.3268271260
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.449291301
Short name T760
Test name
Test status
Simulation time 21733015 ps
CPU time 1.55 seconds
Started Jun 30 06:46:15 PM PDT 24
Finished Jun 30 06:46:17 PM PDT 24
Peak memory 217992 kb
Host smart-833ba1c5-d63e-447c-9b74-b237e7f5a482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449291301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.449291301
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1794585910
Short name T785
Test name
Test status
Simulation time 1199431433 ps
CPU time 29.18 seconds
Started Jun 30 06:46:15 PM PDT 24
Finished Jun 30 06:46:45 PM PDT 24
Peak memory 251132 kb
Host smart-0bd1d4b0-d325-481b-a6d3-69c27cc2217f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794585910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1794585910
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.2675628082
Short name T155
Test name
Test status
Simulation time 62107761 ps
CPU time 7.24 seconds
Started Jun 30 06:46:12 PM PDT 24
Finished Jun 30 06:46:21 PM PDT 24
Peak memory 251144 kb
Host smart-73bd3a93-eb9e-4cfe-bb47-d08f45f1be99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675628082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2675628082
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.3173226380
Short name T434
Test name
Test status
Simulation time 4174944614 ps
CPU time 140.1 seconds
Started Jun 30 06:46:09 PM PDT 24
Finished Jun 30 06:48:30 PM PDT 24
Peak memory 272980 kb
Host smart-e6ce1dd9-76f1-4336-992f-07a6e9f493f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173226380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.3173226380
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.709565855
Short name T392
Test name
Test status
Simulation time 12322566 ps
CPU time 0.88 seconds
Started Jun 30 06:46:10 PM PDT 24
Finished Jun 30 06:46:12 PM PDT 24
Peak memory 212096 kb
Host smart-5ddd99d0-d46e-473c-8311-eafba286ed46
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709565855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr
l_volatile_unlock_smoke.709565855
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.2903258869
Short name T499
Test name
Test status
Simulation time 19809465 ps
CPU time 0.89 seconds
Started Jun 30 06:46:16 PM PDT 24
Finished Jun 30 06:46:17 PM PDT 24
Peak memory 209256 kb
Host smart-9af88eaa-9bdc-455e-a90a-e6a93b103ce3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903258869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2903258869
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.784714279
Short name T206
Test name
Test status
Simulation time 109639026 ps
CPU time 0.89 seconds
Started Jun 30 06:46:18 PM PDT 24
Finished Jun 30 06:46:20 PM PDT 24
Peak memory 209188 kb
Host smart-fb8c7a36-8a2d-409d-8ca6-63f71c5b0ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784714279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.784714279
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.2654067387
Short name T806
Test name
Test status
Simulation time 1429906697 ps
CPU time 11.51 seconds
Started Jun 30 06:46:18 PM PDT 24
Finished Jun 30 06:46:30 PM PDT 24
Peak memory 218448 kb
Host smart-797daa90-f05a-4909-afae-2160eeae17cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654067387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.2654067387
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.2044594015
Short name T424
Test name
Test status
Simulation time 469511719 ps
CPU time 2.04 seconds
Started Jun 30 06:46:18 PM PDT 24
Finished Jun 30 06:46:21 PM PDT 24
Peak memory 217336 kb
Host smart-9b963b07-a96d-4bf1-80b6-f06ca76ae27b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044594015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.2044594015
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.1507721027
Short name T35
Test name
Test status
Simulation time 8353313193 ps
CPU time 33.58 seconds
Started Jun 30 06:46:17 PM PDT 24
Finished Jun 30 06:46:51 PM PDT 24
Peak memory 218864 kb
Host smart-992818ab-dc6d-4c19-953d-3ce11881f027
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507721027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.1507721027
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1920817716
Short name T370
Test name
Test status
Simulation time 1429762501 ps
CPU time 15.95 seconds
Started Jun 30 06:46:16 PM PDT 24
Finished Jun 30 06:46:33 PM PDT 24
Peak memory 217956 kb
Host smart-19397659-095d-47bd-aef1-930eed8074e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920817716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
920817716
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2504304475
Short name T281
Test name
Test status
Simulation time 196125979 ps
CPU time 2.75 seconds
Started Jun 30 06:46:20 PM PDT 24
Finished Jun 30 06:46:23 PM PDT 24
Peak memory 221888 kb
Host smart-e1724110-5f0c-430c-afb2-64e1cb49272d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504304475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2504304475
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2466531090
Short name T574
Test name
Test status
Simulation time 5254121536 ps
CPU time 19.48 seconds
Started Jun 30 06:46:21 PM PDT 24
Finished Jun 30 06:46:40 PM PDT 24
Peak memory 217928 kb
Host smart-44ef2e6d-0830-4dff-adae-39fe32611755
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466531090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.2466531090
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3951440316
Short name T160
Test name
Test status
Simulation time 852419067 ps
CPU time 7.5 seconds
Started Jun 30 06:46:18 PM PDT 24
Finished Jun 30 06:46:26 PM PDT 24
Peak memory 217920 kb
Host smart-f7a4b118-02ac-4479-8777-dab4b114ed99
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951440316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3951440316
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.4121954264
Short name T322
Test name
Test status
Simulation time 4028299073 ps
CPU time 49.76 seconds
Started Jun 30 06:46:21 PM PDT 24
Finished Jun 30 06:47:11 PM PDT 24
Peak memory 253700 kb
Host smart-3c94c118-b336-441a-9871-e3ce92afcb58
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121954264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.4121954264
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2498306520
Short name T152
Test name
Test status
Simulation time 1542933814 ps
CPU time 14.71 seconds
Started Jun 30 06:46:19 PM PDT 24
Finished Jun 30 06:46:34 PM PDT 24
Peak memory 250704 kb
Host smart-d92cf237-db6f-4773-9c43-f0bdb5fd37ed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498306520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.2498306520
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.306425562
Short name T529
Test name
Test status
Simulation time 205716503 ps
CPU time 2.67 seconds
Started Jun 30 06:46:18 PM PDT 24
Finished Jun 30 06:46:22 PM PDT 24
Peak memory 218308 kb
Host smart-54705f7a-ca05-47a4-a43a-b108b04876e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306425562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.306425562
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3364343343
Short name T442
Test name
Test status
Simulation time 243351357 ps
CPU time 15.7 seconds
Started Jun 30 06:46:18 PM PDT 24
Finished Jun 30 06:46:35 PM PDT 24
Peak memory 214944 kb
Host smart-7dcdde97-6c3d-495f-b4f7-8435aeee7992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364343343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3364343343
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.3455603163
Short name T378
Test name
Test status
Simulation time 406132698 ps
CPU time 14.11 seconds
Started Jun 30 06:46:17 PM PDT 24
Finished Jun 30 06:46:32 PM PDT 24
Peak memory 226248 kb
Host smart-681d7f27-7273-4b30-99f2-b0c7ce13eea7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455603163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3455603163
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.4200097424
Short name T391
Test name
Test status
Simulation time 1135841612 ps
CPU time 15.94 seconds
Started Jun 30 06:46:18 PM PDT 24
Finished Jun 30 06:46:35 PM PDT 24
Peak memory 218408 kb
Host smart-c83b89a4-c1ac-45f9-8dc0-e48edf965c00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200097424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.4200097424
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3556957542
Short name T341
Test name
Test status
Simulation time 361636642 ps
CPU time 8.5 seconds
Started Jun 30 06:46:20 PM PDT 24
Finished Jun 30 06:46:29 PM PDT 24
Peak memory 225096 kb
Host smart-61cc1985-fcd1-4933-80d9-c3437f234a1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556957542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3
556957542
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.1409378293
Short name T848
Test name
Test status
Simulation time 512714794 ps
CPU time 12.15 seconds
Started Jun 30 06:46:18 PM PDT 24
Finished Jun 30 06:46:31 PM PDT 24
Peak memory 218556 kb
Host smart-36a99d13-4932-4160-ac04-653aa9f56b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409378293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1409378293
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.769356133
Short name T644
Test name
Test status
Simulation time 51468242 ps
CPU time 1.83 seconds
Started Jun 30 06:46:18 PM PDT 24
Finished Jun 30 06:46:21 PM PDT 24
Peak memory 217892 kb
Host smart-6a700dba-8510-4694-9868-87719c89ad44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769356133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.769356133
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.1823893141
Short name T747
Test name
Test status
Simulation time 1301950709 ps
CPU time 20.92 seconds
Started Jun 30 06:46:17 PM PDT 24
Finished Jun 30 06:46:38 PM PDT 24
Peak memory 251124 kb
Host smart-1f640c53-f650-4fd9-85a9-04b0892e2df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823893141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1823893141
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.439668928
Short name T321
Test name
Test status
Simulation time 519630386 ps
CPU time 11.45 seconds
Started Jun 30 06:46:18 PM PDT 24
Finished Jun 30 06:46:30 PM PDT 24
Peak memory 251148 kb
Host smart-1490bdc0-b5fb-40de-b885-5486cf14ba65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439668928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.439668928
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.1092627556
Short name T821
Test name
Test status
Simulation time 12721740841 ps
CPU time 386.85 seconds
Started Jun 30 06:46:17 PM PDT 24
Finished Jun 30 06:52:44 PM PDT 24
Peak memory 313620 kb
Host smart-c7bcdd60-7f62-4651-8d34-79fb9dccb271
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092627556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.1092627556
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2791565970
Short name T246
Test name
Test status
Simulation time 23179018 ps
CPU time 0.88 seconds
Started Jun 30 06:46:19 PM PDT 24
Finished Jun 30 06:46:20 PM PDT 24
Peak memory 212172 kb
Host smart-67d7d2e3-3cee-494f-a6af-6ca9e57571e8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791565970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2791565970
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.218165800
Short name T655
Test name
Test status
Simulation time 73766807 ps
CPU time 0.92 seconds
Started Jun 30 06:46:23 PM PDT 24
Finished Jun 30 06:46:25 PM PDT 24
Peak memory 209336 kb
Host smart-051d689d-1d55-449e-9982-e605b7c5ed0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218165800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.218165800
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.558617092
Short name T208
Test name
Test status
Simulation time 12764700 ps
CPU time 0.96 seconds
Started Jun 30 06:46:26 PM PDT 24
Finished Jun 30 06:46:27 PM PDT 24
Peak memory 209204 kb
Host smart-b0d58bc1-04cf-4d29-b9a5-04a1dd129694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558617092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.558617092
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.3379628064
Short name T521
Test name
Test status
Simulation time 581755367 ps
CPU time 14.46 seconds
Started Jun 30 06:46:21 PM PDT 24
Finished Jun 30 06:46:36 PM PDT 24
Peak memory 226164 kb
Host smart-42cd9fc5-5bd3-4092-8be3-a01518c8b562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379628064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3379628064
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.445163088
Short name T7
Test name
Test status
Simulation time 272436745 ps
CPU time 3.95 seconds
Started Jun 30 06:46:22 PM PDT 24
Finished Jun 30 06:46:27 PM PDT 24
Peak memory 217536 kb
Host smart-def71d29-5fc0-4374-a622-b147dc798c4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445163088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.445163088
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.449376476
Short name T763
Test name
Test status
Simulation time 9823848929 ps
CPU time 42.8 seconds
Started Jun 30 06:46:23 PM PDT 24
Finished Jun 30 06:47:07 PM PDT 24
Peak memory 226304 kb
Host smart-e23277e9-4d64-458b-bce1-95a8169752b9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449376476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_err
ors.449376476
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.3317947860
Short name T817
Test name
Test status
Simulation time 4876136634 ps
CPU time 11.33 seconds
Started Jun 30 06:46:23 PM PDT 24
Finished Jun 30 06:46:35 PM PDT 24
Peak memory 218028 kb
Host smart-97d895c4-9394-4da1-b292-18cb83cf9100
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317947860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.3
317947860
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.961567
Short name T560
Test name
Test status
Simulation time 444364020 ps
CPU time 7.74 seconds
Started Jun 30 06:46:25 PM PDT 24
Finished Jun 30 06:46:33 PM PDT 24
Peak memory 218444 kb
Host smart-d36d5dc3-f1c3-4fd2-8381-42227c2a9c4e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_pro
g_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_pro
g_failure.961567
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1821071558
Short name T58
Test name
Test status
Simulation time 676180522 ps
CPU time 11.81 seconds
Started Jun 30 06:46:25 PM PDT 24
Finished Jun 30 06:46:37 PM PDT 24
Peak memory 217868 kb
Host smart-78abc6dc-06e2-4497-b631-f8b62d4be2cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821071558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.1821071558
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1306990288
Short name T255
Test name
Test status
Simulation time 854929540 ps
CPU time 6.19 seconds
Started Jun 30 06:46:24 PM PDT 24
Finished Jun 30 06:46:31 PM PDT 24
Peak memory 217908 kb
Host smart-133e600a-175e-4a32-b0f2-73ac00e25c7e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306990288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1306990288
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.819632941
Short name T245
Test name
Test status
Simulation time 870870713 ps
CPU time 36.77 seconds
Started Jun 30 06:46:23 PM PDT 24
Finished Jun 30 06:47:01 PM PDT 24
Peak memory 251112 kb
Host smart-d7313d51-4734-4100-889e-6d3a4358c34d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819632941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_state_failure.819632941
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.988724517
Short name T99
Test name
Test status
Simulation time 1423705093 ps
CPU time 11.43 seconds
Started Jun 30 06:46:22 PM PDT 24
Finished Jun 30 06:46:34 PM PDT 24
Peak memory 250696 kb
Host smart-95bad2ad-895e-48b9-99f3-ecf09a3d7f55
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988724517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_state_post_trans.988724517
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.4114269971
Short name T797
Test name
Test status
Simulation time 91690675 ps
CPU time 2.11 seconds
Started Jun 30 06:46:23 PM PDT 24
Finished Jun 30 06:46:26 PM PDT 24
Peak memory 222416 kb
Host smart-00ea850c-2d45-4352-a164-4f50f6215d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114269971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.4114269971
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.1242601641
Short name T176
Test name
Test status
Simulation time 215157141 ps
CPU time 11.99 seconds
Started Jun 30 06:46:24 PM PDT 24
Finished Jun 30 06:46:37 PM PDT 24
Peak memory 217844 kb
Host smart-448cadb9-df3b-4024-acd4-13c7f81ab2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242601641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.1242601641
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.3757286549
Short name T407
Test name
Test status
Simulation time 4337536903 ps
CPU time 15.02 seconds
Started Jun 30 06:46:23 PM PDT 24
Finished Jun 30 06:46:39 PM PDT 24
Peak memory 226308 kb
Host smart-2ee342d2-3b84-4208-9ff3-e6d70789c97e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757286549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.3757286549
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.353503064
Short name T841
Test name
Test status
Simulation time 443281973 ps
CPU time 6.5 seconds
Started Jun 30 06:46:22 PM PDT 24
Finished Jun 30 06:46:30 PM PDT 24
Peak memory 218428 kb
Host smart-c6dd63aa-0f0c-4d6a-b1fa-38fa41f8a05b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353503064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dig
est.353503064
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.349243673
Short name T55
Test name
Test status
Simulation time 435936900 ps
CPU time 7.87 seconds
Started Jun 30 06:46:22 PM PDT 24
Finished Jun 30 06:46:31 PM PDT 24
Peak memory 218424 kb
Host smart-f3eac807-434d-45bd-a39b-1c2a2b17ec6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349243673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.349243673
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.3142041255
Short name T743
Test name
Test status
Simulation time 1029115330 ps
CPU time 9.08 seconds
Started Jun 30 06:46:23 PM PDT 24
Finished Jun 30 06:46:33 PM PDT 24
Peak memory 218740 kb
Host smart-98951c2a-b6b4-46ca-ad89-9c013ded56a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142041255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.3142041255
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.3863981563
Short name T59
Test name
Test status
Simulation time 21413131 ps
CPU time 1.87 seconds
Started Jun 30 06:46:16 PM PDT 24
Finished Jun 30 06:46:19 PM PDT 24
Peak memory 214104 kb
Host smart-367d6a6d-d145-41fc-adfb-9a4149dc19d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863981563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.3863981563
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3513674030
Short name T279
Test name
Test status
Simulation time 218957464 ps
CPU time 20.92 seconds
Started Jun 30 06:46:25 PM PDT 24
Finished Jun 30 06:46:46 PM PDT 24
Peak memory 251136 kb
Host smart-c1a1ac31-7d99-44c7-a58d-4fe4fbdd453f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513674030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3513674030
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1305543381
Short name T753
Test name
Test status
Simulation time 56503903 ps
CPU time 6.69 seconds
Started Jun 30 06:46:24 PM PDT 24
Finished Jun 30 06:46:31 PM PDT 24
Peak memory 250732 kb
Host smart-34ea1591-a589-4daf-bc10-48c2f7aba687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305543381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1305543381
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.1542175766
Short name T464
Test name
Test status
Simulation time 6976115233 ps
CPU time 30.57 seconds
Started Jun 30 06:46:21 PM PDT 24
Finished Jun 30 06:46:52 PM PDT 24
Peak memory 251176 kb
Host smart-5d42d487-575c-44f3-aef5-00b25865aae2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542175766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.1542175766
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2149218153
Short name T656
Test name
Test status
Simulation time 31248412 ps
CPU time 0.89 seconds
Started Jun 30 06:46:18 PM PDT 24
Finished Jun 30 06:46:19 PM PDT 24
Peak memory 211872 kb
Host smart-2c846ce7-5d73-47ef-bf5c-39a0a5e70a28
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149218153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.2149218153
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.2651924799
Short name T226
Test name
Test status
Simulation time 18462270 ps
CPU time 0.88 seconds
Started Jun 30 06:46:28 PM PDT 24
Finished Jun 30 06:46:29 PM PDT 24
Peak memory 209148 kb
Host smart-c1333946-877b-42a1-9809-0a1abedd5935
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651924799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.2651924799
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.3598442343
Short name T428
Test name
Test status
Simulation time 86017127 ps
CPU time 0.85 seconds
Started Jun 30 06:46:26 PM PDT 24
Finished Jun 30 06:46:28 PM PDT 24
Peak memory 209256 kb
Host smart-42947cd9-f4de-4259-97d0-7b19eb4e22ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598442343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.3598442343
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.4135776542
Short name T538
Test name
Test status
Simulation time 307602871 ps
CPU time 15 seconds
Started Jun 30 06:46:23 PM PDT 24
Finished Jun 30 06:46:39 PM PDT 24
Peak memory 218316 kb
Host smart-9b111d28-3d50-495c-8ead-0a652117a93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135776542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.4135776542
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.418474701
Short name T26
Test name
Test status
Simulation time 2876857735 ps
CPU time 8.41 seconds
Started Jun 30 06:46:30 PM PDT 24
Finished Jun 30 06:46:39 PM PDT 24
Peak memory 217812 kb
Host smart-52288aec-99ba-4740-97a1-cb71753c90b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418474701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.418474701
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.917100560
Short name T613
Test name
Test status
Simulation time 5062258223 ps
CPU time 40.32 seconds
Started Jun 30 06:46:33 PM PDT 24
Finished Jun 30 06:47:15 PM PDT 24
Peak memory 219000 kb
Host smart-9e417168-d443-4e64-a4b2-09e467a534d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917100560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_err
ors.917100560
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.4169499503
Short name T703
Test name
Test status
Simulation time 1929433870 ps
CPU time 12.07 seconds
Started Jun 30 06:46:29 PM PDT 24
Finished Jun 30 06:46:42 PM PDT 24
Peak memory 217708 kb
Host smart-0e0e5452-fe1d-47f3-9518-1b3548da9f05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169499503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.4
169499503
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2987846598
Short name T305
Test name
Test status
Simulation time 815057162 ps
CPU time 21.87 seconds
Started Jun 30 06:46:23 PM PDT 24
Finished Jun 30 06:46:46 PM PDT 24
Peak memory 218396 kb
Host smart-cd5240d5-114e-489d-8a23-d6ea4fbfe800
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987846598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2987846598
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1919008675
Short name T691
Test name
Test status
Simulation time 2363949670 ps
CPU time 35.19 seconds
Started Jun 30 06:46:34 PM PDT 24
Finished Jun 30 06:47:11 PM PDT 24
Peak memory 217940 kb
Host smart-9ee3f332-c43e-49e8-9085-5430327f11e3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919008675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.1919008675
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.694632791
Short name T60
Test name
Test status
Simulation time 935769877 ps
CPU time 7.51 seconds
Started Jun 30 06:46:26 PM PDT 24
Finished Jun 30 06:46:34 PM PDT 24
Peak memory 217912 kb
Host smart-dad81436-6f99-428a-b775-6ce31c00d6ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694632791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.694632791
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.1589783815
Short name T320
Test name
Test status
Simulation time 5404978737 ps
CPU time 70.6 seconds
Started Jun 30 06:46:23 PM PDT 24
Finished Jun 30 06:47:34 PM PDT 24
Peak memory 283984 kb
Host smart-060d048d-11cb-49f1-9d04-dfee15377269
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589783815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.1589783815
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1443609803
Short name T534
Test name
Test status
Simulation time 5150206329 ps
CPU time 16.34 seconds
Started Jun 30 06:46:24 PM PDT 24
Finished Jun 30 06:46:41 PM PDT 24
Peak memory 226480 kb
Host smart-29c57427-5d91-44d3-80d2-d5befe3592fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443609803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.1443609803
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.974494499
Short name T348
Test name
Test status
Simulation time 179255545 ps
CPU time 4.45 seconds
Started Jun 30 06:46:22 PM PDT 24
Finished Jun 30 06:46:27 PM PDT 24
Peak memory 222648 kb
Host smart-d70f2482-652a-4792-9c8b-e3570a5e41f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974494499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.974494499
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.893865013
Short name T721
Test name
Test status
Simulation time 563029150 ps
CPU time 5.58 seconds
Started Jun 30 06:46:22 PM PDT 24
Finished Jun 30 06:46:29 PM PDT 24
Peak memory 217900 kb
Host smart-419daa24-6f75-4d37-afda-7bb1a21a1873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893865013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.893865013
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3113302022
Short name T866
Test name
Test status
Simulation time 1593905361 ps
CPU time 12.31 seconds
Started Jun 30 06:46:33 PM PDT 24
Finished Jun 30 06:46:46 PM PDT 24
Peak memory 226072 kb
Host smart-c8c64171-849d-4b39-ada8-2878f4ca41c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113302022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3113302022
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.1906300813
Short name T405
Test name
Test status
Simulation time 409177131 ps
CPU time 15.88 seconds
Started Jun 30 06:46:33 PM PDT 24
Finished Jun 30 06:46:49 PM PDT 24
Peak memory 218452 kb
Host smart-8ce06c13-801a-4f61-bd4f-573acc581a1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906300813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.1906300813
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3681731286
Short name T95
Test name
Test status
Simulation time 912848465 ps
CPU time 6.39 seconds
Started Jun 30 06:46:30 PM PDT 24
Finished Jun 30 06:46:37 PM PDT 24
Peak memory 218464 kb
Host smart-ca409ca3-0139-439d-b5e1-1721f2d7945f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681731286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
681731286
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.567745861
Short name T430
Test name
Test status
Simulation time 270376191 ps
CPU time 6.86 seconds
Started Jun 30 06:46:22 PM PDT 24
Finished Jun 30 06:46:30 PM PDT 24
Peak memory 218432 kb
Host smart-3a6d67f0-9a85-41ae-affe-37425cbb7710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567745861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.567745861
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.1839683
Short name T153
Test name
Test status
Simulation time 94624860 ps
CPU time 2.48 seconds
Started Jun 30 06:46:23 PM PDT 24
Finished Jun 30 06:46:27 PM PDT 24
Peak memory 214708 kb
Host smart-1c9f1faa-e3e8-44b7-94b4-d9aa3041278e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.1839683
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.1847208548
Short name T508
Test name
Test status
Simulation time 173188384 ps
CPU time 20.58 seconds
Started Jun 30 06:46:25 PM PDT 24
Finished Jun 30 06:46:46 PM PDT 24
Peak memory 251224 kb
Host smart-a071fb7d-ca16-4ba2-a17f-18426c25f7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847208548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.1847208548
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3817342304
Short name T481
Test name
Test status
Simulation time 120596015 ps
CPU time 7.43 seconds
Started Jun 30 06:46:25 PM PDT 24
Finished Jun 30 06:46:33 PM PDT 24
Peak memory 251164 kb
Host smart-1c7e9c7f-718c-43af-bfe9-507ed1ca8f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817342304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3817342304
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.188512125
Short name T711
Test name
Test status
Simulation time 4904467507 ps
CPU time 93.51 seconds
Started Jun 30 06:46:28 PM PDT 24
Finished Jun 30 06:48:02 PM PDT 24
Peak memory 268924 kb
Host smart-f4d61260-b3c7-47fc-9693-d821e271a399
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188512125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.188512125
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.2444788675
Short name T136
Test name
Test status
Simulation time 54826253873 ps
CPU time 610.87 seconds
Started Jun 30 06:46:31 PM PDT 24
Finished Jun 30 06:56:43 PM PDT 24
Peak memory 276160 kb
Host smart-f711a7d4-b0a6-4d07-8c48-6c0423bd3d24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2444788675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.2444788675
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1756523527
Short name T651
Test name
Test status
Simulation time 38010970 ps
CPU time 0.82 seconds
Started Jun 30 06:46:23 PM PDT 24
Finished Jun 30 06:46:25 PM PDT 24
Peak memory 212092 kb
Host smart-fc673dad-aab1-47a1-b957-8d9cfa0ef4a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756523527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.1756523527
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3335979030
Short name T382
Test name
Test status
Simulation time 28957433 ps
CPU time 1.08 seconds
Started Jun 30 06:46:33 PM PDT 24
Finished Jun 30 06:46:35 PM PDT 24
Peak memory 209172 kb
Host smart-89e4363d-abc4-4237-9b7e-0ddb98e1a829
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335979030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3335979030
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.3572086637
Short name T810
Test name
Test status
Simulation time 1165871133 ps
CPU time 13.91 seconds
Started Jun 30 06:46:30 PM PDT 24
Finished Jun 30 06:46:44 PM PDT 24
Peak memory 218436 kb
Host smart-f7306732-6bf7-4163-86f4-72dfcf8f9a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572086637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.3572086637
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3899299630
Short name T463
Test name
Test status
Simulation time 249221356 ps
CPU time 6.18 seconds
Started Jun 30 06:46:33 PM PDT 24
Finished Jun 30 06:46:40 PM PDT 24
Peak memory 217352 kb
Host smart-f8c08604-8a35-4db3-8f2a-5437c2c051a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899299630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3899299630
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.4067282573
Short name T383
Test name
Test status
Simulation time 3385316094 ps
CPU time 50.33 seconds
Started Jun 30 06:46:29 PM PDT 24
Finished Jun 30 06:47:20 PM PDT 24
Peak memory 219200 kb
Host smart-3489b8ba-74df-437e-b54c-9a2c956dfcb0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067282573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.4067282573
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.3514901407
Short name T606
Test name
Test status
Simulation time 212696154 ps
CPU time 3.84 seconds
Started Jun 30 06:46:33 PM PDT 24
Finished Jun 30 06:46:38 PM PDT 24
Peak memory 217964 kb
Host smart-4ba8687a-c28b-4be6-87de-515d78ca0385
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514901407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.3
514901407
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2563804420
Short name T588
Test name
Test status
Simulation time 325292120 ps
CPU time 9 seconds
Started Jun 30 06:46:27 PM PDT 24
Finished Jun 30 06:46:37 PM PDT 24
Peak memory 218428 kb
Host smart-2433d364-56c4-4acd-9d45-717121791a5c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563804420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2563804420
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3387933450
Short name T171
Test name
Test status
Simulation time 3007499957 ps
CPU time 10.78 seconds
Started Jun 30 06:46:27 PM PDT 24
Finished Jun 30 06:46:39 PM PDT 24
Peak memory 218000 kb
Host smart-5cdbb535-fe0f-4aae-9ab5-8a225238301d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387933450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3387933450
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.223059190
Short name T66
Test name
Test status
Simulation time 433345614 ps
CPU time 5.53 seconds
Started Jun 30 06:46:31 PM PDT 24
Finished Jun 30 06:46:37 PM PDT 24
Peak memory 217916 kb
Host smart-6cf32084-f09d-4ce0-aced-7148ec887ad0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223059190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.223059190
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3734314653
Short name T19
Test name
Test status
Simulation time 3292036953 ps
CPU time 110.12 seconds
Started Jun 30 06:46:30 PM PDT 24
Finished Jun 30 06:48:21 PM PDT 24
Peak memory 283952 kb
Host smart-dc359abd-8ef6-4c6f-8e4e-282ae2c151db
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734314653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3734314653
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2063370932
Short name T563
Test name
Test status
Simulation time 287963122 ps
CPU time 10.31 seconds
Started Jun 30 06:46:30 PM PDT 24
Finished Jun 30 06:46:40 PM PDT 24
Peak memory 251152 kb
Host smart-50637beb-2e62-4ee9-88d7-eada6d296584
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063370932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.2063370932
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.2722583257
Short name T556
Test name
Test status
Simulation time 199861096 ps
CPU time 4.5 seconds
Started Jun 30 06:46:30 PM PDT 24
Finished Jun 30 06:46:35 PM PDT 24
Peak memory 218396 kb
Host smart-66ee1936-d0bf-492a-98ad-3f98aff55569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722583257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2722583257
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3647634387
Short name T177
Test name
Test status
Simulation time 1409857653 ps
CPU time 18.06 seconds
Started Jun 30 06:46:29 PM PDT 24
Finished Jun 30 06:46:47 PM PDT 24
Peak memory 217940 kb
Host smart-bf644f2b-0571-4bdb-8b60-de3a56696b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647634387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3647634387
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.3099160161
Short name T585
Test name
Test status
Simulation time 951349372 ps
CPU time 11.66 seconds
Started Jun 30 06:46:31 PM PDT 24
Finished Jun 30 06:46:43 PM PDT 24
Peak memory 226280 kb
Host smart-19bf66e7-bf04-4bac-a8db-b6d0aa188439
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099160161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.3099160161
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.1647755746
Short name T432
Test name
Test status
Simulation time 1631466674 ps
CPU time 10.57 seconds
Started Jun 30 06:46:34 PM PDT 24
Finished Jun 30 06:46:45 PM PDT 24
Peak memory 218524 kb
Host smart-33ed1b70-7234-4026-9096-85802499cc85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647755746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.1647755746
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2993031851
Short name T565
Test name
Test status
Simulation time 510774110 ps
CPU time 6.28 seconds
Started Jun 30 06:46:31 PM PDT 24
Finished Jun 30 06:46:38 PM PDT 24
Peak memory 218424 kb
Host smart-f7991a9d-8b80-4ec5-ae2e-1ff89eddced9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993031851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
993031851
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.2248693823
Short name T634
Test name
Test status
Simulation time 497842225 ps
CPU time 6.29 seconds
Started Jun 30 06:46:34 PM PDT 24
Finished Jun 30 06:46:41 PM PDT 24
Peak memory 218540 kb
Host smart-731237b6-69f3-4075-b420-fd480ffc4d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248693823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2248693823
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.307402328
Short name T859
Test name
Test status
Simulation time 314036323 ps
CPU time 4.46 seconds
Started Jun 30 06:46:34 PM PDT 24
Finished Jun 30 06:46:40 PM PDT 24
Peak memory 217900 kb
Host smart-0099c7f4-4739-4c4e-9f62-3bc900aff63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307402328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.307402328
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.200901106
Short name T589
Test name
Test status
Simulation time 215154509 ps
CPU time 26.24 seconds
Started Jun 30 06:46:31 PM PDT 24
Finished Jun 30 06:46:58 PM PDT 24
Peak memory 251192 kb
Host smart-ddb97a8c-6804-4bbf-947d-c035a8740ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200901106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.200901106
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.2199253112
Short name T410
Test name
Test status
Simulation time 311238425 ps
CPU time 6.39 seconds
Started Jun 30 06:46:34 PM PDT 24
Finished Jun 30 06:46:42 PM PDT 24
Peak memory 250572 kb
Host smart-6d1e5ae4-00c7-49f0-ac69-1ac1fe63d5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199253112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.2199253112
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.923823323
Short name T548
Test name
Test status
Simulation time 4465355102 ps
CPU time 23.84 seconds
Started Jun 30 06:46:34 PM PDT 24
Finished Jun 30 06:46:59 PM PDT 24
Peak memory 251264 kb
Host smart-181771b0-bef6-4206-852c-6e1805754d1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923823323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.923823323
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2516042539
Short name T509
Test name
Test status
Simulation time 29030519 ps
CPU time 0.81 seconds
Started Jun 30 06:46:32 PM PDT 24
Finished Jun 30 06:46:34 PM PDT 24
Peak memory 212076 kb
Host smart-2339f00c-da47-471f-8f14-ba75246590bb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516042539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.2516042539
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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