Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51075 |
1 |
|
|
T1 |
15 |
|
T2 |
41 |
|
T4 |
74 |
auto[1] |
1876 |
1 |
|
|
T2 |
10 |
|
T10 |
18 |
|
T12 |
34 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52197 |
1 |
|
|
T1 |
15 |
|
T2 |
51 |
|
T4 |
74 |
auto[1] |
754 |
1 |
|
|
T35 |
23 |
|
T52 |
13 |
|
T53 |
7 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51200 |
1 |
|
|
T1 |
14 |
|
T2 |
51 |
|
T4 |
67 |
auto[1] |
1751 |
1 |
|
|
T1 |
1 |
|
T4 |
7 |
|
T12 |
41 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51227 |
1 |
|
|
T1 |
14 |
|
T2 |
51 |
|
T4 |
66 |
auto[1] |
1724 |
1 |
|
|
T1 |
1 |
|
T4 |
8 |
|
T12 |
36 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51178 |
1 |
|
|
T1 |
15 |
|
T2 |
51 |
|
T4 |
65 |
auto[1] |
1773 |
1 |
|
|
T4 |
9 |
|
T12 |
51 |
|
T13 |
9 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
47930 |
1 |
|
|
T1 |
6 |
|
T2 |
51 |
|
T4 |
74 |
no_err_inj |
5021 |
1 |
|
|
T1 |
9 |
|
T5 |
9 |
|
T12 |
86 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51065 |
1 |
|
|
T1 |
15 |
|
T2 |
45 |
|
T4 |
74 |
auto[1] |
1886 |
1 |
|
|
T2 |
6 |
|
T10 |
15 |
|
T12 |
42 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52189 |
1 |
|
|
T1 |
15 |
|
T2 |
51 |
|
T4 |
74 |
auto[1] |
762 |
1 |
|
|
T35 |
18 |
|
T52 |
16 |
|
T53 |
6 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37163 |
1 |
|
|
T4 |
74 |
|
T10 |
99 |
|
T11 |
79 |
auto[1] |
15788 |
1 |
|
|
T1 |
15 |
|
T2 |
51 |
|
T5 |
9 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51250 |
1 |
|
|
T1 |
15 |
|
T2 |
51 |
|
T4 |
64 |
auto[1] |
1701 |
1 |
|
|
T4 |
10 |
|
T12 |
40 |
|
T13 |
10 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51249 |
1 |
|
|
T1 |
13 |
|
T2 |
51 |
|
T4 |
68 |
auto[1] |
1702 |
1 |
|
|
T1 |
2 |
|
T4 |
6 |
|
T12 |
39 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51223 |
1 |
|
|
T1 |
14 |
|
T2 |
51 |
|
T4 |
61 |
auto[1] |
1728 |
1 |
|
|
T1 |
1 |
|
T4 |
13 |
|
T12 |
44 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51038 |
1 |
|
|
T1 |
15 |
|
T2 |
41 |
|
T4 |
74 |
auto[1] |
1913 |
1 |
|
|
T2 |
10 |
|
T10 |
8 |
|
T12 |
50 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50791 |
1 |
|
|
T1 |
15 |
|
T2 |
51 |
|
T4 |
74 |
auto[1] |
2160 |
1 |
|
|
T12 |
25 |
|
T18 |
17 |
|
T20 |
6 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52169 |
1 |
|
|
T1 |
15 |
|
T2 |
51 |
|
T4 |
74 |
auto[1] |
782 |
1 |
|
|
T35 |
18 |
|
T52 |
5 |
|
T53 |
12 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52157 |
1 |
|
|
T1 |
15 |
|
T2 |
51 |
|
T4 |
74 |
auto[1] |
794 |
1 |
|
|
T35 |
19 |
|
T52 |
13 |
|
T53 |
9 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52185 |
1 |
|
|
T1 |
15 |
|
T2 |
51 |
|
T4 |
74 |
auto[1] |
766 |
1 |
|
|
T35 |
15 |
|
T52 |
12 |
|
T53 |
17 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50178 |
1 |
|
|
T2 |
51 |
|
T4 |
74 |
|
T10 |
99 |
auto[1] |
2773 |
1 |
|
|
T1 |
15 |
|
T12 |
82 |
|
T15 |
12 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49228 |
1 |
|
|
T1 |
15 |
|
T2 |
51 |
|
T4 |
74 |
auto[1] |
3723 |
1 |
|
|
T31 |
89 |
|
T42 |
83 |
|
T45 |
84 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51196 |
1 |
|
|
T1 |
14 |
|
T2 |
51 |
|
T4 |
68 |
auto[1] |
1755 |
1 |
|
|
T1 |
1 |
|
T4 |
6 |
|
T12 |
41 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51157 |
1 |
|
|
T1 |
15 |
|
T2 |
51 |
|
T4 |
67 |
auto[1] |
1794 |
1 |
|
|
T4 |
7 |
|
T12 |
43 |
|
T13 |
6 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51230 |
1 |
|
|
T1 |
15 |
|
T2 |
51 |
|
T4 |
66 |
auto[1] |
1721 |
1 |
|
|
T4 |
8 |
|
T12 |
46 |
|
T13 |
2 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51132 |
1 |
|
|
T1 |
15 |
|
T2 |
47 |
|
T4 |
74 |
auto[1] |
1819 |
1 |
|
|
T2 |
4 |
|
T10 |
6 |
|
T12 |
48 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47264 |
1 |
|
|
T1 |
15 |
|
T2 |
47 |
|
T4 |
74 |
auto[1] |
5687 |
1 |
|
|
T2 |
4 |
|
T10 |
14 |
|
T12 |
47 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49189 |
1 |
|
|
T1 |
15 |
|
T2 |
51 |
|
T4 |
74 |
auto[1] |
3762 |
1 |
|
|
T11 |
79 |
|
T50 |
77 |
|
T51 |
78 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52951 |
1 |
|
|
T1 |
15 |
|
T2 |
51 |
|
T4 |
74 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51078 |
1 |
|
|
T1 |
15 |
|
T2 |
49 |
|
T4 |
74 |
auto[1] |
1873 |
1 |
|
|
T2 |
2 |
|
T10 |
14 |
|
T12 |
37 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51125 |
1 |
|
|
T1 |
15 |
|
T2 |
44 |
|
T4 |
74 |
auto[1] |
1826 |
1 |
|
|
T2 |
7 |
|
T10 |
13 |
|
T12 |
47 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51053 |
1 |
|
|
T1 |
15 |
|
T2 |
43 |
|
T4 |
74 |
auto[1] |
1898 |
1 |
|
|
T2 |
8 |
|
T10 |
11 |
|
T12 |
47 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
46499 |
1 |
|
|
T2 |
51 |
|
T4 |
74 |
|
T10 |
99 |
auto[0] |
no_err_inj |
3679 |
1 |
|
|
T5 |
9 |
|
T12 |
44 |
|
T19 |
9 |
auto[1] |
err_inj |
1431 |
1 |
|
|
T1 |
6 |
|
T12 |
40 |
|
T15 |
6 |
auto[1] |
no_err_inj |
1342 |
1 |
|
|
T1 |
9 |
|
T12 |
42 |
|
T15 |
6 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48547 |
1 |
|
|
T2 |
51 |
|
T4 |
67 |
|
T10 |
99 |
auto[0] |
auto[1] |
1631 |
1 |
|
|
T4 |
7 |
|
T12 |
41 |
|
T13 |
6 |
auto[1] |
auto[0] |
2610 |
1 |
|
|
T1 |
15 |
|
T12 |
80 |
|
T15 |
12 |
auto[1] |
auto[1] |
163 |
1 |
|
|
T12 |
2 |
|
T63 |
2 |
|
T84 |
4 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48615 |
1 |
|
|
T2 |
51 |
|
T4 |
68 |
|
T10 |
99 |
auto[0] |
auto[1] |
1563 |
1 |
|
|
T4 |
6 |
|
T12 |
36 |
|
T13 |
7 |
auto[1] |
auto[0] |
2634 |
1 |
|
|
T1 |
13 |
|
T12 |
79 |
|
T15 |
11 |
auto[1] |
auto[1] |
139 |
1 |
|
|
T1 |
2 |
|
T12 |
3 |
|
T15 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48610 |
1 |
|
|
T2 |
51 |
|
T4 |
66 |
|
T10 |
99 |
auto[0] |
auto[1] |
1568 |
1 |
|
|
T4 |
8 |
|
T12 |
38 |
|
T13 |
2 |
auto[1] |
auto[0] |
2620 |
1 |
|
|
T1 |
15 |
|
T12 |
74 |
|
T15 |
11 |
auto[1] |
auto[1] |
153 |
1 |
|
|
T12 |
8 |
|
T15 |
1 |
|
T63 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48626 |
1 |
|
|
T2 |
51 |
|
T4 |
66 |
|
T10 |
99 |
auto[0] |
auto[1] |
1552 |
1 |
|
|
T4 |
8 |
|
T12 |
32 |
|
T13 |
5 |
auto[1] |
auto[0] |
2601 |
1 |
|
|
T1 |
14 |
|
T12 |
78 |
|
T15 |
10 |
auto[1] |
auto[1] |
172 |
1 |
|
|
T1 |
1 |
|
T12 |
4 |
|
T15 |
2 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48571 |
1 |
|
|
T2 |
51 |
|
T4 |
65 |
|
T10 |
99 |
auto[0] |
auto[1] |
1607 |
1 |
|
|
T4 |
9 |
|
T12 |
46 |
|
T13 |
9 |
auto[1] |
auto[0] |
2607 |
1 |
|
|
T1 |
15 |
|
T12 |
77 |
|
T15 |
12 |
auto[1] |
auto[1] |
166 |
1 |
|
|
T12 |
5 |
|
T84 |
1 |
|
T209 |
2 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48584 |
1 |
|
|
T2 |
51 |
|
T4 |
67 |
|
T10 |
99 |
auto[0] |
auto[1] |
1594 |
1 |
|
|
T4 |
7 |
|
T12 |
40 |
|
T13 |
4 |
auto[1] |
auto[0] |
2616 |
1 |
|
|
T1 |
14 |
|
T12 |
81 |
|
T15 |
11 |
auto[1] |
auto[1] |
157 |
1 |
|
|
T1 |
1 |
|
T12 |
1 |
|
T15 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36016 |
1 |
|
|
T4 |
74 |
|
T10 |
81 |
|
T11 |
79 |
auto[0] |
auto[1] |
1147 |
1 |
|
|
T10 |
18 |
|
T12 |
25 |
|
T15 |
9 |
auto[1] |
auto[0] |
15059 |
1 |
|
|
T1 |
15 |
|
T2 |
41 |
|
T5 |
9 |
auto[1] |
auto[1] |
729 |
1 |
|
|
T2 |
10 |
|
T12 |
9 |
|
T55 |
13 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36000 |
1 |
|
|
T4 |
74 |
|
T10 |
84 |
|
T11 |
79 |
auto[0] |
auto[1] |
1163 |
1 |
|
|
T10 |
15 |
|
T12 |
25 |
|
T15 |
10 |
auto[1] |
auto[0] |
15065 |
1 |
|
|
T1 |
15 |
|
T2 |
45 |
|
T5 |
9 |
auto[1] |
auto[1] |
723 |
1 |
|
|
T2 |
6 |
|
T12 |
17 |
|
T55 |
12 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35849 |
1 |
|
|
T4 |
74 |
|
T10 |
99 |
|
T11 |
79 |
auto[0] |
auto[1] |
1314 |
1 |
|
|
T12 |
7 |
|
T18 |
17 |
|
T15 |
17 |
auto[1] |
auto[0] |
14942 |
1 |
|
|
T1 |
15 |
|
T2 |
51 |
|
T5 |
9 |
auto[1] |
auto[1] |
846 |
1 |
|
|
T12 |
18 |
|
T20 |
6 |
|
T22 |
20 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35950 |
1 |
|
|
T4 |
74 |
|
T10 |
91 |
|
T11 |
79 |
auto[0] |
auto[1] |
1213 |
1 |
|
|
T10 |
8 |
|
T12 |
38 |
|
T15 |
18 |
auto[1] |
auto[0] |
15088 |
1 |
|
|
T1 |
15 |
|
T2 |
41 |
|
T5 |
9 |
auto[1] |
auto[1] |
700 |
1 |
|
|
T2 |
10 |
|
T12 |
12 |
|
T55 |
8 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32156 |
1 |
|
|
T4 |
74 |
|
T10 |
85 |
|
T11 |
79 |
auto[0] |
auto[1] |
5007 |
1 |
|
|
T10 |
14 |
|
T12 |
36 |
|
T14 |
53 |
auto[1] |
auto[0] |
15108 |
1 |
|
|
T1 |
15 |
|
T2 |
47 |
|
T5 |
9 |
auto[1] |
auto[1] |
680 |
1 |
|
|
T2 |
4 |
|
T12 |
11 |
|
T55 |
15 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36159 |
1 |
|
|
T4 |
67 |
|
T10 |
99 |
|
T11 |
79 |
auto[0] |
auto[1] |
1004 |
1 |
|
|
T4 |
7 |
|
T12 |
1 |
|
T13 |
6 |
auto[1] |
auto[0] |
14998 |
1 |
|
|
T1 |
15 |
|
T2 |
51 |
|
T5 |
9 |
auto[1] |
auto[1] |
790 |
1 |
|
|
T12 |
42 |
|
T21 |
5 |
|
T55 |
18 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36252 |
1 |
|
|
T4 |
68 |
|
T10 |
99 |
|
T11 |
79 |
auto[0] |
auto[1] |
911 |
1 |
|
|
T4 |
6 |
|
T12 |
6 |
|
T13 |
7 |
auto[1] |
auto[0] |
14944 |
1 |
|
|
T1 |
14 |
|
T2 |
51 |
|
T5 |
9 |
auto[1] |
auto[1] |
844 |
1 |
|
|
T1 |
1 |
|
T12 |
35 |
|
T21 |
4 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36257 |
1 |
|
|
T4 |
68 |
|
T10 |
99 |
|
T11 |
79 |
auto[0] |
auto[1] |
906 |
1 |
|
|
T4 |
6 |
|
T12 |
1 |
|
T13 |
7 |
auto[1] |
auto[0] |
14992 |
1 |
|
|
T1 |
13 |
|
T2 |
51 |
|
T5 |
9 |
auto[1] |
auto[1] |
796 |
1 |
|
|
T1 |
2 |
|
T12 |
38 |
|
T15 |
1 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36223 |
1 |
|
|
T4 |
64 |
|
T10 |
99 |
|
T11 |
79 |
auto[0] |
auto[1] |
940 |
1 |
|
|
T4 |
10 |
|
T12 |
2 |
|
T13 |
10 |
auto[1] |
auto[0] |
15027 |
1 |
|
|
T1 |
15 |
|
T2 |
51 |
|
T5 |
9 |
auto[1] |
auto[1] |
761 |
1 |
|
|
T12 |
38 |
|
T15 |
1 |
|
T21 |
4 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36201 |
1 |
|
|
T4 |
66 |
|
T10 |
99 |
|
T11 |
79 |
auto[0] |
auto[1] |
962 |
1 |
|
|
T4 |
8 |
|
T12 |
2 |
|
T13 |
5 |
auto[1] |
auto[0] |
15026 |
1 |
|
|
T1 |
14 |
|
T2 |
51 |
|
T5 |
9 |
auto[1] |
auto[1] |
762 |
1 |
|
|
T1 |
1 |
|
T12 |
34 |
|
T15 |
2 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36250 |
1 |
|
|
T4 |
67 |
|
T10 |
99 |
|
T11 |
79 |
auto[0] |
auto[1] |
913 |
1 |
|
|
T4 |
7 |
|
T13 |
4 |
|
T30 |
8 |
auto[1] |
auto[0] |
14950 |
1 |
|
|
T1 |
14 |
|
T2 |
51 |
|
T5 |
9 |
auto[1] |
auto[1] |
838 |
1 |
|
|
T1 |
1 |
|
T12 |
41 |
|
T15 |
1 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35956 |
1 |
|
|
T4 |
74 |
|
T10 |
88 |
|
T11 |
79 |
auto[0] |
auto[1] |
1207 |
1 |
|
|
T10 |
11 |
|
T12 |
39 |
|
T15 |
10 |
auto[1] |
auto[0] |
15097 |
1 |
|
|
T1 |
15 |
|
T2 |
43 |
|
T5 |
9 |
auto[1] |
auto[1] |
691 |
1 |
|
|
T2 |
8 |
|
T12 |
8 |
|
T55 |
14 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35999 |
1 |
|
|
T4 |
74 |
|
T10 |
86 |
|
T11 |
79 |
auto[0] |
auto[1] |
1164 |
1 |
|
|
T10 |
13 |
|
T12 |
36 |
|
T15 |
6 |
auto[1] |
auto[0] |
15126 |
1 |
|
|
T1 |
15 |
|
T2 |
44 |
|
T5 |
9 |
auto[1] |
auto[1] |
662 |
1 |
|
|
T2 |
7 |
|
T12 |
11 |
|
T55 |
9 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35571 |
1 |
|
|
T4 |
74 |
|
T10 |
99 |
|
T11 |
79 |
auto[0] |
auto[1] |
1592 |
1 |
|
|
T12 |
42 |
|
T63 |
15 |
|
T84 |
13 |
auto[1] |
auto[0] |
14607 |
1 |
|
|
T2 |
51 |
|
T5 |
9 |
|
T12 |
468 |
auto[1] |
auto[1] |
1181 |
1 |
|
|
T1 |
15 |
|
T12 |
40 |
|
T15 |
12 |