Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103973502

1

T1

56899

T2

130717

T3

1321

auto[1]

1343821

1

T1

196

T2

792

T4

3168

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103970928

1

T1

56801

T2

131311

T3

1321

auto[1]

1346395

1

T1

294

T2

198

T4

2079

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7344762	1			T1	3516		T2	4533		T3	93
auto[IdleSt]	21581927	1			T1	15298		T2	64140		T3	68
auto[ClkMuxSt]	36154	1			T1	9		T2	51		T3	1
auto[CntIncrSt]	35839	1			T1	9		T2	51		T3	1
auto[CntProgSt]	1697533	1			T1	95		T2	4827		T3	50
auto[TransCheckSt]	28248	1			T1	9		T2	34		T3	1
auto[TokenHashSt]	43552740	1			T1	210		T2	1788		T3	12
auto[FlashRmaSt]	28824	1			T1	15		T2	26		T10	25
auto[TokenCheck0St]	13132	1			T1	9		T2	16		T10	23
auto[TokenCheck1St]	9772	1			T1	9		T2	10		T10	10
auto[TransProgSt]	375591	1			T1	109		T2	1540		T10	1012
auto[PostTransSt]	12215692	1			T1	20832		T2	49322		T3	1095
auto[ScrapSt]	135252	1			T15	26		T21	9		T31	6
auto[EscalateSt]	6610990	1			T1	8946		T2	5171		T4	7320
auto[InvalidSt]	11649071	1			T1	8027		T4	7394		T12	777603

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1796	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11649071	1			T1	8027		T4	7394		T12	777603
EscalateSt	6610990	1			T1	8946		T2	5171		T4	7320
ScrapSt	135252	1			T15	26		T21	9		T31	6
PostTransSt	12215692	1			T1	20832		T2	49322		T3	1095
TransProgSt	375591	1			T1	109		T2	1540		T10	1012
TokenCheck1St	9772	1			T1	9		T2	10		T10	10
TokenCheck0St	13132	1			T1	9		T2	16		T10	23
FlashRmaSt	28824	1			T1	15		T2	26		T10	25
TokenHashSt	43552740	1			T1	210		T2	1788		T3	12
TransCheckSt	28248	1			T1	9		T2	34		T3	1
CntProgSt	1697533	1			T1	95		T2	4827		T3	50
CntIncrSt	35839	1			T1	9		T2	51		T3	1
ClkMuxSt	36154	1			T1	9		T2	51		T3	1
IdleSt	21581927	1			T1	15298		T2	64140		T3	68
ResetSt	7344762	1			T1	3516		T2	4533		T3	93
arcs[ResetSt=>IdleSt]	53442	1			T1	15		T2	52		T3	1
arcs[IdleSt=>ScrapSt]	300	1			T15	1		T21	1		T31	2
arcs[IdleSt=>ClkMuxSt]	35899	1			T1	9		T2	51		T3	1
arcs[ClkMuxSt=>CntIncrSt]	35839	1			T1	9		T2	51		T3	1
arcs[CntIncrSt=>PostTransSt]	1827	1			T2	7		T10	13		T12	47
arcs[CntIncrSt=>CntProgSt]	33955	1			T1	9		T2	44		T3	1
arcs[CntProgSt=>PostTransSt]	4746	1			T2	10		T10	18		T12	59
arcs[CntProgSt=>TransCheckSt]	28248	1			T1	9		T2	34		T3	1
arcs[TransCheckSt=>PostTransSt]	3784	1			T2	8		T10	11		T11	43
arcs[TransCheckSt=>TokenHashSt]	24323	1			T1	9		T2	26		T3	1
arcs[TokenHashSt=>PostTransSt]	10383	1			T2	10		T3	1		T10	34
arcs[TokenHashSt=>FlashRmaSt]	13230	1			T1	9		T2	16		T10	23
arcs[FlashRmaSt=>TokenCheck0St]	13132	1			T1	9		T2	16		T10	23
arcs[TokenCheck0St=>PostTransSt]	3330	1			T2	6		T10	13		T11	13
arcs[TokenCheck0St=>TokenCheck1St]	9772	1			T1	9		T2	10		T10	10
arcs[TokenCheck1St=>PostTransSt]	659	1			T10	2		T11	13		T12	2
arcs[TransProgSt=>PostTransSt]	8223	1			T1	9		T2	10		T10	8
arcs[IdleSt=>EscalateSt]	220	1			T31	6		T42	4		T45	7
arcs[ClkMuxSt=>EscalateSt]	60	1			T31	1		T42	2		T43	3
arcs[CntIncrSt=>EscalateSt]	57	1			T42	3		T43	1		T44	3
arcs[CntProgSt=>EscalateSt]	961	1			T31	24		T42	21		T45	37
arcs[TransCheckSt=>EscalateSt]	141	1			T43	1		T48	6		T44	3
arcs[TokenHashSt=>EscalateSt]	710	1			T31	17		T42	14		T45	8
arcs[FlashRmaSt=>EscalateSt]	98	1			T31	5		T42	3		T45	1
arcs[TokenCheck0St=>EscalateSt]	30	1			T31	1		T42	1		T48	1
arcs[TokenCheck1St=>EscalateSt]	156	1			T31	5		T42	3		T45	7
arcs[TransProgSt=>EscalateSt]	734	1			T31	22		T42	22		T45	18
arcs[PostTransSt=>EscalateSt]	5030	1			T2	10		T10	18		T12	59
arcs[InvalidSt=>EscalateSt]	13007	1			T1	5		T4	53		T12	293

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7344597	1			T1	3516		T2	4533		T3	93
auto[0]	auto[IdleSt]	21581784	1			T1	15298		T2	64140		T3	68
auto[0]	auto[ClkMuxSt]	36112	1			T1	9		T2	51		T3	1
auto[0]	auto[CntIncrSt]	35802	1			T1	9		T2	51		T3	1
auto[0]	auto[CntProgSt]	1696889	1			T1	95		T2	4827		T3	50
auto[0]	auto[TransCheckSt]	28152	1			T1	9		T2	34		T3	1
auto[0]	auto[TokenHashSt]	43552269	1			T1	210		T2	1788		T3	12
auto[0]	auto[FlashRmaSt]	28760	1			T1	15		T2	26		T10	25
auto[0]	auto[TokenCheck0St]	13111	1			T1	9		T2	16		T10	23
auto[0]	auto[TokenCheck1St]	9675	1			T1	9		T2	10		T10	10
auto[0]	auto[TransProgSt]	375123	1			T1	109		T2	1540		T10	1012
auto[0]	auto[PostTransSt]	12213098	1			T1	20832		T2	49314		T3	1095
auto[0]	auto[ScrapSt]	135211	1			T15	26		T21	9		T31	5
auto[0]	auto[EscalateSt]	5278566	1			T1	8752		T2	4387		T4	4184
auto[0]	auto[InvalidSt]	11642557	1			T1	8025		T4	7362		T12	777472
auto[1]	auto[ResetSt]	165	1			T31	4		T42	4		T45	4
auto[1]	auto[IdleSt]	143	1			T31	4		T42	4		T45	5
auto[1]	auto[ClkMuxSt]	42	1			T31	1		T42	2		T43	1
auto[1]	auto[CntIncrSt]	37	1			T42	2		T43	1		T44	3
auto[1]	auto[CntProgSt]	644	1			T31	13		T42	14		T45	23
auto[1]	auto[TransCheckSt]	96	1			T48	4		T44	2		T208	2
auto[1]	auto[TokenHashSt]	471	1			T31	13		T42	9		T45	4
auto[1]	auto[FlashRmaSt]	64	1			T31	2		T42	2		T45	1
auto[1]	auto[TokenCheck0St]	21	1			T31	1		T48	1		T44	1
auto[1]	auto[TokenCheck1St]	97	1			T31	4		T42	1		T45	5
auto[1]	auto[TransProgSt]	468	1			T31	15		T42	15		T45	13
auto[1]	auto[PostTransSt]	2594	1			T2	8		T10	10		T12	30
auto[1]	auto[ScrapSt]	41	1			T31	1		T42	2		T43	2
auto[1]	auto[EscalateSt]	1332424	1			T1	194		T2	784		T4	3136
auto[1]	auto[InvalidSt]	6514	1			T1	2		T4	32		T12	131

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7344582	1			T1	3516		T2	4533		T3	93
auto[0]	auto[IdleSt]	21581776	1			T1	15298		T2	64140		T3	68
auto[0]	auto[ClkMuxSt]	36119	1			T1	9		T2	51		T3	1
auto[0]	auto[CntIncrSt]	35799	1			T1	9		T2	51		T3	1
auto[0]	auto[CntProgSt]	1696909	1			T1	95		T2	4827		T3	50
auto[0]	auto[TransCheckSt]	28150	1			T1	9		T2	34		T3	1
auto[0]	auto[TokenHashSt]	43552266	1			T1	210		T2	1788		T3	12
auto[0]	auto[FlashRmaSt]	28756	1			T1	15		T2	26		T10	25
auto[0]	auto[TokenCheck0St]	13111	1			T1	9		T2	16		T10	23
auto[0]	auto[TokenCheck1St]	9670	1			T1	9		T2	10		T10	10
auto[0]	auto[TransProgSt]	375078	1			T1	109		T2	1540		T10	1012
auto[0]	auto[PostTransSt]	12213172	1			T1	20832		T2	49320		T3	1095
auto[0]	auto[ScrapSt]	135210	1			T15	26		T21	9		T31	4
auto[0]	auto[EscalateSt]	5275956	1			T1	8655		T2	4975		T4	5262
auto[0]	auto[InvalidSt]	11642578	1			T1	8024		T4	7373		T12	777441
auto[1]	auto[ResetSt]	180	1			T31	4		T42	4		T45	3
auto[1]	auto[IdleSt]	151	1			T31	3		T42	4		T45	4
auto[1]	auto[ClkMuxSt]	35	1			T31	1		T43	2		T166	1
auto[1]	auto[CntIncrSt]	40	1			T42	1		T43	1		T44	1
auto[1]	auto[CntProgSt]	624	1			T31	15		T42	10		T45	25
auto[1]	auto[TransCheckSt]	98	1			T43	1		T48	4		T44	1
auto[1]	auto[TokenHashSt]	474	1			T31	10		T42	11		T45	6
auto[1]	auto[FlashRmaSt]	68	1			T31	4		T42	2		T45	1
auto[1]	auto[TokenCheck0St]	21	1			T31	1		T42	1		T48	1
auto[1]	auto[TokenCheck1St]	102	1			T31	4		T42	2		T45	3
auto[1]	auto[TransProgSt]	513	1			T31	14		T42	15		T45	11
auto[1]	auto[PostTransSt]	2520	1			T2	2		T10	8		T12	29
auto[1]	auto[ScrapSt]	42	1			T31	2		T42	1		T48	2
auto[1]	auto[EscalateSt]	1335034	1			T1	291		T2	196		T4	2058
auto[1]	auto[InvalidSt]	6493	1			T1	3		T4	21		T12	162