Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
60066 |
1 |
|
|
T1 |
59 |
|
T2 |
93 |
|
T3 |
10 |
auto[1] |
2278 |
1 |
|
|
T1 |
10 |
|
T11 |
10 |
|
T5 |
14 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
61545 |
1 |
|
|
T1 |
69 |
|
T2 |
93 |
|
T3 |
10 |
auto[1] |
799 |
1 |
|
|
T40 |
17 |
|
T56 |
20 |
|
T57 |
12 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59949 |
1 |
|
|
T1 |
69 |
|
T2 |
93 |
|
T3 |
10 |
auto[1] |
2395 |
1 |
|
|
T5 |
11 |
|
T20 |
6 |
|
T21 |
1 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59958 |
1 |
|
|
T1 |
69 |
|
T2 |
93 |
|
T3 |
10 |
auto[1] |
2386 |
1 |
|
|
T5 |
15 |
|
T13 |
1 |
|
T20 |
9 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
60034 |
1 |
|
|
T1 |
69 |
|
T2 |
93 |
|
T3 |
9 |
auto[1] |
2310 |
1 |
|
|
T3 |
1 |
|
T5 |
13 |
|
T13 |
1 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
56459 |
1 |
|
|
T1 |
69 |
|
T2 |
93 |
|
T3 |
9 |
no_err_inj |
5885 |
1 |
|
|
T3 |
1 |
|
T5 |
23 |
|
T13 |
8 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
60101 |
1 |
|
|
T1 |
64 |
|
T2 |
93 |
|
T3 |
10 |
auto[1] |
2243 |
1 |
|
|
T1 |
5 |
|
T11 |
11 |
|
T5 |
12 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
61563 |
1 |
|
|
T1 |
69 |
|
T2 |
93 |
|
T3 |
10 |
auto[1] |
781 |
1 |
|
|
T40 |
19 |
|
T56 |
19 |
|
T57 |
11 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
42194 |
1 |
|
|
T2 |
93 |
|
T3 |
10 |
|
T10 |
13 |
auto[1] |
20150 |
1 |
|
|
T1 |
69 |
|
T5 |
130 |
|
T18 |
233 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
60056 |
1 |
|
|
T1 |
69 |
|
T2 |
93 |
|
T3 |
10 |
auto[1] |
2288 |
1 |
|
|
T5 |
16 |
|
T20 |
6 |
|
T45 |
8 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59976 |
1 |
|
|
T1 |
69 |
|
T2 |
93 |
|
T3 |
7 |
auto[1] |
2368 |
1 |
|
|
T3 |
3 |
|
T5 |
8 |
|
T20 |
12 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
60076 |
1 |
|
|
T1 |
69 |
|
T2 |
93 |
|
T3 |
9 |
auto[1] |
2268 |
1 |
|
|
T3 |
1 |
|
T5 |
10 |
|
T20 |
8 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
60144 |
1 |
|
|
T1 |
61 |
|
T2 |
93 |
|
T3 |
10 |
auto[1] |
2200 |
1 |
|
|
T1 |
8 |
|
T11 |
10 |
|
T5 |
18 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59755 |
1 |
|
|
T1 |
69 |
|
T2 |
93 |
|
T3 |
10 |
auto[1] |
2589 |
1 |
|
|
T10 |
13 |
|
T5 |
28 |
|
T53 |
5 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
61551 |
1 |
|
|
T1 |
69 |
|
T2 |
93 |
|
T3 |
10 |
auto[1] |
793 |
1 |
|
|
T40 |
13 |
|
T56 |
12 |
|
T57 |
20 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
61515 |
1 |
|
|
T1 |
69 |
|
T2 |
93 |
|
T3 |
10 |
auto[1] |
829 |
1 |
|
|
T40 |
26 |
|
T56 |
19 |
|
T57 |
17 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
61552 |
1 |
|
|
T1 |
69 |
|
T2 |
93 |
|
T3 |
10 |
auto[1] |
792 |
1 |
|
|
T40 |
19 |
|
T56 |
15 |
|
T57 |
13 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58880 |
1 |
|
|
T1 |
69 |
|
T2 |
93 |
|
T10 |
13 |
auto[1] |
3464 |
1 |
|
|
T3 |
10 |
|
T5 |
32 |
|
T13 |
13 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58666 |
1 |
|
|
T1 |
69 |
|
T3 |
10 |
|
T10 |
13 |
auto[1] |
3678 |
1 |
|
|
T2 |
93 |
|
T12 |
77 |
|
T15 |
71 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59951 |
1 |
|
|
T1 |
69 |
|
T2 |
93 |
|
T3 |
10 |
auto[1] |
2393 |
1 |
|
|
T5 |
10 |
|
T13 |
3 |
|
T20 |
10 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59983 |
1 |
|
|
T1 |
69 |
|
T2 |
93 |
|
T3 |
8 |
auto[1] |
2361 |
1 |
|
|
T3 |
2 |
|
T5 |
19 |
|
T20 |
14 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
60062 |
1 |
|
|
T1 |
69 |
|
T2 |
93 |
|
T3 |
8 |
auto[1] |
2282 |
1 |
|
|
T3 |
2 |
|
T5 |
11 |
|
T20 |
11 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
60165 |
1 |
|
|
T1 |
62 |
|
T2 |
93 |
|
T3 |
10 |
auto[1] |
2179 |
1 |
|
|
T1 |
7 |
|
T11 |
5 |
|
T5 |
8 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56338 |
1 |
|
|
T1 |
61 |
|
T2 |
93 |
|
T3 |
10 |
auto[1] |
6006 |
1 |
|
|
T1 |
8 |
|
T11 |
2 |
|
T5 |
12 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
58606 |
1 |
|
|
T1 |
69 |
|
T2 |
93 |
|
T3 |
10 |
auto[1] |
3738 |
1 |
|
|
T36 |
88 |
|
T54 |
50 |
|
T55 |
65 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
62344 |
1 |
|
|
T1 |
69 |
|
T2 |
93 |
|
T3 |
10 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
60238 |
1 |
|
|
T1 |
59 |
|
T2 |
93 |
|
T3 |
10 |
auto[1] |
2106 |
1 |
|
|
T1 |
10 |
|
T11 |
5 |
|
T5 |
7 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
60144 |
1 |
|
|
T1 |
60 |
|
T2 |
93 |
|
T3 |
10 |
auto[1] |
2200 |
1 |
|
|
T1 |
9 |
|
T11 |
5 |
|
T5 |
8 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
60147 |
1 |
|
|
T1 |
57 |
|
T2 |
93 |
|
T3 |
10 |
auto[1] |
2197 |
1 |
|
|
T1 |
12 |
|
T11 |
8 |
|
T5 |
12 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
54742 |
1 |
|
|
T1 |
69 |
|
T2 |
93 |
|
T10 |
13 |
auto[0] |
no_err_inj |
4138 |
1 |
|
|
T5 |
9 |
|
T18 |
46 |
|
T51 |
5 |
auto[1] |
err_inj |
1717 |
1 |
|
|
T3 |
9 |
|
T5 |
18 |
|
T13 |
5 |
auto[1] |
no_err_inj |
1747 |
1 |
|
|
T3 |
1 |
|
T5 |
14 |
|
T13 |
8 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
56701 |
1 |
|
|
T1 |
69 |
|
T2 |
93 |
|
T10 |
13 |
auto[0] |
auto[1] |
2179 |
1 |
|
|
T5 |
16 |
|
T20 |
14 |
|
T45 |
5 |
auto[1] |
auto[0] |
3282 |
1 |
|
|
T3 |
8 |
|
T5 |
29 |
|
T13 |
13 |
auto[1] |
auto[1] |
182 |
1 |
|
|
T3 |
2 |
|
T5 |
3 |
|
T21 |
2 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
56715 |
1 |
|
|
T1 |
69 |
|
T2 |
93 |
|
T10 |
13 |
auto[0] |
auto[1] |
2165 |
1 |
|
|
T5 |
7 |
|
T20 |
12 |
|
T45 |
8 |
auto[1] |
auto[0] |
3261 |
1 |
|
|
T3 |
7 |
|
T5 |
31 |
|
T13 |
13 |
auto[1] |
auto[1] |
203 |
1 |
|
|
T3 |
3 |
|
T5 |
1 |
|
T21 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
56801 |
1 |
|
|
T1 |
69 |
|
T2 |
93 |
|
T10 |
13 |
auto[0] |
auto[1] |
2079 |
1 |
|
|
T5 |
9 |
|
T20 |
11 |
|
T45 |
5 |
auto[1] |
auto[0] |
3261 |
1 |
|
|
T3 |
8 |
|
T5 |
30 |
|
T13 |
13 |
auto[1] |
auto[1] |
203 |
1 |
|
|
T3 |
2 |
|
T5 |
2 |
|
T21 |
2 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
56682 |
1 |
|
|
T1 |
69 |
|
T2 |
93 |
|
T10 |
13 |
auto[0] |
auto[1] |
2198 |
1 |
|
|
T5 |
15 |
|
T20 |
9 |
|
T45 |
7 |
auto[1] |
auto[0] |
3276 |
1 |
|
|
T3 |
10 |
|
T5 |
32 |
|
T13 |
12 |
auto[1] |
auto[1] |
188 |
1 |
|
|
T13 |
1 |
|
T18 |
3 |
|
T23 |
2 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
56760 |
1 |
|
|
T1 |
69 |
|
T2 |
93 |
|
T10 |
13 |
auto[0] |
auto[1] |
2120 |
1 |
|
|
T5 |
11 |
|
T20 |
11 |
|
T45 |
10 |
auto[1] |
auto[0] |
3274 |
1 |
|
|
T3 |
9 |
|
T5 |
30 |
|
T13 |
12 |
auto[1] |
auto[1] |
190 |
1 |
|
|
T3 |
1 |
|
T5 |
2 |
|
T13 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
56665 |
1 |
|
|
T1 |
69 |
|
T2 |
93 |
|
T10 |
13 |
auto[0] |
auto[1] |
2215 |
1 |
|
|
T5 |
8 |
|
T20 |
6 |
|
T45 |
2 |
auto[1] |
auto[0] |
3284 |
1 |
|
|
T3 |
10 |
|
T5 |
29 |
|
T13 |
13 |
auto[1] |
auto[1] |
180 |
1 |
|
|
T5 |
3 |
|
T21 |
1 |
|
T18 |
3 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
40983 |
1 |
|
|
T2 |
93 |
|
T3 |
10 |
|
T10 |
13 |
auto[0] |
auto[1] |
1211 |
1 |
|
|
T11 |
10 |
|
T14 |
10 |
|
T32 |
24 |
auto[1] |
auto[0] |
19083 |
1 |
|
|
T1 |
59 |
|
T5 |
116 |
|
T18 |
220 |
auto[1] |
auto[1] |
1067 |
1 |
|
|
T1 |
10 |
|
T5 |
14 |
|
T18 |
13 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
41004 |
1 |
|
|
T2 |
93 |
|
T3 |
10 |
|
T10 |
13 |
auto[0] |
auto[1] |
1190 |
1 |
|
|
T11 |
11 |
|
T14 |
7 |
|
T32 |
10 |
auto[1] |
auto[0] |
19097 |
1 |
|
|
T1 |
64 |
|
T5 |
118 |
|
T18 |
227 |
auto[1] |
auto[1] |
1053 |
1 |
|
|
T1 |
5 |
|
T5 |
12 |
|
T18 |
6 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
40805 |
1 |
|
|
T2 |
93 |
|
T3 |
10 |
|
T11 |
56 |
auto[0] |
auto[1] |
1389 |
1 |
|
|
T10 |
13 |
|
T5 |
28 |
|
T53 |
5 |
auto[1] |
auto[0] |
18950 |
1 |
|
|
T1 |
69 |
|
T5 |
130 |
|
T18 |
233 |
auto[1] |
auto[1] |
1200 |
1 |
|
|
T24 |
15 |
|
T32 |
36 |
|
T33 |
16 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
41027 |
1 |
|
|
T2 |
93 |
|
T3 |
10 |
|
T10 |
13 |
auto[0] |
auto[1] |
1167 |
1 |
|
|
T11 |
10 |
|
T14 |
7 |
|
T32 |
23 |
auto[1] |
auto[0] |
19117 |
1 |
|
|
T1 |
61 |
|
T5 |
112 |
|
T18 |
224 |
auto[1] |
auto[1] |
1033 |
1 |
|
|
T1 |
8 |
|
T5 |
18 |
|
T18 |
9 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37263 |
1 |
|
|
T2 |
93 |
|
T3 |
10 |
|
T10 |
13 |
auto[0] |
auto[1] |
4931 |
1 |
|
|
T11 |
2 |
|
T14 |
7 |
|
T16 |
81 |
auto[1] |
auto[0] |
19075 |
1 |
|
|
T1 |
61 |
|
T5 |
118 |
|
T18 |
225 |
auto[1] |
auto[1] |
1075 |
1 |
|
|
T1 |
8 |
|
T5 |
12 |
|
T18 |
8 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
40720 |
1 |
|
|
T2 |
93 |
|
T3 |
8 |
|
T10 |
13 |
auto[0] |
auto[1] |
1474 |
1 |
|
|
T3 |
2 |
|
T5 |
16 |
|
T20 |
14 |
auto[1] |
auto[0] |
19263 |
1 |
|
|
T1 |
69 |
|
T5 |
127 |
|
T18 |
226 |
auto[1] |
auto[1] |
887 |
1 |
|
|
T5 |
3 |
|
T18 |
7 |
|
T22 |
3 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
40689 |
1 |
|
|
T2 |
93 |
|
T3 |
10 |
|
T10 |
13 |
auto[0] |
auto[1] |
1505 |
1 |
|
|
T5 |
9 |
|
T13 |
3 |
|
T20 |
10 |
auto[1] |
auto[0] |
19262 |
1 |
|
|
T1 |
69 |
|
T5 |
129 |
|
T18 |
221 |
auto[1] |
auto[1] |
888 |
1 |
|
|
T5 |
1 |
|
T18 |
12 |
|
T22 |
6 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
40704 |
1 |
|
|
T2 |
93 |
|
T3 |
7 |
|
T10 |
13 |
auto[0] |
auto[1] |
1490 |
1 |
|
|
T3 |
3 |
|
T5 |
7 |
|
T20 |
12 |
auto[1] |
auto[0] |
19272 |
1 |
|
|
T1 |
69 |
|
T5 |
129 |
|
T18 |
223 |
auto[1] |
auto[1] |
878 |
1 |
|
|
T5 |
1 |
|
T18 |
10 |
|
T22 |
5 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
40730 |
1 |
|
|
T2 |
93 |
|
T3 |
10 |
|
T10 |
13 |
auto[0] |
auto[1] |
1464 |
1 |
|
|
T5 |
14 |
|
T20 |
6 |
|
T45 |
8 |
auto[1] |
auto[0] |
19326 |
1 |
|
|
T1 |
69 |
|
T5 |
128 |
|
T18 |
225 |
auto[1] |
auto[1] |
824 |
1 |
|
|
T5 |
2 |
|
T18 |
8 |
|
T22 |
8 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
40678 |
1 |
|
|
T2 |
93 |
|
T3 |
10 |
|
T10 |
13 |
auto[0] |
auto[1] |
1516 |
1 |
|
|
T5 |
15 |
|
T13 |
1 |
|
T20 |
9 |
auto[1] |
auto[0] |
19280 |
1 |
|
|
T1 |
69 |
|
T5 |
130 |
|
T18 |
218 |
auto[1] |
auto[1] |
870 |
1 |
|
|
T18 |
15 |
|
T22 |
8 |
|
T23 |
2 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
40712 |
1 |
|
|
T2 |
93 |
|
T3 |
10 |
|
T10 |
13 |
auto[0] |
auto[1] |
1482 |
1 |
|
|
T5 |
8 |
|
T20 |
6 |
|
T21 |
1 |
auto[1] |
auto[0] |
19237 |
1 |
|
|
T1 |
69 |
|
T5 |
127 |
|
T18 |
213 |
auto[1] |
auto[1] |
913 |
1 |
|
|
T5 |
3 |
|
T18 |
20 |
|
T22 |
10 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
40998 |
1 |
|
|
T2 |
93 |
|
T3 |
10 |
|
T10 |
13 |
auto[0] |
auto[1] |
1196 |
1 |
|
|
T11 |
8 |
|
T14 |
8 |
|
T32 |
21 |
auto[1] |
auto[0] |
19149 |
1 |
|
|
T1 |
57 |
|
T5 |
118 |
|
T18 |
225 |
auto[1] |
auto[1] |
1001 |
1 |
|
|
T1 |
12 |
|
T5 |
12 |
|
T18 |
8 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
41042 |
1 |
|
|
T2 |
93 |
|
T3 |
10 |
|
T10 |
13 |
auto[0] |
auto[1] |
1152 |
1 |
|
|
T11 |
5 |
|
T14 |
7 |
|
T32 |
19 |
auto[1] |
auto[0] |
19102 |
1 |
|
|
T1 |
60 |
|
T5 |
122 |
|
T18 |
227 |
auto[1] |
auto[1] |
1048 |
1 |
|
|
T1 |
9 |
|
T5 |
8 |
|
T18 |
6 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
40411 |
1 |
|
|
T2 |
93 |
|
T10 |
13 |
|
T11 |
56 |
auto[0] |
auto[1] |
1783 |
1 |
|
|
T3 |
10 |
|
T13 |
13 |
|
T21 |
11 |
auto[1] |
auto[0] |
18469 |
1 |
|
|
T1 |
69 |
|
T5 |
98 |
|
T18 |
207 |
auto[1] |
auto[1] |
1681 |
1 |
|
|
T5 |
32 |
|
T18 |
26 |
|
T23 |
15 |