Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

132994267

1

T1

139624

T2

29620

T3

3462

auto[1]

1607208

1

T1

495

T2

11377

T3

495

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

133005097

1

T1

139624

T2

26099

T3

3858

auto[1]

1596378

1

T1

495

T2

14898

T3

99

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	8325336	1			T1	6650		T2	8400		T3	1176
auto[IdleSt]	28810824	1			T1	68395		T2	9733		T3	1044
auto[ClkMuxSt]	40148	1			T1	69		T2	76		T3	1
auto[CntIncrSt]	39834	1			T1	69		T2	75		T3	1
auto[CntProgSt]	2195872	1			T1	112		T2	863		T3	20
auto[TransCheckSt]	31012	1			T1	52		T2	40		T3	1
auto[TokenHashSt]	55685439	1			T1	2813		T2	1591		T3	10
auto[FlashRmaSt]	31900	1			T1	30		T2	36		T3	1
auto[TokenCheck0St]	14601	1			T1	15		T2	28		T3	1
auto[TokenCheck1St]	10894	1			T1	12		T2	28		T3	1
auto[TransProgSt]	575506	1			T1	19		T2	98		T3	104
auto[PostTransSt]	17551289	1			T1	57517		T2	10		T3	189
auto[ScrapSt]	280642	1			T2	3		T5	840		T12	6
auto[EscalateSt]	8116965	1			T1	4366		T2	20016		T3	938
auto[InvalidSt]	12888765	1			T3	467		T5	62379		T13	334

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2448	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12888765	1			T3	467		T5	62379		T13	334
EscalateSt	8116965	1			T1	4366		T2	20016		T3	938
ScrapSt	280642	1			T2	3		T5	840		T12	6
PostTransSt	17551289	1			T1	57517		T2	10		T3	189
TransProgSt	575506	1			T1	19		T2	98		T3	104
TokenCheck1St	10894	1			T1	12		T2	28		T3	1
TokenCheck0St	14601	1			T1	15		T2	28		T3	1
FlashRmaSt	31900	1			T1	30		T2	36		T3	1
TokenHashSt	55685439	1			T1	2813		T2	1591		T3	10
TransCheckSt	31012	1			T1	52		T2	40		T3	1
CntProgSt	2195872	1			T1	112		T2	863		T3	20
CntIncrSt	39834	1			T1	69		T2	75		T3	1
ClkMuxSt	40148	1			T1	69		T2	76		T3	1
IdleSt	28810824	1			T1	68395		T2	9733		T3	1044
ResetSt	8325336	1			T1	6650		T2	8400		T3	1176
arcs[ResetSt=>IdleSt]	62547	1			T1	70		T2	89		T3	10
arcs[IdleSt=>ScrapSt]	307	1			T2	1		T5	1		T12	2
arcs[IdleSt=>ClkMuxSt]	39902	1			T1	69		T2	76		T3	1
arcs[ClkMuxSt=>CntIncrSt]	39834	1			T1	69		T2	75		T3	1
arcs[CntIncrSt=>PostTransSt]	2202	1			T1	9		T11	5		T5	8
arcs[CntIncrSt=>CntProgSt]	37585	1			T1	60		T2	73		T3	1
arcs[CntProgSt=>PostTransSt]	5628	1			T1	8		T10	13		T11	10
arcs[CntProgSt=>TransCheckSt]	31012	1			T1	52		T2	40		T3	1
arcs[TransCheckSt=>PostTransSt]	4064	1			T1	12		T11	8		T5	12
arcs[TransCheckSt=>TokenHashSt]	26779	1			T1	40		T2	39		T3	1
arcs[TokenHashSt=>PostTransSt]	11341	1			T1	25		T11	12		T5	27
arcs[TokenHashSt=>FlashRmaSt]	14698	1			T1	15		T2	28		T3	1
arcs[FlashRmaSt=>TokenCheck0St]	14601	1			T1	15		T2	28		T3	1
arcs[TokenCheck0St=>PostTransSt]	3679	1			T1	3		T11	11		T5	12
arcs[TokenCheck0St=>TokenCheck1St]	10894	1			T1	12		T2	28		T3	1
arcs[TokenCheck1St=>PostTransSt]	710	1			T1	1		T14	1		T19	5
arcs[TransProgSt=>PostTransSt]	9342	1			T1	11		T2	4		T3	1
arcs[IdleSt=>EscalateSt]	182	1			T2	11		T12	5		T48	8
arcs[ClkMuxSt=>EscalateSt]	68	1			T2	1		T15	3		T46	3
arcs[CntIncrSt=>EscalateSt]	47	1			T2	2		T12	1		T47	1
arcs[CntProgSt=>EscalateSt]	945	1			T2	33		T12	12		T15	28
arcs[TransCheckSt=>EscalateSt]	169	1			T2	1		T12	7		T46	9
arcs[TokenHashSt=>EscalateSt]	738	1			T2	11		T12	23		T15	5
arcs[FlashRmaSt=>EscalateSt]	97	1			T12	2		T15	2		T46	2
arcs[TokenCheck0St=>EscalateSt]	28	1			T12	1		T15	1		T46	1
arcs[TokenCheck1St=>EscalateSt]	139	1			T2	2		T15	2		T46	5
arcs[TransProgSt=>EscalateSt]	703	1			T2	22		T12	9		T15	22
arcs[PostTransSt=>EscalateSt]	5922	1			T1	10		T2	4		T10	13
arcs[InvalidSt=>EscalateSt]	17346	1			T3	6		T5	92		T13	5

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8325166	1			T1	6650		T2	8398		T3	1176
auto[0]	auto[IdleSt]	28810697	1			T1	68395		T2	9725		T3	1044
auto[0]	auto[ClkMuxSt]	40105	1			T1	69		T2	75		T3	1
auto[0]	auto[CntIncrSt]	39804	1			T1	69		T2	75		T3	1
auto[0]	auto[CntProgSt]	2195232	1			T1	112		T2	841		T3	20
auto[0]	auto[TransCheckSt]	30906	1			T1	52		T2	39		T3	1
auto[0]	auto[TokenHashSt]	55684956	1			T1	2813		T2	1585		T3	10
auto[0]	auto[FlashRmaSt]	31841	1			T1	30		T2	36		T3	1
auto[0]	auto[TokenCheck0St]	14586	1			T1	15		T2	28		T3	1
auto[0]	auto[TokenCheck1St]	10810	1			T1	12		T2	27		T3	1
auto[0]	auto[TransProgSt]	575038	1			T1	19		T2	90		T3	104
auto[0]	auto[PostTransSt]	17548230	1			T1	57512		T2	7		T3	189
auto[0]	auto[ScrapSt]	280599	1			T2	2		T5	840		T12	4
auto[0]	auto[EscalateSt]	6523826	1			T1	3876		T2	8692		T3	448
auto[0]	auto[InvalidSt]	12880023	1			T3	462		T5	62328		T13	331
auto[1]	auto[ResetSt]	170	1			T2	2		T12	4		T15	2
auto[1]	auto[IdleSt]	127	1			T2	8		T12	4		T48	3
auto[1]	auto[ClkMuxSt]	43	1			T2	1		T15	1		T46	3
auto[1]	auto[CntIncrSt]	30	1			T12	1		T47	1		T216	1
auto[1]	auto[CntProgSt]	640	1			T2	22		T12	8		T15	18
auto[1]	auto[TransCheckSt]	106	1			T2	1		T12	4		T46	6
auto[1]	auto[TokenHashSt]	483	1			T2	6		T12	16		T15	5
auto[1]	auto[FlashRmaSt]	59	1			T12	1		T15	1		T46	1
auto[1]	auto[TokenCheck0St]	15	1			T12	1		T15	1		T216	2
auto[1]	auto[TokenCheck1St]	84	1			T2	1		T15	1		T46	2
auto[1]	auto[TransProgSt]	468	1			T2	8		T12	7		T15	13
auto[1]	auto[PostTransSt]	3059	1			T1	5		T2	3		T10	7
auto[1]	auto[ScrapSt]	43	1			T2	1		T12	2		T15	2
auto[1]	auto[EscalateSt]	1593139	1			T1	490		T2	11324		T3	490
auto[1]	auto[InvalidSt]	8742	1			T3	5		T5	51		T13	3

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8325166	1			T1	6650		T2	8396		T3	1176
auto[0]	auto[IdleSt]	28810701	1			T1	68395		T2	9723		T3	1044
auto[0]	auto[ClkMuxSt]	40106	1			T1	69		T2	76		T3	1
auto[0]	auto[CntIncrSt]	39801	1			T1	69		T2	73		T3	1
auto[0]	auto[CntProgSt]	2195218	1			T1	112		T2	841		T3	20
auto[0]	auto[TransCheckSt]	30899	1			T1	52		T2	39		T3	1
auto[0]	auto[TokenHashSt]	55684932	1			T1	2813		T2	1583		T3	10
auto[0]	auto[FlashRmaSt]	31828	1			T1	30		T2	36		T3	1
auto[0]	auto[TokenCheck0St]	14583	1			T1	15		T2	28		T3	1
auto[0]	auto[TokenCheck1St]	10794	1			T1	12		T2	27		T3	1
auto[0]	auto[TransProgSt]	575036	1			T1	19		T2	79		T3	104
auto[0]	auto[PostTransSt]	17548332	1			T1	57512		T2	9		T3	189
auto[0]	auto[ScrapSt]	280598	1			T2	2		T5	840		T12	4
auto[0]	auto[EscalateSt]	6534494	1			T1	3876		T2	5187		T3	840
auto[0]	auto[InvalidSt]	12880161	1			T3	466		T5	62338		T13	332
auto[1]	auto[ResetSt]	170	1			T2	4		T12	5		T15	4
auto[1]	auto[IdleSt]	123	1			T2	10		T12	4		T48	7
auto[1]	auto[ClkMuxSt]	42	1			T15	2		T46	1		T47	1
auto[1]	auto[CntIncrSt]	33	1			T2	2		T12	1		T47	1
auto[1]	auto[CntProgSt]	654	1			T2	22		T12	7		T15	21
auto[1]	auto[TransCheckSt]	113	1			T2	1		T12	5		T46	7
auto[1]	auto[TokenHashSt]	507	1			T2	8		T12	14		T15	3
auto[1]	auto[FlashRmaSt]	72	1			T12	2		T15	2		T46	1
auto[1]	auto[TokenCheck0St]	18	1			T15	1		T46	1		T47	2
auto[1]	auto[TokenCheck1St]	100	1			T2	1		T15	1		T46	3
auto[1]	auto[TransProgSt]	470	1			T2	19		T12	2		T15	18
auto[1]	auto[PostTransSt]	2957	1			T1	5		T2	1		T10	6
auto[1]	auto[ScrapSt]	44	1			T2	1		T12	2		T15	1
auto[1]	auto[EscalateSt]	1582471	1			T1	490		T2	14829		T3	98
auto[1]	auto[InvalidSt]	8604	1			T3	1		T5	41		T13	2