Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::sec_token_mux_idx_error_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::sec_token_mux_idx_error_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

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Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::sec_token_mux_idx_error_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::sec_token_mux_idx_error_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_q	8	0	8	100.00	100	1	1	0

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_states[ClkMuxSt]	481	1			T36	12		T54	3		T55	9
fsm_states[CntIncrSt]	472	1			T36	6		T54	7		T55	11
fsm_states[CntProgSt]	466	1			T36	12		T54	4		T55	7
fsm_states[TransCheckSt]	448	1			T36	11		T54	5		T55	2
fsm_states[FlashRmaSt]	499	1			T36	9		T54	11		T55	8
fsm_states[TokenHashSt]	448	1			T36	15		T54	7		T55	13
fsm_states[TokenCheck0St]	442	1			T36	16		T54	6		T55	5
fsm_states[TokenCheck1St]	482	1			T36	7		T54	7		T55	10