Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

91031921

1

T1

3577

T2

1132

T3

16772

auto[1]

1364532

1

T3

891

T4

5101

T5

594

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

91022748

1

T1

3577

T2

1132

T3

16376

auto[1]

1373705

1

T3

1287

T4

3535

T5

594

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6988388	1			T1	120		T2	68		T3	6370
auto[IdleSt]	21331330	1			T1	3457		T2	1064		T3	1748
auto[ClkMuxSt]	35303	1			T3	46		T4	12		T12	1
auto[CntIncrSt]	35155	1			T3	46		T4	12		T12	1
auto[CntProgSt]	1614632	1			T3	77		T4	24		T12	2
auto[TransCheckSt]	27033	1			T3	31		T12	1		T14	1
auto[TokenHashSt]	31338435	1			T3	338		T12	29		T14	144
auto[FlashRmaSt]	32958	1			T3	93		T15	11		T6	45
auto[TokenCheck0St]	12079	1			T3	24		T15	11		T6	17
auto[TokenCheck1St]	8724	1			T3	16		T15	11		T6	11
auto[TransProgSt]	391175	1			T3	31		T15	596		T6	231
auto[PostTransSt]	12828984	1			T3	5601		T4	1004		T12	913
auto[ScrapSt]	267939	1			T15	23		T11	931		T34	3
auto[EscalateSt]	6457113	1			T3	2737		T4	34172		T5	1615
auto[InvalidSt]	11025298	1			T3	505		T4	105496		T13	7755

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1907	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11025298	1			T3	505		T4	105496		T13	7755
EscalateSt	6457113	1			T3	2737		T4	34172		T5	1615
ScrapSt	267939	1			T15	23		T11	931		T34	3
PostTransSt	12828984	1			T3	5601		T4	1004		T12	913
TransProgSt	391175	1			T3	31		T15	596		T6	231
TokenCheck1St	8724	1			T3	16		T15	11		T6	11
TokenCheck0St	12079	1			T3	24		T15	11		T6	17
FlashRmaSt	32958	1			T3	93		T15	11		T6	45
TokenHashSt	31338435	1			T3	338		T12	29		T14	144
TransCheckSt	27033	1			T3	31		T12	1		T14	1
CntProgSt	1614632	1			T3	77		T4	24		T12	2
CntIncrSt	35155	1			T3	46		T4	12		T12	1
ClkMuxSt	35303	1			T3	46		T4	12		T12	1
IdleSt	21331330	1			T1	3457		T2	1064		T3	1748
ResetSt	6988388	1			T1	120		T2	68		T3	6370
arcs[ResetSt=>IdleSt]	52642	1			T1	1		T2	1		T3	54
arcs[IdleSt=>ScrapSt]	246	1			T15	1		T11	3		T34	1
arcs[IdleSt=>ClkMuxSt]	35227	1			T3	46		T4	12		T12	1
arcs[ClkMuxSt=>CntIncrSt]	35155	1			T3	46		T4	12		T12	1
arcs[CntIncrSt=>PostTransSt]	1987	1			T6	9		T16	4		T11	71
arcs[CntIncrSt=>CntProgSt]	33104	1			T3	46		T4	12		T12	1
arcs[CntProgSt=>PostTransSt]	4854	1			T3	15		T4	12		T5	12
arcs[CntProgSt=>TransCheckSt]	27033	1			T3	31		T12	1		T14	1
arcs[TransCheckSt=>PostTransSt]	3798	1			T6	4		T16	11		T11	79
arcs[TransCheckSt=>TokenHashSt]	23118	1			T3	31		T12	1		T14	1
arcs[TokenHashSt=>PostTransSt]	10272	1			T3	7		T12	1		T14	1
arcs[TokenHashSt=>FlashRmaSt]	12182	1			T3	24		T15	11		T6	17
arcs[FlashRmaSt=>TokenCheck0St]	12079	1			T3	24		T15	11		T6	17
arcs[TokenCheck0St=>PostTransSt]	3326	1			T3	8		T6	6		T16	8
arcs[TokenCheck0St=>TokenCheck1St]	8724	1			T3	16		T15	11		T6	11
arcs[TokenCheck1St=>PostTransSt]	631	1			T6	1		T11	4		T18	1
arcs[TransProgSt=>PostTransSt]	7136	1			T3	16		T15	11		T6	10
arcs[IdleSt=>EscalateSt]	189	1			T34	7		T50	7		T51	5
arcs[ClkMuxSt=>EscalateSt]	72	1			T34	2		T47	2		T48	2
arcs[CntIncrSt=>EscalateSt]	64	1			T47	2		T48	1		T49	3
arcs[CntProgSt=>EscalateSt]	1217	1			T34	12		T47	13		T50	17
arcs[TransCheckSt=>EscalateSt]	117	1			T34	7		T47	9		T50	1
arcs[TokenHashSt=>EscalateSt]	664	1			T34	20		T17	1		T55	1
arcs[FlashRmaSt=>EscalateSt]	103	1			T34	2		T47	1		T48	1
arcs[TokenCheck0St=>EscalateSt]	29	1			T34	1		T47	1		T54	1
arcs[TokenCheck1St=>EscalateSt]	139	1			T47	1		T50	2		T48	1
arcs[TransProgSt=>EscalateSt]	818	1			T34	13		T47	6		T50	13
arcs[PostTransSt=>EscalateSt]	5074	1			T3	15		T4	12		T5	12
arcs[InvalidSt=>EscalateSt]	12916	1			T3	7		T4	76		T13	57

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6988210	1			T1	120		T2	68		T3	6370
auto[0]	auto[IdleSt]	21331211	1			T1	3457		T2	1064		T3	1748
auto[0]	auto[ClkMuxSt]	35252	1			T3	46		T4	12		T12	1
auto[0]	auto[CntIncrSt]	35109	1			T3	46		T4	12		T12	1
auto[0]	auto[CntProgSt]	1613802	1			T3	77		T4	24		T12	2
auto[0]	auto[TransCheckSt]	26961	1			T3	31		T12	1		T14	1
auto[0]	auto[TokenHashSt]	31337984	1			T3	338		T12	29		T14	144
auto[0]	auto[FlashRmaSt]	32889	1			T3	93		T15	11		T6	45
auto[0]	auto[TokenCheck0St]	12062	1			T3	24		T15	11		T6	17
auto[0]	auto[TokenCheck1St]	8636	1			T3	16		T15	11		T6	11
auto[0]	auto[TransProgSt]	390631	1			T3	31		T15	596		T6	231
auto[0]	auto[PostTransSt]	12826390	1			T3	5595		T4	999		T12	913
auto[0]	auto[ScrapSt]	267905	1			T15	23		T11	931		T34	3
auto[0]	auto[EscalateSt]	5104066	1			T3	1855		T4	29123		T5	1027
auto[0]	auto[InvalidSt]	11018906	1			T3	502		T4	105449		T13	7729
auto[1]	auto[ResetSt]	178	1			T47	2		T50	4		T48	1
auto[1]	auto[IdleSt]	119	1			T34	6		T50	6		T51	3
auto[1]	auto[ClkMuxSt]	51	1			T34	2		T47	2		T48	1
auto[1]	auto[CntIncrSt]	46	1			T48	1		T49	2		T54	2
auto[1]	auto[CntProgSt]	830	1			T34	7		T47	10		T50	10
auto[1]	auto[TransCheckSt]	72	1			T34	2		T47	7		T48	2
auto[1]	auto[TokenHashSt]	451	1			T34	11		T47	21		T50	9
auto[1]	auto[FlashRmaSt]	69	1			T34	2		T48	1		T49	2
auto[1]	auto[TokenCheck0St]	17	1			T34	1		T195	1		T196	1
auto[1]	auto[TokenCheck1St]	88	1			T47	1		T50	2		T48	1
auto[1]	auto[TransProgSt]	544	1			T34	8		T47	5		T50	8
auto[1]	auto[PostTransSt]	2594	1			T3	6		T4	5		T5	6
auto[1]	auto[ScrapSt]	34	1			T48	1		T49	1		T51	1
auto[1]	auto[EscalateSt]	1353047	1			T3	882		T4	5049		T5	588
auto[1]	auto[InvalidSt]	6392	1			T3	3		T4	47		T13	26

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6988193	1			T1	120		T2	68		T3	6370
auto[0]	auto[IdleSt]	21331211	1			T1	3457		T2	1064		T3	1748
auto[0]	auto[ClkMuxSt]	35258	1			T3	46		T4	12		T12	1
auto[0]	auto[CntIncrSt]	35112	1			T3	46		T4	12		T12	1
auto[0]	auto[CntProgSt]	1613827	1			T3	77		T4	24		T12	2
auto[0]	auto[TransCheckSt]	26950	1			T3	31		T12	1		T14	1
auto[0]	auto[TokenHashSt]	31337998	1			T3	338		T12	29		T14	144
auto[0]	auto[FlashRmaSt]	32890	1			T3	93		T15	11		T6	45
auto[0]	auto[TokenCheck0St]	12057	1			T3	24		T15	11		T6	17
auto[0]	auto[TokenCheck1St]	8624	1			T3	16		T15	11		T6	11
auto[0]	auto[TransProgSt]	390622	1			T3	31		T15	596		T6	231
auto[0]	auto[PostTransSt]	12826429	1			T3	5592		T4	997		T12	913
auto[0]	auto[ScrapSt]	267898	1			T15	23		T11	931		T34	2
auto[0]	auto[EscalateSt]	5094998	1			T3	1463		T4	30673		T5	1027
auto[0]	auto[InvalidSt]	11018774	1			T3	501		T4	105467		T13	7724
auto[1]	auto[ResetSt]	195	1			T34	1		T47	2		T50	5
auto[1]	auto[IdleSt]	119	1			T34	3		T50	4		T51	4
auto[1]	auto[ClkMuxSt]	45	1			T48	2		T51	3		T197	2
auto[1]	auto[CntIncrSt]	43	1			T47	2		T48	1		T49	2
auto[1]	auto[CntProgSt]	805	1			T34	9		T47	9		T50	12
auto[1]	auto[TransCheckSt]	83	1			T34	7		T47	4		T50	1
auto[1]	auto[TokenHashSt]	437	1			T34	13		T17	1		T55	1
auto[1]	auto[FlashRmaSt]	68	1			T34	1		T47	1		T49	1
auto[1]	auto[TokenCheck0St]	22	1			T34	1		T47	1		T54	1
auto[1]	auto[TokenCheck1St]	100	1			T50	1		T48	1		T49	2
auto[1]	auto[TransProgSt]	553	1			T34	9		T47	5		T50	10
auto[1]	auto[PostTransSt]	2555	1			T3	9		T4	7		T5	6
auto[1]	auto[ScrapSt]	41	1			T34	1		T48	1		T49	2
auto[1]	auto[EscalateSt]	1362115	1			T3	1274		T4	3499		T5	588
auto[1]	auto[InvalidSt]	6524	1			T3	4		T4	29		T13	31