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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.22 97.92 95.93 93.38 100.00 98.52 98.51 96.29


Total test records in report: 989
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T816 /workspace/coverage/default/39.lc_ctrl_prog_failure.1803727316 Jul 02 09:59:12 AM PDT 24 Jul 02 09:59:22 AM PDT 24 140663875 ps
T817 /workspace/coverage/default/22.lc_ctrl_state_post_trans.3503988426 Jul 02 09:58:34 AM PDT 24 Jul 02 09:58:43 AM PDT 24 46276721 ps
T818 /workspace/coverage/default/3.lc_ctrl_prog_failure.907482760 Jul 02 09:57:58 AM PDT 24 Jul 02 09:58:02 AM PDT 24 54804281 ps
T819 /workspace/coverage/default/39.lc_ctrl_state_failure.1543000268 Jul 02 09:59:07 AM PDT 24 Jul 02 09:59:41 AM PDT 24 307488108 ps
T820 /workspace/coverage/default/12.lc_ctrl_jtag_errors.325224422 Jul 02 09:58:07 AM PDT 24 Jul 02 09:58:50 AM PDT 24 3291048898 ps
T147 /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.1992501655 Jul 02 09:58:45 AM PDT 24 Jul 02 10:03:45 AM PDT 24 12440598075 ps
T821 /workspace/coverage/default/27.lc_ctrl_stress_all.3294512397 Jul 02 09:58:40 AM PDT 24 Jul 02 09:59:51 AM PDT 24 6021235556 ps
T144 /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.3791221813 Jul 02 09:59:02 AM PDT 24 Jul 02 10:15:59 AM PDT 24 31221961859 ps
T822 /workspace/coverage/default/29.lc_ctrl_stress_all.4132539422 Jul 02 09:59:09 AM PDT 24 Jul 02 09:59:47 AM PDT 24 1307848044 ps
T823 /workspace/coverage/default/11.lc_ctrl_state_post_trans.276730760 Jul 02 09:58:11 AM PDT 24 Jul 02 09:58:23 AM PDT 24 105071558 ps
T824 /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3022657405 Jul 02 09:59:04 AM PDT 24 Jul 02 09:59:20 AM PDT 24 1233182991 ps
T825 /workspace/coverage/default/17.lc_ctrl_prog_failure.1554894218 Jul 02 09:58:28 AM PDT 24 Jul 02 09:58:32 AM PDT 24 124600774 ps
T826 /workspace/coverage/default/48.lc_ctrl_jtag_access.775497585 Jul 02 09:59:25 AM PDT 24 Jul 02 09:59:37 AM PDT 24 1191582084 ps
T89 /workspace/coverage/default/1.lc_ctrl_sec_cm.1141069091 Jul 02 09:57:40 AM PDT 24 Jul 02 09:58:04 AM PDT 24 209501561 ps
T827 /workspace/coverage/default/4.lc_ctrl_alert_test.3853177549 Jul 02 09:57:48 AM PDT 24 Jul 02 09:57:51 AM PDT 24 68393285 ps
T828 /workspace/coverage/default/38.lc_ctrl_sec_token_mux.2078427490 Jul 02 09:59:11 AM PDT 24 Jul 02 09:59:29 AM PDT 24 1860524767 ps
T53 /workspace/coverage/default/2.lc_ctrl_sec_cm.775900987 Jul 02 09:57:44 AM PDT 24 Jul 02 09:58:21 AM PDT 24 2876141598 ps
T829 /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3778262321 Jul 02 09:57:46 AM PDT 24 Jul 02 09:57:55 AM PDT 24 967336139 ps
T830 /workspace/coverage/default/26.lc_ctrl_prog_failure.1224045656 Jul 02 09:58:38 AM PDT 24 Jul 02 09:58:41 AM PDT 24 162919904 ps
T93 /workspace/coverage/default/3.lc_ctrl_sec_cm.875495208 Jul 02 09:57:50 AM PDT 24 Jul 02 09:58:29 AM PDT 24 208294992 ps
T831 /workspace/coverage/default/1.lc_ctrl_jtag_errors.2899448725 Jul 02 09:57:58 AM PDT 24 Jul 02 09:58:20 AM PDT 24 4924686939 ps
T832 /workspace/coverage/default/29.lc_ctrl_state_post_trans.4245701118 Jul 02 09:58:47 AM PDT 24 Jul 02 09:58:57 AM PDT 24 1369160244 ps
T833 /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1841238251 Jul 02 09:58:12 AM PDT 24 Jul 02 09:58:25 AM PDT 24 496289744 ps
T834 /workspace/coverage/default/1.lc_ctrl_claim_transition_if.382298239 Jul 02 09:57:46 AM PDT 24 Jul 02 09:57:49 AM PDT 24 30945969 ps
T835 /workspace/coverage/default/31.lc_ctrl_smoke.2637224445 Jul 02 09:58:57 AM PDT 24 Jul 02 09:59:02 AM PDT 24 57971482 ps
T836 /workspace/coverage/default/6.lc_ctrl_smoke.3243560213 Jul 02 09:58:05 AM PDT 24 Jul 02 09:58:13 AM PDT 24 13931321 ps
T837 /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3823953639 Jul 02 09:58:58 AM PDT 24 Jul 02 09:59:08 AM PDT 24 281325548 ps
T838 /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.4208073918 Jul 02 09:58:26 AM PDT 24 Jul 02 09:58:28 AM PDT 24 33785484 ps
T82 /workspace/coverage/default/30.lc_ctrl_stress_all.810576345 Jul 02 09:59:06 AM PDT 24 Jul 02 09:59:51 AM PDT 24 2028571880 ps
T76 /workspace/coverage/default/9.lc_ctrl_claim_transition_if.1902868149 Jul 02 09:58:05 AM PDT 24 Jul 02 09:58:12 AM PDT 24 16891231 ps
T839 /workspace/coverage/default/7.lc_ctrl_sec_token_mux.3159991004 Jul 02 09:58:06 AM PDT 24 Jul 02 09:58:20 AM PDT 24 1409147007 ps
T840 /workspace/coverage/default/5.lc_ctrl_jtag_access.2023881019 Jul 02 09:58:02 AM PDT 24 Jul 02 09:58:08 AM PDT 24 209908973 ps
T841 /workspace/coverage/default/25.lc_ctrl_state_failure.3745889953 Jul 02 09:58:52 AM PDT 24 Jul 02 09:59:22 AM PDT 24 1191415708 ps
T190 /workspace/coverage/default/6.lc_ctrl_claim_transition_if.1427636903 Jul 02 09:58:14 AM PDT 24 Jul 02 09:58:19 AM PDT 24 27365315 ps
T842 /workspace/coverage/default/11.lc_ctrl_jtag_errors.4270680873 Jul 02 09:58:10 AM PDT 24 Jul 02 09:58:46 AM PDT 24 1768665444 ps
T843 /workspace/coverage/default/27.lc_ctrl_state_post_trans.712320930 Jul 02 09:58:50 AM PDT 24 Jul 02 09:58:55 AM PDT 24 88707454 ps
T844 /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1301070400 Jul 02 09:59:16 AM PDT 24 Jul 02 09:59:28 AM PDT 24 789976426 ps
T845 /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3841183472 Jul 02 09:59:02 AM PDT 24 Jul 02 09:59:10 AM PDT 24 11575595 ps
T846 /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3098356295 Jul 02 09:58:39 AM PDT 24 Jul 02 09:58:46 AM PDT 24 238626755 ps
T847 /workspace/coverage/default/5.lc_ctrl_sec_token_digest.1929505862 Jul 02 09:57:50 AM PDT 24 Jul 02 09:58:05 AM PDT 24 253606115 ps
T848 /workspace/coverage/default/46.lc_ctrl_stress_all.2100207663 Jul 02 09:59:34 AM PDT 24 Jul 02 10:04:26 AM PDT 24 26036952416 ps
T849 /workspace/coverage/default/24.lc_ctrl_sec_token_digest.7043360 Jul 02 09:58:41 AM PDT 24 Jul 02 09:58:52 AM PDT 24 1433267003 ps
T850 /workspace/coverage/default/20.lc_ctrl_security_escalation.284834831 Jul 02 09:58:25 AM PDT 24 Jul 02 09:58:35 AM PDT 24 591213429 ps
T851 /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2618865773 Jul 02 09:58:46 AM PDT 24 Jul 02 09:59:00 AM PDT 24 422286187 ps
T852 /workspace/coverage/default/18.lc_ctrl_alert_test.1582843340 Jul 02 09:58:44 AM PDT 24 Jul 02 09:58:47 AM PDT 24 21102946 ps
T853 /workspace/coverage/default/45.lc_ctrl_alert_test.1225926393 Jul 02 09:59:27 AM PDT 24 Jul 02 09:59:30 AM PDT 24 65057030 ps
T189 /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2365349946 Jul 02 09:58:03 AM PDT 24 Jul 02 09:58:07 AM PDT 24 15151785 ps
T854 /workspace/coverage/default/10.lc_ctrl_errors.516983616 Jul 02 09:58:12 AM PDT 24 Jul 02 09:58:28 AM PDT 24 1336847258 ps
T855 /workspace/coverage/default/43.lc_ctrl_state_failure.605243566 Jul 02 09:59:10 AM PDT 24 Jul 02 09:59:41 AM PDT 24 433637448 ps
T856 /workspace/coverage/default/41.lc_ctrl_state_failure.570998277 Jul 02 09:59:08 AM PDT 24 Jul 02 09:59:42 AM PDT 24 2858160106 ps
T857 /workspace/coverage/default/9.lc_ctrl_alert_test.3852264322 Jul 02 09:58:04 AM PDT 24 Jul 02 09:58:10 AM PDT 24 132526028 ps
T858 /workspace/coverage/default/22.lc_ctrl_errors.2051201388 Jul 02 09:58:35 AM PDT 24 Jul 02 09:58:53 AM PDT 24 416993246 ps
T859 /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.622132351 Jul 02 09:58:01 AM PDT 24 Jul 02 09:58:17 AM PDT 24 407182042 ps
T860 /workspace/coverage/default/15.lc_ctrl_sec_token_digest.603204716 Jul 02 09:58:31 AM PDT 24 Jul 02 09:58:47 AM PDT 24 656565935 ps
T118 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.861928909 Jul 02 09:55:02 AM PDT 24 Jul 02 09:55:05 AM PDT 24 17019170 ps
T105 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1766796012 Jul 02 09:55:15 AM PDT 24 Jul 02 09:55:19 AM PDT 24 38014561 ps
T111 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2444390600 Jul 02 09:54:47 AM PDT 24 Jul 02 09:54:49 AM PDT 24 31443431 ps
T106 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.574641101 Jul 02 09:54:59 AM PDT 24 Jul 02 09:55:06 AM PDT 24 458952504 ps
T137 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.4284071869 Jul 02 09:55:16 AM PDT 24 Jul 02 09:55:20 AM PDT 24 188304901 ps
T112 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3408256540 Jul 02 09:54:57 AM PDT 24 Jul 02 09:54:59 AM PDT 24 17056154 ps
T113 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3200291626 Jul 02 09:55:08 AM PDT 24 Jul 02 09:55:10 AM PDT 24 70097947 ps
T861 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3528371378 Jul 02 09:54:48 AM PDT 24 Jul 02 09:54:50 AM PDT 24 61753887 ps
T178 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1915532224 Jul 02 09:55:00 AM PDT 24 Jul 02 09:55:07 AM PDT 24 21385788 ps
T102 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.482528221 Jul 02 09:54:58 AM PDT 24 Jul 02 09:55:01 AM PDT 24 368136481 ps
T139 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1367221635 Jul 02 09:55:10 AM PDT 24 Jul 02 09:55:35 AM PDT 24 2370988324 ps
T862 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2900556705 Jul 02 09:55:07 AM PDT 24 Jul 02 09:55:09 AM PDT 24 20376731 ps
T138 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.269700040 Jul 02 09:55:10 AM PDT 24 Jul 02 09:55:15 AM PDT 24 904527933 ps
T134 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.296237844 Jul 02 09:55:01 AM PDT 24 Jul 02 09:55:05 AM PDT 24 472672427 ps
T863 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2585903931 Jul 02 09:54:49 AM PDT 24 Jul 02 09:54:52 AM PDT 24 28507471 ps
T125 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.112183242 Jul 02 09:55:03 AM PDT 24 Jul 02 09:55:06 AM PDT 24 69650562 ps
T864 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1966637578 Jul 02 09:55:18 AM PDT 24 Jul 02 09:55:23 AM PDT 24 77222319 ps
T179 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3031345129 Jul 02 09:54:52 AM PDT 24 Jul 02 09:54:54 AM PDT 24 19101574 ps
T865 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3931492212 Jul 02 09:55:09 AM PDT 24 Jul 02 09:55:11 AM PDT 24 22319045 ps
T180 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2806949875 Jul 02 09:55:04 AM PDT 24 Jul 02 09:55:07 AM PDT 24 186797232 ps
T170 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1970640786 Jul 02 09:54:58 AM PDT 24 Jul 02 09:55:00 AM PDT 24 13863053 ps
T103 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2140824142 Jul 02 09:55:13 AM PDT 24 Jul 02 09:55:18 AM PDT 24 80575572 ps
T135 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3057664969 Jul 02 09:54:54 AM PDT 24 Jul 02 09:54:57 AM PDT 24 411597983 ps
T866 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3111157876 Jul 02 09:55:08 AM PDT 24 Jul 02 09:55:10 AM PDT 24 37862385 ps
T867 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.348384972 Jul 02 09:55:02 AM PDT 24 Jul 02 09:55:04 AM PDT 24 544542137 ps
T181 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3960088034 Jul 02 09:55:23 AM PDT 24 Jul 02 09:55:28 AM PDT 24 41728208 ps
T868 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3161536310 Jul 02 09:55:14 AM PDT 24 Jul 02 09:55:18 AM PDT 24 57239478 ps
T171 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.269583757 Jul 02 09:55:19 AM PDT 24 Jul 02 09:55:22 AM PDT 24 34080576 ps
T136 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.4189649166 Jul 02 09:55:06 AM PDT 24 Jul 02 09:55:16 AM PDT 24 591523694 ps
T104 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.4060665888 Jul 02 09:55:11 AM PDT 24 Jul 02 09:55:15 AM PDT 24 80722174 ps
T107 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3121318209 Jul 02 09:55:20 AM PDT 24 Jul 02 09:55:25 AM PDT 24 244662797 ps
T182 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.279094747 Jul 02 09:55:08 AM PDT 24 Jul 02 09:55:11 AM PDT 24 163472189 ps
T183 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.4170012395 Jul 02 09:55:19 AM PDT 24 Jul 02 09:55:23 AM PDT 24 21253678 ps
T184 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1127299936 Jul 02 09:55:19 AM PDT 24 Jul 02 09:55:23 AM PDT 24 161776408 ps
T124 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.10907448 Jul 02 09:55:25 AM PDT 24 Jul 02 09:55:40 AM PDT 24 86881699 ps
T869 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.881234657 Jul 02 09:55:10 AM PDT 24 Jul 02 09:55:14 AM PDT 24 64433449 ps
T108 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3504664710 Jul 02 09:55:17 AM PDT 24 Jul 02 09:55:22 AM PDT 24 158256258 ps
T114 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.4280584843 Jul 02 09:55:09 AM PDT 24 Jul 02 09:55:12 AM PDT 24 36502089 ps
T870 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.447556531 Jul 02 09:55:11 AM PDT 24 Jul 02 09:55:15 AM PDT 24 116332661 ps
T185 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1330686615 Jul 02 09:55:02 AM PDT 24 Jul 02 09:55:04 AM PDT 24 28446401 ps
T871 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2795522073 Jul 02 09:55:09 AM PDT 24 Jul 02 09:55:11 AM PDT 24 165323152 ps
T872 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3645588670 Jul 02 09:55:11 AM PDT 24 Jul 02 09:55:27 AM PDT 24 1100735727 ps
T110 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1316504412 Jul 02 09:55:11 AM PDT 24 Jul 02 09:55:16 AM PDT 24 323067857 ps
T172 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.734895090 Jul 02 09:55:16 AM PDT 24 Jul 02 09:55:19 AM PDT 24 18440127 ps
T873 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3517680732 Jul 02 09:54:55 AM PDT 24 Jul 02 09:55:00 AM PDT 24 694311996 ps
T874 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.4192317216 Jul 02 09:55:10 AM PDT 24 Jul 02 09:55:14 AM PDT 24 122154122 ps
T126 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3480813500 Jul 02 09:55:18 AM PDT 24 Jul 02 09:55:22 AM PDT 24 27474357 ps
T875 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3301360536 Jul 02 09:55:03 AM PDT 24 Jul 02 09:55:06 AM PDT 24 44934338 ps
T876 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.516306300 Jul 02 09:55:09 AM PDT 24 Jul 02 09:55:12 AM PDT 24 97480006 ps
T877 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3675750613 Jul 02 09:55:08 AM PDT 24 Jul 02 09:55:59 AM PDT 24 4828877726 ps
T878 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3865882382 Jul 02 09:55:18 AM PDT 24 Jul 02 09:55:22 AM PDT 24 16148837 ps
T879 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.818050538 Jul 02 09:54:56 AM PDT 24 Jul 02 09:54:59 AM PDT 24 23956088 ps
T880 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.204349906 Jul 02 09:55:11 AM PDT 24 Jul 02 09:55:17 AM PDT 24 861441393 ps
T109 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3240485011 Jul 02 09:55:20 AM PDT 24 Jul 02 09:55:25 AM PDT 24 147907356 ps
T881 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1752718078 Jul 02 09:54:43 AM PDT 24 Jul 02 09:54:45 AM PDT 24 212853686 ps
T128 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.534776674 Jul 02 09:55:15 AM PDT 24 Jul 02 09:55:19 AM PDT 24 60557929 ps
T882 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2709628296 Jul 02 09:54:53 AM PDT 24 Jul 02 09:54:58 AM PDT 24 685497376 ps
T883 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2817904029 Jul 02 09:54:55 AM PDT 24 Jul 02 09:54:58 AM PDT 24 257005859 ps
T884 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2307673023 Jul 02 09:54:48 AM PDT 24 Jul 02 09:54:51 AM PDT 24 531361910 ps
T885 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.967065963 Jul 02 09:55:22 AM PDT 24 Jul 02 09:55:31 AM PDT 24 409489093 ps
T886 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.794066897 Jul 02 09:55:02 AM PDT 24 Jul 02 09:55:05 AM PDT 24 21665017 ps
T887 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1582596023 Jul 02 09:55:11 AM PDT 24 Jul 02 09:55:15 AM PDT 24 105976683 ps
T121 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.595707582 Jul 02 09:55:17 AM PDT 24 Jul 02 09:55:21 AM PDT 24 283802033 ps
T888 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2968940613 Jul 02 09:55:10 AM PDT 24 Jul 02 09:55:15 AM PDT 24 85958849 ps
T889 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1803316600 Jul 02 09:55:20 AM PDT 24 Jul 02 09:55:25 AM PDT 24 110273090 ps
T890 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3150252885 Jul 02 09:55:04 AM PDT 24 Jul 02 09:55:06 AM PDT 24 49653219 ps
T193 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1236253881 Jul 02 09:55:27 AM PDT 24 Jul 02 09:55:39 AM PDT 24 182195023 ps
T891 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.4023756750 Jul 02 09:54:54 AM PDT 24 Jul 02 09:54:57 AM PDT 24 19818752 ps
T892 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1091849693 Jul 02 09:55:10 AM PDT 24 Jul 02 09:55:14 AM PDT 24 15414535 ps
T893 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2448992095 Jul 02 09:55:11 AM PDT 24 Jul 02 09:55:15 AM PDT 24 154632228 ps
T894 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2672282501 Jul 02 09:55:14 AM PDT 24 Jul 02 09:55:19 AM PDT 24 79802259 ps
T895 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3274774612 Jul 02 09:55:24 AM PDT 24 Jul 02 09:55:31 AM PDT 24 85740443 ps
T896 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2160491875 Jul 02 09:55:13 AM PDT 24 Jul 02 09:55:17 AM PDT 24 61321125 ps
T897 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1879277336 Jul 02 09:55:10 AM PDT 24 Jul 02 09:55:15 AM PDT 24 2608417341 ps
T898 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.413890167 Jul 02 09:55:01 AM PDT 24 Jul 02 09:55:13 AM PDT 24 451669000 ps
T899 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3159743917 Jul 02 09:55:13 AM PDT 24 Jul 02 09:55:16 AM PDT 24 215370633 ps
T900 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1933557058 Jul 02 09:54:42 AM PDT 24 Jul 02 09:54:45 AM PDT 24 82556377 ps
T901 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2545693954 Jul 02 09:54:42 AM PDT 24 Jul 02 09:54:45 AM PDT 24 175390434 ps
T902 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.265980870 Jul 02 09:55:07 AM PDT 24 Jul 02 09:55:11 AM PDT 24 152526198 ps
T903 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.414719728 Jul 02 09:54:44 AM PDT 24 Jul 02 09:54:46 AM PDT 24 17674898 ps
T173 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2048190951 Jul 02 09:54:54 AM PDT 24 Jul 02 09:54:57 AM PDT 24 54512321 ps
T904 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1875140361 Jul 02 09:55:17 AM PDT 24 Jul 02 09:55:21 AM PDT 24 212699372 ps
T905 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3171546545 Jul 02 09:55:16 AM PDT 24 Jul 02 09:55:20 AM PDT 24 766277699 ps
T906 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1098641912 Jul 02 09:54:56 AM PDT 24 Jul 02 09:54:59 AM PDT 24 87531726 ps
T907 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3751073558 Jul 02 09:55:11 AM PDT 24 Jul 02 09:55:15 AM PDT 24 49399776 ps
T908 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1848923561 Jul 02 09:55:00 AM PDT 24 Jul 02 09:55:02 AM PDT 24 24203345 ps
T909 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1676666808 Jul 02 09:55:24 AM PDT 24 Jul 02 09:55:43 AM PDT 24 949152914 ps
T133 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.550860448 Jul 02 09:54:55 AM PDT 24 Jul 02 09:55:00 AM PDT 24 114338366 ps
T910 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.769737366 Jul 02 09:55:20 AM PDT 24 Jul 02 09:55:24 AM PDT 24 14427313 ps
T911 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1576596408 Jul 02 09:55:05 AM PDT 24 Jul 02 09:55:08 AM PDT 24 297737020 ps
T912 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2718427277 Jul 02 09:55:09 AM PDT 24 Jul 02 09:55:11 AM PDT 24 109929350 ps
T913 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2110524905 Jul 02 09:55:20 AM PDT 24 Jul 02 09:55:24 AM PDT 24 60647733 ps
T914 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3440553558 Jul 02 09:54:58 AM PDT 24 Jul 02 09:55:02 AM PDT 24 48089009 ps
T915 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.977824006 Jul 02 09:55:17 AM PDT 24 Jul 02 09:55:27 AM PDT 24 168163029 ps
T916 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.838276832 Jul 02 09:55:19 AM PDT 24 Jul 02 09:55:24 AM PDT 24 237892765 ps
T917 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2340669576 Jul 02 09:55:08 AM PDT 24 Jul 02 09:55:09 AM PDT 24 13142335 ps
T115 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3399907688 Jul 02 09:55:13 AM PDT 24 Jul 02 09:55:18 AM PDT 24 62449913 ps
T116 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.195737735 Jul 02 09:55:17 AM PDT 24 Jul 02 09:55:22 AM PDT 24 219592414 ps
T918 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.69029854 Jul 02 09:55:11 AM PDT 24 Jul 02 09:55:15 AM PDT 24 164266169 ps
T919 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1912594367 Jul 02 09:55:11 AM PDT 24 Jul 02 09:55:19 AM PDT 24 3091373839 ps
T920 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2835904590 Jul 02 09:54:47 AM PDT 24 Jul 02 09:54:50 AM PDT 24 180211089 ps
T921 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1072168648 Jul 02 09:54:47 AM PDT 24 Jul 02 09:54:50 AM PDT 24 62871407 ps
T922 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2546367410 Jul 02 09:55:02 AM PDT 24 Jul 02 09:55:11 AM PDT 24 385258912 ps
T923 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3013129347 Jul 02 09:55:04 AM PDT 24 Jul 02 09:55:13 AM PDT 24 45627932 ps
T924 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2411862426 Jul 02 09:55:15 AM PDT 24 Jul 02 09:55:18 AM PDT 24 59390684 ps
T925 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.414310330 Jul 02 09:55:11 AM PDT 24 Jul 02 09:55:15 AM PDT 24 14910450 ps
T926 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.181815054 Jul 02 09:55:09 AM PDT 24 Jul 02 09:55:13 AM PDT 24 56681706 ps
T927 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.357238440 Jul 02 09:55:12 AM PDT 24 Jul 02 09:55:16 AM PDT 24 367976540 ps
T928 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.215153814 Jul 02 09:55:01 AM PDT 24 Jul 02 09:55:04 AM PDT 24 29756380 ps
T130 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1631696084 Jul 02 09:55:08 AM PDT 24 Jul 02 09:55:12 AM PDT 24 77458814 ps
T929 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.4281360792 Jul 02 09:55:11 AM PDT 24 Jul 02 09:55:15 AM PDT 24 66955973 ps
T930 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1794380925 Jul 02 09:55:16 AM PDT 24 Jul 02 09:55:20 AM PDT 24 241522567 ps
T931 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2650541604 Jul 02 09:55:07 AM PDT 24 Jul 02 09:55:09 AM PDT 24 14940429 ps
T932 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.4171509550 Jul 02 09:55:19 AM PDT 24 Jul 02 09:55:23 AM PDT 24 128002647 ps
T933 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1768058303 Jul 02 09:55:11 AM PDT 24 Jul 02 09:55:14 AM PDT 24 69621274 ps
T934 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3189834230 Jul 02 09:55:17 AM PDT 24 Jul 02 09:55:20 AM PDT 24 182855465 ps
T935 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.4152502249 Jul 02 09:55:18 AM PDT 24 Jul 02 09:55:22 AM PDT 24 91828592 ps
T936 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1569707677 Jul 02 09:55:14 AM PDT 24 Jul 02 09:55:17 AM PDT 24 64672697 ps
T117 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.600103174 Jul 02 09:55:14 AM PDT 24 Jul 02 09:55:21 AM PDT 24 193760134 ps
T132 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1190352713 Jul 02 09:55:04 AM PDT 24 Jul 02 09:55:09 AM PDT 24 801819963 ps
T937 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1787185712 Jul 02 09:55:14 AM PDT 24 Jul 02 09:55:18 AM PDT 24 262705404 ps
T938 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.4051040563 Jul 02 09:54:59 AM PDT 24 Jul 02 09:55:01 AM PDT 24 58627732 ps
T177 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2487117577 Jul 02 09:55:18 AM PDT 24 Jul 02 09:55:21 AM PDT 24 12554101 ps
T939 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3436792244 Jul 02 09:55:13 AM PDT 24 Jul 02 09:55:19 AM PDT 24 86028365 ps
T127 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3466709119 Jul 02 09:55:31 AM PDT 24 Jul 02 09:55:43 AM PDT 24 61137247 ps
T940 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2259729345 Jul 02 09:55:21 AM PDT 24 Jul 02 09:55:25 AM PDT 24 70312445 ps
T122 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2955886087 Jul 02 09:55:09 AM PDT 24 Jul 02 09:55:13 AM PDT 24 298707873 ps
T941 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3530736439 Jul 02 09:55:10 AM PDT 24 Jul 02 09:55:13 AM PDT 24 70320078 ps
T942 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2508084079 Jul 02 09:55:15 AM PDT 24 Jul 02 09:55:20 AM PDT 24 254986883 ps
T943 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3353585446 Jul 02 09:55:24 AM PDT 24 Jul 02 09:55:31 AM PDT 24 14821816 ps
T944 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3490793659 Jul 02 09:55:24 AM PDT 24 Jul 02 09:55:33 AM PDT 24 64419142 ps
T945 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.59523375 Jul 02 09:54:46 AM PDT 24 Jul 02 09:54:48 AM PDT 24 39683886 ps
T946 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2667787437 Jul 02 09:55:05 AM PDT 24 Jul 02 09:55:17 AM PDT 24 2063956107 ps
T947 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.307511246 Jul 02 09:54:57 AM PDT 24 Jul 02 09:55:03 AM PDT 24 5895421262 ps
T948 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2527358151 Jul 02 09:55:10 AM PDT 24 Jul 02 09:55:28 AM PDT 24 1662819000 ps
T949 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2602247541 Jul 02 09:54:56 AM PDT 24 Jul 02 09:54:59 AM PDT 24 33791829 ps
T950 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.268412521 Jul 02 09:54:56 AM PDT 24 Jul 02 09:55:00 AM PDT 24 97077577 ps
T951 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1294905839 Jul 02 09:55:08 AM PDT 24 Jul 02 09:55:11 AM PDT 24 193370406 ps
T952 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1345639381 Jul 02 09:54:56 AM PDT 24 Jul 02 09:54:59 AM PDT 24 27547926 ps
T953 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1019520242 Jul 02 09:55:02 AM PDT 24 Jul 02 09:55:05 AM PDT 24 39816597 ps
T954 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1001926150 Jul 02 09:55:10 AM PDT 24 Jul 02 09:55:15 AM PDT 24 114481761 ps
T955 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2927808572 Jul 02 09:55:11 AM PDT 24 Jul 02 09:55:17 AM PDT 24 41860548 ps
T956 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.27536250 Jul 02 09:55:12 AM PDT 24 Jul 02 09:55:15 AM PDT 24 47288397 ps
T957 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2217306494 Jul 02 09:55:11 AM PDT 24 Jul 02 09:55:15 AM PDT 24 200311077 ps
T958 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2087439481 Jul 02 09:55:12 AM PDT 24 Jul 02 09:55:19 AM PDT 24 124758403 ps
T959 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3643853756 Jul 02 09:54:53 AM PDT 24 Jul 02 09:54:56 AM PDT 24 39459115 ps
T960 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2431078179 Jul 02 09:55:15 AM PDT 24 Jul 02 09:55:20 AM PDT 24 450072771 ps
T961 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.415286150 Jul 02 09:55:13 AM PDT 24 Jul 02 09:55:28 AM PDT 24 1021094111 ps
T962 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2109112208 Jul 02 09:55:02 AM PDT 24 Jul 02 09:55:05 AM PDT 24 309343935 ps
T963 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1466829542 Jul 02 09:54:58 AM PDT 24 Jul 02 09:55:04 AM PDT 24 722262715 ps
T174 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2687126850 Jul 02 09:55:20 AM PDT 24 Jul 02 09:55:24 AM PDT 24 181988089 ps
T964 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3332195221 Jul 02 09:55:08 AM PDT 24 Jul 02 09:55:10 AM PDT 24 40591285 ps
T965 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1730618634 Jul 02 09:55:06 AM PDT 24 Jul 02 09:55:09 AM PDT 24 210982696 ps
T966 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.39868550 Jul 02 09:55:24 AM PDT 24 Jul 02 09:55:31 AM PDT 24 20709354 ps
T967 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2414023300 Jul 02 09:55:25 AM PDT 24 Jul 02 09:55:35 AM PDT 24 68382697 ps
T968 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3472671842 Jul 02 09:55:10 AM PDT 24 Jul 02 09:55:13 AM PDT 24 13808502 ps
T969 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3749750851 Jul 02 09:55:24 AM PDT 24 Jul 02 09:55:46 AM PDT 24 352415524 ps
T129 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2000891953 Jul 02 09:55:24 AM PDT 24 Jul 02 09:55:36 AM PDT 24 90919197 ps
T119 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2061897646 Jul 02 09:55:26 AM PDT 24 Jul 02 09:55:39 AM PDT 24 721572636 ps
T970 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2777307203 Jul 02 09:54:59 AM PDT 24 Jul 02 09:55:01 AM PDT 24 19597376 ps
T971 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1394935167 Jul 02 09:55:11 AM PDT 24 Jul 02 09:55:15 AM PDT 24 205635480 ps
T972 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1530144456 Jul 02 09:54:53 AM PDT 24 Jul 02 09:54:55 AM PDT 24 65252195 ps
T973 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.754983228 Jul 02 09:55:13 AM PDT 24 Jul 02 09:55:27 AM PDT 24 2851903073 ps
T974 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.800575172 Jul 02 09:54:54 AM PDT 24 Jul 02 09:54:59 AM PDT 24 267559099 ps
T975 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1293819524 Jul 02 09:55:09 AM PDT 24 Jul 02 09:55:27 AM PDT 24 4972081566 ps
T120 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.458770722 Jul 02 09:55:10 AM PDT 24 Jul 02 09:55:15 AM PDT 24 147744075 ps
T976 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2231455987 Jul 02 09:55:28 AM PDT 24 Jul 02 09:55:39 AM PDT 24 40681924 ps
T977 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2858317066 Jul 02 09:55:23 AM PDT 24 Jul 02 09:55:27 AM PDT 24 105500824 ps
T978 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.318113174 Jul 02 09:55:10 AM PDT 24 Jul 02 09:55:13 AM PDT 24 44333641 ps
T979 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2877684689 Jul 02 09:55:02 AM PDT 24 Jul 02 09:55:16 AM PDT 24 2467275436 ps
T175 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.124548005 Jul 02 09:55:08 AM PDT 24 Jul 02 09:55:10 AM PDT 24 12763142 ps
T131 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.427802675 Jul 02 09:55:20 AM PDT 24 Jul 02 09:55:25 AM PDT 24 128720850 ps
T980 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2704205402 Jul 02 09:55:02 AM PDT 24 Jul 02 09:55:15 AM PDT 24 1811155956 ps
T981 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2114482255 Jul 02 09:55:18 AM PDT 24 Jul 02 09:55:22 AM PDT 24 28503963 ps
T982 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3507491835 Jul 02 09:55:14 AM PDT 24 Jul 02 09:55:18 AM PDT 24 32247691 ps
T176 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3093961463 Jul 02 09:55:04 AM PDT 24 Jul 02 09:55:07 AM PDT 24 37665137 ps
T983 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.646185350 Jul 02 09:55:03 AM PDT 24 Jul 02 09:55:07 AM PDT 24 405662710 ps
T984 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3282737403 Jul 02 09:55:18 AM PDT 24 Jul 02 09:55:24 AM PDT 24 164317400 ps
T985 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3401315329 Jul 02 09:55:01 AM PDT 24 Jul 02 09:55:04 AM PDT 24 93814837 ps
T194 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2413288120 Jul 02 09:55:08 AM PDT 24 Jul 02 09:55:13 AM PDT 24 1806678490 ps
T123 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1627840147 Jul 02 09:54:53 AM PDT 24 Jul 02 09:54:56 AM PDT 24 206124244 ps
T986 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1248707892 Jul 02 09:54:55 AM PDT 24 Jul 02 09:54:59 AM PDT 24 804644780 ps
T987 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3481260670 Jul 02 09:55:24 AM PDT 24 Jul 02 09:55:38 AM PDT 24 448168159 ps
T988 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2731866855 Jul 02 09:55:21 AM PDT 24 Jul 02 09:55:26 AM PDT 24 136208138 ps
T989 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2757954449 Jul 02 09:54:59 AM PDT 24 Jul 02 09:55:03 AM PDT 24 221266159 ps

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2106284187
Short name T3
Test name
Test status
Simulation time 353272405 ps
CPU time 9.68 seconds
Started Jul 02 09:58:07 AM PDT 24
Finished Jul 02 09:58:23 AM PDT 24
Peak memory 226020 kb
Host smart-fdb21807-0485-42b7-a16c-b22adccc9438
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106284187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2106284187
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.724062818
Short name T11
Test name
Test status
Simulation time 206911169467 ps
CPU time 1172.4 seconds
Started Jul 02 09:58:06 AM PDT 24
Finished Jul 02 10:17:45 AM PDT 24
Peak memory 283908 kb
Host smart-3de7f0e5-7ece-412b-93fc-ac7dbfc14d33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=724062818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.724062818
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1476208443
Short name T51
Test name
Test status
Simulation time 744295256 ps
CPU time 14.16 seconds
Started Jul 02 09:59:12 AM PDT 24
Finished Jul 02 09:59:33 AM PDT 24
Peak memory 226016 kb
Host smart-9741c9a9-54c3-4d5c-af07-0c92d3c2f43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476208443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1476208443
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.3444170087
Short name T145
Test name
Test status
Simulation time 7609226183 ps
CPU time 201.1 seconds
Started Jul 02 09:59:14 AM PDT 24
Finished Jul 02 10:02:41 AM PDT 24
Peak memory 273860 kb
Host smart-5338fee3-d7ab-4258-95c5-6847d1eaa95e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3444170087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.3444170087
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.1249505680
Short name T52
Test name
Test status
Simulation time 218208520 ps
CPU time 35.81 seconds
Started Jul 02 09:58:04 AM PDT 24
Finished Jul 02 09:58:44 AM PDT 24
Peak memory 282092 kb
Host smart-8d4cae46-4f82-4890-8eba-16d8edac909d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249505680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1249505680
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2393565549
Short name T34
Test name
Test status
Simulation time 1284248068 ps
CPU time 12.64 seconds
Started Jul 02 09:58:28 AM PDT 24
Finished Jul 02 09:58:42 AM PDT 24
Peak memory 226016 kb
Host smart-0ed28684-c2d1-4005-88e7-2808cc7bb2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393565549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2393565549
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.3921240702
Short name T17
Test name
Test status
Simulation time 28263346216 ps
CPU time 644.8 seconds
Started Jul 02 09:58:58 AM PDT 24
Finished Jul 02 10:09:46 AM PDT 24
Peak memory 333112 kb
Host smart-bd2bb39e-38d6-4315-b26e-83a9e0019360
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3921240702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.3921240702
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3599034618
Short name T7
Test name
Test status
Simulation time 970469962 ps
CPU time 6.04 seconds
Started Jul 02 09:58:25 AM PDT 24
Finished Jul 02 09:58:33 AM PDT 24
Peak memory 217224 kb
Host smart-39eb2111-7b7a-4426-a492-dca0a9895263
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599034618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3599034618
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2140824142
Short name T103
Test name
Test status
Simulation time 80575572 ps
CPU time 2.98 seconds
Started Jul 02 09:55:13 AM PDT 24
Finished Jul 02 09:55:18 AM PDT 24
Peak memory 222196 kb
Host smart-4109a2ec-f9e8-42a9-9bb2-008bc287ce61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140824142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2140824142
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.1397468525
Short name T48
Test name
Test status
Simulation time 1548482210 ps
CPU time 10.72 seconds
Started Jul 02 09:58:58 AM PDT 24
Finished Jul 02 09:59:10 AM PDT 24
Peak memory 226016 kb
Host smart-feb52f92-5d80-49fb-b4e7-974d4731ecdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397468525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.1397468525
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.1194863553
Short name T32
Test name
Test status
Simulation time 14970318 ps
CPU time 0.86 seconds
Started Jul 02 09:58:12 AM PDT 24
Finished Jul 02 09:58:18 AM PDT 24
Peak memory 208868 kb
Host smart-0ae2aa7a-c111-4f99-bb72-be2af82ac479
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194863553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.1194863553
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1358252087
Short name T60
Test name
Test status
Simulation time 1259195214 ps
CPU time 10.68 seconds
Started Jul 02 09:58:08 AM PDT 24
Finished Jul 02 09:58:26 AM PDT 24
Peak memory 218180 kb
Host smart-759c07a1-21ef-424c-adbc-3c1cd633ab63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358252087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1358252087
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.574641101
Short name T106
Test name
Test status
Simulation time 458952504 ps
CPU time 6.11 seconds
Started Jul 02 09:54:59 AM PDT 24
Finished Jul 02 09:55:06 AM PDT 24
Peak memory 217968 kb
Host smart-9a43c765-9a50-42da-9293-3a701278b048
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574641
101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.574641101
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.124548005
Short name T175
Test name
Test status
Simulation time 12763142 ps
CPU time 1.1 seconds
Started Jul 02 09:55:08 AM PDT 24
Finished Jul 02 09:55:10 AM PDT 24
Peak memory 209056 kb
Host smart-6524586e-2495-4c9f-9d65-8c35f5e8f275
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124548005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.124548005
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3200291626
Short name T113
Test name
Test status
Simulation time 70097947 ps
CPU time 1.17 seconds
Started Jul 02 09:55:08 AM PDT 24
Finished Jul 02 09:55:10 AM PDT 24
Peak memory 217532 kb
Host smart-3272cc2b-66a0-4837-9c7b-f57449ed6d6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200291626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3200291626
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.534776674
Short name T128
Test name
Test status
Simulation time 60557929 ps
CPU time 2.08 seconds
Started Jul 02 09:55:15 AM PDT 24
Finished Jul 02 09:55:19 AM PDT 24
Peak memory 218616 kb
Host smart-b8bf65ae-75a5-433b-82b1-604dff603dfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534776674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.534776674
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2061897646
Short name T119
Test name
Test status
Simulation time 721572636 ps
CPU time 4.23 seconds
Started Jul 02 09:55:26 AM PDT 24
Finished Jul 02 09:55:39 AM PDT 24
Peak memory 217684 kb
Host smart-93e8303a-bb1a-4b1f-a119-fe8a77b79593
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061897646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.2061897646
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.3594220690
Short name T38
Test name
Test status
Simulation time 348196831 ps
CPU time 11.1 seconds
Started Jul 02 09:59:22 AM PDT 24
Finished Jul 02 09:59:36 AM PDT 24
Peak memory 226028 kb
Host smart-a8355f81-9e88-4e14-a4e3-1f9ab834f250
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594220690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.3594220690
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.2716364620
Short name T18
Test name
Test status
Simulation time 4550838009 ps
CPU time 73.72 seconds
Started Jul 02 09:59:12 AM PDT 24
Finished Jul 02 10:00:32 AM PDT 24
Peak memory 251028 kb
Host smart-9fd0f10b-26ae-4ca3-8f36-95b22558c88a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716364620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.2716364620
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.600103174
Short name T117
Test name
Test status
Simulation time 193760134 ps
CPU time 4.19 seconds
Started Jul 02 09:55:14 AM PDT 24
Finished Jul 02 09:55:21 AM PDT 24
Peak memory 217576 kb
Host smart-11f9f6f8-ad0d-4021-9337-6c729dd62273
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600103174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.600103174
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.307838109
Short name T14
Test name
Test status
Simulation time 13600235 ps
CPU time 0.88 seconds
Started Jul 02 09:59:23 AM PDT 24
Finished Jul 02 09:59:26 AM PDT 24
Peak memory 212100 kb
Host smart-1afe3a2d-a49d-4c84-96b3-3195e2d28a04
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307838109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.307838109
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.847388188
Short name T42
Test name
Test status
Simulation time 86432397430 ps
CPU time 326.83 seconds
Started Jul 02 09:57:49 AM PDT 24
Finished Jul 02 10:03:18 AM PDT 24
Peak memory 267676 kb
Host smart-680aba2c-4670-46ca-9300-c4c018b91e6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=847388188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.847388188
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3121318209
Short name T107
Test name
Test status
Simulation time 244662797 ps
CPU time 1.91 seconds
Started Jul 02 09:55:20 AM PDT 24
Finished Jul 02 09:55:25 AM PDT 24
Peak memory 221968 kb
Host smart-c7181d1c-d988-4aa2-bb51-b1b0f987b325
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121318209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.3121318209
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2955886087
Short name T122
Test name
Test status
Simulation time 298707873 ps
CPU time 2 seconds
Started Jul 02 09:55:09 AM PDT 24
Finished Jul 02 09:55:13 AM PDT 24
Peak memory 222276 kb
Host smart-ef41d1e6-8295-4b1c-b2eb-bf5d087fa5e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955886087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.2955886087
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.550860448
Short name T133
Test name
Test status
Simulation time 114338366 ps
CPU time 3.07 seconds
Started Jul 02 09:54:55 AM PDT 24
Finished Jul 02 09:55:00 AM PDT 24
Peak memory 221928 kb
Host smart-25cf8c7f-c4c3-4a3a-96d9-8850f21f4e84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550860448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_e
rr.550860448
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3466709119
Short name T127
Test name
Test status
Simulation time 61137247 ps
CPU time 1.95 seconds
Started Jul 02 09:55:31 AM PDT 24
Finished Jul 02 09:55:43 AM PDT 24
Peak memory 221692 kb
Host smart-5e34d786-f22b-4736-91c7-5340283d4375
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466709119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.3466709119
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.4273091757
Short name T188
Test name
Test status
Simulation time 41252005 ps
CPU time 0.86 seconds
Started Jul 02 09:57:51 AM PDT 24
Finished Jul 02 09:57:55 AM PDT 24
Peak memory 208720 kb
Host smart-5d26313c-ea6b-4e43-89b4-14926893cf56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273091757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.4273091757
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.478517558
Short name T191
Test name
Test status
Simulation time 13744381 ps
CPU time 0.79 seconds
Started Jul 02 09:57:38 AM PDT 24
Finished Jul 02 09:57:41 AM PDT 24
Peak memory 209016 kb
Host smart-99110caa-409b-41f9-b6e1-3929797a7427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478517558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.478517558
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1017650875
Short name T192
Test name
Test status
Simulation time 13015738 ps
CPU time 1 seconds
Started Jul 02 09:57:50 AM PDT 24
Finished Jul 02 09:57:54 AM PDT 24
Peak memory 209176 kb
Host smart-dcb75c4e-f7c8-420e-90c7-55d676ebc8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017650875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1017650875
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.1427636903
Short name T190
Test name
Test status
Simulation time 27365315 ps
CPU time 0.85 seconds
Started Jul 02 09:58:14 AM PDT 24
Finished Jul 02 09:58:19 AM PDT 24
Peak memory 208780 kb
Host smart-a822ece2-d807-481b-8a7d-a3df181116dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427636903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.1427636903
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.413890167
Short name T898
Test name
Test status
Simulation time 451669000 ps
CPU time 11.08 seconds
Started Jul 02 09:55:01 AM PDT 24
Finished Jul 02 09:55:13 AM PDT 24
Peak memory 209056 kb
Host smart-e2d7cc50-e655-4b4f-b86c-dff5f4a6ce44
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413890167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.413890167
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2000891953
Short name T129
Test name
Test status
Simulation time 90919197 ps
CPU time 3.54 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:36 AM PDT 24
Peak memory 217572 kb
Host smart-baaac994-56b7-41a0-adf0-3af30413bd71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000891953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.2000891953
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1631696084
Short name T130
Test name
Test status
Simulation time 77458814 ps
CPU time 2.63 seconds
Started Jul 02 09:55:08 AM PDT 24
Finished Jul 02 09:55:12 AM PDT 24
Peak memory 217588 kb
Host smart-431aad35-a953-42a3-b6ef-14bc57bbbd44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631696084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.1631696084
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.427802675
Short name T131
Test name
Test status
Simulation time 128720850 ps
CPU time 2.6 seconds
Started Jul 02 09:55:20 AM PDT 24
Finished Jul 02 09:55:25 AM PDT 24
Peak memory 217552 kb
Host smart-c49fba31-c8a5-45df-8b7a-5eb6a047ad8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427802675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_e
rr.427802675
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3525118054
Short name T40
Test name
Test status
Simulation time 46176101864 ps
CPU time 151.29 seconds
Started Jul 02 09:59:01 AM PDT 24
Finished Jul 02 10:01:40 AM PDT 24
Peak memory 282924 kb
Host smart-8cd6b449-22c7-4f3d-b297-c5dc9eef473f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525118054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3525118054
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3828924587
Short name T21
Test name
Test status
Simulation time 1190250185 ps
CPU time 32.65 seconds
Started Jul 02 09:58:20 AM PDT 24
Finished Jul 02 09:58:54 AM PDT 24
Peak memory 267476 kb
Host smart-dd38f25e-92bf-41dc-ba99-f1b361efb56b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828924587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3828924587
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.3205510497
Short name T203
Test name
Test status
Simulation time 919505065 ps
CPU time 12.24 seconds
Started Jul 02 09:57:46 AM PDT 24
Finished Jul 02 09:58:06 AM PDT 24
Peak memory 225956 kb
Host smart-c0b7f795-04c6-4000-b5dd-b3198fd4a6ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205510497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.3205510497
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3401315329
Short name T985
Test name
Test status
Simulation time 93814837 ps
CPU time 1.65 seconds
Started Jul 02 09:55:01 AM PDT 24
Finished Jul 02 09:55:04 AM PDT 24
Peak memory 209324 kb
Host smart-b38d5036-40bc-4d67-b5e9-ed361b15f24b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401315329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.3401315329
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1794380925
Short name T930
Test name
Test status
Simulation time 241522567 ps
CPU time 2.6 seconds
Started Jul 02 09:55:16 AM PDT 24
Finished Jul 02 09:55:20 AM PDT 24
Peak memory 209272 kb
Host smart-de20dda2-1a67-449f-beec-643b6f9a22e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794380925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.1794380925
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2602247541
Short name T949
Test name
Test status
Simulation time 33791829 ps
CPU time 1.32 seconds
Started Jul 02 09:54:56 AM PDT 24
Finished Jul 02 09:54:59 AM PDT 24
Peak memory 211432 kb
Host smart-9d048dcd-2fe7-4228-9927-5527ba74160d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602247541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2602247541
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.357238440
Short name T927
Test name
Test status
Simulation time 367976540 ps
CPU time 1.38 seconds
Started Jul 02 09:55:12 AM PDT 24
Finished Jul 02 09:55:16 AM PDT 24
Peak memory 219060 kb
Host smart-4c8f9f0d-efce-4603-91c7-49180cb5db7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357238440 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.357238440
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2444390600
Short name T111
Test name
Test status
Simulation time 31443431 ps
CPU time 0.97 seconds
Started Jul 02 09:54:47 AM PDT 24
Finished Jul 02 09:54:49 AM PDT 24
Peak memory 209312 kb
Host smart-bde6a5dd-34de-4079-bdea-9efc096c06dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444390600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2444390600
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1752718078
Short name T881
Test name
Test status
Simulation time 212853686 ps
CPU time 1.19 seconds
Started Jul 02 09:54:43 AM PDT 24
Finished Jul 02 09:54:45 AM PDT 24
Peak memory 209184 kb
Host smart-ee25d20d-0493-437c-9db4-b7f88bb30530
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752718078 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1752718078
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2704205402
Short name T980
Test name
Test status
Simulation time 1811155956 ps
CPU time 11.14 seconds
Started Jul 02 09:55:02 AM PDT 24
Finished Jul 02 09:55:15 AM PDT 24
Peak memory 208796 kb
Host smart-05164a8a-a75a-43cf-8310-36eee52e6a94
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704205402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2704205402
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1787185712
Short name T937
Test name
Test status
Simulation time 262705404 ps
CPU time 1.37 seconds
Started Jul 02 09:55:14 AM PDT 24
Finished Jul 02 09:55:18 AM PDT 24
Peak memory 210680 kb
Host smart-6a2c5f9b-ac7a-438d-964b-47b506a1eb2c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787185712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1787185712
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3517680732
Short name T873
Test name
Test status
Simulation time 694311996 ps
CPU time 2.79 seconds
Started Jul 02 09:54:55 AM PDT 24
Finished Jul 02 09:55:00 AM PDT 24
Peak memory 218184 kb
Host smart-c3769b14-6a9d-4744-b149-afae7e60ca3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351768
0732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3517680732
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2545693954
Short name T901
Test name
Test status
Simulation time 175390434 ps
CPU time 1.87 seconds
Started Jul 02 09:54:42 AM PDT 24
Finished Jul 02 09:54:45 AM PDT 24
Peak memory 217440 kb
Host smart-c58ef0a7-2412-46b8-a2c8-7217f6c6af28
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545693954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2545693954
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3643853756
Short name T959
Test name
Test status
Simulation time 39459115 ps
CPU time 1.19 seconds
Started Jul 02 09:54:53 AM PDT 24
Finished Jul 02 09:54:56 AM PDT 24
Peak memory 209368 kb
Host smart-44220671-82dd-402d-81f0-f53ef1659162
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643853756 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.3643853756
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.59523375
Short name T945
Test name
Test status
Simulation time 39683886 ps
CPU time 1.43 seconds
Started Jul 02 09:54:46 AM PDT 24
Finished Jul 02 09:54:48 AM PDT 24
Peak memory 217528 kb
Host smart-fba44c3f-f279-43a4-99e5-775f7d8b6e3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59523375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.59523375
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2048190951
Short name T173
Test name
Test status
Simulation time 54512321 ps
CPU time 0.97 seconds
Started Jul 02 09:54:54 AM PDT 24
Finished Jul 02 09:54:57 AM PDT 24
Peak memory 209576 kb
Host smart-ed867601-6365-4b3c-97cb-8a0eb9ac4119
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048190951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.2048190951
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2585903931
Short name T863
Test name
Test status
Simulation time 28507471 ps
CPU time 1.82 seconds
Started Jul 02 09:54:49 AM PDT 24
Finished Jul 02 09:54:52 AM PDT 24
Peak memory 209312 kb
Host smart-2b603a5a-d8c7-4fd2-a862-443d2ee3b491
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585903931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2585903931
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.414719728
Short name T903
Test name
Test status
Simulation time 17674898 ps
CPU time 1 seconds
Started Jul 02 09:54:44 AM PDT 24
Finished Jul 02 09:54:46 AM PDT 24
Peak memory 210088 kb
Host smart-22ad9f03-5048-44b5-9c45-1b186b668015
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414719728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset
.414719728
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.794066897
Short name T886
Test name
Test status
Simulation time 21665017 ps
CPU time 1.47 seconds
Started Jul 02 09:55:02 AM PDT 24
Finished Jul 02 09:55:05 AM PDT 24
Peak memory 221644 kb
Host smart-f58def59-cea4-4fad-bac3-23f9c5e889aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794066897 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.794066897
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3031345129
Short name T179
Test name
Test status
Simulation time 19101574 ps
CPU time 0.88 seconds
Started Jul 02 09:54:52 AM PDT 24
Finished Jul 02 09:54:54 AM PDT 24
Peak memory 209352 kb
Host smart-a6e60965-1f68-4611-8a91-751227c15175
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031345129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.3031345129
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2307673023
Short name T884
Test name
Test status
Simulation time 531361910 ps
CPU time 1.23 seconds
Started Jul 02 09:54:48 AM PDT 24
Finished Jul 02 09:54:51 AM PDT 24
Peak memory 209188 kb
Host smart-6264429e-9899-4dc3-b2b6-6ecfc55bde05
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307673023 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2307673023
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.4189649166
Short name T136
Test name
Test status
Simulation time 591523694 ps
CPU time 8.95 seconds
Started Jul 02 09:55:06 AM PDT 24
Finished Jul 02 09:55:16 AM PDT 24
Peak memory 209088 kb
Host smart-0c229acd-7de8-46cb-98be-7c42903034e3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189649166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.4189649166
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1293819524
Short name T975
Test name
Test status
Simulation time 4972081566 ps
CPU time 15.74 seconds
Started Jul 02 09:55:09 AM PDT 24
Finished Jul 02 09:55:27 AM PDT 24
Peak memory 209372 kb
Host smart-57618d85-0d91-448d-a856-b0300f4f320f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293819524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1293819524
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3159743917
Short name T899
Test name
Test status
Simulation time 215370633 ps
CPU time 1.33 seconds
Started Jul 02 09:55:13 AM PDT 24
Finished Jul 02 09:55:16 AM PDT 24
Peak memory 217496 kb
Host smart-4ff8d304-7298-4253-956e-8644ac1e90b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159743917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.3159743917
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2757954449
Short name T989
Test name
Test status
Simulation time 221266159 ps
CPU time 3.1 seconds
Started Jul 02 09:54:59 AM PDT 24
Finished Jul 02 09:55:03 AM PDT 24
Peak memory 218584 kb
Host smart-adedaf99-6f74-4dc0-955d-b14f4c6889e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275795
4449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2757954449
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3161536310
Short name T868
Test name
Test status
Simulation time 57239478 ps
CPU time 1.78 seconds
Started Jul 02 09:55:14 AM PDT 24
Finished Jul 02 09:55:18 AM PDT 24
Peak memory 209260 kb
Host smart-87265184-8db9-4172-8a26-dfc3d9b9316c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161536310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.3161536310
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3408256540
Short name T112
Test name
Test status
Simulation time 17056154 ps
CPU time 1.01 seconds
Started Jul 02 09:54:57 AM PDT 24
Finished Jul 02 09:54:59 AM PDT 24
Peak memory 209304 kb
Host smart-790b6bf1-6032-4375-82d4-995738a4a5b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408256540 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.3408256540
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.4023756750
Short name T891
Test name
Test status
Simulation time 19818752 ps
CPU time 1.45 seconds
Started Jul 02 09:54:54 AM PDT 24
Finished Jul 02 09:54:57 AM PDT 24
Peak memory 209312 kb
Host smart-93bef5d9-d72d-4520-896f-bd7e8e18b672
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023756750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.4023756750
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.268412521
Short name T950
Test name
Test status
Simulation time 97077577 ps
CPU time 2.24 seconds
Started Jul 02 09:54:56 AM PDT 24
Finished Jul 02 09:55:00 AM PDT 24
Peak memory 217500 kb
Host smart-253f595d-5883-4748-80aa-01aaeceae516
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268412521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.268412521
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1627840147
Short name T123
Test name
Test status
Simulation time 206124244 ps
CPU time 1.93 seconds
Started Jul 02 09:54:53 AM PDT 24
Finished Jul 02 09:54:56 AM PDT 24
Peak memory 217508 kb
Host smart-5aca6938-0ab1-40ea-820b-d67c0c89792e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627840147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.1627840147
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.4152502249
Short name T935
Test name
Test status
Simulation time 91828592 ps
CPU time 1.01 seconds
Started Jul 02 09:55:18 AM PDT 24
Finished Jul 02 09:55:22 AM PDT 24
Peak memory 219748 kb
Host smart-31779e01-d5a9-4d49-bc5f-ba3f1e1a2024
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152502249 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.4152502249
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2650541604
Short name T931
Test name
Test status
Simulation time 14940429 ps
CPU time 0.88 seconds
Started Jul 02 09:55:07 AM PDT 24
Finished Jul 02 09:55:09 AM PDT 24
Peak memory 209248 kb
Host smart-2907a998-c9b7-4bf5-b3c8-96f207f108ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650541604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2650541604
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1582596023
Short name T887
Test name
Test status
Simulation time 105976683 ps
CPU time 1.22 seconds
Started Jul 02 09:55:11 AM PDT 24
Finished Jul 02 09:55:15 AM PDT 24
Peak memory 209316 kb
Host smart-0079bad0-d924-4f8d-b471-7144aefe2c1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582596023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.1582596023
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2927808572
Short name T955
Test name
Test status
Simulation time 41860548 ps
CPU time 3.07 seconds
Started Jul 02 09:55:11 AM PDT 24
Finished Jul 02 09:55:17 AM PDT 24
Peak memory 218520 kb
Host smart-0f630b9d-1c26-4ae2-ba3a-5f6133af1943
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927808572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2927808572
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1316504412
Short name T110
Test name
Test status
Simulation time 323067857 ps
CPU time 2.92 seconds
Started Jul 02 09:55:11 AM PDT 24
Finished Jul 02 09:55:16 AM PDT 24
Peak memory 217544 kb
Host smart-8327ed25-da86-48da-a066-c756de148ee7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316504412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1316504412
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.4280584843
Short name T114
Test name
Test status
Simulation time 36502089 ps
CPU time 1.49 seconds
Started Jul 02 09:55:09 AM PDT 24
Finished Jul 02 09:55:12 AM PDT 24
Peak memory 217628 kb
Host smart-4e78d80f-b61b-4930-80c1-67d2d61b0939
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280584843 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.4280584843
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3150252885
Short name T890
Test name
Test status
Simulation time 49653219 ps
CPU time 0.83 seconds
Started Jul 02 09:55:04 AM PDT 24
Finished Jul 02 09:55:06 AM PDT 24
Peak memory 208888 kb
Host smart-1dd5fb83-f716-435c-8c5a-71af1312b96b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150252885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3150252885
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.4171509550
Short name T932
Test name
Test status
Simulation time 128002647 ps
CPU time 1.37 seconds
Started Jul 02 09:55:19 AM PDT 24
Finished Jul 02 09:55:23 AM PDT 24
Peak memory 209356 kb
Host smart-502a7e3e-3f26-4ac3-8ad8-0e5fa7174743
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171509550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.4171509550
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2087439481
Short name T958
Test name
Test status
Simulation time 124758403 ps
CPU time 4.75 seconds
Started Jul 02 09:55:12 AM PDT 24
Finished Jul 02 09:55:19 AM PDT 24
Peak memory 217580 kb
Host smart-d8a05ce2-39a7-4f41-907f-fc59e917f434
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087439481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2087439481
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.195737735
Short name T116
Test name
Test status
Simulation time 219592414 ps
CPU time 3.04 seconds
Started Jul 02 09:55:17 AM PDT 24
Finished Jul 02 09:55:22 AM PDT 24
Peak memory 222272 kb
Host smart-6e116e19-0bfd-4adf-a3e7-8641e1339dfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195737735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_
err.195737735
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2110524905
Short name T913
Test name
Test status
Simulation time 60647733 ps
CPU time 1.02 seconds
Started Jul 02 09:55:20 AM PDT 24
Finished Jul 02 09:55:24 AM PDT 24
Peak memory 217524 kb
Host smart-6bb561fd-59cf-4e7c-8e25-8199a68c451d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110524905 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2110524905
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.4170012395
Short name T183
Test name
Test status
Simulation time 21253678 ps
CPU time 1.27 seconds
Started Jul 02 09:55:19 AM PDT 24
Finished Jul 02 09:55:23 AM PDT 24
Peak memory 209408 kb
Host smart-7b06210e-4271-44c3-9c4c-4e998a78884c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170012395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.4170012395
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3240485011
Short name T109
Test name
Test status
Simulation time 147907356 ps
CPU time 2.72 seconds
Started Jul 02 09:55:20 AM PDT 24
Finished Jul 02 09:55:25 AM PDT 24
Peak memory 217628 kb
Host smart-9014d7ba-46d2-4e4c-992c-1e880852da70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240485011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3240485011
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2413288120
Short name T194
Test name
Test status
Simulation time 1806678490 ps
CPU time 3.23 seconds
Started Jul 02 09:55:08 AM PDT 24
Finished Jul 02 09:55:13 AM PDT 24
Peak memory 217472 kb
Host smart-9192d2ee-7bb5-4668-8fb2-4debfc922acc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413288120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.2413288120
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.10907448
Short name T124
Test name
Test status
Simulation time 86881699 ps
CPU time 1.53 seconds
Started Jul 02 09:55:25 AM PDT 24
Finished Jul 02 09:55:40 AM PDT 24
Peak memory 218272 kb
Host smart-8073bd06-fdce-4120-b2d1-5ab91922a345
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10907448 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.10907448
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.734895090
Short name T172
Test name
Test status
Simulation time 18440127 ps
CPU time 0.9 seconds
Started Jul 02 09:55:16 AM PDT 24
Finished Jul 02 09:55:19 AM PDT 24
Peak memory 209328 kb
Host smart-e88468ee-ad81-4276-bd08-dd4b25fe2026
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734895090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.734895090
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2114482255
Short name T981
Test name
Test status
Simulation time 28503963 ps
CPU time 1.19 seconds
Started Jul 02 09:55:18 AM PDT 24
Finished Jul 02 09:55:22 AM PDT 24
Peak memory 209432 kb
Host smart-2abe386e-4eee-474d-8ce6-0ec3823a2527
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114482255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2114482255
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2731866855
Short name T988
Test name
Test status
Simulation time 136208138 ps
CPU time 2.12 seconds
Started Jul 02 09:55:21 AM PDT 24
Finished Jul 02 09:55:26 AM PDT 24
Peak memory 217460 kb
Host smart-6b3394d4-cc02-470c-8b49-d0ba337f78fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731866855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2731866855
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1875140361
Short name T904
Test name
Test status
Simulation time 212699372 ps
CPU time 2.03 seconds
Started Jul 02 09:55:17 AM PDT 24
Finished Jul 02 09:55:21 AM PDT 24
Peak memory 219380 kb
Host smart-e1fa7077-77f2-416f-bd9c-bf98e7f036ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875140361 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1875140361
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2487117577
Short name T177
Test name
Test status
Simulation time 12554101 ps
CPU time 0.87 seconds
Started Jul 02 09:55:18 AM PDT 24
Finished Jul 02 09:55:21 AM PDT 24
Peak memory 209276 kb
Host smart-bfed5c5b-8d3d-4ab2-bd70-d9e3d48b1e70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487117577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2487117577
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.27536250
Short name T956
Test name
Test status
Simulation time 47288397 ps
CPU time 1.16 seconds
Started Jul 02 09:55:12 AM PDT 24
Finished Jul 02 09:55:15 AM PDT 24
Peak memory 209332 kb
Host smart-f6581bf2-de1d-47c2-805b-677540ebbd02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27536250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
same_csr_outstanding.27536250
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3504664710
Short name T108
Test name
Test status
Simulation time 158256258 ps
CPU time 2.2 seconds
Started Jul 02 09:55:17 AM PDT 24
Finished Jul 02 09:55:22 AM PDT 24
Peak memory 217512 kb
Host smart-22dd5f39-246c-4fab-9e40-c61c72feb027
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504664710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3504664710
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1766796012
Short name T105
Test name
Test status
Simulation time 38014561 ps
CPU time 1.3 seconds
Started Jul 02 09:55:15 AM PDT 24
Finished Jul 02 09:55:19 AM PDT 24
Peak memory 218252 kb
Host smart-e36ab90d-4b3a-475b-95bf-d719c50ee819
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766796012 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.1766796012
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2858317066
Short name T977
Test name
Test status
Simulation time 105500824 ps
CPU time 0.8 seconds
Started Jul 02 09:55:23 AM PDT 24
Finished Jul 02 09:55:27 AM PDT 24
Peak memory 208904 kb
Host smart-d75885c9-699c-4db9-bb92-783d10b3b357
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858317066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2858317066
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3960088034
Short name T181
Test name
Test status
Simulation time 41728208 ps
CPU time 1.08 seconds
Started Jul 02 09:55:23 AM PDT 24
Finished Jul 02 09:55:28 AM PDT 24
Peak memory 209264 kb
Host smart-3a5c98d4-4340-4625-8608-94e71e5f3d36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960088034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.3960088034
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3282737403
Short name T984
Test name
Test status
Simulation time 164317400 ps
CPU time 3.36 seconds
Started Jul 02 09:55:18 AM PDT 24
Finished Jul 02 09:55:24 AM PDT 24
Peak memory 217576 kb
Host smart-bb71dbe2-53cc-4681-9335-379d2bd7a49b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282737403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.3282737403
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1236253881
Short name T193
Test name
Test status
Simulation time 182195023 ps
CPU time 1.9 seconds
Started Jul 02 09:55:27 AM PDT 24
Finished Jul 02 09:55:39 AM PDT 24
Peak memory 221736 kb
Host smart-37e8e710-9732-4d7d-9ca5-4f3ab6d523bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236253881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.1236253881
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1803316600
Short name T889
Test name
Test status
Simulation time 110273090 ps
CPU time 2.01 seconds
Started Jul 02 09:55:20 AM PDT 24
Finished Jul 02 09:55:25 AM PDT 24
Peak memory 219196 kb
Host smart-1a6f2502-2be5-462d-8fd2-0f8a16fab859
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803316600 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.1803316600
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.318113174
Short name T978
Test name
Test status
Simulation time 44333641 ps
CPU time 1.01 seconds
Started Jul 02 09:55:10 AM PDT 24
Finished Jul 02 09:55:13 AM PDT 24
Peak memory 209060 kb
Host smart-8e8af373-363d-4b6e-9167-cfb48e91cc46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318113174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.318113174
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2411862426
Short name T924
Test name
Test status
Simulation time 59390684 ps
CPU time 1.04 seconds
Started Jul 02 09:55:15 AM PDT 24
Finished Jul 02 09:55:18 AM PDT 24
Peak memory 217496 kb
Host smart-0c1bfe04-8697-4ad8-9a07-0a30000cf807
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411862426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2411862426
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3436792244
Short name T939
Test name
Test status
Simulation time 86028365 ps
CPU time 3.44 seconds
Started Jul 02 09:55:13 AM PDT 24
Finished Jul 02 09:55:19 AM PDT 24
Peak memory 217580 kb
Host smart-05d69ef4-f475-4be2-a5a5-a49a105c1db1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436792244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3436792244
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3865882382
Short name T878
Test name
Test status
Simulation time 16148837 ps
CPU time 1.2 seconds
Started Jul 02 09:55:18 AM PDT 24
Finished Jul 02 09:55:22 AM PDT 24
Peak memory 217660 kb
Host smart-2f357ab8-b7e2-48ac-9d45-cd8d28d541a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865882382 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3865882382
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2160491875
Short name T896
Test name
Test status
Simulation time 61321125 ps
CPU time 0.88 seconds
Started Jul 02 09:55:13 AM PDT 24
Finished Jul 02 09:55:17 AM PDT 24
Peak memory 209064 kb
Host smart-a57c9cae-9167-4a87-9216-2899eb059065
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160491875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2160491875
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.39868550
Short name T966
Test name
Test status
Simulation time 20709354 ps
CPU time 1.27 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:31 AM PDT 24
Peak memory 211464 kb
Host smart-0792625c-49ee-4e4a-bd96-5c862e5845dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39868550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
same_csr_outstanding.39868550
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2968940613
Short name T888
Test name
Test status
Simulation time 85958849 ps
CPU time 2.67 seconds
Started Jul 02 09:55:10 AM PDT 24
Finished Jul 02 09:55:15 AM PDT 24
Peak memory 217624 kb
Host smart-aef2c9e1-aa78-4a4c-ba6f-e9be404e6b38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968940613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2968940613
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3353585446
Short name T943
Test name
Test status
Simulation time 14821816 ps
CPU time 1.05 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:31 AM PDT 24
Peak memory 219012 kb
Host smart-cf89b2ec-f9c1-47d6-b594-56582d0956db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353585446 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.3353585446
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3490793659
Short name T944
Test name
Test status
Simulation time 64419142 ps
CPU time 0.91 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:33 AM PDT 24
Peak memory 209100 kb
Host smart-52db2f0c-51e2-4224-8035-72183c20d091
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490793659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3490793659
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2231455987
Short name T976
Test name
Test status
Simulation time 40681924 ps
CPU time 1.01 seconds
Started Jul 02 09:55:28 AM PDT 24
Finished Jul 02 09:55:39 AM PDT 24
Peak memory 209288 kb
Host smart-01f45885-e8e0-4b1c-abce-3dc7585f6891
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231455987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.2231455987
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2448992095
Short name T893
Test name
Test status
Simulation time 154632228 ps
CPU time 2.13 seconds
Started Jul 02 09:55:11 AM PDT 24
Finished Jul 02 09:55:15 AM PDT 24
Peak memory 217512 kb
Host smart-86779d6b-fd60-49a7-8c9b-0e91cd7d5c20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448992095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.2448992095
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.595707582
Short name T121
Test name
Test status
Simulation time 283802033 ps
CPU time 2.65 seconds
Started Jul 02 09:55:17 AM PDT 24
Finished Jul 02 09:55:21 AM PDT 24
Peak memory 222184 kb
Host smart-fff86839-4ced-4583-901d-f5bd6fbda539
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595707582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg_
err.595707582
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3480813500
Short name T126
Test name
Test status
Simulation time 27474357 ps
CPU time 1.25 seconds
Started Jul 02 09:55:18 AM PDT 24
Finished Jul 02 09:55:22 AM PDT 24
Peak memory 222168 kb
Host smart-a7e0f944-bd64-4bc0-a3b2-e443f978d71e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480813500 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3480813500
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.269583757
Short name T171
Test name
Test status
Simulation time 34080576 ps
CPU time 1 seconds
Started Jul 02 09:55:19 AM PDT 24
Finished Jul 02 09:55:22 AM PDT 24
Peak memory 217540 kb
Host smart-3538095c-a289-4254-81a1-b392a1347f96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269583757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.269583757
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3274774612
Short name T895
Test name
Test status
Simulation time 85740443 ps
CPU time 1.25 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:31 AM PDT 24
Peak memory 209448 kb
Host smart-c969c913-3319-4453-844a-afb03f373345
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274774612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3274774612
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2508084079
Short name T942
Test name
Test status
Simulation time 254986883 ps
CPU time 2.98 seconds
Started Jul 02 09:55:15 AM PDT 24
Finished Jul 02 09:55:20 AM PDT 24
Peak memory 217332 kb
Host smart-629d90d1-4f67-46ae-97e0-b582075fa4f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508084079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2508084079
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3171546545
Short name T905
Test name
Test status
Simulation time 766277699 ps
CPU time 1.76 seconds
Started Jul 02 09:55:16 AM PDT 24
Finished Jul 02 09:55:20 AM PDT 24
Peak memory 221464 kb
Host smart-f0cf8dfb-215a-4772-ac57-12b9d5ca8d1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171546545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.3171546545
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3528371378
Short name T861
Test name
Test status
Simulation time 61753887 ps
CPU time 1.36 seconds
Started Jul 02 09:54:48 AM PDT 24
Finished Jul 02 09:54:50 AM PDT 24
Peak memory 217432 kb
Host smart-872ee069-f942-4be2-88bb-2d52dad64fb7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528371378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.3528371378
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2777307203
Short name T970
Test name
Test status
Simulation time 19597376 ps
CPU time 1.18 seconds
Started Jul 02 09:54:59 AM PDT 24
Finished Jul 02 09:55:01 AM PDT 24
Peak memory 209204 kb
Host smart-f8969ff4-9480-4bef-865d-15c9035c4b66
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777307203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.2777307203
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.818050538
Short name T879
Test name
Test status
Simulation time 23956088 ps
CPU time 1.34 seconds
Started Jul 02 09:54:56 AM PDT 24
Finished Jul 02 09:54:59 AM PDT 24
Peak memory 211456 kb
Host smart-0a76a1a4-97e7-4d9d-8cdc-a5a283255bcc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818050538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_reset
.818050538
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1098641912
Short name T906
Test name
Test status
Simulation time 87531726 ps
CPU time 1.07 seconds
Started Jul 02 09:54:56 AM PDT 24
Finished Jul 02 09:54:59 AM PDT 24
Peak memory 217732 kb
Host smart-fb4df39e-d755-41c5-b830-271540b2ea75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098641912 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1098641912
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3093961463
Short name T176
Test name
Test status
Simulation time 37665137 ps
CPU time 0.83 seconds
Started Jul 02 09:55:04 AM PDT 24
Finished Jul 02 09:55:07 AM PDT 24
Peak memory 209256 kb
Host smart-c074b891-f326-4dd8-9f10-a5425dc1095e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093961463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3093961463
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1072168648
Short name T921
Test name
Test status
Simulation time 62871407 ps
CPU time 1.2 seconds
Started Jul 02 09:54:47 AM PDT 24
Finished Jul 02 09:54:50 AM PDT 24
Peak memory 209092 kb
Host smart-dccde05f-98f0-47e9-b2be-84e8b1edc45d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072168648 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1072168648
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1912594367
Short name T919
Test name
Test status
Simulation time 3091373839 ps
CPU time 6.17 seconds
Started Jul 02 09:55:11 AM PDT 24
Finished Jul 02 09:55:19 AM PDT 24
Peak memory 209372 kb
Host smart-b2901620-1b1a-4728-a5be-8d29625b61b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912594367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1912594367
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.307511246
Short name T947
Test name
Test status
Simulation time 5895421262 ps
CPU time 4.79 seconds
Started Jul 02 09:54:57 AM PDT 24
Finished Jul 02 09:55:03 AM PDT 24
Peak memory 209504 kb
Host smart-1c1bd01e-31d1-4aad-bf47-874b8ee29d50
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307511246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.307511246
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.348384972
Short name T867
Test name
Test status
Simulation time 544542137 ps
CPU time 1.29 seconds
Started Jul 02 09:55:02 AM PDT 24
Finished Jul 02 09:55:04 AM PDT 24
Peak memory 217392 kb
Host smart-d23a1ae7-97ad-45dd-8493-ced7e2023cf4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348384972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.348384972
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2709628296
Short name T882
Test name
Test status
Simulation time 685497376 ps
CPU time 3.83 seconds
Started Jul 02 09:54:53 AM PDT 24
Finished Jul 02 09:54:58 AM PDT 24
Peak memory 218712 kb
Host smart-bd675734-67f9-43dc-9d1b-6736439e91a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270962
8296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2709628296
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2835904590
Short name T920
Test name
Test status
Simulation time 180211089 ps
CPU time 1.14 seconds
Started Jul 02 09:54:47 AM PDT 24
Finished Jul 02 09:54:50 AM PDT 24
Peak memory 209276 kb
Host smart-417ba80f-36cb-4d62-bf26-4d21b4d46fe9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835904590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.2835904590
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1933557058
Short name T900
Test name
Test status
Simulation time 82556377 ps
CPU time 1.89 seconds
Started Jul 02 09:54:42 AM PDT 24
Finished Jul 02 09:54:45 AM PDT 24
Peak memory 217544 kb
Host smart-696e5535-c87a-4b19-b8a5-43eecbd1b045
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933557058 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1933557058
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1848923561
Short name T908
Test name
Test status
Simulation time 24203345 ps
CPU time 1.21 seconds
Started Jul 02 09:55:00 AM PDT 24
Finished Jul 02 09:55:02 AM PDT 24
Peak memory 217600 kb
Host smart-c39af3c9-faa7-4268-a3a0-bb80b1b32ff4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848923561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.1848923561
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.482528221
Short name T102
Test name
Test status
Simulation time 368136481 ps
CPU time 1.82 seconds
Started Jul 02 09:54:58 AM PDT 24
Finished Jul 02 09:55:01 AM PDT 24
Peak memory 217576 kb
Host smart-e402785e-e3c7-4312-83ac-c3fdfcf8add1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482528221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.482528221
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1190352713
Short name T132
Test name
Test status
Simulation time 801819963 ps
CPU time 4.21 seconds
Started Jul 02 09:55:04 AM PDT 24
Finished Jul 02 09:55:09 AM PDT 24
Peak memory 217608 kb
Host smart-3df80acc-f5a3-42c0-9949-0d776fea6c66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190352713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1190352713
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.4192317216
Short name T874
Test name
Test status
Simulation time 122154122 ps
CPU time 1.57 seconds
Started Jul 02 09:55:10 AM PDT 24
Finished Jul 02 09:55:14 AM PDT 24
Peak memory 209332 kb
Host smart-a8294426-7b0b-4843-bbd5-1196911a5716
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192317216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.4192317216
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.4281360792
Short name T929
Test name
Test status
Simulation time 66955973 ps
CPU time 1.18 seconds
Started Jul 02 09:55:11 AM PDT 24
Finished Jul 02 09:55:15 AM PDT 24
Peak memory 209300 kb
Host smart-c4236228-3d7c-4f7a-8841-a576b095d87d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281360792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.4281360792
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.861928909
Short name T118
Test name
Test status
Simulation time 17019170 ps
CPU time 0.93 seconds
Started Jul 02 09:55:02 AM PDT 24
Finished Jul 02 09:55:05 AM PDT 24
Peak memory 209920 kb
Host smart-02b34031-959a-4a79-a82e-888ef55b083d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861928909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_reset
.861928909
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.69029854
Short name T918
Test name
Test status
Simulation time 164266169 ps
CPU time 1.64 seconds
Started Jul 02 09:55:11 AM PDT 24
Finished Jul 02 09:55:15 AM PDT 24
Peak memory 217776 kb
Host smart-c13aedec-e4fb-4084-91bd-41ee8548d3ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69029854 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.69029854
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2718427277
Short name T912
Test name
Test status
Simulation time 109929350 ps
CPU time 0.92 seconds
Started Jul 02 09:55:09 AM PDT 24
Finished Jul 02 09:55:11 AM PDT 24
Peak memory 209356 kb
Host smart-7ecdf880-3e38-4cd2-915d-977f0e074384
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718427277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2718427277
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.881234657
Short name T869
Test name
Test status
Simulation time 64433449 ps
CPU time 1.33 seconds
Started Jul 02 09:55:10 AM PDT 24
Finished Jul 02 09:55:14 AM PDT 24
Peak memory 209116 kb
Host smart-ce0562dd-825a-48ae-b6a9-37a36db2ad26
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881234657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.lc_ctrl_jtag_alert_test.881234657
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.967065963
Short name T885
Test name
Test status
Simulation time 409489093 ps
CPU time 5.84 seconds
Started Jul 02 09:55:22 AM PDT 24
Finished Jul 02 09:55:31 AM PDT 24
Peak memory 217120 kb
Host smart-83fce73b-6e2d-4e78-9cb2-da85515da0fd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967065963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.967065963
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2527358151
Short name T948
Test name
Test status
Simulation time 1662819000 ps
CPU time 16.38 seconds
Started Jul 02 09:55:10 AM PDT 24
Finished Jul 02 09:55:28 AM PDT 24
Peak memory 217048 kb
Host smart-4bcc71ca-c3b4-4262-a16d-b6a7050fe1eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527358151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.2527358151
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.800575172
Short name T974
Test name
Test status
Simulation time 267559099 ps
CPU time 3.8 seconds
Started Jul 02 09:54:54 AM PDT 24
Finished Jul 02 09:54:59 AM PDT 24
Peak memory 210976 kb
Host smart-7f81946d-6484-489b-ac4b-d133754f818d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800575172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.800575172
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1248707892
Short name T986
Test name
Test status
Simulation time 804644780 ps
CPU time 1.97 seconds
Started Jul 02 09:54:55 AM PDT 24
Finished Jul 02 09:54:59 AM PDT 24
Peak memory 218612 kb
Host smart-0ce78cd7-88eb-4cd5-bd9a-1bbacfe57f02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124870
7892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1248707892
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2817904029
Short name T883
Test name
Test status
Simulation time 257005859 ps
CPU time 1.42 seconds
Started Jul 02 09:54:55 AM PDT 24
Finished Jul 02 09:54:58 AM PDT 24
Peak memory 217364 kb
Host smart-4a3a6aba-6908-47b2-912c-ebbeecb40b5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817904029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2817904029
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1530144456
Short name T972
Test name
Test status
Simulation time 65252195 ps
CPU time 1.38 seconds
Started Jul 02 09:54:53 AM PDT 24
Finished Jul 02 09:54:55 AM PDT 24
Peak memory 217584 kb
Host smart-954a9ca9-613a-4c52-9473-51bd915456bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530144456 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1530144456
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3013129347
Short name T923
Test name
Test status
Simulation time 45627932 ps
CPU time 1.5 seconds
Started Jul 02 09:55:04 AM PDT 24
Finished Jul 02 09:55:13 AM PDT 24
Peak memory 217624 kb
Host smart-e2d7be71-5191-43d9-ba23-5c119b615fba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013129347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.3013129347
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3440553558
Short name T914
Test name
Test status
Simulation time 48089009 ps
CPU time 2.89 seconds
Started Jul 02 09:54:58 AM PDT 24
Finished Jul 02 09:55:02 AM PDT 24
Peak memory 217928 kb
Host smart-9fe28c6b-7da0-4d0b-8fc0-a1e96a68666a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440553558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.3440553558
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2900556705
Short name T862
Test name
Test status
Simulation time 20376731 ps
CPU time 1.14 seconds
Started Jul 02 09:55:07 AM PDT 24
Finished Jul 02 09:55:09 AM PDT 24
Peak memory 209332 kb
Host smart-acc884ef-3fdb-4f7e-80a8-f787d7154bbf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900556705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2900556705
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.181815054
Short name T926
Test name
Test status
Simulation time 56681706 ps
CPU time 2.11 seconds
Started Jul 02 09:55:09 AM PDT 24
Finished Jul 02 09:55:13 AM PDT 24
Peak memory 209296 kb
Host smart-f91fd43c-b051-4a12-9915-5145837391c4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181815054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash
.181815054
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2340669576
Short name T917
Test name
Test status
Simulation time 13142335 ps
CPU time 1.08 seconds
Started Jul 02 09:55:08 AM PDT 24
Finished Jul 02 09:55:09 AM PDT 24
Peak memory 209896 kb
Host smart-c0379a35-edf6-432c-a3cf-f89bdfdc22cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340669576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.2340669576
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1001926150
Short name T954
Test name
Test status
Simulation time 114481761 ps
CPU time 1.79 seconds
Started Jul 02 09:55:10 AM PDT 24
Finished Jul 02 09:55:15 AM PDT 24
Peak memory 217616 kb
Host smart-bbf30c41-b4aa-48b5-9eb2-7ae2e72d50a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001926150 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1001926150
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3931492212
Short name T865
Test name
Test status
Simulation time 22319045 ps
CPU time 0.95 seconds
Started Jul 02 09:55:09 AM PDT 24
Finished Jul 02 09:55:11 AM PDT 24
Peak memory 209356 kb
Host smart-a4308359-a0d2-411f-9ba7-04f38ae4569d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931492212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3931492212
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3751073558
Short name T907
Test name
Test status
Simulation time 49399776 ps
CPU time 1.18 seconds
Started Jul 02 09:55:11 AM PDT 24
Finished Jul 02 09:55:15 AM PDT 24
Peak memory 209164 kb
Host smart-d087078f-3ae1-4c77-800a-9c97c19a1a46
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751073558 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3751073558
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2546367410
Short name T922
Test name
Test status
Simulation time 385258912 ps
CPU time 2.97 seconds
Started Jul 02 09:55:02 AM PDT 24
Finished Jul 02 09:55:11 AM PDT 24
Peak memory 208992 kb
Host smart-bb9b5824-367a-4a9a-ac98-e33daebd1894
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546367410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2546367410
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3675750613
Short name T877
Test name
Test status
Simulation time 4828877726 ps
CPU time 49.57 seconds
Started Jul 02 09:55:08 AM PDT 24
Finished Jul 02 09:55:59 AM PDT 24
Peak memory 209340 kb
Host smart-26a1c1d7-40a0-40c3-9f03-6ee76baa4580
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675750613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3675750613
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.296237844
Short name T134
Test name
Test status
Simulation time 472672427 ps
CPU time 3.02 seconds
Started Jul 02 09:55:01 AM PDT 24
Finished Jul 02 09:55:05 AM PDT 24
Peak memory 217420 kb
Host smart-0e8b9a06-7566-439c-a581-4f5c3f9d2502
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296237844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.296237844
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1294905839
Short name T951
Test name
Test status
Simulation time 193370406 ps
CPU time 1.82 seconds
Started Jul 02 09:55:08 AM PDT 24
Finished Jul 02 09:55:11 AM PDT 24
Peak memory 217656 kb
Host smart-c6577fc6-b232-49dc-ab13-0a96101f0820
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129490
5839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1294905839
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2109112208
Short name T962
Test name
Test status
Simulation time 309343935 ps
CPU time 1.58 seconds
Started Jul 02 09:55:02 AM PDT 24
Finished Jul 02 09:55:05 AM PDT 24
Peak memory 217320 kb
Host smart-18cf3978-47e2-4770-ab52-3831e332aa22
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109112208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.2109112208
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.977824006
Short name T915
Test name
Test status
Simulation time 168163029 ps
CPU time 1.76 seconds
Started Jul 02 09:55:17 AM PDT 24
Finished Jul 02 09:55:27 AM PDT 24
Peak memory 217580 kb
Host smart-1b0f7488-b2d0-4abf-b193-7b38b9823f1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977824006 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.977824006
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1330686615
Short name T185
Test name
Test status
Simulation time 28446401 ps
CPU time 1.1 seconds
Started Jul 02 09:55:02 AM PDT 24
Finished Jul 02 09:55:04 AM PDT 24
Peak memory 209468 kb
Host smart-0d105829-00b8-4a43-8c0c-d4f8c423cb23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330686615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1330686615
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1394935167
Short name T971
Test name
Test status
Simulation time 205635480 ps
CPU time 2.26 seconds
Started Jul 02 09:55:11 AM PDT 24
Finished Jul 02 09:55:15 AM PDT 24
Peak memory 217484 kb
Host smart-fc5abbab-d423-4628-98e5-121cbcbf14ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394935167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1394935167
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.112183242
Short name T125
Test name
Test status
Simulation time 69650562 ps
CPU time 1.09 seconds
Started Jul 02 09:55:03 AM PDT 24
Finished Jul 02 09:55:06 AM PDT 24
Peak memory 218704 kb
Host smart-3e0046d0-8bb3-4c0a-8ea3-3879e3864ba4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112183242 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.112183242
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1970640786
Short name T170
Test name
Test status
Simulation time 13863053 ps
CPU time 0.87 seconds
Started Jul 02 09:54:58 AM PDT 24
Finished Jul 02 09:55:00 AM PDT 24
Peak memory 208672 kb
Host smart-7e11d1fd-46c8-4bd8-aba7-03daa6b503d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970640786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1970640786
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3332195221
Short name T964
Test name
Test status
Simulation time 40591285 ps
CPU time 1.2 seconds
Started Jul 02 09:55:08 AM PDT 24
Finished Jul 02 09:55:10 AM PDT 24
Peak memory 208684 kb
Host smart-b1fa28a0-3049-4bf0-88e9-6213f945913f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332195221 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.3332195221
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.415286150
Short name T961
Test name
Test status
Simulation time 1021094111 ps
CPU time 12.9 seconds
Started Jul 02 09:55:13 AM PDT 24
Finished Jul 02 09:55:28 AM PDT 24
Peak memory 209188 kb
Host smart-52765a1b-1fc7-4286-99e4-4a1e4f30c62d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415286150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.415286150
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2667787437
Short name T946
Test name
Test status
Simulation time 2063956107 ps
CPU time 10.62 seconds
Started Jul 02 09:55:05 AM PDT 24
Finished Jul 02 09:55:17 AM PDT 24
Peak memory 209300 kb
Host smart-40904ac9-9438-4e39-9917-d2b5ecaf8972
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667787437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2667787437
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1879277336
Short name T897
Test name
Test status
Simulation time 2608417341 ps
CPU time 2.14 seconds
Started Jul 02 09:55:10 AM PDT 24
Finished Jul 02 09:55:15 AM PDT 24
Peak memory 217536 kb
Host smart-75b2e213-d17f-48cc-88cb-c5602f9ad042
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879277336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.1879277336
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.447556531
Short name T870
Test name
Test status
Simulation time 116332661 ps
CPU time 1.71 seconds
Started Jul 02 09:55:11 AM PDT 24
Finished Jul 02 09:55:15 AM PDT 24
Peak memory 209292 kb
Host smart-50efe7d1-4565-422f-93db-e414dafbc793
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447556531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.447556531
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1091849693
Short name T892
Test name
Test status
Simulation time 15414535 ps
CPU time 1.18 seconds
Started Jul 02 09:55:10 AM PDT 24
Finished Jul 02 09:55:14 AM PDT 24
Peak memory 209440 kb
Host smart-0a292e43-4556-4ecf-bb31-18b011c0225e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091849693 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.1091849693
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3301360536
Short name T875
Test name
Test status
Simulation time 44934338 ps
CPU time 0.99 seconds
Started Jul 02 09:55:03 AM PDT 24
Finished Jul 02 09:55:06 AM PDT 24
Peak memory 209432 kb
Host smart-1cce94c8-87aa-435d-a8ad-b215064f8b67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301360536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.3301360536
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.265980870
Short name T902
Test name
Test status
Simulation time 152526198 ps
CPU time 3.92 seconds
Started Jul 02 09:55:07 AM PDT 24
Finished Jul 02 09:55:11 AM PDT 24
Peak memory 217500 kb
Host smart-d9d4891f-57c3-414a-a0bf-2d46a5c043f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265980870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.265980870
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2259729345
Short name T940
Test name
Test status
Simulation time 70312445 ps
CPU time 1.12 seconds
Started Jul 02 09:55:21 AM PDT 24
Finished Jul 02 09:55:25 AM PDT 24
Peak memory 219572 kb
Host smart-3e27f0ae-6327-49e3-8f55-f41ec8a722f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259729345 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2259729345
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3472671842
Short name T968
Test name
Test status
Simulation time 13808502 ps
CPU time 0.88 seconds
Started Jul 02 09:55:10 AM PDT 24
Finished Jul 02 09:55:13 AM PDT 24
Peak memory 209336 kb
Host smart-61032c0f-5346-4f71-b5e9-b86794253465
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472671842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3472671842
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1345639381
Short name T952
Test name
Test status
Simulation time 27547926 ps
CPU time 1.02 seconds
Started Jul 02 09:54:56 AM PDT 24
Finished Jul 02 09:54:59 AM PDT 24
Peak memory 209124 kb
Host smart-3df812e0-91f8-4712-b45c-f7151c6455a1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345639381 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1345639381
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3481260670
Short name T987
Test name
Test status
Simulation time 448168159 ps
CPU time 6.9 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:38 AM PDT 24
Peak memory 217080 kb
Host smart-c7f7919f-a624-416d-9bd0-06bd4a1995b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481260670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3481260670
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2877684689
Short name T979
Test name
Test status
Simulation time 2467275436 ps
CPU time 11.76 seconds
Started Jul 02 09:55:02 AM PDT 24
Finished Jul 02 09:55:16 AM PDT 24
Peak memory 209296 kb
Host smart-4246c439-bd52-43b9-9157-e4e6239abe58
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877684689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.2877684689
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2672282501
Short name T894
Test name
Test status
Simulation time 79802259 ps
CPU time 2.51 seconds
Started Jul 02 09:55:14 AM PDT 24
Finished Jul 02 09:55:19 AM PDT 24
Peak memory 210764 kb
Host smart-3ff2a982-bec4-4d06-896b-d50414a699dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672282501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2672282501
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1466829542
Short name T963
Test name
Test status
Simulation time 722262715 ps
CPU time 4.91 seconds
Started Jul 02 09:54:58 AM PDT 24
Finished Jul 02 09:55:04 AM PDT 24
Peak memory 218584 kb
Host smart-c77fb8e5-a513-4224-a7dc-8a1172d78939
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146682
9542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1466829542
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3057664969
Short name T135
Test name
Test status
Simulation time 411597983 ps
CPU time 1.85 seconds
Started Jul 02 09:54:54 AM PDT 24
Finished Jul 02 09:54:57 AM PDT 24
Peak memory 217312 kb
Host smart-bfde2704-f049-4a5f-8f3c-42cc24933399
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057664969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.3057664969
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1915532224
Short name T178
Test name
Test status
Simulation time 21385788 ps
CPU time 1.01 seconds
Started Jul 02 09:55:00 AM PDT 24
Finished Jul 02 09:55:07 AM PDT 24
Peak memory 217600 kb
Host smart-ae0e3b20-794e-407d-91ac-d112dbafc89c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915532224 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1915532224
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.769737366
Short name T910
Test name
Test status
Simulation time 14427313 ps
CPU time 0.98 seconds
Started Jul 02 09:55:20 AM PDT 24
Finished Jul 02 09:55:24 AM PDT 24
Peak memory 209360 kb
Host smart-dcb39c38-253b-48ba-9576-9732a5132f00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769737366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
same_csr_outstanding.769737366
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.4060665888
Short name T104
Test name
Test status
Simulation time 80722174 ps
CPU time 2.03 seconds
Started Jul 02 09:55:11 AM PDT 24
Finished Jul 02 09:55:15 AM PDT 24
Peak memory 217584 kb
Host smart-a7185d55-1043-49dc-b564-70e733ec9a16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060665888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.4060665888
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3399907688
Short name T115
Test name
Test status
Simulation time 62449913 ps
CPU time 2.22 seconds
Started Jul 02 09:55:13 AM PDT 24
Finished Jul 02 09:55:18 AM PDT 24
Peak memory 221948 kb
Host smart-4510a722-9bd2-44d6-b4e7-186f8eeb1089
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399907688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.3399907688
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.215153814
Short name T928
Test name
Test status
Simulation time 29756380 ps
CPU time 2.11 seconds
Started Jul 02 09:55:01 AM PDT 24
Finished Jul 02 09:55:04 AM PDT 24
Peak memory 223072 kb
Host smart-627395d4-7a9c-4e91-bb56-22040ea45e6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215153814 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.215153814
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1768058303
Short name T933
Test name
Test status
Simulation time 69621274 ps
CPU time 0.86 seconds
Started Jul 02 09:55:11 AM PDT 24
Finished Jul 02 09:55:14 AM PDT 24
Peak memory 208996 kb
Host smart-25f3196b-6b38-4582-aef2-f0b81d938794
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768058303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1768058303
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1019520242
Short name T953
Test name
Test status
Simulation time 39816597 ps
CPU time 1.23 seconds
Started Jul 02 09:55:02 AM PDT 24
Finished Jul 02 09:55:05 AM PDT 24
Peak memory 209188 kb
Host smart-efc33a98-b647-4fa1-b25b-2f37316f72d9
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019520242 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1019520242
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.204349906
Short name T880
Test name
Test status
Simulation time 861441393 ps
CPU time 2.84 seconds
Started Jul 02 09:55:11 AM PDT 24
Finished Jul 02 09:55:17 AM PDT 24
Peak memory 209100 kb
Host smart-5231073c-9098-4d2e-ab46-29543fc33f3f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204349906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.204349906
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.754983228
Short name T973
Test name
Test status
Simulation time 2851903073 ps
CPU time 11.18 seconds
Started Jul 02 09:55:13 AM PDT 24
Finished Jul 02 09:55:27 AM PDT 24
Peak memory 209272 kb
Host smart-dd4716d9-9e17-452c-b52a-6cb2fff359b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754983228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.754983228
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2431078179
Short name T960
Test name
Test status
Simulation time 450072771 ps
CPU time 3.2 seconds
Started Jul 02 09:55:15 AM PDT 24
Finished Jul 02 09:55:20 AM PDT 24
Peak memory 211032 kb
Host smart-8bd88a02-a29a-4df1-8a3b-331bf903b7ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431078179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2431078179
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.516306300
Short name T876
Test name
Test status
Simulation time 97480006 ps
CPU time 1.95 seconds
Started Jul 02 09:55:09 AM PDT 24
Finished Jul 02 09:55:12 AM PDT 24
Peak memory 219152 kb
Host smart-940fea62-d4fd-4dd3-a93e-557a50cfa7d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516306
300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.516306300
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.269700040
Short name T138
Test name
Test status
Simulation time 904527933 ps
CPU time 3.25 seconds
Started Jul 02 09:55:10 AM PDT 24
Finished Jul 02 09:55:15 AM PDT 24
Peak memory 209288 kb
Host smart-516f40ca-ff3d-43c5-9cc8-e1099f6115cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269700040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.269700040
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.4051040563
Short name T938
Test name
Test status
Simulation time 58627732 ps
CPU time 0.95 seconds
Started Jul 02 09:54:59 AM PDT 24
Finished Jul 02 09:55:01 AM PDT 24
Peak memory 209388 kb
Host smart-08f87e48-8aa6-479d-aa8d-4932124c32e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051040563 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.4051040563
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.279094747
Short name T182
Test name
Test status
Simulation time 163472189 ps
CPU time 2.05 seconds
Started Jul 02 09:55:08 AM PDT 24
Finished Jul 02 09:55:11 AM PDT 24
Peak memory 217560 kb
Host smart-d72b83dd-d40e-436b-9f83-4666e8ebf8f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279094747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
same_csr_outstanding.279094747
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1576596408
Short name T911
Test name
Test status
Simulation time 297737020 ps
CPU time 2.59 seconds
Started Jul 02 09:55:05 AM PDT 24
Finished Jul 02 09:55:08 AM PDT 24
Peak memory 217556 kb
Host smart-6603a25a-1f2a-4876-8bd4-01d77cb8fbde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576596408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1576596408
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1569707677
Short name T936
Test name
Test status
Simulation time 64672697 ps
CPU time 1.23 seconds
Started Jul 02 09:55:14 AM PDT 24
Finished Jul 02 09:55:17 AM PDT 24
Peak memory 218008 kb
Host smart-b11ee5e7-5f6a-443c-837a-ee55f14f30c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569707677 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1569707677
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2687126850
Short name T174
Test name
Test status
Simulation time 181988089 ps
CPU time 0.85 seconds
Started Jul 02 09:55:20 AM PDT 24
Finished Jul 02 09:55:24 AM PDT 24
Peak memory 209296 kb
Host smart-0f16578b-7171-4d09-912c-7b9e0b1361de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687126850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2687126850
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1966637578
Short name T864
Test name
Test status
Simulation time 77222319 ps
CPU time 2.57 seconds
Started Jul 02 09:55:18 AM PDT 24
Finished Jul 02 09:55:23 AM PDT 24
Peak memory 209192 kb
Host smart-e405f5cf-5815-4c51-9225-75c545fc623d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966637578 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.1966637578
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3645588670
Short name T872
Test name
Test status
Simulation time 1100735727 ps
CPU time 13.49 seconds
Started Jul 02 09:55:11 AM PDT 24
Finished Jul 02 09:55:27 AM PDT 24
Peak memory 208972 kb
Host smart-67fee7fc-5ba2-48dc-929a-6b5941961d1b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645588670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3645588670
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1367221635
Short name T139
Test name
Test status
Simulation time 2370988324 ps
CPU time 23.4 seconds
Started Jul 02 09:55:10 AM PDT 24
Finished Jul 02 09:55:35 AM PDT 24
Peak memory 209376 kb
Host smart-420ec72b-d843-49f3-bbed-efd6754db5c4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367221635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.1367221635
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.838276832
Short name T916
Test name
Test status
Simulation time 237892765 ps
CPU time 1.62 seconds
Started Jul 02 09:55:19 AM PDT 24
Finished Jul 02 09:55:24 AM PDT 24
Peak memory 210676 kb
Host smart-d2eb94c0-ffdd-440e-ac05-9877fa7dcd94
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838276832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.838276832
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1730618634
Short name T965
Test name
Test status
Simulation time 210982696 ps
CPU time 1.92 seconds
Started Jul 02 09:55:06 AM PDT 24
Finished Jul 02 09:55:09 AM PDT 24
Peak memory 219316 kb
Host smart-5a6174cf-dc5f-4af6-bcbd-85769715b4ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173061
8634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1730618634
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.4284071869
Short name T137
Test name
Test status
Simulation time 188304901 ps
CPU time 1.46 seconds
Started Jul 02 09:55:16 AM PDT 24
Finished Jul 02 09:55:20 AM PDT 24
Peak memory 209060 kb
Host smart-1859d529-eccb-49f4-8483-717f37beec96
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284071869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.4284071869
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.414310330
Short name T925
Test name
Test status
Simulation time 14910450 ps
CPU time 1.18 seconds
Started Jul 02 09:55:11 AM PDT 24
Finished Jul 02 09:55:15 AM PDT 24
Peak memory 209352 kb
Host smart-15d3be3b-042d-433d-a3f7-dbb40341ee86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414310330 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.414310330
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2806949875
Short name T180
Test name
Test status
Simulation time 186797232 ps
CPU time 1.1 seconds
Started Jul 02 09:55:04 AM PDT 24
Finished Jul 02 09:55:07 AM PDT 24
Peak memory 209336 kb
Host smart-754d0c11-d0bb-4009-8aee-c2ba7b30c237
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806949875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.2806949875
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3530736439
Short name T941
Test name
Test status
Simulation time 70320078 ps
CPU time 1.55 seconds
Started Jul 02 09:55:10 AM PDT 24
Finished Jul 02 09:55:13 AM PDT 24
Peak memory 217808 kb
Host smart-bab8176b-3bc8-4f24-913f-6a77a3fb2219
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530736439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3530736439
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.458770722
Short name T120
Test name
Test status
Simulation time 147744075 ps
CPU time 3.01 seconds
Started Jul 02 09:55:10 AM PDT 24
Finished Jul 02 09:55:15 AM PDT 24
Peak memory 222532 kb
Host smart-643fa300-5b8b-48d4-ba10-56b2bde0b6ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458770722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_e
rr.458770722
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2414023300
Short name T967
Test name
Test status
Simulation time 68382697 ps
CPU time 1.27 seconds
Started Jul 02 09:55:25 AM PDT 24
Finished Jul 02 09:55:35 AM PDT 24
Peak memory 217552 kb
Host smart-2381a981-c636-4ae9-8512-2a580f09fd2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414023300 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2414023300
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3189834230
Short name T934
Test name
Test status
Simulation time 182855465 ps
CPU time 0.85 seconds
Started Jul 02 09:55:17 AM PDT 24
Finished Jul 02 09:55:20 AM PDT 24
Peak memory 209356 kb
Host smart-8df31918-7afc-48ce-8437-bf3e1e0b6514
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189834230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3189834230
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2795522073
Short name T871
Test name
Test status
Simulation time 165323152 ps
CPU time 1.2 seconds
Started Jul 02 09:55:09 AM PDT 24
Finished Jul 02 09:55:11 AM PDT 24
Peak memory 208620 kb
Host smart-b9aa2d6a-2ea3-4210-a3bb-9a7b7ab11932
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795522073 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2795522073
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1676666808
Short name T909
Test name
Test status
Simulation time 949152914 ps
CPU time 10.63 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:43 AM PDT 24
Peak memory 208976 kb
Host smart-7523f5a0-d73f-4410-bb88-e6d7dbd64124
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676666808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1676666808
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3749750851
Short name T969
Test name
Test status
Simulation time 352415524 ps
CPU time 9.24 seconds
Started Jul 02 09:55:24 AM PDT 24
Finished Jul 02 09:55:46 AM PDT 24
Peak memory 209264 kb
Host smart-c04b2469-9e8d-45b3-9b61-4874181252a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749750851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.3749750851
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2217306494
Short name T957
Test name
Test status
Simulation time 200311077 ps
CPU time 2.05 seconds
Started Jul 02 09:55:11 AM PDT 24
Finished Jul 02 09:55:15 AM PDT 24
Peak memory 210804 kb
Host smart-450f4b93-018f-428e-99fb-a585966208cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217306494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2217306494
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.646185350
Short name T983
Test name
Test status
Simulation time 405662710 ps
CPU time 1.97 seconds
Started Jul 02 09:55:03 AM PDT 24
Finished Jul 02 09:55:07 AM PDT 24
Peak memory 217628 kb
Host smart-5bbabd4e-330b-477b-9946-3978438e88a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646185
350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.646185350
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3111157876
Short name T866
Test name
Test status
Simulation time 37862385 ps
CPU time 1.16 seconds
Started Jul 02 09:55:08 AM PDT 24
Finished Jul 02 09:55:10 AM PDT 24
Peak memory 209288 kb
Host smart-d63a2e8b-be27-41e9-802e-4511655e81a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111157876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3111157876
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3507491835
Short name T982
Test name
Test status
Simulation time 32247691 ps
CPU time 1.19 seconds
Started Jul 02 09:55:14 AM PDT 24
Finished Jul 02 09:55:18 AM PDT 24
Peak memory 209336 kb
Host smart-9789f853-1b10-4e96-8141-0ab94670a76e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507491835 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3507491835
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1127299936
Short name T184
Test name
Test status
Simulation time 161776408 ps
CPU time 1.46 seconds
Started Jul 02 09:55:19 AM PDT 24
Finished Jul 02 09:55:23 AM PDT 24
Peak memory 211308 kb
Host smart-c8dcae8a-6a07-45ef-bea6-f903e3760acd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127299936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.1127299936
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.2653176641
Short name T163
Test name
Test status
Simulation time 20396875 ps
CPU time 0.92 seconds
Started Jul 02 09:57:52 AM PDT 24
Finished Jul 02 09:57:56 AM PDT 24
Peak memory 208944 kb
Host smart-331c1fe3-c970-4d46-9a7b-915ebf93f845
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653176641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2653176641
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.1028001300
Short name T33
Test name
Test status
Simulation time 35559267 ps
CPU time 0.79 seconds
Started Jul 02 09:57:31 AM PDT 24
Finished Jul 02 09:57:33 AM PDT 24
Peak memory 208912 kb
Host smart-cef50608-ed4e-4c7b-910d-2c8087840333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028001300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1028001300
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1809834897
Short name T376
Test name
Test status
Simulation time 1566691103 ps
CPU time 12.42 seconds
Started Jul 02 09:57:46 AM PDT 24
Finished Jul 02 09:58:00 AM PDT 24
Peak memory 225964 kb
Host smart-71459dc9-dc0e-43d6-8bc9-d385f2fc6f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809834897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1809834897
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.1367700947
Short name T276
Test name
Test status
Simulation time 2521687287 ps
CPU time 17.16 seconds
Started Jul 02 09:57:42 AM PDT 24
Finished Jul 02 09:58:01 AM PDT 24
Peak memory 217700 kb
Host smart-18b6549e-7f83-4a1c-a1d2-7d702f42b93a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367700947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.1367700947
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3866341218
Short name T466
Test name
Test status
Simulation time 13370330004 ps
CPU time 92.32 seconds
Started Jul 02 09:57:30 AM PDT 24
Finished Jul 02 09:59:04 AM PDT 24
Peak memory 218940 kb
Host smart-1ca38075-4bb7-4ecc-917d-6ea3dc629cc5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866341218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3866341218
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.489293517
Short name T448
Test name
Test status
Simulation time 118949907 ps
CPU time 2.33 seconds
Started Jul 02 09:57:43 AM PDT 24
Finished Jul 02 09:57:47 AM PDT 24
Peak memory 217776 kb
Host smart-2a61b1dc-a8f5-47ea-8bb0-c87687c0f0f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489293517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.489293517
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.1620407885
Short name T258
Test name
Test status
Simulation time 425395540 ps
CPU time 2.58 seconds
Started Jul 02 09:57:47 AM PDT 24
Finished Jul 02 09:57:51 AM PDT 24
Peak memory 218220 kb
Host smart-575c8645-566b-49c8-9cc5-d619a39f791a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620407885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.1620407885
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2709094835
Short name T23
Test name
Test status
Simulation time 1310536536 ps
CPU time 10.08 seconds
Started Jul 02 09:57:50 AM PDT 24
Finished Jul 02 09:58:02 AM PDT 24
Peak memory 217632 kb
Host smart-448e4cc7-e1d7-45b4-90db-240bf3c05322
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709094835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.2709094835
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.361523632
Short name T309
Test name
Test status
Simulation time 900809685 ps
CPU time 5.14 seconds
Started Jul 02 09:57:37 AM PDT 24
Finished Jul 02 09:57:45 AM PDT 24
Peak memory 217684 kb
Host smart-1a63aa7b-bad7-4b7d-a10c-4b7c850ab7c2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361523632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.361523632
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.2095732195
Short name T392
Test name
Test status
Simulation time 5945157517 ps
CPU time 57.3 seconds
Started Jul 02 09:57:49 AM PDT 24
Finished Jul 02 09:58:49 AM PDT 24
Peak memory 250992 kb
Host smart-dec34ffa-a3c5-42b5-b450-75244f9cf8d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095732195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.2095732195
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.734345136
Short name T673
Test name
Test status
Simulation time 761198062 ps
CPU time 10.12 seconds
Started Jul 02 09:57:44 AM PDT 24
Finished Jul 02 09:57:56 AM PDT 24
Peak memory 247620 kb
Host smart-bc92e024-5075-4b49-821e-d97b5eb37c39
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734345136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.734345136
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.23183413
Short name T260
Test name
Test status
Simulation time 430448207 ps
CPU time 2.76 seconds
Started Jul 02 09:57:42 AM PDT 24
Finished Jul 02 09:57:46 AM PDT 24
Peak memory 218220 kb
Host smart-7662e82a-d781-4e3e-8340-1ae09978824a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23183413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.23183413
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3621887203
Short name T75
Test name
Test status
Simulation time 616023543 ps
CPU time 10.53 seconds
Started Jul 02 09:57:48 AM PDT 24
Finished Jul 02 09:58:01 AM PDT 24
Peak memory 214096 kb
Host smart-87c323c5-db7d-4f83-90c0-70c53fb3a077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621887203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3621887203
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2919297505
Short name T88
Test name
Test status
Simulation time 865336211 ps
CPU time 35.73 seconds
Started Jul 02 09:57:31 AM PDT 24
Finished Jul 02 09:58:09 AM PDT 24
Peak memory 270576 kb
Host smart-18dd615e-2697-4987-92b5-c3034f3f4f90
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919297505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2919297505
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.2328370767
Short name T348
Test name
Test status
Simulation time 1122680717 ps
CPU time 13.09 seconds
Started Jul 02 09:57:47 AM PDT 24
Finished Jul 02 09:58:02 AM PDT 24
Peak memory 226028 kb
Host smart-52e17e63-69b3-46e7-993a-062063c1c935
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328370767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2328370767
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2451646772
Short name T784
Test name
Test status
Simulation time 410597448 ps
CPU time 10.04 seconds
Started Jul 02 09:57:40 AM PDT 24
Finished Jul 02 09:57:52 AM PDT 24
Peak memory 226064 kb
Host smart-de3a49be-6da3-49b7-b343-19d1b3745f98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451646772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2451646772
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.85724750
Short name T374
Test name
Test status
Simulation time 1761465090 ps
CPU time 10.26 seconds
Started Jul 02 09:57:47 AM PDT 24
Finished Jul 02 09:58:00 AM PDT 24
Peak memory 218216 kb
Host smart-a3776803-cd17-4ded-9ac3-666651d87ba7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85724750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.85724750
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.377359761
Short name T619
Test name
Test status
Simulation time 635559132 ps
CPU time 11.67 seconds
Started Jul 02 09:57:42 AM PDT 24
Finished Jul 02 09:57:55 AM PDT 24
Peak memory 226048 kb
Host smart-cdacf33a-5219-48e5-ae25-b71306c5b2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377359761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.377359761
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1196236840
Short name T451
Test name
Test status
Simulation time 77469139 ps
CPU time 1.86 seconds
Started Jul 02 09:57:45 AM PDT 24
Finished Jul 02 09:57:48 AM PDT 24
Peak memory 214180 kb
Host smart-4edbaec7-d232-41af-94df-75a450e92099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196236840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1196236840
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.1690226293
Short name T670
Test name
Test status
Simulation time 935644842 ps
CPU time 25.15 seconds
Started Jul 02 09:57:34 AM PDT 24
Finished Jul 02 09:58:01 AM PDT 24
Peak memory 250960 kb
Host smart-3ab088d0-ef41-430a-a8f7-45e2f9e06f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690226293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1690226293
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1077263072
Short name T717
Test name
Test status
Simulation time 90197445 ps
CPU time 7.74 seconds
Started Jul 02 09:57:49 AM PDT 24
Finished Jul 02 09:57:59 AM PDT 24
Peak memory 250476 kb
Host smart-0f81b419-4b05-4d25-8dc2-149cbee00d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077263072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1077263072
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.992415792
Short name T331
Test name
Test status
Simulation time 13952808070 ps
CPU time 63.92 seconds
Started Jul 02 09:57:46 AM PDT 24
Finished Jul 02 09:58:52 AM PDT 24
Peak memory 251024 kb
Host smart-ea6501ed-6a8e-45ee-93d5-193135feb883
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992415792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.992415792
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2332907569
Short name T741
Test name
Test status
Simulation time 13360215 ps
CPU time 0.95 seconds
Started Jul 02 09:57:38 AM PDT 24
Finished Jul 02 09:57:41 AM PDT 24
Peak memory 211900 kb
Host smart-e97412d2-c979-45b5-9d8a-27d75312d62e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332907569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.2332907569
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.4006664529
Short name T368
Test name
Test status
Simulation time 67880545 ps
CPU time 0.92 seconds
Started Jul 02 09:57:46 AM PDT 24
Finished Jul 02 09:57:49 AM PDT 24
Peak memory 209064 kb
Host smart-23214c27-f39d-42e9-b301-baa83d130efd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006664529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.4006664529
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.382298239
Short name T834
Test name
Test status
Simulation time 30945969 ps
CPU time 0.81 seconds
Started Jul 02 09:57:46 AM PDT 24
Finished Jul 02 09:57:49 AM PDT 24
Peak memory 209040 kb
Host smart-19944f55-abc5-46bf-aca5-814695f47dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382298239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.382298239
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.4097996440
Short name T707
Test name
Test status
Simulation time 5820563825 ps
CPU time 13.05 seconds
Started Jul 02 09:57:55 AM PDT 24
Finished Jul 02 09:58:11 AM PDT 24
Peak memory 226124 kb
Host smart-b910ae66-6c59-4533-827d-80f654bca7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097996440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.4097996440
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.630148616
Short name T527
Test name
Test status
Simulation time 2027953358 ps
CPU time 12.08 seconds
Started Jul 02 09:57:57 AM PDT 24
Finished Jul 02 09:58:11 AM PDT 24
Peak memory 217400 kb
Host smart-d409c62e-8585-4fe8-a8ae-f9d71c53bea3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630148616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.630148616
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2899448725
Short name T831
Test name
Test status
Simulation time 4924686939 ps
CPU time 20.12 seconds
Started Jul 02 09:57:58 AM PDT 24
Finished Jul 02 09:58:20 AM PDT 24
Peak memory 226104 kb
Host smart-175de8b7-088d-4ca3-b66e-9c4a01eedd65
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899448725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2899448725
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2613155944
Short name T353
Test name
Test status
Simulation time 9347781736 ps
CPU time 36.82 seconds
Started Jul 02 09:57:40 AM PDT 24
Finished Jul 02 09:58:23 AM PDT 24
Peak memory 217872 kb
Host smart-1238c79b-20a5-4584-bda0-2947deae2bed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613155944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
613155944
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2582585876
Short name T634
Test name
Test status
Simulation time 380015599 ps
CPU time 3.74 seconds
Started Jul 02 09:57:47 AM PDT 24
Finished Jul 02 09:57:53 AM PDT 24
Peak memory 221864 kb
Host smart-c239e989-2c13-4c41-b6c8-e6245047a400
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582585876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2582585876
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3715537339
Short name T501
Test name
Test status
Simulation time 961083357 ps
CPU time 28 seconds
Started Jul 02 09:57:44 AM PDT 24
Finished Jul 02 09:58:13 AM PDT 24
Peak memory 217752 kb
Host smart-b14e4562-70f7-42e4-89dd-cfc5fdcece18
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715537339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3715537339
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.2820693593
Short name T543
Test name
Test status
Simulation time 375840337 ps
CPU time 2.35 seconds
Started Jul 02 09:58:00 AM PDT 24
Finished Jul 02 09:58:05 AM PDT 24
Peak memory 217732 kb
Host smart-cd1381e6-6eac-4e24-a592-2494ee30d848
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820693593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
2820693593
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.811643186
Short name T780
Test name
Test status
Simulation time 1373176963 ps
CPU time 32.68 seconds
Started Jul 02 09:57:53 AM PDT 24
Finished Jul 02 09:58:28 AM PDT 24
Peak memory 268784 kb
Host smart-6470cfac-f013-41f0-8607-fd71ae281e61
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811643186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.811643186
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1277189991
Short name T287
Test name
Test status
Simulation time 768289998 ps
CPU time 12.78 seconds
Started Jul 02 09:57:45 AM PDT 24
Finished Jul 02 09:58:00 AM PDT 24
Peak memory 250904 kb
Host smart-9f4d5c57-a66c-499a-bd1e-78dfbc80cbdc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277189991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1277189991
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.1856702150
Short name T690
Test name
Test status
Simulation time 54173063 ps
CPU time 3.17 seconds
Started Jul 02 09:57:41 AM PDT 24
Finished Jul 02 09:57:46 AM PDT 24
Peak memory 218160 kb
Host smart-f4543159-1ca0-45a3-923e-a7a21e0b60aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856702150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1856702150
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.1070237313
Short name T601
Test name
Test status
Simulation time 2981633671 ps
CPU time 22.52 seconds
Started Jul 02 09:57:41 AM PDT 24
Finished Jul 02 09:58:06 AM PDT 24
Peak memory 217768 kb
Host smart-88752e46-a53d-4a91-b043-a0287954a5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070237313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.1070237313
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.1141069091
Short name T89
Test name
Test status
Simulation time 209501561 ps
CPU time 21.8 seconds
Started Jul 02 09:57:40 AM PDT 24
Finished Jul 02 09:58:04 AM PDT 24
Peak memory 280720 kb
Host smart-64eb619d-fb55-4d74-b1de-89d1260012c8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141069091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.1141069091
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.1748136387
Short name T556
Test name
Test status
Simulation time 1138969114 ps
CPU time 7.78 seconds
Started Jul 02 09:57:53 AM PDT 24
Finished Jul 02 09:58:04 AM PDT 24
Peak memory 218268 kb
Host smart-80dd8171-6eb6-4227-88a4-c938e219977c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748136387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.1
748136387
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3742195606
Short name T745
Test name
Test status
Simulation time 262990846 ps
CPU time 9.89 seconds
Started Jul 02 09:57:31 AM PDT 24
Finished Jul 02 09:57:42 AM PDT 24
Peak memory 226016 kb
Host smart-99a081c4-cdee-48fc-8018-7d1a7bc6185a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742195606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3742195606
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.2978966952
Short name T95
Test name
Test status
Simulation time 845507227 ps
CPU time 5.13 seconds
Started Jul 02 09:57:42 AM PDT 24
Finished Jul 02 09:57:49 AM PDT 24
Peak memory 217700 kb
Host smart-a1e8c95a-0c07-4483-a758-927e57652b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978966952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2978966952
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3543524488
Short name T495
Test name
Test status
Simulation time 755315957 ps
CPU time 29.11 seconds
Started Jul 02 09:57:40 AM PDT 24
Finished Jul 02 09:58:11 AM PDT 24
Peak memory 250968 kb
Host smart-5a54aa11-e562-427a-9001-b5fae9b48ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543524488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3543524488
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.3360242905
Short name T412
Test name
Test status
Simulation time 47736827 ps
CPU time 5.89 seconds
Started Jul 02 09:57:48 AM PDT 24
Finished Jul 02 09:57:56 AM PDT 24
Peak memory 246776 kb
Host smart-1a545ab2-7cee-4683-b14a-bb2b276ba0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360242905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3360242905
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.24952286
Short name T576
Test name
Test status
Simulation time 45878417644 ps
CPU time 235.81 seconds
Started Jul 02 09:57:54 AM PDT 24
Finished Jul 02 10:01:53 AM PDT 24
Peak memory 251080 kb
Host smart-922f1f95-dcd2-4e68-beb3-88b3c4eb6859
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24952286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.lc_ctrl_stress_all.24952286
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.4084937702
Short name T217
Test name
Test status
Simulation time 32966131 ps
CPU time 0.96 seconds
Started Jul 02 09:58:01 AM PDT 24
Finished Jul 02 09:58:07 AM PDT 24
Peak memory 211804 kb
Host smart-13dfab47-fb2c-4a89-bd44-c038c3d0d6c2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084937702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.4084937702
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.3772826282
Short name T418
Test name
Test status
Simulation time 75810381 ps
CPU time 0.94 seconds
Started Jul 02 09:58:20 AM PDT 24
Finished Jul 02 09:58:21 AM PDT 24
Peak memory 208940 kb
Host smart-baf2d345-a16c-426f-9f9f-fbadd18be57d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772826282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3772826282
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.516983616
Short name T854
Test name
Test status
Simulation time 1336847258 ps
CPU time 10.35 seconds
Started Jul 02 09:58:12 AM PDT 24
Finished Jul 02 09:58:28 AM PDT 24
Peak memory 218116 kb
Host smart-4de12949-c7fe-4496-a803-6dbfe5ae6506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516983616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.516983616
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.2523101177
Short name T423
Test name
Test status
Simulation time 889977446 ps
CPU time 5.56 seconds
Started Jul 02 09:58:10 AM PDT 24
Finished Jul 02 09:58:22 AM PDT 24
Peak memory 217400 kb
Host smart-34a95a87-eec9-4b64-9252-9e4a92aa9c7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523101177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.2523101177
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1893544406
Short name T708
Test name
Test status
Simulation time 6720534704 ps
CPU time 92.64 seconds
Started Jul 02 09:58:08 AM PDT 24
Finished Jul 02 09:59:47 AM PDT 24
Peak memory 219664 kb
Host smart-abf7d71e-09a3-41ea-af87-45da6e9310f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893544406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1893544406
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.591213961
Short name T389
Test name
Test status
Simulation time 649300001 ps
CPU time 3.87 seconds
Started Jul 02 09:58:12 AM PDT 24
Finished Jul 02 09:58:21 AM PDT 24
Peak memory 222848 kb
Host smart-e7f4765c-a4fc-495b-a2cf-7bf83247c3a4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591213961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag
_prog_failure.591213961
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.1794527049
Short name T70
Test name
Test status
Simulation time 412503782 ps
CPU time 3.25 seconds
Started Jul 02 09:58:05 AM PDT 24
Finished Jul 02 09:58:14 AM PDT 24
Peak memory 217728 kb
Host smart-6026f07e-c27f-4a6a-9840-af590cd75f1e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794527049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.1794527049
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.554288245
Short name T798
Test name
Test status
Simulation time 3031507832 ps
CPU time 63.73 seconds
Started Jul 02 09:58:11 AM PDT 24
Finished Jul 02 09:59:20 AM PDT 24
Peak memory 275636 kb
Host smart-f8604754-e75a-42c5-b77b-599a0b61dbbb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554288245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_state_failure.554288245
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3061878340
Short name T715
Test name
Test status
Simulation time 9527914102 ps
CPU time 32.94 seconds
Started Jul 02 09:58:07 AM PDT 24
Finished Jul 02 09:58:46 AM PDT 24
Peak memory 250696 kb
Host smart-7cca1566-04b6-4e2b-9b3c-cc9e8f58b69a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061878340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.3061878340
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.3627564831
Short name T512
Test name
Test status
Simulation time 44437110 ps
CPU time 1.7 seconds
Started Jul 02 09:58:03 AM PDT 24
Finished Jul 02 09:58:09 AM PDT 24
Peak memory 218216 kb
Host smart-cc63119f-3e06-41ed-95bf-331cf4aa73c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627564831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.3627564831
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.873716431
Short name T365
Test name
Test status
Simulation time 283093169 ps
CPU time 13.37 seconds
Started Jul 02 09:58:08 AM PDT 24
Finished Jul 02 09:58:28 AM PDT 24
Peak memory 218136 kb
Host smart-4433d4f8-a8a1-4eec-a929-fae73e17e09e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873716431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.873716431
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1841238251
Short name T833
Test name
Test status
Simulation time 496289744 ps
CPU time 7.93 seconds
Started Jul 02 09:58:12 AM PDT 24
Finished Jul 02 09:58:25 AM PDT 24
Peak memory 226212 kb
Host smart-d4048cdb-74c9-4812-abd9-d9ed4898105d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841238251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1841238251
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.576709446
Short name T232
Test name
Test status
Simulation time 226165749 ps
CPU time 8.54 seconds
Started Jul 02 09:58:22 AM PDT 24
Finished Jul 02 09:58:33 AM PDT 24
Peak memory 218264 kb
Host smart-d9bca4a7-aa7d-4b61-8f92-f8415fb66d29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576709446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.576709446
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.3200894396
Short name T755
Test name
Test status
Simulation time 1165485732 ps
CPU time 10.82 seconds
Started Jul 02 09:58:14 AM PDT 24
Finished Jul 02 09:58:29 AM PDT 24
Peak memory 218332 kb
Host smart-ee4cf19c-47c6-4761-ba44-ebc69eb62a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200894396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.3200894396
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.1899216654
Short name T463
Test name
Test status
Simulation time 58780403 ps
CPU time 3.43 seconds
Started Jul 02 09:58:08 AM PDT 24
Finished Jul 02 09:58:18 AM PDT 24
Peak memory 215044 kb
Host smart-22fb9468-64a6-437c-96ef-d9774b50fb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899216654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1899216654
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.3469643421
Short name T541
Test name
Test status
Simulation time 2592081333 ps
CPU time 18.24 seconds
Started Jul 02 09:58:24 AM PDT 24
Finished Jul 02 09:58:43 AM PDT 24
Peak memory 245716 kb
Host smart-ecfd7072-da45-498c-a7b2-4b75c7fc136f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469643421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.3469643421
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2251627544
Short name T566
Test name
Test status
Simulation time 62081425 ps
CPU time 6.44 seconds
Started Jul 02 09:58:13 AM PDT 24
Finished Jul 02 09:58:24 AM PDT 24
Peak memory 246632 kb
Host smart-004cdffb-9ee7-4af6-b035-06a179c3483f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251627544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2251627544
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.3707413432
Short name T650
Test name
Test status
Simulation time 77617930544 ps
CPU time 220.36 seconds
Started Jul 02 09:58:07 AM PDT 24
Finished Jul 02 10:01:54 AM PDT 24
Peak memory 270148 kb
Host smart-e18d6404-893d-4251-8779-849198831c2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707413432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.3707413432
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.2249433509
Short name T801
Test name
Test status
Simulation time 64695244504 ps
CPU time 329.34 seconds
Started Jul 02 09:58:06 AM PDT 24
Finished Jul 02 10:03:41 AM PDT 24
Peak memory 316616 kb
Host smart-bcf61b04-e0bc-4990-af61-2e67b14980fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2249433509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.2249433509
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2618990271
Short name T153
Test name
Test status
Simulation time 32100369 ps
CPU time 0.8 seconds
Started Jul 02 09:58:06 AM PDT 24
Finished Jul 02 09:58:13 AM PDT 24
Peak memory 211904 kb
Host smart-951eaad6-4653-462f-b75d-4ceaf7a877c5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618990271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.2618990271
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.891054054
Short name T220
Test name
Test status
Simulation time 387856406 ps
CPU time 16.29 seconds
Started Jul 02 09:58:33 AM PDT 24
Finished Jul 02 09:58:51 AM PDT 24
Peak memory 218192 kb
Host smart-fb98ba5b-f184-411b-ab8f-80410c15ee6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891054054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.891054054
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.3599852223
Short name T655
Test name
Test status
Simulation time 2232373978 ps
CPU time 6.78 seconds
Started Jul 02 09:58:14 AM PDT 24
Finished Jul 02 09:58:25 AM PDT 24
Peak memory 217260 kb
Host smart-1fd95674-b7a3-43cd-8ae4-b08d31cbf61f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599852223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.3599852223
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.4270680873
Short name T842
Test name
Test status
Simulation time 1768665444 ps
CPU time 29.3 seconds
Started Jul 02 09:58:10 AM PDT 24
Finished Jul 02 09:58:46 AM PDT 24
Peak memory 218860 kb
Host smart-80787344-9008-4032-807f-e77259bc4e09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270680873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.4270680873
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2680097041
Short name T387
Test name
Test status
Simulation time 1220352756 ps
CPU time 6.83 seconds
Started Jul 02 09:58:07 AM PDT 24
Finished Jul 02 09:58:20 AM PDT 24
Peak memory 218160 kb
Host smart-0bc1019b-0b86-47b3-afa6-32288904b6ae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680097041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.2680097041
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2332834602
Short name T80
Test name
Test status
Simulation time 901634948 ps
CPU time 4.7 seconds
Started Jul 02 09:58:13 AM PDT 24
Finished Jul 02 09:58:23 AM PDT 24
Peak memory 217728 kb
Host smart-8e8c89ab-0600-43df-b0c9-0401ca93fc46
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332834602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2332834602
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.1611052979
Short name T748
Test name
Test status
Simulation time 1359944810 ps
CPU time 39.73 seconds
Started Jul 02 09:58:28 AM PDT 24
Finished Jul 02 09:59:09 AM PDT 24
Peak memory 275588 kb
Host smart-635b32ca-0330-4678-8c56-2324f2490c36
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611052979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.1611052979
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1347581487
Short name T728
Test name
Test status
Simulation time 464932142 ps
CPU time 12.79 seconds
Started Jul 02 09:58:06 AM PDT 24
Finished Jul 02 09:58:25 AM PDT 24
Peak memory 250824 kb
Host smart-48dcbf20-79f5-4a1e-870e-8d9ef71365e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347581487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.1347581487
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.1563771539
Short name T524
Test name
Test status
Simulation time 295564209 ps
CPU time 3.47 seconds
Started Jul 02 09:58:02 AM PDT 24
Finished Jul 02 09:58:08 AM PDT 24
Peak memory 218248 kb
Host smart-494f6987-70c4-4623-88c8-b7b7fa856930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563771539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1563771539
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.1934645426
Short name T409
Test name
Test status
Simulation time 347909804 ps
CPU time 8.85 seconds
Started Jul 02 09:58:04 AM PDT 24
Finished Jul 02 09:58:17 AM PDT 24
Peak memory 218224 kb
Host smart-dc5bd6a6-a4dd-4d68-abff-f66e8cf9860a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934645426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.1934645426
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2165595278
Short name T332
Test name
Test status
Simulation time 1394430445 ps
CPU time 12.09 seconds
Started Jul 02 09:58:09 AM PDT 24
Finished Jul 02 09:58:28 AM PDT 24
Peak memory 226032 kb
Host smart-84b6b419-7e2b-4055-be41-7f26aff02a98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165595278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2165595278
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.675574826
Short name T647
Test name
Test status
Simulation time 278602761 ps
CPU time 7.38 seconds
Started Jul 02 09:58:20 AM PDT 24
Finished Jul 02 09:58:28 AM PDT 24
Peak memory 218224 kb
Host smart-ee90dcc4-9402-4b36-b0b9-8c2fcbc69b34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675574826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.675574826
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2975221245
Short name T669
Test name
Test status
Simulation time 264982768 ps
CPU time 10.74 seconds
Started Jul 02 09:58:11 AM PDT 24
Finished Jul 02 09:58:27 AM PDT 24
Peak memory 225996 kb
Host smart-ac3d25b3-ce76-4e49-b767-39180044e85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975221245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2975221245
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2163411853
Short name T283
Test name
Test status
Simulation time 487276958 ps
CPU time 3.54 seconds
Started Jul 02 09:58:08 AM PDT 24
Finished Jul 02 09:58:18 AM PDT 24
Peak memory 217724 kb
Host smart-12b67ff2-5bad-4f11-b707-19c7a717eb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163411853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2163411853
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3201689272
Short name T247
Test name
Test status
Simulation time 610544615 ps
CPU time 32.77 seconds
Started Jul 02 09:58:16 AM PDT 24
Finished Jul 02 09:58:52 AM PDT 24
Peak memory 251060 kb
Host smart-40e15bd7-fb21-44af-a1b8-bbfd5493941e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201689272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3201689272
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.276730760
Short name T823
Test name
Test status
Simulation time 105071558 ps
CPU time 5.56 seconds
Started Jul 02 09:58:11 AM PDT 24
Finished Jul 02 09:58:23 AM PDT 24
Peak memory 226388 kb
Host smart-3ce1c0b7-b7de-4837-9a23-1eefa2d57f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276730760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.276730760
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.640239813
Short name T84
Test name
Test status
Simulation time 10158100478 ps
CPU time 94.33 seconds
Started Jul 02 09:58:12 AM PDT 24
Finished Jul 02 09:59:52 AM PDT 24
Peak memory 250948 kb
Host smart-9f46b512-6e66-45a6-934a-5d69c3147b17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640239813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.640239813
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2635955455
Short name T591
Test name
Test status
Simulation time 12131902 ps
CPU time 1.02 seconds
Started Jul 02 09:58:05 AM PDT 24
Finished Jul 02 09:58:12 AM PDT 24
Peak memory 211892 kb
Host smart-a97dd35f-07ca-4b69-a936-108bed63712f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635955455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2635955455
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.40203693
Short name T428
Test name
Test status
Simulation time 15043500 ps
CPU time 0.92 seconds
Started Jul 02 09:58:10 AM PDT 24
Finished Jul 02 09:58:17 AM PDT 24
Peak memory 208928 kb
Host smart-6ece0b5e-3d5a-45a9-9fff-2608f7bb471c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40203693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.40203693
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.2041914455
Short name T327
Test name
Test status
Simulation time 4495912752 ps
CPU time 14.02 seconds
Started Jul 02 09:58:05 AM PDT 24
Finished Jul 02 09:58:25 AM PDT 24
Peak memory 218272 kb
Host smart-16eb3060-0cd5-48cf-b742-c93792f1ed86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041914455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2041914455
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.3883108157
Short name T616
Test name
Test status
Simulation time 1631222439 ps
CPU time 11.46 seconds
Started Jul 02 09:58:10 AM PDT 24
Finished Jul 02 09:58:28 AM PDT 24
Peak memory 217020 kb
Host smart-d5df0701-75e2-4e95-887b-e7645105cec6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883108157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3883108157
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.325224422
Short name T820
Test name
Test status
Simulation time 3291048898 ps
CPU time 36.57 seconds
Started Jul 02 09:58:07 AM PDT 24
Finished Jul 02 09:58:50 AM PDT 24
Peak memory 226068 kb
Host smart-77bb6b71-cdfc-47ff-9cef-09651498e81e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325224422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_er
rors.325224422
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2218379091
Short name T458
Test name
Test status
Simulation time 643179959 ps
CPU time 10.36 seconds
Started Jul 02 09:58:07 AM PDT 24
Finished Jul 02 09:58:24 AM PDT 24
Peak memory 218216 kb
Host smart-05a14aa7-1570-4f67-bc3c-43ee8dd60bd5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218379091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.2218379091
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3404052322
Short name T535
Test name
Test status
Simulation time 935886922 ps
CPU time 4.16 seconds
Started Jul 02 09:58:12 AM PDT 24
Finished Jul 02 09:58:25 AM PDT 24
Peak memory 217692 kb
Host smart-b6dc5b48-ce4b-460f-8715-919f190be9d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404052322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.3404052322
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3426336439
Short name T812
Test name
Test status
Simulation time 648133812 ps
CPU time 11.58 seconds
Started Jul 02 09:58:08 AM PDT 24
Finished Jul 02 09:58:26 AM PDT 24
Peak memory 250892 kb
Host smart-fbbd0cec-9b90-4fa0-883f-f1fb1f466104
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426336439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3426336439
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.865268180
Short name T581
Test name
Test status
Simulation time 160814187 ps
CPU time 2.79 seconds
Started Jul 02 09:58:09 AM PDT 24
Finished Jul 02 09:58:19 AM PDT 24
Peak memory 218164 kb
Host smart-34e165cc-0eb5-4611-8ef9-472ebdc78182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865268180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.865268180
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2741166439
Short name T795
Test name
Test status
Simulation time 4005603372 ps
CPU time 21.82 seconds
Started Jul 02 09:58:07 AM PDT 24
Finished Jul 02 09:58:35 AM PDT 24
Peak memory 218292 kb
Host smart-492aaf18-9e57-40a4-a38e-5cecd2f7ccd5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741166439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.2741166439
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3582895771
Short name T792
Test name
Test status
Simulation time 377179985 ps
CPU time 8.53 seconds
Started Jul 02 09:58:07 AM PDT 24
Finished Jul 02 09:58:24 AM PDT 24
Peak memory 218240 kb
Host smart-8241eb34-4b94-44e1-be2f-b7f97235b294
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582895771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3582895771
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.2005629753
Short name T806
Test name
Test status
Simulation time 418781785 ps
CPU time 6.22 seconds
Started Jul 02 09:58:04 AM PDT 24
Finished Jul 02 09:58:16 AM PDT 24
Peak memory 218368 kb
Host smart-29e41f03-ed29-48e0-a3e3-b77a7c8a2b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005629753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2005629753
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.369997595
Short name T253
Test name
Test status
Simulation time 111071833 ps
CPU time 2.19 seconds
Started Jul 02 09:58:14 AM PDT 24
Finished Jul 02 09:58:20 AM PDT 24
Peak memory 214772 kb
Host smart-70e039c7-c7e5-4e4a-8e18-70d53cb4e083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369997595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.369997595
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2718654523
Short name T724
Test name
Test status
Simulation time 456626670 ps
CPU time 19.29 seconds
Started Jul 02 09:58:08 AM PDT 24
Finished Jul 02 09:58:34 AM PDT 24
Peak memory 245452 kb
Host smart-ceecccf9-cecb-47fe-b769-85e0b6b33aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718654523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2718654523
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.3472639144
Short name T558
Test name
Test status
Simulation time 163861493 ps
CPU time 7.21 seconds
Started Jul 02 09:58:06 AM PDT 24
Finished Jul 02 09:58:19 AM PDT 24
Peak memory 248508 kb
Host smart-3027b951-f570-4bef-a88e-6315780c0723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472639144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3472639144
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.1515888249
Short name T531
Test name
Test status
Simulation time 21737394819 ps
CPU time 120.67 seconds
Started Jul 02 09:58:05 AM PDT 24
Finished Jul 02 10:00:11 AM PDT 24
Peak memory 281200 kb
Host smart-3e29e59f-c65e-4d3f-ac26-b49bef59f5c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515888249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.1515888249
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.303665814
Short name T787
Test name
Test status
Simulation time 20828300 ps
CPU time 1.03 seconds
Started Jul 02 09:58:01 AM PDT 24
Finished Jul 02 09:58:05 AM PDT 24
Peak memory 212940 kb
Host smart-f7e41eca-e71d-43f7-87ce-85d8ab060248
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303665814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ct
rl_volatile_unlock_smoke.303665814
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.1933086614
Short name T800
Test name
Test status
Simulation time 200096110 ps
CPU time 1.01 seconds
Started Jul 02 09:58:22 AM PDT 24
Finished Jul 02 09:58:24 AM PDT 24
Peak memory 209072 kb
Host smart-006062f0-aade-4832-b465-e32002acd7b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933086614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.1933086614
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1367935475
Short name T335
Test name
Test status
Simulation time 1104069982 ps
CPU time 15.51 seconds
Started Jul 02 09:58:10 AM PDT 24
Finished Jul 02 09:58:32 AM PDT 24
Peak memory 225832 kb
Host smart-e7e68ed4-9b0c-4b23-a00f-02183a323e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367935475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1367935475
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.1656109333
Short name T683
Test name
Test status
Simulation time 315920180 ps
CPU time 2.09 seconds
Started Jul 02 09:58:07 AM PDT 24
Finished Jul 02 09:58:15 AM PDT 24
Peak memory 217184 kb
Host smart-e103acc3-c2b6-4e42-acba-7d4cf3d93771
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656109333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.1656109333
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.1709574177
Short name T36
Test name
Test status
Simulation time 27355949147 ps
CPU time 41.01 seconds
Started Jul 02 09:59:32 AM PDT 24
Finished Jul 02 10:00:15 AM PDT 24
Peak memory 218708 kb
Host smart-a733897c-636c-4852-bcce-48096b97c5f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709574177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.1709574177
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2242214515
Short name T569
Test name
Test status
Simulation time 294006441 ps
CPU time 9.18 seconds
Started Jul 02 09:58:17 AM PDT 24
Finished Jul 02 09:58:29 AM PDT 24
Peak memory 218228 kb
Host smart-dd9886a2-da41-46cd-b114-4577fe497856
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242214515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2242214515
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2627886213
Short name T554
Test name
Test status
Simulation time 90896087 ps
CPU time 2.19 seconds
Started Jul 02 09:58:12 AM PDT 24
Finished Jul 02 09:58:20 AM PDT 24
Peak memory 217804 kb
Host smart-3fd0880d-6a85-4f8f-ba74-6160cd2b842f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627886213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2627886213
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3846192552
Short name T152
Test name
Test status
Simulation time 1037740303 ps
CPU time 37.22 seconds
Started Jul 02 09:58:06 AM PDT 24
Finished Jul 02 09:58:50 AM PDT 24
Peak memory 251916 kb
Host smart-22a3f985-131b-4f76-85ba-daa5b06de6d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846192552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3846192552
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1677351491
Short name T315
Test name
Test status
Simulation time 488043916 ps
CPU time 12.78 seconds
Started Jul 02 09:58:12 AM PDT 24
Finished Jul 02 09:58:30 AM PDT 24
Peak memory 250572 kb
Host smart-2e7b6ca2-7fa2-4e51-a894-49738e8cc597
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677351491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1677351491
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.3315743069
Short name T148
Test name
Test status
Simulation time 16908786 ps
CPU time 1.43 seconds
Started Jul 02 09:58:10 AM PDT 24
Finished Jul 02 09:58:18 AM PDT 24
Peak memory 218228 kb
Host smart-ee6e5aac-395a-4339-9805-0d256896ae9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315743069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3315743069
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.2767309188
Short name T470
Test name
Test status
Simulation time 778958498 ps
CPU time 11.58 seconds
Started Jul 02 09:59:31 AM PDT 24
Finished Jul 02 09:59:44 AM PDT 24
Peak memory 218724 kb
Host smart-2cf3c8aa-65ae-424e-a9a9-0b6a29bbeeb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767309188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.2767309188
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.879262619
Short name T773
Test name
Test status
Simulation time 1673235864 ps
CPU time 8.87 seconds
Started Jul 02 09:59:41 AM PDT 24
Finished Jul 02 09:59:51 AM PDT 24
Peak memory 225788 kb
Host smart-c6a168ae-a23b-48bb-9331-56571b3f1032
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879262619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di
gest.879262619
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.1156619488
Short name T196
Test name
Test status
Simulation time 301032765 ps
CPU time 11.79 seconds
Started Jul 02 09:59:16 AM PDT 24
Finished Jul 02 09:59:34 AM PDT 24
Peak memory 216388 kb
Host smart-c11d2dcb-6a77-40c4-9a2d-c17b346dcdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156619488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.1156619488
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.4279121363
Short name T67
Test name
Test status
Simulation time 64584443 ps
CPU time 1.39 seconds
Started Jul 02 09:58:38 AM PDT 24
Finished Jul 02 09:58:40 AM PDT 24
Peak memory 217692 kb
Host smart-5677b877-42a1-4471-b253-a3b62af9ae7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279121363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.4279121363
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.323831790
Short name T216
Test name
Test status
Simulation time 211809171 ps
CPU time 24.69 seconds
Started Jul 02 09:58:14 AM PDT 24
Finished Jul 02 09:58:43 AM PDT 24
Peak memory 250992 kb
Host smart-6a844deb-e7d3-4e72-ac21-bd40b3beac7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323831790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.323831790
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.75093062
Short name T211
Test name
Test status
Simulation time 485300057 ps
CPU time 7.06 seconds
Started Jul 02 09:58:15 AM PDT 24
Finished Jul 02 09:58:26 AM PDT 24
Peak memory 248488 kb
Host smart-d8205a36-99d8-480a-b9d2-75d88455e658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75093062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.75093062
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.2334255804
Short name T85
Test name
Test status
Simulation time 2640467316 ps
CPU time 45.04 seconds
Started Jul 02 09:58:14 AM PDT 24
Finished Jul 02 09:59:04 AM PDT 24
Peak memory 226132 kb
Host smart-02aac8a6-6e2f-4750-a12e-a58429837951
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334255804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.2334255804
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3661160977
Short name T161
Test name
Test status
Simulation time 12416190 ps
CPU time 1 seconds
Started Jul 02 09:58:11 AM PDT 24
Finished Jul 02 09:58:18 AM PDT 24
Peak memory 211868 kb
Host smart-5f77eda7-bb84-40f9-aeea-4cf7905fef32
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661160977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.3661160977
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.3341582986
Short name T626
Test name
Test status
Simulation time 20276749 ps
CPU time 1.09 seconds
Started Jul 02 09:59:43 AM PDT 24
Finished Jul 02 09:59:46 AM PDT 24
Peak memory 208720 kb
Host smart-80a6328f-97b5-4330-a82b-f3672f739247
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341582986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3341582986
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2142427249
Short name T288
Test name
Test status
Simulation time 579156640 ps
CPU time 14.57 seconds
Started Jul 02 09:58:18 AM PDT 24
Finished Jul 02 09:58:35 AM PDT 24
Peak memory 218400 kb
Host smart-fe13312c-8481-4ac7-9dea-649fb95c6ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142427249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2142427249
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.4132152670
Short name T783
Test name
Test status
Simulation time 4145820413 ps
CPU time 109.22 seconds
Started Jul 02 09:58:10 AM PDT 24
Finished Jul 02 10:00:05 AM PDT 24
Peak memory 218968 kb
Host smart-aafeb2b1-d7b7-4a0b-9fae-842d6bf01f95
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132152670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.4132152670
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.530802080
Short name T678
Test name
Test status
Simulation time 1031830997 ps
CPU time 8.69 seconds
Started Jul 02 09:58:08 AM PDT 24
Finished Jul 02 09:58:24 AM PDT 24
Peak memory 218184 kb
Host smart-0df288e1-930a-4247-8325-97fdd929ef47
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530802080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag
_prog_failure.530802080
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1301070400
Short name T844
Test name
Test status
Simulation time 789976426 ps
CPU time 5.13 seconds
Started Jul 02 09:59:16 AM PDT 24
Finished Jul 02 09:59:28 AM PDT 24
Peak memory 215788 kb
Host smart-ef1faf06-e784-48b5-955c-8d3ce1136754
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301070400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1301070400
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.1417329714
Short name T548
Test name
Test status
Simulation time 2321002010 ps
CPU time 49.57 seconds
Started Jul 02 09:59:40 AM PDT 24
Finished Jul 02 10:00:32 AM PDT 24
Peak memory 250804 kb
Host smart-e2677907-744d-46b7-a972-d5f7fe5e07c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417329714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.1417329714
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.317954172
Short name T359
Test name
Test status
Simulation time 1168679531 ps
CPU time 25.47 seconds
Started Jul 02 09:59:16 AM PDT 24
Finished Jul 02 09:59:48 AM PDT 24
Peak memory 248768 kb
Host smart-300420c2-6908-46d0-ab6a-3ca3f1792362
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317954172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.317954172
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.4199006817
Short name T507
Test name
Test status
Simulation time 43677439 ps
CPU time 2.13 seconds
Started Jul 02 09:58:07 AM PDT 24
Finished Jul 02 09:58:15 AM PDT 24
Peak memory 218232 kb
Host smart-7bfb1075-149c-4239-bc43-abf66b4ae7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199006817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.4199006817
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.1771878290
Short name T323
Test name
Test status
Simulation time 190190154 ps
CPU time 9.75 seconds
Started Jul 02 09:58:24 AM PDT 24
Finished Jul 02 09:58:35 AM PDT 24
Peak memory 226012 kb
Host smart-d8b5598a-fbfe-4635-9d31-25959717d5f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771878290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1771878290
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.3387757456
Short name T711
Test name
Test status
Simulation time 1488481438 ps
CPU time 18.33 seconds
Started Jul 02 09:58:23 AM PDT 24
Finished Jul 02 09:58:43 AM PDT 24
Peak memory 225984 kb
Host smart-bdba28b3-dc08-4a1a-a964-859d49e086ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387757456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.3387757456
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.2245780109
Short name T742
Test name
Test status
Simulation time 1395238976 ps
CPU time 16.24 seconds
Started Jul 02 09:58:14 AM PDT 24
Finished Jul 02 09:58:34 AM PDT 24
Peak memory 218228 kb
Host smart-63e79ba9-06a8-4bd2-ab18-478716f0373e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245780109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
2245780109
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.3549779333
Short name T363
Test name
Test status
Simulation time 1157405314 ps
CPU time 12.83 seconds
Started Jul 02 09:58:00 AM PDT 24
Finished Jul 02 09:58:15 AM PDT 24
Peak memory 218372 kb
Host smart-e9a06588-034c-4edc-a1c7-94b5039e5487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549779333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.3549779333
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.2422998776
Short name T31
Test name
Test status
Simulation time 88770563 ps
CPU time 1.96 seconds
Started Jul 02 09:58:17 AM PDT 24
Finished Jul 02 09:58:21 AM PDT 24
Peak memory 214100 kb
Host smart-f8ee20c7-77e8-45da-869d-d0f2d7291991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422998776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2422998776
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.4001373522
Short name T329
Test name
Test status
Simulation time 606010543 ps
CPU time 21.04 seconds
Started Jul 02 09:58:09 AM PDT 24
Finished Jul 02 09:58:37 AM PDT 24
Peak memory 250968 kb
Host smart-b7acd0be-8219-45fe-a97c-b20af630316f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001373522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.4001373522
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.3684500906
Short name T642
Test name
Test status
Simulation time 58107718 ps
CPU time 2.76 seconds
Started Jul 02 09:58:14 AM PDT 24
Finished Jul 02 09:58:21 AM PDT 24
Peak memory 222556 kb
Host smart-77b76005-3d2f-4966-8007-28bd93c842b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684500906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3684500906
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.2885383633
Short name T450
Test name
Test status
Simulation time 24180494694 ps
CPU time 84.35 seconds
Started Jul 02 09:58:21 AM PDT 24
Finished Jul 02 09:59:47 AM PDT 24
Peak memory 251044 kb
Host smart-c25bc97c-b7b7-4ceb-a78e-954f57124ba5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885383633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.2885383633
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2135916317
Short name T311
Test name
Test status
Simulation time 19129331 ps
CPU time 0.91 seconds
Started Jul 02 09:58:09 AM PDT 24
Finished Jul 02 09:58:16 AM PDT 24
Peak memory 211796 kb
Host smart-145a7828-4733-4275-9a18-774ed25da369
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135916317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.2135916317
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3131631115
Short name T491
Test name
Test status
Simulation time 19628936 ps
CPU time 0.76 seconds
Started Jul 02 09:59:27 AM PDT 24
Finished Jul 02 09:59:30 AM PDT 24
Peak memory 208368 kb
Host smart-d2bbaeed-5b94-44cf-b8eb-fdfd223dcc72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131631115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3131631115
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.3588789924
Short name T477
Test name
Test status
Simulation time 179830671 ps
CPU time 9.08 seconds
Started Jul 02 09:58:15 AM PDT 24
Finished Jul 02 09:58:28 AM PDT 24
Peak memory 226004 kb
Host smart-13d5c81b-e4f1-4f53-ad9c-a70381a41caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588789924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.3588789924
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2605198156
Short name T617
Test name
Test status
Simulation time 292502997 ps
CPU time 7.65 seconds
Started Jul 02 09:58:16 AM PDT 24
Finished Jul 02 09:58:27 AM PDT 24
Peak memory 217320 kb
Host smart-07d93652-2cc5-4c7a-9663-b8a205c31a85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605198156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2605198156
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.3747640363
Short name T404
Test name
Test status
Simulation time 1495194369 ps
CPU time 27.96 seconds
Started Jul 02 09:58:06 AM PDT 24
Finished Jul 02 09:58:39 AM PDT 24
Peak memory 225664 kb
Host smart-99d78458-81c7-4da2-b607-1ab56965a054
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747640363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.3747640363
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.690163781
Short name T688
Test name
Test status
Simulation time 361543345 ps
CPU time 7.36 seconds
Started Jul 02 09:59:17 AM PDT 24
Finished Jul 02 09:59:30 AM PDT 24
Peak memory 216560 kb
Host smart-32e7a146-d0f1-4f68-aa3d-079dd0d28297
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690163781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.690163781
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3711486723
Short name T350
Test name
Test status
Simulation time 5618967703 ps
CPU time 4.78 seconds
Started Jul 02 09:59:34 AM PDT 24
Finished Jul 02 09:59:42 AM PDT 24
Peak memory 217540 kb
Host smart-8c3a8114-b899-4671-9534-a959f9c6dc56
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711486723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.3711486723
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3110438253
Short name T721
Test name
Test status
Simulation time 2888922783 ps
CPU time 54.81 seconds
Started Jul 02 09:58:12 AM PDT 24
Finished Jul 02 09:59:12 AM PDT 24
Peak memory 267404 kb
Host smart-a397b536-37bb-4ff2-86e5-338ce00be793
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110438253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3110438253
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1569514288
Short name T437
Test name
Test status
Simulation time 358194864 ps
CPU time 11.61 seconds
Started Jul 02 09:58:22 AM PDT 24
Finished Jul 02 09:58:35 AM PDT 24
Peak memory 250872 kb
Host smart-98bb3015-7e12-4402-941b-b3751e137384
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569514288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.1569514288
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.3044614326
Short name T5
Test name
Test status
Simulation time 239749573 ps
CPU time 3.11 seconds
Started Jul 02 09:59:32 AM PDT 24
Finished Jul 02 09:59:37 AM PDT 24
Peak memory 217980 kb
Host smart-5b4680f6-f5a1-4b9b-95f7-69969b4449b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044614326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.3044614326
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.3845029065
Short name T511
Test name
Test status
Simulation time 2036736107 ps
CPU time 9.75 seconds
Started Jul 02 09:58:25 AM PDT 24
Finished Jul 02 09:58:35 AM PDT 24
Peak memory 218228 kb
Host smart-2c5f4e47-328e-442a-a782-ac8a0734b67a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845029065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.3845029065
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.603204716
Short name T860
Test name
Test status
Simulation time 656565935 ps
CPU time 14.91 seconds
Started Jul 02 09:58:31 AM PDT 24
Finished Jul 02 09:58:47 AM PDT 24
Peak memory 218240 kb
Host smart-d7268a65-6a6e-4ac3-bdc3-d868e7314573
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603204716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di
gest.603204716
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1106230715
Short name T439
Test name
Test status
Simulation time 1489459273 ps
CPU time 8.67 seconds
Started Jul 02 09:58:09 AM PDT 24
Finished Jul 02 09:58:24 AM PDT 24
Peak memory 218236 kb
Host smart-1f929dc1-743f-4966-8867-25ff808a6776
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106230715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1106230715
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3773301780
Short name T320
Test name
Test status
Simulation time 709824645 ps
CPU time 16.53 seconds
Started Jul 02 09:58:38 AM PDT 24
Finished Jul 02 09:58:56 AM PDT 24
Peak memory 218304 kb
Host smart-0d93e095-8cb3-425e-8c42-c430d7aeae38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773301780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3773301780
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1455854776
Short name T605
Test name
Test status
Simulation time 43639551 ps
CPU time 2.57 seconds
Started Jul 02 09:58:23 AM PDT 24
Finished Jul 02 09:58:27 AM PDT 24
Peak memory 217748 kb
Host smart-c9ff2bbf-2032-47bd-951e-1ed120d4809d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455854776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1455854776
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.2606759730
Short name T583
Test name
Test status
Simulation time 229198648 ps
CPU time 27.66 seconds
Started Jul 02 09:58:26 AM PDT 24
Finished Jul 02 09:58:54 AM PDT 24
Peak memory 250916 kb
Host smart-07b08031-1f3e-4ecc-bc63-48bc9371f767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606759730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2606759730
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.3341407856
Short name T198
Test name
Test status
Simulation time 264008807 ps
CPU time 6.08 seconds
Started Jul 02 09:58:10 AM PDT 24
Finished Jul 02 09:58:22 AM PDT 24
Peak memory 246228 kb
Host smart-c55b587f-803a-4ef1-adc7-6ca5cf458c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341407856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.3341407856
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.4146165284
Short name T570
Test name
Test status
Simulation time 4850139593 ps
CPU time 77.73 seconds
Started Jul 02 09:58:42 AM PDT 24
Finished Jul 02 10:00:01 AM PDT 24
Peak memory 251016 kb
Host smart-96801252-dbfe-4daf-8be9-c635ae34489d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146165284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.4146165284
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.4208073918
Short name T838
Test name
Test status
Simulation time 33785484 ps
CPU time 0.9 seconds
Started Jul 02 09:58:26 AM PDT 24
Finished Jul 02 09:58:28 AM PDT 24
Peak memory 211892 kb
Host smart-4e19dae0-9055-4d96-9935-13edaf8bd310
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208073918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.4208073918
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.3143226012
Short name T615
Test name
Test status
Simulation time 35742800 ps
CPU time 0.83 seconds
Started Jul 02 09:58:11 AM PDT 24
Finished Jul 02 09:58:18 AM PDT 24
Peak memory 208816 kb
Host smart-ebe10f86-6ab2-4a4d-9ec2-295361aa84f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143226012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.3143226012
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.2823287211
Short name T750
Test name
Test status
Simulation time 684550685 ps
CPU time 13.13 seconds
Started Jul 02 09:58:10 AM PDT 24
Finished Jul 02 09:58:30 AM PDT 24
Peak memory 226116 kb
Host smart-e78edfe1-0515-460e-8b89-9921df3d84f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823287211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.2823287211
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.3688513943
Short name T27
Test name
Test status
Simulation time 2171283719 ps
CPU time 7.14 seconds
Started Jul 02 09:58:29 AM PDT 24
Finished Jul 02 09:58:37 AM PDT 24
Peak memory 217352 kb
Host smart-612d5232-ac1c-4ad9-9a7a-45f4762acba6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688513943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.3688513943
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3010653658
Short name T702
Test name
Test status
Simulation time 19025393846 ps
CPU time 55.95 seconds
Started Jul 02 09:59:14 AM PDT 24
Finished Jul 02 10:00:17 AM PDT 24
Peak memory 218804 kb
Host smart-9fd63af5-4100-4d0e-bff0-d039dd7802bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010653658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3010653658
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.4159979148
Short name T233
Test name
Test status
Simulation time 4960560795 ps
CPU time 7.96 seconds
Started Jul 02 09:58:33 AM PDT 24
Finished Jul 02 09:58:42 AM PDT 24
Peak memory 218320 kb
Host smart-a478c81a-f5f7-4dd2-957f-133cd15147fb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159979148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.4159979148
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3413616239
Short name T435
Test name
Test status
Simulation time 1955757203 ps
CPU time 6.27 seconds
Started Jul 02 09:58:45 AM PDT 24
Finished Jul 02 09:58:52 AM PDT 24
Peak memory 217724 kb
Host smart-7d86eb78-1840-4436-928f-017ae504636e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413616239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3413616239
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1784200278
Short name T613
Test name
Test status
Simulation time 787444941 ps
CPU time 27.78 seconds
Started Jul 02 09:58:05 AM PDT 24
Finished Jul 02 09:58:39 AM PDT 24
Peak memory 250940 kb
Host smart-ce5e1696-04ce-44a9-870a-01930bf33f16
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784200278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.1784200278
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3781927130
Short name T275
Test name
Test status
Simulation time 964315995 ps
CPU time 17.13 seconds
Started Jul 02 09:58:05 AM PDT 24
Finished Jul 02 09:58:27 AM PDT 24
Peak memory 247448 kb
Host smart-849300b1-50d6-44a3-9a0c-2a30692be145
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781927130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3781927130
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2145934750
Short name T536
Test name
Test status
Simulation time 264668235 ps
CPU time 3.94 seconds
Started Jul 02 09:58:30 AM PDT 24
Finished Jul 02 09:58:36 AM PDT 24
Peak memory 218392 kb
Host smart-7c06336b-4635-4ef5-9ba2-899c9b49fd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145934750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2145934750
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1761932496
Short name T254
Test name
Test status
Simulation time 399912756 ps
CPU time 13.48 seconds
Started Jul 02 09:59:40 AM PDT 24
Finished Jul 02 09:59:55 AM PDT 24
Peak memory 225816 kb
Host smart-82ac80cf-bd4a-4549-b2d8-684e28d0dc12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761932496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.1761932496
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2313973505
Short name T530
Test name
Test status
Simulation time 728844268 ps
CPU time 9.17 seconds
Started Jul 02 09:58:29 AM PDT 24
Finished Jul 02 09:58:39 AM PDT 24
Peak memory 218176 kb
Host smart-dc110dc5-889a-45b5-a7be-75eb5810d8fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313973505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2313973505
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.2645841913
Short name T559
Test name
Test status
Simulation time 4733262937 ps
CPU time 7.8 seconds
Started Jul 02 09:59:40 AM PDT 24
Finished Jul 02 09:59:49 AM PDT 24
Peak memory 218136 kb
Host smart-0d4768cc-2960-464c-9058-c4eef765411d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645841913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2645841913
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.1353933620
Short name T59
Test name
Test status
Simulation time 68834127 ps
CPU time 2.79 seconds
Started Jul 02 09:58:05 AM PDT 24
Finished Jul 02 09:58:15 AM PDT 24
Peak memory 214620 kb
Host smart-f0f0f85c-87d0-4c63-bd85-302061789fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353933620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.1353933620
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1927449005
Short name T157
Test name
Test status
Simulation time 1250016810 ps
CPU time 30.29 seconds
Started Jul 02 09:58:07 AM PDT 24
Finished Jul 02 09:58:43 AM PDT 24
Peak memory 250980 kb
Host smart-7d6e8fce-7231-4e1d-a632-0bbdf6e883cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927449005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1927449005
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.2495403612
Short name T417
Test name
Test status
Simulation time 560837756 ps
CPU time 6.61 seconds
Started Jul 02 09:58:17 AM PDT 24
Finished Jul 02 09:58:26 AM PDT 24
Peak memory 250520 kb
Host smart-4cc2abb6-d823-4eb0-9e4b-98a53ab190db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495403612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.2495403612
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1361513050
Short name T304
Test name
Test status
Simulation time 6567940960 ps
CPU time 70.56 seconds
Started Jul 02 09:59:41 AM PDT 24
Finished Jul 02 10:00:54 AM PDT 24
Peak memory 274744 kb
Host smart-6b624c75-3b69-4fa1-b463-9f23723fedf5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361513050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1361513050
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.963477289
Short name T490
Test name
Test status
Simulation time 12257857 ps
CPU time 1.03 seconds
Started Jul 02 09:58:20 AM PDT 24
Finished Jul 02 09:58:22 AM PDT 24
Peak memory 211992 kb
Host smart-0b11245e-4608-485b-8b27-744ba468d0e4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963477289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.963477289
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.676489885
Short name T469
Test name
Test status
Simulation time 57566303 ps
CPU time 1.13 seconds
Started Jul 02 09:58:23 AM PDT 24
Finished Jul 02 09:58:26 AM PDT 24
Peak memory 208972 kb
Host smart-494fcf0f-9f8c-426b-b2d7-b3dc44677b42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676489885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.676489885
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.4107451990
Short name T593
Test name
Test status
Simulation time 570828586 ps
CPU time 14.73 seconds
Started Jul 02 09:58:23 AM PDT 24
Finished Jul 02 09:58:39 AM PDT 24
Peak memory 218184 kb
Host smart-7546a391-4901-4d36-a6fd-e39cb303a697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107451990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.4107451990
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.1518229124
Short name T660
Test name
Test status
Simulation time 4159846202 ps
CPU time 6.4 seconds
Started Jul 02 09:58:09 AM PDT 24
Finished Jul 02 09:58:22 AM PDT 24
Peak memory 217772 kb
Host smart-9de36262-3cc8-4f8b-9d76-308871ddf3d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518229124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.1518229124
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3818648588
Short name T738
Test name
Test status
Simulation time 2533498595 ps
CPU time 27.36 seconds
Started Jul 02 09:58:22 AM PDT 24
Finished Jul 02 09:58:52 AM PDT 24
Peak memory 218268 kb
Host smart-4c1481e3-ce0f-4afe-99f2-38bffb50ae33
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818648588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3818648588
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3908720155
Short name T98
Test name
Test status
Simulation time 2265101384 ps
CPU time 3.95 seconds
Started Jul 02 09:58:30 AM PDT 24
Finished Jul 02 09:58:35 AM PDT 24
Peak memory 218264 kb
Host smart-36544953-641f-44f6-813f-9f458a942203
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908720155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.3908720155
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.967749817
Short name T513
Test name
Test status
Simulation time 2350381036 ps
CPU time 3.4 seconds
Started Jul 02 09:58:26 AM PDT 24
Finished Jul 02 09:58:30 AM PDT 24
Peak memory 217884 kb
Host smart-ed8ba98f-72e0-4dbc-b059-84bb4658db9c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967749817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
967749817
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2168484088
Short name T794
Test name
Test status
Simulation time 2721935132 ps
CPU time 60.3 seconds
Started Jul 02 09:58:20 AM PDT 24
Finished Jul 02 09:59:21 AM PDT 24
Peak memory 251072 kb
Host smart-412520ab-ffee-412b-a68a-d72fce82536b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168484088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2168484088
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.554599886
Short name T390
Test name
Test status
Simulation time 408524172 ps
CPU time 17.45 seconds
Started Jul 02 09:58:27 AM PDT 24
Finished Jul 02 09:58:46 AM PDT 24
Peak memory 250996 kb
Host smart-6d059b20-23a1-4ac8-99b5-8d282aa778c3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554599886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
jtag_state_post_trans.554599886
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1554894218
Short name T825
Test name
Test status
Simulation time 124600774 ps
CPU time 1.96 seconds
Started Jul 02 09:58:28 AM PDT 24
Finished Jul 02 09:58:32 AM PDT 24
Peak memory 222108 kb
Host smart-004948fa-7454-4ca0-8353-17ef25bd2d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554894218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1554894218
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.4170170300
Short name T150
Test name
Test status
Simulation time 963370504 ps
CPU time 13.98 seconds
Started Jul 02 09:58:16 AM PDT 24
Finished Jul 02 09:58:33 AM PDT 24
Peak memory 225628 kb
Host smart-2838d22b-a342-4f88-a38f-9bd0e4bc1acf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170170300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.4170170300
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.2184736633
Short name T330
Test name
Test status
Simulation time 1161958073 ps
CPU time 11.45 seconds
Started Jul 02 09:58:26 AM PDT 24
Finished Jul 02 09:58:39 AM PDT 24
Peak memory 226020 kb
Host smart-94281a43-756e-427d-90c8-0e7356c746ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184736633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.2184736633
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.1542930669
Short name T246
Test name
Test status
Simulation time 4922617723 ps
CPU time 8.18 seconds
Started Jul 02 09:58:07 AM PDT 24
Finished Jul 02 09:58:21 AM PDT 24
Peak memory 226084 kb
Host smart-31ee37ca-279d-4fc9-b679-280c499ed404
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542930669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
1542930669
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.558783878
Short name T197
Test name
Test status
Simulation time 255348641 ps
CPU time 10.13 seconds
Started Jul 02 09:58:08 AM PDT 24
Finished Jul 02 09:58:25 AM PDT 24
Peak memory 225952 kb
Host smart-93a359e6-aa33-44bc-b369-5720d18f032a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558783878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.558783878
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2670890971
Short name T269
Test name
Test status
Simulation time 21034516 ps
CPU time 1.47 seconds
Started Jul 02 09:58:37 AM PDT 24
Finished Jul 02 09:58:39 AM PDT 24
Peak memory 217700 kb
Host smart-9bb15b9a-3eae-4cdf-8c1f-90fef2762d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670890971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2670890971
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.1091807409
Short name T210
Test name
Test status
Simulation time 5365306975 ps
CPU time 26.56 seconds
Started Jul 02 09:58:09 AM PDT 24
Finished Jul 02 09:58:42 AM PDT 24
Peak memory 250972 kb
Host smart-733c679e-69a5-47af-b834-d22ba43be64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091807409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1091807409
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.2462380155
Short name T208
Test name
Test status
Simulation time 259745135 ps
CPU time 7.46 seconds
Started Jul 02 09:58:31 AM PDT 24
Finished Jul 02 09:58:44 AM PDT 24
Peak memory 246772 kb
Host smart-64b42eee-d0c1-4919-b0b0-e1cbdd5d881a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462380155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2462380155
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.2224272346
Short name T35
Test name
Test status
Simulation time 1101477789 ps
CPU time 44.79 seconds
Started Jul 02 09:58:35 AM PDT 24
Finished Jul 02 09:59:21 AM PDT 24
Peak memory 250944 kb
Host smart-b0beece9-83f7-436d-a4b1-3c571318b98e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224272346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.2224272346
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.42661893
Short name T201
Test name
Test status
Simulation time 79711540 ps
CPU time 0.91 seconds
Started Jul 02 09:58:42 AM PDT 24
Finished Jul 02 09:58:44 AM PDT 24
Peak memory 211868 kb
Host smart-d4aa2a56-a26f-472e-8868-c8d057e091f0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42661893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_volatile_unlock_smoke.42661893
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.1582843340
Short name T852
Test name
Test status
Simulation time 21102946 ps
CPU time 1.14 seconds
Started Jul 02 09:58:44 AM PDT 24
Finished Jul 02 09:58:47 AM PDT 24
Peak memory 209040 kb
Host smart-35be155c-6e26-417b-a11b-4b6e1cc963af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582843340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1582843340
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.1919024946
Short name T426
Test name
Test status
Simulation time 268820416 ps
CPU time 12.11 seconds
Started Jul 02 09:58:33 AM PDT 24
Finished Jul 02 09:58:47 AM PDT 24
Peak memory 218196 kb
Host smart-6e5c8150-42f6-48fc-89cc-3674c095138a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919024946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.1919024946
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.4052931666
Short name T689
Test name
Test status
Simulation time 2558072420 ps
CPU time 28.25 seconds
Started Jul 02 09:58:32 AM PDT 24
Finished Jul 02 09:59:02 AM PDT 24
Peak memory 217776 kb
Host smart-c4d98c3b-97d3-4438-823a-19c64acafa38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052931666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.4052931666
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2232835355
Short name T361
Test name
Test status
Simulation time 1913694110 ps
CPU time 29.97 seconds
Started Jul 02 09:58:21 AM PDT 24
Finished Jul 02 09:58:57 AM PDT 24
Peak memory 218260 kb
Host smart-f210830e-8c69-4de8-bcf8-0a59880506a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232835355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2232835355
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.2328398110
Short name T574
Test name
Test status
Simulation time 517890128 ps
CPU time 6.02 seconds
Started Jul 02 09:58:33 AM PDT 24
Finished Jul 02 09:58:40 AM PDT 24
Peak memory 218216 kb
Host smart-1ec4fd5c-3bf9-4ca5-a083-86a6c78b6537
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328398110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.2328398110
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.1715442781
Short name T79
Test name
Test status
Simulation time 309232689 ps
CPU time 8.36 seconds
Started Jul 02 09:58:09 AM PDT 24
Finished Jul 02 09:58:24 AM PDT 24
Peak memory 217924 kb
Host smart-8ef29086-c5bf-4b29-8abf-f2a331652ae6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715442781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.1715442781
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1828910009
Short name T704
Test name
Test status
Simulation time 1441860549 ps
CPU time 57.47 seconds
Started Jul 02 09:58:45 AM PDT 24
Finished Jul 02 09:59:44 AM PDT 24
Peak memory 275536 kb
Host smart-efd2eb45-e4f7-4cbe-a291-072f56f56033
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828910009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1828910009
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.4092524628
Short name T674
Test name
Test status
Simulation time 303160858 ps
CPU time 15.19 seconds
Started Jul 02 09:58:14 AM PDT 24
Finished Jul 02 09:58:34 AM PDT 24
Peak memory 250960 kb
Host smart-8e6bedab-fa21-4044-9edf-1c6e1b51916a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092524628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.4092524628
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.731169871
Short name T765
Test name
Test status
Simulation time 156366624 ps
CPU time 2.49 seconds
Started Jul 02 09:58:22 AM PDT 24
Finished Jul 02 09:58:26 AM PDT 24
Peak memory 222144 kb
Host smart-8d737788-1540-4aea-a270-a7edd3e4d8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731169871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.731169871
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.803019158
Short name T408
Test name
Test status
Simulation time 271012975 ps
CPU time 9.48 seconds
Started Jul 02 09:58:34 AM PDT 24
Finished Jul 02 09:58:45 AM PDT 24
Peak memory 226032 kb
Host smart-86a5bd53-6cc2-400d-83e1-a460e14c4609
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803019158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.803019158
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1334028345
Short name T646
Test name
Test status
Simulation time 518400356 ps
CPU time 8.33 seconds
Started Jul 02 09:58:29 AM PDT 24
Finished Jul 02 09:58:38 AM PDT 24
Peak memory 226012 kb
Host smart-31f970de-b2c7-4ce8-abcc-966fdf2d9cf9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334028345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1334028345
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1041490593
Short name T238
Test name
Test status
Simulation time 1268421477 ps
CPU time 12.29 seconds
Started Jul 02 09:58:27 AM PDT 24
Finished Jul 02 09:58:40 AM PDT 24
Peak memory 218248 kb
Host smart-83ce5c88-3c43-43d7-a8e4-19883dfe01c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041490593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1041490593
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.4220625464
Short name T653
Test name
Test status
Simulation time 339705632 ps
CPU time 3.41 seconds
Started Jul 02 09:58:33 AM PDT 24
Finished Jul 02 09:58:38 AM PDT 24
Peak memory 217696 kb
Host smart-ca0e1348-41ac-40c2-bfaa-3d24fe8ef24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220625464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.4220625464
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2238235728
Short name T633
Test name
Test status
Simulation time 677285958 ps
CPU time 20.95 seconds
Started Jul 02 09:58:08 AM PDT 24
Finished Jul 02 09:58:35 AM PDT 24
Peak memory 250916 kb
Host smart-7f6049d3-7b62-4993-a042-cd6293ab9096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238235728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2238235728
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3928361741
Short name T321
Test name
Test status
Simulation time 238095468 ps
CPU time 6.58 seconds
Started Jul 02 09:58:27 AM PDT 24
Finished Jul 02 09:58:35 AM PDT 24
Peak memory 246612 kb
Host smart-6955b21f-6f04-43fa-b86b-9192abd2f802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928361741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3928361741
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2303592087
Short name T218
Test name
Test status
Simulation time 2154658943 ps
CPU time 66.57 seconds
Started Jul 02 09:58:35 AM PDT 24
Finished Jul 02 09:59:43 AM PDT 24
Peak memory 275636 kb
Host smart-9d2106e9-4edf-4918-add1-f1bdb9951044
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303592087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2303592087
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.1742975267
Short name T146
Test name
Test status
Simulation time 26122508186 ps
CPU time 213.65 seconds
Started Jul 02 09:58:22 AM PDT 24
Finished Jul 02 10:01:57 AM PDT 24
Peak memory 267692 kb
Host smart-43dbec8d-a54a-489f-888b-587496162b1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1742975267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.1742975267
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2778735973
Short name T262
Test name
Test status
Simulation time 13622074 ps
CPU time 0.83 seconds
Started Jul 02 09:58:26 AM PDT 24
Finished Jul 02 09:58:28 AM PDT 24
Peak memory 211964 kb
Host smart-ea204e81-8474-4f1f-83fb-0a64315b2c88
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778735973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.2778735973
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2429835104
Short name T383
Test name
Test status
Simulation time 32262649 ps
CPU time 0.93 seconds
Started Jul 02 09:58:21 AM PDT 24
Finished Jul 02 09:58:23 AM PDT 24
Peak memory 209172 kb
Host smart-09b889af-df55-499c-aa52-3cdf58bd3634
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429835104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2429835104
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1667273878
Short name T16
Test name
Test status
Simulation time 352933554 ps
CPU time 9.34 seconds
Started Jul 02 09:58:33 AM PDT 24
Finished Jul 02 09:58:44 AM PDT 24
Peak memory 218192 kb
Host smart-0f51ab7f-2845-48e6-9255-dbae1e7276e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667273878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1667273878
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.1475296491
Short name T602
Test name
Test status
Simulation time 247509583 ps
CPU time 2.5 seconds
Started Jul 02 09:58:38 AM PDT 24
Finished Jul 02 09:58:41 AM PDT 24
Peak memory 217096 kb
Host smart-ea8d0527-8796-47d7-9fc1-b51dc67e989c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475296491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.1475296491
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2021236437
Short name T296
Test name
Test status
Simulation time 4263323863 ps
CPU time 55.57 seconds
Started Jul 02 09:58:43 AM PDT 24
Finished Jul 02 09:59:40 AM PDT 24
Peak memory 226104 kb
Host smart-8a3c0636-9945-421e-a064-19d73e044668
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021236437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2021236437
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2244190966
Short name T432
Test name
Test status
Simulation time 423022573 ps
CPU time 12.09 seconds
Started Jul 02 09:58:39 AM PDT 24
Finished Jul 02 09:58:52 AM PDT 24
Peak memory 218248 kb
Host smart-0dfc3e02-771f-40cf-9dd9-58900620680a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244190966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.2244190966
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1128303308
Short name T777
Test name
Test status
Simulation time 2050804698 ps
CPU time 6.47 seconds
Started Jul 02 09:58:34 AM PDT 24
Finished Jul 02 09:58:42 AM PDT 24
Peak memory 217696 kb
Host smart-2275f6c7-f130-429b-a914-7405d25af7db
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128303308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1128303308
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.710264627
Short name T293
Test name
Test status
Simulation time 3628259645 ps
CPU time 32.83 seconds
Started Jul 02 09:58:30 AM PDT 24
Finished Jul 02 09:59:04 AM PDT 24
Peak memory 267372 kb
Host smart-d7ece8e5-f7f5-4d59-a63b-a9f47534ce89
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710264627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_state_failure.710264627
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1344138749
Short name T577
Test name
Test status
Simulation time 918308391 ps
CPU time 19 seconds
Started Jul 02 09:58:43 AM PDT 24
Finished Jul 02 09:59:03 AM PDT 24
Peak memory 250604 kb
Host smart-0a59c7a2-7f15-4622-a8b3-5385d995c19b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344138749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1344138749
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.4255565283
Short name T713
Test name
Test status
Simulation time 1956819643 ps
CPU time 5 seconds
Started Jul 02 09:58:18 AM PDT 24
Finished Jul 02 09:58:25 AM PDT 24
Peak memory 218148 kb
Host smart-94bbb970-f9fa-4b24-9b21-1976b2b9571b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255565283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.4255565283
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.1874586548
Short name T405
Test name
Test status
Simulation time 514897031 ps
CPU time 8.79 seconds
Started Jul 02 09:58:31 AM PDT 24
Finished Jul 02 09:58:41 AM PDT 24
Peak memory 218916 kb
Host smart-52cd5c70-177e-4566-a766-57271187774b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874586548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.1874586548
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1713340158
Short name T209
Test name
Test status
Simulation time 433984620 ps
CPU time 13.02 seconds
Started Jul 02 09:58:28 AM PDT 24
Finished Jul 02 09:58:42 AM PDT 24
Peak memory 226024 kb
Host smart-4bce412b-6b68-42e9-85a8-045b1feaa88d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713340158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1713340158
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.106643624
Short name T726
Test name
Test status
Simulation time 337063708 ps
CPU time 13.79 seconds
Started Jul 02 09:58:32 AM PDT 24
Finished Jul 02 09:58:47 AM PDT 24
Peak memory 218252 kb
Host smart-d85514df-4908-40be-b23f-36a6bff6d81a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106643624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.106643624
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.1658490506
Short name T347
Test name
Test status
Simulation time 1565165416 ps
CPU time 14.3 seconds
Started Jul 02 09:58:25 AM PDT 24
Finished Jul 02 09:58:40 AM PDT 24
Peak memory 218272 kb
Host smart-68721e71-489c-4bc9-a46f-e771ef336830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658490506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1658490506
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1288614715
Short name T684
Test name
Test status
Simulation time 75109717 ps
CPU time 1.72 seconds
Started Jul 02 09:58:17 AM PDT 24
Finished Jul 02 09:58:21 AM PDT 24
Peak memory 214012 kb
Host smart-77522361-b51e-4040-bb00-0b81bc564c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288614715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1288614715
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.2038910140
Short name T621
Test name
Test status
Simulation time 713016784 ps
CPU time 26.22 seconds
Started Jul 02 09:58:24 AM PDT 24
Finished Jul 02 09:58:51 AM PDT 24
Peak memory 250976 kb
Host smart-3511f399-95af-48aa-82de-b9911ec6e0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038910140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2038910140
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.3994315525
Short name T716
Test name
Test status
Simulation time 57558533 ps
CPU time 6.73 seconds
Started Jul 02 09:58:28 AM PDT 24
Finished Jul 02 09:58:36 AM PDT 24
Peak memory 250400 kb
Host smart-0cc08f09-fa65-4dfb-ad0e-5ba3616a31a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994315525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3994315525
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1392355416
Short name T292
Test name
Test status
Simulation time 104134475268 ps
CPU time 181.32 seconds
Started Jul 02 09:58:19 AM PDT 24
Finished Jul 02 10:01:21 AM PDT 24
Peak memory 273984 kb
Host smart-329c0b91-ca05-41e5-9504-79703edb882c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392355416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1392355416
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3109109504
Short name T568
Test name
Test status
Simulation time 13699821 ps
CPU time 1.03 seconds
Started Jul 02 09:58:32 AM PDT 24
Finished Jul 02 09:58:34 AM PDT 24
Peak memory 211840 kb
Host smart-46f8f016-9dc0-4386-97c5-0a29b3684472
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109109504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3109109504
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.2594816474
Short name T416
Test name
Test status
Simulation time 31925775 ps
CPU time 1.12 seconds
Started Jul 02 09:57:57 AM PDT 24
Finished Jul 02 09:58:00 AM PDT 24
Peak memory 209328 kb
Host smart-64143141-8971-47f0-9c71-f1b6b4eb20e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594816474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2594816474
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2517448562
Short name T586
Test name
Test status
Simulation time 1338095131 ps
CPU time 13.89 seconds
Started Jul 02 09:57:53 AM PDT 24
Finished Jul 02 09:58:09 AM PDT 24
Peak memory 218080 kb
Host smart-beab4a4d-cf45-4453-b336-72201faa228c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517448562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2517448562
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.4178782160
Short name T526
Test name
Test status
Simulation time 455176318 ps
CPU time 6.05 seconds
Started Jul 02 09:57:48 AM PDT 24
Finished Jul 02 09:57:56 AM PDT 24
Peak memory 217132 kb
Host smart-47d6e08d-8599-45a7-9bdb-0b3399198b50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178782160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.4178782160
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.323340013
Short name T6
Test name
Test status
Simulation time 6216684675 ps
CPU time 25.1 seconds
Started Jul 02 09:57:43 AM PDT 24
Finished Jul 02 09:58:09 AM PDT 24
Peak memory 218336 kb
Host smart-2bf1f26f-d8f0-45e1-b0c2-22b882d7872d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323340013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_err
ors.323340013
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.3409560259
Short name T364
Test name
Test status
Simulation time 91510339 ps
CPU time 2.99 seconds
Started Jul 02 09:58:03 AM PDT 24
Finished Jul 02 09:58:10 AM PDT 24
Peak memory 217536 kb
Host smart-825c0561-5f2f-42e4-9441-396f30ebf3c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409560259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.3
409560259
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3778262321
Short name T829
Test name
Test status
Simulation time 967336139 ps
CPU time 7.65 seconds
Started Jul 02 09:57:46 AM PDT 24
Finished Jul 02 09:57:55 AM PDT 24
Peak memory 218184 kb
Host smart-7e01373c-14cf-43a1-8edb-0562af643e46
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778262321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3778262321
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.26556766
Short name T223
Test name
Test status
Simulation time 2740851588 ps
CPU time 11.57 seconds
Started Jul 02 09:57:47 AM PDT 24
Finished Jul 02 09:58:01 AM PDT 24
Peak memory 217696 kb
Host smart-1e60ac10-bd92-42ab-abbe-1c011cd6d426
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26556766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jt
ag_regwen_during_op.26556766
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.2122836000
Short name T453
Test name
Test status
Simulation time 1253740600 ps
CPU time 6.06 seconds
Started Jul 02 09:57:47 AM PDT 24
Finished Jul 02 09:57:54 AM PDT 24
Peak memory 217736 kb
Host smart-b400c4aa-d1cd-42db-bc4b-b257ba87c9e7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122836000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
2122836000
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.4098207402
Short name T747
Test name
Test status
Simulation time 3766076348 ps
CPU time 38.37 seconds
Started Jul 02 09:58:00 AM PDT 24
Finished Jul 02 09:58:40 AM PDT 24
Peak memory 251384 kb
Host smart-99af9252-f174-421c-8111-2e33d21aeb97
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098207402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.4098207402
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.4191860665
Short name T698
Test name
Test status
Simulation time 2137730548 ps
CPU time 17.86 seconds
Started Jul 02 09:57:53 AM PDT 24
Finished Jul 02 09:58:13 AM PDT 24
Peak memory 226380 kb
Host smart-a4e3002a-891f-4b96-a0cf-08e2b25b8628
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191860665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.4191860665
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.347199667
Short name T703
Test name
Test status
Simulation time 114499941 ps
CPU time 2.68 seconds
Started Jul 02 09:57:49 AM PDT 24
Finished Jul 02 09:57:53 AM PDT 24
Peak memory 218228 kb
Host smart-bac4c37a-5025-48a1-8b34-0b5ce60a2d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347199667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.347199667
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1925997709
Short name T299
Test name
Test status
Simulation time 1287571540 ps
CPU time 12.31 seconds
Started Jul 02 09:57:43 AM PDT 24
Finished Jul 02 09:57:57 AM PDT 24
Peak memory 214700 kb
Host smart-80077de4-9675-415d-a200-2015af63700f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925997709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1925997709
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.775900987
Short name T53
Test name
Test status
Simulation time 2876141598 ps
CPU time 36.68 seconds
Started Jul 02 09:57:44 AM PDT 24
Finished Jul 02 09:58:21 AM PDT 24
Peak memory 269440 kb
Host smart-dec3824b-e973-407d-95c3-01d3c1618c2e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775900987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.775900987
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.3519086331
Short name T618
Test name
Test status
Simulation time 1552048536 ps
CPU time 12.37 seconds
Started Jul 02 09:57:48 AM PDT 24
Finished Jul 02 09:58:02 AM PDT 24
Peak memory 226064 kb
Host smart-0fa5ad24-9f9b-403a-9c53-c5ab2024088c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519086331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.3519086331
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3624120893
Short name T567
Test name
Test status
Simulation time 343905167 ps
CPU time 9.3 seconds
Started Jul 02 09:57:56 AM PDT 24
Finished Jul 02 09:58:08 AM PDT 24
Peak memory 226048 kb
Host smart-33adfb69-c821-40a6-b8a9-70d84c289f28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624120893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.3624120893
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2755341397
Short name T664
Test name
Test status
Simulation time 2616889665 ps
CPU time 12.65 seconds
Started Jul 02 09:57:49 AM PDT 24
Finished Jul 02 09:58:04 AM PDT 24
Peak memory 218328 kb
Host smart-acb57a5c-1055-4881-b9c4-4639303fc8f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755341397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
755341397
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.3052616358
Short name T563
Test name
Test status
Simulation time 200373966 ps
CPU time 6.44 seconds
Started Jul 02 09:57:46 AM PDT 24
Finished Jul 02 09:57:54 AM PDT 24
Peak memory 218276 kb
Host smart-4d2930d3-2448-46f5-a2ad-7d64be746ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052616358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3052616358
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.249740000
Short name T15
Test name
Test status
Simulation time 1302684286 ps
CPU time 4.89 seconds
Started Jul 02 09:57:57 AM PDT 24
Finished Jul 02 09:58:04 AM PDT 24
Peak memory 217684 kb
Host smart-ecc0613c-90fc-42da-a6c5-20db3f0e46d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249740000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.249740000
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.275518083
Short name T438
Test name
Test status
Simulation time 481642048 ps
CPU time 26.97 seconds
Started Jul 02 09:57:52 AM PDT 24
Finished Jul 02 09:58:22 AM PDT 24
Peak memory 250912 kb
Host smart-150b6b8d-71a7-4385-b70a-5752186b6a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275518083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.275518083
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.3925933920
Short name T565
Test name
Test status
Simulation time 68765645 ps
CPU time 7.01 seconds
Started Jul 02 09:57:51 AM PDT 24
Finished Jul 02 09:58:01 AM PDT 24
Peak memory 244592 kb
Host smart-6db053bf-26dd-47ff-867b-b355d713d929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925933920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3925933920
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2408697289
Short name T803
Test name
Test status
Simulation time 11323286713 ps
CPU time 105.23 seconds
Started Jul 02 09:57:56 AM PDT 24
Finished Jul 02 09:59:44 AM PDT 24
Peak memory 226104 kb
Host smart-9abe2825-a916-4bc6-ba8b-3b2832b982bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408697289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2408697289
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.4122888196
Short name T620
Test name
Test status
Simulation time 36771311 ps
CPU time 0.82 seconds
Started Jul 02 09:57:56 AM PDT 24
Finished Jul 02 09:57:59 AM PDT 24
Peak memory 211868 kb
Host smart-856bd4c9-9925-4127-895f-c4367170e6aa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122888196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.4122888196
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.2092826088
Short name T793
Test name
Test status
Simulation time 24706799 ps
CPU time 1.03 seconds
Started Jul 02 09:58:35 AM PDT 24
Finished Jul 02 09:58:37 AM PDT 24
Peak memory 209164 kb
Host smart-9c3c3512-dea7-4755-b6d5-168be28345e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092826088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2092826088
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3917146782
Short name T385
Test name
Test status
Simulation time 633480940 ps
CPU time 18.82 seconds
Started Jul 02 09:58:31 AM PDT 24
Finished Jul 02 09:58:51 AM PDT 24
Peak memory 226060 kb
Host smart-22dde149-ea90-4d56-a752-d7c0296d5de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917146782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3917146782
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.2355085955
Short name T338
Test name
Test status
Simulation time 4108832630 ps
CPU time 3.3 seconds
Started Jul 02 09:58:28 AM PDT 24
Finished Jul 02 09:58:32 AM PDT 24
Peak memory 217756 kb
Host smart-ca6ddfae-1bca-46b2-8e6e-2d3312655a7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355085955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.2355085955
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2049499185
Short name T226
Test name
Test status
Simulation time 32172259 ps
CPU time 1.97 seconds
Started Jul 02 09:58:26 AM PDT 24
Finished Jul 02 09:58:30 AM PDT 24
Peak memory 221936 kb
Host smart-c83bced5-18fd-4758-ab84-a86853b0cddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049499185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2049499185
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.1168252698
Short name T547
Test name
Test status
Simulation time 855323881 ps
CPU time 18.1 seconds
Started Jul 02 09:58:28 AM PDT 24
Finished Jul 02 09:58:47 AM PDT 24
Peak memory 225996 kb
Host smart-96d1619b-76af-48c4-adab-77c535fdb60e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168252698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.1168252698
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2013550847
Short name T259
Test name
Test status
Simulation time 281157686 ps
CPU time 12.7 seconds
Started Jul 02 09:58:31 AM PDT 24
Finished Jul 02 09:58:45 AM PDT 24
Peak memory 226240 kb
Host smart-1c9eda59-e869-464b-a992-1497e751fbf4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013550847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.2013550847
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1115871080
Short name T461
Test name
Test status
Simulation time 1063501323 ps
CPU time 14.41 seconds
Started Jul 02 09:58:25 AM PDT 24
Finished Jul 02 09:58:41 AM PDT 24
Peak memory 226060 kb
Host smart-8dab165d-f7be-4ba4-9bf8-e438b933e1b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115871080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1115871080
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.284834831
Short name T850
Test name
Test status
Simulation time 591213429 ps
CPU time 8.49 seconds
Started Jul 02 09:58:25 AM PDT 24
Finished Jul 02 09:58:35 AM PDT 24
Peak memory 218308 kb
Host smart-cc7a67d6-e50d-473e-838d-d5e9c33298a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284834831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.284834831
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.2450680845
Short name T517
Test name
Test status
Simulation time 50586797 ps
CPU time 2.77 seconds
Started Jul 02 09:58:31 AM PDT 24
Finished Jul 02 09:58:35 AM PDT 24
Peak memory 217708 kb
Host smart-276189ab-7fff-4eff-a002-f5f6e3f49cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450680845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.2450680845
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.1127003908
Short name T274
Test name
Test status
Simulation time 244229164 ps
CPU time 29.06 seconds
Started Jul 02 09:58:49 AM PDT 24
Finished Jul 02 09:59:19 AM PDT 24
Peak memory 250992 kb
Host smart-7dfcebfd-4cb7-4de8-a91c-537a4b754e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127003908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1127003908
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1308164064
Short name T752
Test name
Test status
Simulation time 244493467 ps
CPU time 6.62 seconds
Started Jul 02 09:58:44 AM PDT 24
Finished Jul 02 09:58:52 AM PDT 24
Peak memory 246480 kb
Host smart-d5f88b25-7fcd-4309-ba27-c608791443f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308164064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1308164064
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1137576682
Short name T520
Test name
Test status
Simulation time 2094204763 ps
CPU time 37.49 seconds
Started Jul 02 09:58:29 AM PDT 24
Finished Jul 02 09:59:08 AM PDT 24
Peak memory 251820 kb
Host smart-2085b468-0ada-469a-be27-2518a5b10c29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137576682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.1137576682
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2258986922
Short name T467
Test name
Test status
Simulation time 13654598 ps
CPU time 1.06 seconds
Started Jul 02 09:58:32 AM PDT 24
Finished Jul 02 09:58:35 AM PDT 24
Peak memory 211940 kb
Host smart-ddd2011e-da5e-4227-9eac-2c3d9bef25e2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258986922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2258986922
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.3423370354
Short name T433
Test name
Test status
Simulation time 49728035 ps
CPU time 0.99 seconds
Started Jul 02 09:58:33 AM PDT 24
Finished Jul 02 09:58:35 AM PDT 24
Peak memory 209008 kb
Host smart-9d0a643d-3634-4c92-8cb6-df8979960e4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423370354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.3423370354
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.600008714
Short name T37
Test name
Test status
Simulation time 1201242801 ps
CPU time 13.86 seconds
Started Jul 02 09:58:32 AM PDT 24
Finished Jul 02 09:58:48 AM PDT 24
Peak memory 218144 kb
Host smart-36fd50b2-d69a-4e62-ae12-d9aef42befe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600008714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.600008714
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.1940374302
Short name T29
Test name
Test status
Simulation time 1147690843 ps
CPU time 5.85 seconds
Started Jul 02 09:58:48 AM PDT 24
Finished Jul 02 09:58:55 AM PDT 24
Peak memory 217408 kb
Host smart-5eb6d2b8-9832-44e8-8d92-ecd598135447
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940374302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.1940374302
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.2921098245
Short name T764
Test name
Test status
Simulation time 405433184 ps
CPU time 2.05 seconds
Started Jul 02 09:58:39 AM PDT 24
Finished Jul 02 09:58:42 AM PDT 24
Peak memory 222028 kb
Host smart-70c60d38-5da1-41d5-af36-7303e751cfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921098245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.2921098245
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2897491278
Short name T522
Test name
Test status
Simulation time 355360139 ps
CPU time 9.4 seconds
Started Jul 02 09:58:36 AM PDT 24
Finished Jul 02 09:58:47 AM PDT 24
Peak memory 226020 kb
Host smart-679cd439-7e9b-428e-afc2-e1eb33399b2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897491278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2897491278
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.788781955
Short name T579
Test name
Test status
Simulation time 648109312 ps
CPU time 5.56 seconds
Started Jul 02 09:58:36 AM PDT 24
Finished Jul 02 09:58:43 AM PDT 24
Peak memory 226036 kb
Host smart-74d6511d-4b9e-4cc6-9427-f4aac8c5ed31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788781955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.788781955
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.1089994745
Short name T500
Test name
Test status
Simulation time 1228168252 ps
CPU time 9.61 seconds
Started Jul 02 09:58:40 AM PDT 24
Finished Jul 02 09:58:51 AM PDT 24
Peak memory 226012 kb
Host smart-7ce08174-bd9d-4604-916c-0ca447b06d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089994745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1089994745
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1270155251
Short name T628
Test name
Test status
Simulation time 533517176 ps
CPU time 3.23 seconds
Started Jul 02 09:58:42 AM PDT 24
Finished Jul 02 09:58:47 AM PDT 24
Peak memory 217700 kb
Host smart-1cdb21c0-5eb3-4770-8f65-c380080f1b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270155251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1270155251
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.813200184
Short name T518
Test name
Test status
Simulation time 241313717 ps
CPU time 16.08 seconds
Started Jul 02 09:58:43 AM PDT 24
Finished Jul 02 09:59:00 AM PDT 24
Peak memory 250996 kb
Host smart-461b1df2-9058-4604-89f4-75012cc91c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813200184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.813200184
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.376661115
Short name T482
Test name
Test status
Simulation time 239685644 ps
CPU time 7.6 seconds
Started Jul 02 09:58:38 AM PDT 24
Finished Jul 02 09:58:46 AM PDT 24
Peak memory 250880 kb
Host smart-93b31791-9b02-4200-8a99-4557bf6eadff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376661115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.376661115
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.972617258
Short name T761
Test name
Test status
Simulation time 61249959138 ps
CPU time 114.79 seconds
Started Jul 02 09:58:44 AM PDT 24
Finished Jul 02 10:00:40 AM PDT 24
Peak memory 277040 kb
Host smart-e18ed7c6-2362-4152-aaff-ae1b8a074872
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972617258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.972617258
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.183944578
Short name T227
Test name
Test status
Simulation time 10421171 ps
CPU time 0.86 seconds
Started Jul 02 09:58:21 AM PDT 24
Finished Jul 02 09:58:24 AM PDT 24
Peak memory 208336 kb
Host smart-9b127373-1d22-4407-b006-b0ea8359bcb1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183944578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.183944578
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.3941814734
Short name T552
Test name
Test status
Simulation time 64873492 ps
CPU time 0.94 seconds
Started Jul 02 09:58:43 AM PDT 24
Finished Jul 02 09:58:45 AM PDT 24
Peak memory 208916 kb
Host smart-7f724eb4-eefd-4158-a2c9-ed8f884c120b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941814734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.3941814734
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2051201388
Short name T858
Test name
Test status
Simulation time 416993246 ps
CPU time 16.35 seconds
Started Jul 02 09:58:35 AM PDT 24
Finished Jul 02 09:58:53 AM PDT 24
Peak memory 218248 kb
Host smart-a42cd862-4b34-40c4-8d23-ca3ccd3c6633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051201388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2051201388
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.2502868183
Short name T10
Test name
Test status
Simulation time 193619299 ps
CPU time 3.3 seconds
Started Jul 02 09:58:25 AM PDT 24
Finished Jul 02 09:58:30 AM PDT 24
Peak memory 217112 kb
Host smart-a7c465bc-15af-4e79-8efa-b2607f9350a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502868183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.2502868183
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.743747801
Short name T360
Test name
Test status
Simulation time 134778606 ps
CPU time 3.59 seconds
Started Jul 02 09:58:38 AM PDT 24
Finished Jul 02 09:58:42 AM PDT 24
Peak memory 218236 kb
Host smart-d040a400-e977-47d5-a0ab-193f756beae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743747801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.743747801
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.263923741
Short name T786
Test name
Test status
Simulation time 2192847270 ps
CPU time 11.83 seconds
Started Jul 02 09:58:44 AM PDT 24
Finished Jul 02 09:58:57 AM PDT 24
Peak memory 226076 kb
Host smart-2a18920d-ea2a-4414-ba7a-aab8afe4fdba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263923741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_di
gest.263923741
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3009907498
Short name T592
Test name
Test status
Simulation time 1740693588 ps
CPU time 16.81 seconds
Started Jul 02 09:58:25 AM PDT 24
Finished Jul 02 09:58:43 AM PDT 24
Peak memory 218248 kb
Host smart-8f51f17b-6c5f-4eff-b1e4-8336d6b722ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009907498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
3009907498
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.2970906191
Short name T313
Test name
Test status
Simulation time 1261796897 ps
CPU time 10.76 seconds
Started Jul 02 09:58:32 AM PDT 24
Finished Jul 02 09:58:44 AM PDT 24
Peak memory 218272 kb
Host smart-7bd8c8d9-e5a0-48ac-adc6-36e2b83f88a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970906191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.2970906191
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.3175920085
Short name T775
Test name
Test status
Simulation time 15472867 ps
CPU time 1.27 seconds
Started Jul 02 09:58:35 AM PDT 24
Finished Jul 02 09:58:37 AM PDT 24
Peak memory 217896 kb
Host smart-0e13e888-d905-4f5e-bbc3-286b80dc8ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175920085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3175920085
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.4018836033
Short name T797
Test name
Test status
Simulation time 264339067 ps
CPU time 18.29 seconds
Started Jul 02 09:58:21 AM PDT 24
Finished Jul 02 09:58:41 AM PDT 24
Peak memory 250956 kb
Host smart-a2b644c8-8f1f-412d-bdf6-23e09087016e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018836033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.4018836033
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.3503988426
Short name T817
Test name
Test status
Simulation time 46276721 ps
CPU time 7.7 seconds
Started Jul 02 09:58:34 AM PDT 24
Finished Jul 02 09:58:43 AM PDT 24
Peak memory 250976 kb
Host smart-41cdc658-f56e-459a-b5cb-dd0e8bc128b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503988426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3503988426
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.4056705713
Short name T308
Test name
Test status
Simulation time 19116741550 ps
CPU time 566.75 seconds
Started Jul 02 09:58:34 AM PDT 24
Finished Jul 02 10:08:10 AM PDT 24
Peak memory 271260 kb
Host smart-2b1c411b-a245-44de-972a-8af079511894
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056705713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.4056705713
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2856226523
Short name T234
Test name
Test status
Simulation time 45112365 ps
CPU time 0.88 seconds
Started Jul 02 09:58:41 AM PDT 24
Finished Jul 02 09:58:43 AM PDT 24
Peak memory 211880 kb
Host smart-d3cc1c8c-5b55-4052-a1ff-5f1936b83854
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856226523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2856226523
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.189358845
Short name T317
Test name
Test status
Simulation time 33319239 ps
CPU time 0.82 seconds
Started Jul 02 09:58:50 AM PDT 24
Finished Jul 02 09:58:52 AM PDT 24
Peak memory 208740 kb
Host smart-0ac6a948-d94d-4297-9ee0-367e706a7b25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189358845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.189358845
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.1549636366
Short name T280
Test name
Test status
Simulation time 1012810033 ps
CPU time 14.48 seconds
Started Jul 02 09:58:35 AM PDT 24
Finished Jul 02 09:58:50 AM PDT 24
Peak memory 218088 kb
Host smart-b711c5a9-91c6-4513-b3c9-d9738ab2e3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549636366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.1549636366
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2547244463
Short name T400
Test name
Test status
Simulation time 2119239805 ps
CPU time 16.94 seconds
Started Jul 02 09:58:39 AM PDT 24
Finished Jul 02 09:58:57 AM PDT 24
Peak memory 217120 kb
Host smart-55d6efcb-480e-4f2e-a4f3-7b2967717c43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547244463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2547244463
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.3917616650
Short name T393
Test name
Test status
Simulation time 70243061 ps
CPU time 3.69 seconds
Started Jul 02 09:58:51 AM PDT 24
Finished Jul 02 09:58:56 AM PDT 24
Peak memory 218232 kb
Host smart-6b415be8-fa58-42df-90af-c8d7f51e6a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917616650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3917616650
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.356223333
Short name T582
Test name
Test status
Simulation time 301980497 ps
CPU time 12.14 seconds
Started Jul 02 09:58:41 AM PDT 24
Finished Jul 02 09:58:55 AM PDT 24
Peak memory 218244 kb
Host smart-e4efd4e5-ce81-48fd-9ced-38b03b458deb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356223333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di
gest.356223333
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3098356295
Short name T846
Test name
Test status
Simulation time 238626755 ps
CPU time 6.62 seconds
Started Jul 02 09:58:39 AM PDT 24
Finished Jul 02 09:58:46 AM PDT 24
Peak memory 218160 kb
Host smart-7bf7ba98-5694-4c7a-81b5-0088fd25b7d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098356295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
3098356295
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.3029421628
Short name T744
Test name
Test status
Simulation time 256946571 ps
CPU time 9.64 seconds
Started Jul 02 09:58:40 AM PDT 24
Finished Jul 02 09:58:52 AM PDT 24
Peak memory 218364 kb
Host smart-df4ca2ad-1107-4db9-940f-b19c583276cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029421628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3029421628
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1077523152
Short name T300
Test name
Test status
Simulation time 257676933 ps
CPU time 3.41 seconds
Started Jul 02 09:58:40 AM PDT 24
Finished Jul 02 09:58:45 AM PDT 24
Peak memory 222948 kb
Host smart-07d44894-a573-4ca6-ba13-70f5cb543928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077523152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1077523152
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.482691727
Short name T414
Test name
Test status
Simulation time 215531724 ps
CPU time 25.45 seconds
Started Jul 02 09:58:33 AM PDT 24
Finished Jul 02 09:59:00 AM PDT 24
Peak memory 250980 kb
Host smart-45b3883a-c6a0-4e94-a0f3-f63d8788a588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482691727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.482691727
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3245426627
Short name T459
Test name
Test status
Simulation time 78490395 ps
CPU time 7.46 seconds
Started Jul 02 09:58:45 AM PDT 24
Finished Jul 02 09:58:53 AM PDT 24
Peak memory 251016 kb
Host smart-308fa89c-1c23-4032-b801-fe0531bc9d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245426627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3245426627
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.1605983884
Short name T391
Test name
Test status
Simulation time 5995521312 ps
CPU time 56.04 seconds
Started Jul 02 09:58:42 AM PDT 24
Finished Jul 02 09:59:40 AM PDT 24
Peak memory 251056 kb
Host smart-6f976854-054f-4f0f-a802-2ba7f3f22a56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605983884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.1605983884
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.70420958
Short name T68
Test name
Test status
Simulation time 13123848591 ps
CPU time 461.26 seconds
Started Jul 02 09:58:29 AM PDT 24
Finished Jul 02 10:06:11 AM PDT 24
Peak memory 273868 kb
Host smart-41b548de-de59-4a51-9bdd-f5701345c030
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=70420958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.70420958
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3065761460
Short name T714
Test name
Test status
Simulation time 22032029 ps
CPU time 0.98 seconds
Started Jul 02 09:58:48 AM PDT 24
Finished Jul 02 09:58:51 AM PDT 24
Peak memory 211884 kb
Host smart-b331fbf7-1cf2-4781-a65b-e4f4d1aa189e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065761460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3065761460
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.2171402008
Short name T676
Test name
Test status
Simulation time 69614892 ps
CPU time 0.9 seconds
Started Jul 02 09:58:40 AM PDT 24
Finished Jul 02 09:58:42 AM PDT 24
Peak memory 208948 kb
Host smart-cf2f6026-374e-417e-9d5c-c09bf940d957
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171402008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.2171402008
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1673315168
Short name T723
Test name
Test status
Simulation time 1385077541 ps
CPU time 13.09 seconds
Started Jul 02 09:58:45 AM PDT 24
Finished Jul 02 09:59:00 AM PDT 24
Peak memory 218204 kb
Host smart-9ef2add6-5a85-47b7-ad8d-5a2189bdea36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673315168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1673315168
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.361279584
Short name T756
Test name
Test status
Simulation time 1750975445 ps
CPU time 7.11 seconds
Started Jul 02 09:58:37 AM PDT 24
Finished Jul 02 09:58:45 AM PDT 24
Peak memory 217488 kb
Host smart-82e9a1eb-469c-4b6c-95d7-aff62a9c7422
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361279584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.361279584
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1854761375
Short name T204
Test name
Test status
Simulation time 180211520 ps
CPU time 3.47 seconds
Started Jul 02 09:59:04 AM PDT 24
Finished Jul 02 09:59:14 AM PDT 24
Peak memory 218236 kb
Host smart-5351d763-3082-4f5d-a5bd-4bd6a0bb1f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854761375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1854761375
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.1552520119
Short name T521
Test name
Test status
Simulation time 267976360 ps
CPU time 12.54 seconds
Started Jul 02 09:58:44 AM PDT 24
Finished Jul 02 09:58:57 AM PDT 24
Peak memory 219456 kb
Host smart-3b9e154b-2d4b-4647-a1d9-553b3ffa3a15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552520119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.1552520119
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.7043360
Short name T849
Test name
Test status
Simulation time 1433267003 ps
CPU time 8.95 seconds
Started Jul 02 09:58:41 AM PDT 24
Finished Jul 02 09:58:52 AM PDT 24
Peak memory 226056 kb
Host smart-6a47eb4a-479d-4a19-b763-78767ca358bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7043360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dige
st_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_dige
st.7043360
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2557211215
Short name T316
Test name
Test status
Simulation time 949271113 ps
CPU time 8.88 seconds
Started Jul 02 09:58:34 AM PDT 24
Finished Jul 02 09:58:44 AM PDT 24
Peak memory 218224 kb
Host smart-2f99decb-d0f2-4119-a271-2fe2fb38baab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557211215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
2557211215
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.853101755
Short name T699
Test name
Test status
Simulation time 922798827 ps
CPU time 7.4 seconds
Started Jul 02 09:58:46 AM PDT 24
Finished Jul 02 09:58:55 AM PDT 24
Peak memory 224708 kb
Host smart-4b02b73b-4965-4ac8-926c-7eda9e5b3ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853101755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.853101755
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2105076132
Short name T164
Test name
Test status
Simulation time 82857086 ps
CPU time 1.17 seconds
Started Jul 02 09:58:41 AM PDT 24
Finished Jul 02 09:58:43 AM PDT 24
Peak memory 213676 kb
Host smart-36840c00-87c3-43fe-aafa-13ef5831b7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105076132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2105076132
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.3530002822
Short name T303
Test name
Test status
Simulation time 367019253 ps
CPU time 28.76 seconds
Started Jul 02 09:58:50 AM PDT 24
Finished Jul 02 09:59:20 AM PDT 24
Peak memory 249076 kb
Host smart-6ef140b9-b2f5-4b4a-8a7b-d7757e434642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530002822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.3530002822
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.2089112891
Short name T366
Test name
Test status
Simulation time 219174482 ps
CPU time 8.69 seconds
Started Jul 02 09:58:55 AM PDT 24
Finished Jul 02 09:59:05 AM PDT 24
Peak memory 250968 kb
Host smart-e13837ba-7a40-416d-a756-072cc60ed146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089112891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.2089112891
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.867851099
Short name T706
Test name
Test status
Simulation time 6522131970 ps
CPU time 79.91 seconds
Started Jul 02 09:58:55 AM PDT 24
Finished Jul 02 10:00:16 AM PDT 24
Peak memory 253944 kb
Host smart-553e7d3f-0f8e-4c68-8b7f-947f2ea9a5d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867851099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.867851099
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1390347178
Short name T205
Test name
Test status
Simulation time 15416304 ps
CPU time 1 seconds
Started Jul 02 09:58:54 AM PDT 24
Finished Jul 02 09:58:56 AM PDT 24
Peak memory 217756 kb
Host smart-6188cf02-daed-492f-b33c-b5a16f8b4b62
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390347178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.1390347178
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.2363727802
Short name T788
Test name
Test status
Simulation time 20036321 ps
CPU time 1.28 seconds
Started Jul 02 09:58:54 AM PDT 24
Finished Jul 02 09:58:57 AM PDT 24
Peak memory 208964 kb
Host smart-adb84573-69a5-4c71-a5a8-72d7659f6482
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363727802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.2363727802
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.3230456855
Short name T682
Test name
Test status
Simulation time 278665248 ps
CPU time 8.72 seconds
Started Jul 02 09:58:59 AM PDT 24
Finished Jul 02 09:59:13 AM PDT 24
Peak memory 218220 kb
Host smart-ad74ce40-0ae4-4393-947b-494d33a33fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230456855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3230456855
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.227582757
Short name T345
Test name
Test status
Simulation time 8409946410 ps
CPU time 6.2 seconds
Started Jul 02 09:58:52 AM PDT 24
Finished Jul 02 09:58:59 AM PDT 24
Peak memory 217792 kb
Host smart-80b26507-c234-426f-9fea-de4c52ccc485
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227582757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.227582757
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.503180985
Short name T442
Test name
Test status
Simulation time 45173822 ps
CPU time 2.24 seconds
Started Jul 02 09:58:54 AM PDT 24
Finished Jul 02 09:58:57 AM PDT 24
Peak memory 218248 kb
Host smart-49b95e41-c6e8-4452-a026-0f5af3ada0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503180985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.503180985
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.3611935354
Short name T739
Test name
Test status
Simulation time 516551756 ps
CPU time 9.39 seconds
Started Jul 02 09:58:42 AM PDT 24
Finished Jul 02 09:58:53 AM PDT 24
Peak memory 218164 kb
Host smart-a59eb701-d2bb-43d7-a2a6-1e554149144f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611935354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.3611935354
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2618865773
Short name T851
Test name
Test status
Simulation time 422286187 ps
CPU time 12.57 seconds
Started Jul 02 09:58:46 AM PDT 24
Finished Jul 02 09:59:00 AM PDT 24
Peak memory 226072 kb
Host smart-326245af-4cca-4366-9813-7348b68d4cf2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618865773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2618865773
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1083272447
Short name T61
Test name
Test status
Simulation time 1040919815 ps
CPU time 11.99 seconds
Started Jul 02 09:58:48 AM PDT 24
Finished Jul 02 09:59:01 AM PDT 24
Peak memory 218224 kb
Host smart-084a417d-2d08-443d-a917-35591314868f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083272447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1083272447
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.2362159401
Short name T691
Test name
Test status
Simulation time 1072372481 ps
CPU time 9.94 seconds
Started Jul 02 09:58:43 AM PDT 24
Finished Jul 02 09:58:55 AM PDT 24
Peak memory 218340 kb
Host smart-2259a229-4288-4647-82c7-513d3e5db7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362159401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2362159401
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.4148958585
Short name T72
Test name
Test status
Simulation time 52765671 ps
CPU time 2.83 seconds
Started Jul 02 09:58:44 AM PDT 24
Finished Jul 02 09:58:48 AM PDT 24
Peak memory 217704 kb
Host smart-21aac717-35a8-452c-b0aa-6058bdc9ca7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148958585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.4148958585
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3745889953
Short name T841
Test name
Test status
Simulation time 1191415708 ps
CPU time 28.47 seconds
Started Jul 02 09:58:52 AM PDT 24
Finished Jul 02 09:59:22 AM PDT 24
Peak memory 250980 kb
Host smart-a167da6b-2eba-48dd-a592-532f5f4d726a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745889953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3745889953
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.1386778606
Short name T273
Test name
Test status
Simulation time 66768271 ps
CPU time 7.74 seconds
Started Jul 02 09:58:40 AM PDT 24
Finished Jul 02 09:58:49 AM PDT 24
Peak memory 250908 kb
Host smart-5a68d19c-28e1-4806-8952-c9a6d50bf053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386778606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.1386778606
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.3998741652
Short name T77
Test name
Test status
Simulation time 6095278661 ps
CPU time 195.21 seconds
Started Jul 02 09:58:40 AM PDT 24
Finished Jul 02 10:01:56 AM PDT 24
Peak memory 283820 kb
Host smart-68c92a54-51cf-4c43-b0fc-3380e3d0972f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998741652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.3998741652
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.1992501655
Short name T147
Test name
Test status
Simulation time 12440598075 ps
CPU time 298.19 seconds
Started Jul 02 09:58:45 AM PDT 24
Finished Jul 02 10:03:45 AM PDT 24
Peak memory 279052 kb
Host smart-c456a2b8-11f9-4b3e-b694-550ae32fc443
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1992501655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.1992501655
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2194377209
Short name T263
Test name
Test status
Simulation time 15087063 ps
CPU time 0.75 seconds
Started Jul 02 09:58:40 AM PDT 24
Finished Jul 02 09:58:42 AM PDT 24
Peak memory 207448 kb
Host smart-22c110bd-c70a-441e-b517-052d162516c0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194377209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2194377209
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.2174375655
Short name T349
Test name
Test status
Simulation time 33909391 ps
CPU time 1.09 seconds
Started Jul 02 09:58:43 AM PDT 24
Finished Jul 02 09:58:46 AM PDT 24
Peak memory 208960 kb
Host smart-4ac3ddca-458f-48ef-b9b2-375518d6232e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174375655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2174375655
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.104148087
Short name T815
Test name
Test status
Simulation time 584745874 ps
CPU time 9.69 seconds
Started Jul 02 09:58:51 AM PDT 24
Finished Jul 02 09:59:02 AM PDT 24
Peak memory 218248 kb
Host smart-39995ccd-bd32-4fdf-9065-06611351c562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104148087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.104148087
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1268272474
Short name T166
Test name
Test status
Simulation time 1197466568 ps
CPU time 6.9 seconds
Started Jul 02 09:58:39 AM PDT 24
Finished Jul 02 09:58:48 AM PDT 24
Peak memory 217632 kb
Host smart-39859eb7-0e1e-4d6d-ab63-0fa77be7b5d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268272474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1268272474
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.1224045656
Short name T830
Test name
Test status
Simulation time 162919904 ps
CPU time 2.44 seconds
Started Jul 02 09:58:38 AM PDT 24
Finished Jul 02 09:58:41 AM PDT 24
Peak memory 218228 kb
Host smart-2fde13de-9453-4f6d-8cf4-a7cae625be2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224045656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1224045656
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3391588126
Short name T162
Test name
Test status
Simulation time 2874633127 ps
CPU time 10.07 seconds
Started Jul 02 09:59:04 AM PDT 24
Finished Jul 02 09:59:21 AM PDT 24
Peak memory 226108 kb
Host smart-5ab4b833-8819-462c-b128-01c9eea56546
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391588126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.3391588126
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.603859673
Short name T737
Test name
Test status
Simulation time 1312849988 ps
CPU time 8.91 seconds
Started Jul 02 09:58:38 AM PDT 24
Finished Jul 02 09:58:48 AM PDT 24
Peak memory 226244 kb
Host smart-8c3a3c7b-52d1-4d00-8f67-9b6d2e750f76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603859673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.603859673
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.4025992223
Short name T49
Test name
Test status
Simulation time 2845009006 ps
CPU time 11.64 seconds
Started Jul 02 09:58:54 AM PDT 24
Finished Jul 02 09:59:07 AM PDT 24
Peak memory 226108 kb
Host smart-b18d50ab-d3fc-415b-9b6d-f9c3560ba8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025992223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.4025992223
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.1760193222
Short name T779
Test name
Test status
Simulation time 80115585 ps
CPU time 2.99 seconds
Started Jul 02 09:58:41 AM PDT 24
Finished Jul 02 09:58:46 AM PDT 24
Peak memory 217764 kb
Host smart-90019734-a9ef-4bb1-bc84-f567c469a85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760193222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1760193222
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1780120535
Short name T588
Test name
Test status
Simulation time 3456501615 ps
CPU time 35.87 seconds
Started Jul 02 09:59:00 AM PDT 24
Finished Jul 02 09:59:42 AM PDT 24
Peak memory 251064 kb
Host smart-4f46b0be-7353-484b-a61e-a90308f5a50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780120535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1780120535
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.1346721091
Short name T215
Test name
Test status
Simulation time 605744235 ps
CPU time 7.56 seconds
Started Jul 02 09:58:39 AM PDT 24
Finished Jul 02 09:58:47 AM PDT 24
Peak memory 244404 kb
Host smart-a4c49ebf-e749-4de5-b668-ab6e5aa3d944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346721091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1346721091
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.2391524110
Short name T493
Test name
Test status
Simulation time 17055496342 ps
CPU time 143.92 seconds
Started Jul 02 09:58:45 AM PDT 24
Finished Jul 02 10:01:10 AM PDT 24
Peak memory 271560 kb
Host smart-fc1929bb-a078-4891-b205-ed0d3908b1c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391524110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.2391524110
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.691655830
Short name T92
Test name
Test status
Simulation time 210318556070 ps
CPU time 637.6 seconds
Started Jul 02 09:58:44 AM PDT 24
Finished Jul 02 10:09:23 AM PDT 24
Peak memory 275508 kb
Host smart-1106db46-5415-422b-bb53-e0329fb0bb62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=691655830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.691655830
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1870604423
Short name T310
Test name
Test status
Simulation time 71391463 ps
CPU time 0.97 seconds
Started Jul 02 09:58:42 AM PDT 24
Finished Jul 02 09:58:45 AM PDT 24
Peak memory 211932 kb
Host smart-48b0bc9c-2eac-4b17-aabc-c8bd0a83fc23
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870604423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1870604423
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.3941956510
Short name T734
Test name
Test status
Simulation time 96583261 ps
CPU time 0.96 seconds
Started Jul 02 09:59:05 AM PDT 24
Finished Jul 02 09:59:13 AM PDT 24
Peak memory 208988 kb
Host smart-fcbf9d95-8d8d-40ce-b194-2f67fa1c8f9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941956510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3941956510
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.241598239
Short name T367
Test name
Test status
Simulation time 584913950 ps
CPU time 13.73 seconds
Started Jul 02 09:59:12 AM PDT 24
Finished Jul 02 09:59:33 AM PDT 24
Peak memory 226012 kb
Host smart-9a046eda-2162-4533-806e-d069ba8e9b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241598239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.241598239
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.2591178125
Short name T731
Test name
Test status
Simulation time 604760695 ps
CPU time 2.8 seconds
Started Jul 02 09:58:47 AM PDT 24
Finished Jul 02 09:58:51 AM PDT 24
Peak memory 217100 kb
Host smart-85b17b3e-f219-4424-acd4-7bec6c46d5cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591178125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.2591178125
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.1268540691
Short name T481
Test name
Test status
Simulation time 280611906 ps
CPU time 3.71 seconds
Started Jul 02 09:59:01 AM PDT 24
Finished Jul 02 09:59:10 AM PDT 24
Peak memory 222520 kb
Host smart-44b34ee8-f8b2-417f-89fb-6f281686c59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268540691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.1268540691
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.2560027300
Short name T539
Test name
Test status
Simulation time 350920434 ps
CPU time 15.84 seconds
Started Jul 02 09:58:55 AM PDT 24
Finished Jul 02 09:59:12 AM PDT 24
Peak memory 218900 kb
Host smart-0fe80129-3fa0-468c-9372-ed238ed4628b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560027300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2560027300
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2353084696
Short name T356
Test name
Test status
Simulation time 538636885 ps
CPU time 12.07 seconds
Started Jul 02 09:58:48 AM PDT 24
Finished Jul 02 09:59:02 AM PDT 24
Peak memory 226016 kb
Host smart-5aac7bfc-dc1c-408a-99d0-6ab557e1acd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353084696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2353084696
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.4279753433
Short name T381
Test name
Test status
Simulation time 1320263922 ps
CPU time 12.49 seconds
Started Jul 02 09:58:53 AM PDT 24
Finished Jul 02 09:59:07 AM PDT 24
Peak memory 226068 kb
Host smart-45376321-139e-4ca5-992c-54db488b74ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279753433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
4279753433
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.411263459
Short name T585
Test name
Test status
Simulation time 1924207057 ps
CPU time 9.53 seconds
Started Jul 02 09:58:48 AM PDT 24
Finished Jul 02 09:58:59 AM PDT 24
Peak memory 218264 kb
Host smart-51057d01-fd12-4a9d-a09e-ff5997563603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411263459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.411263459
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.2451888230
Short name T751
Test name
Test status
Simulation time 131829093 ps
CPU time 1.67 seconds
Started Jul 02 09:59:01 AM PDT 24
Finished Jul 02 09:59:08 AM PDT 24
Peak memory 214104 kb
Host smart-a2e01b5e-4a36-4b9d-b299-6a96d0c64022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451888230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2451888230
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.985707775
Short name T514
Test name
Test status
Simulation time 822295325 ps
CPU time 27.07 seconds
Started Jul 02 09:58:49 AM PDT 24
Finished Jul 02 09:59:18 AM PDT 24
Peak memory 250952 kb
Host smart-cf1608d5-df18-42b6-b487-dca6e56ce269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985707775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.985707775
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.712320930
Short name T843
Test name
Test status
Simulation time 88707454 ps
CPU time 3.71 seconds
Started Jul 02 09:58:50 AM PDT 24
Finished Jul 02 09:58:55 AM PDT 24
Peak memory 226428 kb
Host smart-ed55ffa3-fb46-4d3c-a3b9-f14f26ebefe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712320930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.712320930
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3294512397
Short name T821
Test name
Test status
Simulation time 6021235556 ps
CPU time 69.44 seconds
Started Jul 02 09:58:40 AM PDT 24
Finished Jul 02 09:59:51 AM PDT 24
Peak memory 246868 kb
Host smart-a3efa5be-177f-4111-b79e-ce79d238de65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294512397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3294512397
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2291728763
Short name T214
Test name
Test status
Simulation time 41629034 ps
CPU time 0.93 seconds
Started Jul 02 09:58:40 AM PDT 24
Finished Jul 02 09:58:42 AM PDT 24
Peak memory 211960 kb
Host smart-97c0a065-ebdd-4ff6-b99a-8191358499e2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291728763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2291728763
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1191925782
Short name T261
Test name
Test status
Simulation time 59207249 ps
CPU time 0.93 seconds
Started Jul 02 09:59:05 AM PDT 24
Finished Jul 02 09:59:13 AM PDT 24
Peak memory 209048 kb
Host smart-eeaeb792-4b44-4b5b-b7fe-eac7dc587972
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191925782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1191925782
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3048037620
Short name T762
Test name
Test status
Simulation time 1903667317 ps
CPU time 13.54 seconds
Started Jul 02 09:58:41 AM PDT 24
Finished Jul 02 09:58:56 AM PDT 24
Peak memory 226016 kb
Host smart-c4c0eb90-73bb-47ed-8bb5-09a8c1de6fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048037620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3048037620
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.16653682
Short name T553
Test name
Test status
Simulation time 875635533 ps
CPU time 3.15 seconds
Started Jul 02 09:58:54 AM PDT 24
Finished Jul 02 09:58:58 AM PDT 24
Peak memory 217112 kb
Host smart-ef7ccd99-4312-456e-b6a4-a938f9b1e4fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16653682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.16653682
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.3227628101
Short name T766
Test name
Test status
Simulation time 171914032 ps
CPU time 2.55 seconds
Started Jul 02 09:58:53 AM PDT 24
Finished Jul 02 09:58:56 AM PDT 24
Peak memory 218232 kb
Host smart-af2577a5-f3c5-4a38-9b7b-1998c18f0e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227628101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3227628101
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.4000824395
Short name T749
Test name
Test status
Simulation time 893550021 ps
CPU time 15.37 seconds
Started Jul 02 09:59:13 AM PDT 24
Finished Jul 02 09:59:35 AM PDT 24
Peak memory 226064 kb
Host smart-d4946cb3-5c5a-478f-a2a6-8579d664e834
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000824395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.4000824395
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.92001760
Short name T382
Test name
Test status
Simulation time 681537838 ps
CPU time 12.53 seconds
Started Jul 02 09:58:52 AM PDT 24
Finished Jul 02 09:59:06 AM PDT 24
Peak memory 226016 kb
Host smart-043d5a4e-4e27-460b-ae4a-fa830d30c847
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92001760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.92001760
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2280937878
Short name T760
Test name
Test status
Simulation time 462437042 ps
CPU time 9.17 seconds
Started Jul 02 09:58:51 AM PDT 24
Finished Jul 02 09:59:02 AM PDT 24
Peak memory 218264 kb
Host smart-9fadb04e-c047-423c-a3af-5eed802f566f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280937878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2280937878
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.4123313629
Short name T271
Test name
Test status
Simulation time 45304382 ps
CPU time 2.1 seconds
Started Jul 02 09:58:46 AM PDT 24
Finished Jul 02 09:58:49 AM PDT 24
Peak memory 214332 kb
Host smart-8dae54ba-b37d-4338-a5d0-5ea6d2a4cccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123313629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.4123313629
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.2172877516
Short name T236
Test name
Test status
Simulation time 323203684 ps
CPU time 24.9 seconds
Started Jul 02 09:58:59 AM PDT 24
Finished Jul 02 09:59:29 AM PDT 24
Peak memory 250976 kb
Host smart-b5fe2fed-5536-4219-88bd-24d3b6e135e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172877516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2172877516
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.3949782877
Short name T445
Test name
Test status
Simulation time 180068957 ps
CPU time 8.95 seconds
Started Jul 02 09:58:51 AM PDT 24
Finished Jul 02 09:59:02 AM PDT 24
Peak memory 250968 kb
Host smart-977beeb7-7caf-442f-b077-fd163e0d1c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949782877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3949782877
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3911709729
Short name T609
Test name
Test status
Simulation time 4158364043 ps
CPU time 160.45 seconds
Started Jul 02 09:59:10 AM PDT 24
Finished Jul 02 10:01:57 AM PDT 24
Peak memory 283020 kb
Host smart-0219cb78-f0d5-4897-b001-e5836ae55a1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911709729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3911709729
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3261444395
Short name T808
Test name
Test status
Simulation time 12282337 ps
CPU time 1.06 seconds
Started Jul 02 09:59:03 AM PDT 24
Finished Jul 02 09:59:11 AM PDT 24
Peak memory 211848 kb
Host smart-6c3edf38-1299-447e-9f41-dd77d01f29b2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261444395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3261444395
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.1736271028
Short name T443
Test name
Test status
Simulation time 18760980 ps
CPU time 0.91 seconds
Started Jul 02 09:59:03 AM PDT 24
Finished Jul 02 09:59:11 AM PDT 24
Peak memory 209012 kb
Host smart-1a6acf35-7d0c-4919-88da-d9785d151588
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736271028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.1736271028
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.2703523892
Short name T333
Test name
Test status
Simulation time 242627326 ps
CPU time 8.37 seconds
Started Jul 02 09:59:01 AM PDT 24
Finished Jul 02 09:59:15 AM PDT 24
Peak memory 218180 kb
Host smart-7df91332-76b0-49a8-ad32-2fd5f12e3ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703523892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2703523892
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.3804809123
Short name T167
Test name
Test status
Simulation time 525541017 ps
CPU time 4.19 seconds
Started Jul 02 09:58:49 AM PDT 24
Finished Jul 02 09:58:55 AM PDT 24
Peak memory 217692 kb
Host smart-bd206836-df9b-4e06-b486-c2b93cfa9c6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804809123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.3804809123
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.4174936318
Short name T504
Test name
Test status
Simulation time 23667563 ps
CPU time 1.94 seconds
Started Jul 02 09:58:54 AM PDT 24
Finished Jul 02 09:58:58 AM PDT 24
Peak memory 218204 kb
Host smart-62ca45d7-5d1d-449a-8011-a3a6215b7cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174936318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.4174936318
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.280335280
Short name T39
Test name
Test status
Simulation time 863125183 ps
CPU time 16.88 seconds
Started Jul 02 09:58:58 AM PDT 24
Finished Jul 02 09:59:17 AM PDT 24
Peak memory 219064 kb
Host smart-cb499cc9-5663-49db-be55-7deb47daa253
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280335280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.280335280
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.317103540
Short name T532
Test name
Test status
Simulation time 332887231 ps
CPU time 9.48 seconds
Started Jul 02 09:59:08 AM PDT 24
Finished Jul 02 09:59:24 AM PDT 24
Peak memory 226028 kb
Host smart-4d1ab039-080b-4124-86b5-3dc4da2f9d12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317103540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_di
gest.317103540
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1187185155
Short name T302
Test name
Test status
Simulation time 207995183 ps
CPU time 8.77 seconds
Started Jul 02 09:59:02 AM PDT 24
Finished Jul 02 09:59:17 AM PDT 24
Peak memory 226244 kb
Host smart-b3da743c-376c-41f0-a2c6-1c9e822f07d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187185155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
1187185155
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.321739750
Short name T339
Test name
Test status
Simulation time 1502968032 ps
CPU time 8.84 seconds
Started Jul 02 09:59:09 AM PDT 24
Finished Jul 02 09:59:25 AM PDT 24
Peak memory 225376 kb
Host smart-e8868a7c-02f3-4b4b-b953-e7ce47c53bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321739750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.321739750
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.3435634826
Short name T239
Test name
Test status
Simulation time 66865905 ps
CPU time 4.05 seconds
Started Jul 02 09:58:47 AM PDT 24
Finished Jul 02 09:58:53 AM PDT 24
Peak memory 217728 kb
Host smart-77d4e792-2dfc-45a2-a8ab-c440b9bf8747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435634826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.3435634826
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.2170279899
Short name T207
Test name
Test status
Simulation time 269607796 ps
CPU time 19.17 seconds
Started Jul 02 09:59:01 AM PDT 24
Finished Jul 02 09:59:26 AM PDT 24
Peak memory 250980 kb
Host smart-050fe347-c39b-4cc7-bad2-b197670b8acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170279899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2170279899
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.4245701118
Short name T832
Test name
Test status
Simulation time 1369160244 ps
CPU time 7.99 seconds
Started Jul 02 09:58:47 AM PDT 24
Finished Jul 02 09:58:57 AM PDT 24
Peak memory 250904 kb
Host smart-c9f24591-3097-48b5-bf91-8943c30837fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245701118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.4245701118
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.4132539422
Short name T822
Test name
Test status
Simulation time 1307848044 ps
CPU time 30.68 seconds
Started Jul 02 09:59:09 AM PDT 24
Finished Jul 02 09:59:47 AM PDT 24
Peak memory 250580 kb
Host smart-3e89dc4d-3284-4593-a53a-c5311d8395ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132539422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.4132539422
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.221323104
Short name T546
Test name
Test status
Simulation time 48520582 ps
CPU time 0.94 seconds
Started Jul 02 09:59:00 AM PDT 24
Finished Jul 02 09:59:06 AM PDT 24
Peak memory 213096 kb
Host smart-df79daea-d951-4939-80c4-274252451b9b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221323104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct
rl_volatile_unlock_smoke.221323104
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.3460261564
Short name T645
Test name
Test status
Simulation time 26749879 ps
CPU time 1 seconds
Started Jul 02 09:57:52 AM PDT 24
Finished Jul 02 09:57:56 AM PDT 24
Peak memory 208948 kb
Host smart-4032b343-3f5a-471a-9b01-2a1933218d23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460261564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3460261564
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.542067025
Short name T710
Test name
Test status
Simulation time 276158399 ps
CPU time 13.75 seconds
Started Jul 02 09:57:47 AM PDT 24
Finished Jul 02 09:58:03 AM PDT 24
Peak memory 218176 kb
Host smart-483d8bdf-0d7d-4d9a-afd3-1ee83232942c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542067025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.542067025
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3257557564
Short name T168
Test name
Test status
Simulation time 522350471 ps
CPU time 2.24 seconds
Started Jul 02 09:58:04 AM PDT 24
Finished Jul 02 09:58:12 AM PDT 24
Peak memory 217108 kb
Host smart-6b506bdc-374c-409a-99b6-cf276701b313
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257557564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3257557564
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.1950191638
Short name T573
Test name
Test status
Simulation time 1115676050 ps
CPU time 19.76 seconds
Started Jul 02 09:57:57 AM PDT 24
Finished Jul 02 09:58:19 AM PDT 24
Peak memory 225608 kb
Host smart-d9a18442-04ae-4bff-94b2-e44246d46d16
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950191638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.1950191638
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.2213511923
Short name T598
Test name
Test status
Simulation time 1076242684 ps
CPU time 7.04 seconds
Started Jul 02 09:57:48 AM PDT 24
Finished Jul 02 09:57:57 AM PDT 24
Peak memory 217736 kb
Host smart-0ac14c9d-79bd-4614-b325-335b128f7ff5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213511923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.2
213511923
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1896896049
Short name T22
Test name
Test status
Simulation time 2377026592 ps
CPU time 7.37 seconds
Started Jul 02 09:57:58 AM PDT 24
Finished Jul 02 09:58:08 AM PDT 24
Peak memory 218300 kb
Host smart-6420f40c-820f-404b-ab9b-0cb59151e2f7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896896049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1896896049
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1052972274
Short name T401
Test name
Test status
Simulation time 874350582 ps
CPU time 11.1 seconds
Started Jul 02 09:58:03 AM PDT 24
Finished Jul 02 09:58:21 AM PDT 24
Peak memory 217720 kb
Host smart-daf4d858-3696-4d00-9d7b-3bb3a3f6988f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052972274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1052972274
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.3256106427
Short name T384
Test name
Test status
Simulation time 374326773 ps
CPU time 2 seconds
Started Jul 02 09:57:48 AM PDT 24
Finished Jul 02 09:57:52 AM PDT 24
Peak memory 217736 kb
Host smart-f0868d9f-31c6-46fe-b525-e62013d38111
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256106427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
3256106427
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2337469955
Short name T87
Test name
Test status
Simulation time 4715425335 ps
CPU time 49.27 seconds
Started Jul 02 09:57:57 AM PDT 24
Finished Jul 02 09:58:49 AM PDT 24
Peak memory 252340 kb
Host smart-17ed0603-0198-4fb0-910a-3f2692dc91f8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337469955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2337469955
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.355855623
Short name T298
Test name
Test status
Simulation time 302119325 ps
CPU time 13.9 seconds
Started Jul 02 09:57:54 AM PDT 24
Finished Jul 02 09:58:11 AM PDT 24
Peak memory 250984 kb
Host smart-dd543ea7-afc7-4bff-bb82-ce4ef4866a5a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355855623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.355855623
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.907482760
Short name T818
Test name
Test status
Simulation time 54804281 ps
CPU time 1.52 seconds
Started Jul 02 09:57:58 AM PDT 24
Finished Jul 02 09:58:02 AM PDT 24
Peak memory 218200 kb
Host smart-96ce61e6-5807-42b3-a4d6-e76b69711e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907482760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.907482760
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1734578087
Short name T251
Test name
Test status
Simulation time 325940087 ps
CPU time 8.63 seconds
Started Jul 02 09:57:50 AM PDT 24
Finished Jul 02 09:58:01 AM PDT 24
Peak memory 214624 kb
Host smart-238039a3-0cb3-47f1-b38b-ba2960d9e443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734578087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1734578087
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.875495208
Short name T93
Test name
Test status
Simulation time 208294992 ps
CPU time 35.91 seconds
Started Jul 02 09:57:50 AM PDT 24
Finished Jul 02 09:58:29 AM PDT 24
Peak memory 281704 kb
Host smart-5f8f0976-5333-42ae-9276-bd2a84ebceb2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875495208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.875495208
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.369881168
Short name T767
Test name
Test status
Simulation time 1545222312 ps
CPU time 17.31 seconds
Started Jul 02 09:57:48 AM PDT 24
Finished Jul 02 09:58:08 AM PDT 24
Peak memory 226068 kb
Host smart-50c399f4-f834-41aa-a378-0875566f1412
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369881168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.369881168
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.874627356
Short name T398
Test name
Test status
Simulation time 1202184398 ps
CPU time 12.36 seconds
Started Jul 02 09:57:55 AM PDT 24
Finished Jul 02 09:58:10 AM PDT 24
Peak memory 226104 kb
Host smart-3609ac65-1c5d-451c-89b6-91cda6479caf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874627356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_dig
est.874627356
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.2252532219
Short name T156
Test name
Test status
Simulation time 220839079 ps
CPU time 8.47 seconds
Started Jul 02 09:58:08 AM PDT 24
Finished Jul 02 09:58:23 AM PDT 24
Peak memory 226020 kb
Host smart-7e3c89e0-dc6b-48e1-b4cf-f4bf7a1f6463
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252532219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.2
252532219
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.2485288318
Short name T50
Test name
Test status
Simulation time 267714875 ps
CPU time 6.85 seconds
Started Jul 02 09:57:54 AM PDT 24
Finished Jul 02 09:58:04 AM PDT 24
Peak memory 218268 kb
Host smart-82b21e6c-fdfb-4703-8d08-a483eb687f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485288318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.2485288318
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.4118012424
Short name T449
Test name
Test status
Simulation time 75675839 ps
CPU time 1.68 seconds
Started Jul 02 09:57:49 AM PDT 24
Finished Jul 02 09:57:53 AM PDT 24
Peak memory 217644 kb
Host smart-99de4df4-73e1-4de8-902a-c3bfa0cfab7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118012424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.4118012424
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.2778799008
Short name T379
Test name
Test status
Simulation time 660936194 ps
CPU time 17.53 seconds
Started Jul 02 09:57:38 AM PDT 24
Finished Jul 02 09:57:58 AM PDT 24
Peak memory 243992 kb
Host smart-fb8ebe4c-ac0f-4d3b-804c-092f6fb0562b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778799008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2778799008
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.4057136851
Short name T597
Test name
Test status
Simulation time 52071496 ps
CPU time 6.04 seconds
Started Jul 02 09:57:52 AM PDT 24
Finished Jul 02 09:58:01 AM PDT 24
Peak memory 246272 kb
Host smart-0c68766f-3eaa-48d9-926e-d94d361fe76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057136851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.4057136851
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3090881742
Short name T560
Test name
Test status
Simulation time 2246161135 ps
CPU time 40.68 seconds
Started Jul 02 09:58:01 AM PDT 24
Finished Jul 02 09:58:44 AM PDT 24
Peak memory 226016 kb
Host smart-2c9024c2-abd7-4ec6-8bf7-47649cbb2b00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090881742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3090881742
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.1166635182
Short name T43
Test name
Test status
Simulation time 15045524973 ps
CPU time 319.18 seconds
Started Jul 02 09:58:00 AM PDT 24
Finished Jul 02 10:03:21 AM PDT 24
Peak memory 283932 kb
Host smart-a2dcee9f-a4f1-4915-92e0-c412aac3def0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1166635182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.1166635182
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2919461528
Short name T307
Test name
Test status
Simulation time 25406270 ps
CPU time 0.88 seconds
Started Jul 02 09:57:50 AM PDT 24
Finished Jul 02 09:57:54 AM PDT 24
Peak memory 211832 kb
Host smart-9232ba73-8f10-48c9-98b1-e782ae67fbf1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919461528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2919461528
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.2394973320
Short name T282
Test name
Test status
Simulation time 355431593 ps
CPU time 1.15 seconds
Started Jul 02 09:58:49 AM PDT 24
Finished Jul 02 09:58:52 AM PDT 24
Peak memory 209008 kb
Host smart-73aba78b-ede7-47f7-95f2-cf9b28b9e02d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394973320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2394973320
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.2122033419
Short name T665
Test name
Test status
Simulation time 2500843635 ps
CPU time 16.36 seconds
Started Jul 02 09:58:59 AM PDT 24
Finished Jul 02 09:59:20 AM PDT 24
Peak memory 218144 kb
Host smart-25fcec0f-9f4e-4dcd-9e8b-ed2fa02fde10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122033419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2122033419
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.2182100883
Short name T46
Test name
Test status
Simulation time 434254339 ps
CPU time 2.67 seconds
Started Jul 02 09:58:53 AM PDT 24
Finished Jul 02 09:58:56 AM PDT 24
Peak memory 217692 kb
Host smart-9427247b-1a45-4bb9-adf9-3fb7f2336062
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182100883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.2182100883
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.4167905383
Short name T590
Test name
Test status
Simulation time 285222365 ps
CPU time 2.69 seconds
Started Jul 02 09:58:59 AM PDT 24
Finished Jul 02 09:59:07 AM PDT 24
Peak memory 218100 kb
Host smart-3a0a8241-575a-42ee-bd69-7164051ab0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167905383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.4167905383
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.2826549975
Short name T314
Test name
Test status
Simulation time 679648819 ps
CPU time 13.82 seconds
Started Jul 02 09:58:48 AM PDT 24
Finished Jul 02 09:59:04 AM PDT 24
Peak memory 226020 kb
Host smart-3f2da90d-bac2-45a3-ae11-4a4274ebfc89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826549975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.2826549975
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1184847091
Short name T502
Test name
Test status
Simulation time 942185906 ps
CPU time 8.73 seconds
Started Jul 02 09:58:59 AM PDT 24
Finished Jul 02 09:59:12 AM PDT 24
Peak memory 218256 kb
Host smart-7aee92ca-e999-4e37-8f04-0597413a60e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184847091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1184847091
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.3456404714
Short name T562
Test name
Test status
Simulation time 41012585 ps
CPU time 2.93 seconds
Started Jul 02 09:58:42 AM PDT 24
Finished Jul 02 09:58:46 AM PDT 24
Peak memory 214480 kb
Host smart-b859b5cf-8ec8-429c-9bc3-c1eba1745aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456404714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3456404714
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.949454226
Short name T496
Test name
Test status
Simulation time 275311339 ps
CPU time 17.66 seconds
Started Jul 02 09:58:57 AM PDT 24
Finished Jul 02 09:59:16 AM PDT 24
Peak memory 251064 kb
Host smart-b0a46459-33d4-476d-8f53-442c92fb2b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949454226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.949454226
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.1678062375
Short name T256
Test name
Test status
Simulation time 311782989 ps
CPU time 7.39 seconds
Started Jul 02 09:59:13 AM PDT 24
Finished Jul 02 09:59:27 AM PDT 24
Peak memory 250952 kb
Host smart-4218e1c3-5998-4771-a354-5455555a4d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678062375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.1678062375
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.810576345
Short name T82
Test name
Test status
Simulation time 2028571880 ps
CPU time 37.55 seconds
Started Jul 02 09:59:06 AM PDT 24
Finished Jul 02 09:59:51 AM PDT 24
Peak memory 249384 kb
Host smart-7c9ad81f-a0f1-407f-9fe7-89fe07a71707
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810576345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.810576345
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.3791221813
Short name T144
Test name
Test status
Simulation time 31221961859 ps
CPU time 1010.33 seconds
Started Jul 02 09:59:02 AM PDT 24
Finished Jul 02 10:15:59 AM PDT 24
Peak memory 308524 kb
Host smart-c5d1375a-85e3-48e7-88e1-bed958dbce73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3791221813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.3791221813
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1776504895
Short name T187
Test name
Test status
Simulation time 15005473 ps
CPU time 1.08 seconds
Started Jul 02 09:59:02 AM PDT 24
Finished Jul 02 09:59:10 AM PDT 24
Peak memory 211864 kb
Host smart-f098c069-c563-494d-a881-e6c170ef45f2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776504895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.1776504895
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.1287068951
Short name T632
Test name
Test status
Simulation time 66519386 ps
CPU time 0.93 seconds
Started Jul 02 09:58:50 AM PDT 24
Finished Jul 02 09:58:53 AM PDT 24
Peak memory 208992 kb
Host smart-d443579d-0b59-4f04-9aab-55226867188d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287068951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1287068951
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.2127432246
Short name T623
Test name
Test status
Simulation time 244915980 ps
CPU time 9.61 seconds
Started Jul 02 09:59:05 AM PDT 24
Finished Jul 02 09:59:22 AM PDT 24
Peak memory 218236 kb
Host smart-23e54d04-877e-4831-a803-b7d3b1be3b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127432246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.2127432246
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.1278207116
Short name T763
Test name
Test status
Simulation time 425926171 ps
CPU time 11.42 seconds
Started Jul 02 09:59:11 AM PDT 24
Finished Jul 02 09:59:29 AM PDT 24
Peak memory 217620 kb
Host smart-90f05e19-8807-4134-96ca-c30b2050757e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278207116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.1278207116
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3480627110
Short name T200
Test name
Test status
Simulation time 34321345 ps
CPU time 2.29 seconds
Started Jul 02 09:58:42 AM PDT 24
Finished Jul 02 09:58:45 AM PDT 24
Peak memory 218228 kb
Host smart-bfae125a-8b76-4c09-ab02-1812399b98cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480627110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3480627110
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.374991342
Short name T249
Test name
Test status
Simulation time 8677458786 ps
CPU time 19.07 seconds
Started Jul 02 09:58:45 AM PDT 24
Finished Jul 02 09:59:05 AM PDT 24
Peak memory 226120 kb
Host smart-f42a147d-4ff0-4a95-8ab4-43b97c283be2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374991342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.374991342
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1776408517
Short name T680
Test name
Test status
Simulation time 1050023890 ps
CPU time 11.95 seconds
Started Jul 02 09:59:08 AM PDT 24
Finished Jul 02 09:59:27 AM PDT 24
Peak memory 226000 kb
Host smart-f12cbc9b-ab26-4d21-a199-6c618caa62ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776408517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.1776408517
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3823953639
Short name T837
Test name
Test status
Simulation time 281325548 ps
CPU time 7.57 seconds
Started Jul 02 09:58:58 AM PDT 24
Finished Jul 02 09:59:08 AM PDT 24
Peak memory 218220 kb
Host smart-8c06463d-e022-47bc-a7c7-74c2641d042c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823953639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
3823953639
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.853848356
Short name T355
Test name
Test status
Simulation time 983741159 ps
CPU time 9.92 seconds
Started Jul 02 09:59:12 AM PDT 24
Finished Jul 02 09:59:32 AM PDT 24
Peak memory 225992 kb
Host smart-78b240b8-5e21-4eba-976f-27cb1b7dd4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853848356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.853848356
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.2637224445
Short name T835
Test name
Test status
Simulation time 57971482 ps
CPU time 3.08 seconds
Started Jul 02 09:58:57 AM PDT 24
Finished Jul 02 09:59:02 AM PDT 24
Peak memory 214800 kb
Host smart-38a0b607-cc0c-4e5a-aa5b-c86b4cbaee03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637224445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2637224445
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.3742469740
Short name T270
Test name
Test status
Simulation time 239331907 ps
CPU time 17.8 seconds
Started Jul 02 09:59:01 AM PDT 24
Finished Jul 02 09:59:24 AM PDT 24
Peak memory 251000 kb
Host smart-3e79396d-7242-4430-8cf1-f32935e1fd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742469740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.3742469740
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3609738332
Short name T411
Test name
Test status
Simulation time 247045961 ps
CPU time 3.33 seconds
Started Jul 02 09:59:01 AM PDT 24
Finished Jul 02 09:59:11 AM PDT 24
Peak memory 222408 kb
Host smart-dddc2046-5a89-4d4b-8cfa-112f5ea95546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609738332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3609738332
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.1200075262
Short name T140
Test name
Test status
Simulation time 20463054765 ps
CPU time 675.26 seconds
Started Jul 02 09:58:59 AM PDT 24
Finished Jul 02 10:10:19 AM PDT 24
Peak memory 520620 kb
Host smart-f7125170-ff5e-4cf8-ae8a-61fe289418ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1200075262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.1200075262
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.4210297096
Short name T479
Test name
Test status
Simulation time 45031650 ps
CPU time 0.96 seconds
Started Jul 02 09:59:01 AM PDT 24
Finished Jul 02 09:59:08 AM PDT 24
Peak memory 211976 kb
Host smart-432a8375-8e3f-462f-8ba8-253a00de2476
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210297096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.4210297096
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3276501103
Short name T772
Test name
Test status
Simulation time 50235427 ps
CPU time 1.03 seconds
Started Jul 02 09:59:02 AM PDT 24
Finished Jul 02 09:59:10 AM PDT 24
Peak memory 209068 kb
Host smart-be68a6e4-b6d8-4fcf-9f67-acb3d690cdf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276501103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3276501103
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2808004253
Short name T608
Test name
Test status
Simulation time 509205759 ps
CPU time 14.37 seconds
Started Jul 02 09:58:41 AM PDT 24
Finished Jul 02 09:59:03 AM PDT 24
Peak memory 218148 kb
Host smart-bd657fe6-a43d-40c6-9a07-1904a9b0e5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808004253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2808004253
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.1043944454
Short name T28
Test name
Test status
Simulation time 295285514 ps
CPU time 4.48 seconds
Started Jul 02 09:59:10 AM PDT 24
Finished Jul 02 09:59:21 AM PDT 24
Peak memory 217360 kb
Host smart-58b749ec-dc6e-4c5b-85ea-c40be64c9dd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043944454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.1043944454
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.326762967
Short name T494
Test name
Test status
Simulation time 100766008 ps
CPU time 2.13 seconds
Started Jul 02 09:59:00 AM PDT 24
Finished Jul 02 09:59:07 AM PDT 24
Peak memory 218156 kb
Host smart-82771da8-bafe-4139-a865-1bb7aad4631e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326762967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.326762967
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.3551770501
Short name T612
Test name
Test status
Simulation time 807742622 ps
CPU time 8.38 seconds
Started Jul 02 09:59:01 AM PDT 24
Finished Jul 02 09:59:17 AM PDT 24
Peak memory 226056 kb
Host smart-76c41a88-1eef-4337-aa5f-5a9d30f68ed4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551770501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.3551770501
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.2094139810
Short name T268
Test name
Test status
Simulation time 420486562 ps
CPU time 10.92 seconds
Started Jul 02 09:58:53 AM PDT 24
Finished Jul 02 09:59:05 AM PDT 24
Peak memory 226056 kb
Host smart-847789a6-e152-443e-bb79-b79896e2c883
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094139810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
2094139810
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.2132737194
Short name T250
Test name
Test status
Simulation time 587999255 ps
CPU time 6.2 seconds
Started Jul 02 09:58:59 AM PDT 24
Finished Jul 02 09:59:10 AM PDT 24
Peak memory 225044 kb
Host smart-d3a0a9b6-d67a-490f-af96-d064e1d936ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132737194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.2132737194
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.3862559503
Short name T614
Test name
Test status
Simulation time 15081880 ps
CPU time 1.23 seconds
Started Jul 02 09:58:53 AM PDT 24
Finished Jul 02 09:58:56 AM PDT 24
Peak memory 212244 kb
Host smart-9990b8c9-6356-492e-852e-459eac9ac8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862559503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3862559503
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3396350702
Short name T694
Test name
Test status
Simulation time 926457375 ps
CPU time 30.14 seconds
Started Jul 02 09:58:53 AM PDT 24
Finished Jul 02 09:59:24 AM PDT 24
Peak memory 251104 kb
Host smart-2447ee7b-3229-4397-92e2-018d9dcf78a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396350702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3396350702
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.552622671
Short name T685
Test name
Test status
Simulation time 908628834 ps
CPU time 9.68 seconds
Started Jul 02 09:58:53 AM PDT 24
Finished Jul 02 09:59:04 AM PDT 24
Peak memory 250996 kb
Host smart-9b67defd-2570-43ee-a97f-21e5c70c4a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552622671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.552622671
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.2243066786
Short name T587
Test name
Test status
Simulation time 5104610838 ps
CPU time 71.97 seconds
Started Jul 02 09:58:59 AM PDT 24
Finished Jul 02 10:00:16 AM PDT 24
Peak memory 218512 kb
Host smart-f19504cd-ae13-4f28-b633-fe06a0554adc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243066786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.2243066786
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.1945322647
Short name T444
Test name
Test status
Simulation time 66956299552 ps
CPU time 1040.09 seconds
Started Jul 02 09:58:59 AM PDT 24
Finished Jul 02 10:16:25 AM PDT 24
Peak memory 611464 kb
Host smart-02adbadc-38d7-4984-9c1d-0f2b5236c9f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1945322647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.1945322647
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2076989755
Short name T611
Test name
Test status
Simulation time 24220539 ps
CPU time 0.99 seconds
Started Jul 02 09:58:58 AM PDT 24
Finished Jul 02 09:59:02 AM PDT 24
Peak memory 212932 kb
Host smart-0d4031b6-a20b-4c67-ad68-5b8ee8f7107c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076989755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.2076989755
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3848776973
Short name T73
Test name
Test status
Simulation time 60406296 ps
CPU time 1.34 seconds
Started Jul 02 09:58:49 AM PDT 24
Finished Jul 02 09:58:52 AM PDT 24
Peak memory 208996 kb
Host smart-244651d4-7fb8-4a51-bf4a-1ea622d14685
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848776973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3848776973
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3488469401
Short name T631
Test name
Test status
Simulation time 174399269 ps
CPU time 9.22 seconds
Started Jul 02 09:58:57 AM PDT 24
Finished Jul 02 09:59:08 AM PDT 24
Peak memory 218116 kb
Host smart-2184d100-6502-4807-82dc-f8cd8ec3914f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488469401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3488469401
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.4213627826
Short name T422
Test name
Test status
Simulation time 4099142091 ps
CPU time 24.18 seconds
Started Jul 02 09:59:03 AM PDT 24
Finished Jul 02 09:59:34 AM PDT 24
Peak memory 217760 kb
Host smart-e6aa459b-4c68-49fd-bd0c-d713c0557878
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213627826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.4213627826
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.3299881508
Short name T600
Test name
Test status
Simulation time 89705220 ps
CPU time 2.08 seconds
Started Jul 02 09:58:55 AM PDT 24
Finished Jul 02 09:58:59 AM PDT 24
Peak memory 218144 kb
Host smart-0ca12180-7435-4f14-b268-b08dc011436d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299881508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3299881508
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1691692167
Short name T636
Test name
Test status
Simulation time 1015130608 ps
CPU time 13.04 seconds
Started Jul 02 09:58:59 AM PDT 24
Finished Jul 02 09:59:15 AM PDT 24
Peak memory 226012 kb
Host smart-51eb0adb-77a9-4c6b-af5b-c7200979a9d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691692167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1691692167
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.4094666235
Short name T297
Test name
Test status
Simulation time 851854444 ps
CPU time 9.05 seconds
Started Jul 02 09:58:57 AM PDT 24
Finished Jul 02 09:59:08 AM PDT 24
Peak memory 226240 kb
Host smart-38b418be-d768-4e38-b0d8-a8cfd669a5ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094666235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.4094666235
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3540750441
Short name T266
Test name
Test status
Simulation time 2089226863 ps
CPU time 10.49 seconds
Started Jul 02 09:58:50 AM PDT 24
Finished Jul 02 09:59:02 AM PDT 24
Peak memory 218236 kb
Host smart-18f0e730-f257-48c7-965a-ee3785bc141c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540750441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3540750441
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.2671979253
Short name T732
Test name
Test status
Simulation time 1241061639 ps
CPU time 10.07 seconds
Started Jul 02 09:59:01 AM PDT 24
Finished Jul 02 09:59:17 AM PDT 24
Peak memory 218312 kb
Host smart-b4f0df0a-d216-436c-8978-347062100d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671979253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2671979253
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.4124885093
Short name T20
Test name
Test status
Simulation time 35595621 ps
CPU time 0.97 seconds
Started Jul 02 09:58:48 AM PDT 24
Finished Jul 02 09:58:51 AM PDT 24
Peak memory 212072 kb
Host smart-49d3a15b-8f93-454a-908a-cb54b254885e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124885093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.4124885093
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.690134246
Short name T740
Test name
Test status
Simulation time 1044911253 ps
CPU time 28.97 seconds
Started Jul 02 09:58:47 AM PDT 24
Finished Jul 02 09:59:18 AM PDT 24
Peak memory 250948 kb
Host smart-d625f0e0-50ad-430e-8bc7-33e9dccecab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690134246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.690134246
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.2148433534
Short name T718
Test name
Test status
Simulation time 128643350 ps
CPU time 11.63 seconds
Started Jul 02 09:58:59 AM PDT 24
Finished Jul 02 09:59:16 AM PDT 24
Peak memory 250892 kb
Host smart-18fab97f-bd43-4c98-b76b-2c9b3f0fdde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148433534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2148433534
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1709409705
Short name T65
Test name
Test status
Simulation time 13034458010 ps
CPU time 72.66 seconds
Started Jul 02 09:59:01 AM PDT 24
Finished Jul 02 10:00:20 AM PDT 24
Peak memory 269208 kb
Host smart-8e32181d-9e28-47b5-9f83-c0ad8b383a8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709409705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1709409705
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.2991186817
Short name T141
Test name
Test status
Simulation time 46102361877 ps
CPU time 2060.48 seconds
Started Jul 02 09:58:59 AM PDT 24
Finished Jul 02 10:33:24 AM PDT 24
Peak memory 959128 kb
Host smart-532aa2f1-b8b4-4b2b-b40f-22951ff110ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2991186817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.2991186817
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1359469735
Short name T503
Test name
Test status
Simulation time 15157769 ps
CPU time 0.92 seconds
Started Jul 02 09:59:01 AM PDT 24
Finished Jul 02 09:59:08 AM PDT 24
Peak memory 211996 kb
Host smart-fc073441-143a-41c5-af2a-256a25c55fe2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359469735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.1359469735
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.4241539586
Short name T425
Test name
Test status
Simulation time 23461560 ps
CPU time 1.12 seconds
Started Jul 02 09:59:06 AM PDT 24
Finished Jul 02 09:59:14 AM PDT 24
Peak memory 209100 kb
Host smart-3d429924-f078-40f2-88c1-666cd5b32019
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241539586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.4241539586
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.3170011551
Short name T814
Test name
Test status
Simulation time 624063853 ps
CPU time 9.4 seconds
Started Jul 02 09:59:00 AM PDT 24
Finished Jul 02 09:59:16 AM PDT 24
Peak memory 218116 kb
Host smart-bab88694-b69d-497b-a1e3-6b1b3e3c16fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170011551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.3170011551
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.2168194810
Short name T607
Test name
Test status
Simulation time 767283828 ps
CPU time 4.91 seconds
Started Jul 02 09:58:58 AM PDT 24
Finished Jul 02 09:59:05 AM PDT 24
Peak memory 217104 kb
Host smart-c4febca6-1d8e-447c-9226-2523c10e2c27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168194810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.2168194810
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.937395098
Short name T369
Test name
Test status
Simulation time 44365032 ps
CPU time 1.66 seconds
Started Jul 02 09:59:00 AM PDT 24
Finished Jul 02 09:59:08 AM PDT 24
Peak memory 218180 kb
Host smart-246bfac9-d194-4d68-9d57-52b20a9c99cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937395098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.937395098
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.3767442767
Short name T199
Test name
Test status
Simulation time 224964945 ps
CPU time 10.76 seconds
Started Jul 02 09:58:57 AM PDT 24
Finished Jul 02 09:59:09 AM PDT 24
Peak memory 226000 kb
Host smart-2f5ecd45-6185-41fb-9cce-0c3e471ed518
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767442767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.3767442767
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2491309677
Short name T488
Test name
Test status
Simulation time 715026607 ps
CPU time 14.9 seconds
Started Jul 02 09:58:59 AM PDT 24
Finished Jul 02 09:59:20 AM PDT 24
Peak memory 225792 kb
Host smart-617a342f-5206-4497-93a4-8e143c2bdf9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491309677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.2491309677
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2305486068
Short name T340
Test name
Test status
Simulation time 1053654518 ps
CPU time 8.09 seconds
Started Jul 02 09:58:59 AM PDT 24
Finished Jul 02 09:59:13 AM PDT 24
Peak memory 218028 kb
Host smart-7899ac45-1ea6-484b-8ccb-575cd4c61fd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305486068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2305486068
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.1540398542
Short name T580
Test name
Test status
Simulation time 590815398 ps
CPU time 10.24 seconds
Started Jul 02 09:58:53 AM PDT 24
Finished Jul 02 09:59:05 AM PDT 24
Peak memory 224612 kb
Host smart-cf5df469-29a6-4ff9-857a-8fd176862fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540398542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.1540398542
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2634418347
Short name T240
Test name
Test status
Simulation time 132360783 ps
CPU time 3.16 seconds
Started Jul 02 09:59:00 AM PDT 24
Finished Jul 02 09:59:08 AM PDT 24
Peak memory 214568 kb
Host smart-ce110987-0209-41a0-89b6-d60654fac3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634418347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2634418347
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.2616848557
Short name T545
Test name
Test status
Simulation time 4143191002 ps
CPU time 28.34 seconds
Started Jul 02 09:58:55 AM PDT 24
Finished Jul 02 09:59:25 AM PDT 24
Peak memory 251024 kb
Host smart-78d2df3f-f312-4dc4-a8d9-415a1a2ddae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616848557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.2616848557
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.125976133
Short name T386
Test name
Test status
Simulation time 95481573 ps
CPU time 6.43 seconds
Started Jul 02 09:58:59 AM PDT 24
Finished Jul 02 09:59:09 AM PDT 24
Peak memory 247152 kb
Host smart-16e1bed8-c4aa-415c-a2a2-67f316c77ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125976133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.125976133
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.1843765673
Short name T83
Test name
Test status
Simulation time 9233334821 ps
CPU time 56.23 seconds
Started Jul 02 09:59:02 AM PDT 24
Finished Jul 02 10:00:05 AM PDT 24
Peak memory 271664 kb
Host smart-7bee6ab1-facf-4d64-bd4d-bd3c90cf3704
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843765673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.1843765673
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1900920575
Short name T476
Test name
Test status
Simulation time 48001695 ps
CPU time 0.88 seconds
Started Jul 02 09:58:59 AM PDT 24
Finished Jul 02 09:59:04 AM PDT 24
Peak memory 212160 kb
Host smart-e94a67ae-aec4-4d2f-8792-0d17b0ad6f87
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900920575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1900920575
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.2558477384
Short name T420
Test name
Test status
Simulation time 19575813 ps
CPU time 0.93 seconds
Started Jul 02 09:59:03 AM PDT 24
Finished Jul 02 09:59:11 AM PDT 24
Peak memory 208912 kb
Host smart-24803e41-0660-488d-98f0-00249b034ba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558477384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2558477384
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.399643839
Short name T94
Test name
Test status
Simulation time 258187328 ps
CPU time 9.26 seconds
Started Jul 02 09:59:16 AM PDT 24
Finished Jul 02 09:59:31 AM PDT 24
Peak memory 225988 kb
Host smart-45dc4aee-3005-4881-9fb3-d40c88c1efa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399643839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.399643839
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.174767429
Short name T8
Test name
Test status
Simulation time 397696372 ps
CPU time 9.89 seconds
Started Jul 02 09:58:58 AM PDT 24
Finished Jul 02 09:59:11 AM PDT 24
Peak memory 217644 kb
Host smart-e2a6846d-c295-4b98-b8fa-f9257ef3c767
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174767429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.174767429
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.1696274139
Short name T656
Test name
Test status
Simulation time 234627812 ps
CPU time 2.49 seconds
Started Jul 02 09:59:03 AM PDT 24
Finished Jul 02 09:59:12 AM PDT 24
Peak memory 218216 kb
Host smart-47443f65-ce0d-44db-a487-1f4c886e9351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696274139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1696274139
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.1979035304
Short name T407
Test name
Test status
Simulation time 1776801878 ps
CPU time 11.93 seconds
Started Jul 02 09:59:01 AM PDT 24
Finished Jul 02 09:59:19 AM PDT 24
Peak memory 225924 kb
Host smart-dc75aebc-16bd-4d1a-9ad4-51b54c447153
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979035304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.1979035304
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.2057191600
Short name T441
Test name
Test status
Simulation time 1469697071 ps
CPU time 9.47 seconds
Started Jul 02 09:58:50 AM PDT 24
Finished Jul 02 09:59:02 AM PDT 24
Peak memory 226012 kb
Host smart-b309364a-afb7-4de2-97b7-7ea5d5ecbcb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057191600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.2057191600
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.2838461048
Short name T295
Test name
Test status
Simulation time 423715222 ps
CPU time 9.12 seconds
Started Jul 02 09:58:57 AM PDT 24
Finished Jul 02 09:59:08 AM PDT 24
Peak memory 218240 kb
Host smart-1f1ded96-89fe-4cc6-90c2-fd06603540b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838461048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
2838461048
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.1488287786
Short name T662
Test name
Test status
Simulation time 1491070982 ps
CPU time 13.21 seconds
Started Jul 02 09:58:58 AM PDT 24
Finished Jul 02 09:59:14 AM PDT 24
Peak memory 225456 kb
Host smart-386bfe1f-408f-44d3-8670-6f55d78325e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488287786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.1488287786
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3295134002
Short name T58
Test name
Test status
Simulation time 74563939 ps
CPU time 1.7 seconds
Started Jul 02 09:59:02 AM PDT 24
Finished Jul 02 09:59:10 AM PDT 24
Peak memory 213912 kb
Host smart-bfedcc2b-38ed-4ed7-a420-09a945fe4a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295134002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3295134002
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.1999085312
Short name T452
Test name
Test status
Simulation time 187455472 ps
CPU time 19.85 seconds
Started Jul 02 09:59:02 AM PDT 24
Finished Jul 02 09:59:28 AM PDT 24
Peak memory 250996 kb
Host smart-a1c65668-6ef0-4de5-ab1a-4c7dfab7429b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999085312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.1999085312
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.2345365452
Short name T434
Test name
Test status
Simulation time 95469169 ps
CPU time 9.5 seconds
Started Jul 02 09:58:59 AM PDT 24
Finished Jul 02 09:59:14 AM PDT 24
Peak memory 251000 kb
Host smart-4b42d711-607e-4387-aa4e-99937ad852f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345365452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.2345365452
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.987051432
Short name T534
Test name
Test status
Simulation time 9161457195 ps
CPU time 105.97 seconds
Started Jul 02 09:59:03 AM PDT 24
Finished Jul 02 10:00:55 AM PDT 24
Peak memory 283340 kb
Host smart-a8c58d69-e837-4115-b41a-41d14df363ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987051432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.987051432
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2948284310
Short name T343
Test name
Test status
Simulation time 44775451 ps
CPU time 0.91 seconds
Started Jul 02 09:59:00 AM PDT 24
Finished Jul 02 09:59:06 AM PDT 24
Peak memory 211572 kb
Host smart-a7d5fd2d-b8bb-427e-9d07-e7e25c028a34
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948284310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2948284310
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.1026827676
Short name T325
Test name
Test status
Simulation time 27456427 ps
CPU time 1.39 seconds
Started Jul 02 09:58:58 AM PDT 24
Finished Jul 02 09:59:11 AM PDT 24
Peak memory 209076 kb
Host smart-8bf8d98a-8731-4c5d-b0aa-e2bf12801ac1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026827676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.1026827676
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.650519537
Short name T498
Test name
Test status
Simulation time 3616125424 ps
CPU time 20.26 seconds
Started Jul 02 09:59:03 AM PDT 24
Finished Jul 02 09:59:30 AM PDT 24
Peak memory 218288 kb
Host smart-5a2c8c5f-2805-45bc-a54f-f4e1136cd270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650519537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.650519537
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3117259529
Short name T730
Test name
Test status
Simulation time 784586982 ps
CPU time 6.52 seconds
Started Jul 02 09:59:00 AM PDT 24
Finished Jul 02 09:59:13 AM PDT 24
Peak memory 217496 kb
Host smart-185b4eaf-7a6a-41fb-80e6-ed4f481e8bf5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117259529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.3117259529
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.1798594628
Short name T346
Test name
Test status
Simulation time 67054787 ps
CPU time 3.54 seconds
Started Jul 02 09:59:34 AM PDT 24
Finished Jul 02 09:59:40 AM PDT 24
Peak memory 218228 kb
Host smart-c58f2941-fcc5-4b21-bf93-5bcfe8efc922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798594628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1798594628
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.4064767134
Short name T596
Test name
Test status
Simulation time 345656810 ps
CPU time 12.44 seconds
Started Jul 02 09:59:00 AM PDT 24
Finished Jul 02 09:59:19 AM PDT 24
Peak memory 225604 kb
Host smart-00af34e6-9da1-4987-bcee-dcda2328eae3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064767134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.4064767134
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.2279790787
Short name T228
Test name
Test status
Simulation time 1970607634 ps
CPU time 10.17 seconds
Started Jul 02 09:59:12 AM PDT 24
Finished Jul 02 09:59:29 AM PDT 24
Peak memory 226048 kb
Host smart-956f1917-9f13-41c5-b672-1e5357005792
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279790787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.2279790787
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3317995171
Short name T697
Test name
Test status
Simulation time 248453940 ps
CPU time 6.74 seconds
Started Jul 02 09:59:12 AM PDT 24
Finished Jul 02 09:59:25 AM PDT 24
Peak memory 226044 kb
Host smart-62206f51-a9e3-4604-9b6d-108e70913683
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317995171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3317995171
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1955034462
Short name T594
Test name
Test status
Simulation time 303812441 ps
CPU time 11.53 seconds
Started Jul 02 09:59:01 AM PDT 24
Finished Jul 02 09:59:20 AM PDT 24
Peak memory 225956 kb
Host smart-7c809f38-de51-4a1b-b06f-189435f540b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955034462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1955034462
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.3876581140
Short name T525
Test name
Test status
Simulation time 39298044 ps
CPU time 2.42 seconds
Started Jul 02 09:58:58 AM PDT 24
Finished Jul 02 09:59:02 AM PDT 24
Peak memory 217660 kb
Host smart-8245612a-0583-4f1b-92a0-b5d465ae7366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876581140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.3876581140
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.2514636312
Short name T695
Test name
Test status
Simulation time 3081289372 ps
CPU time 32.32 seconds
Started Jul 02 09:58:59 AM PDT 24
Finished Jul 02 09:59:41 AM PDT 24
Peak memory 251132 kb
Host smart-5aee8b47-a2e1-4a0b-97ee-0988af0661b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514636312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2514636312
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3716171464
Short name T371
Test name
Test status
Simulation time 73611379 ps
CPU time 3.1 seconds
Started Jul 02 09:58:51 AM PDT 24
Finished Jul 02 09:58:56 AM PDT 24
Peak memory 222604 kb
Host smart-15d3c1bf-57fc-4247-a35f-b50c0ccbc418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716171464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3716171464
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.473057490
Short name T666
Test name
Test status
Simulation time 8441391495 ps
CPU time 275.1 seconds
Started Jul 02 09:59:02 AM PDT 24
Finished Jul 02 10:03:44 AM PDT 24
Peak memory 316516 kb
Host smart-7dd8d385-5378-4a9d-a35d-ebfe986e5f20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473057490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.473057490
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2629137461
Short name T537
Test name
Test status
Simulation time 50035117 ps
CPU time 0.89 seconds
Started Jul 02 09:59:01 AM PDT 24
Finished Jul 02 09:59:09 AM PDT 24
Peak memory 217684 kb
Host smart-f58f7ebc-d272-48ef-8c9e-721d5e117aa9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629137461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.2629137461
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.1085823824
Short name T90
Test name
Test status
Simulation time 46066715 ps
CPU time 0.88 seconds
Started Jul 02 09:59:13 AM PDT 24
Finished Jul 02 09:59:21 AM PDT 24
Peak memory 208872 kb
Host smart-d5725b53-f47d-4e49-b3d5-d2551c35ba77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085823824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.1085823824
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.126237867
Short name T778
Test name
Test status
Simulation time 740708899 ps
CPU time 15.22 seconds
Started Jul 02 09:59:19 AM PDT 24
Finished Jul 02 09:59:38 AM PDT 24
Peak memory 218236 kb
Host smart-665fdc6f-26c3-426d-83d0-93a59f92ea42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126237867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.126237867
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.76326091
Short name T497
Test name
Test status
Simulation time 819509174 ps
CPU time 5.36 seconds
Started Jul 02 09:59:12 AM PDT 24
Finished Jul 02 09:59:24 AM PDT 24
Peak memory 217232 kb
Host smart-f9b85aed-e137-4a9e-afb6-c7166de08067
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76326091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.76326091
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.555571011
Short name T446
Test name
Test status
Simulation time 375178677 ps
CPU time 4.38 seconds
Started Jul 02 09:59:02 AM PDT 24
Finished Jul 02 09:59:16 AM PDT 24
Peak memory 218124 kb
Host smart-5895993d-dbcb-460e-ad0f-0e6309e44a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555571011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.555571011
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.1486872670
Short name T635
Test name
Test status
Simulation time 2067238513 ps
CPU time 7.76 seconds
Started Jul 02 09:59:06 AM PDT 24
Finished Jul 02 09:59:21 AM PDT 24
Peak memory 226004 kb
Host smart-6d58f8fd-7a04-457a-857a-02cac0d6f182
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486872670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.1486872670
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.1717013763
Short name T357
Test name
Test status
Simulation time 398682476 ps
CPU time 16.25 seconds
Started Jul 02 09:59:00 AM PDT 24
Finished Jul 02 09:59:23 AM PDT 24
Peak memory 226000 kb
Host smart-878ff646-f632-4210-9201-ac8b73d43bdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717013763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.1717013763
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3022657405
Short name T824
Test name
Test status
Simulation time 1233182991 ps
CPU time 9.23 seconds
Started Jul 02 09:59:04 AM PDT 24
Finished Jul 02 09:59:20 AM PDT 24
Peak memory 218448 kb
Host smart-8736f6dc-a733-4db3-9d0a-23021c83ab3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022657405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
3022657405
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.2887767216
Short name T464
Test name
Test status
Simulation time 332859695 ps
CPU time 12.41 seconds
Started Jul 02 09:59:14 AM PDT 24
Finished Jul 02 09:59:33 AM PDT 24
Peak memory 226052 kb
Host smart-93982a0b-5560-40af-9e52-672fd590225e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887767216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.2887767216
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.478358974
Short name T69
Test name
Test status
Simulation time 29461404 ps
CPU time 1.9 seconds
Started Jul 02 09:59:11 AM PDT 24
Finished Jul 02 09:59:20 AM PDT 24
Peak memory 217720 kb
Host smart-61aca007-052e-44ce-b8ec-ddb2ba13dce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478358974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.478358974
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.126558928
Short name T505
Test name
Test status
Simulation time 334409931 ps
CPU time 25.32 seconds
Started Jul 02 09:59:02 AM PDT 24
Finished Jul 02 09:59:34 AM PDT 24
Peak memory 250976 kb
Host smart-e0169728-20a9-4b7b-ab0e-d4a63d21f674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126558928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.126558928
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.877007928
Short name T769
Test name
Test status
Simulation time 91565726 ps
CPU time 7.54 seconds
Started Jul 02 09:58:53 AM PDT 24
Finished Jul 02 09:59:02 AM PDT 24
Peak memory 247524 kb
Host smart-e5a57af5-b3bc-4132-a471-ab3a9539996f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877007928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.877007928
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.3427865495
Short name T57
Test name
Test status
Simulation time 10123989849 ps
CPU time 93.37 seconds
Started Jul 02 09:59:03 AM PDT 24
Finished Jul 02 10:00:43 AM PDT 24
Peak memory 268256 kb
Host smart-140f684c-4318-43c6-a4f8-61d650278292
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427865495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.3427865495
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.2290824419
Short name T44
Test name
Test status
Simulation time 25987083286 ps
CPU time 891.97 seconds
Started Jul 02 09:58:59 AM PDT 24
Finished Jul 02 10:13:56 AM PDT 24
Peak memory 422140 kb
Host smart-27948e50-1e97-4d3f-9d9d-f27f72b15508
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2290824419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.2290824419
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3082095740
Short name T729
Test name
Test status
Simulation time 22892566 ps
CPU time 0.77 seconds
Started Jul 02 09:59:12 AM PDT 24
Finished Jul 02 09:59:20 AM PDT 24
Peak memory 208112 kb
Host smart-a0c2fb26-f9a2-4c5a-aada-dd0d4d6762fd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082095740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3082095740
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.1862357102
Short name T91
Test name
Test status
Simulation time 65375165 ps
CPU time 1 seconds
Started Jul 02 09:59:12 AM PDT 24
Finished Jul 02 09:59:20 AM PDT 24
Peak memory 209072 kb
Host smart-8c910230-12f3-43b0-9294-cb12fd2ccb2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862357102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1862357102
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.3202164003
Short name T370
Test name
Test status
Simulation time 2916703903 ps
CPU time 13.63 seconds
Started Jul 02 09:59:13 AM PDT 24
Finished Jul 02 09:59:37 AM PDT 24
Peak memory 218992 kb
Host smart-f8c09e2c-a40d-43bd-ad76-957662a36e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202164003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.3202164003
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.2832187059
Short name T561
Test name
Test status
Simulation time 377078380 ps
CPU time 5.25 seconds
Started Jul 02 09:59:10 AM PDT 24
Finished Jul 02 09:59:23 AM PDT 24
Peak memory 217436 kb
Host smart-f4839ec4-487d-46f1-9f34-bd1523595afe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832187059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.2832187059
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1022259064
Short name T394
Test name
Test status
Simulation time 346059607 ps
CPU time 2.74 seconds
Started Jul 02 09:59:14 AM PDT 24
Finished Jul 02 09:59:23 AM PDT 24
Peak memory 218308 kb
Host smart-72d45347-5758-4ca6-8b21-c355ccc37698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022259064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1022259064
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.4123397836
Short name T782
Test name
Test status
Simulation time 737774160 ps
CPU time 17.7 seconds
Started Jul 02 09:59:23 AM PDT 24
Finished Jul 02 09:59:43 AM PDT 24
Peak memory 218972 kb
Host smart-cf1743dc-03cb-4c20-a6ba-1ff286cb0072
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123397836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.4123397836
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1990094412
Short name T693
Test name
Test status
Simulation time 365566274 ps
CPU time 10.25 seconds
Started Jul 02 09:59:23 AM PDT 24
Finished Jul 02 09:59:36 AM PDT 24
Peak memory 226052 kb
Host smart-e882b89d-df14-42d6-ad74-13e1d52a4edb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990094412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.1990094412
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.2078427490
Short name T828
Test name
Test status
Simulation time 1860524767 ps
CPU time 11.27 seconds
Started Jul 02 09:59:11 AM PDT 24
Finished Jul 02 09:59:29 AM PDT 24
Peak memory 218244 kb
Host smart-c0ef0801-71f1-405d-b85e-dbde196f1aeb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078427490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
2078427490
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2718251187
Short name T510
Test name
Test status
Simulation time 1315254448 ps
CPU time 12.13 seconds
Started Jul 02 09:58:58 AM PDT 24
Finished Jul 02 09:59:12 AM PDT 24
Peak memory 225360 kb
Host smart-3a71fd8b-14de-423d-b86f-dae83f34d654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718251187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2718251187
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.586820006
Short name T305
Test name
Test status
Simulation time 46832464 ps
CPU time 2.58 seconds
Started Jul 02 09:59:02 AM PDT 24
Finished Jul 02 09:59:12 AM PDT 24
Peak memory 214316 kb
Host smart-06d0739b-db92-46b6-bbfe-449084521b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586820006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.586820006
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.2261791918
Short name T736
Test name
Test status
Simulation time 732897081 ps
CPU time 23.85 seconds
Started Jul 02 09:58:59 AM PDT 24
Finished Jul 02 09:59:28 AM PDT 24
Peak memory 250952 kb
Host smart-28ebeee8-1c51-4106-b4ea-1e3321e653ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261791918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2261791918
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.1927912019
Short name T312
Test name
Test status
Simulation time 317323532 ps
CPU time 8.7 seconds
Started Jul 02 09:59:01 AM PDT 24
Finished Jul 02 09:59:16 AM PDT 24
Peak memory 243556 kb
Host smart-3620dba9-0aa1-4484-9a48-fbe99adf9303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927912019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.1927912019
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.3890289129
Short name T789
Test name
Test status
Simulation time 9065670155 ps
CPU time 48.69 seconds
Started Jul 02 09:59:18 AM PDT 24
Finished Jul 02 10:00:11 AM PDT 24
Peak memory 250792 kb
Host smart-127487d8-9983-40ba-86a9-956807379418
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890289129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.3890289129
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3841183472
Short name T845
Test name
Test status
Simulation time 11575595 ps
CPU time 0.98 seconds
Started Jul 02 09:59:02 AM PDT 24
Finished Jul 02 09:59:10 AM PDT 24
Peak memory 211772 kb
Host smart-22b191d4-de83-4596-b619-578373ba91ea
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841183472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.3841183472
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.3699631421
Short name T341
Test name
Test status
Simulation time 75652810 ps
CPU time 1.19 seconds
Started Jul 02 09:59:02 AM PDT 24
Finished Jul 02 09:59:10 AM PDT 24
Peak memory 209080 kb
Host smart-452ad7b9-36de-4e56-bf58-f5fa7ae410e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699631421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3699631421
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.2103605258
Short name T489
Test name
Test status
Simulation time 1022405714 ps
CPU time 13.82 seconds
Started Jul 02 09:59:09 AM PDT 24
Finished Jul 02 09:59:30 AM PDT 24
Peak memory 218120 kb
Host smart-14841405-6e33-45ad-a9e8-bf6433a2b126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103605258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2103605258
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.972531892
Short name T421
Test name
Test status
Simulation time 641787265 ps
CPU time 3.79 seconds
Started Jul 02 09:59:06 AM PDT 24
Finished Jul 02 09:59:16 AM PDT 24
Peak memory 217212 kb
Host smart-50b226be-8bf6-4ca0-b1cd-6033578bc997
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972531892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.972531892
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.1803727316
Short name T816
Test name
Test status
Simulation time 140663875 ps
CPU time 2.47 seconds
Started Jul 02 09:59:12 AM PDT 24
Finished Jul 02 09:59:22 AM PDT 24
Peak memory 218244 kb
Host smart-f63f0099-91d6-4bb3-bc05-c7491fc3f2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803727316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1803727316
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.467243574
Short name T213
Test name
Test status
Simulation time 437194693 ps
CPU time 10.27 seconds
Started Jul 02 09:59:21 AM PDT 24
Finished Jul 02 09:59:35 AM PDT 24
Peak memory 226048 kb
Host smart-0f9bdfa9-8d5c-4a5b-bc24-df5f7cc34288
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467243574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.467243574
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.1842575411
Short name T771
Test name
Test status
Simulation time 691117270 ps
CPU time 13.86 seconds
Started Jul 02 09:59:13 AM PDT 24
Finished Jul 02 09:59:33 AM PDT 24
Peak memory 218256 kb
Host smart-03bab031-bc78-4539-b34d-37b9465677e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842575411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
1842575411
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1060859956
Short name T474
Test name
Test status
Simulation time 38777606 ps
CPU time 1.43 seconds
Started Jul 02 09:59:12 AM PDT 24
Finished Jul 02 09:59:21 AM PDT 24
Peak memory 213828 kb
Host smart-2b85e375-fe3f-4821-9f79-9a39d60fdf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060859956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1060859956
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.1543000268
Short name T819
Test name
Test status
Simulation time 307488108 ps
CPU time 28.35 seconds
Started Jul 02 09:59:07 AM PDT 24
Finished Jul 02 09:59:41 AM PDT 24
Peak memory 251008 kb
Host smart-c4887141-d967-4fe6-bdef-ec91788c7037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543000268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.1543000268
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.2003053262
Short name T224
Test name
Test status
Simulation time 119808711 ps
CPU time 7.24 seconds
Started Jul 02 09:59:13 AM PDT 24
Finished Jul 02 09:59:27 AM PDT 24
Peak memory 250936 kb
Host smart-643365bf-e1c1-4692-8c8f-32aecd4c8a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003053262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.2003053262
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.3737999975
Short name T686
Test name
Test status
Simulation time 2464295344 ps
CPU time 26.57 seconds
Started Jul 02 09:59:02 AM PDT 24
Finished Jul 02 09:59:36 AM PDT 24
Peak memory 247152 kb
Host smart-b4048670-68d8-41a4-b886-87e55de7dd0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737999975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.3737999975
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.494238945
Short name T328
Test name
Test status
Simulation time 30445737 ps
CPU time 1 seconds
Started Jul 02 09:59:16 AM PDT 24
Finished Jul 02 09:59:22 AM PDT 24
Peak memory 211916 kb
Host smart-2294667a-e390-4af4-ae4b-bbfd535b7811
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494238945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ct
rl_volatile_unlock_smoke.494238945
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.3853177549
Short name T827
Test name
Test status
Simulation time 68393285 ps
CPU time 0.98 seconds
Started Jul 02 09:57:48 AM PDT 24
Finished Jul 02 09:57:51 AM PDT 24
Peak memory 209044 kb
Host smart-b82f7026-8499-42bf-a70f-7c86d93e166c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853177549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3853177549
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1759786427
Short name T483
Test name
Test status
Simulation time 2572928342 ps
CPU time 24.48 seconds
Started Jul 02 09:58:04 AM PDT 24
Finished Jul 02 09:58:32 AM PDT 24
Peak memory 219136 kb
Host smart-c93587d7-fe55-423c-ae5d-c640b34b6c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759786427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1759786427
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.3806436064
Short name T549
Test name
Test status
Simulation time 1988450630 ps
CPU time 5.06 seconds
Started Jul 02 09:57:56 AM PDT 24
Finished Jul 02 09:58:04 AM PDT 24
Peak memory 217116 kb
Host smart-187cd5b9-420d-40fd-909b-538d67dd6391
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806436064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3806436064
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.3856765639
Short name T45
Test name
Test status
Simulation time 4609665263 ps
CPU time 33.94 seconds
Started Jul 02 09:57:54 AM PDT 24
Finished Jul 02 09:58:32 AM PDT 24
Peak memory 218948 kb
Host smart-f72f75f3-d3b2-43ff-a42b-9dd28ff8eaa1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856765639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.3856765639
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.500024742
Short name T641
Test name
Test status
Simulation time 1842808974 ps
CPU time 8.67 seconds
Started Jul 02 09:57:55 AM PDT 24
Finished Jul 02 09:58:06 AM PDT 24
Peak memory 217584 kb
Host smart-743290d7-adcd-46e8-b839-f5d17d0b20bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500024742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.500024742
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.861533354
Short name T415
Test name
Test status
Simulation time 111797905 ps
CPU time 2.75 seconds
Started Jul 02 09:57:50 AM PDT 24
Finished Jul 02 09:57:55 AM PDT 24
Peak memory 218140 kb
Host smart-5f1e778d-122a-4e9b-a19b-75f4ca848c71
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861533354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.861533354
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2363899278
Short name T71
Test name
Test status
Simulation time 7449827448 ps
CPU time 19.18 seconds
Started Jul 02 09:58:02 AM PDT 24
Finished Jul 02 09:58:24 AM PDT 24
Peak memory 217800 kb
Host smart-91491b27-8cfa-4bcb-9ec2-bdad36a1c8f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363899278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.2363899278
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.3705135357
Short name T380
Test name
Test status
Simulation time 224229640 ps
CPU time 2.52 seconds
Started Jul 02 09:58:01 AM PDT 24
Finished Jul 02 09:58:06 AM PDT 24
Peak memory 217636 kb
Host smart-b3961b7d-994c-403e-8553-dcbf1f21fd5a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705135357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
3705135357
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3593697035
Short name T486
Test name
Test status
Simulation time 2929438857 ps
CPU time 50.32 seconds
Started Jul 02 09:58:00 AM PDT 24
Finished Jul 02 09:58:53 AM PDT 24
Peak memory 252920 kb
Host smart-c06760c5-8088-407d-a316-6fd15d721917
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593697035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.3593697035
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2961320464
Short name T159
Test name
Test status
Simulation time 640608063 ps
CPU time 22.66 seconds
Started Jul 02 09:57:57 AM PDT 24
Finished Jul 02 09:58:22 AM PDT 24
Peak memory 250548 kb
Host smart-9c7fc25d-9a55-435e-87ac-0a0237a8e7cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961320464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.2961320464
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.1111745178
Short name T352
Test name
Test status
Simulation time 130145815 ps
CPU time 2.27 seconds
Started Jul 02 09:57:52 AM PDT 24
Finished Jul 02 09:57:57 AM PDT 24
Peak memory 218236 kb
Host smart-0054157b-0bad-4454-beb5-c437a7066da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111745178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.1111745178
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.3601381686
Short name T64
Test name
Test status
Simulation time 618509210 ps
CPU time 7.03 seconds
Started Jul 02 09:57:54 AM PDT 24
Finished Jul 02 09:58:04 AM PDT 24
Peak memory 217924 kb
Host smart-ffbd398b-2f7f-4572-adcc-79a26ae9488b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601381686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.3601381686
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1698752301
Short name T410
Test name
Test status
Simulation time 666770626 ps
CPU time 14.48 seconds
Started Jul 02 09:57:52 AM PDT 24
Finished Jul 02 09:58:09 AM PDT 24
Peak memory 219484 kb
Host smart-0fbb0a07-a39c-40dd-af64-9521978744a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698752301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1698752301
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2581394645
Short name T454
Test name
Test status
Simulation time 244237351 ps
CPU time 11.56 seconds
Started Jul 02 09:58:06 AM PDT 24
Finished Jul 02 09:58:24 AM PDT 24
Peak memory 226052 kb
Host smart-0b26d80f-4047-4f30-a635-fa333e52336c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581394645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.2581394645
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1863945264
Short name T604
Test name
Test status
Simulation time 582128877 ps
CPU time 18.38 seconds
Started Jul 02 09:58:06 AM PDT 24
Finished Jul 02 09:58:31 AM PDT 24
Peak memory 218200 kb
Host smart-f982c911-f089-4ef4-8a4f-0e8c8d8519e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863945264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.1
863945264
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.1300393063
Short name T47
Test name
Test status
Simulation time 464374087 ps
CPU time 9.76 seconds
Started Jul 02 09:57:52 AM PDT 24
Finished Jul 02 09:58:05 AM PDT 24
Peak memory 225292 kb
Host smart-3395ed41-58ae-4aeb-8f05-a536454bf092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300393063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.1300393063
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3396702077
Short name T637
Test name
Test status
Simulation time 42794067 ps
CPU time 1.25 seconds
Started Jul 02 09:57:44 AM PDT 24
Finished Jul 02 09:57:47 AM PDT 24
Peak memory 217700 kb
Host smart-ccdcdcf0-cc86-4b4e-a6a9-20f0233ef8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396702077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3396702077
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.4237381322
Short name T774
Test name
Test status
Simulation time 978148168 ps
CPU time 26.14 seconds
Started Jul 02 09:57:51 AM PDT 24
Finished Jul 02 09:58:20 AM PDT 24
Peak memory 247132 kb
Host smart-0aee046e-8bd6-4682-9efa-2fbcf65b71c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237381322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.4237381322
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.2560231902
Short name T319
Test name
Test status
Simulation time 183146871 ps
CPU time 3.76 seconds
Started Jul 02 09:57:51 AM PDT 24
Finished Jul 02 09:57:58 AM PDT 24
Peak memory 222428 kb
Host smart-2d8b84e6-6cb4-4a88-b886-011f4a18c62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560231902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2560231902
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.4150147788
Short name T610
Test name
Test status
Simulation time 7139415628 ps
CPU time 227.22 seconds
Started Jul 02 09:58:03 AM PDT 24
Finished Jul 02 10:01:53 AM PDT 24
Peak memory 250956 kb
Host smart-8b235c66-f55e-4bb6-833f-1a2b6ebb47e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150147788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.4150147788
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.4146388545
Short name T101
Test name
Test status
Simulation time 38094771604 ps
CPU time 423.46 seconds
Started Jul 02 09:57:56 AM PDT 24
Finished Jul 02 10:05:02 AM PDT 24
Peak memory 316908 kb
Host smart-fa5fee10-ee0d-42d8-b5bc-3a377f5674f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4146388545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.4146388545
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2827033643
Short name T149
Test name
Test status
Simulation time 13257535 ps
CPU time 1.01 seconds
Started Jul 02 09:58:00 AM PDT 24
Finished Jul 02 09:58:03 AM PDT 24
Peak memory 211912 kb
Host smart-a7f691bc-8e6d-40ee-863a-a5bd43fa96b0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827033643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.2827033643
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.72440529
Short name T277
Test name
Test status
Simulation time 67798781 ps
CPU time 1.14 seconds
Started Jul 02 09:59:12 AM PDT 24
Finished Jul 02 09:59:20 AM PDT 24
Peak memory 208996 kb
Host smart-20742588-68fd-434e-9267-eee6ddd42032
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72440529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.72440529
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2034495355
Short name T627
Test name
Test status
Simulation time 1005941972 ps
CPU time 10.72 seconds
Started Jul 02 09:59:12 AM PDT 24
Finished Jul 02 09:59:30 AM PDT 24
Peak memory 218228 kb
Host smart-24a3f400-25d2-43c0-bd8a-88a564a43db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034495355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2034495355
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.342572170
Short name T26
Test name
Test status
Simulation time 1928537563 ps
CPU time 11.37 seconds
Started Jul 02 09:59:08 AM PDT 24
Finished Jul 02 09:59:26 AM PDT 24
Peak memory 217200 kb
Host smart-4bafed04-831d-4099-a34b-051ca697e81c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342572170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.342572170
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.1068920031
Short name T725
Test name
Test status
Simulation time 97829359 ps
CPU time 3.79 seconds
Started Jul 02 09:59:01 AM PDT 24
Finished Jul 02 09:59:12 AM PDT 24
Peak memory 222344 kb
Host smart-28fc7be6-7069-418c-bc9f-0ea1b5549634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068920031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1068920031
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1478418717
Short name T484
Test name
Test status
Simulation time 419719077 ps
CPU time 14.31 seconds
Started Jul 02 09:59:13 AM PDT 24
Finished Jul 02 09:59:34 AM PDT 24
Peak memory 226056 kb
Host smart-637f214d-87c8-4d15-bc18-b53d23df15f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478418717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1478418717
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.188607783
Short name T667
Test name
Test status
Simulation time 429563154 ps
CPU time 9.41 seconds
Started Jul 02 09:59:06 AM PDT 24
Finished Jul 02 09:59:22 AM PDT 24
Peak memory 218272 kb
Host smart-fff913ec-c004-4d8b-b90e-0c85d054e0bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188607783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.188607783
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.2110171403
Short name T54
Test name
Test status
Simulation time 716751261 ps
CPU time 11.3 seconds
Started Jul 02 09:59:23 AM PDT 24
Finished Jul 02 09:59:46 AM PDT 24
Peak memory 226048 kb
Host smart-8c18701c-ad29-47b0-8587-b71ca091a531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110171403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.2110171403
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.2148564612
Short name T727
Test name
Test status
Simulation time 207761445 ps
CPU time 2.71 seconds
Started Jul 02 09:59:05 AM PDT 24
Finished Jul 02 09:59:15 AM PDT 24
Peak memory 217704 kb
Host smart-121c7810-880a-425f-84ca-61f56e2e301e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148564612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.2148564612
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.197805644
Short name T575
Test name
Test status
Simulation time 267561549 ps
CPU time 29.38 seconds
Started Jul 02 09:59:38 AM PDT 24
Finished Jul 02 10:00:10 AM PDT 24
Peak memory 251000 kb
Host smart-dd0b95e7-de56-42ba-b34c-b9f6804201b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197805644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.197805644
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.1958006284
Short name T743
Test name
Test status
Simulation time 48678093 ps
CPU time 7.76 seconds
Started Jul 02 09:59:00 AM PDT 24
Finished Jul 02 09:59:14 AM PDT 24
Peak memory 250976 kb
Host smart-69a8189c-ba1a-403b-abf4-4688ab91c8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958006284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.1958006284
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.447860072
Short name T395
Test name
Test status
Simulation time 5674641558 ps
CPU time 30.69 seconds
Started Jul 02 09:59:17 AM PDT 24
Finished Jul 02 09:59:53 AM PDT 24
Peak memory 227288 kb
Host smart-18884221-8f08-4b10-bc26-dfe0682f4c4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447860072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.447860072
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3928062242
Short name T492
Test name
Test status
Simulation time 12970893 ps
CPU time 0.86 seconds
Started Jul 02 09:59:08 AM PDT 24
Finished Jul 02 09:59:16 AM PDT 24
Peak memory 211848 kb
Host smart-97255d88-b38f-490e-b664-02cfc70bf6f5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928062242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3928062242
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.1960287327
Short name T550
Test name
Test status
Simulation time 15654866 ps
CPU time 0.88 seconds
Started Jul 02 09:59:09 AM PDT 24
Finished Jul 02 09:59:18 AM PDT 24
Peak memory 209056 kb
Host smart-4c10f90a-c2f5-4dbe-882b-6f998711e67f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960287327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.1960287327
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.1416690381
Short name T506
Test name
Test status
Simulation time 873782197 ps
CPU time 12.85 seconds
Started Jul 02 09:59:02 AM PDT 24
Finished Jul 02 09:59:22 AM PDT 24
Peak memory 218208 kb
Host smart-375b1592-1576-4d24-91ca-e8e47d1aa3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416690381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.1416690381
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.700597588
Short name T169
Test name
Test status
Simulation time 1087064992 ps
CPU time 5.54 seconds
Started Jul 02 09:59:01 AM PDT 24
Finished Jul 02 09:59:14 AM PDT 24
Peak memory 217400 kb
Host smart-b18e2a60-1155-4810-8466-5e72f314ebae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700597588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.700597588
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.1924171429
Short name T291
Test name
Test status
Simulation time 191021969 ps
CPU time 2.87 seconds
Started Jul 02 09:59:13 AM PDT 24
Finished Jul 02 09:59:22 AM PDT 24
Peak memory 218228 kb
Host smart-0c9b8ff7-005b-4fa3-9a03-05442c899203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924171429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.1924171429
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.494719711
Short name T753
Test name
Test status
Simulation time 425031901 ps
CPU time 17.57 seconds
Started Jul 02 09:59:15 AM PDT 24
Finished Jul 02 09:59:39 AM PDT 24
Peak memory 219500 kb
Host smart-b4a5a362-1643-4ee7-92bc-6f41bf619cd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494719711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.494719711
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2754719679
Short name T638
Test name
Test status
Simulation time 1091281739 ps
CPU time 8.44 seconds
Started Jul 02 09:59:18 AM PDT 24
Finished Jul 02 09:59:32 AM PDT 24
Peak memory 218244 kb
Host smart-7f10dfce-40f9-437b-b815-0d3b0f03ffcc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754719679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2754719679
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.3436985845
Short name T248
Test name
Test status
Simulation time 265155629 ps
CPU time 6.47 seconds
Started Jul 02 09:59:01 AM PDT 24
Finished Jul 02 09:59:13 AM PDT 24
Peak memory 224968 kb
Host smart-5dc8cc17-bb90-421e-9ceb-72af3362789d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436985845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
3436985845
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3355240865
Short name T648
Test name
Test status
Simulation time 1328981481 ps
CPU time 10.79 seconds
Started Jul 02 09:59:11 AM PDT 24
Finished Jul 02 09:59:29 AM PDT 24
Peak memory 226104 kb
Host smart-715dc30a-2675-4827-a9b9-0fb94ad0af72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355240865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3355240865
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1793465883
Short name T74
Test name
Test status
Simulation time 48163828 ps
CPU time 1.05 seconds
Started Jul 02 09:59:06 AM PDT 24
Finished Jul 02 09:59:14 AM PDT 24
Peak memory 217716 kb
Host smart-8c716827-7a73-4b56-a099-1608d992379c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793465883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1793465883
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.570998277
Short name T856
Test name
Test status
Simulation time 2858160106 ps
CPU time 27.13 seconds
Started Jul 02 09:59:08 AM PDT 24
Finished Jul 02 09:59:42 AM PDT 24
Peak memory 251032 kb
Host smart-6d4184d7-8de3-4c1c-82fd-d1feff6d61c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570998277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.570998277
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.4154011244
Short name T447
Test name
Test status
Simulation time 288341543 ps
CPU time 8.01 seconds
Started Jul 02 09:59:05 AM PDT 24
Finished Jul 02 09:59:20 AM PDT 24
Peak memory 250968 kb
Host smart-174c76d8-ca06-4ae8-b4d8-87f6fd3c52bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154011244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.4154011244
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2658426778
Short name T337
Test name
Test status
Simulation time 14157872321 ps
CPU time 74.32 seconds
Started Jul 02 09:59:07 AM PDT 24
Finished Jul 02 10:00:29 AM PDT 24
Peak memory 226408 kb
Host smart-da3719ae-c029-471c-84f1-2d78105f8898
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658426778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2658426778
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2769636286
Short name T243
Test name
Test status
Simulation time 41179885 ps
CPU time 0.97 seconds
Started Jul 02 09:59:12 AM PDT 24
Finished Jul 02 09:59:20 AM PDT 24
Peak memory 211728 kb
Host smart-ddac9503-441e-401c-8536-054795be4267
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769636286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.2769636286
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1723174628
Short name T529
Test name
Test status
Simulation time 20995125 ps
CPU time 0.92 seconds
Started Jul 02 09:59:09 AM PDT 24
Finished Jul 02 09:59:17 AM PDT 24
Peak memory 208964 kb
Host smart-bc683297-2ab0-4d80-a43b-5907cd3b33ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723174628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1723174628
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.1265077799
Short name T97
Test name
Test status
Simulation time 532874244 ps
CPU time 14.83 seconds
Started Jul 02 09:59:18 AM PDT 24
Finished Jul 02 09:59:37 AM PDT 24
Peak memory 218192 kb
Host smart-a54f59d8-5d0f-457c-89b6-ee911c000d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265077799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1265077799
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.4057662443
Short name T30
Test name
Test status
Simulation time 193063230 ps
CPU time 5.09 seconds
Started Jul 02 09:59:00 AM PDT 24
Finished Jul 02 09:59:11 AM PDT 24
Peak memory 217116 kb
Host smart-a00b4fcd-a482-4769-911d-1365967ff72b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057662443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.4057662443
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.598542141
Short name T221
Test name
Test status
Simulation time 237242715 ps
CPU time 2.14 seconds
Started Jul 02 09:59:12 AM PDT 24
Finished Jul 02 09:59:21 AM PDT 24
Peak memory 218220 kb
Host smart-5968236b-daad-41fb-b280-fcd6eac15cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598542141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.598542141
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.595803127
Short name T402
Test name
Test status
Simulation time 418210086 ps
CPU time 14.14 seconds
Started Jul 02 09:59:32 AM PDT 24
Finished Jul 02 09:59:48 AM PDT 24
Peak memory 218928 kb
Host smart-7163e80b-27fe-4a6e-b3df-b5fa9b2d240e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595803127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.595803127
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.800595885
Short name T155
Test name
Test status
Simulation time 1955380113 ps
CPU time 13.04 seconds
Started Jul 02 09:59:09 AM PDT 24
Finished Jul 02 09:59:29 AM PDT 24
Peak memory 226060 kb
Host smart-b265219f-94ef-4b10-b332-5eebcf7d830b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800595885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_di
gest.800595885
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3532774969
Short name T151
Test name
Test status
Simulation time 1340139472 ps
CPU time 11.7 seconds
Started Jul 02 09:59:05 AM PDT 24
Finished Jul 02 09:59:23 AM PDT 24
Peak memory 218248 kb
Host smart-b560c7ca-53c6-48e3-8b36-a2830d1fd54b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532774969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
3532774969
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.305701819
Short name T571
Test name
Test status
Simulation time 1695758253 ps
CPU time 9.77 seconds
Started Jul 02 09:59:24 AM PDT 24
Finished Jul 02 09:59:36 AM PDT 24
Peak memory 226040 kb
Host smart-18e57d38-eed9-41be-835a-aa41f7c111cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305701819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.305701819
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.4196589055
Short name T811
Test name
Test status
Simulation time 396932854 ps
CPU time 3.4 seconds
Started Jul 02 09:59:02 AM PDT 24
Finished Jul 02 09:59:12 AM PDT 24
Peak memory 217728 kb
Host smart-4430efbc-279b-4f6c-8c09-aff86132b448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196589055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.4196589055
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3581387667
Short name T659
Test name
Test status
Simulation time 836630466 ps
CPU time 21.58 seconds
Started Jul 02 09:58:56 AM PDT 24
Finished Jul 02 09:59:20 AM PDT 24
Peak memory 250996 kb
Host smart-9ba74116-48f5-45b2-8c2a-f62ae6242aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581387667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3581387667
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.4209626381
Short name T810
Test name
Test status
Simulation time 222385960 ps
CPU time 6.4 seconds
Started Jul 02 09:59:11 AM PDT 24
Finished Jul 02 09:59:25 AM PDT 24
Peak memory 250564 kb
Host smart-29709488-6eee-44b3-9368-f294b1296af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209626381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.4209626381
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.3897578805
Short name T687
Test name
Test status
Simulation time 15507236817 ps
CPU time 67.82 seconds
Started Jul 02 09:59:19 AM PDT 24
Finished Jul 02 10:00:31 AM PDT 24
Peak memory 266644 kb
Host smart-d723177f-91ed-4e2f-9509-85f85a710847
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897578805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.3897578805
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2965813575
Short name T285
Test name
Test status
Simulation time 10836598 ps
CPU time 1 seconds
Started Jul 02 09:59:30 AM PDT 24
Finished Jul 02 09:59:33 AM PDT 24
Peak memory 211848 kb
Host smart-cdae6a5b-a1e4-45e4-a4f1-7a2f07788678
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965813575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2965813575
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.3952397477
Short name T487
Test name
Test status
Simulation time 16378900 ps
CPU time 1.18 seconds
Started Jul 02 09:59:05 AM PDT 24
Finished Jul 02 09:59:12 AM PDT 24
Peak memory 208944 kb
Host smart-85e537dc-15de-415d-a190-e20f267ff492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952397477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.3952397477
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2335227488
Short name T700
Test name
Test status
Simulation time 2685543670 ps
CPU time 12.18 seconds
Started Jul 02 09:59:11 AM PDT 24
Finished Jul 02 09:59:30 AM PDT 24
Peak memory 226280 kb
Host smart-3430177b-c546-4be4-92c1-0348adffae2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335227488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2335227488
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.4050796802
Short name T160
Test name
Test status
Simulation time 138648598 ps
CPU time 4.02 seconds
Started Jul 02 09:59:13 AM PDT 24
Finished Jul 02 09:59:24 AM PDT 24
Peak memory 217104 kb
Host smart-7c8af21f-31a8-45dc-9abe-7605a70be3cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050796802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.4050796802
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.1117338501
Short name T245
Test name
Test status
Simulation time 60000854 ps
CPU time 3.17 seconds
Started Jul 02 09:59:13 AM PDT 24
Finished Jul 02 09:59:23 AM PDT 24
Peak memory 218228 kb
Host smart-f85c8fa8-64c4-430f-92c3-3c65821d29c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117338501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1117338501
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.3069475083
Short name T431
Test name
Test status
Simulation time 555333130 ps
CPU time 15.57 seconds
Started Jul 02 09:59:16 AM PDT 24
Finished Jul 02 09:59:37 AM PDT 24
Peak memory 226024 kb
Host smart-099c7cf4-8532-45ad-8ae1-ed5784761c2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069475083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.3069475083
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.4009573711
Short name T56
Test name
Test status
Simulation time 521165224 ps
CPU time 19.44 seconds
Started Jul 02 09:59:07 AM PDT 24
Finished Jul 02 09:59:33 AM PDT 24
Peak memory 226032 kb
Host smart-d9fe34da-db6f-4721-a756-18822eceb858
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009573711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.4009573711
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.4022416598
Short name T237
Test name
Test status
Simulation time 773281587 ps
CPU time 13.84 seconds
Started Jul 02 09:59:10 AM PDT 24
Finished Jul 02 09:59:31 AM PDT 24
Peak memory 225928 kb
Host smart-8b6ff260-a6ce-4f8c-9b51-2e61cd89e604
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022416598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
4022416598
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.3386059574
Short name T629
Test name
Test status
Simulation time 1862117537 ps
CPU time 8.61 seconds
Started Jul 02 09:59:10 AM PDT 24
Finished Jul 02 09:59:26 AM PDT 24
Peak memory 224972 kb
Host smart-3cfa8f0d-bf71-4e4d-884d-6a32292cafe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386059574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3386059574
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.3710904255
Short name T326
Test name
Test status
Simulation time 69476388 ps
CPU time 2.75 seconds
Started Jul 02 09:59:07 AM PDT 24
Finished Jul 02 09:59:16 AM PDT 24
Peak memory 217704 kb
Host smart-a8d4e0a8-2e13-4d3e-b759-465a23172ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710904255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3710904255
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.605243566
Short name T855
Test name
Test status
Simulation time 433637448 ps
CPU time 24.02 seconds
Started Jul 02 09:59:10 AM PDT 24
Finished Jul 02 09:59:41 AM PDT 24
Peak memory 250992 kb
Host smart-8465c136-1b83-4aef-8b3b-247547cb3c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605243566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.605243566
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2883979399
Short name T252
Test name
Test status
Simulation time 280405035 ps
CPU time 3.13 seconds
Started Jul 02 09:59:09 AM PDT 24
Finished Jul 02 09:59:27 AM PDT 24
Peak memory 222272 kb
Host smart-790f53c2-941a-445a-9da3-f8940f386c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883979399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2883979399
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.1042126
Short name T86
Test name
Test status
Simulation time 11209622924 ps
CPU time 92.29 seconds
Started Jul 02 09:59:24 AM PDT 24
Finished Jul 02 10:00:59 AM PDT 24
Peak memory 272744 kb
Host smart-10b43b9a-202b-44ac-8dae-c1dd6d4e3b0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1042126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.1042126
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3769329855
Short name T668
Test name
Test status
Simulation time 112027872 ps
CPU time 0.93 seconds
Started Jul 02 09:59:15 AM PDT 24
Finished Jul 02 09:59:22 AM PDT 24
Peak memory 211768 kb
Host smart-4fccb3a4-bbd0-453b-b8ad-2c09dd42cd10
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769329855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.3769329855
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.3736624903
Short name T533
Test name
Test status
Simulation time 15347304 ps
CPU time 0.84 seconds
Started Jul 02 09:59:03 AM PDT 24
Finished Jul 02 09:59:11 AM PDT 24
Peak memory 208992 kb
Host smart-54202325-4997-4705-b5bd-0e44eb2a4ee4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736624903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.3736624903
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.3066381955
Short name T24
Test name
Test status
Simulation time 3796037420 ps
CPU time 8.24 seconds
Started Jul 02 09:59:02 AM PDT 24
Finished Jul 02 09:59:17 AM PDT 24
Peak memory 217752 kb
Host smart-9aaae9c2-1c7e-4a1a-8e2c-c978ffc78de4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066381955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.3066381955
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2820386206
Short name T644
Test name
Test status
Simulation time 59043293 ps
CPU time 2.47 seconds
Started Jul 02 09:59:02 AM PDT 24
Finished Jul 02 09:59:11 AM PDT 24
Peak memory 218144 kb
Host smart-1c466b59-f3fd-4b21-ab64-d19a4543f241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820386206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2820386206
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.4243315686
Short name T267
Test name
Test status
Simulation time 1361604158 ps
CPU time 14.22 seconds
Started Jul 02 09:59:37 AM PDT 24
Finished Jul 02 09:59:54 AM PDT 24
Peak memory 218864 kb
Host smart-ba835cca-1178-4cf1-9661-44fa5bb7f585
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243315686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.4243315686
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2184743179
Short name T768
Test name
Test status
Simulation time 2843332072 ps
CPU time 10.06 seconds
Started Jul 02 09:59:20 AM PDT 24
Finished Jul 02 09:59:34 AM PDT 24
Peak memory 226112 kb
Host smart-8e986386-3cc1-4833-b2ca-2adb2f582091
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184743179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2184743179
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.4165828893
Short name T538
Test name
Test status
Simulation time 442777254 ps
CPU time 10.34 seconds
Started Jul 02 09:59:18 AM PDT 24
Finished Jul 02 09:59:33 AM PDT 24
Peak memory 218264 kb
Host smart-c8dafa98-c08b-4c18-a23b-6512a01199ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165828893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
4165828893
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.534087355
Short name T595
Test name
Test status
Simulation time 1404908606 ps
CPU time 13.21 seconds
Started Jul 02 09:59:08 AM PDT 24
Finished Jul 02 09:59:28 AM PDT 24
Peak memory 226016 kb
Host smart-f97fed43-b97c-4181-8e63-f1aee10aab36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534087355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.534087355
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.518611275
Short name T675
Test name
Test status
Simulation time 88031038 ps
CPU time 3 seconds
Started Jul 02 09:59:19 AM PDT 24
Finished Jul 02 09:59:26 AM PDT 24
Peak memory 217720 kb
Host smart-a32ea351-c6dd-4a3a-8195-ee1a08b386a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518611275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.518611275
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3195497976
Short name T306
Test name
Test status
Simulation time 605718016 ps
CPU time 19.07 seconds
Started Jul 02 09:59:05 AM PDT 24
Finished Jul 02 09:59:30 AM PDT 24
Peak memory 250916 kb
Host smart-b21e0551-fa71-4b16-9048-02d884df4866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195497976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3195497976
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.323369305
Short name T557
Test name
Test status
Simulation time 60400781 ps
CPU time 8.55 seconds
Started Jul 02 09:59:16 AM PDT 24
Finished Jul 02 09:59:30 AM PDT 24
Peak memory 242872 kb
Host smart-d60d0fab-2d7a-4082-8a86-706a5bdd4bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323369305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.323369305
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2500561090
Short name T652
Test name
Test status
Simulation time 4795667053 ps
CPU time 99.85 seconds
Started Jul 02 09:59:07 AM PDT 24
Finished Jul 02 10:00:53 AM PDT 24
Peak memory 280964 kb
Host smart-47a3214d-5847-45b3-81f0-b6734277870a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500561090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2500561090
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.706206770
Short name T206
Test name
Test status
Simulation time 19157821 ps
CPU time 0.87 seconds
Started Jul 02 09:59:17 AM PDT 24
Finished Jul 02 09:59:23 AM PDT 24
Peak memory 211908 kb
Host smart-f3efacd7-8436-44c0-9219-99689935a4be
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706206770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ct
rl_volatile_unlock_smoke.706206770
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.1225926393
Short name T853
Test name
Test status
Simulation time 65057030 ps
CPU time 1 seconds
Started Jul 02 09:59:27 AM PDT 24
Finished Jul 02 09:59:30 AM PDT 24
Peak memory 209040 kb
Host smart-119a1d15-7d6e-445a-89ee-9a057dc3e7e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225926393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.1225926393
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.4181899315
Short name T672
Test name
Test status
Simulation time 277016906 ps
CPU time 10.63 seconds
Started Jul 02 09:59:23 AM PDT 24
Finished Jul 02 09:59:41 AM PDT 24
Peak memory 218236 kb
Host smart-780884ee-5635-451d-91d9-220540ae6854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181899315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.4181899315
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.3249880313
Short name T544
Test name
Test status
Simulation time 189875317 ps
CPU time 2.27 seconds
Started Jul 02 09:59:16 AM PDT 24
Finished Jul 02 09:59:24 AM PDT 24
Peak memory 217256 kb
Host smart-2e94ee93-71b3-40e0-aa32-70b3973368f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249880313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3249880313
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.1456566039
Short name T578
Test name
Test status
Simulation time 44034753 ps
CPU time 2.21 seconds
Started Jul 02 09:59:29 AM PDT 24
Finished Jul 02 09:59:33 AM PDT 24
Peak memory 218220 kb
Host smart-c834b617-f080-458c-8adb-94d2c7c0ed72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456566039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.1456566039
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.1798443256
Short name T265
Test name
Test status
Simulation time 1112631798 ps
CPU time 15.24 seconds
Started Jul 02 09:59:25 AM PDT 24
Finished Jul 02 09:59:42 AM PDT 24
Peak memory 226148 kb
Host smart-a216319b-b706-443e-b17b-3cc6b3c57a59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798443256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1798443256
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3371917389
Short name T212
Test name
Test status
Simulation time 3278942371 ps
CPU time 14.78 seconds
Started Jul 02 09:59:08 AM PDT 24
Finished Jul 02 09:59:30 AM PDT 24
Peak memory 218940 kb
Host smart-b9b38cdf-aba6-452e-a8c9-b5120447c25c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371917389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3371917389
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.3831337019
Short name T661
Test name
Test status
Simulation time 2368920122 ps
CPU time 13.2 seconds
Started Jul 02 09:59:19 AM PDT 24
Finished Jul 02 09:59:37 AM PDT 24
Peak memory 218316 kb
Host smart-f2cddeec-7baa-478c-8afa-5d6e8d5ff104
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831337019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
3831337019
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1436262660
Short name T709
Test name
Test status
Simulation time 905541478 ps
CPU time 10.61 seconds
Started Jul 02 09:59:28 AM PDT 24
Finished Jul 02 09:59:41 AM PDT 24
Peak memory 225996 kb
Host smart-af395106-9134-4c63-9db1-48150215e056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436262660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1436262660
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.1593330366
Short name T790
Test name
Test status
Simulation time 188907600 ps
CPU time 2.12 seconds
Started Jul 02 09:59:32 AM PDT 24
Finished Jul 02 09:59:35 AM PDT 24
Peak memory 214220 kb
Host smart-d081a8e6-edc1-46d2-9ad0-d4c2adc4d77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593330366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.1593330366
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1317293476
Short name T257
Test name
Test status
Simulation time 1216273017 ps
CPU time 28.21 seconds
Started Jul 02 09:59:20 AM PDT 24
Finished Jul 02 09:59:52 AM PDT 24
Peak memory 250908 kb
Host smart-8625681a-3c69-41ae-8ef6-68933e79d4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317293476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1317293476
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.4080545101
Short name T424
Test name
Test status
Simulation time 533678431 ps
CPU time 8.28 seconds
Started Jul 02 09:59:02 AM PDT 24
Finished Jul 02 09:59:17 AM PDT 24
Peak memory 250964 kb
Host smart-0d74cdb7-37c3-4a66-8c45-fc1af5d725a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080545101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.4080545101
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.1046438399
Short name T41
Test name
Test status
Simulation time 22755812597 ps
CPU time 133.6 seconds
Started Jul 02 09:59:22 AM PDT 24
Finished Jul 02 10:01:38 AM PDT 24
Peak memory 276040 kb
Host smart-6444d070-50a5-454f-8377-efebd106f553
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046438399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.1046438399
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1673842645
Short name T255
Test name
Test status
Simulation time 79405497 ps
CPU time 0.84 seconds
Started Jul 02 09:59:13 AM PDT 24
Finished Jul 02 09:59:21 AM PDT 24
Peak memory 211892 kb
Host smart-2c1d7cec-4b33-4e51-bfc5-86ead0cdd83f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673842645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1673842645
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.123304014
Short name T584
Test name
Test status
Simulation time 43133001 ps
CPU time 1.61 seconds
Started Jul 02 09:59:08 AM PDT 24
Finished Jul 02 09:59:16 AM PDT 24
Peak memory 208960 kb
Host smart-1bea7520-38ad-4276-bb09-8f5ac4dd8fea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123304014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.123304014
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.1305742324
Short name T202
Test name
Test status
Simulation time 337457445 ps
CPU time 10 seconds
Started Jul 02 09:59:22 AM PDT 24
Finished Jul 02 09:59:35 AM PDT 24
Peak memory 225960 kb
Host smart-3e074820-4543-4011-9bd7-b45b3c7c0107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305742324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1305742324
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.352670722
Short name T701
Test name
Test status
Simulation time 2442013811 ps
CPU time 7.44 seconds
Started Jul 02 09:59:25 AM PDT 24
Finished Jul 02 09:59:35 AM PDT 24
Peak memory 217696 kb
Host smart-431e7e71-7641-479f-8d24-7852a282c394
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352670722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.352670722
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.1770338496
Short name T406
Test name
Test status
Simulation time 109807951 ps
CPU time 1.81 seconds
Started Jul 02 09:59:32 AM PDT 24
Finished Jul 02 09:59:36 AM PDT 24
Peak memory 218252 kb
Host smart-15314fae-a2bd-4e45-89d1-a402e23d541b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770338496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1770338496
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.882442913
Short name T485
Test name
Test status
Simulation time 3252898699 ps
CPU time 18.58 seconds
Started Jul 02 09:59:21 AM PDT 24
Finished Jul 02 09:59:43 AM PDT 24
Peak memory 226112 kb
Host smart-7d1be726-afc9-4373-b95f-dce0b17514b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882442913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.882442913
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1507504381
Short name T222
Test name
Test status
Simulation time 714959094 ps
CPU time 15.18 seconds
Started Jul 02 09:59:28 AM PDT 24
Finished Jul 02 09:59:45 AM PDT 24
Peak memory 226060 kb
Host smart-7099dbe7-958a-4b9d-9247-63e12997dbc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507504381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.1507504381
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.707565755
Short name T516
Test name
Test status
Simulation time 256823691 ps
CPU time 10 seconds
Started Jul 02 09:59:18 AM PDT 24
Finished Jul 02 09:59:33 AM PDT 24
Peak memory 226052 kb
Host smart-a92e6825-a914-4ba0-a90a-b64b216561b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707565755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.707565755
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.2944913966
Short name T540
Test name
Test status
Simulation time 1670437837 ps
CPU time 8.17 seconds
Started Jul 02 09:59:37 AM PDT 24
Finished Jul 02 09:59:48 AM PDT 24
Peak memory 218384 kb
Host smart-f37c9e16-66f2-4411-bb51-bc6a999f35a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944913966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.2944913966
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1368683246
Short name T158
Test name
Test status
Simulation time 118297431 ps
CPU time 3.79 seconds
Started Jul 02 09:59:05 AM PDT 24
Finished Jul 02 09:59:16 AM PDT 24
Peak memory 214792 kb
Host smart-6d429025-dd1d-4646-a728-5923af5135ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368683246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1368683246
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3250766556
Short name T640
Test name
Test status
Simulation time 2254641033 ps
CPU time 29.71 seconds
Started Jul 02 09:59:14 AM PDT 24
Finished Jul 02 09:59:50 AM PDT 24
Peak memory 251028 kb
Host smart-3de1c069-ede7-44ba-bfc1-c9b61525457c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250766556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3250766556
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.1799591729
Short name T362
Test name
Test status
Simulation time 160045080 ps
CPU time 9.93 seconds
Started Jul 02 09:59:07 AM PDT 24
Finished Jul 02 09:59:24 AM PDT 24
Peak memory 243896 kb
Host smart-7540e66d-90ab-4fa0-8a5a-30ec973a3536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799591729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1799591729
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.2100207663
Short name T848
Test name
Test status
Simulation time 26036952416 ps
CPU time 289.14 seconds
Started Jul 02 09:59:34 AM PDT 24
Finished Jul 02 10:04:26 AM PDT 24
Peak memory 278112 kb
Host smart-8cd38eb0-27f3-4364-9453-42931136d0c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100207663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.2100207663
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.192030564
Short name T96
Test name
Test status
Simulation time 34287621 ps
CPU time 0.86 seconds
Started Jul 02 09:59:28 AM PDT 24
Finished Jul 02 09:59:31 AM PDT 24
Peak memory 211880 kb
Host smart-248cddbd-ac42-42e6-b723-47fc7248692c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192030564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ct
rl_volatile_unlock_smoke.192030564
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.3994499658
Short name T508
Test name
Test status
Simulation time 15176310 ps
CPU time 1.05 seconds
Started Jul 02 09:59:25 AM PDT 24
Finished Jul 02 09:59:28 AM PDT 24
Peak memory 208984 kb
Host smart-5a6bc3bc-a434-4c4d-871c-3f19d44ae920
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994499658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.3994499658
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.20568683
Short name T281
Test name
Test status
Simulation time 1119639010 ps
CPU time 9.08 seconds
Started Jul 02 09:59:30 AM PDT 24
Finished Jul 02 09:59:41 AM PDT 24
Peak memory 218328 kb
Host smart-5da4e100-d7b9-4106-8b41-fb68b4839d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20568683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.20568683
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3885539750
Short name T758
Test name
Test status
Simulation time 1600382088 ps
CPU time 5.17 seconds
Started Jul 02 09:59:42 AM PDT 24
Finished Jul 02 09:59:50 AM PDT 24
Peak memory 217244 kb
Host smart-f5bf67f6-b445-4567-91bd-149c2f829b78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885539750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3885539750
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.1204469869
Short name T290
Test name
Test status
Simulation time 54903932 ps
CPU time 2.68 seconds
Started Jul 02 09:59:24 AM PDT 24
Finished Jul 02 09:59:29 AM PDT 24
Peak memory 218232 kb
Host smart-01421748-6bab-4eed-87df-72d8df73701e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204469869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1204469869
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.2543786266
Short name T630
Test name
Test status
Simulation time 1502573466 ps
CPU time 18.18 seconds
Started Jul 02 09:59:14 AM PDT 24
Finished Jul 02 09:59:38 AM PDT 24
Peak memory 218668 kb
Host smart-321eed37-80f0-48da-be1d-4bc0f3e08a37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543786266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.2543786266
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1981520720
Short name T460
Test name
Test status
Simulation time 877599748 ps
CPU time 11.86 seconds
Started Jul 02 09:59:39 AM PDT 24
Finished Jul 02 09:59:53 AM PDT 24
Peak memory 226000 kb
Host smart-5ae3a40a-9b16-43a4-a5f3-46cca6f166a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981520720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1981520720
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3520551956
Short name T294
Test name
Test status
Simulation time 268378762 ps
CPU time 11.49 seconds
Started Jul 02 09:59:34 AM PDT 24
Finished Jul 02 09:59:48 AM PDT 24
Peak memory 218240 kb
Host smart-a4572514-0251-4dba-9622-0ed90caed972
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520551956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3520551956
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.2886261335
Short name T403
Test name
Test status
Simulation time 538847437 ps
CPU time 14.23 seconds
Started Jul 02 09:59:24 AM PDT 24
Finished Jul 02 09:59:40 AM PDT 24
Peak memory 225960 kb
Host smart-43dc0f14-28a0-4ded-876a-54984b2b9be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886261335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.2886261335
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2339493028
Short name T63
Test name
Test status
Simulation time 305378561 ps
CPU time 3.07 seconds
Started Jul 02 09:59:19 AM PDT 24
Finished Jul 02 09:59:26 AM PDT 24
Peak memory 217704 kb
Host smart-8be264a5-35a6-475b-aa0a-dea348435ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339493028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2339493028
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.288844598
Short name T264
Test name
Test status
Simulation time 189053394 ps
CPU time 19.39 seconds
Started Jul 02 09:59:07 AM PDT 24
Finished Jul 02 09:59:33 AM PDT 24
Peak memory 250956 kb
Host smart-24953027-073d-4a4b-9db9-04de6999d4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288844598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.288844598
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2993095223
Short name T799
Test name
Test status
Simulation time 274519222 ps
CPU time 4.08 seconds
Started Jul 02 09:59:15 AM PDT 24
Finished Jul 02 09:59:25 AM PDT 24
Peak memory 222564 kb
Host smart-28fe6fa7-978e-4f56-b936-24958f5e151f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993095223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2993095223
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.460881226
Short name T154
Test name
Test status
Simulation time 3346807183 ps
CPU time 52.47 seconds
Started Jul 02 09:59:14 AM PDT 24
Finished Jul 02 10:00:13 AM PDT 24
Peak memory 226052 kb
Host smart-03c78955-9e58-47ec-9774-e5bc167085d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460881226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.460881226
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.941588868
Short name T278
Test name
Test status
Simulation time 38520778 ps
CPU time 1.06 seconds
Started Jul 02 09:59:39 AM PDT 24
Finished Jul 02 09:59:42 AM PDT 24
Peak memory 208940 kb
Host smart-f57bae49-c357-4b83-87c4-47e527e28b6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941588868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.941588868
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1854387955
Short name T55
Test name
Test status
Simulation time 2896872477 ps
CPU time 17.65 seconds
Started Jul 02 09:59:22 AM PDT 24
Finished Jul 02 09:59:43 AM PDT 24
Peak memory 218304 kb
Host smart-54b9e2d2-1072-4292-9a80-3d79743b9c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854387955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1854387955
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.775497585
Short name T826
Test name
Test status
Simulation time 1191582084 ps
CPU time 9.87 seconds
Started Jul 02 09:59:25 AM PDT 24
Finished Jul 02 09:59:37 AM PDT 24
Peak memory 217204 kb
Host smart-0ea46907-f599-440c-8f8b-1d06720cbf57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775497585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.775497585
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.1961226502
Short name T681
Test name
Test status
Simulation time 45820925 ps
CPU time 2.11 seconds
Started Jul 02 09:59:23 AM PDT 24
Finished Jul 02 09:59:28 AM PDT 24
Peak memory 218248 kb
Host smart-a14247bb-eb78-4930-8092-d1e52b627986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961226502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.1961226502
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.1266578215
Short name T639
Test name
Test status
Simulation time 2156832469 ps
CPU time 16.66 seconds
Started Jul 02 09:59:26 AM PDT 24
Finished Jul 02 09:59:45 AM PDT 24
Peak memory 220000 kb
Host smart-1bce64df-333a-4dc1-8b26-ed1795a0e356
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266578215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.1266578215
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3258704291
Short name T625
Test name
Test status
Simulation time 1417352358 ps
CPU time 9.63 seconds
Started Jul 02 09:59:25 AM PDT 24
Finished Jul 02 09:59:37 AM PDT 24
Peak memory 226120 kb
Host smart-b3ce31bf-0f3a-4cd7-8361-5dc02a940e63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258704291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.3258704291
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.2459043306
Short name T62
Test name
Test status
Simulation time 1190890454 ps
CPU time 9.26 seconds
Started Jul 02 09:59:33 AM PDT 24
Finished Jul 02 09:59:43 AM PDT 24
Peak memory 218232 kb
Host smart-11da5072-c546-4a24-bfa3-3e30f134d9f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459043306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
2459043306
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.1464916661
Short name T351
Test name
Test status
Simulation time 351549929 ps
CPU time 9.13 seconds
Started Jul 02 09:59:33 AM PDT 24
Finished Jul 02 09:59:43 AM PDT 24
Peak memory 224864 kb
Host smart-4a611188-3e07-41b9-ba65-7dd43bbf1b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464916661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1464916661
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.3198418902
Short name T624
Test name
Test status
Simulation time 196061891 ps
CPU time 1.3 seconds
Started Jul 02 09:59:18 AM PDT 24
Finished Jul 02 09:59:24 AM PDT 24
Peak memory 213720 kb
Host smart-bb762ae2-7f47-44d3-8d8a-dbbb414c6455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198418902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3198418902
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.2336852181
Short name T13
Test name
Test status
Simulation time 249746240 ps
CPU time 24.01 seconds
Started Jul 02 09:59:45 AM PDT 24
Finished Jul 02 10:00:10 AM PDT 24
Peak memory 247436 kb
Host smart-a362c956-a161-4734-9806-7b6c11457db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336852181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.2336852181
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.4132890666
Short name T440
Test name
Test status
Simulation time 46539186 ps
CPU time 6.39 seconds
Started Jul 02 09:59:10 AM PDT 24
Finished Jul 02 09:59:23 AM PDT 24
Peak memory 246392 kb
Host smart-0748ebde-b3f8-4c9a-b106-19b99bb815fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132890666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.4132890666
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3996395249
Short name T427
Test name
Test status
Simulation time 8961043634 ps
CPU time 254.43 seconds
Started Jul 02 09:59:25 AM PDT 24
Finished Jul 02 10:03:42 AM PDT 24
Peak memory 311464 kb
Host smart-87a0b660-00e5-45ac-a9d0-f822e7318452
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996395249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3996395249
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.2751705112
Short name T100
Test name
Test status
Simulation time 107456623250 ps
CPU time 572.98 seconds
Started Jul 02 09:59:24 AM PDT 24
Finished Jul 02 10:09:00 AM PDT 24
Peak memory 480568 kb
Host smart-e56a6525-fc1e-4052-ae0c-36cf93e2c404
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2751705112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.2751705112
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3898412679
Short name T399
Test name
Test status
Simulation time 25938020 ps
CPU time 0.89 seconds
Started Jul 02 09:59:22 AM PDT 24
Finished Jul 02 09:59:26 AM PDT 24
Peak memory 211792 kb
Host smart-5ae94471-10a8-411b-96d8-f1d204d1cebb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898412679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3898412679
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.97684148
Short name T671
Test name
Test status
Simulation time 68233810 ps
CPU time 1.16 seconds
Started Jul 02 09:59:34 AM PDT 24
Finished Jul 02 09:59:37 AM PDT 24
Peak memory 208996 kb
Host smart-7ba68c21-b505-412a-b9f7-43cf90263670
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97684148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.97684148
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2182618932
Short name T606
Test name
Test status
Simulation time 314301067 ps
CPU time 15.03 seconds
Started Jul 02 09:59:28 AM PDT 24
Finished Jul 02 09:59:45 AM PDT 24
Peak memory 218220 kb
Host smart-bbf77a44-c9ff-41b6-9644-ed094bc3c9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182618932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2182618932
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.43886680
Short name T25
Test name
Test status
Simulation time 231428950 ps
CPU time 3.26 seconds
Started Jul 02 09:59:52 AM PDT 24
Finished Jul 02 09:59:57 AM PDT 24
Peak memory 217148 kb
Host smart-b9488b6b-b392-4175-8af6-2f1f2ecf8912
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43886680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.43886680
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.1713319819
Short name T805
Test name
Test status
Simulation time 77061662 ps
CPU time 3.25 seconds
Started Jul 02 09:59:31 AM PDT 24
Finished Jul 02 09:59:35 AM PDT 24
Peak memory 222384 kb
Host smart-df7c1155-5f4c-49ea-bc90-daba93a9c821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713319819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.1713319819
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2742518344
Short name T654
Test name
Test status
Simulation time 689477499 ps
CPU time 14.84 seconds
Started Jul 02 09:59:37 AM PDT 24
Finished Jul 02 09:59:55 AM PDT 24
Peak memory 226016 kb
Host smart-27d2c18d-513e-4d14-9a79-618dcf3d09a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742518344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.2742518344
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.4117321425
Short name T301
Test name
Test status
Simulation time 382712985 ps
CPU time 7.33 seconds
Started Jul 02 09:59:34 AM PDT 24
Finished Jul 02 09:59:43 AM PDT 24
Peak memory 218232 kb
Host smart-44002b93-8012-4405-8a5e-cab3ab4375c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117321425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
4117321425
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3949489067
Short name T195
Test name
Test status
Simulation time 1472107053 ps
CPU time 14.92 seconds
Started Jul 02 09:59:42 AM PDT 24
Finished Jul 02 09:59:59 AM PDT 24
Peak memory 218168 kb
Host smart-bbe3811d-8efc-47dd-a8eb-eb9ef0b2c90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949489067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3949489067
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.1344975709
Short name T241
Test name
Test status
Simulation time 267638341 ps
CPU time 5.98 seconds
Started Jul 02 09:59:17 AM PDT 24
Finished Jul 02 09:59:29 AM PDT 24
Peak memory 217852 kb
Host smart-cc3a1cfd-50c0-474f-9697-a2c69a0837bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344975709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1344975709
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.4076759020
Short name T657
Test name
Test status
Simulation time 312281276 ps
CPU time 11.52 seconds
Started Jul 02 09:59:22 AM PDT 24
Finished Jul 02 09:59:37 AM PDT 24
Peak memory 251116 kb
Host smart-1125cf22-328b-4b7f-89db-1ee3bd1ec216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076759020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.4076759020
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1079299026
Short name T523
Test name
Test status
Simulation time 157836443 ps
CPU time 2.93 seconds
Started Jul 02 09:59:19 AM PDT 24
Finished Jul 02 09:59:26 AM PDT 24
Peak memory 224160 kb
Host smart-e72354aa-5609-499d-be9a-3fb0977a6e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079299026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1079299026
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.623390974
Short name T478
Test name
Test status
Simulation time 2216562188 ps
CPU time 84.13 seconds
Started Jul 02 09:59:26 AM PDT 24
Finished Jul 02 10:00:56 AM PDT 24
Peak memory 270012 kb
Host smart-a044425e-3db9-4e54-9d98-d3f41d123a47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623390974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.623390974
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2791928225
Short name T12
Test name
Test status
Simulation time 11255951 ps
CPU time 0.84 seconds
Started Jul 02 09:59:21 AM PDT 24
Finished Jul 02 09:59:25 AM PDT 24
Peak memory 211824 kb
Host smart-bda69fe2-d11a-45c0-b169-2484dd9b189e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791928225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.2791928225
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.2242423580
Short name T658
Test name
Test status
Simulation time 22431745 ps
CPU time 0.82 seconds
Started Jul 02 09:57:55 AM PDT 24
Finished Jul 02 09:57:59 AM PDT 24
Peak memory 208776 kb
Host smart-b6250ae6-648f-45fb-87c7-852e0f8ac804
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242423580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.2242423580
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.117654784
Short name T229
Test name
Test status
Simulation time 18889633 ps
CPU time 0.82 seconds
Started Jul 02 09:57:55 AM PDT 24
Finished Jul 02 09:57:59 AM PDT 24
Peak memory 208984 kb
Host smart-78b4f421-45de-47fe-9e27-b23c56b2d4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117654784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.117654784
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.1321306221
Short name T462
Test name
Test status
Simulation time 3257047176 ps
CPU time 11.04 seconds
Started Jul 02 09:58:01 AM PDT 24
Finished Jul 02 09:58:14 AM PDT 24
Peak memory 219196 kb
Host smart-475bc32e-6bb0-472e-9b72-20a829d3e8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321306221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1321306221
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2023881019
Short name T840
Test name
Test status
Simulation time 209908973 ps
CPU time 2.89 seconds
Started Jul 02 09:58:02 AM PDT 24
Finished Jul 02 09:58:08 AM PDT 24
Peak memory 217280 kb
Host smart-c4bc552f-c771-4239-8827-d137118e7f79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023881019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2023881019
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.2731954622
Short name T388
Test name
Test status
Simulation time 2802234582 ps
CPU time 36.62 seconds
Started Jul 02 09:57:58 AM PDT 24
Finished Jul 02 09:58:37 AM PDT 24
Peak memory 219048 kb
Host smart-a3f538d5-f793-4966-be9b-a5ec6f485dfa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731954622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.2731954622
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.3126482033
Short name T9
Test name
Test status
Simulation time 240430300 ps
CPU time 2.07 seconds
Started Jul 02 09:57:58 AM PDT 24
Finished Jul 02 09:58:02 AM PDT 24
Peak memory 217384 kb
Host smart-f3ef1dee-0b87-451a-b44a-b868b3a91158
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126482033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.3
126482033
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.2526620972
Short name T649
Test name
Test status
Simulation time 607699093 ps
CPU time 8.94 seconds
Started Jul 02 09:58:13 AM PDT 24
Finished Jul 02 09:58:27 AM PDT 24
Peak memory 218268 kb
Host smart-cac39b2a-a410-42a5-a1c2-e82005923aec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526620972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.2526620972
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3671598929
Short name T475
Test name
Test status
Simulation time 2709983996 ps
CPU time 20.95 seconds
Started Jul 02 09:57:56 AM PDT 24
Finished Jul 02 09:58:20 AM PDT 24
Peak memory 217788 kb
Host smart-ad08e6a9-b607-4778-bfed-41ece548a165
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671598929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.3671598929
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1266559006
Short name T81
Test name
Test status
Simulation time 423111803 ps
CPU time 6.19 seconds
Started Jul 02 09:58:15 AM PDT 24
Finished Jul 02 09:58:25 AM PDT 24
Peak memory 217720 kb
Host smart-35393fdd-7ca8-4774-aaaa-cc8b111501d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266559006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1266559006
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3270465742
Short name T802
Test name
Test status
Simulation time 1121164995 ps
CPU time 34.69 seconds
Started Jul 02 09:57:55 AM PDT 24
Finished Jul 02 09:58:33 AM PDT 24
Peak memory 267388 kb
Host smart-0eec877f-966e-4f5a-a31a-5444e375e592
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270465742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3270465742
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.622132351
Short name T859
Test name
Test status
Simulation time 407182042 ps
CPU time 13.23 seconds
Started Jul 02 09:58:01 AM PDT 24
Finished Jul 02 09:58:17 AM PDT 24
Peak memory 251000 kb
Host smart-44b00b78-5991-4f71-96ae-cb7ae70829af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622132351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_state_post_trans.622132351
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1923789066
Short name T378
Test name
Test status
Simulation time 61711878 ps
CPU time 2.3 seconds
Started Jul 02 09:58:01 AM PDT 24
Finished Jul 02 09:58:06 AM PDT 24
Peak memory 218224 kb
Host smart-d240e3d6-bbe2-4d58-bd91-f5ed5f9ad36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923789066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1923789066
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.2413569421
Short name T165
Test name
Test status
Simulation time 613340662 ps
CPU time 22.84 seconds
Started Jul 02 09:57:53 AM PDT 24
Finished Jul 02 09:58:19 AM PDT 24
Peak memory 214392 kb
Host smart-32cf4d11-0fcb-4bfc-b3d7-950eaedb7230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413569421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2413569421
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2768456861
Short name T373
Test name
Test status
Simulation time 1538108568 ps
CPU time 12.25 seconds
Started Jul 02 09:57:50 AM PDT 24
Finished Jul 02 09:58:05 AM PDT 24
Peak memory 226048 kb
Host smart-5444cab1-1a5c-4de6-a942-f0502ab1804d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768456861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2768456861
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.1929505862
Short name T847
Test name
Test status
Simulation time 253606115 ps
CPU time 11.61 seconds
Started Jul 02 09:57:50 AM PDT 24
Finished Jul 02 09:58:05 AM PDT 24
Peak memory 226056 kb
Host smart-9c3a210c-45da-4f9a-b7de-1a425cef6cdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929505862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.1929505862
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.2905564310
Short name T472
Test name
Test status
Simulation time 298398965 ps
CPU time 10.54 seconds
Started Jul 02 09:58:05 AM PDT 24
Finished Jul 02 09:58:21 AM PDT 24
Peak memory 225968 kb
Host smart-4a28a270-ff09-4eed-8785-7aab4fe06848
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905564310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.2
905564310
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1267225296
Short name T342
Test name
Test status
Simulation time 1412230779 ps
CPU time 12.13 seconds
Started Jul 02 09:57:52 AM PDT 24
Finished Jul 02 09:58:07 AM PDT 24
Peak memory 225920 kb
Host smart-68b559be-28a7-4bb7-aed3-0b992f546d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267225296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1267225296
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.1211341920
Short name T465
Test name
Test status
Simulation time 124536826 ps
CPU time 2.89 seconds
Started Jul 02 09:57:52 AM PDT 24
Finished Jul 02 09:57:58 AM PDT 24
Peak memory 217728 kb
Host smart-c9814502-6357-4d98-a814-a8cfca43918d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211341920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.1211341920
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1376628479
Short name T322
Test name
Test status
Simulation time 237113895 ps
CPU time 21.52 seconds
Started Jul 02 09:58:10 AM PDT 24
Finished Jul 02 09:58:38 AM PDT 24
Peak memory 251024 kb
Host smart-4fb667ea-86a3-4cac-a696-cdcfa95c24a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376628479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1376628479
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.1979138372
Short name T372
Test name
Test status
Simulation time 55442222 ps
CPU time 5.88 seconds
Started Jul 02 09:57:55 AM PDT 24
Finished Jul 02 09:58:04 AM PDT 24
Peak memory 246108 kb
Host smart-a96ab19a-5052-4667-8d58-5869db629881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979138372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.1979138372
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.2213165929
Short name T231
Test name
Test status
Simulation time 12368971346 ps
CPU time 37.86 seconds
Started Jul 02 09:58:01 AM PDT 24
Finished Jul 02 09:58:41 AM PDT 24
Peak memory 226072 kb
Host smart-824726eb-d7a9-4005-8f92-128919257d83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213165929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.2213165929
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2769427809
Short name T809
Test name
Test status
Simulation time 13990334 ps
CPU time 0.97 seconds
Started Jul 02 09:58:03 AM PDT 24
Finished Jul 02 09:58:08 AM PDT 24
Peak memory 213068 kb
Host smart-7f7a3beb-378d-43b1-adb5-ff118e6aee9d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769427809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.2769427809
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.4186563414
Short name T456
Test name
Test status
Simulation time 53292710 ps
CPU time 0.85 seconds
Started Jul 02 09:58:01 AM PDT 24
Finished Jul 02 09:58:04 AM PDT 24
Peak memory 208796 kb
Host smart-9d36671a-3fe1-4728-aa9f-e3fecf2d9002
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186563414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.4186563414
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.1888358241
Short name T791
Test name
Test status
Simulation time 226279280 ps
CPU time 11.53 seconds
Started Jul 02 09:58:07 AM PDT 24
Finished Jul 02 09:58:24 AM PDT 24
Peak memory 218192 kb
Host smart-ffb89e36-5699-405c-826a-e9aa00e14c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888358241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1888358241
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.3692945392
Short name T430
Test name
Test status
Simulation time 1409406698 ps
CPU time 11.3 seconds
Started Jul 02 09:57:59 AM PDT 24
Finished Jul 02 09:58:12 AM PDT 24
Peak memory 217424 kb
Host smart-9fd330cb-a53f-4d43-b118-65779f042994
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692945392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.3692945392
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.3592934438
Short name T375
Test name
Test status
Simulation time 7225224590 ps
CPU time 49.09 seconds
Started Jul 02 09:58:04 AM PDT 24
Finished Jul 02 09:58:58 AM PDT 24
Peak memory 226108 kb
Host smart-84012cd0-a395-4be5-9882-f08548b68ad1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592934438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.3592934438
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1971166674
Short name T186
Test name
Test status
Simulation time 5700558772 ps
CPU time 9.83 seconds
Started Jul 02 09:58:06 AM PDT 24
Finished Jul 02 09:58:22 AM PDT 24
Peak memory 217852 kb
Host smart-83283e72-01ba-4d75-b625-d9e050914269
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971166674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
971166674
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3271764171
Short name T622
Test name
Test status
Simulation time 368120004 ps
CPU time 7.57 seconds
Started Jul 02 09:58:02 AM PDT 24
Finished Jul 02 09:58:12 AM PDT 24
Peak memory 218204 kb
Host smart-0e1cc915-3dd2-4e02-9135-ad9ed719c2e0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271764171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.3271764171
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1371975556
Short name T286
Test name
Test status
Simulation time 4711667374 ps
CPU time 21.18 seconds
Started Jul 02 09:58:04 AM PDT 24
Finished Jul 02 09:58:31 AM PDT 24
Peak memory 217700 kb
Host smart-f85361a0-df42-4fc4-a10c-633bc23ea67f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371975556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1371975556
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3503036372
Short name T603
Test name
Test status
Simulation time 69492883 ps
CPU time 1.99 seconds
Started Jul 02 09:58:02 AM PDT 24
Finished Jul 02 09:58:06 AM PDT 24
Peak memory 217932 kb
Host smart-be1db686-4594-4ae0-bb30-48f39150ce1f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503036372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3503036372
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.951269185
Short name T436
Test name
Test status
Simulation time 9902590044 ps
CPU time 52.98 seconds
Started Jul 02 09:58:00 AM PDT 24
Finished Jul 02 09:58:55 AM PDT 24
Peak memory 279576 kb
Host smart-79b4d251-1c61-4615-bd0b-bc166f0bdbc4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951269185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_state_failure.951269185
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.233445770
Short name T551
Test name
Test status
Simulation time 594282998 ps
CPU time 15.14 seconds
Started Jul 02 09:57:58 AM PDT 24
Finished Jul 02 09:58:15 AM PDT 24
Peak memory 250916 kb
Host smart-fb97c6c3-80eb-407d-b6e6-31a4f3073bc1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233445770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_state_post_trans.233445770
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3634461365
Short name T457
Test name
Test status
Simulation time 88410311 ps
CPU time 3.74 seconds
Started Jul 02 09:58:02 AM PDT 24
Finished Jul 02 09:58:08 AM PDT 24
Peak memory 222316 kb
Host smart-33fdb364-5eeb-422c-a13a-babc98f86278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634461365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3634461365
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3924963269
Short name T776
Test name
Test status
Simulation time 297815107 ps
CPU time 4.8 seconds
Started Jul 02 09:58:01 AM PDT 24
Finished Jul 02 09:58:08 AM PDT 24
Peak memory 222880 kb
Host smart-33f167ff-829b-493c-af6f-689354eb3fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924963269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3924963269
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.3890579899
Short name T796
Test name
Test status
Simulation time 345690991 ps
CPU time 16.1 seconds
Started Jul 02 09:58:06 AM PDT 24
Finished Jul 02 09:58:28 AM PDT 24
Peak memory 219468 kb
Host smart-c069acfb-8dae-4a59-a045-468c19310814
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890579899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3890579899
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1441518532
Short name T279
Test name
Test status
Simulation time 759677225 ps
CPU time 14.46 seconds
Started Jul 02 09:58:08 AM PDT 24
Finished Jul 02 09:58:29 AM PDT 24
Peak memory 226028 kb
Host smart-ef39c5ca-51ca-4a92-a759-4009aee305b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441518532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.1441518532
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2449079459
Short name T99
Test name
Test status
Simulation time 267813419 ps
CPU time 7.11 seconds
Started Jul 02 09:58:06 AM PDT 24
Finished Jul 02 09:58:19 AM PDT 24
Peak memory 218240 kb
Host smart-72949a42-359e-4c78-81b0-64ab4ee9b2b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449079459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
449079459
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.295407406
Short name T572
Test name
Test status
Simulation time 538888534 ps
CPU time 9.69 seconds
Started Jul 02 09:58:12 AM PDT 24
Finished Jul 02 09:58:27 AM PDT 24
Peak memory 226056 kb
Host smart-684ef127-b41d-4556-81f7-49a5330ccf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295407406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.295407406
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.3243560213
Short name T836
Test name
Test status
Simulation time 13931321 ps
CPU time 1.22 seconds
Started Jul 02 09:58:05 AM PDT 24
Finished Jul 02 09:58:13 AM PDT 24
Peak memory 213632 kb
Host smart-fa8df366-8cc6-4a7f-a53e-72e387e50d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243560213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3243560213
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.2662481662
Short name T643
Test name
Test status
Simulation time 722634216 ps
CPU time 15.61 seconds
Started Jul 02 09:58:01 AM PDT 24
Finished Jul 02 09:58:19 AM PDT 24
Peak memory 250928 kb
Host smart-2f1295f2-3f37-4917-afe7-21da2dddf153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662481662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.2662481662
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3140106342
Short name T564
Test name
Test status
Simulation time 362181315 ps
CPU time 6.46 seconds
Started Jul 02 09:58:03 AM PDT 24
Finished Jul 02 09:58:12 AM PDT 24
Peak memory 247060 kb
Host smart-fd4b7a26-3edf-4c9b-9e8f-f3fc41e8e8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140106342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3140106342
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.3269533141
Short name T284
Test name
Test status
Simulation time 6234225771 ps
CPU time 133.98 seconds
Started Jul 02 09:58:03 AM PDT 24
Finished Jul 02 10:00:21 AM PDT 24
Peak memory 305780 kb
Host smart-55b684f8-859c-4565-8fc1-bae660afa466
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269533141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.3269533141
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.3021444935
Short name T555
Test name
Test status
Simulation time 22413291809 ps
CPU time 563.76 seconds
Started Jul 02 09:58:07 AM PDT 24
Finished Jul 02 10:07:37 AM PDT 24
Peak memory 464200 kb
Host smart-c3284627-40a9-48de-bea6-1a8df01692f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3021444935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.3021444935
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1253085121
Short name T781
Test name
Test status
Simulation time 48845751 ps
CPU time 0.89 seconds
Started Jul 02 09:58:03 AM PDT 24
Finished Jul 02 09:58:09 AM PDT 24
Peak memory 211912 kb
Host smart-7608aeab-16a5-4bd8-910c-aab1088a58cf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253085121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.1253085121
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.3041837524
Short name T757
Test name
Test status
Simulation time 77117688 ps
CPU time 1.17 seconds
Started Jul 02 09:58:04 AM PDT 24
Finished Jul 02 09:58:10 AM PDT 24
Peak memory 209000 kb
Host smart-85d354d1-be4a-448f-b304-df5148338462
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041837524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.3041837524
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2365349946
Short name T189
Test name
Test status
Simulation time 15151785 ps
CPU time 1.05 seconds
Started Jul 02 09:58:03 AM PDT 24
Finished Jul 02 09:58:07 AM PDT 24
Peak memory 209008 kb
Host smart-c6c74a76-3a58-4fc9-bf12-5c35ee5dcb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365349946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2365349946
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.3579028632
Short name T759
Test name
Test status
Simulation time 641164653 ps
CPU time 9.6 seconds
Started Jul 02 09:58:07 AM PDT 24
Finished Jul 02 09:58:24 AM PDT 24
Peak memory 226120 kb
Host smart-ac06ece2-1aea-4591-9d7e-1ae6731c39dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579028632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3579028632
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.3525841863
Short name T1
Test name
Test status
Simulation time 36150559 ps
CPU time 1.21 seconds
Started Jul 02 09:58:02 AM PDT 24
Finished Jul 02 09:58:06 AM PDT 24
Peak memory 217184 kb
Host smart-3078d61d-ad78-42ea-9089-019e430edbb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525841863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.3525841863
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.1295065665
Short name T712
Test name
Test status
Simulation time 1106648112 ps
CPU time 19.45 seconds
Started Jul 02 09:58:05 AM PDT 24
Finished Jul 02 09:58:31 AM PDT 24
Peak memory 218120 kb
Host smart-3e207abe-2948-4ee7-891d-610e11129e61
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295065665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.1295065665
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.1148169282
Short name T692
Test name
Test status
Simulation time 941839668 ps
CPU time 6.77 seconds
Started Jul 02 09:58:08 AM PDT 24
Finished Jul 02 09:58:21 AM PDT 24
Peak memory 217756 kb
Host smart-29e3fc82-4512-48f5-a461-782464255bcc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148169282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.1
148169282
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.482487178
Short name T499
Test name
Test status
Simulation time 1104944808 ps
CPU time 4.9 seconds
Started Jul 02 09:58:02 AM PDT 24
Finished Jul 02 09:58:10 AM PDT 24
Peak memory 218236 kb
Host smart-a7fc23e8-8f8f-444c-b4d8-5c33d1f009a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482487178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
prog_failure.482487178
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.95912059
Short name T733
Test name
Test status
Simulation time 2329405033 ps
CPU time 19.54 seconds
Started Jul 02 09:58:02 AM PDT 24
Finished Jul 02 09:58:25 AM PDT 24
Peak memory 217764 kb
Host smart-00906c98-c001-4bfc-bf19-f33d92ed4b1b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95912059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jt
ag_regwen_during_op.95912059
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1307782298
Short name T429
Test name
Test status
Simulation time 1281164782 ps
CPU time 7.77 seconds
Started Jul 02 09:58:05 AM PDT 24
Finished Jul 02 09:58:18 AM PDT 24
Peak memory 217716 kb
Host smart-ef940d62-1895-421e-8490-3eb02f657784
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307782298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1307782298
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1206397591
Short name T377
Test name
Test status
Simulation time 5215309832 ps
CPU time 92.18 seconds
Started Jul 02 09:58:17 AM PDT 24
Finished Jul 02 09:59:52 AM PDT 24
Peak memory 283708 kb
Host smart-eaa571c6-11f8-4b67-8fca-4b7cebad3afa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206397591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1206397591
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.628517781
Short name T419
Test name
Test status
Simulation time 491264106 ps
CPU time 11.32 seconds
Started Jul 02 09:57:55 AM PDT 24
Finished Jul 02 09:58:09 AM PDT 24
Peak memory 247532 kb
Host smart-b29528ae-7b09-490c-b0a6-9ac1255d4d51
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628517781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_state_post_trans.628517781
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.2791942387
Short name T599
Test name
Test status
Simulation time 72710547 ps
CPU time 3.43 seconds
Started Jul 02 09:58:04 AM PDT 24
Finished Jul 02 09:58:11 AM PDT 24
Peak memory 218228 kb
Host smart-406e4816-76ac-4bdc-81a1-738b3c40accc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791942387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.2791942387
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.1074468389
Short name T473
Test name
Test status
Simulation time 738519875 ps
CPU time 13.07 seconds
Started Jul 02 09:58:03 AM PDT 24
Finished Jul 02 09:58:19 AM PDT 24
Peak memory 217708 kb
Host smart-1eb1539e-1039-44d4-bcc2-179da8d9b09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074468389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.1074468389
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.3816114776
Short name T468
Test name
Test status
Simulation time 327736272 ps
CPU time 14.65 seconds
Started Jul 02 09:58:14 AM PDT 24
Finished Jul 02 09:58:33 AM PDT 24
Peak memory 218908 kb
Host smart-b789f907-3e31-4221-82d7-1624811d097c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816114776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.3816114776
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3041863124
Short name T225
Test name
Test status
Simulation time 1905991791 ps
CPU time 13.9 seconds
Started Jul 02 09:58:04 AM PDT 24
Finished Jul 02 09:58:28 AM PDT 24
Peak memory 226024 kb
Host smart-696fda0f-9422-420b-bb39-4af74202ac44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041863124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3041863124
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.3159991004
Short name T839
Test name
Test status
Simulation time 1409147007 ps
CPU time 8.39 seconds
Started Jul 02 09:58:06 AM PDT 24
Finished Jul 02 09:58:20 AM PDT 24
Peak memory 226132 kb
Host smart-15df236b-ccec-49ac-987a-0a53c6251ba5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159991004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.3
159991004
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.900170305
Short name T735
Test name
Test status
Simulation time 1187223959 ps
CPU time 7.05 seconds
Started Jul 02 09:58:02 AM PDT 24
Finished Jul 02 09:58:12 AM PDT 24
Peak memory 226064 kb
Host smart-f889af6d-7a9e-4592-a6ee-e018042b016a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900170305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.900170305
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1113834500
Short name T78
Test name
Test status
Simulation time 33461086 ps
CPU time 1.27 seconds
Started Jul 02 09:58:00 AM PDT 24
Finished Jul 02 09:58:04 AM PDT 24
Peak memory 221652 kb
Host smart-89eb1272-1c21-41b5-aa8b-ccc72641fc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113834500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1113834500
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1800617577
Short name T230
Test name
Test status
Simulation time 506968880 ps
CPU time 28.77 seconds
Started Jul 02 09:58:05 AM PDT 24
Finished Jul 02 09:58:39 AM PDT 24
Peak memory 250976 kb
Host smart-3f73c77e-cf37-4856-b1b5-24f1ca0cf2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800617577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1800617577
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.736888076
Short name T289
Test name
Test status
Simulation time 403119486 ps
CPU time 8.1 seconds
Started Jul 02 09:57:53 AM PDT 24
Finished Jul 02 09:58:04 AM PDT 24
Peak memory 250940 kb
Host smart-7007d6c0-c0e6-487a-b8e0-d010d46af9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736888076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.736888076
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.3297823149
Short name T663
Test name
Test status
Simulation time 73325609954 ps
CPU time 396.95 seconds
Started Jul 02 09:58:04 AM PDT 24
Finished Jul 02 10:04:46 AM PDT 24
Peak memory 283776 kb
Host smart-0dee2485-eb4d-4fcd-831a-bd232c2d5a5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297823149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.3297823149
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.1553932481
Short name T143
Test name
Test status
Simulation time 17292518353 ps
CPU time 74.68 seconds
Started Jul 02 09:58:04 AM PDT 24
Finished Jul 02 09:59:23 AM PDT 24
Peak memory 234440 kb
Host smart-f58f2131-34f1-4840-b9a0-a8794ce07374
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1553932481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.1553932481
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1263283902
Short name T336
Test name
Test status
Simulation time 65679679 ps
CPU time 0.83 seconds
Started Jul 02 09:58:04 AM PDT 24
Finished Jul 02 09:58:10 AM PDT 24
Peak memory 211892 kb
Host smart-c6890c58-8987-449a-ad18-b8d11baed0ce
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263283902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1263283902
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.514494037
Short name T509
Test name
Test status
Simulation time 48241184 ps
CPU time 0.94 seconds
Started Jul 02 09:58:05 AM PDT 24
Finished Jul 02 09:58:17 AM PDT 24
Peak memory 208992 kb
Host smart-4840e370-bb8f-45c5-bd5b-60dada104d3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514494037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.514494037
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.769797910
Short name T2
Test name
Test status
Simulation time 22662861 ps
CPU time 0.88 seconds
Started Jul 02 09:58:03 AM PDT 24
Finished Jul 02 09:58:07 AM PDT 24
Peak memory 208844 kb
Host smart-02bd8e5e-87ae-45e4-b639-e39e04765bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769797910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.769797910
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.918937005
Short name T705
Test name
Test status
Simulation time 287807215 ps
CPU time 8.6 seconds
Started Jul 02 09:58:03 AM PDT 24
Finished Jul 02 09:58:15 AM PDT 24
Peak memory 218156 kb
Host smart-ff0462d6-8d2a-44d2-80d3-efd5b400de38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918937005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.918937005
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.3919960951
Short name T785
Test name
Test status
Simulation time 1713588611 ps
CPU time 5.44 seconds
Started Jul 02 09:58:06 AM PDT 24
Finished Jul 02 09:58:17 AM PDT 24
Peak memory 217232 kb
Host smart-bde8a50f-b8dc-4fad-a929-77a5354fcf1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919960951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3919960951
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.2147034906
Short name T354
Test name
Test status
Simulation time 3960147282 ps
CPU time 33.81 seconds
Started Jul 02 09:58:07 AM PDT 24
Finished Jul 02 09:58:47 AM PDT 24
Peak memory 218924 kb
Host smart-b191dc1f-6aa5-4664-8554-d79aac93593c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147034906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.2147034906
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1631741056
Short name T589
Test name
Test status
Simulation time 365323735 ps
CPU time 2.7 seconds
Started Jul 02 09:58:05 AM PDT 24
Finished Jul 02 09:58:14 AM PDT 24
Peak memory 217584 kb
Host smart-2d9445e3-8027-4605-81cb-db277c59d17a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631741056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.1
631741056
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3322855671
Short name T358
Test name
Test status
Simulation time 4624042250 ps
CPU time 16.47 seconds
Started Jul 02 09:58:05 AM PDT 24
Finished Jul 02 09:58:26 AM PDT 24
Peak memory 218916 kb
Host smart-6f2af1c6-6f43-4eec-acc9-27c62be1524e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322855671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3322855671
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3352061587
Short name T471
Test name
Test status
Simulation time 1289584874 ps
CPU time 24.15 seconds
Started Jul 02 09:58:04 AM PDT 24
Finished Jul 02 09:58:33 AM PDT 24
Peak memory 217628 kb
Host smart-5e6ffc0f-e35e-4fc9-85bd-a7b7f13f62c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352061587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.3352061587
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.4141943222
Short name T542
Test name
Test status
Simulation time 726019583 ps
CPU time 5.12 seconds
Started Jul 02 09:58:05 AM PDT 24
Finished Jul 02 09:58:15 AM PDT 24
Peak memory 217700 kb
Host smart-71083cf7-9e35-4848-a12d-8a30cacf2620
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141943222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
4141943222
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.228213951
Short name T515
Test name
Test status
Simulation time 2079944867 ps
CPU time 50.35 seconds
Started Jul 02 09:58:07 AM PDT 24
Finished Jul 02 09:59:04 AM PDT 24
Peak memory 267400 kb
Host smart-ce450bba-8b17-42b7-8937-687b9a1789f8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228213951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_state_failure.228213951
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3501690818
Short name T324
Test name
Test status
Simulation time 5547185460 ps
CPU time 16.41 seconds
Started Jul 02 09:58:04 AM PDT 24
Finished Jul 02 09:58:24 AM PDT 24
Peak memory 251020 kb
Host smart-b48b10c9-2029-44b1-bfd7-ac6c34296811
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501690818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.3501690818
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.536381245
Short name T677
Test name
Test status
Simulation time 368657828 ps
CPU time 3.11 seconds
Started Jul 02 09:58:09 AM PDT 24
Finished Jul 02 09:58:19 AM PDT 24
Peak memory 218200 kb
Host smart-90bcd636-91f3-4ff4-a362-e8875ce9d8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536381245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.536381245
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3680463412
Short name T455
Test name
Test status
Simulation time 312641052 ps
CPU time 12.83 seconds
Started Jul 02 09:58:05 AM PDT 24
Finished Jul 02 09:58:24 AM PDT 24
Peak memory 217740 kb
Host smart-03b16f8b-6d5d-49a1-b7d1-c272180da23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680463412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3680463412
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.195171076
Short name T235
Test name
Test status
Simulation time 2820738274 ps
CPU time 14.17 seconds
Started Jul 02 09:58:05 AM PDT 24
Finished Jul 02 09:58:24 AM PDT 24
Peak memory 226120 kb
Host smart-7e8c22fb-518d-49a5-bf3f-edabea2b4035
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195171076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.195171076
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.39920781
Short name T318
Test name
Test status
Simulation time 740533784 ps
CPU time 10.85 seconds
Started Jul 02 09:58:13 AM PDT 24
Finished Jul 02 09:58:28 AM PDT 24
Peak memory 225704 kb
Host smart-26867530-ef61-4e7b-b71d-d46af44663b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39920781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_dige
st.39920781
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3189172280
Short name T397
Test name
Test status
Simulation time 1721091831 ps
CPU time 16.24 seconds
Started Jul 02 09:58:11 AM PDT 24
Finished Jul 02 09:58:33 AM PDT 24
Peak memory 218280 kb
Host smart-578a66eb-379a-4cf9-a0f0-c79dbbb61a1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189172280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
189172280
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.1873590438
Short name T480
Test name
Test status
Simulation time 338840768 ps
CPU time 9.07 seconds
Started Jul 02 09:58:08 AM PDT 24
Finished Jul 02 09:58:24 AM PDT 24
Peak memory 225208 kb
Host smart-fe6c0e2f-87d8-41ac-8eae-023349887958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873590438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.1873590438
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.3114855110
Short name T770
Test name
Test status
Simulation time 19762104 ps
CPU time 1.32 seconds
Started Jul 02 09:58:13 AM PDT 24
Finished Jul 02 09:58:19 AM PDT 24
Peak memory 217436 kb
Host smart-22b69825-1d10-4511-95b4-935f8144cfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114855110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3114855110
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.852493338
Short name T807
Test name
Test status
Simulation time 367447174 ps
CPU time 34.5 seconds
Started Jul 02 09:58:07 AM PDT 24
Finished Jul 02 09:58:48 AM PDT 24
Peak memory 251004 kb
Host smart-4dd1b859-f62b-47c3-a41a-e0bb6be13082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852493338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.852493338
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3804145044
Short name T413
Test name
Test status
Simulation time 648040157 ps
CPU time 7.44 seconds
Started Jul 02 09:58:07 AM PDT 24
Finished Jul 02 09:58:21 AM PDT 24
Peak memory 250600 kb
Host smart-7353f11a-ff0c-483d-b9c8-28d1fa3d4a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804145044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3804145044
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.718646501
Short name T4
Test name
Test status
Simulation time 3626781901 ps
CPU time 81.32 seconds
Started Jul 02 09:58:05 AM PDT 24
Finished Jul 02 09:59:32 AM PDT 24
Peak memory 275212 kb
Host smart-f93aee6b-1a6b-4197-a38c-38e37b88eba6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718646501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.718646501
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.772084711
Short name T142
Test name
Test status
Simulation time 10576312926 ps
CPU time 359.62 seconds
Started Jul 02 09:58:08 AM PDT 24
Finished Jul 02 10:04:14 AM PDT 24
Peak memory 316572 kb
Host smart-ac0b7ba8-fb4d-4787-9b8e-6ed1cebc1658
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=772084711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.772084711
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.4022040236
Short name T219
Test name
Test status
Simulation time 24640487 ps
CPU time 0.94 seconds
Started Jul 02 09:58:06 AM PDT 24
Finished Jul 02 09:58:13 AM PDT 24
Peak memory 212928 kb
Host smart-e6c8803a-06b3-44f9-a43d-c23f4874f1ef
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022040236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.4022040236
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3852264322
Short name T857
Test name
Test status
Simulation time 132526028 ps
CPU time 1.03 seconds
Started Jul 02 09:58:04 AM PDT 24
Finished Jul 02 09:58:10 AM PDT 24
Peak memory 209012 kb
Host smart-c89d5d41-4b87-4715-abeb-7c6f65eb75ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852264322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3852264322
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.1902868149
Short name T76
Test name
Test status
Simulation time 16891231 ps
CPU time 0.83 seconds
Started Jul 02 09:58:05 AM PDT 24
Finished Jul 02 09:58:12 AM PDT 24
Peak memory 208796 kb
Host smart-59fd0b25-34b9-46d5-b018-c2a1dad975ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902868149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1902868149
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.833891070
Short name T396
Test name
Test status
Simulation time 344178843 ps
CPU time 12.27 seconds
Started Jul 02 09:58:05 AM PDT 24
Finished Jul 02 09:58:22 AM PDT 24
Peak memory 218232 kb
Host smart-721d8d8a-50eb-46ab-bc2e-8351a642af6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833891070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.833891070
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3898279799
Short name T679
Test name
Test status
Simulation time 409906216 ps
CPU time 5.62 seconds
Started Jul 02 09:58:07 AM PDT 24
Finished Jul 02 09:58:19 AM PDT 24
Peak memory 217268 kb
Host smart-92ffe5d3-0f28-4bad-87f1-9cf29d43d08a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898279799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3898279799
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.2980457
Short name T334
Test name
Test status
Simulation time 3435742913 ps
CPU time 48.89 seconds
Started Jul 02 09:58:08 AM PDT 24
Finished Jul 02 09:59:03 AM PDT 24
Peak memory 220104 kb
Host smart-774524ce-21b7-4ca8-bbad-f2dc0d0a2743
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc
_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_error
s.2980457
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.1913289066
Short name T746
Test name
Test status
Simulation time 3252663165 ps
CPU time 37.76 seconds
Started Jul 02 09:58:08 AM PDT 24
Finished Jul 02 09:58:52 AM PDT 24
Peak memory 217800 kb
Host smart-705aa21d-dc29-4f25-b2a2-fbe63b10e7e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913289066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.1
913289066
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.155229291
Short name T722
Test name
Test status
Simulation time 6684578644 ps
CPU time 11.25 seconds
Started Jul 02 09:58:08 AM PDT 24
Finished Jul 02 09:58:26 AM PDT 24
Peak memory 223860 kb
Host smart-1d6b8cd0-71e5-42ac-8b38-4ed1b83f4578
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155229291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
prog_failure.155229291
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3803731930
Short name T66
Test name
Test status
Simulation time 1050370266 ps
CPU time 16.08 seconds
Started Jul 02 09:58:14 AM PDT 24
Finished Jul 02 09:58:35 AM PDT 24
Peak memory 217728 kb
Host smart-3f681a29-aea5-4149-9679-70052002a973
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803731930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3803731930
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.3145744290
Short name T528
Test name
Test status
Simulation time 703202172 ps
CPU time 6.62 seconds
Started Jul 02 09:58:10 AM PDT 24
Finished Jul 02 09:58:23 AM PDT 24
Peak memory 217692 kb
Host smart-ae900f37-6e55-4839-9b7e-f50b28eab6e1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145744290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
3145744290
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.972280950
Short name T272
Test name
Test status
Simulation time 4811879932 ps
CPU time 87.81 seconds
Started Jul 02 09:58:11 AM PDT 24
Finished Jul 02 09:59:45 AM PDT 24
Peak memory 281984 kb
Host smart-5ef312ba-a830-40bf-902d-f14166589881
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972280950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_state_failure.972280950
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1325616736
Short name T804
Test name
Test status
Simulation time 2409773225 ps
CPU time 17.59 seconds
Started Jul 02 09:58:01 AM PDT 24
Finished Jul 02 09:58:21 AM PDT 24
Peak memory 250612 kb
Host smart-281592c0-1f88-4895-8024-cbbbf5b4595d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325616736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1325616736
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.925546341
Short name T696
Test name
Test status
Simulation time 21109385 ps
CPU time 1.75 seconds
Started Jul 02 09:58:12 AM PDT 24
Finished Jul 02 09:58:19 AM PDT 24
Peak memory 218112 kb
Host smart-8fe8740c-5f24-45a0-8d07-a54c02e6efc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925546341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.925546341
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.2274532306
Short name T813
Test name
Test status
Simulation time 204225587 ps
CPU time 7.81 seconds
Started Jul 02 09:58:06 AM PDT 24
Finished Jul 02 09:58:20 AM PDT 24
Peak memory 217716 kb
Host smart-ce4bacbc-0a37-4a52-ba7c-dbce641121d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274532306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2274532306
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.294622773
Short name T754
Test name
Test status
Simulation time 876160050 ps
CPU time 13.16 seconds
Started Jul 02 09:58:03 AM PDT 24
Finished Jul 02 09:58:20 AM PDT 24
Peak memory 226060 kb
Host smart-01dbf00a-632a-4237-9692-a185431e742d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294622773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.294622773
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.1043184719
Short name T19
Test name
Test status
Simulation time 242660885 ps
CPU time 10.78 seconds
Started Jul 02 09:58:05 AM PDT 24
Finished Jul 02 09:58:21 AM PDT 24
Peak memory 226020 kb
Host smart-aaa2b9dd-eebd-4724-954e-946d6d5a14a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043184719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.1043184719
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2114932308
Short name T244
Test name
Test status
Simulation time 200130751 ps
CPU time 5.38 seconds
Started Jul 02 09:58:06 AM PDT 24
Finished Jul 02 09:58:17 AM PDT 24
Peak memory 218244 kb
Host smart-2c6f2323-0a2e-47ca-a59a-e38744f7cd10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114932308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
114932308
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.2989218814
Short name T720
Test name
Test status
Simulation time 321881645 ps
CPU time 7.68 seconds
Started Jul 02 09:58:05 AM PDT 24
Finished Jul 02 09:58:17 AM PDT 24
Peak memory 218276 kb
Host smart-f8f9ab30-4d40-432c-b30d-fbf8ed308e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989218814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2989218814
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.3963288398
Short name T719
Test name
Test status
Simulation time 55927222 ps
CPU time 1.41 seconds
Started Jul 02 09:57:57 AM PDT 24
Finished Jul 02 09:58:01 AM PDT 24
Peak memory 213716 kb
Host smart-9823ae9e-fca7-44a4-ba14-522b9f7abbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963288398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.3963288398
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.1560681563
Short name T519
Test name
Test status
Simulation time 230416859 ps
CPU time 25.67 seconds
Started Jul 02 09:58:03 AM PDT 24
Finished Jul 02 09:58:32 AM PDT 24
Peak memory 250968 kb
Host smart-2b35bad1-0c68-4132-848e-39b6324cfd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560681563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1560681563
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.417720836
Short name T242
Test name
Test status
Simulation time 84190166 ps
CPU time 8.55 seconds
Started Jul 02 09:58:06 AM PDT 24
Finished Jul 02 09:58:21 AM PDT 24
Peak memory 251004 kb
Host smart-5e4790e3-c7c9-4ad0-8632-fe9aa2b2370a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417720836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.417720836
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.4292181898
Short name T344
Test name
Test status
Simulation time 17268079122 ps
CPU time 151.77 seconds
Started Jul 02 09:58:09 AM PDT 24
Finished Jul 02 10:00:47 AM PDT 24
Peak memory 300076 kb
Host smart-5ac41bcd-e988-4ac3-bcaf-eade44b5f684
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292181898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.4292181898
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3937695823
Short name T651
Test name
Test status
Simulation time 64744441 ps
CPU time 0.92 seconds
Started Jul 02 09:58:06 AM PDT 24
Finished Jul 02 09:58:13 AM PDT 24
Peak memory 212980 kb
Host smart-4f297312-c69d-4a82-9593-1068bb7ddf5a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937695823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.3937695823
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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