Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

92060172

1

T1

70617

T2

761

T3

1114

auto[1]

1258214

1

T1

297

T4

1881

T5

99

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

92068859

1

T1

70122

T2

761

T3

1114

auto[1]

1249527

1

T1

792

T4

1881

T5

297

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6880435	1			T1	8033		T2	109		T3	101
auto[IdleSt]	20840941	1			T1	7646		T2	16		T3	68
auto[ClkMuxSt]	33074	1			T1	89		T2	1		T3	1
auto[CntIncrSt]	32863	1			T1	89		T2	1		T3	1
auto[CntProgSt]	1981288	1			T1	31502		T2	16		T3	2
auto[TransCheckSt]	25742	1			T1	69		T2	1		T3	1
auto[TokenHashSt]	32364460	1			T1	5015		T2	12		T3	24
auto[FlashRmaSt]	32204	1			T1	39		T4	118		T5	6
auto[TokenCheck0St]	11381	1			T1	17		T4	40		T5	6
auto[TokenCheck1St]	8341	1			T1	9		T4	27		T5	6
auto[TransProgSt]	536779	1			T1	2690		T4	683		T5	561
auto[PostTransSt]	12474076	1			T1	14229		T2	605		T3	916
auto[ScrapSt]	93757	1			T14	3		T22	2718		T32	934
auto[EscalateSt]	6424282	1			T1	1487		T4	4995		T5	877
auto[InvalidSt]	11577060	1			T4	1461		T5	538		T13	37292

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1703	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11577060	1			T4	1461		T5	538		T13	37292
EscalateSt	6424282	1			T1	1487		T4	4995		T5	877
ScrapSt	93757	1			T14	3		T22	2718		T32	934
PostTransSt	12474076	1			T1	14229		T2	605		T3	916
TransProgSt	536779	1			T1	2690		T4	683		T5	561
TokenCheck1St	8341	1			T1	9		T4	27		T5	6
TokenCheck0St	11381	1			T1	17		T4	40		T5	6
FlashRmaSt	32204	1			T1	39		T4	118		T5	6
TokenHashSt	32364460	1			T1	5015		T2	12		T3	24
TransCheckSt	25742	1			T1	69		T2	1		T3	1
CntProgSt	1981288	1			T1	31502		T2	16		T3	2
CntIncrSt	32863	1			T1	89		T2	1		T3	1
ClkMuxSt	33074	1			T1	89		T2	1		T3	1
IdleSt	20840941	1			T1	7646		T2	16		T3	68
ResetSt	6880435	1			T1	8033		T2	109		T3	101
arcs[ResetSt=>IdleSt]	49106	1			T1	90		T2	1		T3	1
arcs[IdleSt=>ScrapSt]	238	1			T14	1		T22	4		T32	1
arcs[IdleSt=>ClkMuxSt]	32907	1			T1	89		T2	1		T3	1
arcs[ClkMuxSt=>CntIncrSt]	32863	1			T1	89		T2	1		T3	1
arcs[CntIncrSt=>PostTransSt]	1669	1			T1	9		T8	7		T13	21
arcs[CntIncrSt=>CntProgSt]	31128	1			T1	80		T2	1		T3	1
arcs[CntProgSt=>PostTransSt]	4348	1			T1	11		T4	19		T8	5
arcs[CntProgSt=>TransCheckSt]	25742	1			T1	69		T2	1		T3	1
arcs[TransCheckSt=>PostTransSt]	3562	1			T1	15		T11	30		T8	7
arcs[TransCheckSt=>TokenHashSt]	22061	1			T1	54		T2	1		T3	1
arcs[TokenHashSt=>PostTransSt]	9949	1			T1	37		T2	1		T3	1
arcs[TokenHashSt=>FlashRmaSt]	11477	1			T1	17		T4	40		T5	6
arcs[FlashRmaSt=>TokenCheck0St]	11381	1			T1	17		T4	40		T5	6
arcs[TokenCheck0St=>PostTransSt]	3013	1			T1	8		T4	13		T11	7
arcs[TokenCheck0St=>TokenCheck1St]	8341	1			T1	9		T4	27		T5	6
arcs[TokenCheck1St=>PostTransSt]	616	1			T1	1		T11	8		T8	1
arcs[TransProgSt=>PostTransSt]	6922	1			T1	8		T4	27		T5	6
arcs[IdleSt=>EscalateSt]	210	1			T40	6		T41	5		T42	4
arcs[ClkMuxSt=>EscalateSt]	44	1			T40	1		T41	2		T42	1
arcs[CntIncrSt=>EscalateSt]	66	1			T43	3		T44	1		T41	2
arcs[CntProgSt=>EscalateSt]	1038	1			T14	5		T40	25		T43	35
arcs[TransCheckSt=>EscalateSt]	119	1			T14	6		T41	7		T42	3
arcs[TokenHashSt=>EscalateSt]	635	1			T14	21		T36	2		T48	3
arcs[FlashRmaSt=>EscalateSt]	96	1			T14	2		T40	2		T43	1
arcs[TokenCheck0St=>EscalateSt]	27	1			T40	1		T43	1		T44	1
arcs[TokenCheck1St=>EscalateSt]	140	1			T14	1		T40	4		T43	3
arcs[TransProgSt=>EscalateSt]	663	1			T14	4		T40	12		T43	23
arcs[PostTransSt=>EscalateSt]	4601	1			T1	11		T4	19		T8	5
arcs[InvalidSt=>EscalateSt]	11913	1			T4	19		T5	4		T13	126

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6880251	1			T1	8033		T2	109		T3	101
auto[0]	auto[IdleSt]	20840795	1			T1	7646		T2	16		T3	68
auto[0]	auto[ClkMuxSt]	33045	1			T1	89		T2	1		T3	1
auto[0]	auto[CntIncrSt]	32821	1			T1	89		T2	1		T3	1
auto[0]	auto[CntProgSt]	1980597	1			T1	31502		T2	16		T3	2
auto[0]	auto[TransCheckSt]	25658	1			T1	69		T2	1		T3	1
auto[0]	auto[TokenHashSt]	32364031	1			T1	5015		T2	12		T3	24
auto[0]	auto[FlashRmaSt]	32147	1			T1	39		T4	118		T5	6
auto[0]	auto[TokenCheck0St]	11363	1			T1	17		T4	40		T5	6
auto[0]	auto[TokenCheck1St]	8255	1			T1	9		T4	27		T5	6
auto[0]	auto[TransProgSt]	536324	1			T1	2690		T4	683		T5	561
auto[0]	auto[PostTransSt]	12471684	1			T1	14226		T2	605		T3	916
auto[0]	auto[ScrapSt]	93716	1			T14	2		T22	2718		T32	934
auto[0]	auto[EscalateSt]	5176641	1			T1	1193		T4	3133		T5	779
auto[0]	auto[InvalidSt]	11571141	1			T4	1456		T5	537		T13	37228
auto[1]	auto[ResetSt]	184	1			T14	2		T40	2		T43	8
auto[1]	auto[IdleSt]	146	1			T40	4		T41	4		T42	3
auto[1]	auto[ClkMuxSt]	29	1			T41	2		T42	1		T176	1
auto[1]	auto[CntIncrSt]	42	1			T43	3		T41	2		T42	2
auto[1]	auto[CntProgSt]	691	1			T14	3		T40	14		T43	20
auto[1]	auto[TransCheckSt]	84	1			T14	5		T41	5		T42	2
auto[1]	auto[TokenHashSt]	429	1			T14	15		T36	1		T48	2
auto[1]	auto[FlashRmaSt]	57	1			T14	1		T40	1		T43	1
auto[1]	auto[TokenCheck0St]	18	1			T40	1		T44	1		T41	1
auto[1]	auto[TokenCheck1St]	86	1			T14	1		T40	2		T43	1
auto[1]	auto[TransProgSt]	455	1			T14	4		T40	7		T43	13
auto[1]	auto[PostTransSt]	2392	1			T1	3		T4	14		T8	2
auto[1]	auto[ScrapSt]	41	1			T14	1		T43	2		T42	1
auto[1]	auto[EscalateSt]	1247641	1			T1	294		T4	1862		T5	98
auto[1]	auto[InvalidSt]	5919	1			T4	5		T5	1		T13	64

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6880272	1			T1	8033		T2	109		T3	101
auto[0]	auto[IdleSt]	20840809	1			T1	7646		T2	16		T3	68
auto[0]	auto[ClkMuxSt]	33042	1			T1	89		T2	1		T3	1
auto[0]	auto[CntIncrSt]	32816	1			T1	89		T2	1		T3	1
auto[0]	auto[CntProgSt]	1980595	1			T1	31502		T2	16		T3	2
auto[0]	auto[TransCheckSt]	25666	1			T1	69		T2	1		T3	1
auto[0]	auto[TokenHashSt]	32364039	1			T1	5015		T2	12		T3	24
auto[0]	auto[FlashRmaSt]	32133	1			T1	39		T4	118		T5	6
auto[0]	auto[TokenCheck0St]	11361	1			T1	17		T4	40		T5	6
auto[0]	auto[TokenCheck1St]	8248	1			T1	9		T4	27		T5	6
auto[0]	auto[TransProgSt]	536336	1			T1	2690		T4	683		T5	561
auto[0]	auto[PostTransSt]	12471788	1			T1	14221		T2	605		T3	916
auto[0]	auto[ScrapSt]	93725	1			T14	3		T22	2718		T32	934
auto[0]	auto[EscalateSt]	5185260	1			T1	703		T4	3133		T5	583
auto[0]	auto[InvalidSt]	11571066	1			T4	1447		T5	535		T13	37230
auto[1]	auto[ResetSt]	163	1			T40	2		T43	9		T44	1
auto[1]	auto[IdleSt]	132	1			T40	6		T41	3		T42	3
auto[1]	auto[ClkMuxSt]	32	1			T40	1		T41	2		T42	1
auto[1]	auto[CntIncrSt]	47	1			T43	1		T44	1		T41	2
auto[1]	auto[CntProgSt]	693	1			T14	4		T40	16		T43	25
auto[1]	auto[TransCheckSt]	76	1			T14	2		T41	2		T42	2
auto[1]	auto[TokenHashSt]	421	1			T14	14		T36	1		T48	1
auto[1]	auto[FlashRmaSt]	71	1			T14	2		T40	1		T44	1
auto[1]	auto[TokenCheck0St]	20	1			T40	1		T43	1		T41	1
auto[1]	auto[TokenCheck1St]	93	1			T40	2		T43	2		T44	1
auto[1]	auto[TransProgSt]	443	1			T14	3		T40	9		T43	16
auto[1]	auto[PostTransSt]	2288	1			T1	8		T4	5		T8	3
auto[1]	auto[ScrapSt]	32	1			T43	2		T44	2		T42	1
auto[1]	auto[EscalateSt]	1239022	1			T1	784		T4	1862		T5	294
auto[1]	auto[InvalidSt]	5994	1			T4	14		T5	3		T13	62