Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.19 97.92 95.66 93.38 100.00 98.52 98.76 96.11


Total test records in report: 992
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T805 /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3204382146 Jul 04 06:44:00 PM PDT 24 Jul 04 06:44:01 PM PDT 24 21117148 ps
T806 /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3829002419 Jul 04 06:39:47 PM PDT 24 Jul 04 06:39:51 PM PDT 24 701303019 ps
T807 /workspace/coverage/default/14.lc_ctrl_state_failure.285476086 Jul 04 06:41:42 PM PDT 24 Jul 04 06:42:02 PM PDT 24 176053945 ps
T808 /workspace/coverage/default/7.lc_ctrl_claim_transition_if.4134616711 Jul 04 06:40:55 PM PDT 24 Jul 04 06:40:56 PM PDT 24 10838362 ps
T809 /workspace/coverage/default/17.lc_ctrl_state_failure.4128356651 Jul 04 06:42:09 PM PDT 24 Jul 04 06:42:33 PM PDT 24 256359318 ps
T810 /workspace/coverage/default/4.lc_ctrl_security_escalation.2576639371 Jul 04 06:40:15 PM PDT 24 Jul 04 06:40:24 PM PDT 24 973209890 ps
T811 /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.488883517 Jul 04 06:39:29 PM PDT 24 Jul 04 06:40:01 PM PDT 24 2363794210 ps
T812 /workspace/coverage/default/6.lc_ctrl_jtag_errors.2123175265 Jul 04 06:40:41 PM PDT 24 Jul 04 06:41:17 PM PDT 24 7708169437 ps
T813 /workspace/coverage/default/0.lc_ctrl_jtag_smoke.973951729 Jul 04 06:39:29 PM PDT 24 Jul 04 06:39:32 PM PDT 24 549125998 ps
T814 /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1781496236 Jul 04 06:41:50 PM PDT 24 Jul 04 06:41:53 PM PDT 24 77352380 ps
T815 /workspace/coverage/default/3.lc_ctrl_sec_token_mux.362533469 Jul 04 06:40:06 PM PDT 24 Jul 04 06:40:16 PM PDT 24 841570894 ps
T816 /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.4097462838 Jul 04 06:42:46 PM PDT 24 Jul 04 06:52:15 PM PDT 24 117223716708 ps
T817 /workspace/coverage/default/10.lc_ctrl_state_post_trans.2745426566 Jul 04 06:41:10 PM PDT 24 Jul 04 06:41:21 PM PDT 24 190054583 ps
T818 /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3176494193 Jul 04 06:41:27 PM PDT 24 Jul 04 06:41:55 PM PDT 24 1728904576 ps
T819 /workspace/coverage/default/37.lc_ctrl_security_escalation.67452839 Jul 04 06:43:59 PM PDT 24 Jul 04 06:44:11 PM PDT 24 635730913 ps
T820 /workspace/coverage/default/1.lc_ctrl_jtag_priority.3816805889 Jul 04 06:39:43 PM PDT 24 Jul 04 06:39:55 PM PDT 24 477396430 ps
T821 /workspace/coverage/default/5.lc_ctrl_prog_failure.852623648 Jul 04 06:40:22 PM PDT 24 Jul 04 06:40:25 PM PDT 24 139727949 ps
T822 /workspace/coverage/default/19.lc_ctrl_jtag_errors.853879682 Jul 04 06:42:25 PM PDT 24 Jul 04 06:43:26 PM PDT 24 2099706771 ps
T823 /workspace/coverage/default/8.lc_ctrl_sec_mubi.221621138 Jul 04 06:41:05 PM PDT 24 Jul 04 06:41:14 PM PDT 24 235377618 ps
T824 /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1351502139 Jul 04 06:43:43 PM PDT 24 Jul 04 06:43:44 PM PDT 24 12469405 ps
T825 /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1538309370 Jul 04 06:39:29 PM PDT 24 Jul 04 06:39:39 PM PDT 24 1180748274 ps
T826 /workspace/coverage/default/25.lc_ctrl_prog_failure.2822723186 Jul 04 06:42:59 PM PDT 24 Jul 04 06:43:01 PM PDT 24 102518986 ps
T827 /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2126841450 Jul 04 06:43:20 PM PDT 24 Jul 04 06:43:41 PM PDT 24 4070352820 ps
T828 /workspace/coverage/default/38.lc_ctrl_sec_mubi.4177366488 Jul 04 06:44:07 PM PDT 24 Jul 04 06:44:22 PM PDT 24 517393539 ps
T829 /workspace/coverage/default/1.lc_ctrl_smoke.3692410973 Jul 04 06:39:38 PM PDT 24 Jul 04 06:39:42 PM PDT 24 563578352 ps
T830 /workspace/coverage/default/45.lc_ctrl_stress_all.251241406 Jul 04 06:44:53 PM PDT 24 Jul 04 06:47:31 PM PDT 24 5509314197 ps
T831 /workspace/coverage/default/10.lc_ctrl_jtag_smoke.539562774 Jul 04 06:41:19 PM PDT 24 Jul 04 06:41:26 PM PDT 24 492805709 ps
T832 /workspace/coverage/default/0.lc_ctrl_sec_mubi.4156545621 Jul 04 06:39:31 PM PDT 24 Jul 04 06:39:43 PM PDT 24 1044025485 ps
T833 /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3948933787 Jul 04 06:42:47 PM PDT 24 Jul 04 06:42:48 PM PDT 24 19714728 ps
T834 /workspace/coverage/default/27.lc_ctrl_state_post_trans.3226023714 Jul 04 06:43:06 PM PDT 24 Jul 04 06:43:14 PM PDT 24 217585254 ps
T79 /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.3303791923 Jul 04 06:40:54 PM PDT 24 Jul 04 06:50:31 PM PDT 24 76551424097 ps
T835 /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1108962106 Jul 04 06:43:06 PM PDT 24 Jul 04 06:43:08 PM PDT 24 100504395 ps
T836 /workspace/coverage/default/24.lc_ctrl_state_failure.4224556602 Jul 04 06:42:47 PM PDT 24 Jul 04 06:43:10 PM PDT 24 405547359 ps
T837 /workspace/coverage/default/38.lc_ctrl_state_post_trans.3126742589 Jul 04 06:44:09 PM PDT 24 Jul 04 06:44:17 PM PDT 24 2161868531 ps
T838 /workspace/coverage/default/19.lc_ctrl_jtag_access.3445301812 Jul 04 06:42:24 PM PDT 24 Jul 04 06:42:28 PM PDT 24 260130416 ps
T839 /workspace/coverage/default/5.lc_ctrl_state_post_trans.150202522 Jul 04 06:40:23 PM PDT 24 Jul 04 06:40:31 PM PDT 24 823524706 ps
T840 /workspace/coverage/default/24.lc_ctrl_sec_token_mux.849970422 Jul 04 06:42:59 PM PDT 24 Jul 04 06:43:13 PM PDT 24 1625282757 ps
T841 /workspace/coverage/default/39.lc_ctrl_security_escalation.2290348271 Jul 04 06:44:23 PM PDT 24 Jul 04 06:44:32 PM PDT 24 403919794 ps
T842 /workspace/coverage/default/48.lc_ctrl_smoke.1503720274 Jul 04 06:45:10 PM PDT 24 Jul 04 06:45:12 PM PDT 24 31197289 ps
T843 /workspace/coverage/default/47.lc_ctrl_stress_all.300994016 Jul 04 06:45:00 PM PDT 24 Jul 04 06:47:03 PM PDT 24 4245885148 ps
T844 /workspace/coverage/default/6.lc_ctrl_alert_test.863532925 Jul 04 06:40:40 PM PDT 24 Jul 04 06:40:42 PM PDT 24 26970669 ps
T845 /workspace/coverage/default/0.lc_ctrl_smoke.3617779275 Jul 04 06:39:31 PM PDT 24 Jul 04 06:39:34 PM PDT 24 155592537 ps
T846 /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2007466680 Jul 04 06:41:03 PM PDT 24 Jul 04 06:41:04 PM PDT 24 14019333 ps
T847 /workspace/coverage/default/15.lc_ctrl_sec_mubi.1945784115 Jul 04 06:41:51 PM PDT 24 Jul 04 06:42:04 PM PDT 24 459287565 ps
T848 /workspace/coverage/default/46.lc_ctrl_jtag_access.1214200560 Jul 04 06:44:55 PM PDT 24 Jul 04 06:45:01 PM PDT 24 1550529875 ps
T849 /workspace/coverage/default/29.lc_ctrl_sec_token_mux.378511029 Jul 04 06:43:21 PM PDT 24 Jul 04 06:43:40 PM PDT 24 2754503712 ps
T850 /workspace/coverage/default/21.lc_ctrl_stress_all.1778313133 Jul 04 06:42:39 PM PDT 24 Jul 04 06:43:31 PM PDT 24 4111887924 ps
T851 /workspace/coverage/default/7.lc_ctrl_security_escalation.2852556436 Jul 04 06:40:53 PM PDT 24 Jul 04 06:41:04 PM PDT 24 1417712969 ps
T852 /workspace/coverage/default/8.lc_ctrl_state_post_trans.2656968281 Jul 04 06:41:05 PM PDT 24 Jul 04 06:41:12 PM PDT 24 80347934 ps
T853 /workspace/coverage/default/9.lc_ctrl_stress_all.3236779339 Jul 04 06:41:10 PM PDT 24 Jul 04 06:46:45 PM PDT 24 15414062223 ps
T854 /workspace/coverage/default/20.lc_ctrl_prog_failure.2637097824 Jul 04 06:42:30 PM PDT 24 Jul 04 06:42:33 PM PDT 24 57271577 ps
T855 /workspace/coverage/default/15.lc_ctrl_sec_token_mux.2884470339 Jul 04 06:41:58 PM PDT 24 Jul 04 06:42:09 PM PDT 24 351588012 ps
T856 /workspace/coverage/default/38.lc_ctrl_prog_failure.2763217561 Jul 04 06:44:06 PM PDT 24 Jul 04 06:44:08 PM PDT 24 80132531 ps
T857 /workspace/coverage/default/35.lc_ctrl_sec_mubi.607149285 Jul 04 06:43:51 PM PDT 24 Jul 04 06:44:02 PM PDT 24 347383420 ps
T858 /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2548802836 Jul 04 06:41:10 PM PDT 24 Jul 04 06:41:19 PM PDT 24 1985764990 ps
T859 /workspace/coverage/default/20.lc_ctrl_smoke.828078116 Jul 04 06:42:24 PM PDT 24 Jul 04 06:42:28 PM PDT 24 67808064 ps
T860 /workspace/coverage/default/8.lc_ctrl_smoke.151167324 Jul 04 06:41:06 PM PDT 24 Jul 04 06:41:11 PM PDT 24 332408981 ps
T109 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3023392423 Jul 04 06:36:35 PM PDT 24 Jul 04 06:36:38 PM PDT 24 207511121 ps
T118 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.476712607 Jul 04 06:37:07 PM PDT 24 Jul 04 06:37:08 PM PDT 24 36548069 ps
T110 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.441369961 Jul 04 06:36:53 PM PDT 24 Jul 04 06:36:56 PM PDT 24 122484830 ps
T111 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1145802658 Jul 04 06:37:03 PM PDT 24 Jul 04 06:37:06 PM PDT 24 72202745 ps
T119 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.362222225 Jul 04 06:36:39 PM PDT 24 Jul 04 06:36:42 PM PDT 24 73031869 ps
T113 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.4085698205 Jul 04 06:37:08 PM PDT 24 Jul 04 06:37:12 PM PDT 24 605442225 ps
T116 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2173267746 Jul 04 06:36:13 PM PDT 24 Jul 04 06:36:15 PM PDT 24 81822037 ps
T136 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2097528379 Jul 04 06:36:40 PM PDT 24 Jul 04 06:36:41 PM PDT 24 17395966 ps
T115 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2861079589 Jul 04 06:36:54 PM PDT 24 Jul 04 06:36:57 PM PDT 24 176425919 ps
T215 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4093194843 Jul 04 06:35:44 PM PDT 24 Jul 04 06:35:53 PM PDT 24 1488460437 ps
T114 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2192637646 Jul 04 06:37:09 PM PDT 24 Jul 04 06:37:13 PM PDT 24 194994958 ps
T125 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.211024401 Jul 04 06:37:17 PM PDT 24 Jul 04 06:37:19 PM PDT 24 150009433 ps
T165 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.169150317 Jul 04 06:36:20 PM PDT 24 Jul 04 06:36:22 PM PDT 24 22359806 ps
T861 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2491182347 Jul 04 06:37:20 PM PDT 24 Jul 04 06:37:23 PM PDT 24 1397229906 ps
T122 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1671049356 Jul 04 06:36:12 PM PDT 24 Jul 04 06:36:17 PM PDT 24 581338137 ps
T184 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2724757914 Jul 04 06:37:06 PM PDT 24 Jul 04 06:37:07 PM PDT 24 46450214 ps
T150 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3923273524 Jul 04 06:35:39 PM PDT 24 Jul 04 06:35:40 PM PDT 24 23347450 ps
T124 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1521755306 Jul 04 06:36:26 PM PDT 24 Jul 04 06:36:29 PM PDT 24 296569784 ps
T862 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3337018950 Jul 04 06:36:38 PM PDT 24 Jul 04 06:36:40 PM PDT 24 1173675103 ps
T151 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3477219492 Jul 04 06:35:58 PM PDT 24 Jul 04 06:36:00 PM PDT 24 63935597 ps
T137 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3815246516 Jul 04 06:35:05 PM PDT 24 Jul 04 06:35:07 PM PDT 24 306643175 ps
T863 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1241506710 Jul 04 06:36:33 PM PDT 24 Jul 04 06:36:34 PM PDT 24 29942888 ps
T208 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2915300888 Jul 04 06:37:01 PM PDT 24 Jul 04 06:37:03 PM PDT 24 43799634 ps
T864 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1113759558 Jul 04 06:37:14 PM PDT 24 Jul 04 06:37:15 PM PDT 24 14047290 ps
T865 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3486393072 Jul 04 06:36:25 PM PDT 24 Jul 04 06:36:26 PM PDT 24 58339550 ps
T866 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1376345184 Jul 04 06:36:13 PM PDT 24 Jul 04 06:36:19 PM PDT 24 193466920 ps
T867 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.44886811 Jul 04 06:36:28 PM PDT 24 Jul 04 06:36:30 PM PDT 24 410940869 ps
T209 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.904198378 Jul 04 06:36:19 PM PDT 24 Jul 04 06:36:20 PM PDT 24 82597039 ps
T868 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3600344068 Jul 04 06:35:18 PM PDT 24 Jul 04 06:35:20 PM PDT 24 231411892 ps
T869 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1556231034 Jul 04 06:36:34 PM PDT 24 Jul 04 06:36:44 PM PDT 24 2720974176 ps
T128 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.713265140 Jul 04 06:37:01 PM PDT 24 Jul 04 06:37:03 PM PDT 24 63961940 ps
T870 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1494394246 Jul 04 06:35:40 PM PDT 24 Jul 04 06:35:42 PM PDT 24 42490083 ps
T152 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.415909757 Jul 04 06:35:46 PM PDT 24 Jul 04 06:35:48 PM PDT 24 46699864 ps
T153 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.342224921 Jul 04 06:35:45 PM PDT 24 Jul 04 06:35:47 PM PDT 24 592067299 ps
T871 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1710746536 Jul 04 06:36:32 PM PDT 24 Jul 04 06:36:36 PM PDT 24 116492106 ps
T117 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1174443411 Jul 04 06:36:39 PM PDT 24 Jul 04 06:36:43 PM PDT 24 184638423 ps
T872 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3265957102 Jul 04 06:35:52 PM PDT 24 Jul 04 06:35:54 PM PDT 24 123972343 ps
T210 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2581148832 Jul 04 06:37:07 PM PDT 24 Jul 04 06:37:08 PM PDT 24 27548807 ps
T873 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3882315545 Jul 04 06:36:19 PM PDT 24 Jul 04 06:36:26 PM PDT 24 1110393580 ps
T126 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2131393823 Jul 04 06:37:00 PM PDT 24 Jul 04 06:37:03 PM PDT 24 61646543 ps
T874 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.654344497 Jul 04 06:35:57 PM PDT 24 Jul 04 06:35:59 PM PDT 24 27825926 ps
T875 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2566175578 Jul 04 06:36:20 PM PDT 24 Jul 04 06:36:23 PM PDT 24 246373618 ps
T197 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.4100091723 Jul 04 06:35:10 PM PDT 24 Jul 04 06:35:12 PM PDT 24 19714564 ps
T876 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2281856861 Jul 04 06:36:18 PM PDT 24 Jul 04 06:36:20 PM PDT 24 28371632 ps
T877 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1334355907 Jul 04 06:36:45 PM PDT 24 Jul 04 06:36:47 PM PDT 24 200137441 ps
T878 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2505721304 Jul 04 06:36:25 PM PDT 24 Jul 04 06:36:26 PM PDT 24 20218326 ps
T879 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1346391074 Jul 04 06:35:05 PM PDT 24 Jul 04 06:35:11 PM PDT 24 2035915953 ps
T131 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1949516082 Jul 04 06:37:14 PM PDT 24 Jul 04 06:37:16 PM PDT 24 431761738 ps
T880 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1631743176 Jul 04 06:36:33 PM PDT 24 Jul 04 06:36:35 PM PDT 24 537261969 ps
T129 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1117061854 Jul 04 06:36:59 PM PDT 24 Jul 04 06:37:02 PM PDT 24 259773832 ps
T881 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1871890956 Jul 04 06:36:00 PM PDT 24 Jul 04 06:36:07 PM PDT 24 1449516359 ps
T882 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2870836537 Jul 04 06:35:16 PM PDT 24 Jul 04 06:35:18 PM PDT 24 119845430 ps
T883 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3369348821 Jul 04 06:36:43 PM PDT 24 Jul 04 06:36:45 PM PDT 24 156512803 ps
T123 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1500139521 Jul 04 06:37:13 PM PDT 24 Jul 04 06:37:17 PM PDT 24 99392208 ps
T884 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.4075772765 Jul 04 06:35:24 PM PDT 24 Jul 04 06:35:49 PM PDT 24 5946621605 ps
T885 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.336336564 Jul 04 06:35:06 PM PDT 24 Jul 04 06:35:12 PM PDT 24 281110209 ps
T886 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.357324046 Jul 04 06:36:27 PM PDT 24 Jul 04 06:36:29 PM PDT 24 429540567 ps
T887 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3548548448 Jul 04 06:37:08 PM PDT 24 Jul 04 06:37:10 PM PDT 24 59771675 ps
T211 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.481167915 Jul 04 06:36:40 PM PDT 24 Jul 04 06:36:41 PM PDT 24 19245759 ps
T212 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3559215890 Jul 04 06:36:40 PM PDT 24 Jul 04 06:36:41 PM PDT 24 15218612 ps
T198 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1162409459 Jul 04 06:36:13 PM PDT 24 Jul 04 06:36:14 PM PDT 24 69270585 ps
T213 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3562666885 Jul 04 06:35:58 PM PDT 24 Jul 04 06:35:59 PM PDT 24 198854176 ps
T888 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.4026380600 Jul 04 06:36:47 PM PDT 24 Jul 04 06:36:51 PM PDT 24 713343364 ps
T889 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2290350300 Jul 04 06:35:53 PM PDT 24 Jul 04 06:35:54 PM PDT 24 96843275 ps
T199 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.781839609 Jul 04 06:37:07 PM PDT 24 Jul 04 06:37:08 PM PDT 24 13099008 ps
T200 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2910047915 Jul 04 06:37:00 PM PDT 24 Jul 04 06:37:02 PM PDT 24 18356703 ps
T890 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.60135011 Jul 04 06:35:18 PM PDT 24 Jul 04 06:35:31 PM PDT 24 1305545402 ps
T891 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3404999082 Jul 04 06:35:58 PM PDT 24 Jul 04 06:36:08 PM PDT 24 2430317065 ps
T892 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2328367141 Jul 04 06:36:38 PM PDT 24 Jul 04 06:36:46 PM PDT 24 301878861 ps
T893 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1851663904 Jul 04 06:35:46 PM PDT 24 Jul 04 06:35:48 PM PDT 24 66278601 ps
T894 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2916743839 Jul 04 06:36:19 PM PDT 24 Jul 04 06:36:22 PM PDT 24 326825108 ps
T201 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.510561090 Jul 04 06:35:52 PM PDT 24 Jul 04 06:35:53 PM PDT 24 26666225 ps
T895 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2049367348 Jul 04 06:36:59 PM PDT 24 Jul 04 06:37:00 PM PDT 24 124764375 ps
T214 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1791068542 Jul 04 06:37:07 PM PDT 24 Jul 04 06:37:09 PM PDT 24 26544420 ps
T896 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.483664896 Jul 04 06:37:14 PM PDT 24 Jul 04 06:37:17 PM PDT 24 92322823 ps
T897 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.4009516958 Jul 04 06:37:17 PM PDT 24 Jul 04 06:37:18 PM PDT 24 50834317 ps
T898 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2331653457 Jul 04 06:37:15 PM PDT 24 Jul 04 06:37:16 PM PDT 24 22405963 ps
T899 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3322242925 Jul 04 06:35:17 PM PDT 24 Jul 04 06:35:19 PM PDT 24 241639744 ps
T900 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2727136975 Jul 04 06:37:03 PM PDT 24 Jul 04 06:37:06 PM PDT 24 153049254 ps
T901 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3299417067 Jul 04 06:36:26 PM PDT 24 Jul 04 06:36:27 PM PDT 24 135808416 ps
T902 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.114561274 Jul 04 06:36:32 PM PDT 24 Jul 04 06:36:34 PM PDT 24 710513547 ps
T903 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2773816931 Jul 04 06:37:07 PM PDT 24 Jul 04 06:37:08 PM PDT 24 39623822 ps
T904 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3154241967 Jul 04 06:35:51 PM PDT 24 Jul 04 06:35:55 PM PDT 24 148221180 ps
T905 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3939736596 Jul 04 06:35:07 PM PDT 24 Jul 04 06:35:08 PM PDT 24 30741653 ps
T906 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2243301254 Jul 04 06:36:24 PM PDT 24 Jul 04 06:36:25 PM PDT 24 48677946 ps
T907 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2219761720 Jul 04 06:35:57 PM PDT 24 Jul 04 06:35:58 PM PDT 24 34916042 ps
T202 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2161385234 Jul 04 06:35:38 PM PDT 24 Jul 04 06:35:39 PM PDT 24 51534914 ps
T908 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.516364510 Jul 04 06:35:46 PM PDT 24 Jul 04 06:35:48 PM PDT 24 194381861 ps
T909 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3201565358 Jul 04 06:37:06 PM PDT 24 Jul 04 06:37:08 PM PDT 24 91605798 ps
T910 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3633168926 Jul 04 06:37:07 PM PDT 24 Jul 04 06:37:08 PM PDT 24 70671705 ps
T911 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2266679457 Jul 04 06:36:45 PM PDT 24 Jul 04 06:37:19 PM PDT 24 1646514604 ps
T912 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1250551909 Jul 04 06:35:45 PM PDT 24 Jul 04 06:35:46 PM PDT 24 42979195 ps
T913 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.616661155 Jul 04 06:36:41 PM PDT 24 Jul 04 06:36:50 PM PDT 24 1515285324 ps
T914 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1399586864 Jul 04 06:35:44 PM PDT 24 Jul 04 06:35:45 PM PDT 24 196756474 ps
T915 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1563587199 Jul 04 06:37:20 PM PDT 24 Jul 04 06:37:21 PM PDT 24 348355080 ps
T916 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.879785824 Jul 04 06:35:11 PM PDT 24 Jul 04 06:35:14 PM PDT 24 352591920 ps
T917 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3214966710 Jul 04 06:35:03 PM PDT 24 Jul 04 06:35:05 PM PDT 24 69741745 ps
T203 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2592619314 Jul 04 06:36:32 PM PDT 24 Jul 04 06:36:33 PM PDT 24 11845065 ps
T918 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1003077018 Jul 04 06:36:39 PM PDT 24 Jul 04 06:36:41 PM PDT 24 100679395 ps
T919 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3852516930 Jul 04 06:36:56 PM PDT 24 Jul 04 06:36:58 PM PDT 24 297509356 ps
T920 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.136263671 Jul 04 06:35:46 PM PDT 24 Jul 04 06:35:59 PM PDT 24 2040540990 ps
T921 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1187877949 Jul 04 06:36:25 PM PDT 24 Jul 04 06:36:29 PM PDT 24 874164328 ps
T922 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2535571483 Jul 04 06:37:02 PM PDT 24 Jul 04 06:37:06 PM PDT 24 148455757 ps
T923 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2559968441 Jul 04 06:36:25 PM PDT 24 Jul 04 06:36:28 PM PDT 24 105035047 ps
T924 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2166802965 Jul 04 06:35:52 PM PDT 24 Jul 04 06:35:55 PM PDT 24 138358520 ps
T925 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3032921584 Jul 04 06:35:18 PM PDT 24 Jul 04 06:35:19 PM PDT 24 15079768 ps
T926 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1635257730 Jul 04 06:37:23 PM PDT 24 Jul 04 06:37:24 PM PDT 24 60123568 ps
T927 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3128644622 Jul 04 06:35:11 PM PDT 24 Jul 04 06:35:12 PM PDT 24 23724302 ps
T928 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2812572230 Jul 04 06:36:19 PM PDT 24 Jul 04 06:36:25 PM PDT 24 162843692 ps
T929 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.766950675 Jul 04 06:36:40 PM PDT 24 Jul 04 06:36:42 PM PDT 24 68507797 ps
T930 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.96487030 Jul 04 06:36:42 PM PDT 24 Jul 04 06:36:43 PM PDT 24 58074339 ps
T135 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2208049011 Jul 04 06:36:33 PM PDT 24 Jul 04 06:36:35 PM PDT 24 124447730 ps
T204 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3433034402 Jul 04 06:35:53 PM PDT 24 Jul 04 06:35:54 PM PDT 24 83483958 ps
T931 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.579195671 Jul 04 06:37:01 PM PDT 24 Jul 04 06:37:04 PM PDT 24 228235380 ps
T932 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2055521204 Jul 04 06:36:59 PM PDT 24 Jul 04 06:37:01 PM PDT 24 51493271 ps
T933 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1099976394 Jul 04 06:36:13 PM PDT 24 Jul 04 06:36:14 PM PDT 24 25198484 ps
T934 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2527927010 Jul 04 06:37:14 PM PDT 24 Jul 04 06:37:16 PM PDT 24 26633944 ps
T935 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1862732005 Jul 04 06:37:09 PM PDT 24 Jul 04 06:37:10 PM PDT 24 16552306 ps
T936 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1173636332 Jul 04 06:36:54 PM PDT 24 Jul 04 06:36:56 PM PDT 24 81229047 ps
T937 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3058284855 Jul 04 06:37:25 PM PDT 24 Jul 04 06:37:27 PM PDT 24 311762936 ps
T938 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2753554302 Jul 04 06:36:20 PM PDT 24 Jul 04 06:36:21 PM PDT 24 48318632 ps
T939 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1159058170 Jul 04 06:37:01 PM PDT 24 Jul 04 06:37:03 PM PDT 24 24972981 ps
T940 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3028508353 Jul 04 06:35:05 PM PDT 24 Jul 04 06:35:08 PM PDT 24 260320056 ps
T941 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3537081783 Jul 04 06:36:12 PM PDT 24 Jul 04 06:36:18 PM PDT 24 533979196 ps
T205 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2729761386 Jul 04 06:35:58 PM PDT 24 Jul 04 06:35:59 PM PDT 24 48781790 ps
T130 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.4047729810 Jul 04 06:37:08 PM PDT 24 Jul 04 06:37:12 PM PDT 24 114204327 ps
T942 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2997669980 Jul 04 06:35:23 PM PDT 24 Jul 04 06:35:26 PM PDT 24 93187892 ps
T943 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.57716039 Jul 04 06:35:53 PM PDT 24 Jul 04 06:35:54 PM PDT 24 46593457 ps
T206 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2842674699 Jul 04 06:35:18 PM PDT 24 Jul 04 06:35:19 PM PDT 24 90161940 ps
T944 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.565637303 Jul 04 06:37:06 PM PDT 24 Jul 04 06:37:08 PM PDT 24 37795581 ps
T945 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1167750973 Jul 04 06:37:08 PM PDT 24 Jul 04 06:37:10 PM PDT 24 141767966 ps
T946 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1817009312 Jul 04 06:35:52 PM PDT 24 Jul 04 06:35:54 PM PDT 24 38875029 ps
T947 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.659218756 Jul 04 06:35:04 PM PDT 24 Jul 04 06:35:31 PM PDT 24 6600971608 ps
T948 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2386798816 Jul 04 06:37:20 PM PDT 24 Jul 04 06:37:37 PM PDT 24 2880419866 ps
T949 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3143384594 Jul 04 06:35:46 PM PDT 24 Jul 04 06:35:48 PM PDT 24 55077586 ps
T127 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1013927231 Jul 04 06:36:25 PM PDT 24 Jul 04 06:36:29 PM PDT 24 188545694 ps
T950 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1958200577 Jul 04 06:37:02 PM PDT 24 Jul 04 06:37:03 PM PDT 24 307568069 ps
T132 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.4512349 Jul 04 06:35:45 PM PDT 24 Jul 04 06:35:49 PM PDT 24 107321801 ps
T951 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.675047188 Jul 04 06:36:54 PM PDT 24 Jul 04 06:36:55 PM PDT 24 35129731 ps
T952 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1894636212 Jul 04 06:36:25 PM PDT 24 Jul 04 06:37:18 PM PDT 24 2469596523 ps
T953 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3991737045 Jul 04 06:37:00 PM PDT 24 Jul 04 06:37:03 PM PDT 24 63191232 ps
T954 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.4066988572 Jul 04 06:36:39 PM PDT 24 Jul 04 06:36:44 PM PDT 24 371777767 ps
T955 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3249053463 Jul 04 06:36:54 PM PDT 24 Jul 04 06:36:57 PM PDT 24 122170239 ps
T956 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1491306482 Jul 04 06:36:35 PM PDT 24 Jul 04 06:36:36 PM PDT 24 211178541 ps
T957 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3997416893 Jul 04 06:37:00 PM PDT 24 Jul 04 06:37:01 PM PDT 24 31172782 ps
T958 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1606016328 Jul 04 06:36:32 PM PDT 24 Jul 04 06:36:33 PM PDT 24 104479203 ps
T133 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.727904627 Jul 04 06:35:39 PM PDT 24 Jul 04 06:35:42 PM PDT 24 224870350 ps
T959 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.663226816 Jul 04 06:36:34 PM PDT 24 Jul 04 06:36:39 PM PDT 24 926219847 ps
T134 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.96113723 Jul 04 06:37:17 PM PDT 24 Jul 04 06:37:20 PM PDT 24 162116965 ps
T960 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.782664841 Jul 04 06:37:01 PM PDT 24 Jul 04 06:37:02 PM PDT 24 28673320 ps
T961 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.527295832 Jul 04 06:37:14 PM PDT 24 Jul 04 06:37:16 PM PDT 24 88132554 ps
T120 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.34112852 Jul 04 06:36:42 PM PDT 24 Jul 04 06:36:45 PM PDT 24 174148683 ps
T962 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2227438604 Jul 04 06:35:23 PM PDT 24 Jul 04 06:35:25 PM PDT 24 90490729 ps
T963 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3106562942 Jul 04 06:35:58 PM PDT 24 Jul 04 06:35:59 PM PDT 24 63392330 ps
T964 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1243778123 Jul 04 06:37:01 PM PDT 24 Jul 04 06:37:02 PM PDT 24 124215749 ps
T965 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1827460024 Jul 04 06:36:12 PM PDT 24 Jul 04 06:36:13 PM PDT 24 30508780 ps
T966 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1275191230 Jul 04 06:35:40 PM PDT 24 Jul 04 06:35:44 PM PDT 24 299021630 ps
T121 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.873850813 Jul 04 06:35:10 PM PDT 24 Jul 04 06:35:13 PM PDT 24 159203344 ps
T967 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2869650180 Jul 04 06:35:59 PM PDT 24 Jul 04 06:36:04 PM PDT 24 311648607 ps
T968 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1296784602 Jul 04 06:37:06 PM PDT 24 Jul 04 06:37:07 PM PDT 24 47522716 ps
T969 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.4218619806 Jul 04 06:35:39 PM PDT 24 Jul 04 06:35:42 PM PDT 24 97390469 ps
T970 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2337373216 Jul 04 06:36:45 PM PDT 24 Jul 04 06:36:46 PM PDT 24 28665909 ps
T971 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2961224499 Jul 04 06:36:19 PM PDT 24 Jul 04 06:36:21 PM PDT 24 65679431 ps
T972 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.556582626 Jul 04 06:35:12 PM PDT 24 Jul 04 06:35:13 PM PDT 24 50974080 ps
T973 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2941330984 Jul 04 06:37:17 PM PDT 24 Jul 04 06:37:18 PM PDT 24 21600419 ps
T974 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2283805599 Jul 04 06:36:53 PM PDT 24 Jul 04 06:36:55 PM PDT 24 33412887 ps
T975 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.830072578 Jul 04 06:37:20 PM PDT 24 Jul 04 06:37:22 PM PDT 24 331629555 ps
T976 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2315594137 Jul 04 06:35:58 PM PDT 24 Jul 04 06:36:00 PM PDT 24 138854032 ps
T977 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1612349039 Jul 04 06:36:24 PM PDT 24 Jul 04 06:36:29 PM PDT 24 628050766 ps
T978 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2043590359 Jul 04 06:36:53 PM PDT 24 Jul 04 06:36:54 PM PDT 24 36284215 ps
T979 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1785192220 Jul 04 06:36:26 PM PDT 24 Jul 04 06:36:27 PM PDT 24 33347506 ps
T980 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2757195661 Jul 04 06:36:13 PM PDT 24 Jul 04 06:36:16 PM PDT 24 187274159 ps
T981 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3818314244 Jul 04 06:37:15 PM PDT 24 Jul 04 06:37:18 PM PDT 24 47242303 ps
T982 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1660526794 Jul 04 06:36:33 PM PDT 24 Jul 04 06:36:34 PM PDT 24 36401319 ps
T983 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3720142428 Jul 04 06:37:09 PM PDT 24 Jul 04 06:37:11 PM PDT 24 105217757 ps
T984 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3917722512 Jul 04 06:36:19 PM PDT 24 Jul 04 06:36:28 PM PDT 24 3153850369 ps
T985 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2104076274 Jul 04 06:35:58 PM PDT 24 Jul 04 06:35:59 PM PDT 24 22913455 ps
T986 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3560576789 Jul 04 06:35:44 PM PDT 24 Jul 04 06:35:46 PM PDT 24 29304208 ps
T987 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2973314461 Jul 04 06:36:39 PM PDT 24 Jul 04 06:36:40 PM PDT 24 24878190 ps
T988 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3757386855 Jul 04 06:35:58 PM PDT 24 Jul 04 06:36:03 PM PDT 24 177891659 ps
T207 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3028847812 Jul 04 06:37:15 PM PDT 24 Jul 04 06:37:16 PM PDT 24 21130201 ps
T989 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.518659041 Jul 04 06:36:34 PM PDT 24 Jul 04 06:36:36 PM PDT 24 30692859 ps
T990 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3940614765 Jul 04 06:36:24 PM PDT 24 Jul 04 06:36:25 PM PDT 24 20774112 ps
T991 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.745659954 Jul 04 06:36:40 PM PDT 24 Jul 04 06:36:42 PM PDT 24 99731329 ps
T992 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1264815005 Jul 04 06:37:08 PM PDT 24 Jul 04 06:37:11 PM PDT 24 43247324 ps

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.2340334074
Short name T4
Test name
Test status
Simulation time 711732835 ps
CPU time 14.34 seconds
Started Jul 04 06:40:42 PM PDT 24
Finished Jul 04 06:40:56 PM PDT 24
Peak memory 226036 kb
Host smart-2be40834-8401-4919-8c14-8ae5708771a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340334074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.2340334074
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.2068223065
Short name T13
Test name
Test status
Simulation time 2918167138 ps
CPU time 89.7 seconds
Started Jul 04 06:43:52 PM PDT 24
Finished Jul 04 06:45:23 PM PDT 24
Peak memory 268708 kb
Host smart-18dc2f20-eaf7-49b8-b503-3b4717f182e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068223065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.2068223065
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.145492157
Short name T14
Test name
Test status
Simulation time 753224143 ps
CPU time 7.71 seconds
Started Jul 04 06:41:23 PM PDT 24
Finished Jul 04 06:41:31 PM PDT 24
Peak memory 218292 kb
Host smart-f513a25e-0d41-4ec6-b81b-0f053351f8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145492157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.145492157
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.2046084594
Short name T36
Test name
Test status
Simulation time 64945071041 ps
CPU time 837.01 seconds
Started Jul 04 06:44:48 PM PDT 24
Finished Jul 04 06:58:45 PM PDT 24
Peak memory 496904 kb
Host smart-80d699d9-6a1d-4e38-8142-7d6fc84595cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2046084594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.2046084594
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.362472920
Short name T42
Test name
Test status
Simulation time 321104871 ps
CPU time 8.51 seconds
Started Jul 04 06:40:23 PM PDT 24
Finished Jul 04 06:40:32 PM PDT 24
Peak memory 226044 kb
Host smart-b0b8faa7-293d-4d6b-b995-4820408baa18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362472920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.362472920
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2861079589
Short name T115
Test name
Test status
Simulation time 176425919 ps
CPU time 2.84 seconds
Started Jul 04 06:36:54 PM PDT 24
Finished Jul 04 06:36:57 PM PDT 24
Peak memory 223608 kb
Host smart-66d5e221-e207-4018-ab6c-5feb42d357d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286107
9589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2861079589
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2287424812
Short name T46
Test name
Test status
Simulation time 213656723 ps
CPU time 37.69 seconds
Started Jul 04 06:39:36 PM PDT 24
Finished Jul 04 06:40:14 PM PDT 24
Peak memory 284472 kb
Host smart-be21dfe3-c7cf-4060-932b-103ddb41ce6b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287424812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2287424812
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1292245035
Short name T11
Test name
Test status
Simulation time 701544577 ps
CPU time 7.03 seconds
Started Jul 04 06:43:42 PM PDT 24
Finished Jul 04 06:43:49 PM PDT 24
Peak memory 218172 kb
Host smart-f4b6cac7-4bd9-4414-a225-cbc8b0c0e8c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292245035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1292245035
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3023392423
Short name T109
Test name
Test status
Simulation time 207511121 ps
CPU time 2.99 seconds
Started Jul 04 06:36:35 PM PDT 24
Finished Jul 04 06:36:38 PM PDT 24
Peak memory 213332 kb
Host smart-2d14f386-6755-4956-9317-08e6abaad5d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023392423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.3023392423
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.3089873717
Short name T107
Test name
Test status
Simulation time 509124363843 ps
CPU time 1636.38 seconds
Started Jul 04 06:44:26 PM PDT 24
Finished Jul 04 07:11:43 PM PDT 24
Peak memory 405396 kb
Host smart-e96956ab-c8fe-483c-aba1-b9ee2a53adbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3089873717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.3089873717
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.2301943143
Short name T163
Test name
Test status
Simulation time 291124654 ps
CPU time 7.88 seconds
Started Jul 04 06:41:13 PM PDT 24
Finished Jul 04 06:41:21 PM PDT 24
Peak memory 224472 kb
Host smart-4dd7c7c4-57ab-483b-8ef2-282237740e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301943143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.2301943143
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.588763599
Short name T6
Test name
Test status
Simulation time 1023002901 ps
CPU time 23.1 seconds
Started Jul 04 06:43:13 PM PDT 24
Finished Jul 04 06:43:37 PM PDT 24
Peak memory 217440 kb
Host smart-00b8ed6f-233d-4948-a2dd-d9f0962a01db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588763599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.588763599
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.476712607
Short name T118
Test name
Test status
Simulation time 36548069 ps
CPU time 1.08 seconds
Started Jul 04 06:37:07 PM PDT 24
Finished Jul 04 06:37:08 PM PDT 24
Peak memory 209160 kb
Host smart-fe0c0354-eab5-460a-a147-100fb4de391a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476712607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.476712607
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1621266671
Short name T24
Test name
Test status
Simulation time 296823240 ps
CPU time 1.3 seconds
Started Jul 04 06:44:48 PM PDT 24
Finished Jul 04 06:44:50 PM PDT 24
Peak memory 208992 kb
Host smart-a532fb17-de74-4bf3-a5e9-961649dd8466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621266671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1621266671
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1013927231
Short name T127
Test name
Test status
Simulation time 188545694 ps
CPU time 4.08 seconds
Started Jul 04 06:36:25 PM PDT 24
Finished Jul 04 06:36:29 PM PDT 24
Peak memory 217552 kb
Host smart-242f0df7-ce94-40f5-94c1-01bf1e9e8cdc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013927231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1013927231
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.96113723
Short name T134
Test name
Test status
Simulation time 162116965 ps
CPU time 3.5 seconds
Started Jul 04 06:37:17 PM PDT 24
Finished Jul 04 06:37:20 PM PDT 24
Peak memory 217600 kb
Host smart-e250ac4d-fb5e-4b22-b9ec-8d35160ba01d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96113723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_e
rr.96113723
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.483664896
Short name T896
Test name
Test status
Simulation time 92322823 ps
CPU time 3.62 seconds
Started Jul 04 06:37:14 PM PDT 24
Finished Jul 04 06:37:17 PM PDT 24
Peak memory 217484 kb
Host smart-2584a2ae-fa0a-43ee-bb94-dcd15140bf9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483664896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.483664896
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.1837434526
Short name T34
Test name
Test status
Simulation time 6266963547 ps
CPU time 190.15 seconds
Started Jul 04 06:41:36 PM PDT 24
Finished Jul 04 06:44:46 PM PDT 24
Peak memory 268060 kb
Host smart-a0da8df6-a6ea-4acf-8457-0c156b16e454
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837434526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.1837434526
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3645711107
Short name T15
Test name
Test status
Simulation time 13869426939 ps
CPU time 517.96 seconds
Started Jul 04 06:42:59 PM PDT 24
Finished Jul 04 06:51:37 PM PDT 24
Peak memory 270524 kb
Host smart-cc3c2cc5-2594-4bc7-b23d-643cf9871b90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645711107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3645711107
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.423036895
Short name T89
Test name
Test status
Simulation time 18759604860 ps
CPU time 307.73 seconds
Started Jul 04 06:43:44 PM PDT 24
Finished Jul 04 06:48:52 PM PDT 24
Peak memory 253252 kb
Host smart-51a66b02-9f20-4c28-855a-3329f337d4b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=423036895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.423036895
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.986432476
Short name T3
Test name
Test status
Simulation time 46525948 ps
CPU time 1.01 seconds
Started Jul 04 06:44:14 PM PDT 24
Finished Jul 04 06:44:16 PM PDT 24
Peak memory 211904 kb
Host smart-d71a17d9-cbe4-4282-a7c7-850dd7ac8a97
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986432476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ct
rl_volatile_unlock_smoke.986432476
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.713265140
Short name T128
Test name
Test status
Simulation time 63961940 ps
CPU time 2.01 seconds
Started Jul 04 06:37:01 PM PDT 24
Finished Jul 04 06:37:03 PM PDT 24
Peak memory 222204 kb
Host smart-8c04f86a-b218-4956-840e-b4adc2dbd2b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713265140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_
err.713265140
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1117061854
Short name T129
Test name
Test status
Simulation time 259773832 ps
CPU time 1.98 seconds
Started Jul 04 06:36:59 PM PDT 24
Finished Jul 04 06:37:02 PM PDT 24
Peak memory 221940 kb
Host smart-97c9f667-065f-461b-9bdd-3ba21739ab9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117061854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1117061854
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.4085698205
Short name T113
Test name
Test status
Simulation time 605442225 ps
CPU time 4.22 seconds
Started Jul 04 06:37:08 PM PDT 24
Finished Jul 04 06:37:12 PM PDT 24
Peak memory 217556 kb
Host smart-899da6fe-7612-49ac-8994-edc7d89323ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085698205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.4085698205
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.34112852
Short name T120
Test name
Test status
Simulation time 174148683 ps
CPU time 2.98 seconds
Started Jul 04 06:36:42 PM PDT 24
Finished Jul 04 06:36:45 PM PDT 24
Peak memory 222552 kb
Host smart-a038216a-4fb8-4094-a169-48ebeb56186b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34112852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_er
r.34112852
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.454826319
Short name T219
Test name
Test status
Simulation time 12480646 ps
CPU time 0.95 seconds
Started Jul 04 06:39:57 PM PDT 24
Finished Jul 04 06:39:58 PM PDT 24
Peak memory 208968 kb
Host smart-23b1ab9a-ebb6-4692-a368-925edc74cfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454826319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.454826319
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.1875078278
Short name T216
Test name
Test status
Simulation time 10881365 ps
CPU time 0.94 seconds
Started Jul 04 06:39:58 PM PDT 24
Finished Jul 04 06:39:59 PM PDT 24
Peak memory 209020 kb
Host smart-05610d4f-8d04-4447-8fba-196130e631e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875078278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1875078278
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.170821784
Short name T217
Test name
Test status
Simulation time 33348246 ps
CPU time 0.87 seconds
Started Jul 04 06:40:14 PM PDT 24
Finished Jul 04 06:40:15 PM PDT 24
Peak memory 209008 kb
Host smart-17144810-41dd-4b81-a2cb-6dbc64ad1f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170821784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.170821784
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2131393823
Short name T126
Test name
Test status
Simulation time 61646543 ps
CPU time 2.38 seconds
Started Jul 04 06:37:00 PM PDT 24
Finished Jul 04 06:37:03 PM PDT 24
Peak memory 222116 kb
Host smart-0e11ee58-57d0-4ad8-9deb-58ea17efe44b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131393823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.2131393823
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2192637646
Short name T114
Test name
Test status
Simulation time 194994958 ps
CPU time 4.17 seconds
Started Jul 04 06:37:09 PM PDT 24
Finished Jul 04 06:37:13 PM PDT 24
Peak memory 217580 kb
Host smart-c632ac00-fce4-4698-8dc5-f9059721e991
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192637646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2192637646
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1949516082
Short name T131
Test name
Test status
Simulation time 431761738 ps
CPU time 2.11 seconds
Started Jul 04 06:37:14 PM PDT 24
Finished Jul 04 06:37:16 PM PDT 24
Peak memory 221764 kb
Host smart-98d4c179-dd2d-4c44-9176-5c49ebd8f0ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949516082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1949516082
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.4512349
Short name T132
Test name
Test status
Simulation time 107321801 ps
CPU time 4.22 seconds
Started Jul 04 06:35:45 PM PDT 24
Finished Jul 04 06:35:49 PM PDT 24
Peak memory 217604 kb
Host smart-5141e045-447d-430c-aa3c-d8c2f3f021b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4512349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_err.4512349
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2208049011
Short name T135
Test name
Test status
Simulation time 124447730 ps
CPU time 2.02 seconds
Started Jul 04 06:36:33 PM PDT 24
Finished Jul 04 06:36:35 PM PDT 24
Peak memory 222068 kb
Host smart-173e2be3-46c7-4c61-8ff1-2e6386c564d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208049011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.2208049011
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2273397573
Short name T7
Test name
Test status
Simulation time 5173127615 ps
CPU time 36.06 seconds
Started Jul 04 06:39:47 PM PDT 24
Finished Jul 04 06:40:24 PM PDT 24
Peak memory 216816 kb
Host smart-0cd35026-09e9-469a-8da0-53c42c4ead86
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273397573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.2273397573
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2696610143
Short name T83
Test name
Test status
Simulation time 164771629 ps
CPU time 7.69 seconds
Started Jul 04 06:43:13 PM PDT 24
Finished Jul 04 06:43:21 PM PDT 24
Peak memory 225984 kb
Host smart-8bfd8258-2380-4182-9ab6-e51074b82017
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696610143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2696610143
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2842674699
Short name T206
Test name
Test status
Simulation time 90161940 ps
CPU time 1.39 seconds
Started Jul 04 06:35:18 PM PDT 24
Finished Jul 04 06:35:19 PM PDT 24
Peak memory 209324 kb
Host smart-0779c3d3-e2a1-4809-8185-9fec984a06e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842674699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.2842674699
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.556582626
Short name T972
Test name
Test status
Simulation time 50974080 ps
CPU time 1.48 seconds
Started Jul 04 06:35:12 PM PDT 24
Finished Jul 04 06:35:13 PM PDT 24
Peak memory 209312 kb
Host smart-940cd903-b34b-4b73-8566-866e5eafa34b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556582626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash
.556582626
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.4100091723
Short name T197
Test name
Test status
Simulation time 19714564 ps
CPU time 1.11 seconds
Started Jul 04 06:35:10 PM PDT 24
Finished Jul 04 06:35:12 PM PDT 24
Peak memory 211364 kb
Host smart-f07b96c8-e027-4111-b836-833e498ee119
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100091723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.4100091723
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2870836537
Short name T882
Test name
Test status
Simulation time 119845430 ps
CPU time 1.2 seconds
Started Jul 04 06:35:16 PM PDT 24
Finished Jul 04 06:35:18 PM PDT 24
Peak memory 218680 kb
Host smart-cfafc308-9ceb-4f44-b265-bb8cfb20140f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870836537 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2870836537
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3128644622
Short name T927
Test name
Test status
Simulation time 23724302 ps
CPU time 0.97 seconds
Started Jul 04 06:35:11 PM PDT 24
Finished Jul 04 06:35:12 PM PDT 24
Peak memory 209276 kb
Host smart-8a24e6f7-4b4c-4da3-8d75-3719f37ac065
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128644622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3128644622
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3214966710
Short name T917
Test name
Test status
Simulation time 69741745 ps
CPU time 1.57 seconds
Started Jul 04 06:35:03 PM PDT 24
Finished Jul 04 06:35:05 PM PDT 24
Peak memory 209168 kb
Host smart-dd211901-ef14-49db-8172-bb80cada646f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214966710 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3214966710
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1346391074
Short name T879
Test name
Test status
Simulation time 2035915953 ps
CPU time 5.88 seconds
Started Jul 04 06:35:05 PM PDT 24
Finished Jul 04 06:35:11 PM PDT 24
Peak memory 208972 kb
Host smart-9a02894a-3fea-4638-98f9-82aedca2c8ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346391074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1346391074
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.659218756
Short name T947
Test name
Test status
Simulation time 6600971608 ps
CPU time 26.42 seconds
Started Jul 04 06:35:04 PM PDT 24
Finished Jul 04 06:35:31 PM PDT 24
Peak memory 217440 kb
Host smart-25ac2b2f-29f3-430a-9680-f3ef3faec682
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659218756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.659218756
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.336336564
Short name T885
Test name
Test status
Simulation time 281110209 ps
CPU time 6.78 seconds
Started Jul 04 06:35:06 PM PDT 24
Finished Jul 04 06:35:12 PM PDT 24
Peak memory 211044 kb
Host smart-d99f3cdf-aacf-4d02-ae43-34ddbc904d31
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336336564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.336336564
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3028508353
Short name T940
Test name
Test status
Simulation time 260320056 ps
CPU time 3.28 seconds
Started Jul 04 06:35:05 PM PDT 24
Finished Jul 04 06:35:08 PM PDT 24
Peak memory 221728 kb
Host smart-eca51f65-c484-4dda-8e76-fe1f0a79f4ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302850
8353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3028508353
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3815246516
Short name T137
Test name
Test status
Simulation time 306643175 ps
CPU time 1.57 seconds
Started Jul 04 06:35:05 PM PDT 24
Finished Jul 04 06:35:07 PM PDT 24
Peak memory 209260 kb
Host smart-62395cc9-b599-4a98-9a08-76cbbe633c86
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815246516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3815246516
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3939736596
Short name T905
Test name
Test status
Simulation time 30741653 ps
CPU time 1.02 seconds
Started Jul 04 06:35:07 PM PDT 24
Finished Jul 04 06:35:08 PM PDT 24
Peak memory 209344 kb
Host smart-cb51fdbb-f2ce-4efa-8b3f-c3a731aaa56c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939736596 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.3939736596
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3032921584
Short name T925
Test name
Test status
Simulation time 15079768 ps
CPU time 1.01 seconds
Started Jul 04 06:35:18 PM PDT 24
Finished Jul 04 06:35:19 PM PDT 24
Peak memory 209316 kb
Host smart-5ab8a69a-047b-42dd-ac33-612e873e4ec6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032921584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3032921584
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.879785824
Short name T916
Test name
Test status
Simulation time 352591920 ps
CPU time 3.08 seconds
Started Jul 04 06:35:11 PM PDT 24
Finished Jul 04 06:35:14 PM PDT 24
Peak memory 218364 kb
Host smart-62758e71-9e8a-420b-bf66-6bef866949bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879785824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.879785824
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.873850813
Short name T121
Test name
Test status
Simulation time 159203344 ps
CPU time 2.12 seconds
Started Jul 04 06:35:10 PM PDT 24
Finished Jul 04 06:35:13 PM PDT 24
Peak memory 217560 kb
Host smart-d4d175e5-ae2d-4a16-b815-c97f638bfe49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873850813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.873850813
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.342224921
Short name T153
Test name
Test status
Simulation time 592067299 ps
CPU time 1.77 seconds
Started Jul 04 06:35:45 PM PDT 24
Finished Jul 04 06:35:47 PM PDT 24
Peak memory 209360 kb
Host smart-8f7e3cbc-fc95-423c-a3b1-67c749501fe3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342224921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.342224921
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.4218619806
Short name T969
Test name
Test status
Simulation time 97390469 ps
CPU time 2.06 seconds
Started Jul 04 06:35:39 PM PDT 24
Finished Jul 04 06:35:42 PM PDT 24
Peak memory 209308 kb
Host smart-77ba0dd6-c658-4d6f-9da4-f6979d4e0e06
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218619806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.4218619806
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3923273524
Short name T150
Test name
Test status
Simulation time 23347450 ps
CPU time 1.08 seconds
Started Jul 04 06:35:39 PM PDT 24
Finished Jul 04 06:35:40 PM PDT 24
Peak memory 211376 kb
Host smart-52961ab3-a8b7-4935-8a2c-4c9e039dec48
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923273524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.3923273524
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1250551909
Short name T912
Test name
Test status
Simulation time 42979195 ps
CPU time 0.97 seconds
Started Jul 04 06:35:45 PM PDT 24
Finished Jul 04 06:35:46 PM PDT 24
Peak memory 217632 kb
Host smart-16b7c343-01fd-4e26-99e6-b84633ee1060
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250551909 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1250551909
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2161385234
Short name T202
Test name
Test status
Simulation time 51534914 ps
CPU time 1.03 seconds
Started Jul 04 06:35:38 PM PDT 24
Finished Jul 04 06:35:39 PM PDT 24
Peak memory 209336 kb
Host smart-14283529-e33a-41b7-87a9-ca08eadcc293
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161385234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2161385234
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1494394246
Short name T870
Test name
Test status
Simulation time 42490083 ps
CPU time 1.68 seconds
Started Jul 04 06:35:40 PM PDT 24
Finished Jul 04 06:35:42 PM PDT 24
Peak memory 208780 kb
Host smart-55db27ed-8de3-4e0b-934a-4167e1b375b9
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494394246 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1494394246
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.4075772765
Short name T884
Test name
Test status
Simulation time 5946621605 ps
CPU time 24.07 seconds
Started Jul 04 06:35:24 PM PDT 24
Finished Jul 04 06:35:49 PM PDT 24
Peak memory 217384 kb
Host smart-6c7e6320-ba46-4743-afe7-09cc5fbdc548
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075772765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.4075772765
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.60135011
Short name T890
Test name
Test status
Simulation time 1305545402 ps
CPU time 12.49 seconds
Started Jul 04 06:35:18 PM PDT 24
Finished Jul 04 06:35:31 PM PDT 24
Peak memory 208956 kb
Host smart-256a42fc-a61b-47d9-a278-7ab8f5fd4169
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60135011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.60135011
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3322242925
Short name T899
Test name
Test status
Simulation time 241639744 ps
CPU time 2.22 seconds
Started Jul 04 06:35:17 PM PDT 24
Finished Jul 04 06:35:19 PM PDT 24
Peak memory 217548 kb
Host smart-37506c63-8439-4951-84bf-541a4febee9d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322242925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.3322242925
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2997669980
Short name T942
Test name
Test status
Simulation time 93187892 ps
CPU time 2.31 seconds
Started Jul 04 06:35:23 PM PDT 24
Finished Jul 04 06:35:26 PM PDT 24
Peak memory 218324 kb
Host smart-021713c0-534d-432b-8ac0-f9f25e560a9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299766
9980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2997669980
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3600344068
Short name T868
Test name
Test status
Simulation time 231411892 ps
CPU time 1.58 seconds
Started Jul 04 06:35:18 PM PDT 24
Finished Jul 04 06:35:20 PM PDT 24
Peak memory 209304 kb
Host smart-a474586f-2194-4435-9b67-95ec363a765d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600344068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.3600344068
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2227438604
Short name T962
Test name
Test status
Simulation time 90490729 ps
CPU time 1.04 seconds
Started Jul 04 06:35:23 PM PDT 24
Finished Jul 04 06:35:25 PM PDT 24
Peak memory 209368 kb
Host smart-ffa212ca-27d6-4903-9820-9e4f4f5c81cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227438604 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.2227438604
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.415909757
Short name T152
Test name
Test status
Simulation time 46699864 ps
CPU time 1.45 seconds
Started Jul 04 06:35:46 PM PDT 24
Finished Jul 04 06:35:48 PM PDT 24
Peak memory 209380 kb
Host smart-1c7c35e4-3a20-454f-b505-ee2c1885a6bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415909757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.415909757
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1275191230
Short name T966
Test name
Test status
Simulation time 299021630 ps
CPU time 4.1 seconds
Started Jul 04 06:35:40 PM PDT 24
Finished Jul 04 06:35:44 PM PDT 24
Peak memory 218316 kb
Host smart-02ab33cf-e372-49e1-9e64-ff80fa33b3ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275191230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1275191230
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.727904627
Short name T133
Test name
Test status
Simulation time 224870350 ps
CPU time 2.59 seconds
Started Jul 04 06:35:39 PM PDT 24
Finished Jul 04 06:35:42 PM PDT 24
Peak memory 217560 kb
Host smart-17248c2d-b7e0-47d4-9d0a-d2630c309510
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727904627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_e
rr.727904627
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1243778123
Short name T964
Test name
Test status
Simulation time 124215749 ps
CPU time 1.11 seconds
Started Jul 04 06:37:01 PM PDT 24
Finished Jul 04 06:37:02 PM PDT 24
Peak memory 219076 kb
Host smart-c736c010-0a14-4ac1-958b-0bd9414c337e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243778123 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1243778123
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2910047915
Short name T200
Test name
Test status
Simulation time 18356703 ps
CPU time 1.2 seconds
Started Jul 04 06:37:00 PM PDT 24
Finished Jul 04 06:37:02 PM PDT 24
Peak memory 209336 kb
Host smart-f5f81169-0319-4e1e-b937-5aaf987d32ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910047915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2910047915
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2915300888
Short name T208
Test name
Test status
Simulation time 43799634 ps
CPU time 1.01 seconds
Started Jul 04 06:37:01 PM PDT 24
Finished Jul 04 06:37:03 PM PDT 24
Peak memory 209448 kb
Host smart-54724ff8-9244-4d62-a1ce-40d49019d701
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915300888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2915300888
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.441369961
Short name T110
Test name
Test status
Simulation time 122484830 ps
CPU time 2.6 seconds
Started Jul 04 06:36:53 PM PDT 24
Finished Jul 04 06:36:56 PM PDT 24
Peak memory 217808 kb
Host smart-f5f7f255-5bfc-4c43-a467-6972624a755b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441369961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.441369961
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1159058170
Short name T939
Test name
Test status
Simulation time 24972981 ps
CPU time 1.51 seconds
Started Jul 04 06:37:01 PM PDT 24
Finished Jul 04 06:37:03 PM PDT 24
Peak memory 221116 kb
Host smart-8d4baaa6-d47c-4f61-ae37-e9401d7c33f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159058170 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1159058170
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.782664841
Short name T960
Test name
Test status
Simulation time 28673320 ps
CPU time 0.91 seconds
Started Jul 04 06:37:01 PM PDT 24
Finished Jul 04 06:37:02 PM PDT 24
Peak memory 209280 kb
Host smart-acb96fb7-42a7-40ea-83c8-a29629da01c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782664841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.782664841
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1958200577
Short name T950
Test name
Test status
Simulation time 307568069 ps
CPU time 1.44 seconds
Started Jul 04 06:37:02 PM PDT 24
Finished Jul 04 06:37:03 PM PDT 24
Peak memory 217604 kb
Host smart-59eed421-70d8-4f91-8a80-715952ce88a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958200577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1958200577
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2727136975
Short name T900
Test name
Test status
Simulation time 153049254 ps
CPU time 2.65 seconds
Started Jul 04 06:37:03 PM PDT 24
Finished Jul 04 06:37:06 PM PDT 24
Peak memory 217512 kb
Host smart-f2528715-9be9-42d8-aef5-07a6e92057e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727136975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2727136975
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3997416893
Short name T957
Test name
Test status
Simulation time 31172782 ps
CPU time 1.01 seconds
Started Jul 04 06:37:00 PM PDT 24
Finished Jul 04 06:37:01 PM PDT 24
Peak memory 217560 kb
Host smart-9ca8aa0a-a024-4ef2-b81c-67246269fcfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997416893 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.3997416893
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2049367348
Short name T895
Test name
Test status
Simulation time 124764375 ps
CPU time 0.87 seconds
Started Jul 04 06:36:59 PM PDT 24
Finished Jul 04 06:37:00 PM PDT 24
Peak memory 209292 kb
Host smart-4c02cac9-afbd-4f95-9779-b88bf19aa12f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049367348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2049367348
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2055521204
Short name T932
Test name
Test status
Simulation time 51493271 ps
CPU time 1.47 seconds
Started Jul 04 06:36:59 PM PDT 24
Finished Jul 04 06:37:01 PM PDT 24
Peak memory 209380 kb
Host smart-2d6e7595-4425-4e28-a403-12dc2434cd57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055521204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.2055521204
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1145802658
Short name T111
Test name
Test status
Simulation time 72202745 ps
CPU time 2.84 seconds
Started Jul 04 06:37:03 PM PDT 24
Finished Jul 04 06:37:06 PM PDT 24
Peak memory 217676 kb
Host smart-88e3bda4-4e07-4b8a-91ab-4c268d5e8aab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145802658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1145802658
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2773816931
Short name T903
Test name
Test status
Simulation time 39623822 ps
CPU time 1.16 seconds
Started Jul 04 06:37:07 PM PDT 24
Finished Jul 04 06:37:08 PM PDT 24
Peak memory 219444 kb
Host smart-ce2491ea-10fb-42a1-89ce-3da6c99cfa9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773816931 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2773816931
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3201565358
Short name T909
Test name
Test status
Simulation time 91605798 ps
CPU time 2.1 seconds
Started Jul 04 06:37:06 PM PDT 24
Finished Jul 04 06:37:08 PM PDT 24
Peak memory 217704 kb
Host smart-30e75ee4-40e2-4533-8c32-6353c65b60f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201565358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.3201565358
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.579195671
Short name T931
Test name
Test status
Simulation time 228235380 ps
CPU time 2.77 seconds
Started Jul 04 06:37:01 PM PDT 24
Finished Jul 04 06:37:04 PM PDT 24
Peak memory 217572 kb
Host smart-19fa448f-83f1-424c-8eee-49692796167c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579195671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.579195671
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3991737045
Short name T953
Test name
Test status
Simulation time 63191232 ps
CPU time 2.74 seconds
Started Jul 04 06:37:00 PM PDT 24
Finished Jul 04 06:37:03 PM PDT 24
Peak memory 217628 kb
Host smart-99acb028-ecdf-4b2b-94c4-7dfc1f22a15c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991737045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.3991737045
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.565637303
Short name T944
Test name
Test status
Simulation time 37795581 ps
CPU time 1.12 seconds
Started Jul 04 06:37:06 PM PDT 24
Finished Jul 04 06:37:08 PM PDT 24
Peak memory 218592 kb
Host smart-c2b661eb-a81a-46b9-8c1d-3cb265061e32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565637303 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.565637303
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1862732005
Short name T935
Test name
Test status
Simulation time 16552306 ps
CPU time 0.92 seconds
Started Jul 04 06:37:09 PM PDT 24
Finished Jul 04 06:37:10 PM PDT 24
Peak memory 209376 kb
Host smart-544ab63b-45a9-4eb1-9a39-493734c6ebd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862732005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1862732005
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2581148832
Short name T210
Test name
Test status
Simulation time 27548807 ps
CPU time 1.4 seconds
Started Jul 04 06:37:07 PM PDT 24
Finished Jul 04 06:37:08 PM PDT 24
Peak memory 209444 kb
Host smart-1f97340b-025f-4d07-b747-c2bb1cbe557d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581148832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2581148832
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3720142428
Short name T983
Test name
Test status
Simulation time 105217757 ps
CPU time 2.45 seconds
Started Jul 04 06:37:09 PM PDT 24
Finished Jul 04 06:37:11 PM PDT 24
Peak memory 217504 kb
Host smart-8eafef6e-f43f-4f92-8217-745b8a4f2e09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720142428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3720142428
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1167750973
Short name T945
Test name
Test status
Simulation time 141767966 ps
CPU time 1.36 seconds
Started Jul 04 06:37:08 PM PDT 24
Finished Jul 04 06:37:10 PM PDT 24
Peak memory 219480 kb
Host smart-3f446698-7d6c-4a1a-9a8a-098f1c440322
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167750973 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.1167750973
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.781839609
Short name T199
Test name
Test status
Simulation time 13099008 ps
CPU time 1.03 seconds
Started Jul 04 06:37:07 PM PDT 24
Finished Jul 04 06:37:08 PM PDT 24
Peak memory 209256 kb
Host smart-a65dffcc-32bc-44e4-85c7-359686fc3f50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781839609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.781839609
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1296784602
Short name T968
Test name
Test status
Simulation time 47522716 ps
CPU time 0.94 seconds
Started Jul 04 06:37:06 PM PDT 24
Finished Jul 04 06:37:07 PM PDT 24
Peak memory 209056 kb
Host smart-ae344ba2-dad9-42fc-b02c-ae7baa897564
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296784602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.1296784602
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1264815005
Short name T992
Test name
Test status
Simulation time 43247324 ps
CPU time 2.98 seconds
Started Jul 04 06:37:08 PM PDT 24
Finished Jul 04 06:37:11 PM PDT 24
Peak memory 217716 kb
Host smart-97e140c7-fc5a-4476-bd27-38cb3e1be9c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264815005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1264815005
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.4047729810
Short name T130
Test name
Test status
Simulation time 114204327 ps
CPU time 4.01 seconds
Started Jul 04 06:37:08 PM PDT 24
Finished Jul 04 06:37:12 PM PDT 24
Peak memory 217616 kb
Host smart-fdf12ffd-fc2d-4a94-9b78-55919ff295ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047729810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.4047729810
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2724757914
Short name T184
Test name
Test status
Simulation time 46450214 ps
CPU time 1.01 seconds
Started Jul 04 06:37:06 PM PDT 24
Finished Jul 04 06:37:07 PM PDT 24
Peak memory 217560 kb
Host smart-ea8283cc-666c-48bd-b069-cc54c0bad121
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724757914 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2724757914
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3633168926
Short name T910
Test name
Test status
Simulation time 70671705 ps
CPU time 0.89 seconds
Started Jul 04 06:37:07 PM PDT 24
Finished Jul 04 06:37:08 PM PDT 24
Peak memory 208760 kb
Host smart-2bb2c9a5-1f15-4ff7-9f19-1b05f496df42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633168926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3633168926
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1791068542
Short name T214
Test name
Test status
Simulation time 26544420 ps
CPU time 1.46 seconds
Started Jul 04 06:37:07 PM PDT 24
Finished Jul 04 06:37:09 PM PDT 24
Peak memory 209384 kb
Host smart-4d3c552b-f12f-4be4-ade3-6267be67f0f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791068542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.1791068542
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3548548448
Short name T887
Test name
Test status
Simulation time 59771675 ps
CPU time 1.97 seconds
Started Jul 04 06:37:08 PM PDT 24
Finished Jul 04 06:37:10 PM PDT 24
Peak memory 217492 kb
Host smart-e7faa17a-e154-4edd-9207-f40667f8bd80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548548448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3548548448
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.211024401
Short name T125
Test name
Test status
Simulation time 150009433 ps
CPU time 1.82 seconds
Started Jul 04 06:37:17 PM PDT 24
Finished Jul 04 06:37:19 PM PDT 24
Peak memory 218780 kb
Host smart-29f58cbd-29cd-4e61-9504-cb3e726ae3c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211024401 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.211024401
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1113759558
Short name T864
Test name
Test status
Simulation time 14047290 ps
CPU time 1.05 seconds
Started Jul 04 06:37:14 PM PDT 24
Finished Jul 04 06:37:15 PM PDT 24
Peak memory 209372 kb
Host smart-8b28109c-13e9-4e39-ae35-2e4426c56898
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113759558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1113759558
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2941330984
Short name T973
Test name
Test status
Simulation time 21600419 ps
CPU time 1.34 seconds
Started Jul 04 06:37:17 PM PDT 24
Finished Jul 04 06:37:18 PM PDT 24
Peak memory 211360 kb
Host smart-e5d22558-67c3-42ea-a89b-76a6c0e891b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941330984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2941330984
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.527295832
Short name T961
Test name
Test status
Simulation time 88132554 ps
CPU time 1.65 seconds
Started Jul 04 06:37:14 PM PDT 24
Finished Jul 04 06:37:16 PM PDT 24
Peak memory 217504 kb
Host smart-79d3f740-3ce5-4078-9d57-ed7494d02150
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527295832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.527295832
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2527927010
Short name T934
Test name
Test status
Simulation time 26633944 ps
CPU time 1.27 seconds
Started Jul 04 06:37:14 PM PDT 24
Finished Jul 04 06:37:16 PM PDT 24
Peak memory 217692 kb
Host smart-5e9ed4a4-9900-4f82-820e-1a6baf704db0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527927010 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.2527927010
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.4009516958
Short name T897
Test name
Test status
Simulation time 50834317 ps
CPU time 0.81 seconds
Started Jul 04 06:37:17 PM PDT 24
Finished Jul 04 06:37:18 PM PDT 24
Peak memory 209312 kb
Host smart-b1da9e84-6d34-4502-9270-c18ab292950d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009516958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.4009516958
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2331653457
Short name T898
Test name
Test status
Simulation time 22405963 ps
CPU time 1.19 seconds
Started Jul 04 06:37:15 PM PDT 24
Finished Jul 04 06:37:16 PM PDT 24
Peak memory 209376 kb
Host smart-2ba4a30a-1754-423c-af3f-5f3f96f50d2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331653457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.2331653457
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3818314244
Short name T981
Test name
Test status
Simulation time 47242303 ps
CPU time 2.82 seconds
Started Jul 04 06:37:15 PM PDT 24
Finished Jul 04 06:37:18 PM PDT 24
Peak memory 217692 kb
Host smart-230eeb52-01ab-4b98-9db2-da0a632ffe02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818314244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3818314244
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1500139521
Short name T123
Test name
Test status
Simulation time 99392208 ps
CPU time 3.93 seconds
Started Jul 04 06:37:13 PM PDT 24
Finished Jul 04 06:37:17 PM PDT 24
Peak memory 217568 kb
Host smart-7acdc1e8-4c54-4357-92f0-25161963796e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500139521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1500139521
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1635257730
Short name T926
Test name
Test status
Simulation time 60123568 ps
CPU time 1.25 seconds
Started Jul 04 06:37:23 PM PDT 24
Finished Jul 04 06:37:24 PM PDT 24
Peak memory 217692 kb
Host smart-b0c43a70-ebd9-417d-9e24-a54f491c442f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635257730 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.1635257730
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3028847812
Short name T207
Test name
Test status
Simulation time 21130201 ps
CPU time 0.99 seconds
Started Jul 04 06:37:15 PM PDT 24
Finished Jul 04 06:37:16 PM PDT 24
Peak memory 209308 kb
Host smart-12bd7d57-908e-4803-aefb-7f1d5931231c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028847812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.3028847812
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3058284855
Short name T937
Test name
Test status
Simulation time 311762936 ps
CPU time 1.87 seconds
Started Jul 04 06:37:25 PM PDT 24
Finished Jul 04 06:37:27 PM PDT 24
Peak memory 217636 kb
Host smart-047d256b-d57c-42c2-bc4b-ab9239e7279e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058284855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3058284855
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.510561090
Short name T201
Test name
Test status
Simulation time 26666225 ps
CPU time 1.42 seconds
Started Jul 04 06:35:52 PM PDT 24
Finished Jul 04 06:35:53 PM PDT 24
Peak memory 209356 kb
Host smart-c26265fc-107a-43fc-90b9-d0e8b28e3401
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510561090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing
.510561090
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2290350300
Short name T889
Test name
Test status
Simulation time 96843275 ps
CPU time 1.55 seconds
Started Jul 04 06:35:53 PM PDT 24
Finished Jul 04 06:35:54 PM PDT 24
Peak memory 209324 kb
Host smart-54b83762-69c8-4a3b-acf4-b0cd34f4ecc6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290350300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.2290350300
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3433034402
Short name T204
Test name
Test status
Simulation time 83483958 ps
CPU time 0.99 seconds
Started Jul 04 06:35:53 PM PDT 24
Finished Jul 04 06:35:54 PM PDT 24
Peak memory 210036 kb
Host smart-95c0ebac-66c5-4f48-819e-83d79133de25
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433034402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3433034402
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3265957102
Short name T872
Test name
Test status
Simulation time 123972343 ps
CPU time 1.51 seconds
Started Jul 04 06:35:52 PM PDT 24
Finished Jul 04 06:35:54 PM PDT 24
Peak memory 222696 kb
Host smart-9dd3ae29-2b09-4259-ade1-0727af984c50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265957102 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3265957102
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.57716039
Short name T943
Test name
Test status
Simulation time 46593457 ps
CPU time 0.96 seconds
Started Jul 04 06:35:53 PM PDT 24
Finished Jul 04 06:35:54 PM PDT 24
Peak memory 209348 kb
Host smart-38429ec4-ee33-46d8-be59-96e4989c3a1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57716039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.57716039
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1851663904
Short name T893
Test name
Test status
Simulation time 66278601 ps
CPU time 1.42 seconds
Started Jul 04 06:35:46 PM PDT 24
Finished Jul 04 06:35:48 PM PDT 24
Peak memory 209224 kb
Host smart-1bb7658c-3ad5-4f9e-a0a3-d83acb61e98e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851663904 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1851663904
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.136263671
Short name T920
Test name
Test status
Simulation time 2040540990 ps
CPU time 13.22 seconds
Started Jul 04 06:35:46 PM PDT 24
Finished Jul 04 06:35:59 PM PDT 24
Peak memory 209084 kb
Host smart-884d74d2-1841-4a9c-bde7-c36e8261203e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136263671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.136263671
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4093194843
Short name T215
Test name
Test status
Simulation time 1488460437 ps
CPU time 9.16 seconds
Started Jul 04 06:35:44 PM PDT 24
Finished Jul 04 06:35:53 PM PDT 24
Peak memory 209280 kb
Host smart-73d95995-dce2-4d7b-899d-6af4fa5e78a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093194843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.4093194843
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.516364510
Short name T908
Test name
Test status
Simulation time 194381861 ps
CPU time 1.95 seconds
Started Jul 04 06:35:46 PM PDT 24
Finished Jul 04 06:35:48 PM PDT 24
Peak memory 210816 kb
Host smart-bb5aed42-a4be-4d07-b94b-8c1a9bffe4c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516364510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.516364510
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1399586864
Short name T914
Test name
Test status
Simulation time 196756474 ps
CPU time 1.58 seconds
Started Jul 04 06:35:44 PM PDT 24
Finished Jul 04 06:35:45 PM PDT 24
Peak memory 217732 kb
Host smart-1542c130-acfc-49c7-a71e-91939c56ad52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139958
6864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1399586864
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2535571483
Short name T922
Test name
Test status
Simulation time 148455757 ps
CPU time 3.95 seconds
Started Jul 04 06:37:02 PM PDT 24
Finished Jul 04 06:37:06 PM PDT 24
Peak memory 216508 kb
Host smart-b15f179b-1ab4-4603-8fe4-0a148f89903e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535571483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.2535571483
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3560576789
Short name T986
Test name
Test status
Simulation time 29304208 ps
CPU time 1.48 seconds
Started Jul 04 06:35:44 PM PDT 24
Finished Jul 04 06:35:46 PM PDT 24
Peak memory 209376 kb
Host smart-5a62b69a-a67b-4ccf-9b33-8373127f0202
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560576789 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.3560576789
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1817009312
Short name T946
Test name
Test status
Simulation time 38875029 ps
CPU time 1.17 seconds
Started Jul 04 06:35:52 PM PDT 24
Finished Jul 04 06:35:54 PM PDT 24
Peak memory 209352 kb
Host smart-d89f2fc2-f19e-4a7b-81bd-a5d678f53ca4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817009312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.1817009312
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3143384594
Short name T949
Test name
Test status
Simulation time 55077586 ps
CPU time 1.86 seconds
Started Jul 04 06:35:46 PM PDT 24
Finished Jul 04 06:35:48 PM PDT 24
Peak memory 217636 kb
Host smart-cc1a5943-d3a0-463e-bd30-131e806e0ef3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143384594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.3143384594
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2729761386
Short name T205
Test name
Test status
Simulation time 48781790 ps
CPU time 1.11 seconds
Started Jul 04 06:35:58 PM PDT 24
Finished Jul 04 06:35:59 PM PDT 24
Peak memory 217632 kb
Host smart-e1fcfdb4-da52-4241-8682-9ee212957bf5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729761386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.2729761386
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.830072578
Short name T975
Test name
Test status
Simulation time 331629555 ps
CPU time 1.86 seconds
Started Jul 04 06:37:20 PM PDT 24
Finished Jul 04 06:37:22 PM PDT 24
Peak memory 209108 kb
Host smart-b07b3c1d-b621-4cc5-b8e5-58f4b40df217
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830072578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bash
.830072578
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2219761720
Short name T907
Test name
Test status
Simulation time 34916042 ps
CPU time 1.1 seconds
Started Jul 04 06:35:57 PM PDT 24
Finished Jul 04 06:35:58 PM PDT 24
Peak memory 211620 kb
Host smart-4973bf43-6f30-4d83-8fca-452a9b544d8d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219761720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.2219761720
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.654344497
Short name T874
Test name
Test status
Simulation time 27825926 ps
CPU time 1.19 seconds
Started Jul 04 06:35:57 PM PDT 24
Finished Jul 04 06:35:59 PM PDT 24
Peak memory 217772 kb
Host smart-c7c333d2-aff6-4fe7-af87-616192838ad6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654344497 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.654344497
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2104076274
Short name T985
Test name
Test status
Simulation time 22913455 ps
CPU time 1.01 seconds
Started Jul 04 06:35:58 PM PDT 24
Finished Jul 04 06:35:59 PM PDT 24
Peak memory 209052 kb
Host smart-dd8d646b-cb94-481c-94ee-9995d89f0c7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104076274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2104076274
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2315594137
Short name T976
Test name
Test status
Simulation time 138854032 ps
CPU time 1.55 seconds
Started Jul 04 06:35:58 PM PDT 24
Finished Jul 04 06:36:00 PM PDT 24
Peak memory 209196 kb
Host smart-5ce7826f-a264-413b-be9d-c4471b522967
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315594137 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2315594137
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1871890956
Short name T881
Test name
Test status
Simulation time 1449516359 ps
CPU time 6.98 seconds
Started Jul 04 06:36:00 PM PDT 24
Finished Jul 04 06:36:07 PM PDT 24
Peak memory 208976 kb
Host smart-f8eba2d1-e3bd-49ee-8390-b338d2027c78
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871890956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1871890956
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3404999082
Short name T891
Test name
Test status
Simulation time 2430317065 ps
CPU time 10.5 seconds
Started Jul 04 06:35:58 PM PDT 24
Finished Jul 04 06:36:08 PM PDT 24
Peak memory 209232 kb
Host smart-b36256ff-2371-4ef0-9117-84bfa67bd11b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404999082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3404999082
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3154241967
Short name T904
Test name
Test status
Simulation time 148221180 ps
CPU time 3.83 seconds
Started Jul 04 06:35:51 PM PDT 24
Finished Jul 04 06:35:55 PM PDT 24
Peak memory 210812 kb
Host smart-039a942c-9c90-4192-930d-48099e15c64c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154241967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3154241967
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3757386855
Short name T988
Test name
Test status
Simulation time 177891659 ps
CPU time 5.36 seconds
Started Jul 04 06:35:58 PM PDT 24
Finished Jul 04 06:36:03 PM PDT 24
Peak memory 217688 kb
Host smart-93a29271-517e-49c5-95ae-b57f0951cf69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375738
6855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3757386855
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2166802965
Short name T924
Test name
Test status
Simulation time 138358520 ps
CPU time 2.04 seconds
Started Jul 04 06:35:52 PM PDT 24
Finished Jul 04 06:35:55 PM PDT 24
Peak memory 209348 kb
Host smart-32e46720-f37c-4630-91a4-72af2f4d9df8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166802965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2166802965
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3106562942
Short name T963
Test name
Test status
Simulation time 63392330 ps
CPU time 1.19 seconds
Started Jul 04 06:35:58 PM PDT 24
Finished Jul 04 06:35:59 PM PDT 24
Peak memory 211504 kb
Host smart-61afc3c9-a81a-4f4b-a14f-42ac788a2df0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106562942 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3106562942
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3562666885
Short name T213
Test name
Test status
Simulation time 198854176 ps
CPU time 1.03 seconds
Started Jul 04 06:35:58 PM PDT 24
Finished Jul 04 06:35:59 PM PDT 24
Peak memory 209572 kb
Host smart-b2b16b65-4941-44dc-be8e-0a4e0d909bbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562666885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.3562666885
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2869650180
Short name T967
Test name
Test status
Simulation time 311648607 ps
CPU time 5 seconds
Started Jul 04 06:35:59 PM PDT 24
Finished Jul 04 06:36:04 PM PDT 24
Peak memory 217508 kb
Host smart-58d01b1e-121e-4a9b-9368-ccef8362ff0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869650180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.2869650180
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3477219492
Short name T151
Test name
Test status
Simulation time 63935597 ps
CPU time 1.84 seconds
Started Jul 04 06:35:58 PM PDT 24
Finished Jul 04 06:36:00 PM PDT 24
Peak memory 217548 kb
Host smart-c6bca155-6201-4982-af58-d34771f47291
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477219492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.3477219492
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2281856861
Short name T876
Test name
Test status
Simulation time 28371632 ps
CPU time 1.11 seconds
Started Jul 04 06:36:18 PM PDT 24
Finished Jul 04 06:36:20 PM PDT 24
Peak memory 209348 kb
Host smart-f8b359a0-a9cb-491b-8da8-026e2ccd668a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281856861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2281856861
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2961224499
Short name T971
Test name
Test status
Simulation time 65679431 ps
CPU time 1.82 seconds
Started Jul 04 06:36:19 PM PDT 24
Finished Jul 04 06:36:21 PM PDT 24
Peak memory 209292 kb
Host smart-1e0b529d-156d-4140-9a48-ec07606ae991
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961224499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2961224499
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1162409459
Short name T198
Test name
Test status
Simulation time 69270585 ps
CPU time 1.12 seconds
Started Jul 04 06:36:13 PM PDT 24
Finished Jul 04 06:36:14 PM PDT 24
Peak memory 219328 kb
Host smart-55e4ceca-4796-44c0-828b-3442672527b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162409459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1162409459
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.169150317
Short name T165
Test name
Test status
Simulation time 22359806 ps
CPU time 1.48 seconds
Started Jul 04 06:36:20 PM PDT 24
Finished Jul 04 06:36:22 PM PDT 24
Peak memory 217744 kb
Host smart-25f65a50-2466-419f-93f9-79e9f82341f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169150317 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.169150317
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1827460024
Short name T965
Test name
Test status
Simulation time 30508780 ps
CPU time 0.9 seconds
Started Jul 04 06:36:12 PM PDT 24
Finished Jul 04 06:36:13 PM PDT 24
Peak memory 209288 kb
Host smart-8d1a026e-b99f-436c-b5c1-a9b4babdc1cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827460024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.1827460024
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1099976394
Short name T933
Test name
Test status
Simulation time 25198484 ps
CPU time 1.06 seconds
Started Jul 04 06:36:13 PM PDT 24
Finished Jul 04 06:36:14 PM PDT 24
Peak memory 209176 kb
Host smart-6f130397-dcc3-4cc9-970d-20f927172817
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099976394 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1099976394
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1376345184
Short name T866
Test name
Test status
Simulation time 193466920 ps
CPU time 5.82 seconds
Started Jul 04 06:36:13 PM PDT 24
Finished Jul 04 06:36:19 PM PDT 24
Peak memory 217284 kb
Host smart-82878b8f-bcc4-4e28-9ea0-0237cf91f29c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376345184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.1376345184
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2386798816
Short name T948
Test name
Test status
Simulation time 2880419866 ps
CPU time 16.6 seconds
Started Jul 04 06:37:20 PM PDT 24
Finished Jul 04 06:37:37 PM PDT 24
Peak memory 209260 kb
Host smart-8ddd369f-6495-47d0-901d-edc7acdee99c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386798816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.2386798816
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2491182347
Short name T861
Test name
Test status
Simulation time 1397229906 ps
CPU time 2.37 seconds
Started Jul 04 06:37:20 PM PDT 24
Finished Jul 04 06:37:23 PM PDT 24
Peak memory 210244 kb
Host smart-f65c842b-99f1-4751-ac59-c1c84dc6f981
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491182347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2491182347
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2173267746
Short name T116
Test name
Test status
Simulation time 81822037 ps
CPU time 2.64 seconds
Started Jul 04 06:36:13 PM PDT 24
Finished Jul 04 06:36:15 PM PDT 24
Peak memory 219124 kb
Host smart-dbccfbbb-e157-4587-9d1b-a7fd663faf52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217326
7746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2173267746
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1563587199
Short name T915
Test name
Test status
Simulation time 348355080 ps
CPU time 1.03 seconds
Started Jul 04 06:37:20 PM PDT 24
Finished Jul 04 06:37:21 PM PDT 24
Peak memory 209140 kb
Host smart-19342bb2-73ef-4496-9af0-3b5c1fe51990
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563587199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1563587199
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2757195661
Short name T980
Test name
Test status
Simulation time 187274159 ps
CPU time 2.08 seconds
Started Jul 04 06:36:13 PM PDT 24
Finished Jul 04 06:36:16 PM PDT 24
Peak memory 211512 kb
Host smart-72b7f3a7-dca9-475e-b9d0-fdd6755913fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757195661 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2757195661
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.904198378
Short name T209
Test name
Test status
Simulation time 82597039 ps
CPU time 1.17 seconds
Started Jul 04 06:36:19 PM PDT 24
Finished Jul 04 06:36:20 PM PDT 24
Peak memory 209176 kb
Host smart-ef8faec1-3b5c-489f-aa0c-dfe74e7cf840
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904198378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
same_csr_outstanding.904198378
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3537081783
Short name T941
Test name
Test status
Simulation time 533979196 ps
CPU time 5.67 seconds
Started Jul 04 06:36:12 PM PDT 24
Finished Jul 04 06:36:18 PM PDT 24
Peak memory 217560 kb
Host smart-344fce6b-31ec-4728-a589-4830253523e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537081783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.3537081783
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1671049356
Short name T122
Test name
Test status
Simulation time 581338137 ps
CPU time 4.45 seconds
Started Jul 04 06:36:12 PM PDT 24
Finished Jul 04 06:36:17 PM PDT 24
Peak memory 217548 kb
Host smart-0826fbd1-35a0-4815-b3d8-a2be7dc3f1b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671049356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1671049356
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2505721304
Short name T878
Test name
Test status
Simulation time 20218326 ps
CPU time 1.33 seconds
Started Jul 04 06:36:25 PM PDT 24
Finished Jul 04 06:36:26 PM PDT 24
Peak memory 221492 kb
Host smart-9aaecc32-0c50-4dd7-85bc-7f95b9a26b27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505721304 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2505721304
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1785192220
Short name T979
Test name
Test status
Simulation time 33347506 ps
CPU time 1.07 seconds
Started Jul 04 06:36:26 PM PDT 24
Finished Jul 04 06:36:27 PM PDT 24
Peak memory 209332 kb
Host smart-b81bbf4b-011f-4399-aa9c-8d57586b175c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785192220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1785192220
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.44886811
Short name T867
Test name
Test status
Simulation time 410940869 ps
CPU time 2.29 seconds
Started Jul 04 06:36:28 PM PDT 24
Finished Jul 04 06:36:30 PM PDT 24
Peak memory 209236 kb
Host smart-e02741fe-dfa0-4f67-86d3-e28514daa3a4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44886811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_alert_test.44886811
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3882315545
Short name T873
Test name
Test status
Simulation time 1110393580 ps
CPU time 6.8 seconds
Started Jul 04 06:36:19 PM PDT 24
Finished Jul 04 06:36:26 PM PDT 24
Peak memory 209044 kb
Host smart-e2481242-5df8-433a-8fe4-ed270c0e4ff5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882315545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3882315545
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3917722512
Short name T984
Test name
Test status
Simulation time 3153850369 ps
CPU time 9.67 seconds
Started Jul 04 06:36:19 PM PDT 24
Finished Jul 04 06:36:28 PM PDT 24
Peak memory 209452 kb
Host smart-6d5d1937-24e2-4d45-b692-d28d30362f01
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917722512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3917722512
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2566175578
Short name T875
Test name
Test status
Simulation time 246373618 ps
CPU time 2.03 seconds
Started Jul 04 06:36:20 PM PDT 24
Finished Jul 04 06:36:23 PM PDT 24
Peak memory 210728 kb
Host smart-605680de-1490-42f6-8730-c34c6364bb2c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566175578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2566175578
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2812572230
Short name T928
Test name
Test status
Simulation time 162843692 ps
CPU time 5.06 seconds
Started Jul 04 06:36:19 PM PDT 24
Finished Jul 04 06:36:25 PM PDT 24
Peak memory 217828 kb
Host smart-a973b284-39ec-480b-9d55-707272924675
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281257
2230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2812572230
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2916743839
Short name T894
Test name
Test status
Simulation time 326825108 ps
CPU time 2.69 seconds
Started Jul 04 06:36:19 PM PDT 24
Finished Jul 04 06:36:22 PM PDT 24
Peak memory 209296 kb
Host smart-7c15fc86-f38f-4b85-8abd-9f2a9e68e045
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916743839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.2916743839
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2753554302
Short name T938
Test name
Test status
Simulation time 48318632 ps
CPU time 1.2 seconds
Started Jul 04 06:36:20 PM PDT 24
Finished Jul 04 06:36:21 PM PDT 24
Peak memory 209360 kb
Host smart-f74333f6-0227-4533-b494-6f03bb9f0dee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753554302 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.2753554302
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3940614765
Short name T990
Test name
Test status
Simulation time 20774112 ps
CPU time 1.01 seconds
Started Jul 04 06:36:24 PM PDT 24
Finished Jul 04 06:36:25 PM PDT 24
Peak memory 209372 kb
Host smart-ed074aa4-e6a7-4f74-8aaa-790d2b36a37a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940614765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.3940614765
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1612349039
Short name T977
Test name
Test status
Simulation time 628050766 ps
CPU time 3.92 seconds
Started Jul 04 06:36:24 PM PDT 24
Finished Jul 04 06:36:29 PM PDT 24
Peak memory 218896 kb
Host smart-4cd602bc-f1d8-425e-870e-60eaf1449cab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612349039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.1612349039
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1241506710
Short name T863
Test name
Test status
Simulation time 29942888 ps
CPU time 1.18 seconds
Started Jul 04 06:36:33 PM PDT 24
Finished Jul 04 06:36:34 PM PDT 24
Peak memory 219944 kb
Host smart-39abc646-dc8f-4bcc-ad0f-ade3d91f0452
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241506710 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.1241506710
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2592619314
Short name T203
Test name
Test status
Simulation time 11845065 ps
CPU time 0.88 seconds
Started Jul 04 06:36:32 PM PDT 24
Finished Jul 04 06:36:33 PM PDT 24
Peak memory 209072 kb
Host smart-e4a64d6f-dad3-45ec-8189-c1ca443b2e44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592619314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.2592619314
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3299417067
Short name T901
Test name
Test status
Simulation time 135808416 ps
CPU time 1.41 seconds
Started Jul 04 06:36:26 PM PDT 24
Finished Jul 04 06:36:27 PM PDT 24
Peak memory 208652 kb
Host smart-043dcb66-97c5-402f-bbcd-587517d84434
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299417067 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.3299417067
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1187877949
Short name T921
Test name
Test status
Simulation time 874164328 ps
CPU time 4.02 seconds
Started Jul 04 06:36:25 PM PDT 24
Finished Jul 04 06:36:29 PM PDT 24
Peak memory 208988 kb
Host smart-9b5d6b18-2945-48c8-8a9b-0d09d18613f1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187877949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1187877949
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1894636212
Short name T952
Test name
Test status
Simulation time 2469596523 ps
CPU time 52.76 seconds
Started Jul 04 06:36:25 PM PDT 24
Finished Jul 04 06:37:18 PM PDT 24
Peak memory 209428 kb
Host smart-61e758ea-ef01-45c8-bacf-9fe684b3633e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894636212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1894636212
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2559968441
Short name T923
Test name
Test status
Simulation time 105035047 ps
CPU time 3.03 seconds
Started Jul 04 06:36:25 PM PDT 24
Finished Jul 04 06:36:28 PM PDT 24
Peak memory 210788 kb
Host smart-aab1d42e-cd8a-47ea-9432-dd5b99351fd3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559968441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2559968441
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.357324046
Short name T886
Test name
Test status
Simulation time 429540567 ps
CPU time 1.83 seconds
Started Jul 04 06:36:27 PM PDT 24
Finished Jul 04 06:36:29 PM PDT 24
Peak memory 217752 kb
Host smart-5c325255-4e1f-4604-8269-728bcec58aa9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357324
046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.357324046
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3486393072
Short name T865
Test name
Test status
Simulation time 58339550 ps
CPU time 1.35 seconds
Started Jul 04 06:36:25 PM PDT 24
Finished Jul 04 06:36:26 PM PDT 24
Peak memory 217308 kb
Host smart-41dc2db6-78ae-4a18-9616-c141b663c0fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486393072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.3486393072
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2243301254
Short name T906
Test name
Test status
Simulation time 48677946 ps
CPU time 1.12 seconds
Started Jul 04 06:36:24 PM PDT 24
Finished Jul 04 06:36:25 PM PDT 24
Peak memory 209360 kb
Host smart-299aea74-8341-4bb5-89e9-a89bf86abfc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243301254 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.2243301254
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1606016328
Short name T958
Test name
Test status
Simulation time 104479203 ps
CPU time 1.09 seconds
Started Jul 04 06:36:32 PM PDT 24
Finished Jul 04 06:36:33 PM PDT 24
Peak memory 209372 kb
Host smart-69874791-83b8-4fd0-911e-5744e6fb4147
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606016328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.1606016328
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1521755306
Short name T124
Test name
Test status
Simulation time 296569784 ps
CPU time 3.3 seconds
Started Jul 04 06:36:26 PM PDT 24
Finished Jul 04 06:36:29 PM PDT 24
Peak memory 217676 kb
Host smart-95ef25b2-9f17-4b9b-b8e5-9a89f0caa93d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521755306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1521755306
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.766950675
Short name T929
Test name
Test status
Simulation time 68507797 ps
CPU time 1.63 seconds
Started Jul 04 06:36:40 PM PDT 24
Finished Jul 04 06:36:42 PM PDT 24
Peak memory 219448 kb
Host smart-565db967-3094-4201-953d-1fb182d51073
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766950675 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.766950675
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2097528379
Short name T136
Test name
Test status
Simulation time 17395966 ps
CPU time 0.92 seconds
Started Jul 04 06:36:40 PM PDT 24
Finished Jul 04 06:36:41 PM PDT 24
Peak memory 208892 kb
Host smart-efe10258-9618-4867-b95c-4e8029e5c717
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097528379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2097528379
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.114561274
Short name T902
Test name
Test status
Simulation time 710513547 ps
CPU time 1.3 seconds
Started Jul 04 06:36:32 PM PDT 24
Finished Jul 04 06:36:34 PM PDT 24
Peak memory 208672 kb
Host smart-2ff6b68e-8625-4dce-9079-d0190b5ed850
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114561274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.lc_ctrl_jtag_alert_test.114561274
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.663226816
Short name T959
Test name
Test status
Simulation time 926219847 ps
CPU time 5.36 seconds
Started Jul 04 06:36:34 PM PDT 24
Finished Jul 04 06:36:39 PM PDT 24
Peak memory 216932 kb
Host smart-b7ca6847-f5df-48ed-b5fc-99c6c5ec3c9f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663226816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.663226816
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1556231034
Short name T869
Test name
Test status
Simulation time 2720974176 ps
CPU time 9.83 seconds
Started Jul 04 06:36:34 PM PDT 24
Finished Jul 04 06:36:44 PM PDT 24
Peak memory 209276 kb
Host smart-20b2a5ed-129e-4576-93db-27673507fd05
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556231034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1556231034
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1491306482
Short name T956
Test name
Test status
Simulation time 211178541 ps
CPU time 1.2 seconds
Started Jul 04 06:36:35 PM PDT 24
Finished Jul 04 06:36:36 PM PDT 24
Peak memory 210408 kb
Host smart-1c9a433d-9a33-4a76-8c0c-45a3e2abd84f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491306482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1491306482
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1710746536
Short name T871
Test name
Test status
Simulation time 116492106 ps
CPU time 3.47 seconds
Started Jul 04 06:36:32 PM PDT 24
Finished Jul 04 06:36:36 PM PDT 24
Peak memory 218432 kb
Host smart-5f13f995-1046-447d-8a7e-7370c5a9e1dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171074
6536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1710746536
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1631743176
Short name T880
Test name
Test status
Simulation time 537261969 ps
CPU time 2.04 seconds
Started Jul 04 06:36:33 PM PDT 24
Finished Jul 04 06:36:35 PM PDT 24
Peak memory 209288 kb
Host smart-2bbbe31c-bc7e-4f9b-99d2-075e403a969a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631743176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.1631743176
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1660526794
Short name T982
Test name
Test status
Simulation time 36401319 ps
CPU time 1.47 seconds
Started Jul 04 06:36:33 PM PDT 24
Finished Jul 04 06:36:34 PM PDT 24
Peak memory 217552 kb
Host smart-b08f07d7-b20c-457b-be5c-35e6e9e1b868
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660526794 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1660526794
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3559215890
Short name T212
Test name
Test status
Simulation time 15218612 ps
CPU time 1.05 seconds
Started Jul 04 06:36:40 PM PDT 24
Finished Jul 04 06:36:41 PM PDT 24
Peak memory 217580 kb
Host smart-98e20793-1bdb-41ea-971e-55b1463e9804
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559215890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3559215890
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.518659041
Short name T989
Test name
Test status
Simulation time 30692859 ps
CPU time 1.92 seconds
Started Jul 04 06:36:34 PM PDT 24
Finished Jul 04 06:36:36 PM PDT 24
Peak memory 217588 kb
Host smart-260c3e5b-d85b-4246-b253-7ac7198f423f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518659041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.518659041
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.745659954
Short name T991
Test name
Test status
Simulation time 99731329 ps
CPU time 1.41 seconds
Started Jul 04 06:36:40 PM PDT 24
Finished Jul 04 06:36:42 PM PDT 24
Peak memory 218500 kb
Host smart-86325ed7-c1e5-4ce1-90a9-da2a29f1d545
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745659954 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.745659954
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2973314461
Short name T987
Test name
Test status
Simulation time 24878190 ps
CPU time 0.87 seconds
Started Jul 04 06:36:39 PM PDT 24
Finished Jul 04 06:36:40 PM PDT 24
Peak memory 209208 kb
Host smart-c3fd10dc-a327-4afb-bdb4-8f92da4df7d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973314461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2973314461
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3337018950
Short name T862
Test name
Test status
Simulation time 1173675103 ps
CPU time 1.33 seconds
Started Jul 04 06:36:38 PM PDT 24
Finished Jul 04 06:36:40 PM PDT 24
Peak memory 208644 kb
Host smart-1ab3917b-74f6-4727-b0bc-d7261a99d5a9
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337018950 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3337018950
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.4066988572
Short name T954
Test name
Test status
Simulation time 371777767 ps
CPU time 4.96 seconds
Started Jul 04 06:36:39 PM PDT 24
Finished Jul 04 06:36:44 PM PDT 24
Peak memory 209252 kb
Host smart-678b0931-9f9d-463f-a1ba-e7fe7c53119a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066988572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.4066988572
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.616661155
Short name T913
Test name
Test status
Simulation time 1515285324 ps
CPU time 8.92 seconds
Started Jul 04 06:36:41 PM PDT 24
Finished Jul 04 06:36:50 PM PDT 24
Peak memory 209240 kb
Host smart-3b1988b6-7227-4bd7-8209-936c4853e3db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616661155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.616661155
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.362222225
Short name T119
Test name
Test status
Simulation time 73031869 ps
CPU time 2.35 seconds
Started Jul 04 06:36:39 PM PDT 24
Finished Jul 04 06:36:42 PM PDT 24
Peak memory 210804 kb
Host smart-8437d052-4644-49bb-b050-4e2e9454791b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362222225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.362222225
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2328367141
Short name T892
Test name
Test status
Simulation time 301878861 ps
CPU time 7.69 seconds
Started Jul 04 06:36:38 PM PDT 24
Finished Jul 04 06:36:46 PM PDT 24
Peak memory 218764 kb
Host smart-7f7e4b41-1504-4d33-b747-fec38e399dd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232836
7141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2328367141
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1003077018
Short name T918
Test name
Test status
Simulation time 100679395 ps
CPU time 1.67 seconds
Started Jul 04 06:36:39 PM PDT 24
Finished Jul 04 06:36:41 PM PDT 24
Peak memory 217284 kb
Host smart-90fa7f3f-f127-40d7-934b-b58a0a991311
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003077018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.1003077018
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.96487030
Short name T930
Test name
Test status
Simulation time 58074339 ps
CPU time 1.16 seconds
Started Jul 04 06:36:42 PM PDT 24
Finished Jul 04 06:36:43 PM PDT 24
Peak memory 209392 kb
Host smart-685cbf8a-e488-4cbb-a5d5-7ef85a733172
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96487030 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.96487030
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.481167915
Short name T211
Test name
Test status
Simulation time 19245759 ps
CPU time 1.35 seconds
Started Jul 04 06:36:40 PM PDT 24
Finished Jul 04 06:36:41 PM PDT 24
Peak memory 209372 kb
Host smart-18d79560-9e86-4cd8-84e7-98c5e4fca9b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481167915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
same_csr_outstanding.481167915
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1174443411
Short name T117
Test name
Test status
Simulation time 184638423 ps
CPU time 3.8 seconds
Started Jul 04 06:36:39 PM PDT 24
Finished Jul 04 06:36:43 PM PDT 24
Peak memory 217512 kb
Host smart-ee474a9a-b584-4500-a9f9-521c376f949b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174443411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1174443411
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2283805599
Short name T974
Test name
Test status
Simulation time 33412887 ps
CPU time 1.82 seconds
Started Jul 04 06:36:53 PM PDT 24
Finished Jul 04 06:36:55 PM PDT 24
Peak memory 222400 kb
Host smart-38f08947-1305-4fb6-914c-5de00411fbf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283805599 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2283805599
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.675047188
Short name T951
Test name
Test status
Simulation time 35129731 ps
CPU time 0.82 seconds
Started Jul 04 06:36:54 PM PDT 24
Finished Jul 04 06:36:55 PM PDT 24
Peak memory 208844 kb
Host smart-28920020-cd48-4b57-bf12-da7b214b36fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675047188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.675047188
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2043590359
Short name T978
Test name
Test status
Simulation time 36284215 ps
CPU time 1.1 seconds
Started Jul 04 06:36:53 PM PDT 24
Finished Jul 04 06:36:54 PM PDT 24
Peak memory 209200 kb
Host smart-0a8b8ed6-46d4-4928-87ad-c52861c8558a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043590359 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2043590359
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.4026380600
Short name T888
Test name
Test status
Simulation time 713343364 ps
CPU time 4.26 seconds
Started Jul 04 06:36:47 PM PDT 24
Finished Jul 04 06:36:51 PM PDT 24
Peak memory 209256 kb
Host smart-64f776d4-ebbf-4f86-9add-050324f6b7cf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026380600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.4026380600
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2266679457
Short name T911
Test name
Test status
Simulation time 1646514604 ps
CPU time 33.68 seconds
Started Jul 04 06:36:45 PM PDT 24
Finished Jul 04 06:37:19 PM PDT 24
Peak memory 209024 kb
Host smart-cc486aa2-5ba4-4683-94fc-96510792ffd8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266679457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2266679457
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3369348821
Short name T883
Test name
Test status
Simulation time 156512803 ps
CPU time 2.45 seconds
Started Jul 04 06:36:43 PM PDT 24
Finished Jul 04 06:36:45 PM PDT 24
Peak memory 210480 kb
Host smart-56de3819-460c-43c8-961a-aac4396326ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369348821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3369348821
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1334355907
Short name T877
Test name
Test status
Simulation time 200137441 ps
CPU time 1.81 seconds
Started Jul 04 06:36:45 PM PDT 24
Finished Jul 04 06:36:47 PM PDT 24
Peak memory 209280 kb
Host smart-3bc09567-bbeb-4114-baf3-4c22f795b129
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334355907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1334355907
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2337373216
Short name T970
Test name
Test status
Simulation time 28665909 ps
CPU time 1.38 seconds
Started Jul 04 06:36:45 PM PDT 24
Finished Jul 04 06:36:46 PM PDT 24
Peak memory 209464 kb
Host smart-3cd94269-9d4c-43b0-82e3-14a4021467f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337373216 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2337373216
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1173636332
Short name T936
Test name
Test status
Simulation time 81229047 ps
CPU time 2 seconds
Started Jul 04 06:36:54 PM PDT 24
Finished Jul 04 06:36:56 PM PDT 24
Peak memory 217544 kb
Host smart-3175c7b9-83db-46ad-8fb6-f2c9e25c2283
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173636332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.1173636332
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3852516930
Short name T919
Test name
Test status
Simulation time 297509356 ps
CPU time 2.48 seconds
Started Jul 04 06:36:56 PM PDT 24
Finished Jul 04 06:36:58 PM PDT 24
Peak memory 217560 kb
Host smart-1758b672-d720-4d18-b562-ee43fcec5f2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852516930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.3852516930
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3249053463
Short name T955
Test name
Test status
Simulation time 122170239 ps
CPU time 2.6 seconds
Started Jul 04 06:36:54 PM PDT 24
Finished Jul 04 06:36:57 PM PDT 24
Peak memory 217592 kb
Host smart-68a7044b-70d2-424b-856b-05d3fb97426b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249053463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3249053463
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.4203160969
Short name T190
Test name
Test status
Simulation time 30459951 ps
CPU time 1.1 seconds
Started Jul 04 06:39:37 PM PDT 24
Finished Jul 04 06:39:38 PM PDT 24
Peak memory 208976 kb
Host smart-bdebdace-e2b4-4d96-ab42-c5079b644571
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203160969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.4203160969
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.2069877790
Short name T23
Test name
Test status
Simulation time 14854720 ps
CPU time 0.87 seconds
Started Jul 04 06:39:35 PM PDT 24
Finished Jul 04 06:39:36 PM PDT 24
Peak memory 208796 kb
Host smart-ca4e8f12-fe97-41cf-80e2-e38e8342da51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069877790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.2069877790
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.2472158542
Short name T639
Test name
Test status
Simulation time 2144689326 ps
CPU time 17.59 seconds
Started Jul 04 06:39:32 PM PDT 24
Finished Jul 04 06:39:49 PM PDT 24
Peak memory 218208 kb
Host smart-f1ef6840-25c4-49ec-a0d0-bb8a14100f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472158542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2472158542
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.818256387
Short name T31
Test name
Test status
Simulation time 1736116961 ps
CPU time 11.92 seconds
Started Jul 04 06:39:29 PM PDT 24
Finished Jul 04 06:39:41 PM PDT 24
Peak memory 217236 kb
Host smart-5c77f1ea-07bf-43f9-90a8-8852dea52802
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818256387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.818256387
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.1664820229
Short name T694
Test name
Test status
Simulation time 3203956538 ps
CPU time 48.56 seconds
Started Jul 04 06:39:32 PM PDT 24
Finished Jul 04 06:40:20 PM PDT 24
Peak memory 220124 kb
Host smart-4eda22f4-a427-4483-8183-bb46f83fb0ae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664820229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.1664820229
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1689174395
Short name T660
Test name
Test status
Simulation time 321732002 ps
CPU time 9.11 seconds
Started Jul 04 06:39:30 PM PDT 24
Finished Jul 04 06:39:40 PM PDT 24
Peak memory 217728 kb
Host smart-070020b4-3e86-43f3-9f42-3a96c71f95be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689174395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
689174395
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2932156051
Short name T246
Test name
Test status
Simulation time 1229135307 ps
CPU time 13.39 seconds
Started Jul 04 06:39:29 PM PDT 24
Finished Jul 04 06:39:42 PM PDT 24
Peak memory 224236 kb
Host smart-76143ff4-27e5-46e9-a029-2620deafe461
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932156051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.2932156051
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.488883517
Short name T811
Test name
Test status
Simulation time 2363794210 ps
CPU time 32.28 seconds
Started Jul 04 06:39:29 PM PDT 24
Finished Jul 04 06:40:01 PM PDT 24
Peak memory 217804 kb
Host smart-4616f1a4-8b0c-4c17-890d-ab147e4a2cdc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488883517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_regwen_during_op.488883517
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.973951729
Short name T813
Test name
Test status
Simulation time 549125998 ps
CPU time 2.46 seconds
Started Jul 04 06:39:29 PM PDT 24
Finished Jul 04 06:39:32 PM PDT 24
Peak memory 217732 kb
Host smart-b528a992-2baf-4063-a1da-3825750d2ee9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973951729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.973951729
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.4284508740
Short name T159
Test name
Test status
Simulation time 966546476 ps
CPU time 47.45 seconds
Started Jul 04 06:39:29 PM PDT 24
Finished Jul 04 06:40:17 PM PDT 24
Peak memory 267404 kb
Host smart-6d562f32-9d11-455c-90e3-d0d688f9af95
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284508740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.4284508740
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1538309370
Short name T825
Test name
Test status
Simulation time 1180748274 ps
CPU time 9.6 seconds
Started Jul 04 06:39:29 PM PDT 24
Finished Jul 04 06:39:39 PM PDT 24
Peak memory 246552 kb
Host smart-7ef9d4c4-f22c-4cf3-9142-e6fa587366c3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538309370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.1538309370
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.77534795
Short name T700
Test name
Test status
Simulation time 76090875 ps
CPU time 2.8 seconds
Started Jul 04 06:39:29 PM PDT 24
Finished Jul 04 06:39:32 PM PDT 24
Peak memory 218224 kb
Host smart-2c62c097-c57f-4df8-aaee-fa1a50346c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77534795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.77534795
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.822026266
Short name T462
Test name
Test status
Simulation time 327199086 ps
CPU time 21.39 seconds
Started Jul 04 06:39:32 PM PDT 24
Finished Jul 04 06:39:53 PM PDT 24
Peak memory 214340 kb
Host smart-3b400a68-aa4b-47eb-8c72-62a45d2faa59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822026266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.822026266
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.4156545621
Short name T832
Test name
Test status
Simulation time 1044025485 ps
CPU time 11.85 seconds
Started Jul 04 06:39:31 PM PDT 24
Finished Jul 04 06:39:43 PM PDT 24
Peak memory 226040 kb
Host smart-99ae7fa1-e2e4-4e1d-8598-a563d4822055
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156545621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.4156545621
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1868506131
Short name T628
Test name
Test status
Simulation time 631192525 ps
CPU time 24.7 seconds
Started Jul 04 06:39:36 PM PDT 24
Finished Jul 04 06:40:01 PM PDT 24
Peak memory 226048 kb
Host smart-a4235c35-e34c-4e4e-974b-e7ed161b1f9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868506131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.1868506131
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1752437434
Short name T682
Test name
Test status
Simulation time 298699024 ps
CPU time 10.14 seconds
Started Jul 04 06:39:29 PM PDT 24
Finished Jul 04 06:39:39 PM PDT 24
Peak memory 218216 kb
Host smart-b10a0d6a-5791-41eb-8fd7-226437d0a650
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752437434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1
752437434
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.3019147841
Short name T517
Test name
Test status
Simulation time 239178806 ps
CPU time 8.95 seconds
Started Jul 04 06:39:30 PM PDT 24
Finished Jul 04 06:39:39 PM PDT 24
Peak memory 218364 kb
Host smart-821be238-b642-4680-a557-c6b006d51af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019147841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3019147841
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.3617779275
Short name T845
Test name
Test status
Simulation time 155592537 ps
CPU time 2.94 seconds
Started Jul 04 06:39:31 PM PDT 24
Finished Jul 04 06:39:34 PM PDT 24
Peak memory 217784 kb
Host smart-f84b01f7-9f93-41c8-9b5e-031fa3546400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617779275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3617779275
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.372613966
Short name T175
Test name
Test status
Simulation time 1142474492 ps
CPU time 27.22 seconds
Started Jul 04 06:39:31 PM PDT 24
Finished Jul 04 06:39:58 PM PDT 24
Peak memory 245404 kb
Host smart-4f2c9270-f3e8-458e-b9e0-c81d0469f676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372613966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.372613966
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2531180036
Short name T674
Test name
Test status
Simulation time 84460780 ps
CPU time 8.18 seconds
Started Jul 04 06:39:30 PM PDT 24
Finished Jul 04 06:39:38 PM PDT 24
Peak memory 250904 kb
Host smart-2cc37a53-e254-4db8-a4f4-72ead18df2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531180036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2531180036
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.815319367
Short name T710
Test name
Test status
Simulation time 34902123301 ps
CPU time 591.53 seconds
Started Jul 04 06:39:36 PM PDT 24
Finished Jul 04 06:49:27 PM PDT 24
Peak memory 283348 kb
Host smart-59f7aa0e-f2f2-4660-b2a0-61e6be39f3c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815319367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.815319367
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.2328399314
Short name T138
Test name
Test status
Simulation time 16329756824 ps
CPU time 731.13 seconds
Started Jul 04 06:39:37 PM PDT 24
Finished Jul 04 06:51:49 PM PDT 24
Peak memory 421720 kb
Host smart-55c983e6-e0f9-4212-a6ec-f7857ce09fad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2328399314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.2328399314
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1077765852
Short name T696
Test name
Test status
Simulation time 34138036 ps
CPU time 0.95 seconds
Started Jul 04 06:39:29 PM PDT 24
Finished Jul 04 06:39:31 PM PDT 24
Peak memory 211948 kb
Host smart-06bd3ba9-fb67-4074-8087-bf63919c721e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077765852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.1077765852
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.916279097
Short name T600
Test name
Test status
Simulation time 64657371 ps
CPU time 1.08 seconds
Started Jul 04 06:39:45 PM PDT 24
Finished Jul 04 06:39:46 PM PDT 24
Peak memory 209072 kb
Host smart-956a0c78-3a14-4b1a-b1cf-63b9e6aad1b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916279097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.916279097
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.985304080
Short name T394
Test name
Test status
Simulation time 263975990 ps
CPU time 11.93 seconds
Started Jul 04 06:39:37 PM PDT 24
Finished Jul 04 06:39:49 PM PDT 24
Peak memory 226048 kb
Host smart-01cc83c1-34f7-4933-8b61-2929705a33c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985304080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.985304080
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.820536079
Short name T461
Test name
Test status
Simulation time 317766233 ps
CPU time 4.67 seconds
Started Jul 04 06:39:56 PM PDT 24
Finished Jul 04 06:40:01 PM PDT 24
Peak memory 217188 kb
Host smart-af57141a-264c-487a-965b-6a48bca8a96b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820536079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.820536079
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.3895525632
Short name T683
Test name
Test status
Simulation time 23473570340 ps
CPU time 99.98 seconds
Started Jul 04 06:39:56 PM PDT 24
Finished Jul 04 06:41:36 PM PDT 24
Peak memory 218928 kb
Host smart-fc14c60e-6356-48da-ab6f-204c45cfa04b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895525632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.3895525632
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.3816805889
Short name T820
Test name
Test status
Simulation time 477396430 ps
CPU time 11.51 seconds
Started Jul 04 06:39:43 PM PDT 24
Finished Jul 04 06:39:55 PM PDT 24
Peak memory 217752 kb
Host smart-191a9226-c8ad-4e36-a68a-e348005adf7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816805889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.3
816805889
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.954832620
Short name T173
Test name
Test status
Simulation time 1932871226 ps
CPU time 9.8 seconds
Started Jul 04 06:39:57 PM PDT 24
Finished Jul 04 06:40:07 PM PDT 24
Peak memory 218204 kb
Host smart-879fe31a-73c8-4729-82fd-ce2154c0c89c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954832620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
prog_failure.954832620
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3829002419
Short name T806
Test name
Test status
Simulation time 701303019 ps
CPU time 3.94 seconds
Started Jul 04 06:39:47 PM PDT 24
Finished Jul 04 06:39:51 PM PDT 24
Peak memory 217660 kb
Host smart-15a07987-977c-4552-9b94-bae8450b34d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829002419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3829002419
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2969873076
Short name T495
Test name
Test status
Simulation time 6979700204 ps
CPU time 68.69 seconds
Started Jul 04 06:39:44 PM PDT 24
Finished Jul 04 06:40:53 PM PDT 24
Peak memory 277856 kb
Host smart-ba81059a-40e1-49ac-860b-d459d71c622a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969873076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.2969873076
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.2554258801
Short name T576
Test name
Test status
Simulation time 469060751 ps
CPU time 19.73 seconds
Started Jul 04 06:39:44 PM PDT 24
Finished Jul 04 06:40:04 PM PDT 24
Peak memory 250444 kb
Host smart-cd9f3bc6-8f36-4ca4-b6f8-d8fef8aa364c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554258801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.2554258801
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.2680771357
Short name T748
Test name
Test status
Simulation time 207647596 ps
CPU time 2.96 seconds
Started Jul 04 06:39:36 PM PDT 24
Finished Jul 04 06:39:40 PM PDT 24
Peak memory 218228 kb
Host smart-b2262108-01a3-4edf-a14c-2b10e91760aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680771357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.2680771357
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.407900482
Short name T355
Test name
Test status
Simulation time 217295735 ps
CPU time 9.17 seconds
Started Jul 04 06:39:37 PM PDT 24
Finished Jul 04 06:39:46 PM PDT 24
Peak memory 217704 kb
Host smart-85fc9952-04f1-4545-bf1e-6a20e84c9809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407900482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.407900482
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.2174380391
Short name T100
Test name
Test status
Simulation time 840697016 ps
CPU time 39.58 seconds
Started Jul 04 06:39:47 PM PDT 24
Finished Jul 04 06:40:27 PM PDT 24
Peak memory 269580 kb
Host smart-5b0e8826-ccab-4a98-a81a-55644ba8cd86
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174380391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2174380391
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.2452301678
Short name T552
Test name
Test status
Simulation time 511582366 ps
CPU time 7.58 seconds
Started Jul 04 06:39:56 PM PDT 24
Finished Jul 04 06:40:04 PM PDT 24
Peak memory 225996 kb
Host smart-36f54b15-766d-4bda-829f-239f2442d1e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452301678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2452301678
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1740226167
Short name T459
Test name
Test status
Simulation time 893082444 ps
CPU time 18.39 seconds
Started Jul 04 06:39:57 PM PDT 24
Finished Jul 04 06:40:15 PM PDT 24
Peak memory 225992 kb
Host smart-5e954b4c-c36c-4b0f-afff-cfacc38d9e3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740226167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1740226167
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2507635410
Short name T391
Test name
Test status
Simulation time 253137776 ps
CPU time 6.86 seconds
Started Jul 04 06:39:47 PM PDT 24
Finished Jul 04 06:39:54 PM PDT 24
Peak memory 224612 kb
Host smart-89608328-7941-4652-91ba-97005438082b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507635410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
507635410
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.558425863
Short name T451
Test name
Test status
Simulation time 582454470 ps
CPU time 7.14 seconds
Started Jul 04 06:39:37 PM PDT 24
Finished Jul 04 06:39:44 PM PDT 24
Peak memory 224632 kb
Host smart-5c16101f-61c7-4b19-a1ee-ba34cccbcaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558425863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.558425863
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.3692410973
Short name T829
Test name
Test status
Simulation time 563578352 ps
CPU time 3.93 seconds
Started Jul 04 06:39:38 PM PDT 24
Finished Jul 04 06:39:42 PM PDT 24
Peak memory 217680 kb
Host smart-80806224-cc16-4f4f-a599-73c829ff12a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692410973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.3692410973
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.1367236067
Short name T624
Test name
Test status
Simulation time 1186940086 ps
CPU time 26.45 seconds
Started Jul 04 06:39:35 PM PDT 24
Finished Jul 04 06:40:02 PM PDT 24
Peak memory 250944 kb
Host smart-0eec753a-3a07-4cce-af61-0ae01a04a979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367236067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1367236067
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1325862618
Short name T354
Test name
Test status
Simulation time 502526530 ps
CPU time 7.36 seconds
Started Jul 04 06:39:38 PM PDT 24
Finished Jul 04 06:39:46 PM PDT 24
Peak memory 247304 kb
Host smart-454af1e7-b45b-4369-ab58-09d285c46535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325862618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1325862618
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.522471609
Short name T653
Test name
Test status
Simulation time 6452605920 ps
CPU time 126.03 seconds
Started Jul 04 06:39:56 PM PDT 24
Finished Jul 04 06:42:02 PM PDT 24
Peak memory 273480 kb
Host smart-8b6145aa-6842-4b1b-9feb-18a7b002b453
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522471609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.522471609
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2410818896
Short name T327
Test name
Test status
Simulation time 36011735 ps
CPU time 0.93 seconds
Started Jul 04 06:39:36 PM PDT 24
Finished Jul 04 06:39:38 PM PDT 24
Peak memory 211996 kb
Host smart-3782965e-8b73-4dec-97f6-eefb49c6fe8b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410818896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2410818896
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.4062836295
Short name T793
Test name
Test status
Simulation time 40464685 ps
CPU time 0.96 seconds
Started Jul 04 06:41:23 PM PDT 24
Finished Jul 04 06:41:24 PM PDT 24
Peak memory 208988 kb
Host smart-7a3f78b8-1a48-4390-ae0c-b9bb7d230803
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062836295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.4062836295
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.4033808501
Short name T538
Test name
Test status
Simulation time 886599715 ps
CPU time 14.95 seconds
Started Jul 04 06:41:11 PM PDT 24
Finished Jul 04 06:41:26 PM PDT 24
Peak memory 226044 kb
Host smart-129a8163-35a2-4f8d-89bb-7cd712f9f169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033808501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.4033808501
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.3065430635
Short name T633
Test name
Test status
Simulation time 398240336 ps
CPU time 10.58 seconds
Started Jul 04 06:41:18 PM PDT 24
Finished Jul 04 06:41:29 PM PDT 24
Peak memory 217160 kb
Host smart-27947ecf-3650-499e-9573-72ca54ed8bf1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065430635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.3065430635
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2975230457
Short name T166
Test name
Test status
Simulation time 16379309557 ps
CPU time 107.72 seconds
Started Jul 04 06:41:12 PM PDT 24
Finished Jul 04 06:43:00 PM PDT 24
Peak memory 220936 kb
Host smart-51a6f795-70c1-4d5b-aef3-bca2f74424b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975230457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2975230457
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.328932171
Short name T608
Test name
Test status
Simulation time 359605049 ps
CPU time 6.49 seconds
Started Jul 04 06:41:11 PM PDT 24
Finished Jul 04 06:41:18 PM PDT 24
Peak memory 223052 kb
Host smart-db1eb959-304a-4004-a166-fa28e7cc61d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328932171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag
_prog_failure.328932171
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.539562774
Short name T831
Test name
Test status
Simulation time 492805709 ps
CPU time 7.2 seconds
Started Jul 04 06:41:19 PM PDT 24
Finished Jul 04 06:41:26 PM PDT 24
Peak memory 217664 kb
Host smart-a6672fdb-f3eb-4ed0-b718-d11b02da59ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539562774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke.
539562774
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.217497388
Short name T325
Test name
Test status
Simulation time 986114639 ps
CPU time 44.44 seconds
Started Jul 04 06:41:11 PM PDT 24
Finished Jul 04 06:41:55 PM PDT 24
Peak memory 251000 kb
Host smart-09d1ccf6-a9b9-471e-8c95-52127a993574
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217497388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_state_failure.217497388
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3654871049
Short name T384
Test name
Test status
Simulation time 1896575968 ps
CPU time 19.8 seconds
Started Jul 04 06:41:18 PM PDT 24
Finished Jul 04 06:41:38 PM PDT 24
Peak memory 250936 kb
Host smart-a15c3e13-1145-45d6-9a68-558888478187
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654871049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.3654871049
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2549248066
Short name T554
Test name
Test status
Simulation time 34888675 ps
CPU time 2.47 seconds
Started Jul 04 06:41:11 PM PDT 24
Finished Jul 04 06:41:14 PM PDT 24
Peak memory 218228 kb
Host smart-a508675c-730e-4f49-aef7-8af5d9aa7fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549248066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2549248066
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1601410485
Short name T548
Test name
Test status
Simulation time 968735614 ps
CPU time 19.19 seconds
Started Jul 04 06:41:10 PM PDT 24
Finished Jul 04 06:41:30 PM PDT 24
Peak memory 226016 kb
Host smart-6e4298fe-ce78-41f6-a176-924b9f5da2de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601410485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1601410485
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2548802836
Short name T858
Test name
Test status
Simulation time 1985764990 ps
CPU time 8.9 seconds
Started Jul 04 06:41:10 PM PDT 24
Finished Jul 04 06:41:19 PM PDT 24
Peak memory 218240 kb
Host smart-0a04d8d5-b39a-46f8-8644-b13037565c21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548802836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
2548802836
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3865260713
Short name T95
Test name
Test status
Simulation time 349302416 ps
CPU time 5.35 seconds
Started Jul 04 06:41:18 PM PDT 24
Finished Jul 04 06:41:23 PM PDT 24
Peak memory 217652 kb
Host smart-fe618ace-27d5-4455-bb05-34ed0376cd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865260713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3865260713
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.2996801158
Short name T257
Test name
Test status
Simulation time 252457436 ps
CPU time 21.49 seconds
Started Jul 04 06:41:10 PM PDT 24
Finished Jul 04 06:41:32 PM PDT 24
Peak memory 250976 kb
Host smart-55b907c3-7f3f-4243-9129-0b7689be04aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996801158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.2996801158
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2745426566
Short name T817
Test name
Test status
Simulation time 190054583 ps
CPU time 9.97 seconds
Started Jul 04 06:41:10 PM PDT 24
Finished Jul 04 06:41:21 PM PDT 24
Peak memory 250988 kb
Host smart-9b7fcbcc-85f9-4b47-bdb3-c7e4d7ecdb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745426566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2745426566
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.3566710759
Short name T673
Test name
Test status
Simulation time 3066427631 ps
CPU time 75.55 seconds
Started Jul 04 06:41:22 PM PDT 24
Finished Jul 04 06:42:38 PM PDT 24
Peak memory 269724 kb
Host smart-cca18c62-8d31-454c-82ca-e7a38993db27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566710759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.3566710759
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.2593000601
Short name T139
Test name
Test status
Simulation time 39010702972 ps
CPU time 452.56 seconds
Started Jul 04 06:41:24 PM PDT 24
Finished Jul 04 06:48:57 PM PDT 24
Peak memory 278860 kb
Host smart-338c17be-0a04-4949-9e7a-d4e4247e828e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2593000601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.2593000601
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2551831348
Short name T512
Test name
Test status
Simulation time 10195042 ps
CPU time 0.92 seconds
Started Jul 04 06:41:13 PM PDT 24
Finished Jul 04 06:41:14 PM PDT 24
Peak memory 208680 kb
Host smart-4cd68521-d112-46d4-b04b-747c2a550e2c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551831348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.2551831348
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.2707162620
Short name T762
Test name
Test status
Simulation time 31158026 ps
CPU time 1.05 seconds
Started Jul 04 06:41:27 PM PDT 24
Finished Jul 04 06:41:28 PM PDT 24
Peak memory 209020 kb
Host smart-86ba7d1a-7109-4f3e-b644-4af56c949a4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707162620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2707162620
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2448900188
Short name T542
Test name
Test status
Simulation time 1899371024 ps
CPU time 19.25 seconds
Started Jul 04 06:41:25 PM PDT 24
Finished Jul 04 06:41:45 PM PDT 24
Peak memory 218236 kb
Host smart-322f79ed-03db-42c3-80cd-eebdeda1de12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448900188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2448900188
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1261061028
Short name T25
Test name
Test status
Simulation time 435420502 ps
CPU time 10.94 seconds
Started Jul 04 06:41:23 PM PDT 24
Finished Jul 04 06:41:34 PM PDT 24
Peak memory 217456 kb
Host smart-c782f375-6e98-4951-91dc-0186a8227a16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261061028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1261061028
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.4107510856
Short name T8
Test name
Test status
Simulation time 27431467170 ps
CPU time 75.45 seconds
Started Jul 04 06:41:23 PM PDT 24
Finished Jul 04 06:42:39 PM PDT 24
Peak memory 218956 kb
Host smart-05c49be6-aca0-4f38-af72-84622a8b20c2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107510856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.4107510856
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.559038320
Short name T229
Test name
Test status
Simulation time 481773732 ps
CPU time 6 seconds
Started Jul 04 06:41:24 PM PDT 24
Finished Jul 04 06:41:30 PM PDT 24
Peak memory 218268 kb
Host smart-b3a4f5ab-84b5-40de-9135-63b555ab70b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559038320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_prog_failure.559038320
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.509602002
Short name T782
Test name
Test status
Simulation time 150673862 ps
CPU time 5.56 seconds
Started Jul 04 06:41:25 PM PDT 24
Finished Jul 04 06:41:30 PM PDT 24
Peak memory 217752 kb
Host smart-666f2538-c68b-48da-a805-15f1f3524a49
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509602002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke.
509602002
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2723596252
Short name T709
Test name
Test status
Simulation time 992647302 ps
CPU time 43.66 seconds
Started Jul 04 06:41:25 PM PDT 24
Finished Jul 04 06:42:09 PM PDT 24
Peak memory 250988 kb
Host smart-fc15ef51-83d6-4f22-8e6d-aa0772d8842c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723596252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.2723596252
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3962664294
Short name T91
Test name
Test status
Simulation time 478189550 ps
CPU time 11.89 seconds
Started Jul 04 06:41:24 PM PDT 24
Finished Jul 04 06:41:36 PM PDT 24
Peak memory 250524 kb
Host smart-6cc366a3-5e5f-478a-a645-99ab99fafa79
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962664294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3962664294
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.118739805
Short name T779
Test name
Test status
Simulation time 122729122 ps
CPU time 2.62 seconds
Started Jul 04 06:41:24 PM PDT 24
Finished Jul 04 06:41:26 PM PDT 24
Peak memory 218232 kb
Host smart-2176878a-eb20-42f1-b654-3720fd79b620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118739805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.118739805
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2347638956
Short name T221
Test name
Test status
Simulation time 1349016365 ps
CPU time 15.23 seconds
Started Jul 04 06:41:24 PM PDT 24
Finished Jul 04 06:41:39 PM PDT 24
Peak memory 219860 kb
Host smart-9e771620-2896-41e0-93ac-cb000f40763b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347638956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2347638956
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.4043225564
Short name T503
Test name
Test status
Simulation time 4832225502 ps
CPU time 21.91 seconds
Started Jul 04 06:41:24 PM PDT 24
Finished Jul 04 06:41:46 PM PDT 24
Peak memory 226128 kb
Host smart-b70b0be1-1b34-4bcf-8345-9ffe96af19c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043225564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.4043225564
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.2748268749
Short name T304
Test name
Test status
Simulation time 1205306322 ps
CPU time 8.69 seconds
Started Jul 04 06:41:24 PM PDT 24
Finished Jul 04 06:41:33 PM PDT 24
Peak memory 218260 kb
Host smart-eab381e0-a68b-4d53-8d59-54e01ec07a59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748268749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
2748268749
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.4177821439
Short name T756
Test name
Test status
Simulation time 97586320 ps
CPU time 2.51 seconds
Started Jul 04 06:41:22 PM PDT 24
Finished Jul 04 06:41:25 PM PDT 24
Peak memory 214444 kb
Host smart-1a2b2ed0-bd39-4e6d-9108-25c3b72be7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177821439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.4177821439
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.2234518328
Short name T518
Test name
Test status
Simulation time 1325675963 ps
CPU time 26.68 seconds
Started Jul 04 06:41:24 PM PDT 24
Finished Jul 04 06:41:51 PM PDT 24
Peak memory 251008 kb
Host smart-bac75891-65c2-4d58-b488-a85c135cb929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234518328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.2234518328
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.1168540822
Short name T374
Test name
Test status
Simulation time 176996657 ps
CPU time 11.33 seconds
Started Jul 04 06:41:19 PM PDT 24
Finished Jul 04 06:41:31 PM PDT 24
Peak memory 250992 kb
Host smart-aa7d2e57-56eb-4276-a3cc-314c4efb707b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168540822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1168540822
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.2629931130
Short name T769
Test name
Test status
Simulation time 34239109902 ps
CPU time 280.26 seconds
Started Jul 04 06:41:25 PM PDT 24
Finished Jul 04 06:46:06 PM PDT 24
Peak memory 276424 kb
Host smart-aebb47cf-6f43-4221-9d41-34f98f6ad04c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629931130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.2629931130
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2874210979
Short name T90
Test name
Test status
Simulation time 35278064 ps
CPU time 0.98 seconds
Started Jul 04 06:41:23 PM PDT 24
Finished Jul 04 06:41:24 PM PDT 24
Peak memory 211860 kb
Host smart-aa10e54a-3db2-44d7-8157-cb8df9ef1c34
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874210979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2874210979
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.2902071272
Short name T390
Test name
Test status
Simulation time 24279323 ps
CPU time 1.06 seconds
Started Jul 04 06:41:35 PM PDT 24
Finished Jul 04 06:41:36 PM PDT 24
Peak memory 208980 kb
Host smart-af7ed73d-216e-4d60-86b8-21508b4dd983
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902071272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.2902071272
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.3618803246
Short name T500
Test name
Test status
Simulation time 345234680 ps
CPU time 15.45 seconds
Started Jul 04 06:41:27 PM PDT 24
Finished Jul 04 06:41:42 PM PDT 24
Peak memory 226032 kb
Host smart-32bed231-2244-498b-b458-e36db76194eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618803246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3618803246
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.1338634160
Short name T59
Test name
Test status
Simulation time 1277974542 ps
CPU time 2.31 seconds
Started Jul 04 06:41:35 PM PDT 24
Finished Jul 04 06:41:37 PM PDT 24
Peak memory 217092 kb
Host smart-75d77c2e-9963-4b10-8de4-a3f8f7b1f310
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338634160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.1338634160
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.2257661182
Short name T789
Test name
Test status
Simulation time 11901871574 ps
CPU time 79.11 seconds
Started Jul 04 06:41:34 PM PDT 24
Finished Jul 04 06:42:53 PM PDT 24
Peak memory 218956 kb
Host smart-9ea6fe31-7ba6-4d24-9364-edfb2baffa4e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257661182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.2257661182
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.149243255
Short name T678
Test name
Test status
Simulation time 2764910662 ps
CPU time 16.64 seconds
Started Jul 04 06:41:35 PM PDT 24
Finished Jul 04 06:41:52 PM PDT 24
Peak memory 218272 kb
Host smart-01506472-4963-4dee-9676-ea76a3a68438
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149243255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag
_prog_failure.149243255
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1524699723
Short name T582
Test name
Test status
Simulation time 1237344494 ps
CPU time 5.18 seconds
Started Jul 04 06:41:27 PM PDT 24
Finished Jul 04 06:41:32 PM PDT 24
Peak memory 217828 kb
Host smart-2664e550-9ad7-409f-8a11-e8603c63f608
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524699723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1524699723
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2523424746
Short name T540
Test name
Test status
Simulation time 6676003660 ps
CPU time 51.92 seconds
Started Jul 04 06:41:25 PM PDT 24
Finished Jul 04 06:42:17 PM PDT 24
Peak memory 251076 kb
Host smart-121d1c30-ec28-442b-8715-64154d826cc0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523424746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.2523424746
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3176494193
Short name T818
Test name
Test status
Simulation time 1728904576 ps
CPU time 27.73 seconds
Started Jul 04 06:41:27 PM PDT 24
Finished Jul 04 06:41:55 PM PDT 24
Peak memory 248148 kb
Host smart-4a6fb430-58fc-4425-81e8-00d86d75b29f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176494193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3176494193
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.3874069926
Short name T744
Test name
Test status
Simulation time 58990302 ps
CPU time 3.46 seconds
Started Jul 04 06:41:26 PM PDT 24
Finished Jul 04 06:41:29 PM PDT 24
Peak memory 218228 kb
Host smart-31f1336e-2ed8-4ba9-94fb-2f06387e3217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874069926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3874069926
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2309822669
Short name T456
Test name
Test status
Simulation time 309531171 ps
CPU time 15.78 seconds
Started Jul 04 06:41:37 PM PDT 24
Finished Jul 04 06:41:53 PM PDT 24
Peak memory 226040 kb
Host smart-c024cfd2-fdda-4a41-b20a-5bddd3c46cbd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309822669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2309822669
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1146059827
Short name T364
Test name
Test status
Simulation time 1365881188 ps
CPU time 12.44 seconds
Started Jul 04 06:41:34 PM PDT 24
Finished Jul 04 06:41:47 PM PDT 24
Peak memory 226036 kb
Host smart-81097e19-e197-415e-85c3-0e1bbcca6ab5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146059827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1146059827
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1245537195
Short name T53
Test name
Test status
Simulation time 1711734513 ps
CPU time 14.2 seconds
Started Jul 04 06:41:34 PM PDT 24
Finished Jul 04 06:41:48 PM PDT 24
Peak memory 218220 kb
Host smart-13ef3661-9cf2-412c-a7cc-c63c6985c03a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245537195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1245537195
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.3874011568
Short name T699
Test name
Test status
Simulation time 1242074716 ps
CPU time 11.34 seconds
Started Jul 04 06:41:26 PM PDT 24
Finished Jul 04 06:41:37 PM PDT 24
Peak memory 225964 kb
Host smart-571fc358-c1f4-4a1f-b69e-4873eb278065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874011568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3874011568
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.804640472
Short name T602
Test name
Test status
Simulation time 31186695 ps
CPU time 2.43 seconds
Started Jul 04 06:41:26 PM PDT 24
Finished Jul 04 06:41:28 PM PDT 24
Peak memory 217724 kb
Host smart-d6ba5e3d-b729-4bc1-bb82-90097e0f86e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804640472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.804640472
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1015826691
Short name T186
Test name
Test status
Simulation time 227805547 ps
CPU time 24.11 seconds
Started Jul 04 06:41:25 PM PDT 24
Finished Jul 04 06:41:49 PM PDT 24
Peak memory 250944 kb
Host smart-ffdb8911-93e7-4ec7-a185-61784407080c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015826691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1015826691
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.155283284
Short name T764
Test name
Test status
Simulation time 285320681 ps
CPU time 7.82 seconds
Started Jul 04 06:41:27 PM PDT 24
Finished Jul 04 06:41:35 PM PDT 24
Peak memory 250912 kb
Host smart-45ed261e-3c0a-4923-ab86-9456b0a0bfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155283284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.155283284
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.1747615902
Short name T149
Test name
Test status
Simulation time 13377994074 ps
CPU time 417.79 seconds
Started Jul 04 06:41:34 PM PDT 24
Finished Jul 04 06:48:32 PM PDT 24
Peak memory 283964 kb
Host smart-2119d492-c39e-402f-beb9-64eb564741f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1747615902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.1747615902
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1122691811
Short name T2
Test name
Test status
Simulation time 30447008 ps
CPU time 0.89 seconds
Started Jul 04 06:41:26 PM PDT 24
Finished Jul 04 06:41:27 PM PDT 24
Peak memory 211896 kb
Host smart-585eda2c-7446-4c65-8c27-8dcdd7dbe406
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122691811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.1122691811
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.2380422142
Short name T763
Test name
Test status
Simulation time 18359692 ps
CPU time 1.1 seconds
Started Jul 04 06:41:40 PM PDT 24
Finished Jul 04 06:41:41 PM PDT 24
Peak memory 209032 kb
Host smart-5266c6f4-ad5f-4d73-b9e6-60554c27f531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380422142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2380422142
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.3828300030
Short name T453
Test name
Test status
Simulation time 4785619329 ps
CPU time 10.29 seconds
Started Jul 04 06:41:34 PM PDT 24
Finished Jul 04 06:41:44 PM PDT 24
Peak memory 218380 kb
Host smart-094fbeef-63a7-4b5c-8e25-7cb60693694f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828300030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.3828300030
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.394549573
Short name T444
Test name
Test status
Simulation time 841291512 ps
CPU time 20.44 seconds
Started Jul 04 06:41:42 PM PDT 24
Finished Jul 04 06:42:03 PM PDT 24
Peak memory 217504 kb
Host smart-28bfd693-b8ff-451d-b53c-abd8bcc5a940
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394549573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.394549573
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.58187799
Short name T619
Test name
Test status
Simulation time 941316189 ps
CPU time 29.82 seconds
Started Jul 04 06:41:40 PM PDT 24
Finished Jul 04 06:42:10 PM PDT 24
Peak memory 226048 kb
Host smart-29d11a83-91a6-4ff3-914a-d2dda8eba97d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58187799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_err
ors.58187799
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.3001530912
Short name T550
Test name
Test status
Simulation time 591059172 ps
CPU time 5.99 seconds
Started Jul 04 06:41:42 PM PDT 24
Finished Jul 04 06:41:48 PM PDT 24
Peak memory 218260 kb
Host smart-4832d562-5c15-4585-83c8-40f6652a85ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001530912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.3001530912
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.197795457
Short name T154
Test name
Test status
Simulation time 296499998 ps
CPU time 4.74 seconds
Started Jul 04 06:41:32 PM PDT 24
Finished Jul 04 06:41:37 PM PDT 24
Peak memory 217716 kb
Host smart-16baf67c-3ba2-4d8c-a680-e4cfce8dc97f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197795457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.
197795457
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.890739547
Short name T256
Test name
Test status
Simulation time 8626713776 ps
CPU time 86.04 seconds
Started Jul 04 06:41:34 PM PDT 24
Finished Jul 04 06:43:00 PM PDT 24
Peak memory 283780 kb
Host smart-72d21ff2-6294-460c-9b61-e7fa070da62a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890739547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_state_failure.890739547
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1234836489
Short name T156
Test name
Test status
Simulation time 324011177 ps
CPU time 9.65 seconds
Started Jul 04 06:41:44 PM PDT 24
Finished Jul 04 06:41:53 PM PDT 24
Peak memory 250388 kb
Host smart-e26b15bf-c9ce-4ff4-a436-74d1c5afe837
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234836489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1234836489
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.63099406
Short name T180
Test name
Test status
Simulation time 48700622 ps
CPU time 1.72 seconds
Started Jul 04 06:41:34 PM PDT 24
Finished Jul 04 06:41:36 PM PDT 24
Peak memory 222108 kb
Host smart-f91ab967-1627-4693-b5e1-09a6b4202315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63099406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.63099406
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.1472050787
Short name T734
Test name
Test status
Simulation time 1859634385 ps
CPU time 20.24 seconds
Started Jul 04 06:41:43 PM PDT 24
Finished Jul 04 06:42:04 PM PDT 24
Peak memory 226144 kb
Host smart-34417834-72a1-49e0-b9c5-22da5950bd97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472050787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.1472050787
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.556164420
Short name T422
Test name
Test status
Simulation time 447337229 ps
CPU time 13.56 seconds
Started Jul 04 06:41:41 PM PDT 24
Finished Jul 04 06:41:54 PM PDT 24
Peak memory 226016 kb
Host smart-5746de98-2642-47af-bebb-e88acae3f2ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556164420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di
gest.556164420
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2150156212
Short name T395
Test name
Test status
Simulation time 540119861 ps
CPU time 19.33 seconds
Started Jul 04 06:41:40 PM PDT 24
Finished Jul 04 06:42:00 PM PDT 24
Peak memory 218220 kb
Host smart-88387de3-f483-4d75-a40e-b7d835d90fff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150156212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
2150156212
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2699944487
Short name T631
Test name
Test status
Simulation time 247606949 ps
CPU time 10.87 seconds
Started Jul 04 06:41:37 PM PDT 24
Finished Jul 04 06:41:48 PM PDT 24
Peak memory 218360 kb
Host smart-c3b5d164-5126-4986-98e9-1d398052d4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699944487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2699944487
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2858855830
Short name T233
Test name
Test status
Simulation time 1254953505 ps
CPU time 2.99 seconds
Started Jul 04 06:41:36 PM PDT 24
Finished Jul 04 06:41:39 PM PDT 24
Peak memory 214956 kb
Host smart-4da4ce96-96e6-4984-9a34-e78a38d0df78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858855830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2858855830
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.568993683
Short name T711
Test name
Test status
Simulation time 590024990 ps
CPU time 27.84 seconds
Started Jul 04 06:41:37 PM PDT 24
Finished Jul 04 06:42:05 PM PDT 24
Peak memory 250972 kb
Host smart-586794dd-0826-4f6e-a875-4576b6db47ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568993683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.568993683
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.354024961
Short name T301
Test name
Test status
Simulation time 147849632 ps
CPU time 6.3 seconds
Started Jul 04 06:41:35 PM PDT 24
Finished Jul 04 06:41:41 PM PDT 24
Peak memory 250980 kb
Host smart-5a2f3d57-2951-4586-84ad-91533ed6e139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354024961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.354024961
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.623387429
Short name T33
Test name
Test status
Simulation time 17348634408 ps
CPU time 84.45 seconds
Started Jul 04 06:41:41 PM PDT 24
Finished Jul 04 06:43:06 PM PDT 24
Peak memory 258924 kb
Host smart-007de5bc-c843-4619-ad61-aa46c94c4583
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623387429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.623387429
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.795811003
Short name T274
Test name
Test status
Simulation time 116293624 ps
CPU time 0.91 seconds
Started Jul 04 06:41:36 PM PDT 24
Finished Jul 04 06:41:37 PM PDT 24
Peak memory 211840 kb
Host smart-a9d85043-2a20-4567-99fe-1cee6a40cbb5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795811003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_volatile_unlock_smoke.795811003
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2828988328
Short name T302
Test name
Test status
Simulation time 48181627 ps
CPU time 0.84 seconds
Started Jul 04 06:41:50 PM PDT 24
Finished Jul 04 06:41:51 PM PDT 24
Peak memory 208892 kb
Host smart-94ad475b-0b32-4b9e-ae73-320155f9f394
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828988328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2828988328
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2967128605
Short name T35
Test name
Test status
Simulation time 387238121 ps
CPU time 13.6 seconds
Started Jul 04 06:41:41 PM PDT 24
Finished Jul 04 06:41:55 PM PDT 24
Peak memory 218220 kb
Host smart-9300c101-e2e9-4dd4-9a8c-6dae688f5579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967128605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2967128605
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.2172334684
Short name T547
Test name
Test status
Simulation time 2520750557 ps
CPU time 6.15 seconds
Started Jul 04 06:41:50 PM PDT 24
Finished Jul 04 06:41:56 PM PDT 24
Peak memory 217648 kb
Host smart-b313c1a2-5938-4cad-bd41-5b700aa13459
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172334684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.2172334684
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.3547826594
Short name T531
Test name
Test status
Simulation time 1801907315 ps
CPU time 23.89 seconds
Started Jul 04 06:41:51 PM PDT 24
Finished Jul 04 06:42:15 PM PDT 24
Peak memory 218256 kb
Host smart-66011a98-b5d6-493e-bd25-f2dce09e8fe8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547826594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.3547826594
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.3260858395
Short name T358
Test name
Test status
Simulation time 1556717059 ps
CPU time 20.59 seconds
Started Jul 04 06:41:49 PM PDT 24
Finished Jul 04 06:42:10 PM PDT 24
Peak memory 218224 kb
Host smart-1bbe5e44-b281-4892-8d7f-d095705f7efc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260858395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.3260858395
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.826108696
Short name T64
Test name
Test status
Simulation time 120614032 ps
CPU time 2.22 seconds
Started Jul 04 06:41:42 PM PDT 24
Finished Jul 04 06:41:44 PM PDT 24
Peak memory 217748 kb
Host smart-6e512d28-88ef-49d5-b840-f408aa8edbb2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826108696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.
826108696
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3383378078
Short name T330
Test name
Test status
Simulation time 9812370138 ps
CPU time 63.61 seconds
Started Jul 04 06:41:41 PM PDT 24
Finished Jul 04 06:42:45 PM PDT 24
Peak memory 273520 kb
Host smart-ad65e7e2-6af2-42ca-a8d7-274c867f948c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383378078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.3383378078
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2404601953
Short name T326
Test name
Test status
Simulation time 739963406 ps
CPU time 11.36 seconds
Started Jul 04 06:41:51 PM PDT 24
Finished Jul 04 06:42:03 PM PDT 24
Peak memory 250964 kb
Host smart-274cbb68-09d7-43c7-9463-a1c6764bb5f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404601953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.2404601953
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.3517438604
Short name T423
Test name
Test status
Simulation time 311950320 ps
CPU time 3.81 seconds
Started Jul 04 06:41:43 PM PDT 24
Finished Jul 04 06:41:47 PM PDT 24
Peak memory 218256 kb
Host smart-ce56fc5b-a73b-4d17-87d6-2152116fcce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517438604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.3517438604
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.4035424115
Short name T738
Test name
Test status
Simulation time 316488709 ps
CPU time 13.22 seconds
Started Jul 04 06:41:50 PM PDT 24
Finished Jul 04 06:42:03 PM PDT 24
Peak memory 218264 kb
Host smart-a64d4ef9-2b01-48a7-82d3-a7fbcc1e782f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035424115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.4035424115
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.2553183739
Short name T320
Test name
Test status
Simulation time 2317585491 ps
CPU time 13 seconds
Started Jul 04 06:41:50 PM PDT 24
Finished Jul 04 06:42:03 PM PDT 24
Peak memory 226116 kb
Host smart-70eb90bc-775d-4b00-bdce-83ec86b7921f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553183739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.2553183739
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.444514994
Short name T289
Test name
Test status
Simulation time 338301800 ps
CPU time 8.87 seconds
Started Jul 04 06:41:51 PM PDT 24
Finished Jul 04 06:42:00 PM PDT 24
Peak memory 218208 kb
Host smart-4695e4d1-3c92-4783-8f0b-ccb5906d8d20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444514994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.444514994
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.4083792058
Short name T386
Test name
Test status
Simulation time 864878428 ps
CPU time 6.52 seconds
Started Jul 04 06:41:42 PM PDT 24
Finished Jul 04 06:41:49 PM PDT 24
Peak memory 224436 kb
Host smart-93308ac0-d57c-4f2c-bcd5-f909eff1d5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083792058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.4083792058
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3617201296
Short name T77
Test name
Test status
Simulation time 611861014 ps
CPU time 2.72 seconds
Started Jul 04 06:41:44 PM PDT 24
Finished Jul 04 06:41:46 PM PDT 24
Peak memory 214688 kb
Host smart-70967009-e53e-44ec-b0db-8ecffa457168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617201296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3617201296
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.285476086
Short name T807
Test name
Test status
Simulation time 176053945 ps
CPU time 19.56 seconds
Started Jul 04 06:41:42 PM PDT 24
Finished Jul 04 06:42:02 PM PDT 24
Peak memory 250976 kb
Host smart-61a52bc1-80c9-4569-8c51-30a7eed26f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285476086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.285476086
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.187569903
Short name T785
Test name
Test status
Simulation time 904917742 ps
CPU time 6.5 seconds
Started Jul 04 06:41:41 PM PDT 24
Finished Jul 04 06:41:48 PM PDT 24
Peak memory 250956 kb
Host smart-e0259308-a8f8-46a7-bfe9-74297324e58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187569903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.187569903
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.3528213270
Short name T313
Test name
Test status
Simulation time 8486190403 ps
CPU time 168.82 seconds
Started Jul 04 06:41:50 PM PDT 24
Finished Jul 04 06:44:39 PM PDT 24
Peak memory 281140 kb
Host smart-5672cbed-a686-44a1-b841-65b468ca0e70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528213270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.3528213270
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3968273413
Short name T261
Test name
Test status
Simulation time 11562863 ps
CPU time 0.99 seconds
Started Jul 04 06:41:42 PM PDT 24
Finished Jul 04 06:41:43 PM PDT 24
Peak memory 211892 kb
Host smart-6c9b1201-f764-419c-a909-9424f8c25b7c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968273413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3968273413
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.44857730
Short name T739
Test name
Test status
Simulation time 220417830 ps
CPU time 0.96 seconds
Started Jul 04 06:42:00 PM PDT 24
Finished Jul 04 06:42:01 PM PDT 24
Peak memory 209112 kb
Host smart-8cd1b1c7-4562-4105-8d1a-4357fdae6743
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44857730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.44857730
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.1424285767
Short name T647
Test name
Test status
Simulation time 271749916 ps
CPU time 11.45 seconds
Started Jul 04 06:41:50 PM PDT 24
Finished Jul 04 06:42:01 PM PDT 24
Peak memory 225984 kb
Host smart-a568c801-80e3-46af-b395-d1ba7fe87aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424285767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.1424285767
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1782833353
Short name T26
Test name
Test status
Simulation time 1693790914 ps
CPU time 10.66 seconds
Started Jul 04 06:41:54 PM PDT 24
Finished Jul 04 06:42:05 PM PDT 24
Peak memory 217108 kb
Host smart-9f2d4aad-e660-44f0-916f-4aba77ea9473
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782833353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1782833353
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1147220931
Short name T720
Test name
Test status
Simulation time 1787227734 ps
CPU time 31.42 seconds
Started Jul 04 06:41:49 PM PDT 24
Finished Jul 04 06:42:21 PM PDT 24
Peak memory 218896 kb
Host smart-454ac4fc-f6a8-416c-ac9d-5bf66b0eaaeb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147220931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1147220931
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.3027268926
Short name T596
Test name
Test status
Simulation time 735100421 ps
CPU time 3.8 seconds
Started Jul 04 06:41:54 PM PDT 24
Finished Jul 04 06:41:58 PM PDT 24
Peak memory 218264 kb
Host smart-f772bb20-d870-45e2-bdc6-9e55227a1435
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027268926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.3027268926
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1781496236
Short name T814
Test name
Test status
Simulation time 77352380 ps
CPU time 3.08 seconds
Started Jul 04 06:41:50 PM PDT 24
Finished Jul 04 06:41:53 PM PDT 24
Peak memory 217724 kb
Host smart-830f3f66-3a70-4107-98fe-84c8f9ab4183
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781496236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1781496236
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.392181241
Short name T737
Test name
Test status
Simulation time 2392182638 ps
CPU time 33.78 seconds
Started Jul 04 06:41:51 PM PDT 24
Finished Jul 04 06:42:25 PM PDT 24
Peak memory 251064 kb
Host smart-43f1637a-fdda-49f8-b3b0-512a6c02b048
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392181241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_state_failure.392181241
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2704648135
Short name T573
Test name
Test status
Simulation time 2284966602 ps
CPU time 15.7 seconds
Started Jul 04 06:41:49 PM PDT 24
Finished Jul 04 06:42:05 PM PDT 24
Peak memory 251144 kb
Host smart-3f574c2b-8f79-4cd6-bf5b-b08a183045e0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704648135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.2704648135
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2258963864
Short name T686
Test name
Test status
Simulation time 63449011 ps
CPU time 3.33 seconds
Started Jul 04 06:41:49 PM PDT 24
Finished Jul 04 06:41:52 PM PDT 24
Peak memory 218176 kb
Host smart-a912b1f1-f818-4a27-9da1-f47d22c1a4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258963864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2258963864
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.1945784115
Short name T847
Test name
Test status
Simulation time 459287565 ps
CPU time 12.79 seconds
Started Jul 04 06:41:51 PM PDT 24
Finished Jul 04 06:42:04 PM PDT 24
Peak memory 226032 kb
Host smart-ddda9795-7dff-4ab7-8d8a-19a2a8c6e4d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945784115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1945784115
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2250101065
Short name T695
Test name
Test status
Simulation time 2768354827 ps
CPU time 12.59 seconds
Started Jul 04 06:42:00 PM PDT 24
Finished Jul 04 06:42:12 PM PDT 24
Peak memory 226100 kb
Host smart-b252e2ce-229d-4371-b03a-1f37490313dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250101065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2250101065
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.2884470339
Short name T855
Test name
Test status
Simulation time 351588012 ps
CPU time 10.6 seconds
Started Jul 04 06:41:58 PM PDT 24
Finished Jul 04 06:42:09 PM PDT 24
Peak memory 226060 kb
Host smart-8c1c866f-cbfa-494d-b059-8ea6f43d5483
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884470339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
2884470339
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3664290371
Short name T372
Test name
Test status
Simulation time 623798374 ps
CPU time 14.42 seconds
Started Jul 04 06:41:49 PM PDT 24
Finished Jul 04 06:42:04 PM PDT 24
Peak memory 226020 kb
Host smart-7f520b65-dedb-4998-96d2-ffba7f5dc463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664290371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3664290371
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1008946298
Short name T743
Test name
Test status
Simulation time 1469465093 ps
CPU time 3.82 seconds
Started Jul 04 06:41:49 PM PDT 24
Finished Jul 04 06:41:53 PM PDT 24
Peak memory 217744 kb
Host smart-30edfe48-fec4-472e-8a68-4773b16a0a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008946298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1008946298
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.1710547934
Short name T230
Test name
Test status
Simulation time 443427507 ps
CPU time 20.06 seconds
Started Jul 04 06:41:49 PM PDT 24
Finished Jul 04 06:42:10 PM PDT 24
Peak memory 251076 kb
Host smart-1886a6d6-1bdd-456f-9026-f6ca1941d2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710547934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.1710547934
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1105022360
Short name T5
Test name
Test status
Simulation time 132129883 ps
CPU time 6.64 seconds
Started Jul 04 06:41:50 PM PDT 24
Finished Jul 04 06:41:57 PM PDT 24
Peak memory 247360 kb
Host smart-ba030fff-39e4-4aec-9bc3-78d3dcb30bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105022360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1105022360
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.1695746376
Short name T565
Test name
Test status
Simulation time 41623798005 ps
CPU time 205.64 seconds
Started Jul 04 06:41:59 PM PDT 24
Finished Jul 04 06:45:25 PM PDT 24
Peak memory 226104 kb
Host smart-2b11a5fb-875e-4ea0-bede-c3d5f224691c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695746376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.1695746376
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1694618156
Short name T12
Test name
Test status
Simulation time 34379396 ps
CPU time 0.91 seconds
Started Jul 04 06:41:49 PM PDT 24
Finished Jul 04 06:41:50 PM PDT 24
Peak memory 211900 kb
Host smart-cf5f66fe-87a0-4b93-8dff-42b7781ca051
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694618156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.1694618156
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2643524036
Short name T751
Test name
Test status
Simulation time 118488704 ps
CPU time 1.09 seconds
Started Jul 04 06:42:09 PM PDT 24
Finished Jul 04 06:42:10 PM PDT 24
Peak memory 208976 kb
Host smart-662b5314-2290-446e-87f2-29174bc4b3b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643524036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2643524036
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.3803344870
Short name T285
Test name
Test status
Simulation time 2970487527 ps
CPU time 18.27 seconds
Started Jul 04 06:41:59 PM PDT 24
Finished Jul 04 06:42:18 PM PDT 24
Peak memory 219096 kb
Host smart-ada5d253-817f-4f2c-813d-af7aab542ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803344870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3803344870
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.188551324
Short name T753
Test name
Test status
Simulation time 677493199 ps
CPU time 4.12 seconds
Started Jul 04 06:42:02 PM PDT 24
Finished Jul 04 06:42:06 PM PDT 24
Peak memory 217040 kb
Host smart-2f634a12-f97d-4c20-803d-67ffbb1e9db5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188551324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.188551324
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.483120985
Short name T265
Test name
Test status
Simulation time 3592649537 ps
CPU time 48.74 seconds
Started Jul 04 06:41:58 PM PDT 24
Finished Jul 04 06:42:47 PM PDT 24
Peak memory 218232 kb
Host smart-f3838708-46c3-4964-b541-3a67e7448c25
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483120985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_er
rors.483120985
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.328951774
Short name T441
Test name
Test status
Simulation time 1299100026 ps
CPU time 6.69 seconds
Started Jul 04 06:41:59 PM PDT 24
Finished Jul 04 06:42:06 PM PDT 24
Peak memory 218252 kb
Host smart-7e6af2fb-459e-4c80-9fcd-3524737d8f5a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328951774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag
_prog_failure.328951774
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2730623280
Short name T502
Test name
Test status
Simulation time 362687123 ps
CPU time 6.34 seconds
Started Jul 04 06:41:59 PM PDT 24
Finished Jul 04 06:42:05 PM PDT 24
Peak memory 217708 kb
Host smart-c1328729-d4c0-4ca7-b884-6faf1ed64e08
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730623280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2730623280
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1804636495
Short name T597
Test name
Test status
Simulation time 4209216939 ps
CPU time 82.72 seconds
Started Jul 04 06:42:00 PM PDT 24
Finished Jul 04 06:43:23 PM PDT 24
Peak memory 283768 kb
Host smart-dc2cec92-d149-4afe-a90f-720d50e2725e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804636495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.1804636495
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.2797446766
Short name T418
Test name
Test status
Simulation time 1167641487 ps
CPU time 27.64 seconds
Started Jul 04 06:42:00 PM PDT 24
Finished Jul 04 06:42:28 PM PDT 24
Peak memory 226620 kb
Host smart-da68063f-4b99-4db5-bad1-d586c59bfcbc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797446766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.2797446766
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2882190603
Short name T697
Test name
Test status
Simulation time 96163192 ps
CPU time 1.82 seconds
Started Jul 04 06:41:59 PM PDT 24
Finished Jul 04 06:42:01 PM PDT 24
Peak memory 218200 kb
Host smart-640f613c-5bd3-461d-b8de-f1deb2abafff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882190603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2882190603
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1382812251
Short name T432
Test name
Test status
Simulation time 2808964584 ps
CPU time 12.79 seconds
Started Jul 04 06:41:59 PM PDT 24
Finished Jul 04 06:42:12 PM PDT 24
Peak memory 226092 kb
Host smart-f32a2fa4-b218-48e2-ac71-e51c0cdac2ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382812251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1382812251
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.259654946
Short name T310
Test name
Test status
Simulation time 711801038 ps
CPU time 10.38 seconds
Started Jul 04 06:41:57 PM PDT 24
Finished Jul 04 06:42:08 PM PDT 24
Peak memory 226012 kb
Host smart-8b185624-7dc3-4c41-824e-99dac2bdfd5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259654946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_di
gest.259654946
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2873300071
Short name T610
Test name
Test status
Simulation time 1485793896 ps
CPU time 8.05 seconds
Started Jul 04 06:41:59 PM PDT 24
Finished Jul 04 06:42:07 PM PDT 24
Peak memory 226040 kb
Host smart-dabe22d7-bf10-4027-9980-e91bf196ac59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873300071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2873300071
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.1582371809
Short name T646
Test name
Test status
Simulation time 290243438 ps
CPU time 8.83 seconds
Started Jul 04 06:41:58 PM PDT 24
Finished Jul 04 06:42:07 PM PDT 24
Peak memory 218304 kb
Host smart-4b2e6f4c-1e55-447a-929d-45dbf67575eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582371809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1582371809
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.2816412570
Short name T311
Test name
Test status
Simulation time 100586367 ps
CPU time 1.62 seconds
Started Jul 04 06:42:01 PM PDT 24
Finished Jul 04 06:42:03 PM PDT 24
Peak memory 217728 kb
Host smart-204be98f-9f21-4ee1-ba50-900fc5115b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816412570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.2816412570
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.3013899898
Short name T357
Test name
Test status
Simulation time 609717627 ps
CPU time 23.99 seconds
Started Jul 04 06:42:00 PM PDT 24
Finished Jul 04 06:42:24 PM PDT 24
Peak memory 250956 kb
Host smart-b913562a-b4d7-45e0-b0b3-dc5d09be8cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013899898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3013899898
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.1321788803
Short name T499
Test name
Test status
Simulation time 648008100 ps
CPU time 6.77 seconds
Started Jul 04 06:42:00 PM PDT 24
Finished Jul 04 06:42:07 PM PDT 24
Peak memory 250952 kb
Host smart-1033923b-6db5-4744-8de0-bcf0fe130691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321788803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.1321788803
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2682500992
Short name T505
Test name
Test status
Simulation time 5559855884 ps
CPU time 158.78 seconds
Started Jul 04 06:42:08 PM PDT 24
Finished Jul 04 06:44:47 PM PDT 24
Peak memory 241744 kb
Host smart-24cb6e72-5ff6-4f68-a72a-3a3b804eece2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682500992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2682500992
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.4237471846
Short name T506
Test name
Test status
Simulation time 45613800 ps
CPU time 1.01 seconds
Started Jul 04 06:41:59 PM PDT 24
Finished Jul 04 06:42:00 PM PDT 24
Peak memory 211964 kb
Host smart-023d24fb-9492-4d8b-bd3a-535d2cc686e9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237471846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.4237471846
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.3524076394
Short name T350
Test name
Test status
Simulation time 42386624 ps
CPU time 0.88 seconds
Started Jul 04 06:42:08 PM PDT 24
Finished Jul 04 06:42:09 PM PDT 24
Peak memory 208784 kb
Host smart-12a0701f-6195-4048-911c-81d6bb962b37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524076394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.3524076394
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.1758983164
Short name T273
Test name
Test status
Simulation time 4998031424 ps
CPU time 16.98 seconds
Started Jul 04 06:42:08 PM PDT 24
Finished Jul 04 06:42:25 PM PDT 24
Peak memory 226108 kb
Host smart-51b923ad-bdf8-4b55-ae3b-7ab6cce013b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758983164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1758983164
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.856845927
Short name T572
Test name
Test status
Simulation time 444944299 ps
CPU time 3.65 seconds
Started Jul 04 06:42:07 PM PDT 24
Finished Jul 04 06:42:11 PM PDT 24
Peak memory 217112 kb
Host smart-cff93008-fb14-4e58-b150-8b616bd78a04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856845927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.856845927
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3399275448
Short name T616
Test name
Test status
Simulation time 7714434270 ps
CPU time 36.45 seconds
Started Jul 04 06:42:08 PM PDT 24
Finished Jul 04 06:42:45 PM PDT 24
Peak memory 218936 kb
Host smart-2c8825af-0c51-4b2a-bd30-bb288a790c0a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399275448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3399275448
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.777022892
Short name T414
Test name
Test status
Simulation time 515304752 ps
CPU time 9.56 seconds
Started Jul 04 06:42:08 PM PDT 24
Finished Jul 04 06:42:17 PM PDT 24
Peak memory 218264 kb
Host smart-a93e4ef4-62ca-4f13-9e26-2b3116e40c3e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777022892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.777022892
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1261883841
Short name T305
Test name
Test status
Simulation time 147965689 ps
CPU time 3.2 seconds
Started Jul 04 06:42:10 PM PDT 24
Finished Jul 04 06:42:14 PM PDT 24
Peak memory 217764 kb
Host smart-8a716037-7d7f-47ff-99f4-dc4a2d35a1cc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261883841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1261883841
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.956619390
Short name T592
Test name
Test status
Simulation time 3371305824 ps
CPU time 66.41 seconds
Started Jul 04 06:42:07 PM PDT 24
Finished Jul 04 06:43:14 PM PDT 24
Peak memory 270848 kb
Host smart-128afb16-9fa2-40c1-92da-02eb6a9a6d8e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956619390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.956619390
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1523575107
Short name T474
Test name
Test status
Simulation time 668956944 ps
CPU time 24.5 seconds
Started Jul 04 06:42:10 PM PDT 24
Finished Jul 04 06:42:35 PM PDT 24
Peak memory 251040 kb
Host smart-b6abe98b-2fcc-437d-bc61-a2f5ef27db73
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523575107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.1523575107
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1303015734
Short name T755
Test name
Test status
Simulation time 385741356 ps
CPU time 4.77 seconds
Started Jul 04 06:42:09 PM PDT 24
Finished Jul 04 06:42:14 PM PDT 24
Peak memory 218192 kb
Host smart-19a052f8-86e2-44e4-b749-be84d2e050da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303015734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1303015734
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.4181789418
Short name T496
Test name
Test status
Simulation time 811080571 ps
CPU time 11.75 seconds
Started Jul 04 06:42:08 PM PDT 24
Finished Jul 04 06:42:20 PM PDT 24
Peak memory 226028 kb
Host smart-57d0124b-b2d1-41a0-a8a1-966e71c83fe0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181789418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.4181789418
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.1068587747
Short name T343
Test name
Test status
Simulation time 1110945325 ps
CPU time 7.84 seconds
Started Jul 04 06:42:08 PM PDT 24
Finished Jul 04 06:42:16 PM PDT 24
Peak memory 218252 kb
Host smart-c46fb5e6-d82e-459c-80e7-068547da8dff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068587747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
1068587747
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.2025549024
Short name T783
Test name
Test status
Simulation time 2191893620 ps
CPU time 13.34 seconds
Started Jul 04 06:42:10 PM PDT 24
Finished Jul 04 06:42:24 PM PDT 24
Peak memory 218428 kb
Host smart-042a5819-dfa0-40b1-9cd8-9bf75ce759d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025549024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2025549024
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.1645750977
Short name T68
Test name
Test status
Simulation time 55634035 ps
CPU time 3.45 seconds
Started Jul 04 06:42:08 PM PDT 24
Finished Jul 04 06:42:12 PM PDT 24
Peak memory 214636 kb
Host smart-c662da88-a2fa-43de-997a-bbb5182da2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645750977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1645750977
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.4128356651
Short name T809
Test name
Test status
Simulation time 256359318 ps
CPU time 23.85 seconds
Started Jul 04 06:42:09 PM PDT 24
Finished Jul 04 06:42:33 PM PDT 24
Peak memory 250992 kb
Host smart-60858096-d7b0-4461-9c2b-405bf56743df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128356651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.4128356651
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.104656431
Short name T729
Test name
Test status
Simulation time 253960454 ps
CPU time 2.74 seconds
Started Jul 04 06:42:10 PM PDT 24
Finished Jul 04 06:42:13 PM PDT 24
Peak memory 226404 kb
Host smart-ae3bd743-686b-4a6e-84fd-6e5a1c2b7909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104656431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.104656431
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.3333899730
Short name T404
Test name
Test status
Simulation time 64571246590 ps
CPU time 251.17 seconds
Started Jul 04 06:42:07 PM PDT 24
Finished Jul 04 06:46:19 PM PDT 24
Peak memory 362060 kb
Host smart-b3b18617-7b4c-4eb5-afe4-fc3594b9607c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333899730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.3333899730
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.3313916982
Short name T142
Test name
Test status
Simulation time 53262317628 ps
CPU time 2656.77 seconds
Started Jul 04 06:42:09 PM PDT 24
Finished Jul 04 07:26:26 PM PDT 24
Peak memory 611608 kb
Host smart-d5183f07-379c-4a9f-8db9-44218740638d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3313916982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.3313916982
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.1445268071
Short name T702
Test name
Test status
Simulation time 27403823 ps
CPU time 0.98 seconds
Started Jul 04 06:42:09 PM PDT 24
Finished Jul 04 06:42:10 PM PDT 24
Peak memory 211852 kb
Host smart-30799997-40a1-4fac-a48b-722b88e4fa15
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445268071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.1445268071
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3041859685
Short name T757
Test name
Test status
Simulation time 20714978 ps
CPU time 1.06 seconds
Started Jul 04 06:42:16 PM PDT 24
Finished Jul 04 06:42:17 PM PDT 24
Peak memory 208972 kb
Host smart-2889879e-f6c8-4185-81b0-677f32ea37ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041859685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3041859685
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.277081616
Short name T356
Test name
Test status
Simulation time 867905312 ps
CPU time 18.95 seconds
Started Jul 04 06:42:07 PM PDT 24
Finished Jul 04 06:42:26 PM PDT 24
Peak memory 218164 kb
Host smart-c91d07ca-1ae1-4a48-a22f-ce8ee583ad8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277081616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.277081616
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.1664884561
Short name T174
Test name
Test status
Simulation time 1065949513 ps
CPU time 6.07 seconds
Started Jul 04 06:42:15 PM PDT 24
Finished Jul 04 06:42:22 PM PDT 24
Peak memory 217764 kb
Host smart-26767401-d49a-4024-b7fa-80ff4ee8c5ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664884561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.1664884561
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2914195545
Short name T594
Test name
Test status
Simulation time 1400527891 ps
CPU time 46.1 seconds
Started Jul 04 06:42:16 PM PDT 24
Finished Jul 04 06:43:03 PM PDT 24
Peak memory 218900 kb
Host smart-631a6656-fb9d-410d-b0f6-541de04c8307
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914195545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2914195545
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3827963426
Short name T365
Test name
Test status
Simulation time 166679234 ps
CPU time 4.44 seconds
Started Jul 04 06:42:16 PM PDT 24
Finished Jul 04 06:42:20 PM PDT 24
Peak memory 218252 kb
Host smart-7a7ada8d-e1a7-477e-bb3f-01944bdb7424
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827963426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3827963426
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2558813161
Short name T75
Test name
Test status
Simulation time 471003425 ps
CPU time 11.68 seconds
Started Jul 04 06:42:07 PM PDT 24
Finished Jul 04 06:42:19 PM PDT 24
Peak memory 217720 kb
Host smart-1652ee03-993a-4da3-bd4b-9bf0001e4652
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558813161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2558813161
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.4055926774
Short name T745
Test name
Test status
Simulation time 1245635046 ps
CPU time 45.98 seconds
Started Jul 04 06:42:15 PM PDT 24
Finished Jul 04 06:43:01 PM PDT 24
Peak memory 267384 kb
Host smart-6d030802-ac09-4982-acc2-2c4faf54e714
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055926774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.4055926774
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3532072092
Short name T369
Test name
Test status
Simulation time 1764979740 ps
CPU time 17.77 seconds
Started Jul 04 06:42:16 PM PDT 24
Finished Jul 04 06:42:34 PM PDT 24
Peak memory 250404 kb
Host smart-3316eaba-309d-44c5-b573-8d75aba265c1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532072092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.3532072092
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3635623794
Short name T481
Test name
Test status
Simulation time 210852972 ps
CPU time 2.03 seconds
Started Jul 04 06:42:08 PM PDT 24
Finished Jul 04 06:42:10 PM PDT 24
Peak memory 222060 kb
Host smart-7e336e4d-4741-4897-8bd3-5764e9ab1144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635623794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3635623794
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.135700143
Short name T317
Test name
Test status
Simulation time 5843981088 ps
CPU time 15.6 seconds
Started Jul 04 06:42:17 PM PDT 24
Finished Jul 04 06:42:33 PM PDT 24
Peak memory 219548 kb
Host smart-289add19-d49f-4339-8c66-009155dba8ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135700143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.135700143
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1173051804
Short name T271
Test name
Test status
Simulation time 1226234439 ps
CPU time 11.5 seconds
Started Jul 04 06:42:15 PM PDT 24
Finished Jul 04 06:42:27 PM PDT 24
Peak memory 226052 kb
Host smart-7f65d031-c72c-4118-ac38-5d401dc77a0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173051804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1173051804
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.4202138828
Short name T645
Test name
Test status
Simulation time 379577979 ps
CPU time 8.77 seconds
Started Jul 04 06:42:16 PM PDT 24
Finished Jul 04 06:42:25 PM PDT 24
Peak memory 218256 kb
Host smart-62c490a5-6884-436f-baf1-c4a7b015a316
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202138828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
4202138828
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.3820974226
Short name T752
Test name
Test status
Simulation time 799424356 ps
CPU time 9.41 seconds
Started Jul 04 06:42:10 PM PDT 24
Finished Jul 04 06:42:19 PM PDT 24
Peak memory 226036 kb
Host smart-e9666175-227d-4339-983e-2a8bac8c314d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820974226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3820974226
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.4166033435
Short name T239
Test name
Test status
Simulation time 36728616 ps
CPU time 1.82 seconds
Started Jul 04 06:42:09 PM PDT 24
Finished Jul 04 06:42:11 PM PDT 24
Peak memory 213844 kb
Host smart-e88b1bce-9e3a-45af-8360-90dea4889ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166033435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.4166033435
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.695267929
Short name T537
Test name
Test status
Simulation time 1311542900 ps
CPU time 33.69 seconds
Started Jul 04 06:42:07 PM PDT 24
Finished Jul 04 06:42:42 PM PDT 24
Peak memory 250960 kb
Host smart-8074884d-a97a-4426-a8e4-5dc0202159f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695267929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.695267929
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.1930515235
Short name T617
Test name
Test status
Simulation time 371884779 ps
CPU time 6.35 seconds
Started Jul 04 06:42:11 PM PDT 24
Finished Jul 04 06:42:17 PM PDT 24
Peak memory 246948 kb
Host smart-1d53a259-fdca-4b8b-9497-978590f6ab3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930515235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1930515235
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.4275144851
Short name T440
Test name
Test status
Simulation time 71386612565 ps
CPU time 90.21 seconds
Started Jul 04 06:42:15 PM PDT 24
Finished Jul 04 06:43:45 PM PDT 24
Peak memory 267544 kb
Host smart-e7fb52c1-5993-468f-b549-8acd47eaa9ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275144851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.4275144851
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.4092878362
Short name T282
Test name
Test status
Simulation time 41368933 ps
CPU time 1.28 seconds
Started Jul 04 06:42:09 PM PDT 24
Finished Jul 04 06:42:11 PM PDT 24
Peak memory 212948 kb
Host smart-f2709f03-7e1b-457e-8e2d-85664b86715c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092878362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.4092878362
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2388006978
Short name T460
Test name
Test status
Simulation time 25616034 ps
CPU time 1.01 seconds
Started Jul 04 06:42:24 PM PDT 24
Finished Jul 04 06:42:25 PM PDT 24
Peak memory 208980 kb
Host smart-d24410a1-9612-4040-8833-306d7afd488b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388006978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2388006978
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1973147157
Short name T171
Test name
Test status
Simulation time 638539535 ps
CPU time 13.22 seconds
Started Jul 04 06:42:24 PM PDT 24
Finished Jul 04 06:42:38 PM PDT 24
Peak memory 218232 kb
Host smart-cdb48b71-c3fb-4cd5-b448-a5721db22cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973147157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1973147157
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.3445301812
Short name T838
Test name
Test status
Simulation time 260130416 ps
CPU time 3.54 seconds
Started Jul 04 06:42:24 PM PDT 24
Finished Jul 04 06:42:28 PM PDT 24
Peak memory 217172 kb
Host smart-d38a256f-ecd0-46f3-84ac-e4496d2284b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445301812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.3445301812
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.853879682
Short name T822
Test name
Test status
Simulation time 2099706771 ps
CPU time 61.16 seconds
Started Jul 04 06:42:25 PM PDT 24
Finished Jul 04 06:43:26 PM PDT 24
Peak memory 218384 kb
Host smart-fba026ee-7d71-4aad-b1d9-36d73354df15
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853879682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_er
rors.853879682
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.4194095479
Short name T366
Test name
Test status
Simulation time 1395291031 ps
CPU time 3.96 seconds
Started Jul 04 06:42:24 PM PDT 24
Finished Jul 04 06:42:28 PM PDT 24
Peak memory 218212 kb
Host smart-2cc705ca-2224-4403-b065-5f9f5cc3f7cc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194095479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.4194095479
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2402325041
Short name T716
Test name
Test status
Simulation time 744843546 ps
CPU time 5.74 seconds
Started Jul 04 06:42:25 PM PDT 24
Finished Jul 04 06:42:31 PM PDT 24
Peak memory 217716 kb
Host smart-d2549467-f830-4b91-907c-6f7667ea2908
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402325041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2402325041
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2363602603
Short name T786
Test name
Test status
Simulation time 1702202924 ps
CPU time 68.44 seconds
Started Jul 04 06:42:22 PM PDT 24
Finished Jul 04 06:43:30 PM PDT 24
Peak memory 276292 kb
Host smart-db2d9ecb-b008-4175-8401-4ed17bbd16d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363602603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.2363602603
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.756575985
Short name T794
Test name
Test status
Simulation time 1537365918 ps
CPU time 16.75 seconds
Started Jul 04 06:42:24 PM PDT 24
Finished Jul 04 06:42:41 PM PDT 24
Peak memory 227444 kb
Host smart-91ab3585-b85e-42c4-9a67-e5d329258f01
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756575985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_
jtag_state_post_trans.756575985
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.1901696476
Short name T607
Test name
Test status
Simulation time 40078661 ps
CPU time 2.42 seconds
Started Jul 04 06:42:16 PM PDT 24
Finished Jul 04 06:42:18 PM PDT 24
Peak memory 218232 kb
Host smart-3a01a724-0323-472a-bbe1-819120989368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901696476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.1901696476
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3828215967
Short name T322
Test name
Test status
Simulation time 298356979 ps
CPU time 15.62 seconds
Started Jul 04 06:42:23 PM PDT 24
Finished Jul 04 06:42:39 PM PDT 24
Peak memory 218896 kb
Host smart-747dffec-7e34-45a4-bb61-21dce64ed3fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828215967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3828215967
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3802136789
Short name T715
Test name
Test status
Simulation time 587185590 ps
CPU time 9.02 seconds
Started Jul 04 06:42:25 PM PDT 24
Finished Jul 04 06:42:34 PM PDT 24
Peak memory 218176 kb
Host smart-18622e11-3914-4c4f-8357-a12b0688903d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802136789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.3802136789
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2847020171
Short name T264
Test name
Test status
Simulation time 347949813 ps
CPU time 9.93 seconds
Started Jul 04 06:42:22 PM PDT 24
Finished Jul 04 06:42:32 PM PDT 24
Peak memory 226052 kb
Host smart-cb06cfa2-7589-456b-b23f-2fee8e11be03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847020171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2847020171
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.2740459897
Short name T761
Test name
Test status
Simulation time 5978575308 ps
CPU time 19.89 seconds
Started Jul 04 06:42:24 PM PDT 24
Finished Jul 04 06:42:44 PM PDT 24
Peak memory 218372 kb
Host smart-0a2e021c-480a-4b0b-9d3d-2fcf2b3469a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740459897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2740459897
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.633623569
Short name T504
Test name
Test status
Simulation time 81954023 ps
CPU time 2.18 seconds
Started Jul 04 06:42:16 PM PDT 24
Finished Jul 04 06:42:18 PM PDT 24
Peak memory 214464 kb
Host smart-874c9d9e-479d-42f9-a626-f4047289adbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633623569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.633623569
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1797549655
Short name T108
Test name
Test status
Simulation time 264466073 ps
CPU time 27.44 seconds
Started Jul 04 06:42:16 PM PDT 24
Finished Jul 04 06:42:44 PM PDT 24
Peak memory 250972 kb
Host smart-629f527f-81bc-4134-a2a0-076ea8050bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797549655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1797549655
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.3188719341
Short name T790
Test name
Test status
Simulation time 235528784 ps
CPU time 6.31 seconds
Started Jul 04 06:42:14 PM PDT 24
Finished Jul 04 06:42:21 PM PDT 24
Peak memory 250528 kb
Host smart-77f92169-a76a-4672-97c0-fddbfadee076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188719341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3188719341
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.233788204
Short name T402
Test name
Test status
Simulation time 14820312103 ps
CPU time 470.16 seconds
Started Jul 04 06:42:24 PM PDT 24
Finished Jul 04 06:50:14 PM PDT 24
Peak memory 282468 kb
Host smart-e7735972-2d43-40f4-b720-032811ceed35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233788204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.233788204
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.362160349
Short name T39
Test name
Test status
Simulation time 72447416257 ps
CPU time 690.4 seconds
Started Jul 04 06:42:24 PM PDT 24
Finished Jul 04 06:53:54 PM PDT 24
Peak memory 272788 kb
Host smart-57562389-6603-41f4-bd2d-ba4840b7fde5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=362160349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.362160349
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.562627233
Short name T563
Test name
Test status
Simulation time 27533226 ps
CPU time 1.01 seconds
Started Jul 04 06:42:15 PM PDT 24
Finished Jul 04 06:42:16 PM PDT 24
Peak memory 211960 kb
Host smart-4fae5539-f5f4-42d9-806c-4cd65600162a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562627233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct
rl_volatile_unlock_smoke.562627233
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.3272892803
Short name T546
Test name
Test status
Simulation time 23975088 ps
CPU time 0.97 seconds
Started Jul 04 06:39:59 PM PDT 24
Finished Jul 04 06:40:01 PM PDT 24
Peak memory 208944 kb
Host smart-3889422c-cba1-4eb0-9b5a-be56b73e56a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272892803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3272892803
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.3017364602
Short name T708
Test name
Test status
Simulation time 39751210 ps
CPU time 0.95 seconds
Started Jul 04 06:39:54 PM PDT 24
Finished Jul 04 06:39:55 PM PDT 24
Peak memory 209056 kb
Host smart-a7aae7be-66ec-42d8-8ebb-0010b0f2f8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017364602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.3017364602
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.219583921
Short name T435
Test name
Test status
Simulation time 2716070482 ps
CPU time 8.74 seconds
Started Jul 04 06:39:59 PM PDT 24
Finished Jul 04 06:40:08 PM PDT 24
Peak memory 218268 kb
Host smart-927526b6-5d9a-4e92-a901-22b7b389c27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219583921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.219583921
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.3725796777
Short name T568
Test name
Test status
Simulation time 369702226 ps
CPU time 5.34 seconds
Started Jul 04 06:39:52 PM PDT 24
Finished Jul 04 06:39:57 PM PDT 24
Peak memory 217352 kb
Host smart-c2394408-7031-4996-9489-ab30864fcc64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725796777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.3725796777
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.2265582015
Short name T276
Test name
Test status
Simulation time 1733855489 ps
CPU time 53.8 seconds
Started Jul 04 06:39:52 PM PDT 24
Finished Jul 04 06:40:46 PM PDT 24
Peak memory 226068 kb
Host smart-0b4db128-5739-40f1-97e4-917469450eef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265582015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.2265582015
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.2832380671
Short name T523
Test name
Test status
Simulation time 313576868 ps
CPU time 3.88 seconds
Started Jul 04 06:39:52 PM PDT 24
Finished Jul 04 06:39:56 PM PDT 24
Peak memory 217792 kb
Host smart-07b06a1c-dacd-42ee-a22f-12187f83a81e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832380671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.2
832380671
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3122119362
Short name T679
Test name
Test status
Simulation time 770110100 ps
CPU time 22.52 seconds
Started Jul 04 06:39:53 PM PDT 24
Finished Jul 04 06:40:15 PM PDT 24
Peak memory 218216 kb
Host smart-dd61cb27-c54f-4caf-a90e-989327c84493
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122119362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3122119362
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2158120684
Short name T72
Test name
Test status
Simulation time 873205338 ps
CPU time 12.27 seconds
Started Jul 04 06:39:53 PM PDT 24
Finished Jul 04 06:40:05 PM PDT 24
Peak memory 217732 kb
Host smart-9191faf0-5f8a-4b71-aa19-1f786488d47c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158120684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.2158120684
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.2423889126
Short name T781
Test name
Test status
Simulation time 1385556909 ps
CPU time 11.38 seconds
Started Jul 04 06:39:53 PM PDT 24
Finished Jul 04 06:40:05 PM PDT 24
Peak memory 217692 kb
Host smart-8a4193c0-7fbb-46f7-800b-a08584f2cd00
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423889126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
2423889126
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.255977823
Short name T85
Test name
Test status
Simulation time 7562590149 ps
CPU time 91.98 seconds
Started Jul 04 06:39:51 PM PDT 24
Finished Jul 04 06:41:23 PM PDT 24
Peak memory 283744 kb
Host smart-90ecef71-d5ad-4863-b026-8b6102cb5a8d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255977823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_state_failure.255977823
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.1861347031
Short name T727
Test name
Test status
Simulation time 1576105324 ps
CPU time 10.54 seconds
Started Jul 04 06:39:53 PM PDT 24
Finished Jul 04 06:40:03 PM PDT 24
Peak memory 247480 kb
Host smart-6821f3cf-5abb-4089-855b-0f30feb44c4a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861347031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.1861347031
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2987830798
Short name T295
Test name
Test status
Simulation time 231267624 ps
CPU time 3 seconds
Started Jul 04 06:39:53 PM PDT 24
Finished Jul 04 06:39:56 PM PDT 24
Peak memory 222332 kb
Host smart-73543004-f5e7-428d-a530-628b23d2762c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987830798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2987830798
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1674559791
Short name T179
Test name
Test status
Simulation time 1490395516 ps
CPU time 26.84 seconds
Started Jul 04 06:39:52 PM PDT 24
Finished Jul 04 06:40:19 PM PDT 24
Peak memory 215116 kb
Host smart-beae8d3e-1294-40ee-a21e-509e9a552489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674559791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1674559791
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.460201431
Short name T99
Test name
Test status
Simulation time 465575281 ps
CPU time 23.92 seconds
Started Jul 04 06:39:59 PM PDT 24
Finished Jul 04 06:40:23 PM PDT 24
Peak memory 269584 kb
Host smart-0ece14a6-5949-4300-99bf-eca52152c0fe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460201431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.460201431
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.121474710
Short name T522
Test name
Test status
Simulation time 406473878 ps
CPU time 13.29 seconds
Started Jul 04 06:39:51 PM PDT 24
Finished Jul 04 06:40:05 PM PDT 24
Peak memory 218808 kb
Host smart-dc5a64a1-a585-4e00-b15d-2e4da28ecf20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121474710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.121474710
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.4058273738
Short name T167
Test name
Test status
Simulation time 1072373091 ps
CPU time 13.48 seconds
Started Jul 04 06:40:06 PM PDT 24
Finished Jul 04 06:40:19 PM PDT 24
Peak memory 226056 kb
Host smart-4a0abf56-7978-4fb9-a779-701b6bd509df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058273738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.4058273738
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.3996121776
Short name T622
Test name
Test status
Simulation time 1189969122 ps
CPU time 10.63 seconds
Started Jul 04 06:39:59 PM PDT 24
Finished Jul 04 06:40:10 PM PDT 24
Peak memory 218252 kb
Host smart-561fdde9-e63e-41cd-946e-7e3952996405
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996121776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.3
996121776
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.2876514482
Short name T448
Test name
Test status
Simulation time 523889265 ps
CPU time 11.54 seconds
Started Jul 04 06:39:51 PM PDT 24
Finished Jul 04 06:40:02 PM PDT 24
Peak memory 226036 kb
Host smart-97fdbdd5-ed33-4a1c-a516-d99368746110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876514482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2876514482
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.1394418996
Short name T258
Test name
Test status
Simulation time 109486485 ps
CPU time 3.26 seconds
Started Jul 04 06:39:47 PM PDT 24
Finished Jul 04 06:39:51 PM PDT 24
Peak memory 216908 kb
Host smart-e2cf6d01-8984-44f9-8fda-df33f19d7acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394418996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1394418996
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.18788755
Short name T183
Test name
Test status
Simulation time 1090042243 ps
CPU time 33.24 seconds
Started Jul 04 06:39:45 PM PDT 24
Finished Jul 04 06:40:18 PM PDT 24
Peak memory 250992 kb
Host smart-80e2d264-21e3-430c-a070-5da65c76c971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18788755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.18788755
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.2545817554
Short name T685
Test name
Test status
Simulation time 64898150 ps
CPU time 7.17 seconds
Started Jul 04 06:39:51 PM PDT 24
Finished Jul 04 06:39:59 PM PDT 24
Peak memory 250996 kb
Host smart-d391ef43-6e72-4eac-a102-a65fcd52e8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545817554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2545817554
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.3242910218
Short name T161
Test name
Test status
Simulation time 9540031045 ps
CPU time 71.14 seconds
Started Jul 04 06:40:02 PM PDT 24
Finished Jul 04 06:41:13 PM PDT 24
Peak memory 272572 kb
Host smart-fe138c28-bba0-4c7e-8a2e-7a20969441d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242910218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.3242910218
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.2233212303
Short name T87
Test name
Test status
Simulation time 13028208816 ps
CPU time 594.93 seconds
Started Jul 04 06:40:00 PM PDT 24
Finished Jul 04 06:49:55 PM PDT 24
Peak memory 496936 kb
Host smart-67025be1-a523-49b6-9e9e-285dc7a8ec6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2233212303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.2233212303
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2262607943
Short name T580
Test name
Test status
Simulation time 49172215 ps
CPU time 0.91 seconds
Started Jul 04 06:39:45 PM PDT 24
Finished Jul 04 06:39:46 PM PDT 24
Peak memory 213012 kb
Host smart-78f9985b-a215-4b19-b351-58d4870fa7ee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262607943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.2262607943
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.2816404038
Short name T373
Test name
Test status
Simulation time 21800485 ps
CPU time 0.97 seconds
Started Jul 04 06:42:30 PM PDT 24
Finished Jul 04 06:42:31 PM PDT 24
Peak memory 208964 kb
Host smart-318709c4-df88-4291-aa6c-d1bdca722df5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816404038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2816404038
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.4219119516
Short name T690
Test name
Test status
Simulation time 1565189475 ps
CPU time 16.87 seconds
Started Jul 04 06:42:31 PM PDT 24
Finished Jul 04 06:42:48 PM PDT 24
Peak memory 226056 kb
Host smart-4fd47815-c7d4-4741-9785-535f668aa024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219119516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.4219119516
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.1408760602
Short name T693
Test name
Test status
Simulation time 277823650 ps
CPU time 6.92 seconds
Started Jul 04 06:42:30 PM PDT 24
Finished Jul 04 06:42:38 PM PDT 24
Peak memory 217280 kb
Host smart-c30eae14-b7a7-41e6-8b04-159c26edb8ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408760602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.1408760602
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2637097824
Short name T854
Test name
Test status
Simulation time 57271577 ps
CPU time 3.12 seconds
Started Jul 04 06:42:30 PM PDT 24
Finished Jul 04 06:42:33 PM PDT 24
Peak memory 218244 kb
Host smart-b5987017-190d-4632-a741-41698ced37f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637097824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2637097824
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.979608744
Short name T553
Test name
Test status
Simulation time 220010226 ps
CPU time 9.45 seconds
Started Jul 04 06:42:30 PM PDT 24
Finished Jul 04 06:42:40 PM PDT 24
Peak memory 226052 kb
Host smart-c508780c-dd5b-4840-860b-ee87c3b3d40f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979608744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.979608744
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.205829628
Short name T375
Test name
Test status
Simulation time 950700276 ps
CPU time 7.55 seconds
Started Jul 04 06:42:30 PM PDT 24
Finished Jul 04 06:42:37 PM PDT 24
Peak memory 226008 kb
Host smart-1fad7716-beaf-4686-b536-e7fb47484c74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205829628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_di
gest.205829628
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1681515023
Short name T615
Test name
Test status
Simulation time 586205803 ps
CPU time 10.63 seconds
Started Jul 04 06:42:34 PM PDT 24
Finished Jul 04 06:42:45 PM PDT 24
Peak memory 218236 kb
Host smart-a65d6f51-ff0a-4672-9fb0-4455fa70981a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681515023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1681515023
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.4268811384
Short name T338
Test name
Test status
Simulation time 379165133 ps
CPU time 6 seconds
Started Jul 04 06:42:30 PM PDT 24
Finished Jul 04 06:42:36 PM PDT 24
Peak memory 225972 kb
Host smart-84952bb3-a775-49c6-89a7-15707a7ec7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268811384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.4268811384
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.828078116
Short name T859
Test name
Test status
Simulation time 67808064 ps
CPU time 3.05 seconds
Started Jul 04 06:42:24 PM PDT 24
Finished Jul 04 06:42:28 PM PDT 24
Peak memory 214776 kb
Host smart-fe9cce69-b2d7-4cc6-8040-bcca4222179f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828078116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.828078116
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.2559155223
Short name T361
Test name
Test status
Simulation time 352695945 ps
CPU time 29.07 seconds
Started Jul 04 06:42:23 PM PDT 24
Finished Jul 04 06:42:52 PM PDT 24
Peak memory 250996 kb
Host smart-edd79832-300a-4590-ac90-635d3ec3a4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559155223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2559155223
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1473462874
Short name T147
Test name
Test status
Simulation time 555341134 ps
CPU time 9.09 seconds
Started Jul 04 06:42:30 PM PDT 24
Finished Jul 04 06:42:39 PM PDT 24
Peak memory 250840 kb
Host smart-c170dcff-a268-47ff-9550-27be04755acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473462874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1473462874
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3318664349
Short name T48
Test name
Test status
Simulation time 34193874145 ps
CPU time 276.54 seconds
Started Jul 04 06:42:31 PM PDT 24
Finished Jul 04 06:47:08 PM PDT 24
Peak memory 220400 kb
Host smart-1f2d281c-f5f4-46fb-ba6c-cbbb702bce4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318664349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3318664349
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.439237639
Short name T551
Test name
Test status
Simulation time 25424591 ps
CPU time 0.96 seconds
Started Jul 04 06:42:23 PM PDT 24
Finished Jul 04 06:42:24 PM PDT 24
Peak memory 213236 kb
Host smart-d2f59b86-8c86-4264-a65d-237e2c496631
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439237639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ct
rl_volatile_unlock_smoke.439237639
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.2020384323
Short name T247
Test name
Test status
Simulation time 35712460 ps
CPU time 0.98 seconds
Started Jul 04 06:42:40 PM PDT 24
Finished Jul 04 06:42:41 PM PDT 24
Peak memory 208960 kb
Host smart-5d526510-8b37-45ea-a95d-d399e1583d30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020384323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2020384323
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.2820411955
Short name T389
Test name
Test status
Simulation time 747073314 ps
CPU time 10.39 seconds
Started Jul 04 06:42:32 PM PDT 24
Finished Jul 04 06:42:42 PM PDT 24
Peak memory 225976 kb
Host smart-5b800236-4305-4eec-b189-e8d53b336279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820411955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.2820411955
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.1618285783
Short name T10
Test name
Test status
Simulation time 219670837 ps
CPU time 3 seconds
Started Jul 04 06:42:37 PM PDT 24
Finished Jul 04 06:42:40 PM PDT 24
Peak memory 217716 kb
Host smart-8d59ccb9-121d-400b-8444-325dd1b3ce4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618285783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.1618285783
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.1343819556
Short name T501
Test name
Test status
Simulation time 85636311 ps
CPU time 3.38 seconds
Started Jul 04 06:42:31 PM PDT 24
Finished Jul 04 06:42:34 PM PDT 24
Peak memory 218168 kb
Host smart-79fe526d-7eed-4864-b109-2385b50bd1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343819556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1343819556
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.514957831
Short name T800
Test name
Test status
Simulation time 569288651 ps
CPU time 11.19 seconds
Started Jul 04 06:42:39 PM PDT 24
Finished Jul 04 06:42:50 PM PDT 24
Peak memory 226020 kb
Host smart-54fb056e-8add-4d63-9b9a-0d0883ce406f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514957831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.514957831
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.722391424
Short name T681
Test name
Test status
Simulation time 283502447 ps
CPU time 13.09 seconds
Started Jul 04 06:42:38 PM PDT 24
Finished Jul 04 06:42:52 PM PDT 24
Peak memory 226032 kb
Host smart-d4e805b1-59e5-4b57-9473-67282cb15f70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722391424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_di
gest.722391424
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.667197852
Short name T494
Test name
Test status
Simulation time 1996956356 ps
CPU time 11.62 seconds
Started Jul 04 06:42:38 PM PDT 24
Finished Jul 04 06:42:50 PM PDT 24
Peak memory 218256 kb
Host smart-4676141f-39e9-4f5b-a521-65342a5988d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667197852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.667197852
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.878728573
Short name T665
Test name
Test status
Simulation time 616733125 ps
CPU time 9.53 seconds
Started Jul 04 06:42:39 PM PDT 24
Finished Jul 04 06:42:48 PM PDT 24
Peak memory 218328 kb
Host smart-b413bf28-05a5-43f8-90d2-ea74bb62ee7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878728573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.878728573
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.2909085821
Short name T56
Test name
Test status
Simulation time 130745725 ps
CPU time 2.8 seconds
Started Jul 04 06:42:31 PM PDT 24
Finished Jul 04 06:42:34 PM PDT 24
Peak memory 214740 kb
Host smart-9fa6e880-8e51-4033-913b-8572386397d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909085821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.2909085821
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.508298705
Short name T526
Test name
Test status
Simulation time 2055500890 ps
CPU time 30.74 seconds
Started Jul 04 06:42:30 PM PDT 24
Finished Jul 04 06:43:01 PM PDT 24
Peak memory 251112 kb
Host smart-e53d4e45-5696-4087-a33f-745a0a6e937c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508298705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.508298705
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.1918453068
Short name T314
Test name
Test status
Simulation time 279589861 ps
CPU time 3.67 seconds
Started Jul 04 06:42:34 PM PDT 24
Finished Jul 04 06:42:38 PM PDT 24
Peak memory 222216 kb
Host smart-0925a73f-39fe-42e9-b31d-f1997aa787da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918453068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1918453068
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.1778313133
Short name T850
Test name
Test status
Simulation time 4111887924 ps
CPU time 51.91 seconds
Started Jul 04 06:42:39 PM PDT 24
Finished Jul 04 06:43:31 PM PDT 24
Peak memory 250976 kb
Host smart-f723b69a-1a64-4a82-b4b5-c7837e9a27fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778313133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.1778313133
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1440307047
Short name T527
Test name
Test status
Simulation time 28025154 ps
CPU time 0.92 seconds
Started Jul 04 06:42:31 PM PDT 24
Finished Jul 04 06:42:32 PM PDT 24
Peak memory 211848 kb
Host smart-ab0f51b1-72f9-4eaf-a475-4f3e1d87558f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440307047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.1440307047
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.1452705569
Short name T388
Test name
Test status
Simulation time 139840521 ps
CPU time 0.89 seconds
Started Jul 04 06:42:46 PM PDT 24
Finished Jul 04 06:42:47 PM PDT 24
Peak memory 208964 kb
Host smart-ef012290-0365-445d-a9d9-89c141a5bba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452705569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1452705569
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.1420495282
Short name T424
Test name
Test status
Simulation time 732147141 ps
CPU time 15 seconds
Started Jul 04 06:42:38 PM PDT 24
Finished Jul 04 06:42:53 PM PDT 24
Peak memory 226000 kb
Host smart-f6b1e815-8edb-4acd-a43e-1e44f4979d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420495282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1420495282
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.291175875
Short name T766
Test name
Test status
Simulation time 6393095560 ps
CPU time 10.85 seconds
Started Jul 04 06:42:38 PM PDT 24
Finished Jul 04 06:42:49 PM PDT 24
Peak memory 217744 kb
Host smart-5f1461a6-9a20-43a2-b3be-73600a76cb15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291175875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.291175875
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.474517841
Short name T299
Test name
Test status
Simulation time 62221845 ps
CPU time 2.77 seconds
Started Jul 04 06:42:39 PM PDT 24
Finished Jul 04 06:42:42 PM PDT 24
Peak memory 218224 kb
Host smart-e15b8114-96a6-45fa-8127-9dc9e483eb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474517841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.474517841
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.3856884082
Short name T670
Test name
Test status
Simulation time 885790733 ps
CPU time 11.91 seconds
Started Jul 04 06:42:37 PM PDT 24
Finished Jul 04 06:42:49 PM PDT 24
Peak memory 218220 kb
Host smart-df561aa9-74ec-4701-9428-abd4badbb135
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856884082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.3856884082
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.4275230356
Short name T583
Test name
Test status
Simulation time 844900181 ps
CPU time 12.2 seconds
Started Jul 04 06:42:48 PM PDT 24
Finished Jul 04 06:43:01 PM PDT 24
Peak memory 226020 kb
Host smart-8286d0f1-b8ea-458d-8669-4e9863f4587b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275230356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.4275230356
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.1960326779
Short name T296
Test name
Test status
Simulation time 1296177286 ps
CPU time 10.91 seconds
Started Jul 04 06:42:39 PM PDT 24
Finished Jul 04 06:42:50 PM PDT 24
Peak memory 218216 kb
Host smart-81353da4-76b8-4d95-92c6-05b18f23ccac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960326779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
1960326779
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.3358846213
Short name T333
Test name
Test status
Simulation time 288661963 ps
CPU time 9.2 seconds
Started Jul 04 06:42:39 PM PDT 24
Finished Jul 04 06:42:48 PM PDT 24
Peak memory 226012 kb
Host smart-9366ee96-7460-4aff-a638-ba21283bbc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358846213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3358846213
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.3039134749
Short name T260
Test name
Test status
Simulation time 29632385 ps
CPU time 2.23 seconds
Started Jul 04 06:42:38 PM PDT 24
Finished Jul 04 06:42:40 PM PDT 24
Peak memory 214024 kb
Host smart-5d305aa9-c9f2-4822-89ae-2e05a65b15c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039134749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3039134749
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.3241777444
Short name T222
Test name
Test status
Simulation time 238846963 ps
CPU time 30.61 seconds
Started Jul 04 06:42:38 PM PDT 24
Finished Jul 04 06:43:09 PM PDT 24
Peak memory 250972 kb
Host smart-774f8bbf-6003-4eca-9142-60d83f6abc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241777444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.3241777444
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1626439026
Short name T643
Test name
Test status
Simulation time 178677947 ps
CPU time 7.7 seconds
Started Jul 04 06:42:44 PM PDT 24
Finished Jul 04 06:42:51 PM PDT 24
Peak memory 247156 kb
Host smart-a6f9b684-fe39-4c44-9d9b-d06560bff8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626439026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1626439026
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2234630402
Short name T67
Test name
Test status
Simulation time 4942931711 ps
CPU time 185.65 seconds
Started Jul 04 06:42:47 PM PDT 24
Finished Jul 04 06:45:53 PM PDT 24
Peak memory 283812 kb
Host smart-4fc3856e-390b-4baf-8ab9-6d2c8131d346
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234630402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2234630402
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.954201824
Short name T381
Test name
Test status
Simulation time 45089375 ps
CPU time 0.93 seconds
Started Jul 04 06:42:38 PM PDT 24
Finished Jul 04 06:42:40 PM PDT 24
Peak memory 213056 kb
Host smart-4bc9edcb-fd4b-4e6d-832f-7b78bbd1c2c0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954201824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct
rl_volatile_unlock_smoke.954201824
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1826435193
Short name T69
Test name
Test status
Simulation time 54952307 ps
CPU time 1.11 seconds
Started Jul 04 06:42:46 PM PDT 24
Finished Jul 04 06:42:47 PM PDT 24
Peak memory 208988 kb
Host smart-32cfd277-8138-4613-91fa-966d7d924767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826435193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1826435193
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.28100936
Short name T688
Test name
Test status
Simulation time 222213939 ps
CPU time 11.39 seconds
Started Jul 04 06:42:47 PM PDT 24
Finished Jul 04 06:42:59 PM PDT 24
Peak memory 226064 kb
Host smart-4cbaba33-1c18-491c-9ea2-7aefaaa901e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28100936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.28100936
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.349254549
Short name T336
Test name
Test status
Simulation time 104527885 ps
CPU time 1.3 seconds
Started Jul 04 06:42:48 PM PDT 24
Finished Jul 04 06:42:49 PM PDT 24
Peak memory 217076 kb
Host smart-a44d2dd4-3bd2-4710-a2d3-f84e7be09692
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349254549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.349254549
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.654860913
Short name T788
Test name
Test status
Simulation time 151769911 ps
CPU time 1.98 seconds
Started Jul 04 06:42:47 PM PDT 24
Finished Jul 04 06:42:49 PM PDT 24
Peak memory 218232 kb
Host smart-04dd4b05-e7db-47e3-af38-679400cda334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654860913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.654860913
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.3729190021
Short name T249
Test name
Test status
Simulation time 289577393 ps
CPU time 13.77 seconds
Started Jul 04 06:42:47 PM PDT 24
Finished Jul 04 06:43:01 PM PDT 24
Peak memory 225972 kb
Host smart-2a98199e-6bcc-4590-ba47-e14bb64ae8ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729190021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.3729190021
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1214678330
Short name T706
Test name
Test status
Simulation time 589115492 ps
CPU time 8.9 seconds
Started Jul 04 06:42:48 PM PDT 24
Finished Jul 04 06:42:57 PM PDT 24
Peak memory 226052 kb
Host smart-19d7979b-566e-45d1-ab55-dbdb5b9ab77b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214678330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.1214678330
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.47074200
Short name T655
Test name
Test status
Simulation time 951896661 ps
CPU time 7.33 seconds
Started Jul 04 06:42:49 PM PDT 24
Finished Jul 04 06:42:56 PM PDT 24
Peak memory 218224 kb
Host smart-9bb53763-f59c-418d-8fd3-383e97ead1f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47074200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.47074200
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.705266778
Short name T367
Test name
Test status
Simulation time 203178679 ps
CPU time 6.49 seconds
Started Jul 04 06:42:48 PM PDT 24
Finished Jul 04 06:42:54 PM PDT 24
Peak memory 218208 kb
Host smart-9743708d-0c39-47b2-8f18-e8abfb00c083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705266778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.705266778
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1166875283
Short name T74
Test name
Test status
Simulation time 126029531 ps
CPU time 4.45 seconds
Started Jul 04 06:42:48 PM PDT 24
Finished Jul 04 06:42:52 PM PDT 24
Peak memory 217740 kb
Host smart-7dcf85dc-b90c-4b78-9c17-7f2d934a3054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166875283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1166875283
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.228013443
Short name T293
Test name
Test status
Simulation time 1249068741 ps
CPU time 28 seconds
Started Jul 04 06:42:46 PM PDT 24
Finished Jul 04 06:43:14 PM PDT 24
Peak memory 250916 kb
Host smart-c48b7e27-b164-4cad-b435-c1ab4e200d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228013443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.228013443
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.620804767
Short name T659
Test name
Test status
Simulation time 503906384 ps
CPU time 8.32 seconds
Started Jul 04 06:42:47 PM PDT 24
Finished Jul 04 06:42:55 PM PDT 24
Peak memory 250964 kb
Host smart-bfbdd848-449c-4e63-8531-ee4bcec0ad3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620804767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.620804767
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.4097462838
Short name T816
Test name
Test status
Simulation time 117223716708 ps
CPU time 568.24 seconds
Started Jul 04 06:42:46 PM PDT 24
Finished Jul 04 06:52:15 PM PDT 24
Peak memory 373156 kb
Host smart-09487ea7-087c-43b6-9c0e-16045eea4fda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4097462838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.4097462838
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.4145761835
Short name T771
Test name
Test status
Simulation time 13266786 ps
CPU time 0.9 seconds
Started Jul 04 06:42:45 PM PDT 24
Finished Jul 04 06:42:46 PM PDT 24
Peak memory 211844 kb
Host smart-e4fe6f3e-6ee5-4eda-a753-db5a7df0a084
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145761835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.4145761835
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.1331535588
Short name T575
Test name
Test status
Simulation time 19040723 ps
CPU time 0.97 seconds
Started Jul 04 06:42:58 PM PDT 24
Finished Jul 04 06:42:59 PM PDT 24
Peak memory 208888 kb
Host smart-5ad25172-4182-4b32-b8dc-151da296098f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331535588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1331535588
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1452316692
Short name T254
Test name
Test status
Simulation time 1114173457 ps
CPU time 15.17 seconds
Started Jul 04 06:42:47 PM PDT 24
Finished Jul 04 06:43:03 PM PDT 24
Peak memory 218236 kb
Host smart-f56629b0-e6c3-4511-9925-a72403afb185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452316692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1452316692
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.2326715631
Short name T664
Test name
Test status
Simulation time 449511164 ps
CPU time 11.52 seconds
Started Jul 04 06:42:46 PM PDT 24
Finished Jul 04 06:42:58 PM PDT 24
Peak memory 217136 kb
Host smart-7d05bc7d-4ee7-4cd8-9454-076c85315444
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326715631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.2326715631
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1974171594
Short name T621
Test name
Test status
Simulation time 54889958 ps
CPU time 3.08 seconds
Started Jul 04 06:42:47 PM PDT 24
Finished Jul 04 06:42:50 PM PDT 24
Peak memory 222280 kb
Host smart-7ea66976-7ebb-42e6-822a-3d1d5e819dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974171594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1974171594
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.1739767099
Short name T507
Test name
Test status
Simulation time 688602745 ps
CPU time 17.21 seconds
Started Jul 04 06:42:50 PM PDT 24
Finished Jul 04 06:43:08 PM PDT 24
Peak memory 226044 kb
Host smart-83258f84-df15-4ade-a9d6-f9538427a309
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739767099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.1739767099
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.4088519400
Short name T187
Test name
Test status
Simulation time 2124203335 ps
CPU time 15.15 seconds
Started Jul 04 06:42:57 PM PDT 24
Finished Jul 04 06:43:13 PM PDT 24
Peak memory 226016 kb
Host smart-b78f9fb4-a9d9-4670-aa8f-3bb48ca0de58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088519400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.4088519400
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.849970422
Short name T840
Test name
Test status
Simulation time 1625282757 ps
CPU time 14.37 seconds
Started Jul 04 06:42:59 PM PDT 24
Finished Jul 04 06:43:13 PM PDT 24
Peak memory 218228 kb
Host smart-721ba6f3-ef4e-4b2a-8aee-5342f9813de4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849970422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.849970422
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3142474231
Short name T642
Test name
Test status
Simulation time 562952488 ps
CPU time 10.97 seconds
Started Jul 04 06:42:50 PM PDT 24
Finished Jul 04 06:43:01 PM PDT 24
Peak memory 226040 kb
Host smart-83ae328c-9fe3-4cef-b289-b348fc9ea22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142474231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3142474231
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.1124036432
Short name T378
Test name
Test status
Simulation time 28020826 ps
CPU time 1.36 seconds
Started Jul 04 06:42:47 PM PDT 24
Finished Jul 04 06:42:49 PM PDT 24
Peak memory 217692 kb
Host smart-61938e93-63ef-499f-8eb6-e7fe41a648cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124036432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1124036432
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.4224556602
Short name T836
Test name
Test status
Simulation time 405547359 ps
CPU time 22.7 seconds
Started Jul 04 06:42:47 PM PDT 24
Finished Jul 04 06:43:10 PM PDT 24
Peak memory 250960 kb
Host smart-a1d1b6f7-82cd-436b-842d-0720ddbecaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224556602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.4224556602
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.1218830512
Short name T676
Test name
Test status
Simulation time 451732891 ps
CPU time 7.56 seconds
Started Jul 04 06:42:47 PM PDT 24
Finished Jul 04 06:42:55 PM PDT 24
Peak memory 250976 kb
Host smart-ce3835f6-c1f7-4ddc-bcb1-5b16df0bf2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218830512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1218830512
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3948933787
Short name T833
Test name
Test status
Simulation time 19714728 ps
CPU time 0.91 seconds
Started Jul 04 06:42:47 PM PDT 24
Finished Jul 04 06:42:48 PM PDT 24
Peak memory 211876 kb
Host smart-3f82b04c-40e0-484d-986b-3c23fd151107
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948933787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3948933787
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.296494929
Short name T347
Test name
Test status
Simulation time 38351123 ps
CPU time 0.95 seconds
Started Jul 04 06:42:57 PM PDT 24
Finished Jul 04 06:42:58 PM PDT 24
Peak memory 208972 kb
Host smart-d24d9b0a-53dc-4508-a736-6e97b55070f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296494929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.296494929
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.3167679961
Short name T466
Test name
Test status
Simulation time 1122534364 ps
CPU time 9.94 seconds
Started Jul 04 06:42:59 PM PDT 24
Finished Jul 04 06:43:09 PM PDT 24
Peak memory 226076 kb
Host smart-d88b2ea5-1cab-4bc4-bb84-8dd3a4f3005b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167679961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3167679961
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.2140974787
Short name T195
Test name
Test status
Simulation time 1471283385 ps
CPU time 10.6 seconds
Started Jul 04 06:42:58 PM PDT 24
Finished Jul 04 06:43:09 PM PDT 24
Peak memory 217736 kb
Host smart-d3ff4650-9810-4ba9-bf4b-6a924f393c14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140974787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.2140974787
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.2822723186
Short name T826
Test name
Test status
Simulation time 102518986 ps
CPU time 2.66 seconds
Started Jul 04 06:42:59 PM PDT 24
Finished Jul 04 06:43:01 PM PDT 24
Peak memory 222532 kb
Host smart-3d98b709-529b-40e9-8058-3d8c1bac9acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822723186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2822723186
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.3213175918
Short name T371
Test name
Test status
Simulation time 1404386203 ps
CPU time 13.38 seconds
Started Jul 04 06:42:57 PM PDT 24
Finished Jul 04 06:43:10 PM PDT 24
Peak memory 226032 kb
Host smart-0e38458a-ff4f-4808-8652-fc221a6eeeb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213175918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.3213175918
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2002043404
Short name T532
Test name
Test status
Simulation time 818041924 ps
CPU time 17.99 seconds
Started Jul 04 06:42:57 PM PDT 24
Finished Jul 04 06:43:15 PM PDT 24
Peak memory 226056 kb
Host smart-31090d05-d33c-4743-9234-ab6852925548
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002043404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2002043404
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1037400956
Short name T758
Test name
Test status
Simulation time 3118740091 ps
CPU time 13.96 seconds
Started Jul 04 06:42:56 PM PDT 24
Finished Jul 04 06:43:11 PM PDT 24
Peak memory 226112 kb
Host smart-92a4b2e4-c603-4cad-ad82-3602e8bf9689
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037400956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1037400956
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1321603762
Short name T732
Test name
Test status
Simulation time 2745241189 ps
CPU time 7.43 seconds
Started Jul 04 06:42:57 PM PDT 24
Finished Jul 04 06:43:04 PM PDT 24
Peak memory 218436 kb
Host smart-44f3d152-d993-44f5-a42e-9de411d99bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321603762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1321603762
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3443948809
Short name T370
Test name
Test status
Simulation time 160119219 ps
CPU time 1.35 seconds
Started Jul 04 06:42:57 PM PDT 24
Finished Jul 04 06:42:58 PM PDT 24
Peak memory 213860 kb
Host smart-a63dee84-735d-44d9-ae17-2962c866bc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443948809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3443948809
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.4292174115
Short name T741
Test name
Test status
Simulation time 1000140372 ps
CPU time 21.4 seconds
Started Jul 04 06:42:59 PM PDT 24
Finished Jul 04 06:43:20 PM PDT 24
Peak memory 250920 kb
Host smart-b7ba5b6d-52b5-4869-ab3e-28dab8fb5859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292174115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.4292174115
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.1047305642
Short name T520
Test name
Test status
Simulation time 101418506 ps
CPU time 8.3 seconds
Started Jul 04 06:42:57 PM PDT 24
Finished Jul 04 06:43:06 PM PDT 24
Peak memory 250940 kb
Host smart-ec5e03a2-5e1c-42e0-af69-31f0906c39c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047305642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.1047305642
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.1126577029
Short name T248
Test name
Test status
Simulation time 24704927192 ps
CPU time 79.25 seconds
Started Jul 04 06:42:56 PM PDT 24
Finished Jul 04 06:44:15 PM PDT 24
Peak memory 267428 kb
Host smart-f700bd91-dd20-465e-bb5d-681b11b339a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126577029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.1126577029
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3896609963
Short name T245
Test name
Test status
Simulation time 22164960 ps
CPU time 0.83 seconds
Started Jul 04 06:42:57 PM PDT 24
Finished Jul 04 06:42:58 PM PDT 24
Peak memory 217720 kb
Host smart-bbb52569-8055-4e26-aab8-a2aab46886a1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896609963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.3896609963
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1475196339
Short name T406
Test name
Test status
Simulation time 79540584 ps
CPU time 0.93 seconds
Started Jul 04 06:43:07 PM PDT 24
Finished Jul 04 06:43:08 PM PDT 24
Peak memory 209028 kb
Host smart-27ae44e5-d382-48b0-afb4-3d3d87ed0797
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475196339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1475196339
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.3746695592
Short name T475
Test name
Test status
Simulation time 424118654 ps
CPU time 17.43 seconds
Started Jul 04 06:43:07 PM PDT 24
Finished Jul 04 06:43:24 PM PDT 24
Peak memory 226040 kb
Host smart-dc5f27ee-fd47-4579-9ce2-f8ba22eea32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746695592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3746695592
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1945255859
Short name T485
Test name
Test status
Simulation time 8347246431 ps
CPU time 17.58 seconds
Started Jul 04 06:43:05 PM PDT 24
Finished Jul 04 06:43:23 PM PDT 24
Peak memory 217848 kb
Host smart-6a18011e-89e3-440e-ab12-9ddbf2bb5f19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945255859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1945255859
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.940296631
Short name T714
Test name
Test status
Simulation time 64520381 ps
CPU time 2.98 seconds
Started Jul 04 06:43:07 PM PDT 24
Finished Jul 04 06:43:10 PM PDT 24
Peak memory 222580 kb
Host smart-d425c7fd-30bf-4665-9853-ce052db3350f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940296631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.940296631
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.159611887
Short name T368
Test name
Test status
Simulation time 972504152 ps
CPU time 14.79 seconds
Started Jul 04 06:43:07 PM PDT 24
Finished Jul 04 06:43:22 PM PDT 24
Peak memory 226024 kb
Host smart-a2953b05-90c7-4eeb-875e-eb44de75a4f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159611887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.159611887
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2438416801
Short name T243
Test name
Test status
Simulation time 357367330 ps
CPU time 10.08 seconds
Started Jul 04 06:43:06 PM PDT 24
Finished Jul 04 06:43:16 PM PDT 24
Peak memory 226020 kb
Host smart-c7fa1f17-67e2-4a79-ba13-bb6db0b324b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438416801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.2438416801
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.606411164
Short name T278
Test name
Test status
Simulation time 730494589 ps
CPU time 6.06 seconds
Started Jul 04 06:43:07 PM PDT 24
Finished Jul 04 06:43:14 PM PDT 24
Peak memory 218332 kb
Host smart-c75ac920-6395-493e-98f6-02e64ea797d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606411164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.606411164
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3586414073
Short name T635
Test name
Test status
Simulation time 2922589090 ps
CPU time 9.09 seconds
Started Jul 04 06:43:05 PM PDT 24
Finished Jul 04 06:43:15 PM PDT 24
Peak memory 225060 kb
Host smart-22417c12-afdc-493d-9278-6fcffe53d865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586414073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3586414073
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.4241590966
Short name T579
Test name
Test status
Simulation time 27737604 ps
CPU time 1.19 seconds
Started Jul 04 06:43:04 PM PDT 24
Finished Jul 04 06:43:06 PM PDT 24
Peak memory 217864 kb
Host smart-c3ae92a6-aa94-48fb-ac9f-4b6c7067df38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241590966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.4241590966
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3025126953
Short name T707
Test name
Test status
Simulation time 298951682 ps
CPU time 22.82 seconds
Started Jul 04 06:43:07 PM PDT 24
Finished Jul 04 06:43:30 PM PDT 24
Peak memory 251104 kb
Host smart-a0af15f9-9517-46e2-929b-fcc5e2781521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025126953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3025126953
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.2252823135
Short name T269
Test name
Test status
Simulation time 118293241 ps
CPU time 6.79 seconds
Started Jul 04 06:43:07 PM PDT 24
Finished Jul 04 06:43:14 PM PDT 24
Peak memory 242868 kb
Host smart-1a75410b-2cd4-4c28-be43-82474f3cf1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252823135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.2252823135
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1312167102
Short name T463
Test name
Test status
Simulation time 14279297404 ps
CPU time 140.67 seconds
Started Jul 04 06:43:06 PM PDT 24
Finished Jul 04 06:45:27 PM PDT 24
Peak memory 267432 kb
Host smart-ea910bfc-ac9d-4ff2-9e96-06c7a0121146
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312167102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1312167102
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.3139407761
Short name T141
Test name
Test status
Simulation time 137993480250 ps
CPU time 552.12 seconds
Started Jul 04 06:43:05 PM PDT 24
Finished Jul 04 06:52:17 PM PDT 24
Peak memory 421996 kb
Host smart-c3f3b8e5-f05e-4ada-9636-a57a99355dc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3139407761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.3139407761
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1108962106
Short name T835
Test name
Test status
Simulation time 100504395 ps
CPU time 1.11 seconds
Started Jul 04 06:43:06 PM PDT 24
Finished Jul 04 06:43:08 PM PDT 24
Peak memory 217856 kb
Host smart-9b2572b2-8514-405b-9821-9013517f8208
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108962106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1108962106
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.1297577346
Short name T433
Test name
Test status
Simulation time 15767200 ps
CPU time 0.88 seconds
Started Jul 04 06:43:11 PM PDT 24
Finished Jul 04 06:43:12 PM PDT 24
Peak memory 208948 kb
Host smart-215c81fa-ebdd-473f-b22c-a5a6b2002765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297577346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.1297577346
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.2900095287
Short name T268
Test name
Test status
Simulation time 2741656029 ps
CPU time 14.19 seconds
Started Jul 04 06:43:08 PM PDT 24
Finished Jul 04 06:43:22 PM PDT 24
Peak memory 218980 kb
Host smart-7e5d6b4b-54df-4562-a85e-8d44448373e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900095287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2900095287
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.16237630
Short name T443
Test name
Test status
Simulation time 1957418766 ps
CPU time 5.66 seconds
Started Jul 04 06:43:05 PM PDT 24
Finished Jul 04 06:43:10 PM PDT 24
Peak memory 217396 kb
Host smart-552c4cee-7094-4502-8594-0c5fd859d839
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16237630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.16237630
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.740636426
Short name T516
Test name
Test status
Simulation time 44769488 ps
CPU time 1.83 seconds
Started Jul 04 06:43:07 PM PDT 24
Finished Jul 04 06:43:09 PM PDT 24
Peak memory 218228 kb
Host smart-64d594c7-bf24-4ddc-83b7-1cb614b19116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740636426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.740636426
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1972912531
Short name T634
Test name
Test status
Simulation time 633340440 ps
CPU time 11.26 seconds
Started Jul 04 06:43:13 PM PDT 24
Finished Jul 04 06:43:25 PM PDT 24
Peak memory 218196 kb
Host smart-5291b5c4-c6bb-4c69-9cca-749eafea9ced
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972912531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1972912531
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.3944054130
Short name T398
Test name
Test status
Simulation time 603862137 ps
CPU time 11.85 seconds
Started Jul 04 06:43:05 PM PDT 24
Finished Jul 04 06:43:17 PM PDT 24
Peak memory 218280 kb
Host smart-43dfab86-0d06-4154-8fa1-381ab962775f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944054130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3944054130
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3486922870
Short name T625
Test name
Test status
Simulation time 41687752 ps
CPU time 1.12 seconds
Started Jul 04 06:43:06 PM PDT 24
Finished Jul 04 06:43:07 PM PDT 24
Peak memory 217836 kb
Host smart-de534ec5-05b8-4834-b03f-8248e735ed2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486922870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3486922870
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.2129108258
Short name T733
Test name
Test status
Simulation time 1141404133 ps
CPU time 22.44 seconds
Started Jul 04 06:43:05 PM PDT 24
Finished Jul 04 06:43:28 PM PDT 24
Peak memory 250960 kb
Host smart-240ad438-2b42-4c59-bd9f-5e247a1dcf94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129108258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2129108258
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3226023714
Short name T834
Test name
Test status
Simulation time 217585254 ps
CPU time 8.38 seconds
Started Jul 04 06:43:06 PM PDT 24
Finished Jul 04 06:43:14 PM PDT 24
Peak memory 250904 kb
Host smart-ae457103-31ae-4fc1-a70b-a51d15fac30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226023714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3226023714
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.2990333094
Short name T431
Test name
Test status
Simulation time 8650746887 ps
CPU time 289.45 seconds
Started Jul 04 06:43:12 PM PDT 24
Finished Jul 04 06:48:02 PM PDT 24
Peak memory 252568 kb
Host smart-0ab5369a-3d7c-4a9a-b71f-877e8457b42f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990333094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.2990333094
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.4009251364
Short name T691
Test name
Test status
Simulation time 25145721 ps
CPU time 0.97 seconds
Started Jul 04 06:43:06 PM PDT 24
Finished Jul 04 06:43:07 PM PDT 24
Peak memory 213108 kb
Host smart-bbfc16cc-e4f2-4f24-aa70-7e6f3f66e376
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009251364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.4009251364
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.4191394697
Short name T776
Test name
Test status
Simulation time 148233576 ps
CPU time 0.92 seconds
Started Jul 04 06:43:22 PM PDT 24
Finished Jul 04 06:43:23 PM PDT 24
Peak memory 208936 kb
Host smart-bd2299ce-701e-4659-9e2a-964d55887084
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191394697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.4191394697
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3732395760
Short name T559
Test name
Test status
Simulation time 1746089301 ps
CPU time 9.85 seconds
Started Jul 04 06:43:14 PM PDT 24
Finished Jul 04 06:43:24 PM PDT 24
Peak memory 218168 kb
Host smart-c2352b54-626f-44bd-8dab-53e57861d31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732395760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3732395760
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.3881562337
Short name T703
Test name
Test status
Simulation time 39489537 ps
CPU time 2.56 seconds
Started Jul 04 06:43:13 PM PDT 24
Finished Jul 04 06:43:16 PM PDT 24
Peak memory 218152 kb
Host smart-1bcddc01-cabf-4cb6-8d3c-29fec0e8485b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881562337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3881562337
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.575707500
Short name T292
Test name
Test status
Simulation time 1589431761 ps
CPU time 18.02 seconds
Started Jul 04 06:43:13 PM PDT 24
Finished Jul 04 06:43:31 PM PDT 24
Peak memory 218888 kb
Host smart-b90482c4-67c5-4911-bac2-9b8d5dbbbb41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575707500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.575707500
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2126841450
Short name T827
Test name
Test status
Simulation time 4070352820 ps
CPU time 21.02 seconds
Started Jul 04 06:43:20 PM PDT 24
Finished Jul 04 06:43:41 PM PDT 24
Peak memory 226136 kb
Host smart-2799d9d5-1112-4579-b61d-fb86c3fefb35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126841450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.2126841450
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.604635918
Short name T438
Test name
Test status
Simulation time 657308746 ps
CPU time 7.46 seconds
Started Jul 04 06:43:12 PM PDT 24
Finished Jul 04 06:43:20 PM PDT 24
Peak memory 226036 kb
Host smart-ecaf26c3-0d34-4730-8e38-ea91cb5b4ac0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604635918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.604635918
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2725679963
Short name T382
Test name
Test status
Simulation time 215699168 ps
CPU time 8.91 seconds
Started Jul 04 06:43:13 PM PDT 24
Finished Jul 04 06:43:22 PM PDT 24
Peak memory 218316 kb
Host smart-b0eba2f6-a9bd-43d7-a6c8-0eee0fdb224e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725679963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2725679963
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.4122890573
Short name T791
Test name
Test status
Simulation time 230340124 ps
CPU time 3.35 seconds
Started Jul 04 06:43:11 PM PDT 24
Finished Jul 04 06:43:14 PM PDT 24
Peak memory 214624 kb
Host smart-a2995591-58fa-4e85-afdf-f453b944023f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122890573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.4122890573
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.3496215429
Short name T294
Test name
Test status
Simulation time 192993003 ps
CPU time 20.96 seconds
Started Jul 04 06:43:14 PM PDT 24
Finished Jul 04 06:43:36 PM PDT 24
Peak memory 250992 kb
Host smart-1cb1688f-cae8-4d2a-a45a-482b8755bdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496215429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3496215429
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.3583524074
Short name T467
Test name
Test status
Simulation time 116132172 ps
CPU time 12.16 seconds
Started Jul 04 06:43:13 PM PDT 24
Finished Jul 04 06:43:26 PM PDT 24
Peak memory 250960 kb
Host smart-4cf6f0fd-bdfe-4f7f-93e7-6e0a41549814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583524074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3583524074
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.528681527
Short name T436
Test name
Test status
Simulation time 11168804501 ps
CPU time 127.44 seconds
Started Jul 04 06:43:20 PM PDT 24
Finished Jul 04 06:45:28 PM PDT 24
Peak memory 270580 kb
Host smart-05f1c5e9-f381-4987-b29f-7d098ea7bea8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528681527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.528681527
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3466855686
Short name T680
Test name
Test status
Simulation time 13568262 ps
CPU time 1.05 seconds
Started Jul 04 06:43:12 PM PDT 24
Finished Jul 04 06:43:13 PM PDT 24
Peak memory 211892 kb
Host smart-aa54b326-7859-46b0-9db3-1c68b6655f5d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466855686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3466855686
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.1731018654
Short name T561
Test name
Test status
Simulation time 18005459 ps
CPU time 0.89 seconds
Started Jul 04 06:43:19 PM PDT 24
Finished Jul 04 06:43:21 PM PDT 24
Peak memory 208980 kb
Host smart-ab84adf7-59d9-494e-9c17-d4c8f94b54ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731018654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.1731018654
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.4089287942
Short name T250
Test name
Test status
Simulation time 335841136 ps
CPU time 15.16 seconds
Started Jul 04 06:43:20 PM PDT 24
Finished Jul 04 06:43:36 PM PDT 24
Peak memory 226036 kb
Host smart-192a0dcd-1aa1-4e83-b297-bfd37e2f1b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089287942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.4089287942
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.4171772121
Short name T427
Test name
Test status
Simulation time 404033334 ps
CPU time 5.68 seconds
Started Jul 04 06:43:19 PM PDT 24
Finished Jul 04 06:43:24 PM PDT 24
Peak memory 217268 kb
Host smart-42c027f4-6430-42d8-b6b4-bc676319901e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171772121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.4171772121
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.1153397147
Short name T533
Test name
Test status
Simulation time 23801936 ps
CPU time 1.5 seconds
Started Jul 04 06:43:20 PM PDT 24
Finished Jul 04 06:43:21 PM PDT 24
Peak memory 218228 kb
Host smart-fce31c5d-01ca-42a9-a2d3-b6171bc9acfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153397147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1153397147
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.1916131178
Short name T768
Test name
Test status
Simulation time 899699006 ps
CPU time 12.38 seconds
Started Jul 04 06:43:20 PM PDT 24
Finished Jul 04 06:43:33 PM PDT 24
Peak memory 225996 kb
Host smart-d08cd7fd-cb3c-4da6-9c37-6c7d4857e5ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916131178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1916131178
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2171660187
Short name T227
Test name
Test status
Simulation time 486376815 ps
CPU time 9.37 seconds
Started Jul 04 06:43:22 PM PDT 24
Finished Jul 04 06:43:31 PM PDT 24
Peak memory 226060 kb
Host smart-f5ace299-454c-490a-97ce-5b4329a18175
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171660187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.2171660187
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.378511029
Short name T849
Test name
Test status
Simulation time 2754503712 ps
CPU time 18.3 seconds
Started Jul 04 06:43:21 PM PDT 24
Finished Jul 04 06:43:40 PM PDT 24
Peak memory 218312 kb
Host smart-c92d6c2b-c7e6-411b-b1d9-eb0c51f00689
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378511029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.378511029
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.4086791864
Short name T307
Test name
Test status
Simulation time 286996386 ps
CPU time 7.62 seconds
Started Jul 04 06:43:20 PM PDT 24
Finished Jul 04 06:43:28 PM PDT 24
Peak memory 218296 kb
Host smart-67d872d4-6de9-4928-99f1-f85496ec0e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086791864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.4086791864
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.88664305
Short name T104
Test name
Test status
Simulation time 150735062 ps
CPU time 3.8 seconds
Started Jul 04 06:43:21 PM PDT 24
Finished Jul 04 06:43:25 PM PDT 24
Peak memory 214824 kb
Host smart-5c64db14-d3e1-42e8-9a8d-8efb9e130bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88664305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.88664305
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.1209019121
Short name T324
Test name
Test status
Simulation time 469515093 ps
CPU time 32.7 seconds
Started Jul 04 06:43:24 PM PDT 24
Finished Jul 04 06:43:57 PM PDT 24
Peak memory 250976 kb
Host smart-501a471e-e97b-4585-aa2f-b3b5369da3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209019121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1209019121
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.1187784089
Short name T188
Test name
Test status
Simulation time 259481895 ps
CPU time 6.74 seconds
Started Jul 04 06:43:20 PM PDT 24
Finished Jul 04 06:43:27 PM PDT 24
Peak memory 250564 kb
Host smart-96cb5097-fbc3-4980-81ec-89783119bad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187784089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1187784089
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1350749621
Short name T334
Test name
Test status
Simulation time 2271282354 ps
CPU time 44.43 seconds
Started Jul 04 06:43:19 PM PDT 24
Finished Jul 04 06:44:04 PM PDT 24
Peak memory 250768 kb
Host smart-d8f80967-81f8-419b-a47d-3832c4a5d1c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350749621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1350749621
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2078317234
Short name T57
Test name
Test status
Simulation time 15554943 ps
CPU time 0.88 seconds
Started Jul 04 06:43:19 PM PDT 24
Finished Jul 04 06:43:20 PM PDT 24
Peak memory 211860 kb
Host smart-bd4ff95e-6bbf-4fab-b41f-1f2b08b0eeee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078317234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.2078317234
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.4217996417
Short name T71
Test name
Test status
Simulation time 18672046 ps
CPU time 1.16 seconds
Started Jul 04 06:40:15 PM PDT 24
Finished Jul 04 06:40:17 PM PDT 24
Peak memory 208960 kb
Host smart-758d72d5-8e13-4176-87ac-f9cdcaf55881
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217996417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.4217996417
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.3498644686
Short name T784
Test name
Test status
Simulation time 484491939 ps
CPU time 9.4 seconds
Started Jul 04 06:39:58 PM PDT 24
Finished Jul 04 06:40:08 PM PDT 24
Peak memory 218328 kb
Host smart-84246610-000b-4f74-a51d-3cdd31537f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498644686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3498644686
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.2115632409
Short name T96
Test name
Test status
Simulation time 251809903 ps
CPU time 1.36 seconds
Started Jul 04 06:40:05 PM PDT 24
Finished Jul 04 06:40:06 PM PDT 24
Peak memory 216952 kb
Host smart-92f4f2b1-2180-4dab-a1c3-329cef882bc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115632409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.2115632409
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.205100526
Short name T238
Test name
Test status
Simulation time 1595095891 ps
CPU time 31.65 seconds
Started Jul 04 06:40:05 PM PDT 24
Finished Jul 04 06:40:37 PM PDT 24
Peak memory 218256 kb
Host smart-c70fb188-96ac-437c-b643-b09d81ab749f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205100526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_err
ors.205100526
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.2180739133
Short name T62
Test name
Test status
Simulation time 3023281131 ps
CPU time 17.47 seconds
Started Jul 04 06:40:05 PM PDT 24
Finished Jul 04 06:40:23 PM PDT 24
Peak memory 217976 kb
Host smart-de197469-b5e7-402e-981f-23a44673abdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180739133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.2
180739133
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.2025085545
Short name T362
Test name
Test status
Simulation time 1607278854 ps
CPU time 21.66 seconds
Started Jul 04 06:40:06 PM PDT 24
Finished Jul 04 06:40:28 PM PDT 24
Peak memory 218272 kb
Host smart-bca573ac-af18-47df-9a24-279fdf6a0fcb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025085545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.2025085545
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2694530944
Short name T392
Test name
Test status
Simulation time 2739213350 ps
CPU time 11.6 seconds
Started Jul 04 06:40:07 PM PDT 24
Finished Jul 04 06:40:18 PM PDT 24
Peak memory 217796 kb
Host smart-adf3941d-9f9c-46de-ac1b-f4f9c191883a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694530944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2694530944
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.3720377817
Short name T284
Test name
Test status
Simulation time 199660944 ps
CPU time 6.79 seconds
Started Jul 04 06:40:00 PM PDT 24
Finished Jul 04 06:40:07 PM PDT 24
Peak memory 217700 kb
Host smart-1dc59002-a467-4a8a-afd9-ee747fba1bfb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720377817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
3720377817
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2915529998
Short name T636
Test name
Test status
Simulation time 954112071 ps
CPU time 45.01 seconds
Started Jul 04 06:40:03 PM PDT 24
Finished Jul 04 06:40:48 PM PDT 24
Peak memory 251016 kb
Host smart-79d34ab8-aaf4-4183-8c3e-04f541b8162a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915529998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2915529998
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.3267845794
Short name T598
Test name
Test status
Simulation time 643045500 ps
CPU time 6.75 seconds
Started Jul 04 06:39:59 PM PDT 24
Finished Jul 04 06:40:06 PM PDT 24
Peak memory 223584 kb
Host smart-ad6c654e-cbdc-4220-9cc2-48a2a79ec442
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267845794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.3267845794
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.4131072409
Short name T383
Test name
Test status
Simulation time 177965041 ps
CPU time 4.47 seconds
Started Jul 04 06:40:06 PM PDT 24
Finished Jul 04 06:40:10 PM PDT 24
Peak memory 218256 kb
Host smart-a360fdb2-99fc-4947-adb0-b124637120e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131072409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.4131072409
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.651636468
Short name T760
Test name
Test status
Simulation time 945436102 ps
CPU time 8.99 seconds
Started Jul 04 06:39:59 PM PDT 24
Finished Jul 04 06:40:08 PM PDT 24
Peak memory 217752 kb
Host smart-3ffa9838-0cfd-45f8-8747-ddf374941b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651636468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.651636468
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1801089987
Short name T47
Test name
Test status
Simulation time 283006544 ps
CPU time 36.33 seconds
Started Jul 04 06:40:05 PM PDT 24
Finished Jul 04 06:40:42 PM PDT 24
Peak memory 282476 kb
Host smart-22be7fae-2ce3-45b8-81f1-4af557016548
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801089987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1801089987
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.1811618564
Short name T787
Test name
Test status
Simulation time 3271893767 ps
CPU time 18.97 seconds
Started Jul 04 06:40:04 PM PDT 24
Finished Jul 04 06:40:23 PM PDT 24
Peak memory 226076 kb
Host smart-8b5650f9-0bb8-42b8-aed0-8526d4f2bc75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811618564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1811618564
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2805627503
Short name T385
Test name
Test status
Simulation time 928956981 ps
CPU time 8.14 seconds
Started Jul 04 06:40:04 PM PDT 24
Finished Jul 04 06:40:13 PM PDT 24
Peak memory 226024 kb
Host smart-d330a784-16a2-41f7-b777-50dde7097437
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805627503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2805627503
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.362533469
Short name T815
Test name
Test status
Simulation time 841570894 ps
CPU time 10.18 seconds
Started Jul 04 06:40:06 PM PDT 24
Finished Jul 04 06:40:16 PM PDT 24
Peak memory 226052 kb
Host smart-4b03b74d-02df-4810-acd0-d991cda649a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362533469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.362533469
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.4271402303
Short name T735
Test name
Test status
Simulation time 238253869 ps
CPU time 9.52 seconds
Started Jul 04 06:40:00 PM PDT 24
Finished Jul 04 06:40:10 PM PDT 24
Peak memory 225212 kb
Host smart-c98d9341-135b-4a31-8c39-dfddb3e6c1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271402303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.4271402303
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.530852748
Short name T515
Test name
Test status
Simulation time 950803220 ps
CPU time 4.08 seconds
Started Jul 04 06:39:59 PM PDT 24
Finished Jul 04 06:40:03 PM PDT 24
Peak memory 217660 kb
Host smart-4bdbce54-8818-4a93-b7aa-31e229544b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530852748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.530852748
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.2746526139
Short name T654
Test name
Test status
Simulation time 659915167 ps
CPU time 28.06 seconds
Started Jul 04 06:39:59 PM PDT 24
Finished Jul 04 06:40:27 PM PDT 24
Peak memory 250972 kb
Host smart-5abb24bd-797a-47be-95d8-88bc995fc683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746526139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2746526139
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.4079126763
Short name T698
Test name
Test status
Simulation time 322753655 ps
CPU time 7.11 seconds
Started Jul 04 06:40:00 PM PDT 24
Finished Jul 04 06:40:07 PM PDT 24
Peak memory 247176 kb
Host smart-07a2cb4e-4f74-460d-87a5-db0559c1a342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079126763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.4079126763
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.2203162881
Short name T442
Test name
Test status
Simulation time 1383082957 ps
CPU time 29.35 seconds
Started Jul 04 06:40:06 PM PDT 24
Finished Jul 04 06:40:35 PM PDT 24
Peak memory 251056 kb
Host smart-5dcbb59b-ad4a-4f48-8907-1529556e7f99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203162881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.2203162881
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.3713616431
Short name T479
Test name
Test status
Simulation time 31026207 ps
CPU time 0.96 seconds
Started Jul 04 06:40:02 PM PDT 24
Finished Jul 04 06:40:04 PM PDT 24
Peak memory 211924 kb
Host smart-cdedba07-021e-4ab8-b7d1-ab5467f8bb95
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713616431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.3713616431
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.206068764
Short name T349
Test name
Test status
Simulation time 29145702 ps
CPU time 1.38 seconds
Started Jul 04 06:43:27 PM PDT 24
Finished Jul 04 06:43:29 PM PDT 24
Peak memory 208972 kb
Host smart-d8b38ca8-7973-44c4-8cfd-944bf4af6ad7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206068764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.206068764
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.648995229
Short name T569
Test name
Test status
Simulation time 1219328925 ps
CPU time 11.46 seconds
Started Jul 04 06:43:27 PM PDT 24
Finished Jul 04 06:43:39 PM PDT 24
Peak memory 226052 kb
Host smart-b14b7f99-7c98-4f73-ba5b-4519b18c17e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648995229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.648995229
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.872667246
Short name T586
Test name
Test status
Simulation time 1083656817 ps
CPU time 7.78 seconds
Started Jul 04 06:43:29 PM PDT 24
Finished Jul 04 06:43:37 PM PDT 24
Peak memory 217692 kb
Host smart-6cb02194-b9a2-471a-8253-15e7897b05ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872667246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.872667246
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3125420939
Short name T521
Test name
Test status
Simulation time 102178203 ps
CPU time 3.74 seconds
Started Jul 04 06:43:24 PM PDT 24
Finished Jul 04 06:43:28 PM PDT 24
Peak memory 218240 kb
Host smart-80f63e63-46c0-459c-bdd8-176902ce7c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125420939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3125420939
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.1300173073
Short name T158
Test name
Test status
Simulation time 1237988292 ps
CPU time 11.41 seconds
Started Jul 04 06:43:28 PM PDT 24
Finished Jul 04 06:43:40 PM PDT 24
Peak memory 218900 kb
Host smart-6c304d00-c5a9-48ec-b7e0-959d29ebc003
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300173073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.1300173073
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1608342771
Short name T376
Test name
Test status
Simulation time 533525148 ps
CPU time 9.55 seconds
Started Jul 04 06:43:28 PM PDT 24
Finished Jul 04 06:43:39 PM PDT 24
Peak memory 225472 kb
Host smart-5fc2e9b0-14e0-449e-a65e-03ca1d9c2416
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608342771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1608342771
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1562857699
Short name T591
Test name
Test status
Simulation time 312895401 ps
CPU time 11.27 seconds
Started Jul 04 06:43:28 PM PDT 24
Finished Jul 04 06:43:40 PM PDT 24
Peak memory 226032 kb
Host smart-f74e5052-58c4-44d0-a338-145009360c4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562857699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1562857699
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.3392360205
Short name T657
Test name
Test status
Simulation time 1072734134 ps
CPU time 7.71 seconds
Started Jul 04 06:43:27 PM PDT 24
Finished Jul 04 06:43:35 PM PDT 24
Peak memory 224908 kb
Host smart-d96e0ab4-9938-4fd1-ac9f-dc3e5e6c590b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392360205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3392360205
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.962725933
Short name T492
Test name
Test status
Simulation time 562525495 ps
CPU time 4.06 seconds
Started Jul 04 06:43:23 PM PDT 24
Finished Jul 04 06:43:27 PM PDT 24
Peak memory 217712 kb
Host smart-3bec40d5-6704-455d-b84b-f0281c1f972e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962725933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.962725933
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.706047425
Short name T298
Test name
Test status
Simulation time 753720683 ps
CPU time 24.23 seconds
Started Jul 04 06:43:19 PM PDT 24
Finished Jul 04 06:43:44 PM PDT 24
Peak memory 251024 kb
Host smart-0765a454-e16b-4b56-a6a2-b304d649c7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706047425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.706047425
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.1042663640
Short name T344
Test name
Test status
Simulation time 61262795 ps
CPU time 7.11 seconds
Started Jul 04 06:43:20 PM PDT 24
Finished Jul 04 06:43:28 PM PDT 24
Peak memory 250472 kb
Host smart-9eb7cf73-116d-4e8c-bd2f-1b72b372a93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042663640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.1042663640
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3019463856
Short name T410
Test name
Test status
Simulation time 6326614407 ps
CPU time 43.96 seconds
Started Jul 04 06:43:27 PM PDT 24
Finished Jul 04 06:44:11 PM PDT 24
Peak memory 267312 kb
Host smart-5da89eca-1c64-4248-82ed-40b162698d7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019463856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3019463856
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2185117255
Short name T721
Test name
Test status
Simulation time 40581135 ps
CPU time 0.84 seconds
Started Jul 04 06:43:20 PM PDT 24
Finished Jul 04 06:43:21 PM PDT 24
Peak memory 211832 kb
Host smart-86a5f80a-40dd-4dea-941d-08a8eb8e25ac
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185117255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.2185117255
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.328130335
Short name T297
Test name
Test status
Simulation time 30408972 ps
CPU time 0.9 seconds
Started Jul 04 06:43:27 PM PDT 24
Finished Jul 04 06:43:28 PM PDT 24
Peak memory 209052 kb
Host smart-50205457-639a-4fce-911b-aee40181be6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328130335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.328130335
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.3568326407
Short name T1
Test name
Test status
Simulation time 709156692 ps
CPU time 18.89 seconds
Started Jul 04 06:43:27 PM PDT 24
Finished Jul 04 06:43:47 PM PDT 24
Peak memory 218264 kb
Host smart-b7720577-83f7-44b4-b2ca-311316cb89cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568326407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3568326407
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.1735305222
Short name T719
Test name
Test status
Simulation time 399504874 ps
CPU time 5.96 seconds
Started Jul 04 06:43:28 PM PDT 24
Finished Jul 04 06:43:34 PM PDT 24
Peak memory 217108 kb
Host smart-ce8c708b-d529-490d-9f4b-61edc2018032
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735305222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.1735305222
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.478629114
Short name T244
Test name
Test status
Simulation time 51501600 ps
CPU time 1.97 seconds
Started Jul 04 06:43:28 PM PDT 24
Finished Jul 04 06:43:30 PM PDT 24
Peak memory 222056 kb
Host smart-21959464-0fe2-4997-88ee-6b7d96a53370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478629114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.478629114
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.1055252337
Short name T170
Test name
Test status
Simulation time 282722710 ps
CPU time 14.07 seconds
Started Jul 04 06:43:26 PM PDT 24
Finished Jul 04 06:43:41 PM PDT 24
Peak memory 226052 kb
Host smart-03b45a2f-33a2-49c5-b92b-9fec97229ba7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055252337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.1055252337
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.4121035830
Short name T614
Test name
Test status
Simulation time 1133490517 ps
CPU time 7.7 seconds
Started Jul 04 06:43:27 PM PDT 24
Finished Jul 04 06:43:34 PM PDT 24
Peak memory 226172 kb
Host smart-93a738de-17cc-4a8a-9cec-1b37177d56c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121035830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.4121035830
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1549777701
Short name T687
Test name
Test status
Simulation time 423028033 ps
CPU time 11.01 seconds
Started Jul 04 06:43:28 PM PDT 24
Finished Jul 04 06:43:40 PM PDT 24
Peak memory 218188 kb
Host smart-b5bf5d68-4517-41cf-9a59-7e697c6392b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549777701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
1549777701
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.3864471033
Short name T412
Test name
Test status
Simulation time 250652002 ps
CPU time 11.11 seconds
Started Jul 04 06:43:29 PM PDT 24
Finished Jul 04 06:43:40 PM PDT 24
Peak memory 226032 kb
Host smart-e9451661-54ea-4538-9f6d-a9c91c4c5740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864471033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3864471033
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3099804099
Short name T513
Test name
Test status
Simulation time 100524039 ps
CPU time 3.17 seconds
Started Jul 04 06:43:28 PM PDT 24
Finished Jul 04 06:43:32 PM PDT 24
Peak memory 222836 kb
Host smart-1ad34079-c693-4130-933d-288d4edb2f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099804099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3099804099
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1831224101
Short name T189
Test name
Test status
Simulation time 823152315 ps
CPU time 29.67 seconds
Started Jul 04 06:43:27 PM PDT 24
Finished Jul 04 06:43:57 PM PDT 24
Peak memory 250968 kb
Host smart-30877d67-be7b-4d65-ad7f-3574b301a4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831224101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1831224101
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1797080741
Short name T181
Test name
Test status
Simulation time 75958718 ps
CPU time 8.32 seconds
Started Jul 04 06:43:27 PM PDT 24
Finished Jul 04 06:43:36 PM PDT 24
Peak memory 250952 kb
Host smart-606e6a4c-f2af-476e-a93e-7f09ac2b7470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797080741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1797080741
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3121503444
Short name T514
Test name
Test status
Simulation time 11308242453 ps
CPU time 206.12 seconds
Started Jul 04 06:43:27 PM PDT 24
Finished Jul 04 06:46:54 PM PDT 24
Peak memory 281900 kb
Host smart-245e557f-950c-49f7-903f-1c9be6c44126
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121503444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3121503444
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1810378215
Short name T620
Test name
Test status
Simulation time 15880074 ps
CPU time 0.89 seconds
Started Jul 04 06:43:27 PM PDT 24
Finished Jul 04 06:43:28 PM PDT 24
Peak memory 212948 kb
Host smart-dcab5649-22c5-4c21-bb92-7ac0b9ddee28
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810378215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1810378215
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.719591892
Short name T772
Test name
Test status
Simulation time 300168936 ps
CPU time 0.87 seconds
Started Jul 04 06:43:45 PM PDT 24
Finished Jul 04 06:43:46 PM PDT 24
Peak memory 209040 kb
Host smart-8cad2f1c-f4c2-4290-b569-26d368530019
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719591892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.719591892
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.106541213
Short name T315
Test name
Test status
Simulation time 1219128920 ps
CPU time 12.89 seconds
Started Jul 04 06:43:43 PM PDT 24
Finished Jul 04 06:43:56 PM PDT 24
Peak memory 226016 kb
Host smart-46865e0d-75bc-4c82-b74b-268d2916d5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106541213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.106541213
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.391434664
Short name T28
Test name
Test status
Simulation time 285893059 ps
CPU time 1.81 seconds
Started Jul 04 06:43:44 PM PDT 24
Finished Jul 04 06:43:46 PM PDT 24
Peak memory 217160 kb
Host smart-a5b3bc34-823d-4acc-b506-e86021280ea4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391434664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.391434664
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3707016518
Short name T237
Test name
Test status
Simulation time 276646178 ps
CPU time 2.91 seconds
Started Jul 04 06:43:44 PM PDT 24
Finished Jul 04 06:43:47 PM PDT 24
Peak memory 218192 kb
Host smart-5cf410cb-a2d6-43ea-89be-3855dcbf0c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707016518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3707016518
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.1254028402
Short name T348
Test name
Test status
Simulation time 274676449 ps
CPU time 11.23 seconds
Started Jul 04 06:43:36 PM PDT 24
Finished Jul 04 06:43:47 PM PDT 24
Peak memory 225996 kb
Host smart-019a91b7-e21b-4a59-968b-8c27b095ae10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254028402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.1254028402
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2384915300
Short name T50
Test name
Test status
Simulation time 362347814 ps
CPU time 12.33 seconds
Started Jul 04 06:43:34 PM PDT 24
Finished Jul 04 06:43:47 PM PDT 24
Peak memory 226032 kb
Host smart-9c59f2f8-a66a-4cce-af82-0f6cf063ba6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384915300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2384915300
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.893817515
Short name T562
Test name
Test status
Simulation time 799977066 ps
CPU time 9.47 seconds
Started Jul 04 06:43:36 PM PDT 24
Finished Jul 04 06:43:46 PM PDT 24
Peak memory 226048 kb
Host smart-60fcd98f-3332-434a-83fd-d353976a409f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893817515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.893817515
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.1978741081
Short name T339
Test name
Test status
Simulation time 57866224 ps
CPU time 2.16 seconds
Started Jul 04 06:43:37 PM PDT 24
Finished Jul 04 06:43:40 PM PDT 24
Peak memory 214500 kb
Host smart-ca8c6ae1-5190-4f85-9d9e-5dd204de65fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978741081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.1978741081
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.199485720
Short name T595
Test name
Test status
Simulation time 353970617 ps
CPU time 31.01 seconds
Started Jul 04 06:43:42 PM PDT 24
Finished Jul 04 06:44:13 PM PDT 24
Peak memory 251112 kb
Host smart-24662592-389d-49a8-8546-0ebf850447aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199485720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.199485720
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.2424169721
Short name T445
Test name
Test status
Simulation time 245668765 ps
CPU time 7.82 seconds
Started Jul 04 06:43:43 PM PDT 24
Finished Jul 04 06:43:51 PM PDT 24
Peak memory 250952 kb
Host smart-bc558b08-dc3a-4490-8f3f-2fc8e2bced4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424169721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.2424169721
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.2188432250
Short name T439
Test name
Test status
Simulation time 27362297839 ps
CPU time 436.29 seconds
Started Jul 04 06:43:43 PM PDT 24
Finished Jul 04 06:51:00 PM PDT 24
Peak memory 268332 kb
Host smart-95f48343-6791-4e8a-8b16-8b08cfb5e7b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188432250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.2188432250
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.804666734
Short name T312
Test name
Test status
Simulation time 18352860 ps
CPU time 0.87 seconds
Started Jul 04 06:43:36 PM PDT 24
Finished Jul 04 06:43:37 PM PDT 24
Peak memory 211920 kb
Host smart-b72f18cf-42d7-4f33-ae30-425ac1229fb8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804666734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ct
rl_volatile_unlock_smoke.804666734
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.333477424
Short name T658
Test name
Test status
Simulation time 27015072 ps
CPU time 1.03 seconds
Started Jul 04 06:43:44 PM PDT 24
Finished Jul 04 06:43:45 PM PDT 24
Peak memory 208956 kb
Host smart-18ee625f-ec9e-4071-82f4-add922a26fef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333477424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.333477424
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.881395923
Short name T290
Test name
Test status
Simulation time 287561805 ps
CPU time 9.55 seconds
Started Jul 04 06:43:44 PM PDT 24
Finished Jul 04 06:43:54 PM PDT 24
Peak memory 226048 kb
Host smart-33aecdc2-1eef-42c6-ac2a-6ecdb5817afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881395923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.881395923
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.4285197218
Short name T773
Test name
Test status
Simulation time 579864100 ps
CPU time 2.18 seconds
Started Jul 04 06:43:43 PM PDT 24
Finished Jul 04 06:43:45 PM PDT 24
Peak memory 217116 kb
Host smart-66908c08-e7c5-4a63-9898-14d3bff1e5b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285197218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.4285197218
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.3992271408
Short name T558
Test name
Test status
Simulation time 22456522 ps
CPU time 1.77 seconds
Started Jul 04 06:43:44 PM PDT 24
Finished Jul 04 06:43:46 PM PDT 24
Peak memory 218236 kb
Host smart-947a4e61-14cb-4075-aa63-a0c85573672c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992271408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.3992271408
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.954293300
Short name T713
Test name
Test status
Simulation time 200166783 ps
CPU time 7.7 seconds
Started Jul 04 06:43:44 PM PDT 24
Finished Jul 04 06:43:52 PM PDT 24
Peak memory 218224 kb
Host smart-de36e70e-81bf-4b81-9839-34d1d520d520
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954293300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.954293300
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1240151165
Short name T611
Test name
Test status
Simulation time 337037831 ps
CPU time 14.61 seconds
Started Jul 04 06:43:43 PM PDT 24
Finished Jul 04 06:43:58 PM PDT 24
Peak memory 226044 kb
Host smart-68015a8d-43ae-44e2-ad70-ed767725d26e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240151165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.1240151165
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.1121046770
Short name T52
Test name
Test status
Simulation time 319027761 ps
CPU time 8.99 seconds
Started Jul 04 06:43:43 PM PDT 24
Finished Jul 04 06:43:52 PM PDT 24
Peak memory 226012 kb
Host smart-5d0282ab-f6ba-4106-86f9-e97d62efd155
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121046770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
1121046770
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.2222410284
Short name T40
Test name
Test status
Simulation time 1190037798 ps
CPU time 7.55 seconds
Started Jul 04 06:43:45 PM PDT 24
Finished Jul 04 06:43:52 PM PDT 24
Peak memory 224712 kb
Host smart-2bba627b-f559-487e-9afd-1ffbfb975f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222410284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2222410284
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.3143589828
Short name T76
Test name
Test status
Simulation time 26057224 ps
CPU time 1.81 seconds
Started Jul 04 06:43:44 PM PDT 24
Finished Jul 04 06:43:47 PM PDT 24
Peak memory 213992 kb
Host smart-3cbbb5a7-503c-459e-a861-fe629eabfd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143589828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3143589828
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2306305763
Short name T225
Test name
Test status
Simulation time 371276592 ps
CPU time 41.35 seconds
Started Jul 04 06:43:43 PM PDT 24
Finished Jul 04 06:44:24 PM PDT 24
Peak memory 251024 kb
Host smart-0de2c9c9-126c-42f3-96f7-61fabb8f54d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306305763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2306305763
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3515257921
Short name T564
Test name
Test status
Simulation time 62943217 ps
CPU time 3.67 seconds
Started Jul 04 06:43:43 PM PDT 24
Finished Jul 04 06:43:47 PM PDT 24
Peak memory 222580 kb
Host smart-e9a41033-401e-484c-9398-fd11ebc4ca32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515257921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3515257921
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.3913354822
Short name T80
Test name
Test status
Simulation time 4591047346 ps
CPU time 149.17 seconds
Started Jul 04 06:43:42 PM PDT 24
Finished Jul 04 06:46:12 PM PDT 24
Peak memory 251060 kb
Host smart-a85fb4ae-e358-40d4-8c3f-ff8ee8b1a766
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913354822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.3913354822
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1373193573
Short name T465
Test name
Test status
Simulation time 30773331 ps
CPU time 1.17 seconds
Started Jul 04 06:43:44 PM PDT 24
Finished Jul 04 06:43:46 PM PDT 24
Peak memory 217744 kb
Host smart-39bdc904-333e-4c99-93e7-72454d63d01f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373193573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.1373193573
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1618200542
Short name T663
Test name
Test status
Simulation time 18878999 ps
CPU time 0.92 seconds
Started Jul 04 06:43:51 PM PDT 24
Finished Jul 04 06:43:52 PM PDT 24
Peak memory 208936 kb
Host smart-3a2debe8-6f9b-4467-9f89-b893ff6ea9f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618200542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1618200542
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.693652612
Short name T724
Test name
Test status
Simulation time 761442085 ps
CPU time 18.01 seconds
Started Jul 04 06:43:53 PM PDT 24
Finished Jul 04 06:44:11 PM PDT 24
Peak memory 218216 kb
Host smart-99c31118-5c81-4f87-8502-083a7624d3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693652612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.693652612
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.3329880342
Short name T630
Test name
Test status
Simulation time 461120669 ps
CPU time 6.27 seconds
Started Jul 04 06:43:50 PM PDT 24
Finished Jul 04 06:43:56 PM PDT 24
Peak memory 217356 kb
Host smart-388797c5-1ee5-4deb-a42a-33f55ead6eb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329880342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.3329880342
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.2278572413
Short name T413
Test name
Test status
Simulation time 71591970 ps
CPU time 1.72 seconds
Started Jul 04 06:43:54 PM PDT 24
Finished Jul 04 06:43:56 PM PDT 24
Peak memory 218208 kb
Host smart-f8c38de8-2a75-4372-9223-b68b2dffe6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278572413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2278572413
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.2131499262
Short name T37
Test name
Test status
Simulation time 959164107 ps
CPU time 16.09 seconds
Started Jul 04 06:43:51 PM PDT 24
Finished Jul 04 06:44:07 PM PDT 24
Peak memory 218468 kb
Host smart-a10456e9-09a0-47a6-971d-126be02f8b8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131499262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.2131499262
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2436296129
Short name T351
Test name
Test status
Simulation time 847065594 ps
CPU time 10.54 seconds
Started Jul 04 06:43:52 PM PDT 24
Finished Jul 04 06:44:03 PM PDT 24
Peak memory 226108 kb
Host smart-f3334617-d028-439a-bbcf-e5eba59d86d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436296129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.2436296129
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2116676081
Short name T92
Test name
Test status
Simulation time 622748541 ps
CPU time 9.4 seconds
Started Jul 04 06:43:54 PM PDT 24
Finished Jul 04 06:44:04 PM PDT 24
Peak memory 226048 kb
Host smart-32909592-7113-4821-9e56-c9c85d744d5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116676081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2116676081
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.1673178190
Short name T41
Test name
Test status
Simulation time 1044174566 ps
CPU time 7.37 seconds
Started Jul 04 06:43:51 PM PDT 24
Finished Jul 04 06:43:58 PM PDT 24
Peak memory 218292 kb
Host smart-91df665a-3556-4fdb-bee8-dd1d7795fb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673178190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.1673178190
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.4275554381
Short name T728
Test name
Test status
Simulation time 40286933 ps
CPU time 2.93 seconds
Started Jul 04 06:43:43 PM PDT 24
Finished Jul 04 06:43:46 PM PDT 24
Peak memory 214524 kb
Host smart-27464674-cdf0-4e3c-bd53-39df08b5fdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275554381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.4275554381
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1561023100
Short name T101
Test name
Test status
Simulation time 612763478 ps
CPU time 31.15 seconds
Started Jul 04 06:43:44 PM PDT 24
Finished Jul 04 06:44:16 PM PDT 24
Peak memory 251052 kb
Host smart-04b4ec9e-3a0a-4d61-86e9-518b5ad29600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561023100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1561023100
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.322807469
Short name T641
Test name
Test status
Simulation time 373505865 ps
CPU time 6.46 seconds
Started Jul 04 06:43:44 PM PDT 24
Finished Jul 04 06:43:51 PM PDT 24
Peak memory 247656 kb
Host smart-1ee57b30-e6b7-428b-98c1-76fd11c8b0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322807469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.322807469
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1351502139
Short name T824
Test name
Test status
Simulation time 12469405 ps
CPU time 0.98 seconds
Started Jul 04 06:43:43 PM PDT 24
Finished Jul 04 06:43:44 PM PDT 24
Peak memory 211944 kb
Host smart-1464ab26-df66-455f-954d-2c2d0945efe3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351502139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1351502139
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.3261293847
Short name T63
Test name
Test status
Simulation time 39079859 ps
CPU time 0.83 seconds
Started Jul 04 06:43:53 PM PDT 24
Finished Jul 04 06:43:54 PM PDT 24
Peak memory 208772 kb
Host smart-e289ca5b-8f85-4368-a683-ca113bb0b94b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261293847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3261293847
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.50359977
Short name T627
Test name
Test status
Simulation time 977984084 ps
CPU time 11.49 seconds
Started Jul 04 06:43:54 PM PDT 24
Finished Jul 04 06:44:05 PM PDT 24
Peak memory 225960 kb
Host smart-39aeab01-a737-4ad3-9f6f-be3e2bd8b67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50359977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.50359977
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.3502523284
Short name T18
Test name
Test status
Simulation time 592533976 ps
CPU time 2.17 seconds
Started Jul 04 06:43:53 PM PDT 24
Finished Jul 04 06:43:55 PM PDT 24
Peak memory 217188 kb
Host smart-c19227ae-a84a-4e8a-a405-6a0066e58577
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502523284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.3502523284
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.171137375
Short name T19
Test name
Test status
Simulation time 354103739 ps
CPU time 3.27 seconds
Started Jul 04 06:43:52 PM PDT 24
Finished Jul 04 06:43:56 PM PDT 24
Peak memory 218244 kb
Host smart-50fbf0fc-6fb0-4860-8aa6-5920194b4722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171137375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.171137375
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.607149285
Short name T857
Test name
Test status
Simulation time 347383420 ps
CPU time 10.71 seconds
Started Jul 04 06:43:51 PM PDT 24
Finished Jul 04 06:44:02 PM PDT 24
Peak memory 225976 kb
Host smart-fee357d6-b6e6-4e34-8667-ecb4011a6573
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607149285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.607149285
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.1705599643
Short name T730
Test name
Test status
Simulation time 282372374 ps
CPU time 11.46 seconds
Started Jul 04 06:43:51 PM PDT 24
Finished Jul 04 06:44:02 PM PDT 24
Peak memory 226028 kb
Host smart-4c0b9969-1f2a-4b2d-8443-a17cb46b05e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705599643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.1705599643
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.2634671694
Short name T185
Test name
Test status
Simulation time 4283289503 ps
CPU time 13.05 seconds
Started Jul 04 06:43:51 PM PDT 24
Finished Jul 04 06:44:04 PM PDT 24
Peak memory 218324 kb
Host smart-d3af1e9b-89ce-4a4b-a188-3db155f99fef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634671694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
2634671694
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.2545447365
Short name T97
Test name
Test status
Simulation time 2809607275 ps
CPU time 9.15 seconds
Started Jul 04 06:43:53 PM PDT 24
Finished Jul 04 06:44:02 PM PDT 24
Peak memory 226088 kb
Host smart-8adbab4e-2a46-4bd7-a695-0cd561c3285a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545447365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2545447365
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.2373668147
Short name T70
Test name
Test status
Simulation time 191177299 ps
CPU time 3.46 seconds
Started Jul 04 06:43:51 PM PDT 24
Finished Jul 04 06:43:54 PM PDT 24
Peak memory 214896 kb
Host smart-25e9f65c-21eb-4740-9930-5a7874bd132c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373668147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.2373668147
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.1791103152
Short name T106
Test name
Test status
Simulation time 326830689 ps
CPU time 15.13 seconds
Started Jul 04 06:43:52 PM PDT 24
Finished Jul 04 06:44:07 PM PDT 24
Peak memory 251044 kb
Host smart-428bdbe3-95bc-4cf1-b802-0d1a8231b087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791103152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.1791103152
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.291458611
Short name T235
Test name
Test status
Simulation time 188917291 ps
CPU time 3.5 seconds
Started Jul 04 06:43:54 PM PDT 24
Finished Jul 04 06:43:58 PM PDT 24
Peak memory 226420 kb
Host smart-e0f94f33-8a6f-4e73-876b-88a68ba2eee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291458611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.291458611
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.498139874
Short name T241
Test name
Test status
Simulation time 11573687500 ps
CPU time 68.29 seconds
Started Jul 04 06:43:53 PM PDT 24
Finished Jul 04 06:45:02 PM PDT 24
Peak memory 251028 kb
Host smart-645e0280-cd77-44e3-a788-b502b8f44a39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498139874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.498139874
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1407404727
Short name T259
Test name
Test status
Simulation time 29022271 ps
CPU time 0.8 seconds
Started Jul 04 06:43:50 PM PDT 24
Finished Jul 04 06:43:51 PM PDT 24
Peak memory 211960 kb
Host smart-105548fe-2f96-4b82-bc7b-413042b98c16
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407404727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.1407404727
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.2572764480
Short name T571
Test name
Test status
Simulation time 40522563 ps
CPU time 0.98 seconds
Started Jul 04 06:43:58 PM PDT 24
Finished Jul 04 06:44:00 PM PDT 24
Peak memory 209032 kb
Host smart-d77717dc-0c23-48ca-b797-0821558aef69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572764480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.2572764480
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.2874683368
Short name T228
Test name
Test status
Simulation time 287303538 ps
CPU time 11.53 seconds
Started Jul 04 06:44:01 PM PDT 24
Finished Jul 04 06:44:12 PM PDT 24
Peak memory 218224 kb
Host smart-59910380-09ba-4751-9ca9-1db770784502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874683368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2874683368
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.613325657
Short name T543
Test name
Test status
Simulation time 1423082028 ps
CPU time 4.37 seconds
Started Jul 04 06:43:58 PM PDT 24
Finished Jul 04 06:44:02 PM PDT 24
Peak memory 217728 kb
Host smart-2aff0a17-e5b3-41b1-8429-9f7c82ff71b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613325657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.613325657
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.31072459
Short name T510
Test name
Test status
Simulation time 51243916 ps
CPU time 1.94 seconds
Started Jul 04 06:44:00 PM PDT 24
Finished Jul 04 06:44:02 PM PDT 24
Peak memory 218224 kb
Host smart-2d4658d9-7ad9-43fc-b194-d26bc4d747a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31072459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.31072459
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.703641908
Short name T780
Test name
Test status
Simulation time 267766688 ps
CPU time 8.9 seconds
Started Jul 04 06:43:58 PM PDT 24
Finished Jul 04 06:44:07 PM PDT 24
Peak memory 226060 kb
Host smart-e4251658-9765-46bf-b755-8217b674949a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703641908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.703641908
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.1503460076
Short name T280
Test name
Test status
Simulation time 8705765516 ps
CPU time 16.19 seconds
Started Jul 04 06:43:58 PM PDT 24
Finished Jul 04 06:44:15 PM PDT 24
Peak memory 226124 kb
Host smart-45272be1-64b8-4db0-aa80-ceeb94013a1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503460076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.1503460076
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.1548488588
Short name T143
Test name
Test status
Simulation time 438916945 ps
CPU time 6.43 seconds
Started Jul 04 06:43:59 PM PDT 24
Finished Jul 04 06:44:05 PM PDT 24
Peak memory 218208 kb
Host smart-c42bc8c8-987c-4cba-a11d-66c804d4fc92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548488588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
1548488588
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1763576758
Short name T44
Test name
Test status
Simulation time 169112835 ps
CPU time 8.12 seconds
Started Jul 04 06:44:00 PM PDT 24
Finished Jul 04 06:44:09 PM PDT 24
Peak memory 224904 kb
Host smart-9cb517c9-e87b-4045-9e5e-760232cab857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763576758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1763576758
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.1855508169
Short name T795
Test name
Test status
Simulation time 42595470 ps
CPU time 2.03 seconds
Started Jul 04 06:43:53 PM PDT 24
Finished Jul 04 06:43:55 PM PDT 24
Peak memory 214100 kb
Host smart-65990233-4e70-4375-9ced-c006776fc7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855508169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1855508169
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3583991667
Short name T567
Test name
Test status
Simulation time 1145323998 ps
CPU time 29.82 seconds
Started Jul 04 06:44:00 PM PDT 24
Finished Jul 04 06:44:30 PM PDT 24
Peak memory 251048 kb
Host smart-b005da7f-8a2c-4c16-938c-04c7cd26d974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583991667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3583991667
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.338515270
Short name T717
Test name
Test status
Simulation time 83800757 ps
CPU time 8.13 seconds
Started Jul 04 06:44:00 PM PDT 24
Finished Jul 04 06:44:08 PM PDT 24
Peak memory 250920 kb
Host smart-4d90e19d-46f4-4358-89c2-0bf7cca14825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338515270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.338515270
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.445006418
Short name T677
Test name
Test status
Simulation time 3328151334 ps
CPU time 76.74 seconds
Started Jul 04 06:43:59 PM PDT 24
Finished Jul 04 06:45:16 PM PDT 24
Peak memory 283844 kb
Host smart-34aa0877-4067-4aab-898f-7ab21a6c586f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445006418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.445006418
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.4098778143
Short name T232
Test name
Test status
Simulation time 13833552 ps
CPU time 0.87 seconds
Started Jul 04 06:43:52 PM PDT 24
Finished Jul 04 06:43:53 PM PDT 24
Peak memory 211884 kb
Host smart-f500bde3-9d6c-4e71-a762-3798cb39b1cd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098778143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.4098778143
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.2331023633
Short name T509
Test name
Test status
Simulation time 21357250 ps
CPU time 0.95 seconds
Started Jul 04 06:44:15 PM PDT 24
Finished Jul 04 06:44:16 PM PDT 24
Peak memory 208972 kb
Host smart-7edb59da-10bd-483c-9811-61d63b6ab01e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331023633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.2331023633
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1830559979
Short name T490
Test name
Test status
Simulation time 1249440604 ps
CPU time 11.89 seconds
Started Jul 04 06:43:58 PM PDT 24
Finished Jul 04 06:44:10 PM PDT 24
Peak memory 218164 kb
Host smart-6dd1c4b4-fc88-4221-8533-2d767ec7731f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830559979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1830559979
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.3195690580
Short name T27
Test name
Test status
Simulation time 686925408 ps
CPU time 9.3 seconds
Started Jul 04 06:44:08 PM PDT 24
Finished Jul 04 06:44:17 PM PDT 24
Peak memory 217620 kb
Host smart-e419799e-2ca5-401f-8ea7-549895493180
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195690580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.3195690580
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.637536431
Short name T605
Test name
Test status
Simulation time 215233934 ps
CPU time 3.34 seconds
Started Jul 04 06:43:59 PM PDT 24
Finished Jul 04 06:44:02 PM PDT 24
Peak memory 222460 kb
Host smart-7c6215ff-eebe-4bbd-878d-4e27db34b744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637536431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.637536431
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.413325441
Short name T393
Test name
Test status
Simulation time 1600758929 ps
CPU time 14.55 seconds
Started Jul 04 06:44:06 PM PDT 24
Finished Jul 04 06:44:20 PM PDT 24
Peak memory 226036 kb
Host smart-7872dcae-d528-4f1e-bf02-03a8a59dc6da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413325441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.413325441
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2858528421
Short name T722
Test name
Test status
Simulation time 735296708 ps
CPU time 11.08 seconds
Started Jul 04 06:44:14 PM PDT 24
Finished Jul 04 06:44:26 PM PDT 24
Peak memory 226032 kb
Host smart-f944ea50-a2df-4a95-adcb-244b5b480c38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858528421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2858528421
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2331910130
Short name T747
Test name
Test status
Simulation time 761875458 ps
CPU time 6.82 seconds
Started Jul 04 06:44:06 PM PDT 24
Finished Jul 04 06:44:13 PM PDT 24
Peak memory 218224 kb
Host smart-33e750d7-eca2-41b2-b211-f506032beb3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331910130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2331910130
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.67452839
Short name T819
Test name
Test status
Simulation time 635730913 ps
CPU time 11.88 seconds
Started Jul 04 06:43:59 PM PDT 24
Finished Jul 04 06:44:11 PM PDT 24
Peak memory 224980 kb
Host smart-e8bd8247-c8ab-46de-8d62-4f4a5d56dd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67452839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.67452839
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.1840735102
Short name T411
Test name
Test status
Simulation time 47842994 ps
CPU time 1.02 seconds
Started Jul 04 06:44:00 PM PDT 24
Finished Jul 04 06:44:01 PM PDT 24
Peak memory 212124 kb
Host smart-93caba7e-a896-4130-a6d6-0a37e22816a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840735102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.1840735102
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.2886000912
Short name T157
Test name
Test status
Simulation time 263676892 ps
CPU time 31.59 seconds
Started Jul 04 06:44:01 PM PDT 24
Finished Jul 04 06:44:33 PM PDT 24
Peak memory 250960 kb
Host smart-06219423-1938-4897-8de1-8d109028f08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886000912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2886000912
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.209005014
Short name T323
Test name
Test status
Simulation time 96409256 ps
CPU time 3.3 seconds
Started Jul 04 06:43:58 PM PDT 24
Finished Jul 04 06:44:01 PM PDT 24
Peak memory 226336 kb
Host smart-3103615a-aa99-4484-8d4e-092ee6b21c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209005014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.209005014
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.3558715351
Short name T88
Test name
Test status
Simulation time 1934315296 ps
CPU time 21.23 seconds
Started Jul 04 06:44:09 PM PDT 24
Finished Jul 04 06:44:30 PM PDT 24
Peak memory 243792 kb
Host smart-88897916-e18a-4094-ab89-e26feff1b612
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558715351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.3558715351
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.2385358084
Short name T164
Test name
Test status
Simulation time 67625844494 ps
CPU time 522.06 seconds
Started Jul 04 06:44:15 PM PDT 24
Finished Jul 04 06:52:57 PM PDT 24
Peak memory 300328 kb
Host smart-889e5826-e1da-4a5c-aff6-9b20c9abccd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2385358084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.2385358084
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3204382146
Short name T805
Test name
Test status
Simulation time 21117148 ps
CPU time 0.89 seconds
Started Jul 04 06:44:00 PM PDT 24
Finished Jul 04 06:44:01 PM PDT 24
Peak memory 211968 kb
Host smart-89d756e1-cb63-42ed-bb25-85d64e669769
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204382146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3204382146
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3344785898
Short name T623
Test name
Test status
Simulation time 57485814 ps
CPU time 1.06 seconds
Started Jul 04 06:44:08 PM PDT 24
Finished Jul 04 06:44:09 PM PDT 24
Peak memory 209008 kb
Host smart-ee62e761-3fa3-4edf-bd63-302211662247
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344785898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3344785898
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.3008554013
Short name T473
Test name
Test status
Simulation time 1364566502 ps
CPU time 13.37 seconds
Started Jul 04 06:44:09 PM PDT 24
Finished Jul 04 06:44:22 PM PDT 24
Peak memory 226040 kb
Host smart-843710be-0972-4632-bb89-bdaefbc8f317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008554013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.3008554013
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.712687873
Short name T640
Test name
Test status
Simulation time 2072868374 ps
CPU time 5.7 seconds
Started Jul 04 06:44:09 PM PDT 24
Finished Jul 04 06:44:15 PM PDT 24
Peak memory 217344 kb
Host smart-6f324e1a-0c56-4721-9606-888a8efe8b2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712687873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.712687873
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.2763217561
Short name T856
Test name
Test status
Simulation time 80132531 ps
CPU time 1.58 seconds
Started Jul 04 06:44:06 PM PDT 24
Finished Jul 04 06:44:08 PM PDT 24
Peak memory 218212 kb
Host smart-2b4cfbaa-cb0a-4077-9c2e-b3f560f3e815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763217561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.2763217561
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.4177366488
Short name T828
Test name
Test status
Simulation time 517393539 ps
CPU time 14.78 seconds
Started Jul 04 06:44:07 PM PDT 24
Finished Jul 04 06:44:22 PM PDT 24
Peak memory 226012 kb
Host smart-867c6349-9d1e-41d5-b298-c2c22b83bc1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177366488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.4177366488
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.4259906780
Short name T231
Test name
Test status
Simulation time 433806722 ps
CPU time 15.8 seconds
Started Jul 04 06:44:07 PM PDT 24
Finished Jul 04 06:44:23 PM PDT 24
Peak memory 226016 kb
Host smart-88ae2fd5-22e7-468c-9c40-196394b951ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259906780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.4259906780
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.262302719
Short name T725
Test name
Test status
Simulation time 547136157 ps
CPU time 16.72 seconds
Started Jul 04 06:44:14 PM PDT 24
Finished Jul 04 06:44:31 PM PDT 24
Peak memory 218236 kb
Host smart-3f59ef68-28cb-4e8f-883c-c1fe6ed2dddd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262302719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.262302719
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.1006588031
Short name T454
Test name
Test status
Simulation time 1109129393 ps
CPU time 12.7 seconds
Started Jul 04 06:44:09 PM PDT 24
Finished Jul 04 06:44:22 PM PDT 24
Peak memory 218380 kb
Host smart-789172a5-a8ec-46a8-b20c-5a83e31cf4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006588031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1006588031
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.2079953542
Short name T309
Test name
Test status
Simulation time 31483642 ps
CPU time 1.51 seconds
Started Jul 04 06:44:07 PM PDT 24
Finished Jul 04 06:44:09 PM PDT 24
Peak memory 217820 kb
Host smart-16ae4ba8-0cce-4c93-a1fb-de307e606b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079953542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.2079953542
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.1610130237
Short name T498
Test name
Test status
Simulation time 466324646 ps
CPU time 23.16 seconds
Started Jul 04 06:44:08 PM PDT 24
Finished Jul 04 06:44:31 PM PDT 24
Peak memory 250988 kb
Host smart-404a2652-b654-49a4-b6b7-faa16b1e3a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610130237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.1610130237
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3126742589
Short name T837
Test name
Test status
Simulation time 2161868531 ps
CPU time 7.49 seconds
Started Jul 04 06:44:09 PM PDT 24
Finished Jul 04 06:44:17 PM PDT 24
Peak memory 250476 kb
Host smart-302db695-0edf-4ccd-9fd1-7d92423569c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126742589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3126742589
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.4129593165
Short name T51
Test name
Test status
Simulation time 30637832804 ps
CPU time 183.2 seconds
Started Jul 04 06:44:15 PM PDT 24
Finished Jul 04 06:47:18 PM PDT 24
Peak memory 251060 kb
Host smart-ed068892-755a-408a-8e79-452bc162c336
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129593165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.4129593165
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.4053619509
Short name T480
Test name
Test status
Simulation time 20413529 ps
CPU time 0.98 seconds
Started Jul 04 06:44:06 PM PDT 24
Finished Jul 04 06:44:07 PM PDT 24
Peak memory 212840 kb
Host smart-5cf6af8d-05d8-4b40-bad2-e80446003ba3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053619509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.4053619509
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.3212962769
Short name T162
Test name
Test status
Simulation time 23690048 ps
CPU time 1.17 seconds
Started Jul 04 06:44:14 PM PDT 24
Finished Jul 04 06:44:15 PM PDT 24
Peak memory 209056 kb
Host smart-974169be-81b7-488a-98f9-a4a9fd2052d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212962769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3212962769
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.1597234514
Short name T767
Test name
Test status
Simulation time 3604512182 ps
CPU time 14.74 seconds
Started Jul 04 06:44:16 PM PDT 24
Finished Jul 04 06:44:30 PM PDT 24
Peak memory 218948 kb
Host smart-789cea75-a8de-4023-9182-1b2b98218646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597234514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1597234514
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2817586954
Short name T9
Test name
Test status
Simulation time 1679981052 ps
CPU time 21.07 seconds
Started Jul 04 06:44:15 PM PDT 24
Finished Jul 04 06:44:36 PM PDT 24
Peak memory 217660 kb
Host smart-28c3f476-c661-4ed8-8aa8-376b72740c5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817586954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2817586954
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.3491986645
Short name T148
Test name
Test status
Simulation time 120442441 ps
CPU time 1.88 seconds
Started Jul 04 06:44:15 PM PDT 24
Finished Jul 04 06:44:17 PM PDT 24
Peak memory 218196 kb
Host smart-bd865e36-a55c-46f2-8bb5-61d0dc328a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491986645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3491986645
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3368674618
Short name T604
Test name
Test status
Simulation time 669291137 ps
CPU time 14.19 seconds
Started Jul 04 06:44:15 PM PDT 24
Finished Jul 04 06:44:30 PM PDT 24
Peak memory 226020 kb
Host smart-d9f21ceb-44dd-4a25-885e-793ee6477df8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368674618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3368674618
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.2916191926
Short name T341
Test name
Test status
Simulation time 280981456 ps
CPU time 7.91 seconds
Started Jul 04 06:44:16 PM PDT 24
Finished Jul 04 06:44:24 PM PDT 24
Peak memory 226056 kb
Host smart-c925fc9b-1d2c-4329-aa34-6d5444ff0a6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916191926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.2916191926
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2692352504
Short name T275
Test name
Test status
Simulation time 891881204 ps
CPU time 9.06 seconds
Started Jul 04 06:44:23 PM PDT 24
Finished Jul 04 06:44:32 PM PDT 24
Peak memory 218244 kb
Host smart-0ad41686-e2c7-48ff-a9ae-fef8450a54e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692352504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2692352504
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.2290348271
Short name T841
Test name
Test status
Simulation time 403919794 ps
CPU time 8.73 seconds
Started Jul 04 06:44:23 PM PDT 24
Finished Jul 04 06:44:32 PM PDT 24
Peak memory 224636 kb
Host smart-23428cb4-89b4-458c-b8b5-986212b79da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290348271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2290348271
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.758852494
Short name T437
Test name
Test status
Simulation time 58534733 ps
CPU time 1.9 seconds
Started Jul 04 06:44:07 PM PDT 24
Finished Jul 04 06:44:09 PM PDT 24
Peak memory 214052 kb
Host smart-7da44269-f6ca-48f4-b090-7c32a920474c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758852494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.758852494
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3766057121
Short name T555
Test name
Test status
Simulation time 599086342 ps
CPU time 28.82 seconds
Started Jul 04 06:44:16 PM PDT 24
Finished Jul 04 06:44:45 PM PDT 24
Peak memory 245376 kb
Host smart-ec541435-281f-4172-ab03-4dbfab9126a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766057121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3766057121
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.2532154227
Short name T581
Test name
Test status
Simulation time 166993600 ps
CPU time 5.82 seconds
Started Jul 04 06:44:15 PM PDT 24
Finished Jul 04 06:44:21 PM PDT 24
Peak memory 250572 kb
Host smart-6105ec48-c812-40ee-87df-8eb0ff7df259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532154227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.2532154227
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.2022022993
Short name T81
Test name
Test status
Simulation time 3072119219 ps
CPU time 113.27 seconds
Started Jul 04 06:44:15 PM PDT 24
Finished Jul 04 06:46:09 PM PDT 24
Peak memory 283836 kb
Host smart-9c1f26be-ed63-47b7-af0f-a50e65c5aac2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022022993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.2022022993
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.1063979199
Short name T701
Test name
Test status
Simulation time 114388209775 ps
CPU time 467.33 seconds
Started Jul 04 06:44:14 PM PDT 24
Finished Jul 04 06:52:01 PM PDT 24
Peak memory 287104 kb
Host smart-5e36b9fc-68ff-4bdb-99bc-a3332cabfd72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1063979199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.1063979199
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1335203839
Short name T105
Test name
Test status
Simulation time 13861270 ps
CPU time 0.89 seconds
Started Jul 04 06:44:15 PM PDT 24
Finished Jul 04 06:44:16 PM PDT 24
Peak memory 211908 kb
Host smart-ec301ee2-3b1f-4aa0-ae74-33d88cd5447f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335203839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1335203839
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2416559259
Short name T609
Test name
Test status
Simulation time 44998482 ps
CPU time 0.82 seconds
Started Jul 04 06:40:23 PM PDT 24
Finished Jul 04 06:40:24 PM PDT 24
Peak memory 208832 kb
Host smart-60459a7d-0fd1-407c-90fc-d6525a6ce926
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416559259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2416559259
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.561826191
Short name T84
Test name
Test status
Simulation time 2467527188 ps
CPU time 18.34 seconds
Started Jul 04 06:40:15 PM PDT 24
Finished Jul 04 06:40:34 PM PDT 24
Peak memory 218932 kb
Host smart-29997093-ec7f-45ec-bbaa-0443f7a0acb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561826191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.561826191
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.3704224650
Short name T94
Test name
Test status
Simulation time 260406702 ps
CPU time 4.07 seconds
Started Jul 04 06:40:14 PM PDT 24
Finished Jul 04 06:40:18 PM PDT 24
Peak memory 217084 kb
Host smart-24856ccb-0994-4803-ac4e-763930e614c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704224650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3704224650
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.4001213492
Short name T539
Test name
Test status
Simulation time 3034308640 ps
CPU time 22.74 seconds
Started Jul 04 06:40:14 PM PDT 24
Finished Jul 04 06:40:37 PM PDT 24
Peak memory 226116 kb
Host smart-bc45c0e6-b96e-4e80-b13c-0be8d695c99a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001213492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.4001213492
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.902251933
Short name T61
Test name
Test status
Simulation time 435569220 ps
CPU time 2.06 seconds
Started Jul 04 06:40:15 PM PDT 24
Finished Jul 04 06:40:17 PM PDT 24
Peak memory 217756 kb
Host smart-26723408-e1f9-4cae-b2d9-e00c4250b7fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902251933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.902251933
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.87945024
Short name T103
Test name
Test status
Simulation time 492807556 ps
CPU time 15.3 seconds
Started Jul 04 06:40:15 PM PDT 24
Finished Jul 04 06:40:31 PM PDT 24
Peak memory 224304 kb
Host smart-2c5515d4-6d52-423b-b4df-1df499f590be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87945024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_p
rog_failure.87945024
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3980387632
Short name T65
Test name
Test status
Simulation time 4538846955 ps
CPU time 17.74 seconds
Started Jul 04 06:40:14 PM PDT 24
Finished Jul 04 06:40:32 PM PDT 24
Peak memory 217772 kb
Host smart-3bcb3efa-6d83-4b0c-89b1-29e81bebc8e4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980387632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3980387632
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.4073835637
Short name T425
Test name
Test status
Simulation time 603595695 ps
CPU time 8.87 seconds
Started Jul 04 06:40:14 PM PDT 24
Finished Jul 04 06:40:23 PM PDT 24
Peak memory 217724 kb
Host smart-1e844da4-2ad5-487c-8460-58c79568368e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073835637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
4073835637
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1950829140
Short name T20
Test name
Test status
Simulation time 5290001570 ps
CPU time 38.9 seconds
Started Jul 04 06:40:16 PM PDT 24
Finished Jul 04 06:40:55 PM PDT 24
Peak memory 251016 kb
Host smart-5e45f77f-2865-4885-b4be-6f14696ea9a8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950829140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.1950829140
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1350915190
Short name T574
Test name
Test status
Simulation time 2873863769 ps
CPU time 15.68 seconds
Started Jul 04 06:40:13 PM PDT 24
Finished Jul 04 06:40:29 PM PDT 24
Peak memory 218400 kb
Host smart-faef8d7b-6d5d-459c-877a-93ce87038891
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350915190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1350915190
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3689804151
Short name T534
Test name
Test status
Simulation time 96287291 ps
CPU time 4.57 seconds
Started Jul 04 06:40:13 PM PDT 24
Finished Jul 04 06:40:17 PM PDT 24
Peak memory 218232 kb
Host smart-ac8018db-1dec-4b41-b3d9-6ecaf3893e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689804151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3689804151
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1133253695
Short name T58
Test name
Test status
Simulation time 5359303951 ps
CPU time 10.46 seconds
Started Jul 04 06:40:15 PM PDT 24
Finished Jul 04 06:40:26 PM PDT 24
Peak memory 217780 kb
Host smart-fe3b4608-e620-40d1-88b4-d5caf96a7333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133253695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1133253695
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.1979387864
Short name T45
Test name
Test status
Simulation time 839493240 ps
CPU time 39.32 seconds
Started Jul 04 06:40:24 PM PDT 24
Finished Jul 04 06:41:04 PM PDT 24
Peak memory 268700 kb
Host smart-acc3053b-70e6-4627-bf75-ec2020143546
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979387864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1979387864
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.188424741
Short name T606
Test name
Test status
Simulation time 740083436 ps
CPU time 10.99 seconds
Started Jul 04 06:40:12 PM PDT 24
Finished Jul 04 06:40:23 PM PDT 24
Peak memory 226028 kb
Host smart-7cbeec3d-37e3-4525-a590-3a60df6c73f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188424741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.188424741
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2543967094
Short name T638
Test name
Test status
Simulation time 357803348 ps
CPU time 16.23 seconds
Started Jul 04 06:40:23 PM PDT 24
Finished Jul 04 06:40:39 PM PDT 24
Peak memory 226072 kb
Host smart-8a71b255-33b7-443d-970c-9d1b900910ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543967094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.2543967094
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1008554355
Short name T666
Test name
Test status
Simulation time 169438852 ps
CPU time 7.1 seconds
Started Jul 04 06:40:23 PM PDT 24
Finished Jul 04 06:40:30 PM PDT 24
Peak memory 218312 kb
Host smart-ce51e1e3-1ded-466f-a3a5-704a295236cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008554355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.1
008554355
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.2576639371
Short name T810
Test name
Test status
Simulation time 973209890 ps
CPU time 8.62 seconds
Started Jul 04 06:40:15 PM PDT 24
Finished Jul 04 06:40:24 PM PDT 24
Peak memory 218308 kb
Host smart-56564548-eb35-4bb9-9a68-3ce3c02be77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576639371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.2576639371
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.1557762039
Short name T458
Test name
Test status
Simulation time 235127977 ps
CPU time 2.8 seconds
Started Jul 04 06:40:15 PM PDT 24
Finished Jul 04 06:40:18 PM PDT 24
Peak memory 214696 kb
Host smart-9286220e-3d1a-4710-8813-11489812fc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557762039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1557762039
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.2758300941
Short name T749
Test name
Test status
Simulation time 716408029 ps
CPU time 17.7 seconds
Started Jul 04 06:40:14 PM PDT 24
Finished Jul 04 06:40:32 PM PDT 24
Peak memory 251048 kb
Host smart-66fa41d5-6e29-4aa7-8d41-7889363aa58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758300941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.2758300941
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.1690264189
Short name T577
Test name
Test status
Simulation time 105075019 ps
CPU time 9.2 seconds
Started Jul 04 06:40:15 PM PDT 24
Finished Jul 04 06:40:24 PM PDT 24
Peak memory 250960 kb
Host smart-eccb09e1-4575-4d7a-93f4-a27762ad6af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690264189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.1690264189
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.2127078779
Short name T303
Test name
Test status
Simulation time 9104750687 ps
CPU time 60.07 seconds
Started Jul 04 06:40:23 PM PDT 24
Finished Jul 04 06:41:24 PM PDT 24
Peak memory 251056 kb
Host smart-4fa4393a-37e2-4a0a-835a-3f5e4d7deeb8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127078779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.2127078779
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.1698822043
Short name T140
Test name
Test status
Simulation time 17729517175 ps
CPU time 599.24 seconds
Started Jul 04 06:40:22 PM PDT 24
Finished Jul 04 06:50:22 PM PDT 24
Peak memory 283892 kb
Host smart-68cbb885-c67e-4a48-a39f-05dd4281b302
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1698822043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.1698822043
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2902393960
Short name T224
Test name
Test status
Simulation time 53709229 ps
CPU time 1.06 seconds
Started Jul 04 06:40:14 PM PDT 24
Finished Jul 04 06:40:16 PM PDT 24
Peak memory 217668 kb
Host smart-6b682247-7ca5-4742-bfc5-ba48980f09dc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902393960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.2902393960
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.2523827697
Short name T599
Test name
Test status
Simulation time 33624915 ps
CPU time 1.09 seconds
Started Jul 04 06:44:24 PM PDT 24
Finished Jul 04 06:44:26 PM PDT 24
Peak memory 209092 kb
Host smart-5de57012-118a-49f3-a60c-1cfa632c8e0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523827697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.2523827697
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.3994385519
Short name T396
Test name
Test status
Simulation time 299236499 ps
CPU time 11.14 seconds
Started Jul 04 06:44:23 PM PDT 24
Finished Jul 04 06:44:34 PM PDT 24
Peak memory 226044 kb
Host smart-f3f076f9-263b-4c9f-9632-a7f46c78cfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994385519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.3994385519
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.4004246148
Short name T329
Test name
Test status
Simulation time 1459608628 ps
CPU time 7.44 seconds
Started Jul 04 06:44:25 PM PDT 24
Finished Jul 04 06:44:33 PM PDT 24
Peak memory 217192 kb
Host smart-fba98e6f-3d94-46dc-b361-0a9d4391f4bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004246148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.4004246148
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.2858174058
Short name T345
Test name
Test status
Simulation time 43114008 ps
CPU time 2.12 seconds
Started Jul 04 06:44:15 PM PDT 24
Finished Jul 04 06:44:17 PM PDT 24
Peak memory 222336 kb
Host smart-851084bb-402e-4474-ad73-c2599234f335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858174058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2858174058
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.2260220368
Short name T272
Test name
Test status
Simulation time 565699885 ps
CPU time 14.59 seconds
Started Jul 04 06:44:23 PM PDT 24
Finished Jul 04 06:44:38 PM PDT 24
Peak memory 226012 kb
Host smart-65dc4dc8-83c5-446a-8308-319facd11165
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260220368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.2260220368
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1539468954
Short name T426
Test name
Test status
Simulation time 750321773 ps
CPU time 10.84 seconds
Started Jul 04 06:44:23 PM PDT 24
Finished Jul 04 06:44:34 PM PDT 24
Peak memory 226012 kb
Host smart-24a077c9-dbfc-401b-8fe9-547166f1b3d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539468954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1539468954
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.4067888473
Short name T742
Test name
Test status
Simulation time 1196950884 ps
CPU time 11.29 seconds
Started Jul 04 06:44:23 PM PDT 24
Finished Jul 04 06:44:35 PM PDT 24
Peak memory 218192 kb
Host smart-b430f62a-2eaf-4396-8092-ecb814a26c74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067888473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
4067888473
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.491537683
Short name T590
Test name
Test status
Simulation time 909166197 ps
CPU time 6.8 seconds
Started Jul 04 06:44:23 PM PDT 24
Finished Jul 04 06:44:30 PM PDT 24
Peak memory 225252 kb
Host smart-280f0523-a217-4f9a-9a3b-6e237864cf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491537683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.491537683
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.3057049470
Short name T472
Test name
Test status
Simulation time 34845921 ps
CPU time 2.38 seconds
Started Jul 04 06:44:23 PM PDT 24
Finished Jul 04 06:44:26 PM PDT 24
Peak memory 217712 kb
Host smart-388556e0-4023-49ec-a704-551f82e68cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057049470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3057049470
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.4208678623
Short name T234
Test name
Test status
Simulation time 377573217 ps
CPU time 24.57 seconds
Started Jul 04 06:44:14 PM PDT 24
Finished Jul 04 06:44:39 PM PDT 24
Peak memory 251040 kb
Host smart-f2d2206d-6766-4752-8d28-0709ec874415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208678623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.4208678623
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.1356397981
Short name T754
Test name
Test status
Simulation time 60054980 ps
CPU time 6.5 seconds
Started Jul 04 06:44:14 PM PDT 24
Finished Jul 04 06:44:21 PM PDT 24
Peak memory 247124 kb
Host smart-30080edc-2274-4663-a849-9d3f924481ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356397981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.1356397981
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1365940569
Short name T193
Test name
Test status
Simulation time 12531502114 ps
CPU time 384.81 seconds
Started Jul 04 06:44:24 PM PDT 24
Finished Jul 04 06:50:49 PM PDT 24
Peak memory 277168 kb
Host smart-eb31acde-d02b-486c-86b0-85a72ec7a9e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365940569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1365940569
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2630142846
Short name T584
Test name
Test status
Simulation time 33382594 ps
CPU time 1.51 seconds
Started Jul 04 06:44:38 PM PDT 24
Finished Jul 04 06:44:40 PM PDT 24
Peak memory 208976 kb
Host smart-af12eef5-34d5-4262-83ef-67fb8181ad50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630142846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2630142846
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.1586481746
Short name T765
Test name
Test status
Simulation time 445723009 ps
CPU time 11.25 seconds
Started Jul 04 06:44:24 PM PDT 24
Finished Jul 04 06:44:35 PM PDT 24
Peak memory 218236 kb
Host smart-2c9550df-358b-4040-970e-747792eca457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586481746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.1586481746
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.1877182115
Short name T750
Test name
Test status
Simulation time 889248795 ps
CPU time 8.6 seconds
Started Jul 04 06:44:24 PM PDT 24
Finished Jul 04 06:44:33 PM PDT 24
Peak memory 217436 kb
Host smart-bb7f3748-d5d7-4789-b3e0-e7357ec7931b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877182115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.1877182115
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.2433776550
Short name T589
Test name
Test status
Simulation time 421697064 ps
CPU time 4.08 seconds
Started Jul 04 06:44:24 PM PDT 24
Finished Jul 04 06:44:28 PM PDT 24
Peak memory 222736 kb
Host smart-b8ab8e6a-1592-4748-9cdf-ae93a26d4afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433776550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2433776550
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.865614909
Short name T650
Test name
Test status
Simulation time 2136640665 ps
CPU time 19.01 seconds
Started Jul 04 06:44:24 PM PDT 24
Finished Jul 04 06:44:44 PM PDT 24
Peak memory 218836 kb
Host smart-ebb5cd5f-4329-41cb-91f7-efafa414d13e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865614909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.865614909
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.1486624320
Short name T689
Test name
Test status
Simulation time 812430900 ps
CPU time 15.31 seconds
Started Jul 04 06:44:23 PM PDT 24
Finished Jul 04 06:44:39 PM PDT 24
Peak memory 226052 kb
Host smart-34ac2d5c-6840-4f56-9a53-6a52688a6251
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486624320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.1486624320
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.3101717848
Short name T353
Test name
Test status
Simulation time 348767839 ps
CPU time 10.92 seconds
Started Jul 04 06:44:25 PM PDT 24
Finished Jul 04 06:44:36 PM PDT 24
Peak memory 226056 kb
Host smart-99aedbb6-5fdb-4faa-a268-fa33431d8103
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101717848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
3101717848
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.926710926
Short name T377
Test name
Test status
Simulation time 418339195 ps
CPU time 10.93 seconds
Started Jul 04 06:44:23 PM PDT 24
Finished Jul 04 06:44:34 PM PDT 24
Peak memory 218320 kb
Host smart-c8fe0802-33d7-4cfb-8a6b-08ce64ecf068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926710926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.926710926
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.222583828
Short name T397
Test name
Test status
Simulation time 297280558 ps
CPU time 8.89 seconds
Started Jul 04 06:44:25 PM PDT 24
Finished Jul 04 06:44:34 PM PDT 24
Peak memory 217732 kb
Host smart-a31dc3f1-89cf-4667-b59c-22ab501c82fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222583828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.222583828
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.1712464482
Short name T618
Test name
Test status
Simulation time 1134649745 ps
CPU time 21.11 seconds
Started Jul 04 06:44:23 PM PDT 24
Finished Jul 04 06:44:45 PM PDT 24
Peak memory 250988 kb
Host smart-75481e5b-afdc-4cbe-bbc1-de4a7ffbc0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712464482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1712464482
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.612043988
Short name T286
Test name
Test status
Simulation time 159885273 ps
CPU time 6.34 seconds
Started Jul 04 06:44:25 PM PDT 24
Finished Jul 04 06:44:31 PM PDT 24
Peak memory 250396 kb
Host smart-debf870e-1864-4461-a0a4-fa9d1148a79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612043988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.612043988
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.4185467224
Short name T306
Test name
Test status
Simulation time 20888554667 ps
CPU time 103.68 seconds
Started Jul 04 06:44:23 PM PDT 24
Finished Jul 04 06:46:07 PM PDT 24
Peak memory 279392 kb
Host smart-c2a9e764-8a4c-4e78-ab0e-000426e801a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185467224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.4185467224
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1109577911
Short name T82
Test name
Test status
Simulation time 22707163 ps
CPU time 1 seconds
Started Jul 04 06:44:24 PM PDT 24
Finished Jul 04 06:44:26 PM PDT 24
Peak memory 212032 kb
Host smart-0c5e0cae-803b-4287-a8bd-faf453e61654
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109577911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1109577911
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.49495553
Short name T86
Test name
Test status
Simulation time 73712867 ps
CPU time 0.92 seconds
Started Jul 04 06:44:33 PM PDT 24
Finished Jul 04 06:44:34 PM PDT 24
Peak memory 208968 kb
Host smart-ee0518c5-6727-407a-a907-bc594ea5fe49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49495553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.49495553
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.1427917002
Short name T379
Test name
Test status
Simulation time 1313041397 ps
CPU time 11.09 seconds
Started Jul 04 06:44:32 PM PDT 24
Finished Jul 04 06:44:44 PM PDT 24
Peak memory 218236 kb
Host smart-dcfac485-0734-465e-822e-a4396467e40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427917002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1427917002
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.1847341418
Short name T651
Test name
Test status
Simulation time 1091438796 ps
CPU time 4.82 seconds
Started Jul 04 06:44:33 PM PDT 24
Finished Jul 04 06:44:38 PM PDT 24
Peak memory 217080 kb
Host smart-f0a84c87-a99e-478e-9d3d-8fa9d9fe9320
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847341418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.1847341418
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.3167799313
Short name T283
Test name
Test status
Simulation time 55549094 ps
CPU time 3.06 seconds
Started Jul 04 06:44:32 PM PDT 24
Finished Jul 04 06:44:36 PM PDT 24
Peak memory 222472 kb
Host smart-6e4cb41f-c4b1-489a-8537-47d3a2761bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167799313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.3167799313
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.1288926610
Short name T511
Test name
Test status
Simulation time 317119671 ps
CPU time 14.4 seconds
Started Jul 04 06:44:33 PM PDT 24
Finished Jul 04 06:44:48 PM PDT 24
Peak memory 226008 kb
Host smart-62b18015-8003-4a4a-b469-52cfaf9a91b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288926610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1288926610
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2937164703
Short name T471
Test name
Test status
Simulation time 311937800 ps
CPU time 14.02 seconds
Started Jul 04 06:44:38 PM PDT 24
Finished Jul 04 06:44:52 PM PDT 24
Peak memory 218200 kb
Host smart-104cd646-1430-4fcc-a942-e163db2c891d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937164703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2937164703
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3823190139
Short name T380
Test name
Test status
Simulation time 1450461918 ps
CPU time 8.36 seconds
Started Jul 04 06:44:33 PM PDT 24
Finished Jul 04 06:44:42 PM PDT 24
Peak memory 226008 kb
Host smart-94e7ef9d-35d1-454f-bd3a-6fc9c364286a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823190139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
3823190139
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.1288065191
Short name T740
Test name
Test status
Simulation time 287795104 ps
CPU time 8.44 seconds
Started Jul 04 06:44:31 PM PDT 24
Finished Jul 04 06:44:40 PM PDT 24
Peak memory 218284 kb
Host smart-300383da-218c-49cb-8b0e-8235d6597dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288065191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.1288065191
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.1790989705
Short name T66
Test name
Test status
Simulation time 48761551 ps
CPU time 2.97 seconds
Started Jul 04 06:44:40 PM PDT 24
Finished Jul 04 06:44:43 PM PDT 24
Peak memory 217748 kb
Host smart-30389f58-eb85-4572-a003-3e417f0ca024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790989705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1790989705
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.172112536
Short name T401
Test name
Test status
Simulation time 930716271 ps
CPU time 25.15 seconds
Started Jul 04 06:44:39 PM PDT 24
Finished Jul 04 06:45:05 PM PDT 24
Peak memory 250980 kb
Host smart-7a99f95b-5d43-48a0-aaef-4e18ffd7845a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172112536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.172112536
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.1143675715
Short name T652
Test name
Test status
Simulation time 84614515 ps
CPU time 3.15 seconds
Started Jul 04 06:44:38 PM PDT 24
Finished Jul 04 06:44:42 PM PDT 24
Peak memory 226028 kb
Host smart-4273e9e8-97a4-4604-b1cc-095b008db3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143675715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.1143675715
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.3052547627
Short name T182
Test name
Test status
Simulation time 1976613379 ps
CPU time 14.42 seconds
Started Jul 04 06:44:33 PM PDT 24
Finished Jul 04 06:44:47 PM PDT 24
Peak memory 224456 kb
Host smart-c77eac1b-9e8e-4a08-9674-963891f6e812
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052547627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.3052547627
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.946131197
Short name T477
Test name
Test status
Simulation time 38325558 ps
CPU time 0.94 seconds
Started Jul 04 06:44:31 PM PDT 24
Finished Jul 04 06:44:32 PM PDT 24
Peak memory 211896 kb
Host smart-03af2400-9457-46cb-a0fa-c4681369ff4c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946131197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ct
rl_volatile_unlock_smoke.946131197
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2957964798
Short name T726
Test name
Test status
Simulation time 13402362 ps
CPU time 0.96 seconds
Started Jul 04 06:44:41 PM PDT 24
Finished Jul 04 06:44:42 PM PDT 24
Peak memory 208920 kb
Host smart-58e905ee-fb96-4576-8d3f-d42666e3f909
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957964798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2957964798
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2300249376
Short name T399
Test name
Test status
Simulation time 184938499 ps
CPU time 10.18 seconds
Started Jul 04 06:44:38 PM PDT 24
Finished Jul 04 06:44:49 PM PDT 24
Peak memory 218248 kb
Host smart-121f249e-609d-4029-bf11-d208a8d03727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300249376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2300249376
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.2533082320
Short name T637
Test name
Test status
Simulation time 378568350 ps
CPU time 3.39 seconds
Started Jul 04 06:44:40 PM PDT 24
Finished Jul 04 06:44:44 PM PDT 24
Peak memory 217088 kb
Host smart-40eab1f7-f35f-4c4c-b39f-cd506cbe2093
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533082320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.2533082320
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.1942001938
Short name T291
Test name
Test status
Simulation time 48927005 ps
CPU time 2.46 seconds
Started Jul 04 06:44:38 PM PDT 24
Finished Jul 04 06:44:41 PM PDT 24
Peak memory 218200 kb
Host smart-3e326be1-3b9b-4987-8df7-0e97d693d7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942001938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1942001938
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.277813028
Short name T668
Test name
Test status
Simulation time 770006726 ps
CPU time 9.81 seconds
Started Jul 04 06:44:41 PM PDT 24
Finished Jul 04 06:44:51 PM PDT 24
Peak memory 226092 kb
Host smart-f14bb9f2-a179-4ecd-8858-923c7dda3650
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277813028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.277813028
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.4176795509
Short name T798
Test name
Test status
Simulation time 883686197 ps
CPU time 10.21 seconds
Started Jul 04 06:44:41 PM PDT 24
Finished Jul 04 06:44:52 PM PDT 24
Peak memory 226032 kb
Host smart-5b1d4a8d-2503-431a-8ba8-99e30799c7b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176795509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.4176795509
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2814357604
Short name T644
Test name
Test status
Simulation time 715633449 ps
CPU time 12.09 seconds
Started Jul 04 06:44:39 PM PDT 24
Finished Jul 04 06:44:51 PM PDT 24
Peak memory 225968 kb
Host smart-7324193f-a804-493d-af62-e5664d5614ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814357604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2814357604
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.484441026
Short name T519
Test name
Test status
Simulation time 1513005255 ps
CPU time 7.74 seconds
Started Jul 04 06:44:40 PM PDT 24
Finished Jul 04 06:44:48 PM PDT 24
Peak memory 226012 kb
Host smart-ce658a23-6058-4fad-b1d0-9a0375019388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484441026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.484441026
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.2571890480
Short name T55
Test name
Test status
Simulation time 21282202 ps
CPU time 1.79 seconds
Started Jul 04 06:44:32 PM PDT 24
Finished Jul 04 06:44:34 PM PDT 24
Peak memory 214328 kb
Host smart-77cf3f76-95d1-46e2-8ddd-9c96a5d3ea81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571890480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.2571890480
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.1103719918
Short name T671
Test name
Test status
Simulation time 260053738 ps
CPU time 24.64 seconds
Started Jul 04 06:44:33 PM PDT 24
Finished Jul 04 06:44:58 PM PDT 24
Peak memory 250968 kb
Host smart-ed09bc28-0499-4cf0-a4db-7c0678a7905f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103719918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.1103719918
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.3327330460
Short name T692
Test name
Test status
Simulation time 367389749 ps
CPU time 3.54 seconds
Started Jul 04 06:44:32 PM PDT 24
Finished Jul 04 06:44:35 PM PDT 24
Peak memory 222272 kb
Host smart-d4b1b934-424f-4711-a688-a472015a46da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327330460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3327330460
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.308690020
Short name T352
Test name
Test status
Simulation time 15058317160 ps
CPU time 209.57 seconds
Started Jul 04 06:44:40 PM PDT 24
Finished Jul 04 06:48:10 PM PDT 24
Peak memory 267516 kb
Host smart-bcc556fd-1925-48d8-be50-9871f28221d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308690020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.308690020
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3504989060
Short name T328
Test name
Test status
Simulation time 48660322 ps
CPU time 1.04 seconds
Started Jul 04 06:44:32 PM PDT 24
Finished Jul 04 06:44:33 PM PDT 24
Peak memory 217856 kb
Host smart-fd52d261-093d-474d-9137-55df1ada8304
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504989060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.3504989060
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.3701731981
Short name T535
Test name
Test status
Simulation time 569278503 ps
CPU time 11.34 seconds
Started Jul 04 06:44:38 PM PDT 24
Finished Jul 04 06:44:50 PM PDT 24
Peak memory 226052 kb
Host smart-7ebe88d7-1bf8-4ab3-a80f-d3abd14a6ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701731981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.3701731981
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.3315407966
Short name T588
Test name
Test status
Simulation time 1525320020 ps
CPU time 10.26 seconds
Started Jul 04 06:44:40 PM PDT 24
Finished Jul 04 06:44:51 PM PDT 24
Peak memory 217124 kb
Host smart-bb59f443-df20-4b82-bc99-2fde5af5397c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315407966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.3315407966
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.1076046535
Short name T662
Test name
Test status
Simulation time 65699445 ps
CPU time 3.01 seconds
Started Jul 04 06:44:41 PM PDT 24
Finished Jul 04 06:44:44 PM PDT 24
Peak memory 218240 kb
Host smart-5efe9c73-e66c-4e55-a301-6c43a35e8d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076046535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1076046535
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.2846163168
Short name T98
Test name
Test status
Simulation time 467782589 ps
CPU time 15.09 seconds
Started Jul 04 06:44:48 PM PDT 24
Finished Jul 04 06:45:03 PM PDT 24
Peak memory 226044 kb
Host smart-73baabe1-c18a-4115-a039-02662248256c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846163168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2846163168
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.467537185
Short name T252
Test name
Test status
Simulation time 1586004737 ps
CPU time 12.52 seconds
Started Jul 04 06:44:47 PM PDT 24
Finished Jul 04 06:45:00 PM PDT 24
Peak memory 225960 kb
Host smart-4c46b73d-cb38-4f0b-9fcb-376bb304af0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467537185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_di
gest.467537185
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1955560227
Short name T408
Test name
Test status
Simulation time 370742313 ps
CPU time 6.59 seconds
Started Jul 04 06:44:47 PM PDT 24
Finished Jul 04 06:44:54 PM PDT 24
Peak memory 225980 kb
Host smart-834a5de5-b612-4265-bec8-f9704df705bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955560227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1955560227
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2326717511
Short name T649
Test name
Test status
Simulation time 1175241759 ps
CPU time 8.53 seconds
Started Jul 04 06:44:40 PM PDT 24
Finished Jul 04 06:44:49 PM PDT 24
Peak memory 225304 kb
Host smart-291bde6b-b9ec-45bb-a889-44f9684e3a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326717511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2326717511
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.3205844447
Short name T557
Test name
Test status
Simulation time 130613096 ps
CPU time 2.36 seconds
Started Jul 04 06:44:40 PM PDT 24
Finished Jul 04 06:44:42 PM PDT 24
Peak memory 214236 kb
Host smart-0eb91663-3e1f-4359-9047-3bccdd8cf41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205844447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.3205844447
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3674798049
Short name T226
Test name
Test status
Simulation time 837591898 ps
CPU time 21.91 seconds
Started Jul 04 06:44:41 PM PDT 24
Finished Jul 04 06:45:03 PM PDT 24
Peak memory 250920 kb
Host smart-d1fb1f9c-ea38-4439-ae01-13c89d1219a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674798049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3674798049
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.1960303143
Short name T778
Test name
Test status
Simulation time 363940829 ps
CPU time 7.74 seconds
Started Jul 04 06:44:41 PM PDT 24
Finished Jul 04 06:44:49 PM PDT 24
Peak memory 250988 kb
Host smart-2f8e80d9-a3de-49eb-b0fc-e996e8d77a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960303143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.1960303143
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.4080567169
Short name T603
Test name
Test status
Simulation time 34349383803 ps
CPU time 162.94 seconds
Started Jul 04 06:44:48 PM PDT 24
Finished Jul 04 06:47:31 PM PDT 24
Peak memory 283920 kb
Host smart-004aef1b-2d7d-43c9-9892-1233ccd22c8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080567169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.4080567169
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1649491343
Short name T335
Test name
Test status
Simulation time 12665908 ps
CPU time 0.9 seconds
Started Jul 04 06:44:41 PM PDT 24
Finished Jul 04 06:44:42 PM PDT 24
Peak memory 211908 kb
Host smart-7339b2cc-c0b8-4ea5-ad85-837b6330b290
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649491343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.1649491343
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.4033622831
Short name T656
Test name
Test status
Simulation time 46342777 ps
CPU time 0.98 seconds
Started Jul 04 06:44:55 PM PDT 24
Finished Jul 04 06:44:56 PM PDT 24
Peak memory 209004 kb
Host smart-d06dc69e-6376-413f-a5ff-04f5a3db1937
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033622831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.4033622831
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.464752419
Short name T497
Test name
Test status
Simulation time 749903611 ps
CPU time 17.17 seconds
Started Jul 04 06:44:46 PM PDT 24
Finished Jul 04 06:45:04 PM PDT 24
Peak memory 218220 kb
Host smart-3916bd55-758d-4a86-8ef8-227c8af312d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464752419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.464752419
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.4155388504
Short name T449
Test name
Test status
Simulation time 2299756346 ps
CPU time 8.89 seconds
Started Jul 04 06:44:49 PM PDT 24
Finished Jul 04 06:44:58 PM PDT 24
Peak memory 217552 kb
Host smart-47fe1601-0216-4bf3-8825-5efba71ff6de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155388504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.4155388504
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.507412577
Short name T601
Test name
Test status
Simulation time 320369365 ps
CPU time 4.19 seconds
Started Jul 04 06:44:48 PM PDT 24
Finished Jul 04 06:44:52 PM PDT 24
Peak memory 218248 kb
Host smart-655b76ce-10f2-4f84-95d1-fd42f739dcba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507412577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.507412577
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.914332744
Short name T54
Test name
Test status
Simulation time 452562151 ps
CPU time 9.81 seconds
Started Jul 04 06:44:47 PM PDT 24
Finished Jul 04 06:44:57 PM PDT 24
Peak memory 218460 kb
Host smart-30ed182d-d388-4c50-8507-66ce7805131c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914332744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.914332744
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1569398470
Short name T746
Test name
Test status
Simulation time 452996235 ps
CPU time 9.09 seconds
Started Jul 04 06:44:56 PM PDT 24
Finished Jul 04 06:45:06 PM PDT 24
Peak memory 226060 kb
Host smart-254271cf-b2db-43b8-a2d2-f8a054ea41a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569398470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.1569398470
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.3805979377
Short name T718
Test name
Test status
Simulation time 261665637 ps
CPU time 8.29 seconds
Started Jul 04 06:44:48 PM PDT 24
Finished Jul 04 06:44:56 PM PDT 24
Peak memory 218260 kb
Host smart-60189c97-41ea-4f6d-a00f-08c0cc9d06dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805979377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
3805979377
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.2660745148
Short name T482
Test name
Test status
Simulation time 683415301 ps
CPU time 9.53 seconds
Started Jul 04 06:44:48 PM PDT 24
Finished Jul 04 06:44:58 PM PDT 24
Peak memory 226024 kb
Host smart-f94f3034-38f5-4f25-b330-c2134fc6146b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660745148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2660745148
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.1990225971
Short name T279
Test name
Test status
Simulation time 68391557 ps
CPU time 3.44 seconds
Started Jul 04 06:44:47 PM PDT 24
Finished Jul 04 06:44:51 PM PDT 24
Peak memory 217724 kb
Host smart-c71f7e7f-f7c9-45a9-b744-9b3384baedea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990225971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.1990225971
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1369459237
Short name T612
Test name
Test status
Simulation time 295238868 ps
CPU time 29.81 seconds
Started Jul 04 06:44:47 PM PDT 24
Finished Jul 04 06:45:17 PM PDT 24
Peak memory 250944 kb
Host smart-d2c1111b-23f3-467e-8f99-1ea00dc521be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369459237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1369459237
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.784886940
Short name T359
Test name
Test status
Simulation time 130671048 ps
CPU time 6.41 seconds
Started Jul 04 06:44:47 PM PDT 24
Finished Jul 04 06:44:53 PM PDT 24
Peak memory 250980 kb
Host smart-5abb34eb-c9e3-4841-8233-07c62c84efaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784886940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.784886940
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.251241406
Short name T830
Test name
Test status
Simulation time 5509314197 ps
CPU time 157.66 seconds
Started Jul 04 06:44:53 PM PDT 24
Finished Jul 04 06:47:31 PM PDT 24
Peak memory 250992 kb
Host smart-62b78d32-f01f-43dc-bb67-9e889c3384d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251241406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.251241406
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.2367424768
Short name T340
Test name
Test status
Simulation time 25564635 ps
CPU time 1.04 seconds
Started Jul 04 06:44:48 PM PDT 24
Finished Jul 04 06:44:49 PM PDT 24
Peak memory 217732 kb
Host smart-1a86d93c-8688-4fb2-b589-3ff8d224da42
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367424768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.2367424768
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.1974329494
Short name T319
Test name
Test status
Simulation time 40190922 ps
CPU time 1.22 seconds
Started Jul 04 06:45:00 PM PDT 24
Finished Jul 04 06:45:02 PM PDT 24
Peak memory 208960 kb
Host smart-55903870-7eb5-4ab6-97bb-6689c026036a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974329494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1974329494
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2723925183
Short name T675
Test name
Test status
Simulation time 401031950 ps
CPU time 11.97 seconds
Started Jul 04 06:44:52 PM PDT 24
Finished Jul 04 06:45:05 PM PDT 24
Peak memory 218244 kb
Host smart-e69b1bab-6923-47ea-8651-35c3248418ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723925183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2723925183
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1214200560
Short name T848
Test name
Test status
Simulation time 1550529875 ps
CPU time 5.5 seconds
Started Jul 04 06:44:55 PM PDT 24
Finished Jul 04 06:45:01 PM PDT 24
Peak memory 217760 kb
Host smart-7e0f0f46-ae00-403c-8c56-af53620ca522
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214200560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.1214200560
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.4076985703
Short name T220
Test name
Test status
Simulation time 63879899 ps
CPU time 2.62 seconds
Started Jul 04 06:44:55 PM PDT 24
Finished Jul 04 06:44:58 PM PDT 24
Peak memory 218224 kb
Host smart-bf3bc94c-5cea-45ef-a2e3-a1e99c93e55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076985703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.4076985703
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3088507391
Short name T177
Test name
Test status
Simulation time 319773705 ps
CPU time 15.51 seconds
Started Jul 04 06:44:53 PM PDT 24
Finished Jul 04 06:45:09 PM PDT 24
Peak memory 218896 kb
Host smart-6b951499-68ba-45a0-944a-38b236e40a94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088507391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3088507391
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.566378433
Short name T593
Test name
Test status
Simulation time 460363985 ps
CPU time 13.36 seconds
Started Jul 04 06:44:55 PM PDT 24
Finished Jul 04 06:45:09 PM PDT 24
Peak memory 226040 kb
Host smart-b605ec1a-c14e-4fb2-a3dc-d3f725629374
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566378433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_di
gest.566378433
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3410938610
Short name T804
Test name
Test status
Simulation time 555193232 ps
CPU time 11.04 seconds
Started Jul 04 06:44:55 PM PDT 24
Finished Jul 04 06:45:06 PM PDT 24
Peak memory 218248 kb
Host smart-e91d348b-e7e6-42c2-85d6-72e27d98dcca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410938610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3410938610
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1014436964
Short name T585
Test name
Test status
Simulation time 1571717861 ps
CPU time 10.05 seconds
Started Jul 04 06:44:53 PM PDT 24
Finished Jul 04 06:45:03 PM PDT 24
Peak memory 225528 kb
Host smart-4246224c-7154-4d87-8103-5ae9b7e35cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014436964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1014436964
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.2175848023
Short name T770
Test name
Test status
Simulation time 13296435 ps
CPU time 1.21 seconds
Started Jul 04 06:44:54 PM PDT 24
Finished Jul 04 06:44:55 PM PDT 24
Peak memory 212284 kb
Host smart-ac93b3f9-9539-4e78-801a-063683596d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175848023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2175848023
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3369341602
Short name T287
Test name
Test status
Simulation time 894832910 ps
CPU time 24.05 seconds
Started Jul 04 06:44:56 PM PDT 24
Finished Jul 04 06:45:20 PM PDT 24
Peak memory 251072 kb
Host smart-0c6a8581-4f94-46e7-89bc-c981b0b3a554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369341602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3369341602
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.1995293211
Short name T488
Test name
Test status
Simulation time 247265424 ps
CPU time 3.17 seconds
Started Jul 04 06:44:54 PM PDT 24
Finished Jul 04 06:44:57 PM PDT 24
Peak memory 218148 kb
Host smart-196f0644-5afd-4235-95f7-e57ccf925bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995293211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1995293211
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1015440667
Short name T22
Test name
Test status
Simulation time 9515389665 ps
CPU time 167.06 seconds
Started Jul 04 06:44:52 PM PDT 24
Finished Jul 04 06:47:40 PM PDT 24
Peak memory 285728 kb
Host smart-38ded8ae-67a2-418a-9fcf-c0bda273c17c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015440667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1015440667
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3045533483
Short name T403
Test name
Test status
Simulation time 23316562 ps
CPU time 0.92 seconds
Started Jul 04 06:44:54 PM PDT 24
Finished Jul 04 06:44:56 PM PDT 24
Peak memory 211920 kb
Host smart-5f3c8c1b-528c-42f8-92f8-08be3aa79d44
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045533483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3045533483
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.432936233
Short name T626
Test name
Test status
Simulation time 18718037 ps
CPU time 1.13 seconds
Started Jul 04 06:45:10 PM PDT 24
Finished Jul 04 06:45:11 PM PDT 24
Peak memory 209012 kb
Host smart-5204ee93-151e-4410-833f-9fef915a2808
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432936233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.432936233
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.2190828735
Short name T508
Test name
Test status
Simulation time 1620623655 ps
CPU time 17.83 seconds
Started Jul 04 06:45:00 PM PDT 24
Finished Jul 04 06:45:18 PM PDT 24
Peak memory 218236 kb
Host smart-3e5171d5-5f88-4afa-96b7-c85f92f0606d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190828735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.2190828735
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.1727158618
Short name T160
Test name
Test status
Simulation time 1076404897 ps
CPU time 6.67 seconds
Started Jul 04 06:45:00 PM PDT 24
Finished Jul 04 06:45:07 PM PDT 24
Peak memory 217276 kb
Host smart-e795ecc2-6fa5-4875-ac4a-89b46bd6d9c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727158618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.1727158618
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.3108630598
Short name T667
Test name
Test status
Simulation time 507864132 ps
CPU time 2.55 seconds
Started Jul 04 06:45:02 PM PDT 24
Finished Jul 04 06:45:04 PM PDT 24
Peak memory 218212 kb
Host smart-5c5687ef-20df-4fb1-b009-741b1b6ab678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108630598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.3108630598
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1615801222
Short name T777
Test name
Test status
Simulation time 2307082345 ps
CPU time 11.54 seconds
Started Jul 04 06:45:02 PM PDT 24
Finished Jul 04 06:45:13 PM PDT 24
Peak memory 226096 kb
Host smart-003edca5-94aa-4176-b5ea-6bc73a247209
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615801222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1615801222
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.4046028505
Short name T242
Test name
Test status
Simulation time 184686680 ps
CPU time 7.73 seconds
Started Jul 04 06:45:02 PM PDT 24
Finished Jul 04 06:45:10 PM PDT 24
Peak memory 218248 kb
Host smart-6c41ba9b-01ff-4072-9fff-3123e82f0106
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046028505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
4046028505
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3812620020
Short name T43
Test name
Test status
Simulation time 1259202686 ps
CPU time 12.67 seconds
Started Jul 04 06:45:02 PM PDT 24
Finished Jul 04 06:45:15 PM PDT 24
Peak memory 226044 kb
Host smart-ac0999ab-fb97-4f17-b663-72a714098463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812620020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3812620020
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.1390758954
Short name T78
Test name
Test status
Simulation time 135486231 ps
CPU time 1.95 seconds
Started Jul 04 06:44:59 PM PDT 24
Finished Jul 04 06:45:02 PM PDT 24
Peak memory 217728 kb
Host smart-845d796e-403b-41f2-84b2-32a56b1eef21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390758954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.1390758954
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.2495436604
Short name T544
Test name
Test status
Simulation time 968300438 ps
CPU time 16.57 seconds
Started Jul 04 06:45:01 PM PDT 24
Finished Jul 04 06:45:18 PM PDT 24
Peak memory 250980 kb
Host smart-7da2f450-e299-42d6-a36a-2a098426e22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495436604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.2495436604
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.1070660151
Short name T263
Test name
Test status
Simulation time 202129757 ps
CPU time 6.95 seconds
Started Jul 04 06:45:01 PM PDT 24
Finished Jul 04 06:45:08 PM PDT 24
Peak memory 246856 kb
Host smart-049b7aa4-2e7c-4726-aaee-1740e451a04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070660151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.1070660151
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.300994016
Short name T843
Test name
Test status
Simulation time 4245885148 ps
CPU time 122.37 seconds
Started Jul 04 06:45:00 PM PDT 24
Finished Jul 04 06:47:03 PM PDT 24
Peak memory 271824 kb
Host smart-0a4645a6-e6b6-4cba-8eea-989a0123174c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300994016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.300994016
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2190158039
Short name T191
Test name
Test status
Simulation time 58221404 ps
CPU time 0.84 seconds
Started Jul 04 06:45:02 PM PDT 24
Finished Jul 04 06:45:03 PM PDT 24
Peak memory 211912 kb
Host smart-96b6bf0c-95e0-4f4c-ad0d-e76a62811ecf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190158039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2190158039
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.3681377874
Short name T672
Test name
Test status
Simulation time 67271934 ps
CPU time 0.84 seconds
Started Jul 04 06:45:11 PM PDT 24
Finished Jul 04 06:45:12 PM PDT 24
Peak memory 208780 kb
Host smart-83199eea-3d1b-4599-9943-cc088613e703
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681377874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3681377874
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1394635506
Short name T669
Test name
Test status
Simulation time 2483245399 ps
CPU time 12.06 seconds
Started Jul 04 06:45:09 PM PDT 24
Finished Jul 04 06:45:21 PM PDT 24
Peak memory 218296 kb
Host smart-8cb5a216-3723-4981-bc05-0a504b9a07f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394635506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1394635506
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.1304951310
Short name T308
Test name
Test status
Simulation time 556367710 ps
CPU time 13.21 seconds
Started Jul 04 06:45:12 PM PDT 24
Finished Jul 04 06:45:26 PM PDT 24
Peak memory 217240 kb
Host smart-0994ba9e-6981-4805-8603-af1683198b78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304951310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.1304951310
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.3220495834
Short name T560
Test name
Test status
Simulation time 393699959 ps
CPU time 2.85 seconds
Started Jul 04 06:45:09 PM PDT 24
Finished Jul 04 06:45:12 PM PDT 24
Peak memory 222364 kb
Host smart-4b2991ca-60db-4f23-95b7-b6d516a3afa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220495834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3220495834
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.2776548913
Short name T428
Test name
Test status
Simulation time 3130231761 ps
CPU time 21.78 seconds
Started Jul 04 06:45:10 PM PDT 24
Finished Jul 04 06:45:31 PM PDT 24
Peak memory 226108 kb
Host smart-04abc4d7-3cf6-444c-a457-2f380bd43746
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776548913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2776548913
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.1417303268
Short name T447
Test name
Test status
Simulation time 564588207 ps
CPU time 15.41 seconds
Started Jul 04 06:45:11 PM PDT 24
Finished Jul 04 06:45:27 PM PDT 24
Peak memory 226028 kb
Host smart-5f09e6de-6993-46e7-a057-ebe992d18a6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417303268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.1417303268
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1474152603
Short name T360
Test name
Test status
Simulation time 1386735289 ps
CPU time 10.29 seconds
Started Jul 04 06:45:10 PM PDT 24
Finished Jul 04 06:45:20 PM PDT 24
Peak memory 225352 kb
Host smart-503b1303-9a51-45ce-9596-4b54e789038e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474152603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1474152603
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.3981574149
Short name T342
Test name
Test status
Simulation time 1044935883 ps
CPU time 10.13 seconds
Started Jul 04 06:45:11 PM PDT 24
Finished Jul 04 06:45:21 PM PDT 24
Peak memory 224692 kb
Host smart-ec1f6083-5900-4f25-9a83-5080132faf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981574149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3981574149
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.1503720274
Short name T842
Test name
Test status
Simulation time 31197289 ps
CPU time 1.76 seconds
Started Jul 04 06:45:10 PM PDT 24
Finished Jul 04 06:45:12 PM PDT 24
Peak memory 214216 kb
Host smart-32329d6f-d062-467c-ba70-7d6d102489a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503720274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1503720274
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1075766374
Short name T468
Test name
Test status
Simulation time 302018462 ps
CPU time 30.23 seconds
Started Jul 04 06:45:11 PM PDT 24
Finished Jul 04 06:45:41 PM PDT 24
Peak memory 250976 kb
Host smart-11be2343-5eed-4f07-afe6-9726875273e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075766374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1075766374
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3368417928
Short name T483
Test name
Test status
Simulation time 80927314 ps
CPU time 7.51 seconds
Started Jul 04 06:45:10 PM PDT 24
Finished Jul 04 06:45:18 PM PDT 24
Peak memory 246284 kb
Host smart-e51a4dd6-da28-4aff-b2db-b7b0647c9c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368417928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3368417928
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.268122645
Short name T169
Test name
Test status
Simulation time 9598199899 ps
CPU time 144.17 seconds
Started Jul 04 06:45:11 PM PDT 24
Finished Jul 04 06:47:35 PM PDT 24
Peak memory 283420 kb
Host smart-20a6a58c-218d-4f42-a9cc-85ee0f7c9ebf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268122645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.268122645
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.1624958477
Short name T450
Test name
Test status
Simulation time 23488285769 ps
CPU time 524.95 seconds
Started Jul 04 06:45:10 PM PDT 24
Finished Jul 04 06:53:56 PM PDT 24
Peak memory 422132 kb
Host smart-e2937d92-2496-4bf7-81db-8665e22d8541
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1624958477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.1624958477
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3963373849
Short name T332
Test name
Test status
Simulation time 46526245 ps
CPU time 0.84 seconds
Started Jul 04 06:45:12 PM PDT 24
Finished Jul 04 06:45:13 PM PDT 24
Peak memory 217740 kb
Host smart-793bbd66-1d3d-47bf-ae17-988efaccfe68
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963373849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3963373849
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.848939660
Short name T629
Test name
Test status
Simulation time 22641783 ps
CPU time 0.96 seconds
Started Jul 04 06:45:17 PM PDT 24
Finished Jul 04 06:45:18 PM PDT 24
Peak memory 208940 kb
Host smart-d901480c-fd8d-4bed-9288-7826ff8e9d6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848939660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.848939660
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.1098427241
Short name T253
Test name
Test status
Simulation time 285116058 ps
CPU time 13.53 seconds
Started Jul 04 06:45:19 PM PDT 24
Finished Jul 04 06:45:33 PM PDT 24
Peak memory 226036 kb
Host smart-ce5a882d-993f-4d6a-9620-f53d0b4ade6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098427241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.1098427241
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.563420759
Short name T415
Test name
Test status
Simulation time 121040398 ps
CPU time 1.99 seconds
Started Jul 04 06:45:17 PM PDT 24
Finished Jul 04 06:45:20 PM PDT 24
Peak memory 217068 kb
Host smart-891361ef-7d03-491b-8249-926b847880bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563420759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.563420759
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.562927196
Short name T277
Test name
Test status
Simulation time 130900224 ps
CPU time 5.7 seconds
Started Jul 04 06:45:16 PM PDT 24
Finished Jul 04 06:45:22 PM PDT 24
Peak memory 222748 kb
Host smart-fba84b30-3b21-4942-a34f-14c7b3586288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562927196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.562927196
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.121977467
Short name T455
Test name
Test status
Simulation time 3618706026 ps
CPU time 13.26 seconds
Started Jul 04 06:45:16 PM PDT 24
Finished Jul 04 06:45:29 PM PDT 24
Peak memory 226044 kb
Host smart-b42db8e2-7940-48ef-9e09-8924af6aef10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121977467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.121977467
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.4011898376
Short name T409
Test name
Test status
Simulation time 1777787911 ps
CPU time 19.44 seconds
Started Jul 04 06:45:18 PM PDT 24
Finished Jul 04 06:45:38 PM PDT 24
Peak memory 226032 kb
Host smart-5fbcfd22-a0fb-4c57-a60e-e1617e62d397
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011898376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.4011898376
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.3244474504
Short name T446
Test name
Test status
Simulation time 262997730 ps
CPU time 7.2 seconds
Started Jul 04 06:45:17 PM PDT 24
Finished Jul 04 06:45:25 PM PDT 24
Peak memory 226032 kb
Host smart-169301a7-0714-4636-ba47-5b6c6328ed1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244474504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
3244474504
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.918373642
Short name T556
Test name
Test status
Simulation time 3654507640 ps
CPU time 6.64 seconds
Started Jul 04 06:45:17 PM PDT 24
Finished Jul 04 06:45:24 PM PDT 24
Peak memory 224936 kb
Host smart-0615304f-c445-48c8-9f5e-979230764c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918373642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.918373642
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.2403352190
Short name T16
Test name
Test status
Simulation time 186100496 ps
CPU time 2.52 seconds
Started Jul 04 06:45:09 PM PDT 24
Finished Jul 04 06:45:12 PM PDT 24
Peak memory 217700 kb
Host smart-24430db9-499f-4e08-8d66-7aaa546db081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403352190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.2403352190
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1205027783
Short name T661
Test name
Test status
Simulation time 264415534 ps
CPU time 24.24 seconds
Started Jul 04 06:45:16 PM PDT 24
Finished Jul 04 06:45:41 PM PDT 24
Peak memory 250944 kb
Host smart-cc0984b7-deb9-49c6-afc8-d787eb93aff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205027783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1205027783
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.2178311549
Short name T321
Test name
Test status
Simulation time 368118416 ps
CPU time 8.12 seconds
Started Jul 04 06:45:17 PM PDT 24
Finished Jul 04 06:45:26 PM PDT 24
Peak memory 250384 kb
Host smart-849ea6c8-c5f6-4043-b7d1-a63c234e7d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178311549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.2178311549
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3469248849
Short name T476
Test name
Test status
Simulation time 213093791234 ps
CPU time 666.69 seconds
Started Jul 04 06:45:15 PM PDT 24
Finished Jul 04 06:56:22 PM PDT 24
Peak memory 562340 kb
Host smart-eb33d8e3-fc46-4815-a211-970ea399f6b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469248849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3469248849
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1487619306
Short name T566
Test name
Test status
Simulation time 75446794 ps
CPU time 0.89 seconds
Started Jul 04 06:45:09 PM PDT 24
Finished Jul 04 06:45:10 PM PDT 24
Peak memory 211848 kb
Host smart-1c4ecbc0-ac7c-4d31-8904-3675facccfb9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487619306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1487619306
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3746272516
Short name T705
Test name
Test status
Simulation time 53891300 ps
CPU time 1.06 seconds
Started Jul 04 06:40:31 PM PDT 24
Finished Jul 04 06:40:32 PM PDT 24
Peak memory 209180 kb
Host smart-a459e813-caaf-4560-91ed-c29f2b89ff4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746272516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3746272516
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1285089998
Short name T486
Test name
Test status
Simulation time 37393237 ps
CPU time 0.79 seconds
Started Jul 04 06:40:23 PM PDT 24
Finished Jul 04 06:40:24 PM PDT 24
Peak memory 208968 kb
Host smart-117d1072-0046-40c0-af7c-dac538ba8ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285089998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1285089998
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.1516120056
Short name T363
Test name
Test status
Simulation time 279845507 ps
CPU time 12.29 seconds
Started Jul 04 06:40:22 PM PDT 24
Finished Jul 04 06:40:34 PM PDT 24
Peak memory 226096 kb
Host smart-313d13a6-3e6d-4747-9076-8896825ff303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516120056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1516120056
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3550783149
Short name T736
Test name
Test status
Simulation time 224456479 ps
CPU time 3.4 seconds
Started Jul 04 06:40:34 PM PDT 24
Finished Jul 04 06:40:37 PM PDT 24
Peak memory 217248 kb
Host smart-addb4cad-aca9-40d8-a272-e22b8d703529
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550783149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3550783149
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1133061855
Short name T525
Test name
Test status
Simulation time 17247548509 ps
CPU time 124.16 seconds
Started Jul 04 06:40:30 PM PDT 24
Finished Jul 04 06:42:34 PM PDT 24
Peak memory 218964 kb
Host smart-288df010-132f-4716-bee7-9ca34a073478
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133061855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1133061855
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.1735340785
Short name T387
Test name
Test status
Simulation time 364116705 ps
CPU time 9.39 seconds
Started Jul 04 06:40:31 PM PDT 24
Finished Jul 04 06:40:40 PM PDT 24
Peak memory 217596 kb
Host smart-a87d32e9-7e76-4a63-b453-bec629ab05f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735340785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.1
735340785
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3749527205
Short name T478
Test name
Test status
Simulation time 1638850216 ps
CPU time 13.12 seconds
Started Jul 04 06:40:32 PM PDT 24
Finished Jul 04 06:40:45 PM PDT 24
Peak memory 223264 kb
Host smart-44a0fc7c-bfd0-4649-a47f-659ba7b542f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749527205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3749527205
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2734459016
Short name T270
Test name
Test status
Simulation time 11099288605 ps
CPU time 11 seconds
Started Jul 04 06:40:32 PM PDT 24
Finished Jul 04 06:40:43 PM PDT 24
Peak memory 217788 kb
Host smart-cea494c2-8a9b-4e6f-9702-73bffcacfa68
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734459016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.2734459016
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1808631980
Short name T417
Test name
Test status
Simulation time 3148531562 ps
CPU time 9.01 seconds
Started Jul 04 06:40:24 PM PDT 24
Finished Jul 04 06:40:33 PM PDT 24
Peak memory 217824 kb
Host smart-54e75075-1275-4a56-8785-2919bd1d939e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808631980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1808631980
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3613964508
Short name T529
Test name
Test status
Simulation time 4715077249 ps
CPU time 52.43 seconds
Started Jul 04 06:40:23 PM PDT 24
Finished Jul 04 06:41:15 PM PDT 24
Peak memory 271872 kb
Host smart-5a60c088-3398-4885-b553-c6e6e38c32d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613964508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3613964508
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2617058173
Short name T464
Test name
Test status
Simulation time 457858651 ps
CPU time 18.33 seconds
Started Jul 04 06:40:22 PM PDT 24
Finished Jul 04 06:40:41 PM PDT 24
Peak memory 247792 kb
Host smart-5b413092-806f-4f8f-823a-4c4ed670dcfb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617058173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2617058173
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.852623648
Short name T821
Test name
Test status
Simulation time 139727949 ps
CPU time 2.73 seconds
Started Jul 04 06:40:22 PM PDT 24
Finished Jul 04 06:40:25 PM PDT 24
Peak memory 218208 kb
Host smart-b2b2cfbe-d44e-460e-a425-e95a604e732a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852623648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.852623648
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.460214710
Short name T32
Test name
Test status
Simulation time 154399721 ps
CPU time 10.88 seconds
Started Jul 04 06:40:22 PM PDT 24
Finished Jul 04 06:40:33 PM PDT 24
Peak memory 214568 kb
Host smart-4fb165f8-eb00-483a-9878-e6a1839ff7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460214710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.460214710
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2331184140
Short name T489
Test name
Test status
Simulation time 910474487 ps
CPU time 14.56 seconds
Started Jul 04 06:40:30 PM PDT 24
Finished Jul 04 06:40:44 PM PDT 24
Peak memory 226048 kb
Host smart-7b952cd9-e2fc-47ba-9f25-44c22325676a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331184140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2331184140
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2004719781
Short name T684
Test name
Test status
Simulation time 1579394706 ps
CPU time 16.82 seconds
Started Jul 04 06:40:30 PM PDT 24
Finished Jul 04 06:40:48 PM PDT 24
Peak memory 225944 kb
Host smart-29318c9f-2679-4f76-b64d-6a17ce122f3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004719781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.2004719781
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.2999376041
Short name T420
Test name
Test status
Simulation time 251920110 ps
CPU time 7.48 seconds
Started Jul 04 06:40:31 PM PDT 24
Finished Jul 04 06:40:39 PM PDT 24
Peak memory 226052 kb
Host smart-a79c0524-4048-4c61-86d8-fc665459c8da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999376041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.2
999376041
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.3528488808
Short name T792
Test name
Test status
Simulation time 78737539 ps
CPU time 5.08 seconds
Started Jul 04 06:40:23 PM PDT 24
Finished Jul 04 06:40:29 PM PDT 24
Peak memory 217736 kb
Host smart-e371a83d-7d69-44b2-a816-ddfd261baa90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528488808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3528488808
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.3800107813
Short name T102
Test name
Test status
Simulation time 857357267 ps
CPU time 28.08 seconds
Started Jul 04 06:40:23 PM PDT 24
Finished Jul 04 06:40:52 PM PDT 24
Peak memory 250960 kb
Host smart-75134da7-cfe6-4250-86d6-1d137a75563d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800107813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3800107813
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.150202522
Short name T839
Test name
Test status
Simulation time 823524706 ps
CPU time 7.2 seconds
Started Jul 04 06:40:23 PM PDT 24
Finished Jul 04 06:40:31 PM PDT 24
Peak memory 250960 kb
Host smart-b4860f42-9b1c-4fcb-910e-c33609ab54dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150202522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.150202522
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.200849987
Short name T172
Test name
Test status
Simulation time 2510107980 ps
CPU time 49.38 seconds
Started Jul 04 06:40:30 PM PDT 24
Finished Jul 04 06:41:20 PM PDT 24
Peak memory 250088 kb
Host smart-532b0f4b-3fb0-4157-b0bf-597db17df004
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200849987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.200849987
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.739275767
Short name T774
Test name
Test status
Simulation time 12471895 ps
CPU time 0.88 seconds
Started Jul 04 06:40:22 PM PDT 24
Finished Jul 04 06:40:23 PM PDT 24
Peak memory 211928 kb
Host smart-3a1ed1a4-a396-4a26-b235-7f52ddc15310
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739275767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr
l_volatile_unlock_smoke.739275767
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.863532925
Short name T844
Test name
Test status
Simulation time 26970669 ps
CPU time 1.35 seconds
Started Jul 04 06:40:40 PM PDT 24
Finished Jul 04 06:40:42 PM PDT 24
Peak memory 209116 kb
Host smart-fe577e1b-3975-42e0-9337-825108b087a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863532925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.863532925
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.1316861616
Short name T251
Test name
Test status
Simulation time 36593823 ps
CPU time 0.8 seconds
Started Jul 04 06:40:40 PM PDT 24
Finished Jul 04 06:40:41 PM PDT 24
Peak memory 208904 kb
Host smart-2f6dc044-8aed-4047-a9be-9ac22f956e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316861616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.1316861616
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.1522623434
Short name T38
Test name
Test status
Simulation time 280553569 ps
CPU time 10.23 seconds
Started Jul 04 06:40:39 PM PDT 24
Finished Jul 04 06:40:50 PM PDT 24
Peak memory 226040 kb
Host smart-b58ea0c7-74e2-4f9c-b00d-422ca55cd301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522623434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1522623434
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.3825820440
Short name T530
Test name
Test status
Simulation time 191854531 ps
CPU time 1.61 seconds
Started Jul 04 06:40:42 PM PDT 24
Finished Jul 04 06:40:44 PM PDT 24
Peak memory 217072 kb
Host smart-e7290a14-72db-4671-9019-0104f07f6dcb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825820440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.3825820440
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.2123175265
Short name T812
Test name
Test status
Simulation time 7708169437 ps
CPU time 36.3 seconds
Started Jul 04 06:40:41 PM PDT 24
Finished Jul 04 06:41:17 PM PDT 24
Peak memory 226220 kb
Host smart-6c5149b7-6fc3-40be-83da-0b907af68bb1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123175265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.2123175265
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.3364663385
Short name T797
Test name
Test status
Simulation time 2155657894 ps
CPU time 20.15 seconds
Started Jul 04 06:40:42 PM PDT 24
Finished Jul 04 06:41:02 PM PDT 24
Peak memory 217848 kb
Host smart-34751554-88b5-4d32-a508-475c9ea0e508
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364663385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.3
364663385
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3846363298
Short name T487
Test name
Test status
Simulation time 348913807 ps
CPU time 11.18 seconds
Started Jul 04 06:40:39 PM PDT 24
Finished Jul 04 06:40:51 PM PDT 24
Peak memory 223264 kb
Host smart-d2c07d68-8567-4fc8-87d5-5c337b11ea21
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846363298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.3846363298
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3337925883
Short name T613
Test name
Test status
Simulation time 2318251691 ps
CPU time 8.82 seconds
Started Jul 04 06:40:41 PM PDT 24
Finished Jul 04 06:40:50 PM PDT 24
Peak memory 217892 kb
Host smart-35499cce-82b0-4304-9cf4-da0429e78cb7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337925883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.3337925883
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.903627016
Short name T421
Test name
Test status
Simulation time 1350048949 ps
CPU time 2.01 seconds
Started Jul 04 06:40:41 PM PDT 24
Finished Jul 04 06:40:43 PM PDT 24
Peak memory 217688 kb
Host smart-6edcd0d3-8353-40b3-adbf-1fdf28e163de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903627016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.903627016
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.3594097040
Short name T17
Test name
Test status
Simulation time 34307594843 ps
CPU time 151.25 seconds
Started Jul 04 06:40:41 PM PDT 24
Finished Jul 04 06:43:12 PM PDT 24
Peak memory 283824 kb
Host smart-7adf7ca9-d491-4337-b358-e0b00d3febd1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594097040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.3594097040
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.276564069
Short name T541
Test name
Test status
Simulation time 2890638627 ps
CPU time 14.67 seconds
Started Jul 04 06:40:41 PM PDT 24
Finished Jul 04 06:40:56 PM PDT 24
Peak memory 250556 kb
Host smart-9429b3b1-fa20-4074-966f-5760fd24644b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276564069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_state_post_trans.276564069
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.729225661
Short name T524
Test name
Test status
Simulation time 201552396 ps
CPU time 3.82 seconds
Started Jul 04 06:40:39 PM PDT 24
Finished Jul 04 06:40:43 PM PDT 24
Peak memory 222648 kb
Host smart-535b1af4-cde1-4bca-961e-fea5db12bce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729225661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.729225661
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2112770027
Short name T196
Test name
Test status
Simulation time 756537848 ps
CPU time 12.59 seconds
Started Jul 04 06:40:40 PM PDT 24
Finished Jul 04 06:40:53 PM PDT 24
Peak memory 214092 kb
Host smart-7b13b0e0-1e38-41ea-b926-42b570bfa755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112770027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2112770027
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.890368780
Short name T712
Test name
Test status
Simulation time 4372675113 ps
CPU time 15.99 seconds
Started Jul 04 06:40:39 PM PDT 24
Finished Jul 04 06:40:56 PM PDT 24
Peak memory 226064 kb
Host smart-a6a726f1-acfa-439a-b71d-da30a78bae6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890368780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dig
est.890368780
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3337265734
Short name T799
Test name
Test status
Simulation time 337823267 ps
CPU time 10.16 seconds
Started Jul 04 06:40:40 PM PDT 24
Finished Jul 04 06:40:50 PM PDT 24
Peak memory 218224 kb
Host smart-5d64f809-e3b4-445d-ae1c-dacd8bddac74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337265734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3
337265734
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.11871392
Short name T176
Test name
Test status
Simulation time 2090134136 ps
CPU time 10.13 seconds
Started Jul 04 06:40:39 PM PDT 24
Finished Jul 04 06:40:50 PM PDT 24
Peak memory 225804 kb
Host smart-7e738e5e-d89a-46d5-875c-384a65650f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11871392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.11871392
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.556806956
Short name T731
Test name
Test status
Simulation time 131353119 ps
CPU time 1.7 seconds
Started Jul 04 06:40:30 PM PDT 24
Finished Jul 04 06:40:32 PM PDT 24
Peak memory 217708 kb
Host smart-e371be6e-5215-40c6-b81a-0cf92f431813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556806956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.556806956
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.4194462455
Short name T146
Test name
Test status
Simulation time 201050756 ps
CPU time 21.24 seconds
Started Jul 04 06:40:32 PM PDT 24
Finished Jul 04 06:40:53 PM PDT 24
Peak memory 250988 kb
Host smart-fcf9377b-3ea7-47d6-ac73-81021a2493a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194462455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.4194462455
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2063741715
Short name T192
Test name
Test status
Simulation time 103829711 ps
CPU time 6.97 seconds
Started Jul 04 06:40:33 PM PDT 24
Finished Jul 04 06:40:40 PM PDT 24
Peak memory 250556 kb
Host smart-18b137ab-7047-46a9-a659-eb1eefd7a1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063741715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2063741715
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.3025951371
Short name T570
Test name
Test status
Simulation time 3915886645 ps
CPU time 124.61 seconds
Started Jul 04 06:40:40 PM PDT 24
Finished Jul 04 06:42:45 PM PDT 24
Peak memory 283824 kb
Host smart-16d01ae9-9cc8-4af1-8322-9c0946cf7743
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025951371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.3025951371
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2618714027
Short name T491
Test name
Test status
Simulation time 39370735 ps
CPU time 0.88 seconds
Started Jul 04 06:40:30 PM PDT 24
Finished Jul 04 06:40:32 PM PDT 24
Peak memory 211872 kb
Host smart-60fef4c8-1b12-4d09-90e7-61881bf018d0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618714027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2618714027
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.3407284548
Short name T723
Test name
Test status
Simulation time 163359874 ps
CPU time 1.26 seconds
Started Jul 04 06:40:55 PM PDT 24
Finished Jul 04 06:40:56 PM PDT 24
Peak memory 209060 kb
Host smart-a0235f4c-a873-45be-90b8-44d3c9ab318a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407284548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.3407284548
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.4134616711
Short name T808
Test name
Test status
Simulation time 10838362 ps
CPU time 0.95 seconds
Started Jul 04 06:40:55 PM PDT 24
Finished Jul 04 06:40:56 PM PDT 24
Peak memory 209008 kb
Host smart-fc3d0b96-e136-40d9-96a6-8fd3e5579535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134616711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.4134616711
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.3589896002
Short name T405
Test name
Test status
Simulation time 882642859 ps
CPU time 18.58 seconds
Started Jul 04 06:40:56 PM PDT 24
Finished Jul 04 06:41:15 PM PDT 24
Peak memory 225980 kb
Host smart-53160c7e-ded1-4b4b-9d88-352421e8d57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589896002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3589896002
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.172997855
Short name T30
Test name
Test status
Simulation time 846233658 ps
CPU time 7.84 seconds
Started Jul 04 06:40:55 PM PDT 24
Finished Jul 04 06:41:03 PM PDT 24
Peak memory 217512 kb
Host smart-46ba5a0e-5909-40c3-b492-37b46b85b85a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172997855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.172997855
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2454271026
Short name T528
Test name
Test status
Simulation time 6725078618 ps
CPU time 29.32 seconds
Started Jul 04 06:40:52 PM PDT 24
Finished Jul 04 06:41:22 PM PDT 24
Peak memory 218920 kb
Host smart-c03dba12-5919-4320-8ea0-c710ecd5f701
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454271026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2454271026
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.2596666075
Short name T60
Test name
Test status
Simulation time 5665122912 ps
CPU time 13.32 seconds
Started Jul 04 06:40:54 PM PDT 24
Finished Jul 04 06:41:07 PM PDT 24
Peak memory 217872 kb
Host smart-f606a00e-3eb6-4605-b205-3ed99543858d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596666075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.2
596666075
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.3776659521
Short name T430
Test name
Test status
Simulation time 6558831676 ps
CPU time 11.27 seconds
Started Jul 04 06:40:52 PM PDT 24
Finished Jul 04 06:41:04 PM PDT 24
Peak memory 218312 kb
Host smart-8d4338cb-86bf-49b6-8134-de410d6caaf1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776659521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.3776659521
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.701730329
Short name T457
Test name
Test status
Simulation time 5451944297 ps
CPU time 21.32 seconds
Started Jul 04 06:40:53 PM PDT 24
Finished Jul 04 06:41:15 PM PDT 24
Peak memory 217768 kb
Host smart-9e166449-8d56-4032-9a94-765372e43379
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701730329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.701730329
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1422875917
Short name T759
Test name
Test status
Simulation time 233048252 ps
CPU time 6.76 seconds
Started Jul 04 06:40:54 PM PDT 24
Finished Jul 04 06:41:01 PM PDT 24
Peak memory 217708 kb
Host smart-4c4be617-3f46-4258-879e-8e10bedb92c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422875917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1422875917
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.270281363
Short name T536
Test name
Test status
Simulation time 5861665561 ps
CPU time 86.39 seconds
Started Jul 04 06:40:53 PM PDT 24
Finished Jul 04 06:42:20 PM PDT 24
Peak memory 267564 kb
Host smart-2931b936-abed-4e90-b899-f88144aa287c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270281363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_state_failure.270281363
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.3152535369
Short name T288
Test name
Test status
Simulation time 963830131 ps
CPU time 30.27 seconds
Started Jul 04 06:40:57 PM PDT 24
Finished Jul 04 06:41:28 PM PDT 24
Peak memory 250896 kb
Host smart-8314f147-33ac-40b4-8a82-36ab30991e5b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152535369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.3152535369
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1056442596
Short name T803
Test name
Test status
Simulation time 186191709 ps
CPU time 4.31 seconds
Started Jul 04 06:40:54 PM PDT 24
Finished Jul 04 06:40:58 PM PDT 24
Peak memory 222296 kb
Host smart-5ed155f8-5f4a-4580-976b-d07dcfce395f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056442596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1056442596
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.441084245
Short name T493
Test name
Test status
Simulation time 4572153035 ps
CPU time 19.69 seconds
Started Jul 04 06:40:55 PM PDT 24
Finished Jul 04 06:41:15 PM PDT 24
Peak memory 217804 kb
Host smart-46d3ea97-4cec-41b0-9d44-822311ce69d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441084245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.441084245
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.2350969895
Short name T775
Test name
Test status
Simulation time 1306870438 ps
CPU time 9.89 seconds
Started Jul 04 06:40:54 PM PDT 24
Finished Jul 04 06:41:04 PM PDT 24
Peak memory 225980 kb
Host smart-61dbad84-77d4-4aab-be1d-8746965c3e12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350969895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2350969895
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2131888255
Short name T801
Test name
Test status
Simulation time 1268729114 ps
CPU time 8.71 seconds
Started Jul 04 06:40:53 PM PDT 24
Finished Jul 04 06:41:02 PM PDT 24
Peak memory 226032 kb
Host smart-c9839089-4ad4-4641-8552-1c5bbb791c23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131888255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2131888255
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.960602938
Short name T452
Test name
Test status
Simulation time 1078569245 ps
CPU time 7.57 seconds
Started Jul 04 06:40:54 PM PDT 24
Finished Jul 04 06:41:01 PM PDT 24
Peak memory 226052 kb
Host smart-6216c1b5-bbb5-44dd-b04c-5df53d813034
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960602938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.960602938
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2852556436
Short name T851
Test name
Test status
Simulation time 1417712969 ps
CPU time 10.33 seconds
Started Jul 04 06:40:53 PM PDT 24
Finished Jul 04 06:41:04 PM PDT 24
Peak memory 226044 kb
Host smart-e3bbacf5-56e6-458e-b409-2ed69fb6c1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852556436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2852556436
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.347225627
Short name T429
Test name
Test status
Simulation time 222532760 ps
CPU time 2.62 seconds
Started Jul 04 06:40:40 PM PDT 24
Finished Jul 04 06:40:43 PM PDT 24
Peak memory 214512 kb
Host smart-b3b46343-50bc-41fd-a773-1a0b4de0fa2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347225627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.347225627
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3357930790
Short name T223
Test name
Test status
Simulation time 210487273 ps
CPU time 21.93 seconds
Started Jul 04 06:40:55 PM PDT 24
Finished Jul 04 06:41:17 PM PDT 24
Peak memory 250880 kb
Host smart-a6196f07-b1b2-414c-af50-46b0d74c5b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357930790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3357930790
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.968258429
Short name T416
Test name
Test status
Simulation time 211686623 ps
CPU time 3.05 seconds
Started Jul 04 06:40:51 PM PDT 24
Finished Jul 04 06:40:54 PM PDT 24
Peak memory 218156 kb
Host smart-02fc7ebf-e253-460e-9fe2-62d1eb2011bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968258429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.968258429
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.209830743
Short name T545
Test name
Test status
Simulation time 12576361938 ps
CPU time 220.01 seconds
Started Jul 04 06:40:57 PM PDT 24
Finished Jul 04 06:44:38 PM PDT 24
Peak memory 226100 kb
Host smart-105f03e0-d67f-4dad-95bc-a16c64dc39ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209830743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.209830743
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.3303791923
Short name T79
Test name
Test status
Simulation time 76551424097 ps
CPU time 576.51 seconds
Started Jul 04 06:40:54 PM PDT 24
Finished Jul 04 06:50:31 PM PDT 24
Peak memory 266380 kb
Host smart-7f1759e6-3325-4aef-8a47-a22c04d80ab9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3303791923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.3303791923
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.950758929
Short name T802
Test name
Test status
Simulation time 13255085 ps
CPU time 1.02 seconds
Started Jul 04 06:40:53 PM PDT 24
Finished Jul 04 06:40:54 PM PDT 24
Peak memory 211876 kb
Host smart-7dd60b56-3f2c-482f-afbb-475fa3140ffb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950758929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.950758929
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.3634486141
Short name T281
Test name
Test status
Simulation time 205304256 ps
CPU time 1.35 seconds
Started Jul 04 06:41:03 PM PDT 24
Finished Jul 04 06:41:04 PM PDT 24
Peak memory 208996 kb
Host smart-d7d592fa-bd3a-4843-b4d9-54e6298ab4d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634486141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.3634486141
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.3418499479
Short name T218
Test name
Test status
Simulation time 12325364 ps
CPU time 0.99 seconds
Started Jul 04 06:41:05 PM PDT 24
Finished Jul 04 06:41:06 PM PDT 24
Peak memory 208984 kb
Host smart-1af1bae2-365d-4148-8b32-6abc9764986e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418499479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.3418499479
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.3984249159
Short name T316
Test name
Test status
Simulation time 1055379812 ps
CPU time 9.57 seconds
Started Jul 04 06:41:03 PM PDT 24
Finished Jul 04 06:41:13 PM PDT 24
Peak memory 226020 kb
Host smart-9220ba14-2532-4c91-a9f9-0d3f4a019415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984249159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3984249159
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.14923924
Short name T29
Test name
Test status
Simulation time 311936086 ps
CPU time 7.78 seconds
Started Jul 04 06:41:02 PM PDT 24
Finished Jul 04 06:41:10 PM PDT 24
Peak memory 217160 kb
Host smart-0963477e-8919-4206-b44c-5541d1b8c565
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14923924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.14923924
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.3059219136
Short name T796
Test name
Test status
Simulation time 6289503665 ps
CPU time 22.83 seconds
Started Jul 04 06:41:02 PM PDT 24
Finished Jul 04 06:41:25 PM PDT 24
Peak memory 218968 kb
Host smart-b84a7d25-6f6a-49da-889d-000c1b726d3b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059219136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.3059219136
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2815141617
Short name T484
Test name
Test status
Simulation time 725958189 ps
CPU time 6.06 seconds
Started Jul 04 06:41:03 PM PDT 24
Finished Jul 04 06:41:09 PM PDT 24
Peak memory 217760 kb
Host smart-2137de47-d82d-4ff2-b1d2-92247f30c1fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815141617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
815141617
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2755147960
Short name T337
Test name
Test status
Simulation time 197863701 ps
CPU time 2.76 seconds
Started Jul 04 06:41:03 PM PDT 24
Finished Jul 04 06:41:06 PM PDT 24
Peak memory 221760 kb
Host smart-d0bff39a-23d3-40c2-b2e3-92f56a4d3b4e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755147960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2755147960
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1033844555
Short name T144
Test name
Test status
Simulation time 13489358869 ps
CPU time 14.45 seconds
Started Jul 04 06:41:04 PM PDT 24
Finished Jul 04 06:41:19 PM PDT 24
Peak memory 217776 kb
Host smart-42375d61-3ebe-4fdb-a886-d244afbd29d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033844555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.1033844555
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.3332530880
Short name T331
Test name
Test status
Simulation time 99185296 ps
CPU time 2.07 seconds
Started Jul 04 06:41:05 PM PDT 24
Finished Jul 04 06:41:07 PM PDT 24
Peak memory 217660 kb
Host smart-339934fc-759a-461d-9690-ae5ff6e7de91
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332530880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
3332530880
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2938333512
Short name T145
Test name
Test status
Simulation time 5199490455 ps
CPU time 57.65 seconds
Started Jul 04 06:41:05 PM PDT 24
Finished Jul 04 06:42:03 PM PDT 24
Peak memory 276804 kb
Host smart-6eaf2b25-1970-4aa3-b248-bdcb80707011
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938333512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2938333512
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1866629197
Short name T300
Test name
Test status
Simulation time 2629954706 ps
CPU time 20.02 seconds
Started Jul 04 06:41:03 PM PDT 24
Finished Jul 04 06:41:23 PM PDT 24
Peak memory 226464 kb
Host smart-ac695af9-a6af-43ba-b292-2f42344cacd8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866629197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.1866629197
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.1529355583
Short name T318
Test name
Test status
Simulation time 78540697 ps
CPU time 3.7 seconds
Started Jul 04 06:41:02 PM PDT 24
Finished Jul 04 06:41:06 PM PDT 24
Peak memory 218200 kb
Host smart-37eb0a5a-411d-45bd-8f6c-8613e5fc54be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529355583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1529355583
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3093568996
Short name T168
Test name
Test status
Simulation time 1363705218 ps
CPU time 7.55 seconds
Started Jul 04 06:41:03 PM PDT 24
Finished Jul 04 06:41:10 PM PDT 24
Peak memory 217744 kb
Host smart-66d34826-f118-41f8-b903-f88983028384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093568996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3093568996
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.221621138
Short name T823
Test name
Test status
Simulation time 235377618 ps
CPU time 8.76 seconds
Started Jul 04 06:41:05 PM PDT 24
Finished Jul 04 06:41:14 PM PDT 24
Peak memory 226048 kb
Host smart-12ffdbd7-6f37-4eda-ab6b-abdfe4faa6c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221621138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.221621138
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2866622221
Short name T469
Test name
Test status
Simulation time 347716534 ps
CPU time 13.94 seconds
Started Jul 04 06:41:04 PM PDT 24
Finished Jul 04 06:41:18 PM PDT 24
Peak memory 226056 kb
Host smart-c77988ac-6a03-412d-80f3-54248935f43f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866622221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2866622221
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.2594361105
Short name T578
Test name
Test status
Simulation time 383363118 ps
CPU time 5.37 seconds
Started Jul 04 06:41:03 PM PDT 24
Finished Jul 04 06:41:08 PM PDT 24
Peak memory 218252 kb
Host smart-ae51fb81-5863-43f8-bc0f-4f38f6d47b89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594361105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.2
594361105
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.2366121534
Short name T49
Test name
Test status
Simulation time 4017704247 ps
CPU time 16.2 seconds
Started Jul 04 06:41:03 PM PDT 24
Finished Jul 04 06:41:20 PM PDT 24
Peak memory 218412 kb
Host smart-0297709f-9c6b-416a-8be4-635b2d69e25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366121534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2366121534
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.151167324
Short name T860
Test name
Test status
Simulation time 332408981 ps
CPU time 5.35 seconds
Started Jul 04 06:41:06 PM PDT 24
Finished Jul 04 06:41:11 PM PDT 24
Peak memory 217840 kb
Host smart-0c1f7f38-d79a-4ada-a721-c14cbffa83d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151167324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.151167324
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3574792865
Short name T407
Test name
Test status
Simulation time 275374054 ps
CPU time 32.9 seconds
Started Jul 04 06:41:04 PM PDT 24
Finished Jul 04 06:41:37 PM PDT 24
Peak memory 250948 kb
Host smart-d77a1e34-df3e-4cda-8db7-82bc009f11fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574792865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3574792865
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.2656968281
Short name T852
Test name
Test status
Simulation time 80347934 ps
CPU time 7.45 seconds
Started Jul 04 06:41:05 PM PDT 24
Finished Jul 04 06:41:12 PM PDT 24
Peak memory 246928 kb
Host smart-5c992e27-bd31-455f-9659-1d2384687da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656968281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2656968281
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.1701580601
Short name T704
Test name
Test status
Simulation time 3444877248 ps
CPU time 79.39 seconds
Started Jul 04 06:41:05 PM PDT 24
Finished Jul 04 06:42:24 PM PDT 24
Peak memory 277684 kb
Host smart-2cc37dbd-2ba6-4521-9e38-bd8a6db48a5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701580601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.1701580601
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.4091236594
Short name T112
Test name
Test status
Simulation time 18741721006 ps
CPU time 300.32 seconds
Started Jul 04 06:41:02 PM PDT 24
Finished Jul 04 06:46:03 PM PDT 24
Peak memory 267560 kb
Host smart-ef8744aa-1cf7-4690-9afc-a0ca791b4318
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4091236594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.4091236594
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1972353416
Short name T267
Test name
Test status
Simulation time 42361346 ps
CPU time 0.85 seconds
Started Jul 04 06:41:05 PM PDT 24
Finished Jul 04 06:41:06 PM PDT 24
Peak memory 211828 kb
Host smart-0d411944-874b-4ce4-ace7-20a2962cdf7f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972353416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.1972353416
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3813999448
Short name T400
Test name
Test status
Simulation time 51898022 ps
CPU time 1.08 seconds
Started Jul 04 06:41:11 PM PDT 24
Finished Jul 04 06:41:12 PM PDT 24
Peak memory 209056 kb
Host smart-dc0314e9-833b-4db5-a59b-718c36130ce3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813999448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3813999448
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2007466680
Short name T846
Test name
Test status
Simulation time 14019333 ps
CPU time 1.02 seconds
Started Jul 04 06:41:03 PM PDT 24
Finished Jul 04 06:41:04 PM PDT 24
Peak memory 209264 kb
Host smart-d9c7dc12-efe2-497f-82ae-8671817dbb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007466680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2007466680
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.3876064011
Short name T470
Test name
Test status
Simulation time 1576541401 ps
CPU time 11.81 seconds
Started Jul 04 06:41:06 PM PDT 24
Finished Jul 04 06:41:18 PM PDT 24
Peak memory 226012 kb
Host smart-612a19d3-8d9a-44bf-a1a7-0166f4b59597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876064011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.3876064011
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.1880749012
Short name T434
Test name
Test status
Simulation time 1034237459 ps
CPU time 7.55 seconds
Started Jul 04 06:41:05 PM PDT 24
Finished Jul 04 06:41:13 PM PDT 24
Peak memory 217092 kb
Host smart-e8a3cf5f-7e13-4939-b44c-f753fd864db2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880749012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.1880749012
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1108530473
Short name T178
Test name
Test status
Simulation time 2520639746 ps
CPU time 40.7 seconds
Started Jul 04 06:41:03 PM PDT 24
Finished Jul 04 06:41:44 PM PDT 24
Peak memory 218964 kb
Host smart-5508b926-3daa-4219-a7b7-b1a15a5c009d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108530473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1108530473
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2342929901
Short name T93
Test name
Test status
Simulation time 990276632 ps
CPU time 7.21 seconds
Started Jul 04 06:41:02 PM PDT 24
Finished Jul 04 06:41:09 PM PDT 24
Peak memory 217636 kb
Host smart-c5c644f4-0233-4c33-aae7-7bda0fc23227
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342929901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
342929901
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2202252358
Short name T21
Test name
Test status
Simulation time 1106794468 ps
CPU time 8.92 seconds
Started Jul 04 06:41:04 PM PDT 24
Finished Jul 04 06:41:13 PM PDT 24
Peak memory 218240 kb
Host smart-0638c4d3-3230-4ec9-86d2-9bc8833b0570
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202252358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2202252358
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3559647232
Short name T155
Test name
Test status
Simulation time 889910013 ps
CPU time 26.16 seconds
Started Jul 04 06:41:05 PM PDT 24
Finished Jul 04 06:41:31 PM PDT 24
Peak memory 217752 kb
Host smart-fdd3ed51-779a-40af-bffa-453352fcab44
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559647232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3559647232
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2820958739
Short name T587
Test name
Test status
Simulation time 311882585 ps
CPU time 2.54 seconds
Started Jul 04 06:41:01 PM PDT 24
Finished Jul 04 06:41:04 PM PDT 24
Peak memory 217732 kb
Host smart-58d25bda-f56b-4ff9-8bb0-2d889b5802a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820958739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2820958739
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3041726055
Short name T549
Test name
Test status
Simulation time 2455373845 ps
CPU time 37.8 seconds
Started Jul 04 06:41:03 PM PDT 24
Finished Jul 04 06:41:41 PM PDT 24
Peak memory 251052 kb
Host smart-b3333fab-9479-4cfa-98af-f1bd45e16f19
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041726055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3041726055
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2679151704
Short name T346
Test name
Test status
Simulation time 3054422777 ps
CPU time 17.56 seconds
Started Jul 04 06:41:06 PM PDT 24
Finished Jul 04 06:41:23 PM PDT 24
Peak memory 251040 kb
Host smart-f0c369ce-442d-438f-948f-8c0905533275
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679151704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.2679151704
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.666006014
Short name T255
Test name
Test status
Simulation time 80291329 ps
CPU time 1.96 seconds
Started Jul 04 06:41:03 PM PDT 24
Finished Jul 04 06:41:05 PM PDT 24
Peak memory 218236 kb
Host smart-21f7c6a2-8372-473d-83cf-08371e04197c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666006014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.666006014
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.709548204
Short name T194
Test name
Test status
Simulation time 245642283 ps
CPU time 12.35 seconds
Started Jul 04 06:41:05 PM PDT 24
Finished Jul 04 06:41:17 PM PDT 24
Peak memory 214600 kb
Host smart-62f49b95-c20f-4671-8007-d77008f2d1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709548204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.709548204
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.306460078
Short name T262
Test name
Test status
Simulation time 376321216 ps
CPU time 13.77 seconds
Started Jul 04 06:41:04 PM PDT 24
Finished Jul 04 06:41:18 PM PDT 24
Peak memory 218892 kb
Host smart-ebe20fb9-cf5d-4674-b300-9aea52f60352
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306460078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.306460078
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.501728110
Short name T632
Test name
Test status
Simulation time 5333055030 ps
CPU time 12.83 seconds
Started Jul 04 06:41:13 PM PDT 24
Finished Jul 04 06:41:26 PM PDT 24
Peak memory 226108 kb
Host smart-45bf4d98-95dc-4516-911b-4bd608798452
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501728110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dig
est.501728110
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2248774473
Short name T648
Test name
Test status
Simulation time 248530915 ps
CPU time 10.17 seconds
Started Jul 04 06:41:12 PM PDT 24
Finished Jul 04 06:41:23 PM PDT 24
Peak memory 218284 kb
Host smart-9921d01c-3949-4cc2-a1af-e311059c0a06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248774473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
248774473
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.3573261321
Short name T266
Test name
Test status
Simulation time 583555729 ps
CPU time 10.58 seconds
Started Jul 04 06:41:06 PM PDT 24
Finished Jul 04 06:41:17 PM PDT 24
Peak memory 225108 kb
Host smart-c5626977-ebfb-4ed4-9c11-b6b2c15aac68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573261321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.3573261321
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.2308827929
Short name T73
Test name
Test status
Simulation time 235030167 ps
CPU time 3.73 seconds
Started Jul 04 06:41:04 PM PDT 24
Finished Jul 04 06:41:08 PM PDT 24
Peak memory 217712 kb
Host smart-02357c23-9a58-474f-affe-72137aefe351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308827929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.2308827929
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.858044838
Short name T240
Test name
Test status
Simulation time 202219793 ps
CPU time 24.22 seconds
Started Jul 04 06:41:06 PM PDT 24
Finished Jul 04 06:41:30 PM PDT 24
Peak memory 244928 kb
Host smart-49da60a3-8d1f-48d8-a303-63b717d2ca0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858044838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.858044838
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.862296070
Short name T419
Test name
Test status
Simulation time 146140259 ps
CPU time 10.02 seconds
Started Jul 04 06:41:02 PM PDT 24
Finished Jul 04 06:41:12 PM PDT 24
Peak memory 250940 kb
Host smart-31f92b9a-7026-47db-a7ee-8efa1e304da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862296070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.862296070
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3236779339
Short name T853
Test name
Test status
Simulation time 15414062223 ps
CPU time 334.86 seconds
Started Jul 04 06:41:10 PM PDT 24
Finished Jul 04 06:46:45 PM PDT 24
Peak memory 283820 kb
Host smart-e64954e4-0f18-4fe0-90e8-4480dacf11d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236779339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3236779339
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2005593429
Short name T236
Test name
Test status
Simulation time 12195913 ps
CPU time 0.88 seconds
Started Jul 04 06:41:03 PM PDT 24
Finished Jul 04 06:41:04 PM PDT 24
Peak memory 211872 kb
Host smart-a850b45b-1fb3-40d5-9a96-cc8e8da83e31
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005593429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.2005593429
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%