Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105133359

1

T1

27995

T2

12923

T3

725

auto[1]

1399977

1

T1

12753

T2

1485

T4

396

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105140255

1

T1

28128

T2

12032

T3

725

auto[1]

1393081

1

T1

12620

T2

2376

T4

594

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7151318	1			T1	9016		T2	5463		T3	117
auto[IdleSt]	21470304	1			T1	8801		T2	1201		T3	59
auto[ClkMuxSt]	34986	1			T1	79		T3	1		T4	10
auto[CntIncrSt]	34733	1			T1	77		T3	1		T4	10
auto[CntProgSt]	1524514	1			T1	143		T3	2		T4	20
auto[TransCheckSt]	27086	1			T1	65		T3	1		T10	1
auto[TokenHashSt]	45680363	1			T1	2917		T3	44		T10	24
auto[FlashRmaSt]	34717	1			T1	159		T7	6		T19	24
auto[TokenCheck0St]	12194	1			T1	30		T7	6		T19	8
auto[TokenCheck1St]	8925	1			T1	30		T7	6		T19	8
auto[TransProgSt]	377750	1			T1	46		T7	12		T19	16
auto[PostTransSt]	12451172	1			T1	31		T3	500		T4	626
auto[ScrapSt]	145111	1			T1	3		T22	3		T14	345
auto[EscalateSt]	6612513	1			T1	19351		T2	4987		T4	1343
auto[InvalidSt]	10965578	1			T2	2751		T19	172		T14	94243

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2072	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10965578	1			T2	2751		T19	172		T14	94243
EscalateSt	6612513	1			T1	19351		T2	4987		T4	1343
ScrapSt	145111	1			T1	3		T22	3		T14	345
PostTransSt	12451172	1			T1	31		T3	500		T4	626
TransProgSt	377750	1			T1	46		T7	12		T19	16
TokenCheck1St	8925	1			T1	30		T7	6		T19	8
TokenCheck0St	12194	1			T1	30		T7	6		T19	8
FlashRmaSt	34717	1			T1	159		T7	6		T19	24
TokenHashSt	45680363	1			T1	2917		T3	44		T10	24
TransCheckSt	27086	1			T1	65		T3	1		T10	1
CntProgSt	1524514	1			T1	143		T3	2		T4	20
CntIncrSt	34733	1			T1	77		T3	1		T4	10
ClkMuxSt	34986	1			T1	79		T3	1		T4	10
IdleSt	21470304	1			T1	8801		T2	1201		T3	59
ResetSt	7151318	1			T1	9016		T2	5463		T3	117
arcs[ResetSt=>IdleSt]	53629	1			T1	88		T2	44		T3	1
arcs[IdleSt=>ScrapSt]	277	1			T1	1		T22	1		T14	4
arcs[IdleSt=>ClkMuxSt]	34788	1			T1	79		T3	1		T4	10
arcs[ClkMuxSt=>CntIncrSt]	34733	1			T1	77		T3	1		T4	10
arcs[CntIncrSt=>PostTransSt]	1745	1			T9	6		T13	13		T14	17
arcs[CntIncrSt=>CntProgSt]	32924	1			T1	74		T3	1		T4	10
arcs[CntProgSt=>PostTransSt]	4786	1			T4	10		T18	19		T9	5
arcs[CntProgSt=>TransCheckSt]	27086	1			T1	65		T3	1		T10	1
arcs[TransCheckSt=>PostTransSt]	3728	1			T9	4		T13	9		T21	45
arcs[TransCheckSt=>TokenHashSt]	23218	1			T1	55		T3	1		T10	1
arcs[TokenHashSt=>PostTransSt]	10282	1			T3	1		T10	1		T11	54
arcs[TokenHashSt=>FlashRmaSt]	12279	1			T1	32		T7	6		T19	8
arcs[FlashRmaSt=>TokenCheck0St]	12194	1			T1	30		T7	6		T19	8
arcs[TokenCheck0St=>PostTransSt]	3236	1			T9	7		T13	11		T21	27
arcs[TokenCheck0St=>TokenCheck1St]	8925	1			T1	30		T7	6		T19	8
arcs[TokenCheck1St=>PostTransSt]	624	1			T13	3		T21	6		T14	2
arcs[TransProgSt=>PostTransSt]	7435	1			T1	18		T7	6		T19	8
arcs[IdleSt=>EscalateSt]	219	1			T1	7		T22	10		T45	9
arcs[ClkMuxSt=>EscalateSt]	55	1			T1	2		T22	1		T45	1
arcs[CntIncrSt=>EscalateSt]	64	1			T1	3		T22	1		T45	2
arcs[CntProgSt=>EscalateSt]	1052	1			T1	9		T22	21		T45	5
arcs[TransCheckSt=>EscalateSt]	140	1			T1	10		T45	3		T51	1
arcs[TokenHashSt=>EscalateSt]	656	1			T1	23		T22	6		T45	18
arcs[FlashRmaSt=>EscalateSt]	85	1			T1	2		T22	3		T45	2
arcs[TokenCheck0St=>EscalateSt]	33	1			T22	1		T50	1		T46	1
arcs[TokenCheck1St=>EscalateSt]	159	1			T1	5		T22	3		T45	3
arcs[TransProgSt=>EscalateSt]	707	1			T1	7		T22	8		T45	12
arcs[PostTransSt=>EscalateSt]	5030	1			T1	18		T4	10		T18	19
arcs[InvalidSt=>EscalateSt]	14137	1			T2	39		T19	1		T14	101

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7151130	1			T1	9013		T2	5463		T3	117
auto[0]	auto[IdleSt]	21470166	1			T1	8795		T2	1201		T3	59
auto[0]	auto[ClkMuxSt]	34947	1			T1	78		T3	1		T4	10
auto[0]	auto[CntIncrSt]	34689	1			T1	75		T3	1		T4	10
auto[0]	auto[CntProgSt]	1523821	1			T1	136		T3	2		T4	20
auto[0]	auto[TransCheckSt]	26988	1			T1	58		T3	1		T10	1
auto[0]	auto[TokenHashSt]	45679939	1			T1	2900		T3	44		T10	24
auto[0]	auto[FlashRmaSt]	34659	1			T1	157		T7	6		T19	24
auto[0]	auto[TokenCheck0St]	12170	1			T1	30		T7	6		T19	8
auto[0]	auto[TokenCheck1St]	8820	1			T1	28		T7	6		T19	8
auto[0]	auto[TransProgSt]	377271	1			T1	41		T7	12		T19	16
auto[0]	auto[PostTransSt]	12448620	1			T1	21		T3	500		T4	622
auto[0]	auto[ScrapSt]	145070	1			T1	3		T22	2		T14	345
auto[0]	auto[EscalateSt]	5224543	1			T1	6660		T2	3517		T4	951
auto[0]	auto[InvalidSt]	10958454	1			T2	2736		T19	171		T14	94193
auto[1]	auto[ResetSt]	188	1			T1	3		T22	2		T45	7
auto[1]	auto[IdleSt]	138	1			T1	6		T22	7		T45	6
auto[1]	auto[ClkMuxSt]	39	1			T1	1		T22	1		T46	1
auto[1]	auto[CntIncrSt]	44	1			T1	2		T22	1		T45	2
auto[1]	auto[CntProgSt]	693	1			T1	7		T22	15		T45	3
auto[1]	auto[TransCheckSt]	98	1			T1	7		T45	2		T233	1
auto[1]	auto[TokenHashSt]	424	1			T1	17		T22	4		T45	15
auto[1]	auto[FlashRmaSt]	58	1			T1	2		T22	2		T45	1
auto[1]	auto[TokenCheck0St]	24	1			T22	1		T46	1		T83	1
auto[1]	auto[TokenCheck1St]	105	1			T1	2		T22	1		T45	2
auto[1]	auto[TransProgSt]	479	1			T1	5		T22	6		T45	9
auto[1]	auto[PostTransSt]	2552	1			T1	10		T4	4		T18	12
auto[1]	auto[ScrapSt]	41	1			T22	1		T46	1		T51	1
auto[1]	auto[EscalateSt]	1387970	1			T1	12691		T2	1470		T4	392
auto[1]	auto[InvalidSt]	7124	1			T2	15		T19	1		T14	50

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7151138	1			T1	9010		T2	5463		T3	117
auto[0]	auto[IdleSt]	21470160	1			T1	8796		T2	1201		T3	59
auto[0]	auto[ClkMuxSt]	34943	1			T1	78		T3	1		T4	10
auto[0]	auto[CntIncrSt]	34688	1			T1	74		T3	1		T4	10
auto[0]	auto[CntProgSt]	1523822	1			T1	137		T3	2		T4	20
auto[0]	auto[TransCheckSt]	27000	1			T1	60		T3	1		T10	1
auto[0]	auto[TokenHashSt]	45679925	1			T1	2902		T3	44		T10	24
auto[0]	auto[FlashRmaSt]	34658	1			T1	158		T7	6		T19	24
auto[0]	auto[TokenCheck0St]	12170	1			T1	30		T7	6		T19	8
auto[0]	auto[TokenCheck1St]	8815	1			T1	27		T7	6		T19	8
auto[0]	auto[TransProgSt]	377261	1			T1	44		T7	12		T19	16
auto[0]	auto[PostTransSt]	12448628	1			T1	19		T3	500		T4	620
auto[0]	auto[ScrapSt]	145079	1			T1	2		T22	3		T14	345
auto[0]	auto[EscalateSt]	5231331	1			T1	6791		T2	2635		T4	755
auto[0]	auto[InvalidSt]	10958565	1			T2	2727		T19	172		T14	94192
auto[1]	auto[ResetSt]	180	1			T1	6		T22	1		T45	7
auto[1]	auto[IdleSt]	144	1			T1	5		T22	7		T45	5
auto[1]	auto[ClkMuxSt]	43	1			T1	1		T22	1		T45	1
auto[1]	auto[CntIncrSt]	45	1			T1	3		T45	2		T50	1
auto[1]	auto[CntProgSt]	692	1			T1	6		T22	12		T45	4
auto[1]	auto[TransCheckSt]	86	1			T1	5		T45	1		T51	1
auto[1]	auto[TokenHashSt]	438	1			T1	15		T22	5		T45	10
auto[1]	auto[FlashRmaSt]	59	1			T1	1		T22	2		T45	1
auto[1]	auto[TokenCheck0St]	24	1			T50	1		T46	1		T83	1
auto[1]	auto[TokenCheck1St]	110	1			T1	3		T22	2		T45	2
auto[1]	auto[TransProgSt]	489	1			T1	2		T22	4		T45	6
auto[1]	auto[PostTransSt]	2544	1			T1	12		T4	6		T18	7
auto[1]	auto[ScrapSt]	32	1			T1	1		T83	1		T51	1
auto[1]	auto[EscalateSt]	1381182	1			T1	12560		T2	2352		T4	588
auto[1]	auto[InvalidSt]	7013	1			T2	24		T14	51		T20	2