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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.84 97.92 95.84 93.38 97.62 98.52 98.51 96.11


Total test records in report: 991
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T817 /workspace/coverage/default/11.lc_ctrl_prog_failure.3485967509 Jul 05 05:28:14 PM PDT 24 Jul 05 05:28:17 PM PDT 24 107734237 ps
T818 /workspace/coverage/default/24.lc_ctrl_security_escalation.609123137 Jul 05 05:29:07 PM PDT 24 Jul 05 05:29:15 PM PDT 24 3304471784 ps
T819 /workspace/coverage/default/11.lc_ctrl_security_escalation.1782665840 Jul 05 05:28:16 PM PDT 24 Jul 05 05:28:27 PM PDT 24 1176392147 ps
T820 /workspace/coverage/default/29.lc_ctrl_jtag_access.2762473048 Jul 05 05:29:20 PM PDT 24 Jul 05 05:29:24 PM PDT 24 43039785 ps
T821 /workspace/coverage/default/23.lc_ctrl_prog_failure.162623747 Jul 05 05:29:02 PM PDT 24 Jul 05 05:29:06 PM PDT 24 50116544 ps
T822 /workspace/coverage/default/20.lc_ctrl_jtag_access.2111260415 Jul 05 05:28:58 PM PDT 24 Jul 05 05:29:12 PM PDT 24 1338547914 ps
T823 /workspace/coverage/default/40.lc_ctrl_errors.641777060 Jul 05 05:29:52 PM PDT 24 Jul 05 05:30:01 PM PDT 24 2555537682 ps
T824 /workspace/coverage/default/1.lc_ctrl_stress_all.4110520842 Jul 05 05:27:40 PM PDT 24 Jul 05 05:31:21 PM PDT 24 6387345718 ps
T825 /workspace/coverage/default/33.lc_ctrl_prog_failure.2290682343 Jul 05 05:29:37 PM PDT 24 Jul 05 05:29:41 PM PDT 24 71345907 ps
T826 /workspace/coverage/default/32.lc_ctrl_sec_mubi.534511101 Jul 05 05:29:29 PM PDT 24 Jul 05 05:29:42 PM PDT 24 671119112 ps
T827 /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.195518754 Jul 05 05:27:45 PM PDT 24 Jul 05 05:29:27 PM PDT 24 3011178262 ps
T828 /workspace/coverage/default/47.lc_ctrl_security_escalation.567534559 Jul 05 05:30:13 PM PDT 24 Jul 05 05:30:26 PM PDT 24 433862503 ps
T829 /workspace/coverage/default/13.lc_ctrl_prog_failure.302839860 Jul 05 05:28:32 PM PDT 24 Jul 05 05:28:36 PM PDT 24 126896585 ps
T230 /workspace/coverage/default/4.lc_ctrl_claim_transition_if.4030586464 Jul 05 05:27:45 PM PDT 24 Jul 05 05:27:46 PM PDT 24 33290996 ps
T830 /workspace/coverage/default/16.lc_ctrl_smoke.1502267871 Jul 05 05:28:38 PM PDT 24 Jul 05 05:28:41 PM PDT 24 24418790 ps
T831 /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1749552834 Jul 05 05:28:07 PM PDT 24 Jul 05 05:28:20 PM PDT 24 846207611 ps
T832 /workspace/coverage/default/11.lc_ctrl_smoke.4040252139 Jul 05 05:28:17 PM PDT 24 Jul 05 05:28:20 PM PDT 24 14487574 ps
T833 /workspace/coverage/default/19.lc_ctrl_state_failure.4051748653 Jul 05 05:28:56 PM PDT 24 Jul 05 05:29:26 PM PDT 24 989759434 ps
T834 /workspace/coverage/default/7.lc_ctrl_jtag_priority.1093729914 Jul 05 05:28:01 PM PDT 24 Jul 05 05:28:05 PM PDT 24 98116024 ps
T835 /workspace/coverage/default/32.lc_ctrl_security_escalation.9992475 Jul 05 05:29:29 PM PDT 24 Jul 05 05:29:43 PM PDT 24 3466046850 ps
T836 /workspace/coverage/default/8.lc_ctrl_prog_failure.3233858531 Jul 05 05:28:06 PM PDT 24 Jul 05 05:28:09 PM PDT 24 107546547 ps
T837 /workspace/coverage/default/9.lc_ctrl_errors.540765858 Jul 05 05:28:08 PM PDT 24 Jul 05 05:28:22 PM PDT 24 3430142603 ps
T838 /workspace/coverage/default/34.lc_ctrl_stress_all.957457326 Jul 05 05:29:40 PM PDT 24 Jul 05 05:30:45 PM PDT 24 41367024605 ps
T839 /workspace/coverage/default/30.lc_ctrl_prog_failure.1658473655 Jul 05 05:29:22 PM PDT 24 Jul 05 05:29:27 PM PDT 24 551122202 ps
T840 /workspace/coverage/default/25.lc_ctrl_alert_test.4199355128 Jul 05 05:29:14 PM PDT 24 Jul 05 05:29:16 PM PDT 24 51599481 ps
T841 /workspace/coverage/default/30.lc_ctrl_smoke.3984473273 Jul 05 05:29:28 PM PDT 24 Jul 05 05:29:34 PM PDT 24 1071733180 ps
T842 /workspace/coverage/default/15.lc_ctrl_smoke.176012167 Jul 05 05:28:41 PM PDT 24 Jul 05 05:28:45 PM PDT 24 49550435 ps
T843 /workspace/coverage/default/44.lc_ctrl_smoke.4277042531 Jul 05 05:30:01 PM PDT 24 Jul 05 05:30:05 PM PDT 24 24224716 ps
T844 /workspace/coverage/default/34.lc_ctrl_alert_test.3338479805 Jul 05 05:29:39 PM PDT 24 Jul 05 05:29:40 PM PDT 24 41606579 ps
T845 /workspace/coverage/default/30.lc_ctrl_state_failure.1772141665 Jul 05 05:29:27 PM PDT 24 Jul 05 05:29:57 PM PDT 24 307380019 ps
T846 /workspace/coverage/default/49.lc_ctrl_state_post_trans.3845777843 Jul 05 05:30:12 PM PDT 24 Jul 05 05:30:23 PM PDT 24 712136459 ps
T847 /workspace/coverage/default/24.lc_ctrl_stress_all.3166742849 Jul 05 05:29:01 PM PDT 24 Jul 05 05:30:41 PM PDT 24 3222948016 ps
T848 /workspace/coverage/default/39.lc_ctrl_sec_token_digest.1763074465 Jul 05 05:29:53 PM PDT 24 Jul 05 05:30:01 PM PDT 24 4003971963 ps
T849 /workspace/coverage/default/28.lc_ctrl_state_failure.2088426668 Jul 05 05:29:27 PM PDT 24 Jul 05 05:29:52 PM PDT 24 293220194 ps
T850 /workspace/coverage/default/6.lc_ctrl_stress_all.1381150321 Jul 05 05:28:02 PM PDT 24 Jul 05 05:28:59 PM PDT 24 19227406100 ps
T851 /workspace/coverage/default/31.lc_ctrl_prog_failure.2020831874 Jul 05 05:29:27 PM PDT 24 Jul 05 05:29:33 PM PDT 24 68803164 ps
T852 /workspace/coverage/default/23.lc_ctrl_jtag_access.2423537452 Jul 05 05:29:01 PM PDT 24 Jul 05 05:29:11 PM PDT 24 690195546 ps
T853 /workspace/coverage/default/1.lc_ctrl_smoke.2546156711 Jul 05 05:27:34 PM PDT 24 Jul 05 05:27:40 PM PDT 24 61579043 ps
T854 /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1796539314 Jul 05 05:28:42 PM PDT 24 Jul 05 05:28:52 PM PDT 24 1862230270 ps
T855 /workspace/coverage/default/32.lc_ctrl_smoke.4145696670 Jul 05 05:29:27 PM PDT 24 Jul 05 05:29:32 PM PDT 24 144963617 ps
T856 /workspace/coverage/default/20.lc_ctrl_sec_mubi.4041758581 Jul 05 05:28:56 PM PDT 24 Jul 05 05:29:09 PM PDT 24 1090659486 ps
T857 /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2960519888 Jul 05 05:29:26 PM PDT 24 Jul 05 05:29:44 PM PDT 24 379624789 ps
T858 /workspace/coverage/default/4.lc_ctrl_jtag_priority.1912458581 Jul 05 05:27:49 PM PDT 24 Jul 05 05:27:55 PM PDT 24 1591360530 ps
T859 /workspace/coverage/default/3.lc_ctrl_sec_token_digest.4081736515 Jul 05 05:27:47 PM PDT 24 Jul 05 05:28:00 PM PDT 24 483544824 ps
T860 /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.1232045721 Jul 05 05:27:42 PM PDT 24 Jul 05 05:30:43 PM PDT 24 18855820234 ps
T861 /workspace/coverage/default/17.lc_ctrl_sec_token_mux.1584710403 Jul 05 05:28:46 PM PDT 24 Jul 05 05:28:56 PM PDT 24 328936185 ps
T862 /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.854386602 Jul 05 05:28:39 PM PDT 24 Jul 05 05:28:44 PM PDT 24 532111724 ps
T863 /workspace/coverage/default/37.lc_ctrl_stress_all.1289969347 Jul 05 05:29:47 PM PDT 24 Jul 05 05:37:51 PM PDT 24 49137357860 ps
T864 /workspace/coverage/default/44.lc_ctrl_sec_mubi.3288580787 Jul 05 05:30:01 PM PDT 24 Jul 05 05:30:15 PM PDT 24 305476498 ps
T865 /workspace/coverage/default/1.lc_ctrl_sec_mubi.3648422351 Jul 05 05:27:39 PM PDT 24 Jul 05 05:27:56 PM PDT 24 243675896 ps
T866 /workspace/coverage/default/41.lc_ctrl_state_post_trans.2135242431 Jul 05 05:29:54 PM PDT 24 Jul 05 05:30:02 PM PDT 24 54420529 ps
T867 /workspace/coverage/default/40.lc_ctrl_stress_all.3615620411 Jul 05 05:29:59 PM PDT 24 Jul 05 05:32:09 PM PDT 24 57779383275 ps
T868 /workspace/coverage/default/15.lc_ctrl_security_escalation.1917291570 Jul 05 05:28:40 PM PDT 24 Jul 05 05:28:49 PM PDT 24 235069419 ps
T869 /workspace/coverage/default/21.lc_ctrl_stress_all.61054944 Jul 05 05:28:58 PM PDT 24 Jul 05 05:34:39 PM PDT 24 45495798219 ps
T870 /workspace/coverage/default/45.lc_ctrl_alert_test.4121401264 Jul 05 05:30:02 PM PDT 24 Jul 05 05:30:05 PM PDT 24 270637615 ps
T871 /workspace/coverage/default/6.lc_ctrl_errors.1562394987 Jul 05 05:27:55 PM PDT 24 Jul 05 05:28:15 PM PDT 24 1509093931 ps
T106 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.922731006 Jul 05 05:59:26 PM PDT 24 Jul 05 05:59:29 PM PDT 24 671543820 ps
T121 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.294256341 Jul 05 05:59:25 PM PDT 24 Jul 05 05:59:28 PM PDT 24 55665910 ps
T122 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2918969684 Jul 05 05:59:25 PM PDT 24 Jul 05 05:59:27 PM PDT 24 265623581 ps
T221 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.436763786 Jul 05 05:59:32 PM PDT 24 Jul 05 05:59:35 PM PDT 24 41567701 ps
T116 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2727030569 Jul 05 06:00:07 PM PDT 24 Jul 05 06:00:09 PM PDT 24 47550031 ps
T117 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.291542424 Jul 05 05:59:46 PM PDT 24 Jul 05 05:59:48 PM PDT 24 86509050 ps
T118 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1843960931 Jul 05 05:59:38 PM PDT 24 Jul 05 05:59:39 PM PDT 24 13211561 ps
T110 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2459158980 Jul 05 05:59:46 PM PDT 24 Jul 05 05:59:49 PM PDT 24 61925692 ps
T872 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3109319138 Jul 05 05:59:25 PM PDT 24 Jul 05 05:59:28 PM PDT 24 443026174 ps
T148 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.7534618 Jul 05 05:59:30 PM PDT 24 Jul 05 05:59:33 PM PDT 24 93370229 ps
T107 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3049918572 Jul 05 05:59:47 PM PDT 24 Jul 05 05:59:50 PM PDT 24 152635855 ps
T873 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.38169111 Jul 05 05:59:59 PM PDT 24 Jul 05 06:00:00 PM PDT 24 39472006 ps
T150 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.303909060 Jul 05 05:59:26 PM PDT 24 Jul 05 05:59:28 PM PDT 24 29294378 ps
T108 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.4116260287 Jul 05 05:59:41 PM PDT 24 Jul 05 05:59:43 PM PDT 24 48261671 ps
T222 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1889079972 Jul 05 05:59:44 PM PDT 24 Jul 05 05:59:46 PM PDT 24 77652415 ps
T149 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1860361932 Jul 05 05:59:35 PM PDT 24 Jul 05 05:59:37 PM PDT 24 110253028 ps
T151 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.4011702765 Jul 05 05:59:35 PM PDT 24 Jul 05 05:59:41 PM PDT 24 494624406 ps
T223 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1909143331 Jul 05 05:59:45 PM PDT 24 Jul 05 05:59:46 PM PDT 24 107502042 ps
T874 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1949963838 Jul 05 05:59:37 PM PDT 24 Jul 05 05:59:39 PM PDT 24 97624117 ps
T224 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.639636516 Jul 05 05:59:34 PM PDT 24 Jul 05 05:59:36 PM PDT 24 60043649 ps
T111 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1853681054 Jul 05 05:59:40 PM PDT 24 Jul 05 05:59:49 PM PDT 24 1239908826 ps
T144 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3206265800 Jul 05 05:59:56 PM PDT 24 Jul 05 06:00:02 PM PDT 24 1991449527 ps
T875 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3467270527 Jul 05 05:59:24 PM PDT 24 Jul 05 05:59:26 PM PDT 24 91699231 ps
T876 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3809682119 Jul 05 05:59:43 PM PDT 24 Jul 05 05:59:50 PM PDT 24 769217680 ps
T136 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3507670984 Jul 05 05:59:47 PM PDT 24 Jul 05 05:59:49 PM PDT 24 57904206 ps
T123 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.4159385768 Jul 05 05:59:44 PM PDT 24 Jul 05 05:59:46 PM PDT 24 29855220 ps
T225 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3754816380 Jul 05 05:59:47 PM PDT 24 Jul 05 05:59:50 PM PDT 24 565256886 ps
T208 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3449567014 Jul 05 05:59:30 PM PDT 24 Jul 05 05:59:32 PM PDT 24 87747436 ps
T877 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.109040211 Jul 05 05:59:41 PM PDT 24 Jul 05 05:59:47 PM PDT 24 2061024138 ps
T209 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2736816317 Jul 05 05:59:21 PM PDT 24 Jul 05 05:59:22 PM PDT 24 31711529 ps
T878 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2513671338 Jul 05 05:59:29 PM PDT 24 Jul 05 05:59:31 PM PDT 24 248802662 ps
T226 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2338179868 Jul 05 05:59:44 PM PDT 24 Jul 05 05:59:46 PM PDT 24 128299056 ps
T112 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2144743854 Jul 05 05:59:40 PM PDT 24 Jul 05 05:59:44 PM PDT 24 195663486 ps
T115 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.508679797 Jul 05 05:59:36 PM PDT 24 Jul 05 05:59:39 PM PDT 24 80977632 ps
T145 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2674727708 Jul 05 05:59:24 PM PDT 24 Jul 05 05:59:26 PM PDT 24 73758478 ps
T113 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.870597638 Jul 05 06:00:02 PM PDT 24 Jul 05 06:00:04 PM PDT 24 47537639 ps
T227 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1064551378 Jul 05 05:59:38 PM PDT 24 Jul 05 05:59:40 PM PDT 24 37154203 ps
T879 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1457102998 Jul 05 05:59:30 PM PDT 24 Jul 05 05:59:34 PM PDT 24 532552916 ps
T114 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1302324063 Jul 05 05:59:34 PM PDT 24 Jul 05 05:59:37 PM PDT 24 77176881 ps
T146 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3056655381 Jul 05 05:59:31 PM PDT 24 Jul 05 05:59:34 PM PDT 24 93792719 ps
T228 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2940234913 Jul 05 05:59:39 PM PDT 24 Jul 05 05:59:41 PM PDT 24 24904961 ps
T880 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3819289841 Jul 05 05:59:25 PM PDT 24 Jul 05 05:59:30 PM PDT 24 1118076937 ps
T881 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.936379229 Jul 05 05:59:41 PM PDT 24 Jul 05 05:59:42 PM PDT 24 85151675 ps
T124 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1175361376 Jul 05 05:59:23 PM PDT 24 Jul 05 05:59:26 PM PDT 24 1100388985 ps
T882 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1883302942 Jul 05 05:59:29 PM PDT 24 Jul 05 05:59:30 PM PDT 24 21384848 ps
T883 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1221212583 Jul 05 05:59:39 PM PDT 24 Jul 05 05:59:46 PM PDT 24 25971322 ps
T119 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.596430707 Jul 05 05:59:46 PM PDT 24 Jul 05 05:59:50 PM PDT 24 125454796 ps
T884 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1977691723 Jul 05 05:59:41 PM PDT 24 Jul 05 06:00:03 PM PDT 24 899026113 ps
T128 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.942903315 Jul 05 05:59:56 PM PDT 24 Jul 05 05:59:58 PM PDT 24 258754317 ps
T885 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1991956779 Jul 05 05:59:44 PM PDT 24 Jul 05 05:59:46 PM PDT 24 165720215 ps
T886 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3458728995 Jul 05 05:59:30 PM PDT 24 Jul 05 05:59:33 PM PDT 24 32492889 ps
T887 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2937060604 Jul 05 05:59:25 PM PDT 24 Jul 05 05:59:27 PM PDT 24 34516370 ps
T888 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.577235468 Jul 05 05:59:45 PM PDT 24 Jul 05 05:59:47 PM PDT 24 33243936 ps
T135 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2302995583 Jul 05 05:59:30 PM PDT 24 Jul 05 05:59:34 PM PDT 24 64136635 ps
T129 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3635699816 Jul 05 05:59:31 PM PDT 24 Jul 05 05:59:36 PM PDT 24 159511486 ps
T143 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2235043745 Jul 05 05:59:37 PM PDT 24 Jul 05 05:59:40 PM PDT 24 223204613 ps
T889 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.4035381788 Jul 05 05:59:30 PM PDT 24 Jul 05 05:59:33 PM PDT 24 83197123 ps
T890 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2607173174 Jul 05 05:59:44 PM PDT 24 Jul 05 05:59:46 PM PDT 24 14213888 ps
T210 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2276187419 Jul 05 05:59:27 PM PDT 24 Jul 05 05:59:29 PM PDT 24 43218769 ps
T891 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3826280839 Jul 05 05:59:26 PM PDT 24 Jul 05 05:59:28 PM PDT 24 30169594 ps
T141 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2003432283 Jul 05 05:59:32 PM PDT 24 Jul 05 05:59:36 PM PDT 24 296084354 ps
T892 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.785247927 Jul 05 05:59:29 PM PDT 24 Jul 05 05:59:31 PM PDT 24 124935138 ps
T140 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3258633651 Jul 05 05:59:42 PM PDT 24 Jul 05 05:59:45 PM PDT 24 120798098 ps
T893 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.852126305 Jul 05 05:59:23 PM PDT 24 Jul 05 05:59:24 PM PDT 24 20402571 ps
T142 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.4248746781 Jul 05 05:59:40 PM PDT 24 Jul 05 05:59:42 PM PDT 24 267378419 ps
T894 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.866798857 Jul 05 05:59:48 PM PDT 24 Jul 05 05:59:50 PM PDT 24 85814930 ps
T895 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2565908670 Jul 05 05:59:27 PM PDT 24 Jul 05 05:59:30 PM PDT 24 85444749 ps
T896 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2623367756 Jul 05 05:59:22 PM PDT 24 Jul 05 05:59:24 PM PDT 24 571130263 ps
T897 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.4068171348 Jul 05 05:59:25 PM PDT 24 Jul 05 05:59:28 PM PDT 24 76420922 ps
T211 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2640070726 Jul 05 05:59:26 PM PDT 24 Jul 05 05:59:28 PM PDT 24 59257512 ps
T130 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2487363280 Jul 05 05:59:42 PM PDT 24 Jul 05 05:59:47 PM PDT 24 128505552 ps
T133 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2711240391 Jul 05 05:59:54 PM PDT 24 Jul 05 05:59:58 PM PDT 24 170723193 ps
T120 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1009149828 Jul 05 05:59:32 PM PDT 24 Jul 05 05:59:35 PM PDT 24 848099696 ps
T212 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.504267261 Jul 05 05:59:31 PM PDT 24 Jul 05 05:59:33 PM PDT 24 157515018 ps
T898 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.375208012 Jul 05 05:59:28 PM PDT 24 Jul 05 05:59:30 PM PDT 24 75234880 ps
T899 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2099170626 Jul 05 05:59:39 PM PDT 24 Jul 05 05:59:40 PM PDT 24 29270226 ps
T900 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.651339194 Jul 05 05:59:47 PM PDT 24 Jul 05 05:59:50 PM PDT 24 26704144 ps
T901 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.4088833935 Jul 05 05:59:47 PM PDT 24 Jul 05 05:59:49 PM PDT 24 53891139 ps
T902 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4197021962 Jul 05 05:59:26 PM PDT 24 Jul 05 05:59:28 PM PDT 24 176789671 ps
T903 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.969669398 Jul 05 05:59:49 PM PDT 24 Jul 05 05:59:52 PM PDT 24 41508828 ps
T904 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3586178096 Jul 05 05:59:38 PM PDT 24 Jul 05 05:59:43 PM PDT 24 105198481 ps
T905 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.546387534 Jul 05 05:59:45 PM PDT 24 Jul 05 05:59:50 PM PDT 24 1834135046 ps
T213 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.747959814 Jul 05 05:59:35 PM PDT 24 Jul 05 05:59:36 PM PDT 24 23659553 ps
T906 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2903604701 Jul 05 05:59:23 PM PDT 24 Jul 05 05:59:27 PM PDT 24 122686033 ps
T907 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.643813719 Jul 05 05:59:24 PM PDT 24 Jul 05 05:59:26 PM PDT 24 40387831 ps
T908 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.481359561 Jul 05 05:59:36 PM PDT 24 Jul 05 05:59:37 PM PDT 24 65829187 ps
T134 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3198015723 Jul 05 05:59:48 PM PDT 24 Jul 05 05:59:51 PM PDT 24 601739704 ps
T909 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3459031343 Jul 05 05:59:28 PM PDT 24 Jul 05 05:59:30 PM PDT 24 14955605 ps
T910 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1193763486 Jul 05 05:59:41 PM PDT 24 Jul 05 05:59:43 PM PDT 24 63380073 ps
T911 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3423219852 Jul 05 05:59:24 PM PDT 24 Jul 05 05:59:27 PM PDT 24 322390323 ps
T912 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1083006117 Jul 05 05:59:29 PM PDT 24 Jul 05 05:59:47 PM PDT 24 2069270226 ps
T913 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3538761424 Jul 05 05:59:25 PM PDT 24 Jul 05 05:59:27 PM PDT 24 46253253 ps
T914 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3027690273 Jul 05 05:59:49 PM PDT 24 Jul 05 05:59:52 PM PDT 24 87772199 ps
T915 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1250869857 Jul 05 05:59:33 PM PDT 24 Jul 05 05:59:35 PM PDT 24 14820349 ps
T916 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3550219771 Jul 05 05:59:49 PM PDT 24 Jul 05 05:59:53 PM PDT 24 53457653 ps
T917 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4147983963 Jul 05 05:59:28 PM PDT 24 Jul 05 05:59:30 PM PDT 24 379503255 ps
T918 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2946125219 Jul 05 05:59:29 PM PDT 24 Jul 05 05:59:31 PM PDT 24 97974431 ps
T919 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2069361366 Jul 05 05:59:32 PM PDT 24 Jul 05 05:59:34 PM PDT 24 13798921 ps
T920 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.967288971 Jul 05 06:00:02 PM PDT 24 Jul 05 06:00:06 PM PDT 24 158977000 ps
T125 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.79667991 Jul 05 05:59:36 PM PDT 24 Jul 05 05:59:39 PM PDT 24 209964173 ps
T214 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.315907594 Jul 05 05:59:43 PM PDT 24 Jul 05 05:59:45 PM PDT 24 41206282 ps
T921 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.352693298 Jul 05 05:59:44 PM PDT 24 Jul 05 05:59:46 PM PDT 24 21001285 ps
T922 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.806943199 Jul 05 05:59:30 PM PDT 24 Jul 05 05:59:38 PM PDT 24 4597490125 ps
T923 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1030508984 Jul 05 05:59:28 PM PDT 24 Jul 05 05:59:30 PM PDT 24 34754816 ps
T924 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1797639863 Jul 05 05:59:40 PM PDT 24 Jul 05 05:59:42 PM PDT 24 69301029 ps
T925 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1779323245 Jul 05 05:59:30 PM PDT 24 Jul 05 05:59:32 PM PDT 24 25100548 ps
T215 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3089914987 Jul 05 05:59:47 PM PDT 24 Jul 05 05:59:49 PM PDT 24 26452779 ps
T926 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1996164412 Jul 05 05:59:28 PM PDT 24 Jul 05 05:59:31 PM PDT 24 99499217 ps
T927 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1532794275 Jul 05 05:59:39 PM PDT 24 Jul 05 05:59:42 PM PDT 24 29558764 ps
T928 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3869930565 Jul 05 05:59:45 PM PDT 24 Jul 05 05:59:47 PM PDT 24 68297260 ps
T929 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3597535630 Jul 05 05:59:29 PM PDT 24 Jul 05 05:59:46 PM PDT 24 732311800 ps
T930 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2902048924 Jul 05 05:59:15 PM PDT 24 Jul 05 05:59:25 PM PDT 24 779615876 ps
T931 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2508736942 Jul 05 05:59:50 PM PDT 24 Jul 05 05:59:55 PM PDT 24 144269098 ps
T932 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2356254953 Jul 05 05:59:46 PM PDT 24 Jul 05 05:59:48 PM PDT 24 21903313 ps
T933 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3582250072 Jul 05 05:59:39 PM PDT 24 Jul 05 05:59:46 PM PDT 24 1035528689 ps
T934 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1718864021 Jul 05 05:59:40 PM PDT 24 Jul 05 05:59:42 PM PDT 24 70899213 ps
T935 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2762894298 Jul 05 05:59:24 PM PDT 24 Jul 05 05:59:26 PM PDT 24 80494081 ps
T936 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3138977409 Jul 05 05:59:31 PM PDT 24 Jul 05 05:59:44 PM PDT 24 1981674461 ps
T937 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2397459946 Jul 05 05:59:31 PM PDT 24 Jul 05 05:59:46 PM PDT 24 1506638156 ps
T938 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1267562665 Jul 05 05:59:32 PM PDT 24 Jul 05 05:59:34 PM PDT 24 15123236 ps
T939 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.166904119 Jul 05 05:59:28 PM PDT 24 Jul 05 05:59:32 PM PDT 24 337458889 ps
T131 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1825627802 Jul 05 05:59:43 PM PDT 24 Jul 05 05:59:46 PM PDT 24 45573539 ps
T940 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1987220035 Jul 05 05:59:57 PM PDT 24 Jul 05 05:59:58 PM PDT 24 53821380 ps
T941 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3622039429 Jul 05 05:59:30 PM PDT 24 Jul 05 05:59:32 PM PDT 24 26150736 ps
T942 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.797365157 Jul 05 05:59:22 PM PDT 24 Jul 05 05:59:31 PM PDT 24 4493548949 ps
T216 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.751506115 Jul 05 05:59:28 PM PDT 24 Jul 05 05:59:30 PM PDT 24 30151777 ps
T943 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1642824983 Jul 05 05:59:35 PM PDT 24 Jul 05 05:59:37 PM PDT 24 46678813 ps
T944 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.638785126 Jul 05 05:59:48 PM PDT 24 Jul 05 05:59:50 PM PDT 24 231455666 ps
T945 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2758117734 Jul 05 05:59:31 PM PDT 24 Jul 05 05:59:34 PM PDT 24 119191997 ps
T946 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1903891340 Jul 05 05:59:33 PM PDT 24 Jul 05 05:59:42 PM PDT 24 3179842001 ps
T947 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3017672167 Jul 05 05:59:30 PM PDT 24 Jul 05 05:59:37 PM PDT 24 496559277 ps
T139 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1616028862 Jul 05 05:59:37 PM PDT 24 Jul 05 05:59:40 PM PDT 24 240783226 ps
T948 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.521924849 Jul 05 05:59:30 PM PDT 24 Jul 05 06:00:15 PM PDT 24 4120102511 ps
T949 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1555256108 Jul 05 05:59:23 PM PDT 24 Jul 05 05:59:25 PM PDT 24 90557867 ps
T950 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3311851485 Jul 05 05:59:50 PM PDT 24 Jul 05 05:59:52 PM PDT 24 18617821 ps
T951 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.922374119 Jul 05 05:59:33 PM PDT 24 Jul 05 05:59:35 PM PDT 24 25213917 ps
T217 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3279470604 Jul 05 05:59:41 PM PDT 24 Jul 05 05:59:43 PM PDT 24 12637922 ps
T952 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3300691843 Jul 05 05:59:29 PM PDT 24 Jul 05 05:59:32 PM PDT 24 2061020477 ps
T953 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1767419133 Jul 05 05:59:30 PM PDT 24 Jul 05 05:59:35 PM PDT 24 259049623 ps
T954 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.874600881 Jul 05 05:59:28 PM PDT 24 Jul 05 05:59:30 PM PDT 24 16296534 ps
T955 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.424993494 Jul 05 05:59:33 PM PDT 24 Jul 05 05:59:35 PM PDT 24 15588393 ps
T956 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.330286719 Jul 05 05:59:31 PM PDT 24 Jul 05 05:59:35 PM PDT 24 228231238 ps
T957 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3439737889 Jul 05 05:59:35 PM PDT 24 Jul 05 05:59:37 PM PDT 24 87812775 ps
T958 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.477242145 Jul 05 05:59:31 PM PDT 24 Jul 05 05:59:35 PM PDT 24 222480466 ps
T959 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2383055318 Jul 05 05:59:43 PM PDT 24 Jul 05 05:59:44 PM PDT 24 155906708 ps
T960 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3417024647 Jul 05 05:59:25 PM PDT 24 Jul 05 05:59:28 PM PDT 24 128002803 ps
T961 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3268573615 Jul 05 05:59:34 PM PDT 24 Jul 05 05:59:51 PM PDT 24 729299981 ps
T962 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3216412568 Jul 05 05:59:34 PM PDT 24 Jul 05 05:59:38 PM PDT 24 138504661 ps
T963 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1598910668 Jul 05 05:59:34 PM PDT 24 Jul 05 05:59:36 PM PDT 24 56669486 ps
T964 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1861121597 Jul 05 05:59:57 PM PDT 24 Jul 05 06:00:00 PM PDT 24 150005688 ps
T965 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.376112088 Jul 05 05:59:46 PM PDT 24 Jul 05 05:59:48 PM PDT 24 167516100 ps
T966 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2689102688 Jul 05 05:59:27 PM PDT 24 Jul 05 05:59:29 PM PDT 24 688891494 ps
T218 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1202664339 Jul 05 05:59:31 PM PDT 24 Jul 05 05:59:33 PM PDT 24 31716123 ps
T967 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.4149258925 Jul 05 05:59:30 PM PDT 24 Jul 05 05:59:33 PM PDT 24 484447341 ps
T968 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.210146067 Jul 05 05:59:33 PM PDT 24 Jul 05 05:59:35 PM PDT 24 80343483 ps
T969 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2771782985 Jul 05 05:59:32 PM PDT 24 Jul 05 05:59:39 PM PDT 24 665837347 ps
T970 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2919175045 Jul 05 05:59:37 PM PDT 24 Jul 05 05:59:39 PM PDT 24 152158046 ps
T971 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3714419656 Jul 05 05:59:33 PM PDT 24 Jul 05 05:59:49 PM PDT 24 2615321304 ps
T972 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1891843624 Jul 05 05:59:40 PM PDT 24 Jul 05 05:59:43 PM PDT 24 220821137 ps
T973 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3830359627 Jul 05 05:59:30 PM PDT 24 Jul 05 05:59:34 PM PDT 24 96610999 ps
T219 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1687079431 Jul 05 05:59:31 PM PDT 24 Jul 05 05:59:33 PM PDT 24 20667489 ps
T974 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.4033681986 Jul 05 05:59:40 PM PDT 24 Jul 05 05:59:42 PM PDT 24 59427567 ps
T975 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.864971469 Jul 05 05:59:42 PM PDT 24 Jul 05 05:59:44 PM PDT 24 37223101 ps
T976 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3595976565 Jul 05 05:59:46 PM PDT 24 Jul 05 05:59:50 PM PDT 24 1115759050 ps
T977 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.98424631 Jul 05 05:59:40 PM PDT 24 Jul 05 05:59:45 PM PDT 24 874665783 ps
T126 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1915745265 Jul 05 05:59:24 PM PDT 24 Jul 05 05:59:27 PM PDT 24 42082130 ps
T978 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.903082821 Jul 05 05:59:29 PM PDT 24 Jul 05 05:59:32 PM PDT 24 82025989 ps
T979 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2455238642 Jul 05 05:59:38 PM PDT 24 Jul 05 05:59:42 PM PDT 24 291714244 ps
T980 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.51618601 Jul 05 05:59:35 PM PDT 24 Jul 05 05:59:42 PM PDT 24 76041245 ps
T981 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1327499001 Jul 05 05:59:41 PM PDT 24 Jul 05 05:59:44 PM PDT 24 291007948 ps
T982 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1475851545 Jul 05 05:59:37 PM PDT 24 Jul 05 05:59:38 PM PDT 24 48720496 ps
T137 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3205710247 Jul 05 05:59:43 PM PDT 24 Jul 05 05:59:45 PM PDT 24 443683994 ps
T983 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2879059830 Jul 05 05:59:50 PM PDT 24 Jul 05 05:59:54 PM PDT 24 18290542 ps
T984 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.203812711 Jul 05 05:59:27 PM PDT 24 Jul 05 05:59:29 PM PDT 24 111057356 ps
T985 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2136158884 Jul 05 05:59:49 PM PDT 24 Jul 05 05:59:52 PM PDT 24 104762891 ps
T220 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1488566953 Jul 05 05:59:31 PM PDT 24 Jul 05 05:59:34 PM PDT 24 102621327 ps
T132 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4142939631 Jul 05 05:59:52 PM PDT 24 Jul 05 05:59:56 PM PDT 24 561466510 ps
T986 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2002637035 Jul 05 05:59:24 PM PDT 24 Jul 05 05:59:26 PM PDT 24 68429815 ps
T987 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3378548473 Jul 05 05:59:36 PM PDT 24 Jul 05 05:59:38 PM PDT 24 337738189 ps
T988 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.4176154468 Jul 05 05:59:30 PM PDT 24 Jul 05 05:59:45 PM PDT 24 2833626319 ps
T127 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.758544734 Jul 05 05:59:38 PM PDT 24 Jul 05 05:59:41 PM PDT 24 497414492 ps
T989 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2589998041 Jul 05 05:59:48 PM PDT 24 Jul 05 05:59:50 PM PDT 24 33702480 ps
T990 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2012815596 Jul 05 05:59:42 PM PDT 24 Jul 05 05:59:45 PM PDT 24 111234910 ps
T991 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1786391541 Jul 05 06:02:35 PM PDT 24 Jul 05 06:02:36 PM PDT 24 51881769 ps
T138 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.433292580 Jul 05 05:59:34 PM PDT 24 Jul 05 05:59:38 PM PDT 24 398288230 ps

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1176443084
Short name T1
Test name
Test status
Simulation time 407495736 ps
CPU time 10.06 seconds
Started Jul 05 05:30:02 PM PDT 24
Finished Jul 05 05:30:14 PM PDT 24
Peak memory 226052 kb
Host smart-f19656ea-e8fa-400e-acb4-6f455c976cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176443084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1176443084
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.3256834525
Short name T14
Test name
Test status
Simulation time 18865736603 ps
CPU time 172.51 seconds
Started Jul 05 05:29:38 PM PDT 24
Finished Jul 05 05:32:31 PM PDT 24
Peak memory 275156 kb
Host smart-bb53b16d-d581-4fda-bab0-e38e339aaba6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256834525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.3256834525
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.1558052025
Short name T54
Test name
Test status
Simulation time 55857154751 ps
CPU time 613.24 seconds
Started Jul 05 05:28:55 PM PDT 24
Finished Jul 05 05:39:09 PM PDT 24
Peak memory 275772 kb
Host smart-c6cea80d-a0f2-429b-823c-c62c4c86e9dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1558052025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.1558052025
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.1434866975
Short name T15
Test name
Test status
Simulation time 426467728 ps
CPU time 17.96 seconds
Started Jul 05 05:30:00 PM PDT 24
Finished Jul 05 05:30:19 PM PDT 24
Peak memory 226048 kb
Host smart-2b17e0b4-680e-4f11-9d3a-dc0c0132d98f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434866975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1434866975
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1853681054
Short name T111
Test name
Test status
Simulation time 1239908826 ps
CPU time 7.87 seconds
Started Jul 05 05:59:40 PM PDT 24
Finished Jul 05 05:59:49 PM PDT 24
Peak memory 217580 kb
Host smart-bb4516ec-235d-43fd-9000-74383aff1eba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185368
1054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1853681054
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3166511451
Short name T19
Test name
Test status
Simulation time 150619552 ps
CPU time 3.17 seconds
Started Jul 05 05:29:53 PM PDT 24
Finished Jul 05 05:29:57 PM PDT 24
Peak memory 226408 kb
Host smart-f1340c1d-bfa1-44bb-8266-43d202e6d2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166511451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3166511451
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2765831434
Short name T48
Test name
Test status
Simulation time 878272728 ps
CPU time 42.92 seconds
Started Jul 05 05:27:32 PM PDT 24
Finished Jul 05 05:28:16 PM PDT 24
Peak memory 284560 kb
Host smart-a6975902-c218-45aa-943a-d78f142fc6f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765831434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2765831434
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.1877973995
Short name T8
Test name
Test status
Simulation time 727001948 ps
CPU time 7.18 seconds
Started Jul 05 05:28:50 PM PDT 24
Finished Jul 05 05:28:57 PM PDT 24
Peak memory 217072 kb
Host smart-6358fd92-d66e-435f-b6f4-9b26f2cc8701
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877973995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.1877973995
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.3925828167
Short name T22
Test name
Test status
Simulation time 246593181 ps
CPU time 9.27 seconds
Started Jul 05 05:27:38 PM PDT 24
Finished Jul 05 05:27:51 PM PDT 24
Peak memory 218204 kb
Host smart-3fd9e79d-bebd-4ebe-983f-76d8b1348e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925828167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3925828167
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3049918572
Short name T107
Test name
Test status
Simulation time 152635855 ps
CPU time 2.16 seconds
Started Jul 05 05:59:47 PM PDT 24
Finished Jul 05 05:59:50 PM PDT 24
Peak memory 213092 kb
Host smart-807ee32a-09da-4fc7-93c3-ae06dda671c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049918572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3049918572
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.591055202
Short name T12
Test name
Test status
Simulation time 13288362 ps
CPU time 0.99 seconds
Started Jul 05 05:30:05 PM PDT 24
Finished Jul 05 05:30:06 PM PDT 24
Peak memory 209056 kb
Host smart-18a818dd-ca6c-451d-b13d-b2d3a3ebb45d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591055202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.591055202
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.472580416
Short name T21
Test name
Test status
Simulation time 1042360551 ps
CPU time 15.77 seconds
Started Jul 05 05:29:13 PM PDT 24
Finished Jul 05 05:29:30 PM PDT 24
Peak memory 226036 kb
Host smart-3ed7eb4a-5f7e-48a8-8b49-3b784ed06d37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472580416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.472580416
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.747959814
Short name T213
Test name
Test status
Simulation time 23659553 ps
CPU time 1.02 seconds
Started Jul 05 05:59:35 PM PDT 24
Finished Jul 05 05:59:36 PM PDT 24
Peak memory 210648 kb
Host smart-ab8e393a-5ea1-4ef0-b585-a4526f6b4390
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747959814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset
.747959814
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.2970876754
Short name T53
Test name
Test status
Simulation time 52633923365 ps
CPU time 536.72 seconds
Started Jul 05 05:29:03 PM PDT 24
Finished Jul 05 05:38:01 PM PDT 24
Peak memory 283948 kb
Host smart-b81c5fe4-98b7-4a63-b111-7a9d76d14153
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2970876754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.2970876754
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2711240391
Short name T133
Test name
Test status
Simulation time 170723193 ps
CPU time 3.5 seconds
Started Jul 05 05:59:54 PM PDT 24
Finished Jul 05 05:59:58 PM PDT 24
Peak memory 217480 kb
Host smart-e884dab4-7db7-4ea9-b55b-9635248c9bf1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711240391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2711240391
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.79667991
Short name T125
Test name
Test status
Simulation time 209964173 ps
CPU time 2.88 seconds
Started Jul 05 05:59:36 PM PDT 24
Finished Jul 05 05:59:39 PM PDT 24
Peak memory 213380 kb
Host smart-4d07b9c8-c15e-4ea3-b936-dc85ef09e783
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79667991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_er
r.79667991
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3258633651
Short name T140
Test name
Test status
Simulation time 120798098 ps
CPU time 2.86 seconds
Started Jul 05 05:59:42 PM PDT 24
Finished Jul 05 05:59:45 PM PDT 24
Peak memory 222052 kb
Host smart-01538cf7-2f9c-4e8e-8d05-f6b15cf0d2a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258633651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.3258633651
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1814405642
Short name T550
Test name
Test status
Simulation time 2609053872 ps
CPU time 13.82 seconds
Started Jul 05 05:27:33 PM PDT 24
Finished Jul 05 05:27:49 PM PDT 24
Peak memory 218964 kb
Host smart-b88b780e-6446-47b2-a8d3-8e9befad9511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814405642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1814405642
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.488132343
Short name T43
Test name
Test status
Simulation time 14116954061 ps
CPU time 328.18 seconds
Started Jul 05 05:27:31 PM PDT 24
Finished Jul 05 05:33:00 PM PDT 24
Peak memory 283900 kb
Host smart-c3e253a0-aeca-49c6-b694-935a10cd45d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=488132343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.488132343
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.649230293
Short name T703
Test name
Test status
Simulation time 4718283879 ps
CPU time 143.33 seconds
Started Jul 05 05:28:33 PM PDT 24
Finished Jul 05 05:30:58 PM PDT 24
Peak memory 332764 kb
Host smart-5aaa1082-c30e-4e11-82aa-328df828e649
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649230293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.649230293
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1175361376
Short name T124
Test name
Test status
Simulation time 1100388985 ps
CPU time 2.49 seconds
Started Jul 05 05:59:23 PM PDT 24
Finished Jul 05 05:59:26 PM PDT 24
Peak memory 217764 kb
Host smart-ebaa0ec6-be8c-44f0-aa68-4765980183e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117536
1376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1175361376
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4142939631
Short name T132
Test name
Test status
Simulation time 561466510 ps
CPU time 3.05 seconds
Started Jul 05 05:59:52 PM PDT 24
Finished Jul 05 05:59:56 PM PDT 24
Peak memory 222332 kb
Host smart-e7b107b6-7414-4ac8-a77a-9d6c0def4157
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142939631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.4142939631
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1909143331
Short name T223
Test name
Test status
Simulation time 107502042 ps
CPU time 1.08 seconds
Started Jul 05 05:59:45 PM PDT 24
Finished Jul 05 05:59:46 PM PDT 24
Peak memory 209308 kb
Host smart-137b4e04-620c-48d1-9678-5177678d5a48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909143331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.1909143331
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3264643753
Short name T3
Test name
Test status
Simulation time 48477834 ps
CPU time 0.83 seconds
Started Jul 05 05:28:42 PM PDT 24
Finished Jul 05 05:28:44 PM PDT 24
Peak memory 211876 kb
Host smart-486285fa-7385-4181-aeaf-e9058a8195e4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264643753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3264643753
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2302995583
Short name T135
Test name
Test status
Simulation time 64136635 ps
CPU time 2.89 seconds
Started Jul 05 05:59:30 PM PDT 24
Finished Jul 05 05:59:34 PM PDT 24
Peak memory 217500 kb
Host smart-e73f1993-5564-4c0e-97c0-8a0ff57b2723
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302995583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.2302995583
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2144743854
Short name T112
Test name
Test status
Simulation time 195663486 ps
CPU time 3.67 seconds
Started Jul 05 05:59:40 PM PDT 24
Finished Jul 05 05:59:44 PM PDT 24
Peak memory 217512 kb
Host smart-ddada367-47eb-4dfa-b8c8-cff3693f7bf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144743854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.2144743854
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.2251441817
Short name T231
Test name
Test status
Simulation time 30998249 ps
CPU time 0.87 seconds
Started Jul 05 05:27:33 PM PDT 24
Finished Jul 05 05:27:36 PM PDT 24
Peak memory 208976 kb
Host smart-16afb390-349e-49ed-9180-f8190a89a5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251441817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.2251441817
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2393977824
Short name T83
Test name
Test status
Simulation time 850091421 ps
CPU time 11.44 seconds
Started Jul 05 05:28:29 PM PDT 24
Finished Jul 05 05:28:42 PM PDT 24
Peak memory 226048 kb
Host smart-4b1007e6-7bd3-4bfc-ad32-8bc56a87e720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393977824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2393977824
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.4030586464
Short name T230
Test name
Test status
Simulation time 33290996 ps
CPU time 0.81 seconds
Started Jul 05 05:27:45 PM PDT 24
Finished Jul 05 05:27:46 PM PDT 24
Peak memory 208860 kb
Host smart-244924ae-74f8-454c-8507-3795bf017505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030586464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.4030586464
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.988346596
Short name T71
Test name
Test status
Simulation time 16386830 ps
CPU time 0.81 seconds
Started Jul 05 05:27:56 PM PDT 24
Finished Jul 05 05:27:59 PM PDT 24
Peak memory 208768 kb
Host smart-a8f65b1e-78f1-4f15-9053-6625dfa06941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988346596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.988346596
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1915745265
Short name T126
Test name
Test status
Simulation time 42082130 ps
CPU time 2.09 seconds
Started Jul 05 05:59:24 PM PDT 24
Finished Jul 05 05:59:27 PM PDT 24
Peak memory 217504 kb
Host smart-c3e80f6a-d8bd-4a4f-99e8-9c5029e84a8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915745265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.1915745265
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1825627802
Short name T131
Test name
Test status
Simulation time 45573539 ps
CPU time 2.25 seconds
Started Jul 05 05:59:43 PM PDT 24
Finished Jul 05 05:59:46 PM PDT 24
Peak memory 217560 kb
Host smart-94a30ca5-a370-4ff9-bf82-141f7e548581
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825627802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1825627802
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1009149828
Short name T120
Test name
Test status
Simulation time 848099696 ps
CPU time 1.93 seconds
Started Jul 05 05:59:32 PM PDT 24
Finished Jul 05 05:59:35 PM PDT 24
Peak memory 221924 kb
Host smart-6fc3c508-04e6-4a26-9ae7-23e0f413518f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009149828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.1009149828
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.870597638
Short name T113
Test name
Test status
Simulation time 47537639 ps
CPU time 1.92 seconds
Started Jul 05 06:00:02 PM PDT 24
Finished Jul 05 06:00:04 PM PDT 24
Peak memory 221684 kb
Host smart-7d6d092f-ca25-4f35-9101-c3d2ed6c5f99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870597638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_
err.870597638
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2235043745
Short name T143
Test name
Test status
Simulation time 223204613 ps
CPU time 2.55 seconds
Started Jul 05 05:59:37 PM PDT 24
Finished Jul 05 05:59:40 PM PDT 24
Peak memory 217556 kb
Host smart-69317f79-f463-44cc-8380-f0f4bd92e689
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235043745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2235043745
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.758544734
Short name T127
Test name
Test status
Simulation time 497414492 ps
CPU time 2.63 seconds
Started Jul 05 05:59:38 PM PDT 24
Finished Jul 05 05:59:41 PM PDT 24
Peak memory 217564 kb
Host smart-65e0eb53-9653-44d2-acd1-5bb712861bcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758544734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_e
rr.758544734
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.508679797
Short name T115
Test name
Test status
Simulation time 80977632 ps
CPU time 2.74 seconds
Started Jul 05 05:59:36 PM PDT 24
Finished Jul 05 05:59:39 PM PDT 24
Peak memory 217488 kb
Host smart-6401e24b-f51d-4a92-902f-806345be0572
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508679797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.508679797
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.3977666942
Short name T42
Test name
Test status
Simulation time 6376518306 ps
CPU time 16.01 seconds
Started Jul 05 05:29:02 PM PDT 24
Finished Jul 05 05:29:20 PM PDT 24
Peak memory 218588 kb
Host smart-8f874a37-731a-45b4-8e6c-5f6b2c0b2a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977666942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3977666942
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2945750449
Short name T11
Test name
Test status
Simulation time 610287304 ps
CPU time 8.34 seconds
Started Jul 05 05:30:08 PM PDT 24
Finished Jul 05 05:30:17 PM PDT 24
Peak memory 226044 kb
Host smart-89df3504-93c3-4fdf-9ac1-ad663200f7a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945750449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2945750449
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.4256026051
Short name T7
Test name
Test status
Simulation time 207740613 ps
CPU time 4.06 seconds
Started Jul 05 05:28:15 PM PDT 24
Finished Jul 05 05:28:22 PM PDT 24
Peak memory 217716 kb
Host smart-34bdd80a-8f7f-4de3-97b5-e48925f3e239
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256026051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.4256026051
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.504267261
Short name T212
Test name
Test status
Simulation time 157515018 ps
CPU time 1 seconds
Started Jul 05 05:59:31 PM PDT 24
Finished Jul 05 05:59:33 PM PDT 24
Peak memory 209184 kb
Host smart-b4693f05-6ec2-42c8-bae4-c8aa322333c3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504267261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing
.504267261
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.294256341
Short name T121
Test name
Test status
Simulation time 55665910 ps
CPU time 2.13 seconds
Started Jul 05 05:59:25 PM PDT 24
Finished Jul 05 05:59:28 PM PDT 24
Peak memory 209232 kb
Host smart-6cc8e24d-a8dc-42a5-9094-31b2b0b16341
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294256341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash
.294256341
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1797639863
Short name T924
Test name
Test status
Simulation time 69301029 ps
CPU time 1.58 seconds
Started Jul 05 05:59:40 PM PDT 24
Finished Jul 05 05:59:42 PM PDT 24
Peak memory 219704 kb
Host smart-a4608162-846d-4e16-aa91-ca820d44a725
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797639863 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1797639863
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2276187419
Short name T210
Test name
Test status
Simulation time 43218769 ps
CPU time 1.02 seconds
Started Jul 05 05:59:27 PM PDT 24
Finished Jul 05 05:59:29 PM PDT 24
Peak memory 209156 kb
Host smart-1f2958b7-2e01-4bc2-8151-8c4ee2eb4018
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276187419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2276187419
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.4035381788
Short name T889
Test name
Test status
Simulation time 83197123 ps
CPU time 1.19 seconds
Started Jul 05 05:59:30 PM PDT 24
Finished Jul 05 05:59:33 PM PDT 24
Peak memory 209104 kb
Host smart-7f45b99a-4c83-4b70-9cd0-9aa11fb625ec
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035381788 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.4035381788
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.797365157
Short name T942
Test name
Test status
Simulation time 4493548949 ps
CPU time 7.65 seconds
Started Jul 05 05:59:22 PM PDT 24
Finished Jul 05 05:59:31 PM PDT 24
Peak memory 217340 kb
Host smart-58f9d05a-1b3d-4004-9c1a-d30fe5b9c8ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797365157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.797365157
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3819289841
Short name T880
Test name
Test status
Simulation time 1118076937 ps
CPU time 4.96 seconds
Started Jul 05 05:59:25 PM PDT 24
Finished Jul 05 05:59:30 PM PDT 24
Peak memory 217028 kb
Host smart-05f7b7ad-43d5-4067-a395-72c220761015
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819289841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.3819289841
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2689102688
Short name T966
Test name
Test status
Simulation time 688891494 ps
CPU time 1.38 seconds
Started Jul 05 05:59:27 PM PDT 24
Finished Jul 05 05:59:29 PM PDT 24
Peak memory 210724 kb
Host smart-032e8d28-a298-4720-9bce-a08e5aa1ab58
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689102688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.2689102688
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2674727708
Short name T145
Test name
Test status
Simulation time 73758478 ps
CPU time 1.45 seconds
Started Jul 05 05:59:24 PM PDT 24
Finished Jul 05 05:59:26 PM PDT 24
Peak memory 209304 kb
Host smart-824ffd12-3c65-4a26-9bae-fbfb7e32bf65
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674727708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2674727708
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.874600881
Short name T954
Test name
Test status
Simulation time 16296534 ps
CPU time 1.24 seconds
Started Jul 05 05:59:28 PM PDT 24
Finished Jul 05 05:59:30 PM PDT 24
Peak memory 217560 kb
Host smart-82d37011-6cd1-48e8-ba81-bcc02f203d87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874600881 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.874600881
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.424993494
Short name T955
Test name
Test status
Simulation time 15588393 ps
CPU time 1.03 seconds
Started Jul 05 05:59:33 PM PDT 24
Finished Jul 05 05:59:35 PM PDT 24
Peak memory 209224 kb
Host smart-a3b6df35-67bb-4ba6-9060-03d80af7647c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424993494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
same_csr_outstanding.424993494
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.166904119
Short name T939
Test name
Test status
Simulation time 337458889 ps
CPU time 3.46 seconds
Started Jul 05 05:59:28 PM PDT 24
Finished Jul 05 05:59:32 PM PDT 24
Peak memory 217744 kb
Host smart-4b076e61-535d-41c2-9a01-0001f45534a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166904119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.166904119
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2640070726
Short name T211
Test name
Test status
Simulation time 59257512 ps
CPU time 1.22 seconds
Started Jul 05 05:59:26 PM PDT 24
Finished Jul 05 05:59:28 PM PDT 24
Peak memory 217464 kb
Host smart-9c72eb1e-5a8d-4cbd-85c7-9c0480fff8ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640070726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.2640070726
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3109319138
Short name T872
Test name
Test status
Simulation time 443026174 ps
CPU time 1.75 seconds
Started Jul 05 05:59:25 PM PDT 24
Finished Jul 05 05:59:28 PM PDT 24
Peak memory 209440 kb
Host smart-33538afc-2e32-4a89-86d9-4404dbb9b9d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109319138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3109319138
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2736816317
Short name T209
Test name
Test status
Simulation time 31711529 ps
CPU time 1.27 seconds
Started Jul 05 05:59:21 PM PDT 24
Finished Jul 05 05:59:22 PM PDT 24
Peak memory 217584 kb
Host smart-0655ff6d-b1fd-4fe7-895e-fbad07f8abac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736816317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.2736816317
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.375208012
Short name T898
Test name
Test status
Simulation time 75234880 ps
CPU time 1.05 seconds
Started Jul 05 05:59:28 PM PDT 24
Finished Jul 05 05:59:30 PM PDT 24
Peak memory 218612 kb
Host smart-b06da7a6-182f-455e-8443-22cad8f190dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375208012 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.375208012
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3467270527
Short name T875
Test name
Test status
Simulation time 91699231 ps
CPU time 0.86 seconds
Started Jul 05 05:59:24 PM PDT 24
Finished Jul 05 05:59:26 PM PDT 24
Peak memory 209356 kb
Host smart-2d264af3-2369-49c7-be14-cce033dd7baf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467270527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.3467270527
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.303909060
Short name T150
Test name
Test status
Simulation time 29294378 ps
CPU time 1.47 seconds
Started Jul 05 05:59:26 PM PDT 24
Finished Jul 05 05:59:28 PM PDT 24
Peak memory 209180 kb
Host smart-3a8ff33f-ff56-4ee0-9586-627fe5793c11
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303909060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.303909060
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.806943199
Short name T922
Test name
Test status
Simulation time 4597490125 ps
CPU time 6.67 seconds
Started Jul 05 05:59:30 PM PDT 24
Finished Jul 05 05:59:38 PM PDT 24
Peak memory 217428 kb
Host smart-b0fa94b1-11fa-45f9-ba39-cadd4ec7a8c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806943199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.806943199
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.4011702765
Short name T151
Test name
Test status
Simulation time 494624406 ps
CPU time 5.45 seconds
Started Jul 05 05:59:35 PM PDT 24
Finished Jul 05 05:59:41 PM PDT 24
Peak memory 216960 kb
Host smart-05a8fb6a-6726-489a-81a3-37b074790245
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011702765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.4011702765
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3300691843
Short name T952
Test name
Test status
Simulation time 2061020477 ps
CPU time 2.1 seconds
Started Jul 05 05:59:29 PM PDT 24
Finished Jul 05 05:59:32 PM PDT 24
Peak memory 210896 kb
Host smart-108dcd49-076d-48d7-829d-261f5ed07ff5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300691843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.3300691843
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1457102998
Short name T879
Test name
Test status
Simulation time 532552916 ps
CPU time 2.01 seconds
Started Jul 05 05:59:30 PM PDT 24
Finished Jul 05 05:59:34 PM PDT 24
Peak memory 220152 kb
Host smart-8fe136ff-8fc4-47b3-af3b-5ae25a737336
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145710
2998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1457102998
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.4068171348
Short name T897
Test name
Test status
Simulation time 76420922 ps
CPU time 2.65 seconds
Started Jul 05 05:59:25 PM PDT 24
Finished Jul 05 05:59:28 PM PDT 24
Peak memory 209268 kb
Host smart-99e0aa92-1135-4959-84b6-466714418b21
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068171348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.4068171348
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.852126305
Short name T893
Test name
Test status
Simulation time 20402571 ps
CPU time 1.19 seconds
Started Jul 05 05:59:23 PM PDT 24
Finished Jul 05 05:59:24 PM PDT 24
Peak memory 211280 kb
Host smart-b18b2f35-c2e8-43d4-a2da-447be1486cb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852126305 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.852126305
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2937060604
Short name T887
Test name
Test status
Simulation time 34516370 ps
CPU time 1.28 seconds
Started Jul 05 05:59:25 PM PDT 24
Finished Jul 05 05:59:27 PM PDT 24
Peak memory 209288 kb
Host smart-e24db385-bed5-4713-b527-708c55c3fb68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937060604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.2937060604
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.330286719
Short name T956
Test name
Test status
Simulation time 228231238 ps
CPU time 3.02 seconds
Started Jul 05 05:59:31 PM PDT 24
Finished Jul 05 05:59:35 PM PDT 24
Peak memory 217500 kb
Host smart-f22ed91e-2dfe-42b9-ad8c-7b8e17e69936
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330286719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.330286719
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2727030569
Short name T116
Test name
Test status
Simulation time 47550031 ps
CPU time 1.37 seconds
Started Jul 05 06:00:07 PM PDT 24
Finished Jul 05 06:00:09 PM PDT 24
Peak memory 221800 kb
Host smart-76243fc6-6446-4875-bdff-72c837499825
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727030569 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2727030569
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3027690273
Short name T914
Test name
Test status
Simulation time 87772199 ps
CPU time 0.86 seconds
Started Jul 05 05:59:49 PM PDT 24
Finished Jul 05 05:59:52 PM PDT 24
Peak memory 209340 kb
Host smart-9ee0c00b-b6aa-43eb-b693-9b52442d3fc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027690273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3027690273
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2508736942
Short name T931
Test name
Test status
Simulation time 144269098 ps
CPU time 2.75 seconds
Started Jul 05 05:59:50 PM PDT 24
Finished Jul 05 05:59:55 PM PDT 24
Peak memory 217568 kb
Host smart-248a6500-8785-4bb3-ba58-abf6c87c61db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508736942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2508736942
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2136158884
Short name T985
Test name
Test status
Simulation time 104762891 ps
CPU time 1.68 seconds
Started Jul 05 05:59:49 PM PDT 24
Finished Jul 05 05:59:52 PM PDT 24
Peak memory 219804 kb
Host smart-4bfef88d-b3bb-49e8-960c-7d982487ecd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136158884 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.2136158884
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3089914987
Short name T215
Test name
Test status
Simulation time 26452779 ps
CPU time 1.05 seconds
Started Jul 05 05:59:47 PM PDT 24
Finished Jul 05 05:59:49 PM PDT 24
Peak memory 209368 kb
Host smart-46f35d19-08a7-420b-bad0-37501a7a0cf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089914987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3089914987
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.577235468
Short name T888
Test name
Test status
Simulation time 33243936 ps
CPU time 1.24 seconds
Started Jul 05 05:59:45 PM PDT 24
Finished Jul 05 05:59:47 PM PDT 24
Peak memory 217532 kb
Host smart-ad981232-e763-4a1b-970a-2b22b1f4604a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577235468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_same_csr_outstanding.577235468
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3216412568
Short name T962
Test name
Test status
Simulation time 138504661 ps
CPU time 3.21 seconds
Started Jul 05 05:59:34 PM PDT 24
Finished Jul 05 05:59:38 PM PDT 24
Peak memory 217476 kb
Host smart-aca11d3d-6431-4cea-b88b-84fd667aafd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216412568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3216412568
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3507670984
Short name T136
Test name
Test status
Simulation time 57904206 ps
CPU time 0.95 seconds
Started Jul 05 05:59:47 PM PDT 24
Finished Jul 05 05:59:49 PM PDT 24
Peak memory 217636 kb
Host smart-4261248f-3e9e-47e9-8fda-e0a555dc6071
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507670984 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.3507670984
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.315907594
Short name T214
Test name
Test status
Simulation time 41206282 ps
CPU time 0.98 seconds
Started Jul 05 05:59:43 PM PDT 24
Finished Jul 05 05:59:45 PM PDT 24
Peak memory 209352 kb
Host smart-2aa5dc7a-82a1-40f6-bf9e-abaeeedffb6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315907594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.315907594
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1267562665
Short name T938
Test name
Test status
Simulation time 15123236 ps
CPU time 1.05 seconds
Started Jul 05 05:59:32 PM PDT 24
Finished Jul 05 05:59:34 PM PDT 24
Peak memory 209372 kb
Host smart-d3c9e6a2-adf0-45ed-98e1-bfbec04de11e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267562665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.1267562665
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.967288971
Short name T920
Test name
Test status
Simulation time 158977000 ps
CPU time 3.06 seconds
Started Jul 05 06:00:02 PM PDT 24
Finished Jul 05 06:00:06 PM PDT 24
Peak memory 217612 kb
Host smart-9e638739-ce06-49b1-a53b-d8eb412fb465
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967288971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.967288971
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.969669398
Short name T903
Test name
Test status
Simulation time 41508828 ps
CPU time 2.13 seconds
Started Jul 05 05:59:49 PM PDT 24
Finished Jul 05 05:59:52 PM PDT 24
Peak memory 221312 kb
Host smart-39a8d46f-7cf9-4215-b46c-c062d25717cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969669398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_
err.969669398
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.638785126
Short name T944
Test name
Test status
Simulation time 231455666 ps
CPU time 1.35 seconds
Started Jul 05 05:59:48 PM PDT 24
Finished Jul 05 05:59:50 PM PDT 24
Peak memory 222588 kb
Host smart-6de0c6b4-7342-4afb-bf23-f3dcab94fcf9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638785126 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.638785126
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.38169111
Short name T873
Test name
Test status
Simulation time 39472006 ps
CPU time 0.81 seconds
Started Jul 05 05:59:59 PM PDT 24
Finished Jul 05 06:00:00 PM PDT 24
Peak memory 209244 kb
Host smart-63284027-ee44-47f6-b5f2-da08b32dc4ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38169111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.38169111
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3439737889
Short name T957
Test name
Test status
Simulation time 87812775 ps
CPU time 1.06 seconds
Started Jul 05 05:59:35 PM PDT 24
Finished Jul 05 05:59:37 PM PDT 24
Peak memory 209340 kb
Host smart-b423c247-70a4-463a-9c30-14713b18b561
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439737889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.3439737889
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3198015723
Short name T134
Test name
Test status
Simulation time 601739704 ps
CPU time 2.74 seconds
Started Jul 05 05:59:48 PM PDT 24
Finished Jul 05 05:59:51 PM PDT 24
Peak memory 217524 kb
Host smart-1b58eccf-8906-4e70-907b-eeb55c49885c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198015723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3198015723
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1532794275
Short name T927
Test name
Test status
Simulation time 29558764 ps
CPU time 2.21 seconds
Started Jul 05 05:59:39 PM PDT 24
Finished Jul 05 05:59:42 PM PDT 24
Peak memory 217708 kb
Host smart-7a51f5de-9458-45c7-a080-030157535974
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532794275 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1532794275
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1250869857
Short name T915
Test name
Test status
Simulation time 14820349 ps
CPU time 0.92 seconds
Started Jul 05 05:59:33 PM PDT 24
Finished Jul 05 05:59:35 PM PDT 24
Peak memory 209372 kb
Host smart-488fcc3c-7a7b-4bbd-a12d-6431bae15554
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250869857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1250869857
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2879059830
Short name T983
Test name
Test status
Simulation time 18290542 ps
CPU time 1.17 seconds
Started Jul 05 05:59:50 PM PDT 24
Finished Jul 05 05:59:54 PM PDT 24
Peak memory 209376 kb
Host smart-c7fdefdd-f870-4465-a85c-24a4e2a602f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879059830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2879059830
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1861121597
Short name T964
Test name
Test status
Simulation time 150005688 ps
CPU time 2.3 seconds
Started Jul 05 05:59:57 PM PDT 24
Finished Jul 05 06:00:00 PM PDT 24
Peak memory 217576 kb
Host smart-662d7584-3834-4459-b02f-1743fe96e45c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861121597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.1861121597
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.4116260287
Short name T108
Test name
Test status
Simulation time 48261671 ps
CPU time 1.31 seconds
Started Jul 05 05:59:41 PM PDT 24
Finished Jul 05 05:59:43 PM PDT 24
Peak memory 217704 kb
Host smart-d8de7109-e7f2-41f1-b7e8-a099eab37437
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116260287 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.4116260287
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2069361366
Short name T919
Test name
Test status
Simulation time 13798921 ps
CPU time 0.87 seconds
Started Jul 05 05:59:32 PM PDT 24
Finished Jul 05 05:59:34 PM PDT 24
Peak memory 209252 kb
Host smart-94078b42-8ef1-46e2-975c-52044e50683d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069361366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2069361366
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.436763786
Short name T221
Test name
Test status
Simulation time 41567701 ps
CPU time 1.24 seconds
Started Jul 05 05:59:32 PM PDT 24
Finished Jul 05 05:59:35 PM PDT 24
Peak memory 209372 kb
Host smart-51720280-05f9-441e-b756-970738e26482
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436763786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.436763786
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2487363280
Short name T130
Test name
Test status
Simulation time 128505552 ps
CPU time 4.49 seconds
Started Jul 05 05:59:42 PM PDT 24
Finished Jul 05 05:59:47 PM PDT 24
Peak memory 217576 kb
Host smart-5e8f0221-e55d-4bfd-8eec-11fd02f95366
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487363280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.2487363280
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.4248746781
Short name T142
Test name
Test status
Simulation time 267378419 ps
CPU time 2.09 seconds
Started Jul 05 05:59:40 PM PDT 24
Finished Jul 05 05:59:42 PM PDT 24
Peak memory 222104 kb
Host smart-1d34180f-0ea2-4268-83b3-11aec9cd78ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248746781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.4248746781
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2459158980
Short name T110
Test name
Test status
Simulation time 61925692 ps
CPU time 1.19 seconds
Started Jul 05 05:59:46 PM PDT 24
Finished Jul 05 05:59:49 PM PDT 24
Peak memory 217640 kb
Host smart-af81b09e-9d7c-42a7-8ede-1ebb373e12f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459158980 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2459158980
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3279470604
Short name T217
Test name
Test status
Simulation time 12637922 ps
CPU time 1.04 seconds
Started Jul 05 05:59:41 PM PDT 24
Finished Jul 05 05:59:43 PM PDT 24
Peak memory 209372 kb
Host smart-8cd24630-e8d7-4a3f-803f-ad511cd00f8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279470604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3279470604
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1987220035
Short name T940
Test name
Test status
Simulation time 53821380 ps
CPU time 1.38 seconds
Started Jul 05 05:59:57 PM PDT 24
Finished Jul 05 05:59:58 PM PDT 24
Peak memory 209356 kb
Host smart-af04ae6f-61be-4b87-b2a2-a9ea9a948cff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987220035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.1987220035
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.942903315
Short name T128
Test name
Test status
Simulation time 258754317 ps
CPU time 1.98 seconds
Started Jul 05 05:59:56 PM PDT 24
Finished Jul 05 05:59:58 PM PDT 24
Peak memory 217504 kb
Host smart-770c98cd-539d-4b9b-8635-8947096db4d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942903315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.942903315
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3635699816
Short name T129
Test name
Test status
Simulation time 159511486 ps
CPU time 3.77 seconds
Started Jul 05 05:59:31 PM PDT 24
Finished Jul 05 05:59:36 PM PDT 24
Peak memory 217560 kb
Host smart-213b15b5-95af-4258-86fb-87c13baa98ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635699816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.3635699816
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2099170626
Short name T899
Test name
Test status
Simulation time 29270226 ps
CPU time 1.31 seconds
Started Jul 05 05:59:39 PM PDT 24
Finished Jul 05 05:59:40 PM PDT 24
Peak memory 217676 kb
Host smart-f25f05b7-c630-45c2-961e-750b0f6e5b3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099170626 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2099170626
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1843960931
Short name T118
Test name
Test status
Simulation time 13211561 ps
CPU time 0.83 seconds
Started Jul 05 05:59:38 PM PDT 24
Finished Jul 05 05:59:39 PM PDT 24
Peak memory 208548 kb
Host smart-4f88113e-4401-491e-abda-be47c8aa5202
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843960931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1843960931
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1889079972
Short name T222
Test name
Test status
Simulation time 77652415 ps
CPU time 1.27 seconds
Started Jul 05 05:59:44 PM PDT 24
Finished Jul 05 05:59:46 PM PDT 24
Peak memory 217536 kb
Host smart-ae587c8b-beae-4c0b-8e34-3294e51b395b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889079972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.1889079972
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2455238642
Short name T979
Test name
Test status
Simulation time 291714244 ps
CPU time 3.38 seconds
Started Jul 05 05:59:38 PM PDT 24
Finished Jul 05 05:59:42 PM PDT 24
Peak memory 217508 kb
Host smart-fd9659ac-ada2-48c9-8aa7-73323f9c41cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455238642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2455238642
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.651339194
Short name T900
Test name
Test status
Simulation time 26704144 ps
CPU time 1.84 seconds
Started Jul 05 05:59:47 PM PDT 24
Finished Jul 05 05:59:50 PM PDT 24
Peak memory 217744 kb
Host smart-dd2189b6-eabd-4151-92fa-80b42aa25e71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651339194 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.651339194
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.922374119
Short name T951
Test name
Test status
Simulation time 25213917 ps
CPU time 0.97 seconds
Started Jul 05 05:59:33 PM PDT 24
Finished Jul 05 05:59:35 PM PDT 24
Peak memory 208804 kb
Host smart-4e91af47-08a2-4d49-aa12-575ed682f559
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922374119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.922374119
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2940234913
Short name T228
Test name
Test status
Simulation time 24904961 ps
CPU time 1.08 seconds
Started Jul 05 05:59:39 PM PDT 24
Finished Jul 05 05:59:41 PM PDT 24
Peak memory 209368 kb
Host smart-c2d5a99d-6f8c-4296-9cb1-2a467e120336
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940234913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.2940234913
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1302324063
Short name T114
Test name
Test status
Simulation time 77176881 ps
CPU time 2.59 seconds
Started Jul 05 05:59:34 PM PDT 24
Finished Jul 05 05:59:37 PM PDT 24
Peak memory 217496 kb
Host smart-952570c0-9162-4feb-b756-ecd52ca54024
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302324063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1302324063
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.433292580
Short name T138
Test name
Test status
Simulation time 398288230 ps
CPU time 3.1 seconds
Started Jul 05 05:59:34 PM PDT 24
Finished Jul 05 05:59:38 PM PDT 24
Peak memory 222388 kb
Host smart-ce9c7c00-8594-4e66-b04d-6fc2d26a2161
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433292580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg_
err.433292580
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2589998041
Short name T989
Test name
Test status
Simulation time 33702480 ps
CPU time 1.06 seconds
Started Jul 05 05:59:48 PM PDT 24
Finished Jul 05 05:59:50 PM PDT 24
Peak memory 217600 kb
Host smart-68b7fb53-972d-4070-9beb-5adc7562c79c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589998041 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2589998041
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.4088833935
Short name T901
Test name
Test status
Simulation time 53891139 ps
CPU time 0.88 seconds
Started Jul 05 05:59:47 PM PDT 24
Finished Jul 05 05:59:49 PM PDT 24
Peak memory 209296 kb
Host smart-aad75ef2-d9ab-4a6d-b2dc-c2cf7378e806
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088833935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.4088833935
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3311851485
Short name T950
Test name
Test status
Simulation time 18617821 ps
CPU time 1.01 seconds
Started Jul 05 05:59:50 PM PDT 24
Finished Jul 05 05:59:52 PM PDT 24
Peak memory 209352 kb
Host smart-5c893ffc-b659-4eb2-9e14-4b45d0fb296d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311851485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3311851485
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.751506115
Short name T216
Test name
Test status
Simulation time 30151777 ps
CPU time 1.35 seconds
Started Jul 05 05:59:28 PM PDT 24
Finished Jul 05 05:59:30 PM PDT 24
Peak memory 209480 kb
Host smart-d12478c2-46c9-4157-a8d1-ec52d5aecb05
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751506115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing
.751506115
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2918969684
Short name T122
Test name
Test status
Simulation time 265623581 ps
CPU time 2.07 seconds
Started Jul 05 05:59:25 PM PDT 24
Finished Jul 05 05:59:27 PM PDT 24
Peak memory 209372 kb
Host smart-6c5e047e-bbba-4cc1-be92-075730dc5460
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918969684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.2918969684
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1687079431
Short name T219
Test name
Test status
Simulation time 20667489 ps
CPU time 1.33 seconds
Started Jul 05 05:59:31 PM PDT 24
Finished Jul 05 05:59:33 PM PDT 24
Peak memory 218200 kb
Host smart-1bb07f8c-9b46-40e1-8256-af97287e8f9d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687079431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.1687079431
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.210146067
Short name T968
Test name
Test status
Simulation time 80343483 ps
CPU time 1.33 seconds
Started Jul 05 05:59:33 PM PDT 24
Finished Jul 05 05:59:35 PM PDT 24
Peak memory 218152 kb
Host smart-7057db18-38d3-402c-b812-9479284be9d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210146067 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.210146067
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.643813719
Short name T907
Test name
Test status
Simulation time 40387831 ps
CPU time 0.96 seconds
Started Jul 05 05:59:24 PM PDT 24
Finished Jul 05 05:59:26 PM PDT 24
Peak memory 209304 kb
Host smart-0da4a50f-156d-44ec-91ff-7b3edd850c3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643813719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.643813719
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3423219852
Short name T911
Test name
Test status
Simulation time 322390323 ps
CPU time 2.2 seconds
Started Jul 05 05:59:24 PM PDT 24
Finished Jul 05 05:59:27 PM PDT 24
Peak memory 209128 kb
Host smart-02844cd7-957a-41fa-bb67-510a9b49e124
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423219852 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3423219852
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2902048924
Short name T930
Test name
Test status
Simulation time 779615876 ps
CPU time 9.56 seconds
Started Jul 05 05:59:15 PM PDT 24
Finished Jul 05 05:59:25 PM PDT 24
Peak memory 217160 kb
Host smart-1b68e8c7-b64a-4f86-be9e-c25f89a78b93
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902048924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.2902048924
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2397459946
Short name T937
Test name
Test status
Simulation time 1506638156 ps
CPU time 13.3 seconds
Started Jul 05 05:59:31 PM PDT 24
Finished Jul 05 05:59:46 PM PDT 24
Peak memory 208928 kb
Host smart-2bd61213-e664-453a-b494-5d177563e4b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397459946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.2397459946
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1996164412
Short name T926
Test name
Test status
Simulation time 99499217 ps
CPU time 1.95 seconds
Started Jul 05 05:59:28 PM PDT 24
Finished Jul 05 05:59:31 PM PDT 24
Peak memory 210788 kb
Host smart-fd65f931-2283-42fa-a912-4c6f65e3e809
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996164412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.1996164412
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2623367756
Short name T896
Test name
Test status
Simulation time 571130263 ps
CPU time 1.86 seconds
Started Jul 05 05:59:22 PM PDT 24
Finished Jul 05 05:59:24 PM PDT 24
Peak memory 217668 kb
Host smart-dca01d51-eecb-4029-ac2e-251c4ac4201b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262336
7756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2623367756
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2002637035
Short name T986
Test name
Test status
Simulation time 68429815 ps
CPU time 2.12 seconds
Started Jul 05 05:59:24 PM PDT 24
Finished Jul 05 05:59:26 PM PDT 24
Peak memory 209248 kb
Host smart-aff460ed-55fd-482f-8ea1-0be45951c90c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002637035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.2002637035
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2762894298
Short name T935
Test name
Test status
Simulation time 80494081 ps
CPU time 1.46 seconds
Started Jul 05 05:59:24 PM PDT 24
Finished Jul 05 05:59:26 PM PDT 24
Peak memory 217576 kb
Host smart-90dcd2e9-d53b-49f5-ab24-943ed10ad3b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762894298 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.2762894298
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1779323245
Short name T925
Test name
Test status
Simulation time 25100548 ps
CPU time 1.02 seconds
Started Jul 05 05:59:30 PM PDT 24
Finished Jul 05 05:59:32 PM PDT 24
Peak memory 209372 kb
Host smart-b6deb617-4f23-4c7a-a263-e362e4f2ce4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779323245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.1779323245
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.922731006
Short name T106
Test name
Test status
Simulation time 671543820 ps
CPU time 1.64 seconds
Started Jul 05 05:59:26 PM PDT 24
Finished Jul 05 05:59:29 PM PDT 24
Peak memory 217448 kb
Host smart-ec376787-4638-4815-a595-d68002eadaf1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922731006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.922731006
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2513671338
Short name T878
Test name
Test status
Simulation time 248802662 ps
CPU time 1.51 seconds
Started Jul 05 05:59:29 PM PDT 24
Finished Jul 05 05:59:31 PM PDT 24
Peak memory 209284 kb
Host smart-68e201d1-1921-4a96-b884-58228012563a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513671338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.2513671338
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1949963838
Short name T874
Test name
Test status
Simulation time 97624117 ps
CPU time 1.43 seconds
Started Jul 05 05:59:37 PM PDT 24
Finished Jul 05 05:59:39 PM PDT 24
Peak memory 217256 kb
Host smart-2d2e5ba3-8c7a-4cf5-a87f-2b6776e6c2f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949963838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.1949963838
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3459031343
Short name T909
Test name
Test status
Simulation time 14955605 ps
CPU time 1.11 seconds
Started Jul 05 05:59:28 PM PDT 24
Finished Jul 05 05:59:30 PM PDT 24
Peak memory 211472 kb
Host smart-81fe8098-84e2-49ac-b597-b4a4e4e22263
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459031343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3459031343
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3622039429
Short name T941
Test name
Test status
Simulation time 26150736 ps
CPU time 1.2 seconds
Started Jul 05 05:59:30 PM PDT 24
Finished Jul 05 05:59:32 PM PDT 24
Peak memory 218708 kb
Host smart-288cc37b-7b5e-47d6-80bb-d076f8707a60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622039429 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3622039429
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1202664339
Short name T218
Test name
Test status
Simulation time 31716123 ps
CPU time 0.9 seconds
Started Jul 05 05:59:31 PM PDT 24
Finished Jul 05 05:59:33 PM PDT 24
Peak memory 209272 kb
Host smart-b75a0dfb-7d8d-403e-ba9a-3e1b1d15ad73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202664339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1202664339
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2356254953
Short name T932
Test name
Test status
Simulation time 21903313 ps
CPU time 0.88 seconds
Started Jul 05 05:59:46 PM PDT 24
Finished Jul 05 05:59:48 PM PDT 24
Peak memory 208648 kb
Host smart-05005456-8f21-4a76-932f-3c165d0e3e36
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356254953 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2356254953
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.4176154468
Short name T988
Test name
Test status
Simulation time 2833626319 ps
CPU time 12.97 seconds
Started Jul 05 05:59:30 PM PDT 24
Finished Jul 05 05:59:45 PM PDT 24
Peak memory 209384 kb
Host smart-a460105d-6944-4cf4-9d28-1ede5be4fddd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176154468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.4176154468
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3017672167
Short name T947
Test name
Test status
Simulation time 496559277 ps
CPU time 5.72 seconds
Started Jul 05 05:59:30 PM PDT 24
Finished Jul 05 05:59:37 PM PDT 24
Peak memory 208992 kb
Host smart-0c4de47b-68e8-4da3-b896-49081913dc7a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017672167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3017672167
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2903604701
Short name T906
Test name
Test status
Simulation time 122686033 ps
CPU time 3.57 seconds
Started Jul 05 05:59:23 PM PDT 24
Finished Jul 05 05:59:27 PM PDT 24
Peak memory 210968 kb
Host smart-b21c6e4c-f4be-4759-a68e-f0863794b682
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903604701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.2903604701
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2919175045
Short name T970
Test name
Test status
Simulation time 152158046 ps
CPU time 1.83 seconds
Started Jul 05 05:59:37 PM PDT 24
Finished Jul 05 05:59:39 PM PDT 24
Peak memory 217648 kb
Host smart-57e2b3df-4543-40cb-af65-5e56298674c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291917
5045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2919175045
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4197021962
Short name T902
Test name
Test status
Simulation time 176789671 ps
CPU time 1.72 seconds
Started Jul 05 05:59:26 PM PDT 24
Finished Jul 05 05:59:28 PM PDT 24
Peak memory 209248 kb
Host smart-ebf13b8b-7053-4ede-8d69-2939112437db
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197021962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.4197021962
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3826280839
Short name T891
Test name
Test status
Simulation time 30169594 ps
CPU time 1.5 seconds
Started Jul 05 05:59:26 PM PDT 24
Finished Jul 05 05:59:28 PM PDT 24
Peak memory 209428 kb
Host smart-9afe8136-0f6e-477d-a87f-57d9ebeb6877
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826280839 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3826280839
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.936379229
Short name T881
Test name
Test status
Simulation time 85151675 ps
CPU time 1.08 seconds
Started Jul 05 05:59:41 PM PDT 24
Finished Jul 05 05:59:42 PM PDT 24
Peak memory 209508 kb
Host smart-8371caa7-cfb5-4ea5-b03a-68c58dc109b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936379229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.936379229
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3417024647
Short name T960
Test name
Test status
Simulation time 128002803 ps
CPU time 2.49 seconds
Started Jul 05 05:59:25 PM PDT 24
Finished Jul 05 05:59:28 PM PDT 24
Peak memory 217540 kb
Host smart-8d910956-9eb4-4281-b558-64a74d5df777
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417024647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.3417024647
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2003432283
Short name T141
Test name
Test status
Simulation time 296084354 ps
CPU time 3.17 seconds
Started Jul 05 05:59:32 PM PDT 24
Finished Jul 05 05:59:36 PM PDT 24
Peak memory 213208 kb
Host smart-3b240a3a-eb29-46ab-aae7-e5d7b5650488
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003432283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2003432283
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1488566953
Short name T220
Test name
Test status
Simulation time 102621327 ps
CPU time 1.64 seconds
Started Jul 05 05:59:31 PM PDT 24
Finished Jul 05 05:59:34 PM PDT 24
Peak memory 209364 kb
Host smart-17babac6-2cd8-4dac-9155-07ebe6c7b06f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488566953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.1488566953
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3830359627
Short name T973
Test name
Test status
Simulation time 96610999 ps
CPU time 2.08 seconds
Started Jul 05 05:59:30 PM PDT 24
Finished Jul 05 05:59:34 PM PDT 24
Peak memory 209284 kb
Host smart-df3c2b36-e2d1-4e1b-9bbc-96acda68ccaf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830359627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.3830359627
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1883302942
Short name T882
Test name
Test status
Simulation time 21384848 ps
CPU time 0.9 seconds
Started Jul 05 05:59:29 PM PDT 24
Finished Jul 05 05:59:30 PM PDT 24
Peak memory 209900 kb
Host smart-f3e9248f-b3cf-487e-bb80-3ac00b4fb7dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883302942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1883302942
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1598910668
Short name T963
Test name
Test status
Simulation time 56669486 ps
CPU time 1.26 seconds
Started Jul 05 05:59:34 PM PDT 24
Finished Jul 05 05:59:36 PM PDT 24
Peak memory 217704 kb
Host smart-b2f35de4-4151-47a2-945e-4f938495c8c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598910668 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1598910668
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1642824983
Short name T943
Test name
Test status
Simulation time 46678813 ps
CPU time 0.85 seconds
Started Jul 05 05:59:35 PM PDT 24
Finished Jul 05 05:59:37 PM PDT 24
Peak memory 209352 kb
Host smart-b16d6c80-86da-46e3-93e0-d69352cc6238
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642824983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.1642824983
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.376112088
Short name T965
Test name
Test status
Simulation time 167516100 ps
CPU time 1.65 seconds
Started Jul 05 05:59:46 PM PDT 24
Finished Jul 05 05:59:48 PM PDT 24
Peak memory 209192 kb
Host smart-bc2dd861-e37e-4b89-b23d-6cafa3c58b90
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376112088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_alert_test.376112088
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3714419656
Short name T971
Test name
Test status
Simulation time 2615321304 ps
CPU time 14.85 seconds
Started Jul 05 05:59:33 PM PDT 24
Finished Jul 05 05:59:49 PM PDT 24
Peak memory 217572 kb
Host smart-c0c478fc-48c8-48ac-8757-bea61405cb46
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714419656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3714419656
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.521924849
Short name T948
Test name
Test status
Simulation time 4120102511 ps
CPU time 44.61 seconds
Started Jul 05 05:59:30 PM PDT 24
Finished Jul 05 06:00:15 PM PDT 24
Peak memory 209544 kb
Host smart-b8927955-8c24-4e4e-b29b-d686aeaab0d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521924849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.521924849
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1193763486
Short name T910
Test name
Test status
Simulation time 63380073 ps
CPU time 2.16 seconds
Started Jul 05 05:59:41 PM PDT 24
Finished Jul 05 05:59:43 PM PDT 24
Peak memory 210800 kb
Host smart-916ed85a-3bee-4e32-b94f-308454f61e59
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193763486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.1193763486
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.546387534
Short name T905
Test name
Test status
Simulation time 1834135046 ps
CPU time 3.43 seconds
Started Jul 05 05:59:45 PM PDT 24
Finished Jul 05 05:59:50 PM PDT 24
Peak memory 218760 kb
Host smart-02d62044-daac-47f1-85ee-ef44729f2f09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546387
534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.546387534
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1718864021
Short name T934
Test name
Test status
Simulation time 70899213 ps
CPU time 1.22 seconds
Started Jul 05 05:59:40 PM PDT 24
Finished Jul 05 05:59:42 PM PDT 24
Peak memory 209296 kb
Host smart-a1fd9d6f-21b6-4722-9d55-1d8f49ac34cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718864021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1718864021
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.291542424
Short name T117
Test name
Test status
Simulation time 86509050 ps
CPU time 1.02 seconds
Started Jul 05 05:59:46 PM PDT 24
Finished Jul 05 05:59:48 PM PDT 24
Peak memory 209372 kb
Host smart-a2f743bd-a101-4ee9-89c2-1768b476ee63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291542424 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.291542424
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3754816380
Short name T225
Test name
Test status
Simulation time 565256886 ps
CPU time 1.84 seconds
Started Jul 05 05:59:47 PM PDT 24
Finished Jul 05 05:59:50 PM PDT 24
Peak memory 217492 kb
Host smart-9350d75d-fe85-4dae-bdfd-ae47f22026c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754816380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.3754816380
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2946125219
Short name T918
Test name
Test status
Simulation time 97974431 ps
CPU time 2.04 seconds
Started Jul 05 05:59:29 PM PDT 24
Finished Jul 05 05:59:31 PM PDT 24
Peak memory 217704 kb
Host smart-0e08bed4-d999-460f-93d2-cc3cc2211793
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946125219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2946125219
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.352693298
Short name T921
Test name
Test status
Simulation time 21001285 ps
CPU time 1.14 seconds
Started Jul 05 05:59:44 PM PDT 24
Finished Jul 05 05:59:46 PM PDT 24
Peak memory 217668 kb
Host smart-0bca65c4-c307-4191-b820-de2504c47307
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352693298 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.352693298
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.864971469
Short name T975
Test name
Test status
Simulation time 37223101 ps
CPU time 1.02 seconds
Started Jul 05 05:59:42 PM PDT 24
Finished Jul 05 05:59:44 PM PDT 24
Peak memory 209352 kb
Host smart-3bf837d5-3822-419a-8737-3c6c25ecfd3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864971469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.864971469
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1030508984
Short name T923
Test name
Test status
Simulation time 34754816 ps
CPU time 1.57 seconds
Started Jul 05 05:59:28 PM PDT 24
Finished Jul 05 05:59:30 PM PDT 24
Peak memory 209196 kb
Host smart-c82d603d-2735-4f0a-b1bf-0958284d6583
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030508984 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1030508984
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2771782985
Short name T969
Test name
Test status
Simulation time 665837347 ps
CPU time 5.58 seconds
Started Jul 05 05:59:32 PM PDT 24
Finished Jul 05 05:59:39 PM PDT 24
Peak memory 208988 kb
Host smart-8159f9ad-8035-4556-bb87-68af1e608659
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771782985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2771782985
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3809682119
Short name T876
Test name
Test status
Simulation time 769217680 ps
CPU time 6.46 seconds
Started Jul 05 05:59:43 PM PDT 24
Finished Jul 05 05:59:50 PM PDT 24
Peak memory 217060 kb
Host smart-5fd84e85-8bb7-4f69-9e5b-25bc2e827934
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809682119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3809682119
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4147983963
Short name T917
Test name
Test status
Simulation time 379503255 ps
CPU time 1.66 seconds
Started Jul 05 05:59:28 PM PDT 24
Finished Jul 05 05:59:30 PM PDT 24
Peak memory 210924 kb
Host smart-b0114402-2a62-4fad-8c61-f33412f5e677
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147983963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.4147983963
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1555256108
Short name T949
Test name
Test status
Simulation time 90557867 ps
CPU time 1.87 seconds
Started Jul 05 05:59:23 PM PDT 24
Finished Jul 05 05:59:25 PM PDT 24
Peak memory 222012 kb
Host smart-38380a8b-8282-47d1-81db-57a126a11b81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155525
6108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1555256108
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.51618601
Short name T980
Test name
Test status
Simulation time 76041245 ps
CPU time 1.39 seconds
Started Jul 05 05:59:35 PM PDT 24
Finished Jul 05 05:59:42 PM PDT 24
Peak memory 217404 kb
Host smart-7aa8b770-9ff2-438c-b747-9beabe6623e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51618601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test
+UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 5.lc_ctrl_jtag_csr_rw.51618601
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3550219771
Short name T916
Test name
Test status
Simulation time 53457653 ps
CPU time 1.38 seconds
Started Jul 05 05:59:49 PM PDT 24
Finished Jul 05 05:59:53 PM PDT 24
Peak memory 209392 kb
Host smart-c9f8de34-79fe-4f6a-92b2-a67248d0065a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550219771 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3550219771
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3869930565
Short name T928
Test name
Test status
Simulation time 68297260 ps
CPU time 1.38 seconds
Started Jul 05 05:59:45 PM PDT 24
Finished Jul 05 05:59:47 PM PDT 24
Peak memory 211508 kb
Host smart-42ad88d8-cc52-4588-a59a-3d7c37014926
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869930565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.3869930565
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.477242145
Short name T958
Test name
Test status
Simulation time 222480466 ps
CPU time 3.41 seconds
Started Jul 05 05:59:31 PM PDT 24
Finished Jul 05 05:59:35 PM PDT 24
Peak memory 217504 kb
Host smart-2a3024ea-31b4-43f7-a24d-a7bf3dea3cda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477242145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.477242145
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3205710247
Short name T137
Test name
Test status
Simulation time 443683994 ps
CPU time 1.9 seconds
Started Jul 05 05:59:43 PM PDT 24
Finished Jul 05 05:59:45 PM PDT 24
Peak memory 222104 kb
Host smart-fe45dc2b-cf15-4c24-b45f-9c707d711d5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205710247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.3205710247
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3538761424
Short name T913
Test name
Test status
Simulation time 46253253 ps
CPU time 1.79 seconds
Started Jul 05 05:59:25 PM PDT 24
Finished Jul 05 05:59:27 PM PDT 24
Peak memory 224164 kb
Host smart-e86c6805-fbfc-49d9-847e-005b755e1f8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538761424 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3538761424
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1786391541
Short name T991
Test name
Test status
Simulation time 51881769 ps
CPU time 1.01 seconds
Started Jul 05 06:02:35 PM PDT 24
Finished Jul 05 06:02:36 PM PDT 24
Peak memory 209464 kb
Host smart-f43e637d-93c5-4fa1-856f-5d7a0eb292f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786391541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1786391541
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1991956779
Short name T885
Test name
Test status
Simulation time 165720215 ps
CPU time 1.37 seconds
Started Jul 05 05:59:44 PM PDT 24
Finished Jul 05 05:59:46 PM PDT 24
Peak memory 209204 kb
Host smart-d801218b-3f59-4b8d-83e9-8eb8ce450080
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991956779 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1991956779
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3597535630
Short name T929
Test name
Test status
Simulation time 732311800 ps
CPU time 16.71 seconds
Started Jul 05 05:59:29 PM PDT 24
Finished Jul 05 05:59:46 PM PDT 24
Peak memory 209280 kb
Host smart-1d974ee5-f03e-4302-832a-9594d6b827c0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597535630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3597535630
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1903891340
Short name T946
Test name
Test status
Simulation time 3179842001 ps
CPU time 8.14 seconds
Started Jul 05 05:59:33 PM PDT 24
Finished Jul 05 05:59:42 PM PDT 24
Peak memory 209484 kb
Host smart-e1541240-7101-4511-ba2c-440130c4f2d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903891340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1903891340
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3378548473
Short name T987
Test name
Test status
Simulation time 337738189 ps
CPU time 1.63 seconds
Started Jul 05 05:59:36 PM PDT 24
Finished Jul 05 05:59:38 PM PDT 24
Peak memory 210876 kb
Host smart-7f138696-bef7-49dd-8d2f-9f963ce89052
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378548473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.3378548473
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1327499001
Short name T981
Test name
Test status
Simulation time 291007948 ps
CPU time 2.08 seconds
Started Jul 05 05:59:41 PM PDT 24
Finished Jul 05 05:59:44 PM PDT 24
Peak memory 209216 kb
Host smart-ffba6bd3-7b5d-4bee-81e3-b279cfb2532f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327499001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1327499001
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2565908670
Short name T895
Test name
Test status
Simulation time 85444749 ps
CPU time 1.95 seconds
Started Jul 05 05:59:27 PM PDT 24
Finished Jul 05 05:59:30 PM PDT 24
Peak memory 217636 kb
Host smart-fbe5d541-f3be-43ec-9073-42ef9eb8097f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565908670 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.2565908670
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1475851545
Short name T982
Test name
Test status
Simulation time 48720496 ps
CPU time 1.13 seconds
Started Jul 05 05:59:37 PM PDT 24
Finished Jul 05 05:59:38 PM PDT 24
Peak memory 209304 kb
Host smart-086fb9e4-1f60-40f1-afff-9b3f1015a649
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475851545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.1475851545
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.903082821
Short name T978
Test name
Test status
Simulation time 82025989 ps
CPU time 2.86 seconds
Started Jul 05 05:59:29 PM PDT 24
Finished Jul 05 05:59:32 PM PDT 24
Peak memory 218476 kb
Host smart-93ad4751-8822-4bb4-bc68-bc1cd93df8fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903082821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.903082821
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.785247927
Short name T892
Test name
Test status
Simulation time 124935138 ps
CPU time 1.18 seconds
Started Jul 05 05:59:29 PM PDT 24
Finished Jul 05 05:59:31 PM PDT 24
Peak memory 217708 kb
Host smart-36eb6979-70f0-4488-a879-3e8c428d4463
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785247927 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.785247927
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3449567014
Short name T208
Test name
Test status
Simulation time 87747436 ps
CPU time 1.11 seconds
Started Jul 05 05:59:30 PM PDT 24
Finished Jul 05 05:59:32 PM PDT 24
Peak memory 209124 kb
Host smart-5e001d86-daab-42c0-8c2d-1e03386d5e47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449567014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.3449567014
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3458728995
Short name T886
Test name
Test status
Simulation time 32492889 ps
CPU time 1.44 seconds
Started Jul 05 05:59:30 PM PDT 24
Finished Jul 05 05:59:33 PM PDT 24
Peak memory 209212 kb
Host smart-69286799-f060-42af-ae21-1f5ba032f45a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458728995 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3458728995
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3138977409
Short name T936
Test name
Test status
Simulation time 1981674461 ps
CPU time 11.39 seconds
Started Jul 05 05:59:31 PM PDT 24
Finished Jul 05 05:59:44 PM PDT 24
Peak memory 209036 kb
Host smart-22823043-aa6e-46ca-bdeb-be69b117bd8a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138977409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3138977409
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.109040211
Short name T877
Test name
Test status
Simulation time 2061024138 ps
CPU time 6.2 seconds
Started Jul 05 05:59:41 PM PDT 24
Finished Jul 05 05:59:47 PM PDT 24
Peak memory 209248 kb
Host smart-9ac24428-4e74-4c96-ab34-f5f0500c5e67
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109040211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.109040211
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1860361932
Short name T149
Test name
Test status
Simulation time 110253028 ps
CPU time 1.65 seconds
Started Jul 05 05:59:35 PM PDT 24
Finished Jul 05 05:59:37 PM PDT 24
Peak memory 210876 kb
Host smart-5f569ace-5768-42ea-8461-3e03e106f2ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860361932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1860361932
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3586178096
Short name T904
Test name
Test status
Simulation time 105198481 ps
CPU time 3.86 seconds
Started Jul 05 05:59:38 PM PDT 24
Finished Jul 05 05:59:43 PM PDT 24
Peak memory 218952 kb
Host smart-7f9140da-5511-472d-b2a4-6cfb6f74d772
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358617
8096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3586178096
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1891843624
Short name T972
Test name
Test status
Simulation time 220821137 ps
CPU time 1.97 seconds
Started Jul 05 05:59:40 PM PDT 24
Finished Jul 05 05:59:43 PM PDT 24
Peak memory 209296 kb
Host smart-89e78709-6683-4f58-98f4-05341752482a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891843624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.1891843624
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1064551378
Short name T227
Test name
Test status
Simulation time 37154203 ps
CPU time 1.47 seconds
Started Jul 05 05:59:38 PM PDT 24
Finished Jul 05 05:59:40 PM PDT 24
Peak memory 209376 kb
Host smart-9c63eb01-56a7-40e7-ae56-cdcba63f1192
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064551378 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1064551378
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1221212583
Short name T883
Test name
Test status
Simulation time 25971322 ps
CPU time 1.36 seconds
Started Jul 05 05:59:39 PM PDT 24
Finished Jul 05 05:59:46 PM PDT 24
Peak memory 217600 kb
Host smart-350088f0-d626-48c0-b0ed-aff9d938a11d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221212583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.1221212583
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2758117734
Short name T945
Test name
Test status
Simulation time 119191997 ps
CPU time 1.93 seconds
Started Jul 05 05:59:31 PM PDT 24
Finished Jul 05 05:59:34 PM PDT 24
Peak memory 217624 kb
Host smart-06d30a64-b235-4c88-b241-79e686ee1e56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758117734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.2758117734
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.4159385768
Short name T123
Test name
Test status
Simulation time 29855220 ps
CPU time 1.62 seconds
Started Jul 05 05:59:44 PM PDT 24
Finished Jul 05 05:59:46 PM PDT 24
Peak memory 218684 kb
Host smart-2a5e2117-7dcd-470b-a7ac-56436f9cd98f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159385768 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.4159385768
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.481359561
Short name T908
Test name
Test status
Simulation time 65829187 ps
CPU time 0.91 seconds
Started Jul 05 05:59:36 PM PDT 24
Finished Jul 05 05:59:37 PM PDT 24
Peak memory 209324 kb
Host smart-ddffd91d-d713-4a5a-89cc-a16edf1b4436
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481359561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.481359561
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2012815596
Short name T990
Test name
Test status
Simulation time 111234910 ps
CPU time 2.01 seconds
Started Jul 05 05:59:42 PM PDT 24
Finished Jul 05 05:59:45 PM PDT 24
Peak memory 209280 kb
Host smart-5d360eeb-7235-4218-b698-f95cbbaf3c51
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012815596 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2012815596
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3268573615
Short name T961
Test name
Test status
Simulation time 729299981 ps
CPU time 16.5 seconds
Started Jul 05 05:59:34 PM PDT 24
Finished Jul 05 05:59:51 PM PDT 24
Peak memory 209252 kb
Host smart-f68faa10-9505-44fa-837c-817a7a3eb8c4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268573615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3268573615
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1977691723
Short name T884
Test name
Test status
Simulation time 899026113 ps
CPU time 20.34 seconds
Started Jul 05 05:59:41 PM PDT 24
Finished Jul 05 06:00:03 PM PDT 24
Peak memory 217208 kb
Host smart-c4f1e00b-d3c4-4062-906e-874a50628fc8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977691723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.1977691723
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.4149258925
Short name T967
Test name
Test status
Simulation time 484447341 ps
CPU time 2.04 seconds
Started Jul 05 05:59:30 PM PDT 24
Finished Jul 05 05:59:33 PM PDT 24
Peak memory 210936 kb
Host smart-b60c6b65-5630-4ed0-ab61-6a2e8f7e08f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149258925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.4149258925
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3582250072
Short name T933
Test name
Test status
Simulation time 1035528689 ps
CPU time 6.69 seconds
Started Jul 05 05:59:39 PM PDT 24
Finished Jul 05 05:59:46 PM PDT 24
Peak memory 218384 kb
Host smart-a0103275-514f-4100-afbd-bc51c6802a65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358225
0072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3582250072
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3056655381
Short name T146
Test name
Test status
Simulation time 93792719 ps
CPU time 1.97 seconds
Started Jul 05 05:59:31 PM PDT 24
Finished Jul 05 05:59:34 PM PDT 24
Peak memory 209300 kb
Host smart-aa78fdd0-8258-48cf-af0b-2ed68717c812
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056655381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.3056655381
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.639636516
Short name T224
Test name
Test status
Simulation time 60043649 ps
CPU time 1.15 seconds
Started Jul 05 05:59:34 PM PDT 24
Finished Jul 05 05:59:36 PM PDT 24
Peak memory 209368 kb
Host smart-728de7ea-3864-48b6-9cd9-a007068d1bd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639636516 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.639636516
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.866798857
Short name T894
Test name
Test status
Simulation time 85814930 ps
CPU time 1.32 seconds
Started Jul 05 05:59:48 PM PDT 24
Finished Jul 05 05:59:50 PM PDT 24
Peak memory 209320 kb
Host smart-6fa5d43d-a028-4606-af11-76c1e4705de1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866798857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
same_csr_outstanding.866798857
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.596430707
Short name T119
Test name
Test status
Simulation time 125454796 ps
CPU time 2.99 seconds
Started Jul 05 05:59:46 PM PDT 24
Finished Jul 05 05:59:50 PM PDT 24
Peak memory 217752 kb
Host smart-7fff2b1d-4e96-4a69-9fcd-5737be315968
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596430707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.596430707
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.4033681986
Short name T974
Test name
Test status
Simulation time 59427567 ps
CPU time 1.19 seconds
Started Jul 05 05:59:40 PM PDT 24
Finished Jul 05 05:59:42 PM PDT 24
Peak memory 218660 kb
Host smart-32868158-bf83-4f4f-8f03-186e78e1437f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033681986 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.4033681986
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2607173174
Short name T890
Test name
Test status
Simulation time 14213888 ps
CPU time 1.06 seconds
Started Jul 05 05:59:44 PM PDT 24
Finished Jul 05 05:59:46 PM PDT 24
Peak memory 209352 kb
Host smart-ace8ad87-422b-4c4a-9851-c8300227e279
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607173174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.2607173174
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.203812711
Short name T984
Test name
Test status
Simulation time 111057356 ps
CPU time 1.25 seconds
Started Jul 05 05:59:27 PM PDT 24
Finished Jul 05 05:59:29 PM PDT 24
Peak memory 209424 kb
Host smart-dc25bdeb-f62f-4c19-9fa3-7c99adb0db46
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203812711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.lc_ctrl_jtag_alert_test.203812711
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3206265800
Short name T144
Test name
Test status
Simulation time 1991449527 ps
CPU time 5.85 seconds
Started Jul 05 05:59:56 PM PDT 24
Finished Jul 05 06:00:02 PM PDT 24
Peak memory 209300 kb
Host smart-fd8f1b22-3999-47ac-91fb-35d682973b20
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206265800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3206265800
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1083006117
Short name T912
Test name
Test status
Simulation time 2069270226 ps
CPU time 17.04 seconds
Started Jul 05 05:59:29 PM PDT 24
Finished Jul 05 05:59:47 PM PDT 24
Peak memory 217040 kb
Host smart-a6a08356-6d77-4e57-9b3a-31baaa298a98
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083006117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1083006117
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.7534618
Short name T148
Test name
Test status
Simulation time 93370229 ps
CPU time 1.45 seconds
Started Jul 05 05:59:30 PM PDT 24
Finished Jul 05 05:59:33 PM PDT 24
Peak memory 217520 kb
Host smart-b4cdc65a-0b2a-4171-8c67-c8ce1718feee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7534618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base
_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 9.lc_ctrl_jtag_csr_hw_reset.7534618
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1767419133
Short name T953
Test name
Test status
Simulation time 259049623 ps
CPU time 4.33 seconds
Started Jul 05 05:59:30 PM PDT 24
Finished Jul 05 05:59:35 PM PDT 24
Peak memory 218660 kb
Host smart-5c44e1d1-636a-4310-bd06-6b592603d090
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176741
9133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1767419133
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.98424631
Short name T977
Test name
Test status
Simulation time 874665783 ps
CPU time 4.32 seconds
Started Jul 05 05:59:40 PM PDT 24
Finished Jul 05 05:59:45 PM PDT 24
Peak memory 217452 kb
Host smart-8bf9ab8c-a58b-4d6f-8ca6-14bc62902bbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98424631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test
+UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 9.lc_ctrl_jtag_csr_rw.98424631
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2383055318
Short name T959
Test name
Test status
Simulation time 155906708 ps
CPU time 1.11 seconds
Started Jul 05 05:59:43 PM PDT 24
Finished Jul 05 05:59:44 PM PDT 24
Peak memory 217568 kb
Host smart-34cc91ea-07c9-422c-a57a-8a082c8841aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383055318 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2383055318
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2338179868
Short name T226
Test name
Test status
Simulation time 128299056 ps
CPU time 1.43 seconds
Started Jul 05 05:59:44 PM PDT 24
Finished Jul 05 05:59:46 PM PDT 24
Peak memory 209368 kb
Host smart-0b461e0f-bb79-4c35-90c7-29e76b8aa7a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338179868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2338179868
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3595976565
Short name T976
Test name
Test status
Simulation time 1115759050 ps
CPU time 2.66 seconds
Started Jul 05 05:59:46 PM PDT 24
Finished Jul 05 05:59:50 PM PDT 24
Peak memory 217700 kb
Host smart-9438cc2f-f8fc-4687-823f-460e711e55cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595976565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.3595976565
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1616028862
Short name T139
Test name
Test status
Simulation time 240783226 ps
CPU time 2.09 seconds
Started Jul 05 05:59:37 PM PDT 24
Finished Jul 05 05:59:40 PM PDT 24
Peak memory 222296 kb
Host smart-65005ad8-ccc2-47bd-8503-606e83103664
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616028862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.1616028862
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.2454769669
Short name T344
Test name
Test status
Simulation time 20622411 ps
CPU time 1 seconds
Started Jul 05 05:27:34 PM PDT 24
Finished Jul 05 05:27:38 PM PDT 24
Peak memory 208920 kb
Host smart-38951d2b-c779-49ee-b62c-5b0ac87b4a4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454769669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2454769669
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.928155844
Short name T387
Test name
Test status
Simulation time 747332893 ps
CPU time 5.31 seconds
Started Jul 05 05:27:36 PM PDT 24
Finished Jul 05 05:27:44 PM PDT 24
Peak memory 217120 kb
Host smart-b0b73014-4c3c-43cf-99f8-a1304ac77ffc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928155844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.928155844
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.1522961581
Short name T568
Test name
Test status
Simulation time 5908221802 ps
CPU time 71.76 seconds
Started Jul 05 05:27:34 PM PDT 24
Finished Jul 05 05:28:49 PM PDT 24
Peak memory 225996 kb
Host smart-5ee710a1-7da7-4e8b-9514-1d8d7d2a8990
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522961581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.1522961581
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.4227369558
Short name T497
Test name
Test status
Simulation time 162300581 ps
CPU time 2.84 seconds
Started Jul 05 05:27:35 PM PDT 24
Finished Jul 05 05:27:41 PM PDT 24
Peak memory 217792 kb
Host smart-4b5597f7-22b5-46db-84a5-94d5cce41f45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227369558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.4
227369558
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2556722550
Short name T449
Test name
Test status
Simulation time 661148364 ps
CPU time 6.13 seconds
Started Jul 05 05:27:33 PM PDT 24
Finished Jul 05 05:27:42 PM PDT 24
Peak memory 218156 kb
Host smart-0c9b0120-e17b-4e97-b937-9d9b89d0753b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556722550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.2556722550
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2072648717
Short name T477
Test name
Test status
Simulation time 969569949 ps
CPU time 14.9 seconds
Started Jul 05 05:27:33 PM PDT 24
Finished Jul 05 05:27:51 PM PDT 24
Peak memory 217652 kb
Host smart-04e734c0-8b60-49bd-9cd7-663e2cabb7f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072648717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.2072648717
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3065363719
Short name T72
Test name
Test status
Simulation time 2410648950 ps
CPU time 4.81 seconds
Started Jul 05 05:27:35 PM PDT 24
Finished Jul 05 05:27:42 PM PDT 24
Peak memory 217792 kb
Host smart-d46913ac-cb59-47bb-a211-3d8f98ed61c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065363719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3065363719
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.3397384917
Short name T468
Test name
Test status
Simulation time 1843732204 ps
CPU time 63.75 seconds
Started Jul 05 05:27:35 PM PDT 24
Finished Jul 05 05:28:42 PM PDT 24
Peak memory 270600 kb
Host smart-74ba5cf0-59b8-4dae-a696-ac7f46fb7b63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397384917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.3397384917
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2401478965
Short name T623
Test name
Test status
Simulation time 1195900270 ps
CPU time 11.19 seconds
Started Jul 05 05:27:36 PM PDT 24
Finished Jul 05 05:27:50 PM PDT 24
Peak memory 250920 kb
Host smart-c7a186db-51a2-498f-82ce-6e3bc5390c68
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401478965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.2401478965
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.3336074982
Short name T252
Test name
Test status
Simulation time 250186700 ps
CPU time 2.9 seconds
Started Jul 05 05:27:37 PM PDT 24
Finished Jul 05 05:27:43 PM PDT 24
Peak memory 218224 kb
Host smart-ff58700a-0986-4dc1-a207-bffa49ac9663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336074982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3336074982
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.4122515330
Short name T431
Test name
Test status
Simulation time 1500407006 ps
CPU time 21.83 seconds
Started Jul 05 05:27:32 PM PDT 24
Finished Jul 05 05:27:55 PM PDT 24
Peak memory 217724 kb
Host smart-e30d1785-a4c8-4be4-bf2d-dab9c99eddc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122515330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.4122515330
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.3767343930
Short name T339
Test name
Test status
Simulation time 564132274 ps
CPU time 15.11 seconds
Started Jul 05 05:27:35 PM PDT 24
Finished Jul 05 05:27:52 PM PDT 24
Peak memory 218960 kb
Host smart-63ee4b09-5fe5-47ea-9076-2db22aef5e64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767343930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.3767343930
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3739480679
Short name T380
Test name
Test status
Simulation time 1149620290 ps
CPU time 26.35 seconds
Started Jul 05 05:27:33 PM PDT 24
Finished Jul 05 05:28:02 PM PDT 24
Peak memory 225944 kb
Host smart-99b99b4d-131c-4eea-810d-6fc977ffc29d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739480679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.3739480679
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1572089501
Short name T742
Test name
Test status
Simulation time 495865082 ps
CPU time 10.81 seconds
Started Jul 05 05:27:32 PM PDT 24
Finished Jul 05 05:27:45 PM PDT 24
Peak memory 218240 kb
Host smart-34e86a00-0265-43d7-bca9-a1182987b73d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572089501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1
572089501
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.165904096
Short name T672
Test name
Test status
Simulation time 32694724 ps
CPU time 2.17 seconds
Started Jul 05 05:27:32 PM PDT 24
Finished Jul 05 05:27:36 PM PDT 24
Peak memory 217732 kb
Host smart-f500a92e-2f35-4f01-8ea3-b2332d1cf68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165904096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.165904096
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.3492523768
Short name T773
Test name
Test status
Simulation time 593374806 ps
CPU time 18.91 seconds
Started Jul 05 05:27:34 PM PDT 24
Finished Jul 05 05:27:56 PM PDT 24
Peak memory 250936 kb
Host smart-05b2d32d-3bf0-43da-b192-ac3ea5021a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492523768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3492523768
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2720639757
Short name T381
Test name
Test status
Simulation time 216785586 ps
CPU time 3.7 seconds
Started Jul 05 05:27:33 PM PDT 24
Finished Jul 05 05:27:39 PM PDT 24
Peak memory 226408 kb
Host smart-2ea79357-4116-46a1-8018-efd2b967a961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720639757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2720639757
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.645615850
Short name T761
Test name
Test status
Simulation time 24324911258 ps
CPU time 307.48 seconds
Started Jul 05 05:27:35 PM PDT 24
Finished Jul 05 05:32:45 PM PDT 24
Peak memory 316708 kb
Host smart-40001763-9ecb-43cb-a568-abf8d0d2820c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645615850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.645615850
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3669668123
Short name T321
Test name
Test status
Simulation time 13459753 ps
CPU time 0.91 seconds
Started Jul 05 05:27:32 PM PDT 24
Finished Jul 05 05:27:34 PM PDT 24
Peak memory 211904 kb
Host smart-79d5a40f-780e-42f0-b0cb-b8b4bbfcf327
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669668123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.3669668123
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.759000621
Short name T294
Test name
Test status
Simulation time 131581873 ps
CPU time 0.97 seconds
Started Jul 05 05:27:38 PM PDT 24
Finished Jul 05 05:27:42 PM PDT 24
Peak memory 208992 kb
Host smart-1f2846f3-f228-4b3b-9994-a5e49f9851ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759000621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.759000621
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1019656341
Short name T354
Test name
Test status
Simulation time 15512666 ps
CPU time 0.96 seconds
Started Jul 05 05:27:32 PM PDT 24
Finished Jul 05 05:27:35 PM PDT 24
Peak memory 209004 kb
Host smart-7b52d903-0cf7-484f-8921-fa8d0d2f7a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019656341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.1019656341
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.3797319749
Short name T769
Test name
Test status
Simulation time 900431603 ps
CPU time 10.51 seconds
Started Jul 05 05:27:35 PM PDT 24
Finished Jul 05 05:27:48 PM PDT 24
Peak memory 226044 kb
Host smart-46816060-3b1f-482c-bc32-0546ee81d524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797319749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.3797319749
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.854230601
Short name T639
Test name
Test status
Simulation time 2182320623 ps
CPU time 13.05 seconds
Started Jul 05 05:27:37 PM PDT 24
Finished Jul 05 05:27:54 PM PDT 24
Peak memory 217452 kb
Host smart-5376a42a-2e91-4be9-95da-3f1d2c62de60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854230601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.854230601
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.1068816611
Short name T619
Test name
Test status
Simulation time 3608291982 ps
CPU time 29.47 seconds
Started Jul 05 05:27:35 PM PDT 24
Finished Jul 05 05:28:07 PM PDT 24
Peak memory 218968 kb
Host smart-b78474d3-78f8-40d2-bdab-15d4bad53306
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068816611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.1068816611
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.472000216
Short name T806
Test name
Test status
Simulation time 544085937 ps
CPU time 3.83 seconds
Started Jul 05 05:27:37 PM PDT 24
Finished Jul 05 05:27:45 PM PDT 24
Peak memory 217784 kb
Host smart-f4676ff6-c21d-4f75-9553-0b92be31a879
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472000216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.472000216
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1661603654
Short name T160
Test name
Test status
Simulation time 198406338 ps
CPU time 3.53 seconds
Started Jul 05 05:27:32 PM PDT 24
Finished Jul 05 05:27:38 PM PDT 24
Peak memory 218264 kb
Host smart-fae0cd4d-a476-48b1-bb63-5b51aba7cc63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661603654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.1661603654
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3480539174
Short name T76
Test name
Test status
Simulation time 1842835312 ps
CPU time 14.51 seconds
Started Jul 05 05:27:42 PM PDT 24
Finished Jul 05 05:27:58 PM PDT 24
Peak memory 217712 kb
Host smart-468a3d8b-5b66-4f97-9ad3-73e912fa6b6c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480539174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3480539174
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3804337377
Short name T70
Test name
Test status
Simulation time 2608249624 ps
CPU time 15.52 seconds
Started Jul 05 05:27:39 PM PDT 24
Finished Jul 05 05:27:57 PM PDT 24
Peak memory 217724 kb
Host smart-876dd189-4607-4260-83fd-4f7e5c51e5e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804337377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3804337377
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.4259491701
Short name T630
Test name
Test status
Simulation time 1408271424 ps
CPU time 49.45 seconds
Started Jul 05 05:27:33 PM PDT 24
Finished Jul 05 05:28:25 PM PDT 24
Peak memory 251648 kb
Host smart-a87dc8fa-a9ef-4490-af04-bac04233f369
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259491701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.4259491701
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1004476053
Short name T695
Test name
Test status
Simulation time 302624298 ps
CPU time 10.37 seconds
Started Jul 05 05:27:35 PM PDT 24
Finished Jul 05 05:27:48 PM PDT 24
Peak memory 250968 kb
Host smart-ab2fabd6-1b79-4c06-96e1-b2521e5bd1b7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004476053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1004476053
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.2529795654
Short name T462
Test name
Test status
Simulation time 93225755 ps
CPU time 4.31 seconds
Started Jul 05 05:27:33 PM PDT 24
Finished Jul 05 05:27:41 PM PDT 24
Peak memory 222536 kb
Host smart-0f1acb5c-bc2a-4423-88ac-59d4ead5d661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529795654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.2529795654
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2160401909
Short name T562
Test name
Test status
Simulation time 183111493 ps
CPU time 12.64 seconds
Started Jul 05 05:27:36 PM PDT 24
Finished Jul 05 05:27:51 PM PDT 24
Peak memory 214692 kb
Host smart-3ab346f0-5bce-455e-bdd2-ac8192a694fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160401909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2160401909
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.524729488
Short name T49
Test name
Test status
Simulation time 312205166 ps
CPU time 40.9 seconds
Started Jul 05 05:27:37 PM PDT 24
Finished Jul 05 05:28:22 PM PDT 24
Peak memory 270516 kb
Host smart-0c103854-d9fb-4321-8d18-7974312aaf6e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524729488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.524729488
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.3648422351
Short name T865
Test name
Test status
Simulation time 243675896 ps
CPU time 13.93 seconds
Started Jul 05 05:27:39 PM PDT 24
Finished Jul 05 05:27:56 PM PDT 24
Peak memory 218892 kb
Host smart-3a25fcb7-e07c-4e25-830f-77c42946ee2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648422351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.3648422351
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.2207835010
Short name T405
Test name
Test status
Simulation time 445041208 ps
CPU time 12.02 seconds
Started Jul 05 05:27:44 PM PDT 24
Finished Jul 05 05:27:57 PM PDT 24
Peak memory 225392 kb
Host smart-29615444-8cdd-4d9a-8310-d5eac01d6a54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207835010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.2207835010
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2123944405
Short name T629
Test name
Test status
Simulation time 234794956 ps
CPU time 8.64 seconds
Started Jul 05 05:27:37 PM PDT 24
Finished Jul 05 05:27:49 PM PDT 24
Peak memory 218244 kb
Host smart-4d785c1f-ac88-466c-8744-0aa25a99cad4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123944405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
123944405
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.1145936430
Short name T720
Test name
Test status
Simulation time 1604410008 ps
CPU time 6.04 seconds
Started Jul 05 05:27:35 PM PDT 24
Finished Jul 05 05:27:44 PM PDT 24
Peak memory 218296 kb
Host smart-be6448f0-6d47-4b33-b9b2-997c97d3ceb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145936430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.1145936430
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.2546156711
Short name T853
Test name
Test status
Simulation time 61579043 ps
CPU time 3.34 seconds
Started Jul 05 05:27:34 PM PDT 24
Finished Jul 05 05:27:40 PM PDT 24
Peak memory 217728 kb
Host smart-eb50e614-6ce4-4edf-bd4d-60f5a8fc4e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546156711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2546156711
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.1527565158
Short name T512
Test name
Test status
Simulation time 452629810 ps
CPU time 26.08 seconds
Started Jul 05 05:27:38 PM PDT 24
Finished Jul 05 05:28:08 PM PDT 24
Peak memory 250956 kb
Host smart-cb4406a8-db1f-4cc6-b52a-78475942fab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527565158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1527565158
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1624224558
Short name T737
Test name
Test status
Simulation time 376672036 ps
CPU time 6.7 seconds
Started Jul 05 05:27:32 PM PDT 24
Finished Jul 05 05:27:41 PM PDT 24
Peak memory 247324 kb
Host smart-c590ed27-e48a-43ab-b433-ae3e92c7631c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624224558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1624224558
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.4110520842
Short name T824
Test name
Test status
Simulation time 6387345718 ps
CPU time 218.04 seconds
Started Jul 05 05:27:40 PM PDT 24
Finished Jul 05 05:31:21 PM PDT 24
Peak memory 280276 kb
Host smart-d759f61f-d94a-45fd-b5a3-4939f93e8208
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110520842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.4110520842
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.532493303
Short name T332
Test name
Test status
Simulation time 22301831 ps
CPU time 0.97 seconds
Started Jul 05 05:27:32 PM PDT 24
Finished Jul 05 05:27:34 PM PDT 24
Peak memory 211848 kb
Host smart-a90a2bdc-e7d4-4416-af53-2695f7946a96
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532493303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctr
l_volatile_unlock_smoke.532493303
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.1929972075
Short name T64
Test name
Test status
Simulation time 16543397 ps
CPU time 1.09 seconds
Started Jul 05 05:28:16 PM PDT 24
Finished Jul 05 05:28:19 PM PDT 24
Peak memory 209008 kb
Host smart-6ac1e858-791f-4119-85ff-b2c5d2a476c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929972075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.1929972075
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.2616801177
Short name T282
Test name
Test status
Simulation time 302463728 ps
CPU time 12.18 seconds
Started Jul 05 05:28:15 PM PDT 24
Finished Jul 05 05:28:29 PM PDT 24
Peak memory 218236 kb
Host smart-75d32baa-f2b8-413b-80fa-44df33835b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616801177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.2616801177
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.939723650
Short name T450
Test name
Test status
Simulation time 3947092259 ps
CPU time 23.47 seconds
Started Jul 05 05:28:15 PM PDT 24
Finished Jul 05 05:28:40 PM PDT 24
Peak memory 217740 kb
Host smart-25df6f24-6cfb-4c67-8827-493ab7ea217d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939723650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.939723650
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2448877439
Short name T374
Test name
Test status
Simulation time 3792695431 ps
CPU time 19.07 seconds
Started Jul 05 05:28:15 PM PDT 24
Finished Jul 05 05:28:37 PM PDT 24
Peak memory 218312 kb
Host smart-1ea6e38e-dd5f-4307-95f6-50745cff5964
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448877439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2448877439
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2158659403
Short name T656
Test name
Test status
Simulation time 1167895438 ps
CPU time 5.45 seconds
Started Jul 05 05:28:15 PM PDT 24
Finished Jul 05 05:28:22 PM PDT 24
Peak memory 218252 kb
Host smart-f4be4ec3-e37e-4a83-a009-b46399494b98
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158659403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.2158659403
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3154085594
Short name T353
Test name
Test status
Simulation time 916737443 ps
CPU time 3.08 seconds
Started Jul 05 05:28:13 PM PDT 24
Finished Jul 05 05:28:17 PM PDT 24
Peak memory 217704 kb
Host smart-a1d8cc49-fd0e-4117-abab-0743f528fa89
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154085594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.3154085594
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2389595177
Short name T91
Test name
Test status
Simulation time 1279915943 ps
CPU time 42.52 seconds
Started Jul 05 05:28:16 PM PDT 24
Finished Jul 05 05:29:01 PM PDT 24
Peak memory 267268 kb
Host smart-94f290d8-600a-4a39-b62a-d5d99244745b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389595177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2389595177
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2384293758
Short name T552
Test name
Test status
Simulation time 837219910 ps
CPU time 19.17 seconds
Started Jul 05 05:28:13 PM PDT 24
Finished Jul 05 05:28:33 PM PDT 24
Peak memory 250968 kb
Host smart-0cdf82e5-477e-48c0-a036-3455603b2dd2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384293758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.2384293758
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.4014772946
Short name T245
Test name
Test status
Simulation time 24341612 ps
CPU time 1.95 seconds
Started Jul 05 05:28:14 PM PDT 24
Finished Jul 05 05:28:17 PM PDT 24
Peak memory 218240 kb
Host smart-92b12709-5402-41c2-9cf6-02d22b3a3e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014772946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.4014772946
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.74640901
Short name T813
Test name
Test status
Simulation time 336404780 ps
CPU time 10.55 seconds
Started Jul 05 05:28:15 PM PDT 24
Finished Jul 05 05:28:28 PM PDT 24
Peak memory 226044 kb
Host smart-cbd6da37-f16c-4ecb-9bd3-57b3d3633753
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74640901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.74640901
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1284621471
Short name T173
Test name
Test status
Simulation time 2343403449 ps
CPU time 8.91 seconds
Started Jul 05 05:28:12 PM PDT 24
Finished Jul 05 05:28:22 PM PDT 24
Peak memory 226028 kb
Host smart-0be73f65-3a6f-463c-bc1e-ed6aaa1e39ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284621471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1284621471
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.3045947992
Short name T426
Test name
Test status
Simulation time 249183270 ps
CPU time 10.95 seconds
Started Jul 05 05:28:16 PM PDT 24
Finished Jul 05 05:28:29 PM PDT 24
Peak memory 218144 kb
Host smart-5d935720-aa57-4ae7-b37f-0ab1b8150494
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045947992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
3045947992
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.465728913
Short name T575
Test name
Test status
Simulation time 204938586 ps
CPU time 6.13 seconds
Started Jul 05 05:28:16 PM PDT 24
Finished Jul 05 05:28:24 PM PDT 24
Peak memory 218372 kb
Host smart-099db26e-a932-4fa0-92bc-06eef754fdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465728913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.465728913
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.749535664
Short name T655
Test name
Test status
Simulation time 42588838 ps
CPU time 2.36 seconds
Started Jul 05 05:28:06 PM PDT 24
Finished Jul 05 05:28:09 PM PDT 24
Peak memory 223632 kb
Host smart-7ebef576-0d6c-4b17-ad70-229c710a9d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749535664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.749535664
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.1551130206
Short name T466
Test name
Test status
Simulation time 1442407365 ps
CPU time 24.15 seconds
Started Jul 05 05:28:11 PM PDT 24
Finished Jul 05 05:28:36 PM PDT 24
Peak memory 250988 kb
Host smart-ecfbfff8-d6d8-48f0-b9d7-108dfea6fefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551130206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1551130206
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.1310447632
Short name T595
Test name
Test status
Simulation time 343970444 ps
CPU time 9.45 seconds
Started Jul 05 05:28:09 PM PDT 24
Finished Jul 05 05:28:20 PM PDT 24
Peak memory 250932 kb
Host smart-60a55308-3cc3-407f-a952-9d19a0e6e141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310447632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.1310447632
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.3795555538
Short name T176
Test name
Test status
Simulation time 5081278494 ps
CPU time 60.19 seconds
Started Jul 05 05:28:16 PM PDT 24
Finished Jul 05 05:29:18 PM PDT 24
Peak memory 263632 kb
Host smart-b7e049b6-88ae-4803-834c-46b455adceb2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795555538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.3795555538
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3698044347
Short name T237
Test name
Test status
Simulation time 40805149 ps
CPU time 0.9 seconds
Started Jul 05 05:28:14 PM PDT 24
Finished Jul 05 05:28:17 PM PDT 24
Peak memory 208612 kb
Host smart-9d2eafef-8d58-4907-98bc-12e1bd451244
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698044347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3698044347
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.3959162554
Short name T683
Test name
Test status
Simulation time 20747140 ps
CPU time 1.23 seconds
Started Jul 05 05:28:24 PM PDT 24
Finished Jul 05 05:28:26 PM PDT 24
Peak memory 209120 kb
Host smart-e167fbf0-ee3a-446c-801f-436ee79f8544
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959162554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3959162554
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.1468420917
Short name T287
Test name
Test status
Simulation time 179492764 ps
CPU time 9.18 seconds
Started Jul 05 05:28:14 PM PDT 24
Finished Jul 05 05:28:24 PM PDT 24
Peak memory 218212 kb
Host smart-0dfe5797-38c6-48a6-97a8-9a03c33057bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468420917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.1468420917
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.3559656908
Short name T490
Test name
Test status
Simulation time 485068435 ps
CPU time 3.11 seconds
Started Jul 05 05:28:25 PM PDT 24
Finished Jul 05 05:28:29 PM PDT 24
Peak memory 217188 kb
Host smart-68c2258b-eb5b-4183-858c-2b39b760f9ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559656908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.3559656908
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.980846900
Short name T789
Test name
Test status
Simulation time 4631442209 ps
CPU time 34.44 seconds
Started Jul 05 05:28:23 PM PDT 24
Finished Jul 05 05:28:59 PM PDT 24
Peak memory 226060 kb
Host smart-7308d928-bde1-45aa-b965-1da831b93a5c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980846900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_er
rors.980846900
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2895427820
Short name T273
Test name
Test status
Simulation time 186127502 ps
CPU time 4.4 seconds
Started Jul 05 05:28:24 PM PDT 24
Finished Jul 05 05:28:30 PM PDT 24
Peak memory 218240 kb
Host smart-ee3ae382-d30c-40ca-9f0c-e340456ef348
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895427820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.2895427820
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.4087592707
Short name T348
Test name
Test status
Simulation time 13210858175 ps
CPU time 37.87 seconds
Started Jul 05 05:28:15 PM PDT 24
Finished Jul 05 05:28:55 PM PDT 24
Peak memory 275504 kb
Host smart-b1b90a9a-7c4f-4198-9a9c-8be21d1734cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087592707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.4087592707
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1014987979
Short name T763
Test name
Test status
Simulation time 557154069 ps
CPU time 13.95 seconds
Started Jul 05 05:28:17 PM PDT 24
Finished Jul 05 05:28:32 PM PDT 24
Peak memory 250896 kb
Host smart-75e01e88-bc74-424a-9dc7-10ae39b157e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014987979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.1014987979
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.3485967509
Short name T817
Test name
Test status
Simulation time 107734237 ps
CPU time 2.36 seconds
Started Jul 05 05:28:14 PM PDT 24
Finished Jul 05 05:28:17 PM PDT 24
Peak memory 222304 kb
Host smart-a94573d2-04e5-4405-b8b2-792c3784efe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485967509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.3485967509
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1181292801
Short name T255
Test name
Test status
Simulation time 586829775 ps
CPU time 13.56 seconds
Started Jul 05 05:28:23 PM PDT 24
Finished Jul 05 05:28:37 PM PDT 24
Peak memory 226072 kb
Host smart-e168eda9-8e87-47b9-9311-55d2dc66fc07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181292801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1181292801
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1789611886
Short name T275
Test name
Test status
Simulation time 471608326 ps
CPU time 13.03 seconds
Started Jul 05 05:28:25 PM PDT 24
Finished Jul 05 05:28:39 PM PDT 24
Peak memory 218268 kb
Host smart-5d4cbe05-24a1-4f82-95bd-ce644f5dce62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789611886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
1789611886
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1782665840
Short name T819
Test name
Test status
Simulation time 1176392147 ps
CPU time 9.21 seconds
Started Jul 05 05:28:16 PM PDT 24
Finished Jul 05 05:28:27 PM PDT 24
Peak memory 225172 kb
Host smart-1511e682-62ab-4850-90b3-bb9dfadb286e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782665840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1782665840
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.4040252139
Short name T832
Test name
Test status
Simulation time 14487574 ps
CPU time 1.18 seconds
Started Jul 05 05:28:17 PM PDT 24
Finished Jul 05 05:28:20 PM PDT 24
Peak memory 212060 kb
Host smart-18fa7a39-eae4-4f02-af9c-fb457e43b842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040252139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.4040252139
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1813744374
Short name T95
Test name
Test status
Simulation time 1327465458 ps
CPU time 35.8 seconds
Started Jul 05 05:28:14 PM PDT 24
Finished Jul 05 05:28:51 PM PDT 24
Peak memory 250952 kb
Host smart-b900d6bb-b8eb-4c60-83df-0beedd7dfd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813744374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1813744374
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.3024479812
Short name T585
Test name
Test status
Simulation time 1667270815 ps
CPU time 7.98 seconds
Started Jul 05 05:28:14 PM PDT 24
Finished Jul 05 05:28:24 PM PDT 24
Peak memory 247000 kb
Host smart-4273693a-37f4-4a5a-b795-f9beef56a8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024479812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3024479812
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.3320542876
Short name T514
Test name
Test status
Simulation time 7976628873 ps
CPU time 143.75 seconds
Started Jul 05 05:28:23 PM PDT 24
Finished Jul 05 05:30:48 PM PDT 24
Peak memory 270692 kb
Host smart-2e603d13-eb3e-46b5-a911-34d340780fd5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320542876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.3320542876
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.652418682
Short name T281
Test name
Test status
Simulation time 17462435 ps
CPU time 0.91 seconds
Started Jul 05 05:28:15 PM PDT 24
Finished Jul 05 05:28:18 PM PDT 24
Peak memory 211912 kb
Host smart-b3135415-33c0-4461-aafd-f10eeafe13ec
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652418682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct
rl_volatile_unlock_smoke.652418682
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3199710575
Short name T620
Test name
Test status
Simulation time 141500938 ps
CPU time 1.02 seconds
Started Jul 05 05:28:21 PM PDT 24
Finished Jul 05 05:28:23 PM PDT 24
Peak memory 209052 kb
Host smart-988776f3-cab0-470d-b0d0-331ab59294d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199710575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3199710575
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.170002024
Short name T421
Test name
Test status
Simulation time 626681546 ps
CPU time 14.71 seconds
Started Jul 05 05:28:21 PM PDT 24
Finished Jul 05 05:28:36 PM PDT 24
Peak memory 218232 kb
Host smart-b5b1870c-ca0c-421c-bbd6-ee46c4ea3e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170002024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.170002024
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.2249534655
Short name T101
Test name
Test status
Simulation time 195328392 ps
CPU time 5.87 seconds
Started Jul 05 05:28:24 PM PDT 24
Finished Jul 05 05:28:31 PM PDT 24
Peak memory 217164 kb
Host smart-2ec8411b-dd42-4cad-8183-576831aaa2d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249534655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.2249534655
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.880655315
Short name T452
Test name
Test status
Simulation time 4885844431 ps
CPU time 39.55 seconds
Started Jul 05 05:28:23 PM PDT 24
Finished Jul 05 05:29:04 PM PDT 24
Peak memory 218964 kb
Host smart-b134dfea-94c8-4795-be36-14e688be5d3b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880655315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_er
rors.880655315
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.393521289
Short name T157
Test name
Test status
Simulation time 564787405 ps
CPU time 5.01 seconds
Started Jul 05 05:28:19 PM PDT 24
Finished Jul 05 05:28:25 PM PDT 24
Peak memory 218248 kb
Host smart-29eee8d8-d01f-4ca8-8387-610d148fa36e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393521289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag
_prog_failure.393521289
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2071683682
Short name T257
Test name
Test status
Simulation time 370733348 ps
CPU time 6.46 seconds
Started Jul 05 05:28:23 PM PDT 24
Finished Jul 05 05:28:30 PM PDT 24
Peak memory 217748 kb
Host smart-101f64f0-b3ba-4bfc-b29f-870c0ff56f3d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071683682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2071683682
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3423569118
Short name T548
Test name
Test status
Simulation time 5121185012 ps
CPU time 55.04 seconds
Started Jul 05 05:28:24 PM PDT 24
Finished Jul 05 05:29:20 PM PDT 24
Peak memory 276180 kb
Host smart-90e33635-0844-4732-87d5-eac9f4f0fa51
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423569118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3423569118
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2772099810
Short name T617
Test name
Test status
Simulation time 1031821013 ps
CPU time 18.34 seconds
Started Jul 05 05:28:26 PM PDT 24
Finished Jul 05 05:28:45 PM PDT 24
Peak memory 250276 kb
Host smart-5f91021a-94dc-4c6a-a241-e4e8d8535826
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772099810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.2772099810
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.4292242406
Short name T677
Test name
Test status
Simulation time 26658893 ps
CPU time 1.78 seconds
Started Jul 05 05:28:21 PM PDT 24
Finished Jul 05 05:28:24 PM PDT 24
Peak memory 218168 kb
Host smart-d1b4d7b4-f523-4229-84d0-abedd5603bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292242406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.4292242406
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.1470499221
Short name T20
Test name
Test status
Simulation time 315655066 ps
CPU time 13.77 seconds
Started Jul 05 05:28:23 PM PDT 24
Finished Jul 05 05:28:38 PM PDT 24
Peak memory 218964 kb
Host smart-197d3309-3b6d-476e-a343-adbdd60e95db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470499221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1470499221
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2678425013
Short name T284
Test name
Test status
Simulation time 1522873037 ps
CPU time 11.46 seconds
Started Jul 05 05:28:23 PM PDT 24
Finished Jul 05 05:28:36 PM PDT 24
Peak memory 226048 kb
Host smart-64cc8440-d7c0-486e-81e2-830b236e287a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678425013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.2678425013
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.2460915510
Short name T697
Test name
Test status
Simulation time 1043686473 ps
CPU time 10.67 seconds
Started Jul 05 05:28:21 PM PDT 24
Finished Jul 05 05:28:32 PM PDT 24
Peak memory 226044 kb
Host smart-fce4293e-8fa4-4036-92a8-cb431d97e53b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460915510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
2460915510
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.93231323
Short name T624
Test name
Test status
Simulation time 2055458116 ps
CPU time 14.17 seconds
Started Jul 05 05:28:24 PM PDT 24
Finished Jul 05 05:28:39 PM PDT 24
Peak memory 218284 kb
Host smart-0a30c2a4-954b-46de-9b99-3f3893eb8e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93231323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.93231323
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.828221680
Short name T398
Test name
Test status
Simulation time 360911599 ps
CPU time 2.81 seconds
Started Jul 05 05:28:22 PM PDT 24
Finished Jul 05 05:28:26 PM PDT 24
Peak memory 217804 kb
Host smart-0c882b02-d72b-4b37-80d1-14bfc817446f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828221680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.828221680
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.711965722
Short name T605
Test name
Test status
Simulation time 1146389789 ps
CPU time 22.58 seconds
Started Jul 05 05:28:22 PM PDT 24
Finished Jul 05 05:28:45 PM PDT 24
Peak memory 250876 kb
Host smart-74be5fbd-1abe-4f6e-9aff-cbba7826d00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711965722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.711965722
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.1820980350
Short name T296
Test name
Test status
Simulation time 1039852070 ps
CPU time 3.78 seconds
Started Jul 05 05:28:22 PM PDT 24
Finished Jul 05 05:28:26 PM PDT 24
Peak memory 218220 kb
Host smart-3ffab840-bfe0-4330-bb8d-a0673f492b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820980350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1820980350
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2335816773
Short name T58
Test name
Test status
Simulation time 3353924940 ps
CPU time 137.82 seconds
Started Jul 05 05:28:26 PM PDT 24
Finished Jul 05 05:30:45 PM PDT 24
Peak memory 278844 kb
Host smart-9fb7d25a-4559-4297-bd56-c1677fb4ede7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335816773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2335816773
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3661172497
Short name T276
Test name
Test status
Simulation time 19776504 ps
CPU time 0.95 seconds
Started Jul 05 05:28:22 PM PDT 24
Finished Jul 05 05:28:24 PM PDT 24
Peak memory 211908 kb
Host smart-e9d142fa-3215-48d4-b35f-36555174831f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661172497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3661172497
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.2091992955
Short name T523
Test name
Test status
Simulation time 27394199 ps
CPU time 1.02 seconds
Started Jul 05 05:28:33 PM PDT 24
Finished Jul 05 05:28:35 PM PDT 24
Peak memory 208876 kb
Host smart-0e810893-3605-48a8-8981-dc00c4f9d19c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091992955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2091992955
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1704172577
Short name T555
Test name
Test status
Simulation time 423436882 ps
CPU time 19.32 seconds
Started Jul 05 05:28:30 PM PDT 24
Finished Jul 05 05:28:50 PM PDT 24
Peak memory 218388 kb
Host smart-e39e2800-0c1e-4c25-8b07-036e5c55d006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704172577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1704172577
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.1663054534
Short name T396
Test name
Test status
Simulation time 893207467 ps
CPU time 5.37 seconds
Started Jul 05 05:28:32 PM PDT 24
Finished Jul 05 05:28:38 PM PDT 24
Peak memory 217360 kb
Host smart-e10e3064-6d2d-48b3-be57-88029133b972
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663054534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.1663054534
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.580145992
Short name T665
Test name
Test status
Simulation time 3555966994 ps
CPU time 45.33 seconds
Started Jul 05 05:28:30 PM PDT 24
Finished Jul 05 05:29:17 PM PDT 24
Peak memory 218952 kb
Host smart-6c5c8b38-127e-44ca-9f92-e83aaaf287b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580145992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_er
rors.580145992
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.3338148621
Short name T335
Test name
Test status
Simulation time 3298753285 ps
CPU time 21.93 seconds
Started Jul 05 05:28:31 PM PDT 24
Finished Jul 05 05:28:54 PM PDT 24
Peak memory 218256 kb
Host smart-fb9d7cff-40c4-4bc5-ae9e-e21d2d061117
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338148621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.3338148621
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.3426867233
Short name T784
Test name
Test status
Simulation time 382427346 ps
CPU time 7.01 seconds
Started Jul 05 05:28:31 PM PDT 24
Finished Jul 05 05:28:39 PM PDT 24
Peak memory 217728 kb
Host smart-4f18ccb2-20b0-4645-9cae-bd56be0c3594
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426867233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.3426867233
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.1199554347
Short name T388
Test name
Test status
Simulation time 6068369758 ps
CPU time 41.81 seconds
Started Jul 05 05:28:29 PM PDT 24
Finished Jul 05 05:29:12 PM PDT 24
Peak memory 250976 kb
Host smart-ca37f3d6-b831-44e8-8f0d-35ff67afcefb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199554347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.1199554347
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.436025890
Short name T362
Test name
Test status
Simulation time 501656096 ps
CPU time 15.59 seconds
Started Jul 05 05:28:33 PM PDT 24
Finished Jul 05 05:28:50 PM PDT 24
Peak memory 223060 kb
Host smart-f92fa09e-28ee-426c-af3c-8f953d1ab132
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436025890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_
jtag_state_post_trans.436025890
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.302839860
Short name T829
Test name
Test status
Simulation time 126896585 ps
CPU time 2.73 seconds
Started Jul 05 05:28:32 PM PDT 24
Finished Jul 05 05:28:36 PM PDT 24
Peak memory 218168 kb
Host smart-ccf17ada-b2b5-4bee-8190-1453bceaf4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302839860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.302839860
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3773878431
Short name T648
Test name
Test status
Simulation time 318761036 ps
CPU time 13.42 seconds
Started Jul 05 05:28:32 PM PDT 24
Finished Jul 05 05:28:47 PM PDT 24
Peak memory 218876 kb
Host smart-4df8735b-ac70-44ed-90f6-330b565cec85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773878431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3773878431
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2946803516
Short name T566
Test name
Test status
Simulation time 1692569456 ps
CPU time 16.24 seconds
Started Jul 05 05:28:29 PM PDT 24
Finished Jul 05 05:28:47 PM PDT 24
Peak memory 226048 kb
Host smart-da3ed718-acb8-42b1-9164-e988a0143c20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946803516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.2946803516
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.738091726
Short name T55
Test name
Test status
Simulation time 1478175298 ps
CPU time 6.23 seconds
Started Jul 05 05:28:30 PM PDT 24
Finished Jul 05 05:28:38 PM PDT 24
Peak memory 218240 kb
Host smart-f1fde673-37a8-47ec-8aea-b68cb1374979
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738091726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.738091726
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.3214827217
Short name T531
Test name
Test status
Simulation time 27290207 ps
CPU time 1.86 seconds
Started Jul 05 05:28:33 PM PDT 24
Finished Jul 05 05:28:36 PM PDT 24
Peak memory 213880 kb
Host smart-bfd5cd68-e315-43e5-94d1-ceaa130b921a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214827217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.3214827217
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.894952369
Short name T645
Test name
Test status
Simulation time 454417754 ps
CPU time 30.55 seconds
Started Jul 05 05:28:32 PM PDT 24
Finished Jul 05 05:29:03 PM PDT 24
Peak memory 250988 kb
Host smart-cdfc8c61-347d-4709-9d4d-30a40f93e12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894952369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.894952369
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.3161314030
Short name T698
Test name
Test status
Simulation time 273586269 ps
CPU time 3.91 seconds
Started Jul 05 05:28:30 PM PDT 24
Finished Jul 05 05:28:35 PM PDT 24
Peak memory 226388 kb
Host smart-c9c1a503-4178-4ec0-aeb4-3f21ee61cd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161314030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.3161314030
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.2999151864
Short name T87
Test name
Test status
Simulation time 3745224997 ps
CPU time 82 seconds
Started Jul 05 05:28:30 PM PDT 24
Finished Jul 05 05:29:53 PM PDT 24
Peak memory 251052 kb
Host smart-cc271179-187a-4a39-9970-f27f291f0adb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999151864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.2999151864
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.2393869262
Short name T172
Test name
Test status
Simulation time 52687052324 ps
CPU time 937.97 seconds
Started Jul 05 05:28:31 PM PDT 24
Finished Jul 05 05:44:10 PM PDT 24
Peak memory 282024 kb
Host smart-c2dacaed-1a92-438c-825e-ba7abfe4b207
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2393869262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.2393869262
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1284647302
Short name T811
Test name
Test status
Simulation time 21048460 ps
CPU time 0.96 seconds
Started Jul 05 05:28:29 PM PDT 24
Finished Jul 05 05:28:30 PM PDT 24
Peak memory 211856 kb
Host smart-0f281d74-95c1-474b-b6c9-dd3a6163e025
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284647302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.1284647302
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.635815116
Short name T802
Test name
Test status
Simulation time 83967836 ps
CPU time 1.06 seconds
Started Jul 05 05:28:40 PM PDT 24
Finished Jul 05 05:28:42 PM PDT 24
Peak memory 208972 kb
Host smart-36b0c977-551f-456b-87cd-fb9c2c098236
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635815116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.635815116
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.453981072
Short name T474
Test name
Test status
Simulation time 936648471 ps
CPU time 9.78 seconds
Started Jul 05 05:28:29 PM PDT 24
Finished Jul 05 05:28:40 PM PDT 24
Peak memory 218136 kb
Host smart-090726c8-678c-4e4a-bd1e-7b92ac8a8f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453981072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.453981072
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.1380774083
Short name T628
Test name
Test status
Simulation time 784079599 ps
CPU time 6.23 seconds
Started Jul 05 05:28:33 PM PDT 24
Finished Jul 05 05:28:40 PM PDT 24
Peak memory 217392 kb
Host smart-92fa8fac-43b3-42fe-b7d8-a76ef8547099
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380774083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.1380774083
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.274693207
Short name T587
Test name
Test status
Simulation time 5938832112 ps
CPU time 82.43 seconds
Started Jul 05 05:28:31 PM PDT 24
Finished Jul 05 05:29:54 PM PDT 24
Peak memory 218848 kb
Host smart-191d4dce-336d-48b5-9f84-9f69cc6ff35d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274693207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_er
rors.274693207
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.3980291712
Short name T759
Test name
Test status
Simulation time 316062862 ps
CPU time 6.59 seconds
Started Jul 05 05:28:31 PM PDT 24
Finished Jul 05 05:28:38 PM PDT 24
Peak memory 223292 kb
Host smart-85dffc18-b923-42e4-b9a9-4c2015202fe8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980291712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.3980291712
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.3815743839
Short name T336
Test name
Test status
Simulation time 1040024573 ps
CPU time 3.38 seconds
Started Jul 05 05:28:32 PM PDT 24
Finished Jul 05 05:28:36 PM PDT 24
Peak memory 217652 kb
Host smart-790c948d-d2ee-48fa-b84a-63708f2a07fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815743839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.3815743839
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.4107548908
Short name T291
Test name
Test status
Simulation time 1766253432 ps
CPU time 40.19 seconds
Started Jul 05 05:28:32 PM PDT 24
Finished Jul 05 05:29:13 PM PDT 24
Peak memory 250972 kb
Host smart-147e62b1-cf0c-4a1c-af8d-87194aac791f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107548908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.4107548908
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.4230063795
Short name T609
Test name
Test status
Simulation time 4079108501 ps
CPU time 14.91 seconds
Started Jul 05 05:28:30 PM PDT 24
Finished Jul 05 05:28:46 PM PDT 24
Peak memory 226508 kb
Host smart-31125632-4403-409e-837e-03a7299c9dfb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230063795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.4230063795
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2689946334
Short name T347
Test name
Test status
Simulation time 57703719 ps
CPU time 3.08 seconds
Started Jul 05 05:28:32 PM PDT 24
Finished Jul 05 05:28:36 PM PDT 24
Peak memory 218232 kb
Host smart-22bbdefd-f788-44fc-b78f-db2684b2c213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689946334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2689946334
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.4071940367
Short name T676
Test name
Test status
Simulation time 465354034 ps
CPU time 18.4 seconds
Started Jul 05 05:28:31 PM PDT 24
Finished Jul 05 05:28:50 PM PDT 24
Peak memory 218892 kb
Host smart-01ec94d8-6ac2-432f-b988-ab9be6e9fbbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071940367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.4071940367
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.3326853284
Short name T692
Test name
Test status
Simulation time 945776535 ps
CPU time 10.69 seconds
Started Jul 05 05:28:34 PM PDT 24
Finished Jul 05 05:28:46 PM PDT 24
Peak memory 218240 kb
Host smart-3786682e-c6e8-4151-a611-5809e626060b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326853284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.3326853284
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.165642464
Short name T420
Test name
Test status
Simulation time 264199613 ps
CPU time 7.06 seconds
Started Jul 05 05:28:33 PM PDT 24
Finished Jul 05 05:28:41 PM PDT 24
Peak memory 218148 kb
Host smart-19154ce8-fc16-4b19-9302-bd0ba4d64687
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165642464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.165642464
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.509058098
Short name T51
Test name
Test status
Simulation time 1307137335 ps
CPU time 7.75 seconds
Started Jul 05 05:28:30 PM PDT 24
Finished Jul 05 05:28:38 PM PDT 24
Peak memory 224976 kb
Host smart-48d9e1b8-ab67-4bef-95e5-f70fbd1467f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509058098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.509058098
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.2433551037
Short name T277
Test name
Test status
Simulation time 78843885 ps
CPU time 1.77 seconds
Started Jul 05 05:28:31 PM PDT 24
Finished Jul 05 05:28:34 PM PDT 24
Peak memory 217720 kb
Host smart-10f5026e-cca3-4754-a12d-ad794f6db478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433551037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2433551037
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2143677003
Short name T599
Test name
Test status
Simulation time 515108912 ps
CPU time 31.7 seconds
Started Jul 05 05:28:31 PM PDT 24
Finished Jul 05 05:29:04 PM PDT 24
Peak memory 251048 kb
Host smart-4641c6db-2bfd-43b9-8aa4-24050bb81ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143677003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2143677003
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.3534849046
Short name T415
Test name
Test status
Simulation time 90947278 ps
CPU time 10.4 seconds
Started Jul 05 05:28:31 PM PDT 24
Finished Jul 05 05:28:42 PM PDT 24
Peak memory 250976 kb
Host smart-f117491d-9a4c-4b04-9ea2-320d711f6e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534849046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3534849046
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3194245086
Short name T459
Test name
Test status
Simulation time 13076660 ps
CPU time 0.89 seconds
Started Jul 05 05:28:30 PM PDT 24
Finished Jul 05 05:28:32 PM PDT 24
Peak memory 211912 kb
Host smart-6d748ab6-3a65-4f7e-b1eb-4cfc524d4578
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194245086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3194245086
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.1198377928
Short name T641
Test name
Test status
Simulation time 161354922 ps
CPU time 0.91 seconds
Started Jul 05 05:28:45 PM PDT 24
Finished Jul 05 05:28:46 PM PDT 24
Peak memory 208996 kb
Host smart-d07bb821-bd77-42f6-a199-67de1ec0694c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198377928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.1198377928
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.2456504666
Short name T711
Test name
Test status
Simulation time 859841160 ps
CPU time 11.77 seconds
Started Jul 05 05:28:39 PM PDT 24
Finished Jul 05 05:28:52 PM PDT 24
Peak memory 225988 kb
Host smart-0e639776-4b72-43fd-9ada-26ed209bc562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456504666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2456504666
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2484085400
Short name T564
Test name
Test status
Simulation time 159262079 ps
CPU time 4.05 seconds
Started Jul 05 05:28:39 PM PDT 24
Finished Jul 05 05:28:44 PM PDT 24
Peak memory 217132 kb
Host smart-b09ca586-3433-4bc1-b945-50475d02861b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484085400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2484085400
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1066623805
Short name T652
Test name
Test status
Simulation time 5797867356 ps
CPU time 77.97 seconds
Started Jul 05 05:28:39 PM PDT 24
Finished Jul 05 05:29:57 PM PDT 24
Peak memory 220008 kb
Host smart-ef2c5145-33c9-4396-a80c-581b77e575a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066623805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1066623805
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.854386602
Short name T862
Test name
Test status
Simulation time 532111724 ps
CPU time 4.86 seconds
Started Jul 05 05:28:39 PM PDT 24
Finished Jul 05 05:28:44 PM PDT 24
Peak memory 218356 kb
Host smart-5efb45bc-62ee-440c-95bf-b97f1803e2ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854386602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.854386602
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1798778043
Short name T526
Test name
Test status
Simulation time 821555597 ps
CPU time 2.63 seconds
Started Jul 05 05:28:41 PM PDT 24
Finished Jul 05 05:28:44 PM PDT 24
Peak memory 217724 kb
Host smart-04143302-2af2-4221-bb17-89c5e8193ed9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798778043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1798778043
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1662799805
Short name T622
Test name
Test status
Simulation time 5776889987 ps
CPU time 54.45 seconds
Started Jul 05 05:28:43 PM PDT 24
Finished Jul 05 05:29:39 PM PDT 24
Peak memory 269716 kb
Host smart-3b44fc44-4836-4f9a-9c42-7bc999bb39de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662799805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.1662799805
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.8337172
Short name T168
Test name
Test status
Simulation time 325022775 ps
CPU time 6.64 seconds
Started Jul 05 05:28:38 PM PDT 24
Finished Jul 05 05:28:46 PM PDT 24
Peak memory 226420 kb
Host smart-f20fffd5-5256-43b3-99dd-d835cf561e26
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8337172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_st
ate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_post_trans.8337172
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.435143610
Short name T4
Test name
Test status
Simulation time 46343448 ps
CPU time 2.74 seconds
Started Jul 05 05:28:43 PM PDT 24
Finished Jul 05 05:28:46 PM PDT 24
Peak memory 218244 kb
Host smart-e5a0cd01-2876-46a7-955d-cd3db51e9b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435143610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.435143610
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.3194099385
Short name T98
Test name
Test status
Simulation time 847635948 ps
CPU time 13.89 seconds
Started Jul 05 05:28:40 PM PDT 24
Finished Jul 05 05:28:55 PM PDT 24
Peak memory 218924 kb
Host smart-908b359e-e37e-4d46-ab03-b7c5969c0933
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194099385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.3194099385
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.4196271293
Short name T682
Test name
Test status
Simulation time 361427041 ps
CPU time 12 seconds
Started Jul 05 05:28:40 PM PDT 24
Finished Jul 05 05:28:53 PM PDT 24
Peak memory 225992 kb
Host smart-90722c5a-37f4-482b-b07e-8eac3b860579
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196271293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.4196271293
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1796539314
Short name T854
Test name
Test status
Simulation time 1862230270 ps
CPU time 9.01 seconds
Started Jul 05 05:28:42 PM PDT 24
Finished Jul 05 05:28:52 PM PDT 24
Peak memory 218224 kb
Host smart-4f006b4a-218a-48b3-a4ba-369595e93710
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796539314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1796539314
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.1917291570
Short name T868
Test name
Test status
Simulation time 235069419 ps
CPU time 7.71 seconds
Started Jul 05 05:28:40 PM PDT 24
Finished Jul 05 05:28:49 PM PDT 24
Peak memory 226044 kb
Host smart-959f5b79-e6e8-46c1-ab08-3d9f203dda21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917291570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.1917291570
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.176012167
Short name T842
Test name
Test status
Simulation time 49550435 ps
CPU time 3.5 seconds
Started Jul 05 05:28:41 PM PDT 24
Finished Jul 05 05:28:45 PM PDT 24
Peak memory 214880 kb
Host smart-a123a9dd-6252-47bb-a4d0-da672d8d3962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176012167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.176012167
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.2739036742
Short name T423
Test name
Test status
Simulation time 753473202 ps
CPU time 15.13 seconds
Started Jul 05 05:28:38 PM PDT 24
Finished Jul 05 05:28:53 PM PDT 24
Peak memory 250980 kb
Host smart-eb1515f4-bd0e-4c56-9534-7d157d236de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739036742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2739036742
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.2948547354
Short name T689
Test name
Test status
Simulation time 57992476 ps
CPU time 5.93 seconds
Started Jul 05 05:28:36 PM PDT 24
Finished Jul 05 05:28:43 PM PDT 24
Peak memory 246788 kb
Host smart-09c69559-f237-4b08-a790-7f440df174f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948547354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.2948547354
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.2280753254
Short name T651
Test name
Test status
Simulation time 43731049667 ps
CPU time 104.43 seconds
Started Jul 05 05:28:42 PM PDT 24
Finished Jul 05 05:30:27 PM PDT 24
Peak memory 246928 kb
Host smart-a97ded27-a63a-4473-b557-fd3494e12893
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280753254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.2280753254
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.1607816979
Short name T751
Test name
Test status
Simulation time 9671795529 ps
CPU time 172.76 seconds
Started Jul 05 05:28:38 PM PDT 24
Finished Jul 05 05:31:32 PM PDT 24
Peak memory 316748 kb
Host smart-43a02e76-ff5b-442a-88b9-9ad4dcdb875a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1607816979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.1607816979
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1263302455
Short name T382
Test name
Test status
Simulation time 22600812 ps
CPU time 1.01 seconds
Started Jul 05 05:28:39 PM PDT 24
Finished Jul 05 05:28:41 PM PDT 24
Peak memory 211820 kb
Host smart-916948d2-de0d-4ed6-8b46-c569862bbde5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263302455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.1263302455
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.416950383
Short name T649
Test name
Test status
Simulation time 90234714 ps
CPU time 0.99 seconds
Started Jul 05 05:28:37 PM PDT 24
Finished Jul 05 05:28:39 PM PDT 24
Peak memory 208972 kb
Host smart-f709002f-45ae-45b7-9cd8-3f9f3aafd368
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416950383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.416950383
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.844722012
Short name T34
Test name
Test status
Simulation time 803017232 ps
CPU time 12.41 seconds
Started Jul 05 05:28:39 PM PDT 24
Finished Jul 05 05:28:52 PM PDT 24
Peak memory 218228 kb
Host smart-cb5f7895-a3a1-44a0-971e-5bb1829b769e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844722012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.844722012
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.852643537
Short name T701
Test name
Test status
Simulation time 7355530201 ps
CPU time 7.79 seconds
Started Jul 05 05:28:44 PM PDT 24
Finished Jul 05 05:28:53 PM PDT 24
Peak memory 217732 kb
Host smart-3593639d-f7b2-44f9-b616-71e70bb00f3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852643537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.852643537
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.78385142
Short name T350
Test name
Test status
Simulation time 5239475732 ps
CPU time 21.42 seconds
Started Jul 05 05:28:37 PM PDT 24
Finished Jul 05 05:28:59 PM PDT 24
Peak memory 218176 kb
Host smart-850703cc-2451-413e-9061-adcf0de585df
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78385142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_err
ors.78385142
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1875008578
Short name T97
Test name
Test status
Simulation time 3630579853 ps
CPU time 20.93 seconds
Started Jul 05 05:28:45 PM PDT 24
Finished Jul 05 05:29:07 PM PDT 24
Peak memory 218308 kb
Host smart-6cee5c72-80cd-4c92-9818-6f13451ed247
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875008578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1875008578
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2633868181
Short name T26
Test name
Test status
Simulation time 655093076 ps
CPU time 5.33 seconds
Started Jul 05 05:28:35 PM PDT 24
Finished Jul 05 05:28:41 PM PDT 24
Peak memory 217644 kb
Host smart-d3f84d28-831c-44d2-a79e-f1e4baeb8aab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633868181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2633868181
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.3746246558
Short name T569
Test name
Test status
Simulation time 1006069786 ps
CPU time 46.28 seconds
Started Jul 05 05:28:39 PM PDT 24
Finished Jul 05 05:29:26 PM PDT 24
Peak memory 250972 kb
Host smart-ccbe3f7e-6fdf-4603-b572-b898932c9a08
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746246558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.3746246558
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3363881026
Short name T735
Test name
Test status
Simulation time 4037006165 ps
CPU time 14.29 seconds
Started Jul 05 05:28:44 PM PDT 24
Finished Jul 05 05:28:59 PM PDT 24
Peak memory 226784 kb
Host smart-4675ee86-76db-437d-a52e-84a4aba1329f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363881026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3363881026
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.1804795376
Short name T741
Test name
Test status
Simulation time 103019940 ps
CPU time 3.39 seconds
Started Jul 05 05:28:43 PM PDT 24
Finished Jul 05 05:28:47 PM PDT 24
Peak memory 218148 kb
Host smart-18b4822f-fbce-416b-b233-aff2245dc0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804795376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1804795376
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.3694567216
Short name T189
Test name
Test status
Simulation time 1460657320 ps
CPU time 14.19 seconds
Started Jul 05 05:28:40 PM PDT 24
Finished Jul 05 05:28:55 PM PDT 24
Peak memory 218896 kb
Host smart-67673e08-5709-4a47-8cba-61110a98bcd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694567216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.3694567216
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2693716414
Short name T454
Test name
Test status
Simulation time 6359265008 ps
CPU time 16.05 seconds
Started Jul 05 05:28:41 PM PDT 24
Finished Jul 05 05:28:58 PM PDT 24
Peak memory 226104 kb
Host smart-6fceef7e-7cf7-4673-b9a1-5eca807c93cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693716414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2693716414
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2485516371
Short name T529
Test name
Test status
Simulation time 1428297002 ps
CPU time 12.87 seconds
Started Jul 05 05:28:40 PM PDT 24
Finished Jul 05 05:28:54 PM PDT 24
Peak memory 218248 kb
Host smart-c80d42da-e8f6-4d5d-84f2-20d990e73694
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485516371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2485516371
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.3192845853
Short name T600
Test name
Test status
Simulation time 353499563 ps
CPU time 8.91 seconds
Started Jul 05 05:28:51 PM PDT 24
Finished Jul 05 05:29:00 PM PDT 24
Peak memory 225376 kb
Host smart-4037e797-954c-44a3-abdf-03a06651ea05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192845853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.3192845853
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.1502267871
Short name T830
Test name
Test status
Simulation time 24418790 ps
CPU time 1.63 seconds
Started Jul 05 05:28:38 PM PDT 24
Finished Jul 05 05:28:41 PM PDT 24
Peak memory 217680 kb
Host smart-8bc3d20d-7e99-4719-ace1-96ba2e3dc7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502267871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.1502267871
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.3350863670
Short name T782
Test name
Test status
Simulation time 1293835329 ps
CPU time 27.86 seconds
Started Jul 05 05:28:38 PM PDT 24
Finished Jul 05 05:29:06 PM PDT 24
Peak memory 250992 kb
Host smart-bb73159f-a384-46b4-870a-82f18b7e5bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350863670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3350863670
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.2473971965
Short name T535
Test name
Test status
Simulation time 52304889 ps
CPU time 6.8 seconds
Started Jul 05 05:28:39 PM PDT 24
Finished Jul 05 05:28:47 PM PDT 24
Peak memory 250624 kb
Host smart-c06d024a-1311-46e1-bf11-ef2e0dfd8810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473971965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.2473971965
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.3127472063
Short name T432
Test name
Test status
Simulation time 29500400452 ps
CPU time 153.36 seconds
Started Jul 05 05:28:38 PM PDT 24
Finished Jul 05 05:31:13 PM PDT 24
Peak memory 266668 kb
Host smart-2bf9a480-f1b0-4c66-b0b2-000b225c0459
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127472063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.3127472063
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1501721867
Short name T772
Test name
Test status
Simulation time 49152644 ps
CPU time 0.88 seconds
Started Jul 05 05:28:48 PM PDT 24
Finished Jul 05 05:28:50 PM PDT 24
Peak memory 208732 kb
Host smart-b671ef2e-7af6-4f04-bd42-8934ea36e611
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501721867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1501721867
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.1521998228
Short name T322
Test name
Test status
Simulation time 966224567 ps
CPU time 8.66 seconds
Started Jul 05 05:28:46 PM PDT 24
Finished Jul 05 05:28:55 PM PDT 24
Peak memory 218144 kb
Host smart-7e5cc73f-c10b-432b-b010-80f880adad69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521998228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1521998228
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.4058352683
Short name T616
Test name
Test status
Simulation time 2296658487 ps
CPU time 12.16 seconds
Started Jul 05 05:28:44 PM PDT 24
Finished Jul 05 05:28:57 PM PDT 24
Peak memory 217364 kb
Host smart-2aa5275a-640a-4ffd-98f9-7375f2bccaa9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058352683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.4058352683
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3279016162
Short name T9
Test name
Test status
Simulation time 18055348002 ps
CPU time 29.62 seconds
Started Jul 05 05:28:46 PM PDT 24
Finished Jul 05 05:29:16 PM PDT 24
Peak memory 218876 kb
Host smart-4115c2b2-fabc-4ddc-afb7-4e0e39cd1ace
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279016162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3279016162
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3970601256
Short name T357
Test name
Test status
Simulation time 163110483 ps
CPU time 6.02 seconds
Started Jul 05 05:28:45 PM PDT 24
Finished Jul 05 05:28:52 PM PDT 24
Peak memory 218248 kb
Host smart-64aba12f-aa0d-4d21-a168-09dab3e7da90
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970601256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.3970601256
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1706932033
Short name T340
Test name
Test status
Simulation time 412415910 ps
CPU time 11.51 seconds
Started Jul 05 05:28:47 PM PDT 24
Finished Jul 05 05:28:59 PM PDT 24
Peak memory 217728 kb
Host smart-a87abfe2-0ce1-4a30-98f5-71dd5d968f98
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706932033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1706932033
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2751100609
Short name T313
Test name
Test status
Simulation time 10514777748 ps
CPU time 53.3 seconds
Started Jul 05 05:28:49 PM PDT 24
Finished Jul 05 05:29:43 PM PDT 24
Peak memory 275208 kb
Host smart-5c4777a5-77ff-48b9-8b6a-949bb56d6302
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751100609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2751100609
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3730860650
Short name T591
Test name
Test status
Simulation time 789443429 ps
CPU time 18.37 seconds
Started Jul 05 05:28:50 PM PDT 24
Finished Jul 05 05:29:09 PM PDT 24
Peak memory 245200 kb
Host smart-805f76bb-7bfe-45b3-b85d-775e44842e8c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730860650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.3730860650
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1942335295
Short name T475
Test name
Test status
Simulation time 351402145 ps
CPU time 2.92 seconds
Started Jul 05 05:28:48 PM PDT 24
Finished Jul 05 05:28:51 PM PDT 24
Peak memory 222216 kb
Host smart-cc2d303f-944c-4393-a74b-3ce282620374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942335295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1942335295
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.3656927373
Short name T547
Test name
Test status
Simulation time 235218294 ps
CPU time 9.88 seconds
Started Jul 05 05:28:45 PM PDT 24
Finished Jul 05 05:28:56 PM PDT 24
Peak memory 218360 kb
Host smart-6a0adbf9-74a3-4456-9e2b-3d46c38a2852
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656927373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3656927373
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.2237775197
Short name T578
Test name
Test status
Simulation time 413234905 ps
CPU time 12.68 seconds
Started Jul 05 05:28:47 PM PDT 24
Finished Jul 05 05:29:01 PM PDT 24
Peak memory 226000 kb
Host smart-3e164fdf-ce6c-4671-8505-336bb6be7ed6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237775197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.2237775197
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.1584710403
Short name T861
Test name
Test status
Simulation time 328936185 ps
CPU time 8.73 seconds
Started Jul 05 05:28:46 PM PDT 24
Finished Jul 05 05:28:56 PM PDT 24
Peak memory 218264 kb
Host smart-dd9993c5-fe3f-48ee-9738-d02c653cc90a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584710403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
1584710403
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.2394557716
Short name T46
Test name
Test status
Simulation time 1113415494 ps
CPU time 11.3 seconds
Started Jul 05 05:28:48 PM PDT 24
Finished Jul 05 05:29:01 PM PDT 24
Peak memory 218300 kb
Host smart-fc4d9697-940a-41a7-8a9d-68166f26f8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394557716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2394557716
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2728375085
Short name T736
Test name
Test status
Simulation time 155191533 ps
CPU time 3.13 seconds
Started Jul 05 05:28:39 PM PDT 24
Finished Jul 05 05:28:43 PM PDT 24
Peak memory 217644 kb
Host smart-cf228bbb-ec70-4875-88f1-af844bce74ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728375085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2728375085
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.64309215
Short name T260
Test name
Test status
Simulation time 340715435 ps
CPU time 33.29 seconds
Started Jul 05 05:28:50 PM PDT 24
Finished Jul 05 05:29:24 PM PDT 24
Peak memory 250960 kb
Host smart-1d6b60e9-bedf-420d-b6b9-529eaeb89dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64309215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.64309215
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.1081169882
Short name T234
Test name
Test status
Simulation time 157784188 ps
CPU time 7.42 seconds
Started Jul 05 05:28:46 PM PDT 24
Finished Jul 05 05:28:54 PM PDT 24
Peak memory 250392 kb
Host smart-868aa14f-3d1f-4111-a848-c9fca8d9a050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081169882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.1081169882
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.4222075370
Short name T771
Test name
Test status
Simulation time 5268854446 ps
CPU time 57.15 seconds
Started Jul 05 05:28:50 PM PDT 24
Finished Jul 05 05:29:48 PM PDT 24
Peak memory 251024 kb
Host smart-4076b7a7-24a7-4b18-930c-88b659e9fe3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222075370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.4222075370
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.356300120
Short name T749
Test name
Test status
Simulation time 16992887316 ps
CPU time 626.06 seconds
Started Jul 05 05:28:49 PM PDT 24
Finished Jul 05 05:39:16 PM PDT 24
Peak memory 422140 kb
Host smart-a375b559-98a8-442a-955b-beebaae5e080
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=356300120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.356300120
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.640920640
Short name T179
Test name
Test status
Simulation time 38604992 ps
CPU time 0.91 seconds
Started Jul 05 05:28:45 PM PDT 24
Finished Jul 05 05:28:47 PM PDT 24
Peak memory 211952 kb
Host smart-ea039a52-022e-42df-87eb-1c397b5583ac
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640920640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.640920640
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.2259895383
Short name T705
Test name
Test status
Simulation time 72731170 ps
CPU time 1.09 seconds
Started Jul 05 05:28:48 PM PDT 24
Finished Jul 05 05:28:50 PM PDT 24
Peak memory 208996 kb
Host smart-4f54c0ec-c076-4574-8378-360c420ddc9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259895383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2259895383
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.2920286734
Short name T522
Test name
Test status
Simulation time 177989978 ps
CPU time 10.88 seconds
Started Jul 05 05:28:47 PM PDT 24
Finished Jul 05 05:28:59 PM PDT 24
Peak memory 218220 kb
Host smart-6a759a0a-48f4-4455-a3e0-5155488b431b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920286734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2920286734
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.3454694531
Short name T582
Test name
Test status
Simulation time 8544407360 ps
CPU time 55.71 seconds
Started Jul 05 05:28:47 PM PDT 24
Finished Jul 05 05:29:44 PM PDT 24
Peak memory 218208 kb
Host smart-f713e31b-b3fe-4911-aed2-f0618b8b76a2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454694531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.3454694531
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3367792302
Short name T650
Test name
Test status
Simulation time 335762719 ps
CPU time 11.48 seconds
Started Jul 05 05:28:48 PM PDT 24
Finished Jul 05 05:29:01 PM PDT 24
Peak memory 218244 kb
Host smart-67cbd609-13ac-4123-a3c6-c721cf8a3b5b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367792302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3367792302
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.1834699169
Short name T570
Test name
Test status
Simulation time 329362022 ps
CPU time 1.77 seconds
Started Jul 05 05:28:47 PM PDT 24
Finished Jul 05 05:28:50 PM PDT 24
Peak memory 217724 kb
Host smart-10286a61-f994-4f52-b0ee-10ad5580c0ee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834699169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.1834699169
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1904168401
Short name T596
Test name
Test status
Simulation time 1593768043 ps
CPU time 45.53 seconds
Started Jul 05 05:28:45 PM PDT 24
Finished Jul 05 05:29:32 PM PDT 24
Peak memory 267252 kb
Host smart-9535fa93-bf7b-4201-8371-3e12d4a41c75
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904168401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1904168401
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.236062816
Short name T147
Test name
Test status
Simulation time 316801857 ps
CPU time 12.11 seconds
Started Jul 05 05:28:46 PM PDT 24
Finished Jul 05 05:28:59 PM PDT 24
Peak memory 250940 kb
Host smart-a9c16eb9-0951-4a6a-aec8-8c4df23398e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236062816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_
jtag_state_post_trans.236062816
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3806227312
Short name T358
Test name
Test status
Simulation time 421550107 ps
CPU time 3.11 seconds
Started Jul 05 05:28:50 PM PDT 24
Finished Jul 05 05:28:54 PM PDT 24
Peak memory 222568 kb
Host smart-23a8cc3b-a222-4d43-b6f6-764d54bfa202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806227312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3806227312
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.2823730264
Short name T442
Test name
Test status
Simulation time 382618742 ps
CPU time 11.61 seconds
Started Jul 05 05:28:47 PM PDT 24
Finished Jul 05 05:28:59 PM PDT 24
Peak memory 226048 kb
Host smart-c50bc032-03fa-4ea8-a94f-e9d930730a7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823730264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.2823730264
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1481475592
Short name T803
Test name
Test status
Simulation time 2033153147 ps
CPU time 11.58 seconds
Started Jul 05 05:28:45 PM PDT 24
Finished Jul 05 05:28:58 PM PDT 24
Peak memory 218220 kb
Host smart-3275fa37-8506-4db0-b0f8-56a14ed4fd4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481475592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1481475592
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.3997845905
Short name T50
Test name
Test status
Simulation time 352800378 ps
CPU time 13.73 seconds
Started Jul 05 05:28:48 PM PDT 24
Finished Jul 05 05:29:03 PM PDT 24
Peak memory 218192 kb
Host smart-48062c1a-82d1-4095-9e33-f66ad6c34770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997845905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3997845905
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.2747959693
Short name T66
Test name
Test status
Simulation time 529293462 ps
CPU time 2.2 seconds
Started Jul 05 05:28:43 PM PDT 24
Finished Jul 05 05:28:46 PM PDT 24
Peak memory 214596 kb
Host smart-760cbb20-c5fc-40e0-9244-c098072afbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747959693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2747959693
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.1091413759
Short name T56
Test name
Test status
Simulation time 276096238 ps
CPU time 38.26 seconds
Started Jul 05 05:28:47 PM PDT 24
Finished Jul 05 05:29:26 PM PDT 24
Peak memory 250992 kb
Host smart-c71e26e9-58e2-460e-9dfb-2139d6e3abfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091413759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.1091413759
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.1408554561
Short name T795
Test name
Test status
Simulation time 61166631 ps
CPU time 8.07 seconds
Started Jul 05 05:28:47 PM PDT 24
Finished Jul 05 05:28:56 PM PDT 24
Peak memory 250984 kb
Host smart-82df5403-ec27-4b66-9945-12f99d7a1e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408554561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1408554561
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.1208828290
Short name T251
Test name
Test status
Simulation time 4090023388 ps
CPU time 66.8 seconds
Started Jul 05 05:28:50 PM PDT 24
Finished Jul 05 05:29:58 PM PDT 24
Peak memory 275852 kb
Host smart-5ae0f690-5bac-458e-a2f4-1634f1ccb873
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208828290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.1208828290
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.174691636
Short name T791
Test name
Test status
Simulation time 22330539 ps
CPU time 1.02 seconds
Started Jul 05 05:28:46 PM PDT 24
Finished Jul 05 05:28:48 PM PDT 24
Peak memory 217724 kb
Host smart-177805a0-0bc0-4858-81e7-b25b827e69d0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174691636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.174691636
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2375920073
Short name T501
Test name
Test status
Simulation time 38346192 ps
CPU time 0.94 seconds
Started Jul 05 05:28:59 PM PDT 24
Finished Jul 05 05:29:01 PM PDT 24
Peak memory 208916 kb
Host smart-f18f32c9-d172-4ab2-8ae4-5207d87c7473
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375920073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2375920073
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.3098716164
Short name T407
Test name
Test status
Simulation time 443304585 ps
CPU time 11.69 seconds
Started Jul 05 05:28:56 PM PDT 24
Finished Jul 05 05:29:09 PM PDT 24
Peak memory 225988 kb
Host smart-aca8c453-1e4c-45fc-b93c-b1c92daf4977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098716164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.3098716164
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.297737256
Short name T32
Test name
Test status
Simulation time 125395447 ps
CPU time 3.54 seconds
Started Jul 05 05:28:56 PM PDT 24
Finished Jul 05 05:29:02 PM PDT 24
Peak memory 217060 kb
Host smart-2af512b4-562f-4dc4-8376-a8e605fe876c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297737256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.297737256
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.3627163826
Short name T472
Test name
Test status
Simulation time 2524843782 ps
CPU time 41.12 seconds
Started Jul 05 05:28:54 PM PDT 24
Finished Jul 05 05:29:36 PM PDT 24
Peak memory 218968 kb
Host smart-33a2060f-8694-4fbc-b967-1f3f28c06174
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627163826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.3627163826
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.366008484
Short name T747
Test name
Test status
Simulation time 328986828 ps
CPU time 6.47 seconds
Started Jul 05 05:28:53 PM PDT 24
Finished Jul 05 05:29:00 PM PDT 24
Peak memory 218212 kb
Host smart-0fb65b90-325c-43d9-9bad-0926b42e7cbe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366008484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.366008484
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1963003025
Short name T73
Test name
Test status
Simulation time 747223375 ps
CPU time 1.94 seconds
Started Jul 05 05:28:55 PM PDT 24
Finished Jul 05 05:28:59 PM PDT 24
Peak memory 217716 kb
Host smart-f3e36379-1320-4b3b-a15c-d4bffb48e25e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963003025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1963003025
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3671600194
Short name T96
Test name
Test status
Simulation time 16262956323 ps
CPU time 45.13 seconds
Started Jul 05 05:28:55 PM PDT 24
Finished Jul 05 05:29:42 PM PDT 24
Peak memory 283804 kb
Host smart-e89b130b-fcc9-415b-ba01-68a8e6e32879
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671600194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3671600194
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2126637825
Short name T338
Test name
Test status
Simulation time 2744362028 ps
CPU time 14.59 seconds
Started Jul 05 05:28:59 PM PDT 24
Finished Jul 05 05:29:15 PM PDT 24
Peak memory 248884 kb
Host smart-37403a58-fe90-46b3-8982-56defa709268
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126637825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.2126637825
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.2251237380
Short name T158
Test name
Test status
Simulation time 364588589 ps
CPU time 2.9 seconds
Started Jul 05 05:28:54 PM PDT 24
Finished Jul 05 05:28:57 PM PDT 24
Peak memory 222424 kb
Host smart-3ef908fe-a448-4cd1-8734-f28ec5336670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251237380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.2251237380
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3758342974
Short name T738
Test name
Test status
Simulation time 1067829941 ps
CPU time 12.72 seconds
Started Jul 05 05:28:54 PM PDT 24
Finished Jul 05 05:29:07 PM PDT 24
Peak memory 218172 kb
Host smart-f54fdf92-e90c-4d1e-baa0-b70d096456b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758342974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3758342974
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1891043852
Short name T458
Test name
Test status
Simulation time 2485549853 ps
CPU time 17.44 seconds
Started Jul 05 05:28:55 PM PDT 24
Finished Jul 05 05:29:14 PM PDT 24
Peak memory 226000 kb
Host smart-843af5e1-15ba-42dc-9d50-0cbd8ea4a857
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891043852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1891043852
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.1961491578
Short name T618
Test name
Test status
Simulation time 471752767 ps
CPU time 15.78 seconds
Started Jul 05 05:28:55 PM PDT 24
Finished Jul 05 05:29:12 PM PDT 24
Peak memory 226052 kb
Host smart-311a4dad-550d-4029-9d66-e393d2f2467b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961491578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
1961491578
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.560826627
Short name T553
Test name
Test status
Simulation time 675251554 ps
CPU time 16.12 seconds
Started Jul 05 05:28:53 PM PDT 24
Finished Jul 05 05:29:10 PM PDT 24
Peak memory 225992 kb
Host smart-83143957-0206-495f-bf26-a9036b7181d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560826627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.560826627
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1521277360
Short name T447
Test name
Test status
Simulation time 86517167 ps
CPU time 3.78 seconds
Started Jul 05 05:28:46 PM PDT 24
Finished Jul 05 05:28:51 PM PDT 24
Peak memory 217716 kb
Host smart-5372e527-e18e-4afb-9ebc-2d571dd6a938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521277360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1521277360
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.4051748653
Short name T833
Test name
Test status
Simulation time 989759434 ps
CPU time 29.13 seconds
Started Jul 05 05:28:56 PM PDT 24
Finished Jul 05 05:29:26 PM PDT 24
Peak memory 250976 kb
Host smart-21f06c0f-7480-4ff2-bba0-520e95518f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051748653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.4051748653
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.564577267
Short name T337
Test name
Test status
Simulation time 100150602 ps
CPU time 10.5 seconds
Started Jul 05 05:28:55 PM PDT 24
Finished Jul 05 05:29:07 PM PDT 24
Peak memory 250984 kb
Host smart-1da9de8f-56cb-4e92-8f83-7c22e38b675c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564577267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.564577267
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.4007159238
Short name T104
Test name
Test status
Simulation time 9612554625 ps
CPU time 190.38 seconds
Started Jul 05 05:28:57 PM PDT 24
Finished Jul 05 05:32:09 PM PDT 24
Peak memory 267408 kb
Host smart-4891fc7c-94ae-4566-ad7d-f353195f6a45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007159238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.4007159238
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3575137282
Short name T418
Test name
Test status
Simulation time 62250628 ps
CPU time 0.84 seconds
Started Jul 05 05:28:48 PM PDT 24
Finished Jul 05 05:28:50 PM PDT 24
Peak memory 211828 kb
Host smart-47c74f52-e24a-4e3b-a813-767955178c35
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575137282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3575137282
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.3671251705
Short name T592
Test name
Test status
Simulation time 153312795 ps
CPU time 1.25 seconds
Started Jul 05 05:27:40 PM PDT 24
Finished Jul 05 05:27:44 PM PDT 24
Peak memory 209220 kb
Host smart-e4b057f5-a8ac-41bc-a6fe-7bc20d30b227
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671251705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3671251705
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.3973263039
Short name T298
Test name
Test status
Simulation time 20041767 ps
CPU time 0.81 seconds
Started Jul 05 05:27:40 PM PDT 24
Finished Jul 05 05:27:44 PM PDT 24
Peak memory 209012 kb
Host smart-23e473cc-fde4-4165-b379-ab7ba82f9dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973263039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.3973263039
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2739413054
Short name T235
Test name
Test status
Simulation time 383150122 ps
CPU time 10.7 seconds
Started Jul 05 05:27:40 PM PDT 24
Finished Jul 05 05:27:53 PM PDT 24
Peak memory 226164 kb
Host smart-0631243b-7159-4ff7-b8ff-0a92126fa0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739413054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2739413054
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.3838729065
Short name T31
Test name
Test status
Simulation time 674012624 ps
CPU time 5.96 seconds
Started Jul 05 05:27:41 PM PDT 24
Finished Jul 05 05:27:49 PM PDT 24
Peak memory 217604 kb
Host smart-7e1ec13f-654b-492f-9874-673e083c03d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838729065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.3838729065
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.2398712146
Short name T333
Test name
Test status
Simulation time 6410471599 ps
CPU time 42.77 seconds
Started Jul 05 05:27:39 PM PDT 24
Finished Jul 05 05:28:25 PM PDT 24
Peak memory 218964 kb
Host smart-36e1db99-db17-42b4-86b9-67bc30ba5295
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398712146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.2398712146
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.4147331104
Short name T560
Test name
Test status
Simulation time 301317571 ps
CPU time 4.62 seconds
Started Jul 05 05:27:40 PM PDT 24
Finished Jul 05 05:27:47 PM PDT 24
Peak memory 217748 kb
Host smart-b7e7772b-8aba-464e-b18c-37b4fd8d0c1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147331104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.4
147331104
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.4119582778
Short name T804
Test name
Test status
Simulation time 6486698880 ps
CPU time 9.16 seconds
Started Jul 05 05:27:39 PM PDT 24
Finished Jul 05 05:27:51 PM PDT 24
Peak memory 218244 kb
Host smart-1f8d2d8d-50a1-4491-b62f-be1f4f693185
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119582778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.4119582778
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1451055943
Short name T764
Test name
Test status
Simulation time 8387015905 ps
CPU time 21.03 seconds
Started Jul 05 05:27:38 PM PDT 24
Finished Jul 05 05:28:02 PM PDT 24
Peak memory 217796 kb
Host smart-5b0bd316-b5d1-46f2-8eae-71445149af64
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451055943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.1451055943
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.3531059107
Short name T81
Test name
Test status
Simulation time 1084168666 ps
CPU time 6.14 seconds
Started Jul 05 05:27:40 PM PDT 24
Finished Jul 05 05:27:49 PM PDT 24
Peak memory 217728 kb
Host smart-176bf633-1f5f-47dc-bd10-09836bdec5a8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531059107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
3531059107
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1878414651
Short name T293
Test name
Test status
Simulation time 6035831117 ps
CPU time 52.63 seconds
Started Jul 05 05:27:40 PM PDT 24
Finished Jul 05 05:28:35 PM PDT 24
Peak memory 275812 kb
Host smart-5bc12dcf-f0da-4d1e-981e-38ac334de751
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878414651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.1878414651
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3788969468
Short name T177
Test name
Test status
Simulation time 602671945 ps
CPU time 11.41 seconds
Started Jul 05 05:27:39 PM PDT 24
Finished Jul 05 05:27:53 PM PDT 24
Peak memory 222152 kb
Host smart-ae93aba0-047b-4722-87b4-20ca7a66597a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788969468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.3788969468
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.479633813
Short name T262
Test name
Test status
Simulation time 416792898 ps
CPU time 3.35 seconds
Started Jul 05 05:27:39 PM PDT 24
Finished Jul 05 05:27:46 PM PDT 24
Peak memory 218256 kb
Host smart-7155942d-05b9-4e7f-8021-1e48bd90884e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479633813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.479633813
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2627540670
Short name T78
Test name
Test status
Simulation time 207559344 ps
CPU time 8.52 seconds
Started Jul 05 05:27:36 PM PDT 24
Finished Jul 05 05:27:48 PM PDT 24
Peak memory 217788 kb
Host smart-4d1f4bbb-340f-4e52-8dc4-7d4cd6fa118f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627540670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2627540670
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.4181874093
Short name T47
Test name
Test status
Simulation time 424436781 ps
CPU time 40.63 seconds
Started Jul 05 05:27:38 PM PDT 24
Finished Jul 05 05:28:22 PM PDT 24
Peak memory 269260 kb
Host smart-42e687e5-5058-4a80-9f10-b4a658d340d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181874093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.4181874093
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.150933592
Short name T699
Test name
Test status
Simulation time 173599384 ps
CPU time 9.53 seconds
Started Jul 05 05:27:38 PM PDT 24
Finished Jul 05 05:27:51 PM PDT 24
Peak memory 225968 kb
Host smart-5d1c4084-4d4a-4f98-9f38-f00e608b3ef0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150933592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.150933592
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2907408955
Short name T518
Test name
Test status
Simulation time 373895826 ps
CPU time 12.65 seconds
Started Jul 05 05:27:39 PM PDT 24
Finished Jul 05 05:27:54 PM PDT 24
Peak memory 225960 kb
Host smart-5e768f03-021c-48e4-af45-754bdb74c836
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907408955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2907408955
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1806358485
Short name T781
Test name
Test status
Simulation time 1553106688 ps
CPU time 11.12 seconds
Started Jul 05 05:27:41 PM PDT 24
Finished Jul 05 05:27:54 PM PDT 24
Peak memory 226036 kb
Host smart-258b0876-4151-4b92-86fd-cd31b478c17b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806358485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.1
806358485
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.3455487439
Short name T520
Test name
Test status
Simulation time 404278192 ps
CPU time 8.14 seconds
Started Jul 05 05:27:38 PM PDT 24
Finished Jul 05 05:27:50 PM PDT 24
Peak memory 226016 kb
Host smart-11672d13-aabf-476a-954c-d43e3eafea32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455487439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3455487439
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.4158866278
Short name T278
Test name
Test status
Simulation time 87139733 ps
CPU time 4.47 seconds
Started Jul 05 05:27:39 PM PDT 24
Finished Jul 05 05:27:47 PM PDT 24
Peak memory 217764 kb
Host smart-20999b39-c6ac-47ff-aa68-52f4f3c4dedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158866278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.4158866278
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.1039167891
Short name T422
Test name
Test status
Simulation time 294157562 ps
CPU time 28.3 seconds
Started Jul 05 05:27:39 PM PDT 24
Finished Jul 05 05:28:10 PM PDT 24
Peak memory 250984 kb
Host smart-10ac3b0d-439d-4a78-8aaa-b6dba0a5514c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039167891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1039167891
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.2839004706
Short name T496
Test name
Test status
Simulation time 90551101 ps
CPU time 11.23 seconds
Started Jul 05 05:27:44 PM PDT 24
Finished Jul 05 05:27:56 PM PDT 24
Peak memory 250300 kb
Host smart-f4a13d89-645e-465c-bde3-4713103b7915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839004706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2839004706
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.398333262
Short name T498
Test name
Test status
Simulation time 13256979967 ps
CPU time 158.05 seconds
Started Jul 05 05:27:40 PM PDT 24
Finished Jul 05 05:30:21 PM PDT 24
Peak memory 226084 kb
Host smart-85256d8b-46c6-4ecf-8b98-989710156c1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398333262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.398333262
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.1232045721
Short name T860
Test name
Test status
Simulation time 18855820234 ps
CPU time 179.79 seconds
Started Jul 05 05:27:42 PM PDT 24
Finished Jul 05 05:30:43 PM PDT 24
Peak memory 316768 kb
Host smart-59236da4-420a-47cc-9338-e546f7706d6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1232045721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.1232045721
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.377818179
Short name T202
Test name
Test status
Simulation time 15289284 ps
CPU time 1.02 seconds
Started Jul 05 05:27:39 PM PDT 24
Finished Jul 05 05:27:43 PM PDT 24
Peak memory 213164 kb
Host smart-2502f9e5-edd0-4d4b-bac3-d427b6491b67
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377818179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr
l_volatile_unlock_smoke.377818179
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.272829576
Short name T723
Test name
Test status
Simulation time 20925817 ps
CPU time 0.88 seconds
Started Jul 05 05:28:56 PM PDT 24
Finished Jul 05 05:28:58 PM PDT 24
Peak memory 208788 kb
Host smart-a7e7ea3c-522a-4387-9df0-9798d83267fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272829576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.272829576
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3372065519
Short name T580
Test name
Test status
Simulation time 672287150 ps
CPU time 15.22 seconds
Started Jul 05 05:28:53 PM PDT 24
Finished Jul 05 05:29:09 PM PDT 24
Peak memory 226044 kb
Host smart-72b6a50e-a553-491e-b479-089b95ed99c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372065519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3372065519
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.2111260415
Short name T822
Test name
Test status
Simulation time 1338547914 ps
CPU time 12.52 seconds
Started Jul 05 05:28:58 PM PDT 24
Finished Jul 05 05:29:12 PM PDT 24
Peak memory 217372 kb
Host smart-f699a696-5cbb-430a-8ce1-ae1bc7b73a7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111260415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.2111260415
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.1942050673
Short name T169
Test name
Test status
Simulation time 60781103 ps
CPU time 2.08 seconds
Started Jul 05 05:28:52 PM PDT 24
Finished Jul 05 05:28:54 PM PDT 24
Peak memory 222236 kb
Host smart-577874bd-670d-45cd-ab18-3003cd8c7d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942050673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1942050673
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.4041758581
Short name T856
Test name
Test status
Simulation time 1090659486 ps
CPU time 12.38 seconds
Started Jul 05 05:28:56 PM PDT 24
Finished Jul 05 05:29:09 PM PDT 24
Peak memory 226044 kb
Host smart-d855f656-b05f-4b50-a101-594b504c780e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041758581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.4041758581
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.1052829702
Short name T542
Test name
Test status
Simulation time 600373482 ps
CPU time 11.52 seconds
Started Jul 05 05:28:55 PM PDT 24
Finished Jul 05 05:29:08 PM PDT 24
Peak memory 226052 kb
Host smart-6aaada70-a074-4fd3-ada8-49ab44220e04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052829702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.1052829702
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.51310221
Short name T710
Test name
Test status
Simulation time 442040754 ps
CPU time 8.01 seconds
Started Jul 05 05:28:56 PM PDT 24
Finished Jul 05 05:29:05 PM PDT 24
Peak memory 218136 kb
Host smart-2cde008f-21d5-4508-9a35-c6f0e9fe4386
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51310221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.51310221
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3457114166
Short name T369
Test name
Test status
Simulation time 847987484 ps
CPU time 8.85 seconds
Started Jul 05 05:28:58 PM PDT 24
Finished Jul 05 05:29:08 PM PDT 24
Peak memory 226016 kb
Host smart-fcbc0b88-2e43-4914-8382-6b53d6f9bd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457114166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3457114166
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.2504605581
Short name T608
Test name
Test status
Simulation time 53810548 ps
CPU time 2.12 seconds
Started Jul 05 05:28:59 PM PDT 24
Finished Jul 05 05:29:02 PM PDT 24
Peak memory 214396 kb
Host smart-c781bd2d-cbd7-43ed-9979-4e13067d634c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504605581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.2504605581
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.2646301702
Short name T572
Test name
Test status
Simulation time 246413271 ps
CPU time 24.18 seconds
Started Jul 05 05:28:54 PM PDT 24
Finished Jul 05 05:29:19 PM PDT 24
Peak memory 250984 kb
Host smart-b05ab594-27c7-44e1-b1b3-8f46c13de648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646301702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2646301702
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.2853104398
Short name T653
Test name
Test status
Simulation time 66468607 ps
CPU time 9.19 seconds
Started Jul 05 05:28:55 PM PDT 24
Finished Jul 05 05:29:05 PM PDT 24
Peak memory 250940 kb
Host smart-af8bbae7-47f9-49e7-b9cc-222bb6477379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853104398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2853104398
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.1132513977
Short name T35
Test name
Test status
Simulation time 6255601168 ps
CPU time 227.76 seconds
Started Jul 05 05:28:55 PM PDT 24
Finished Jul 05 05:32:44 PM PDT 24
Peak memory 283824 kb
Host smart-4d5903ff-ce1f-4a8a-af14-963debef8083
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132513977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.1132513977
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2069102583
Short name T589
Test name
Test status
Simulation time 23133073 ps
CPU time 1.27 seconds
Started Jul 05 05:28:57 PM PDT 24
Finished Jul 05 05:28:59 PM PDT 24
Peak memory 213004 kb
Host smart-b4b2fc95-4b3b-4058-a9c2-cfef74128d9e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069102583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2069102583
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.3987278074
Short name T766
Test name
Test status
Simulation time 297873913 ps
CPU time 1.21 seconds
Started Jul 05 05:28:58 PM PDT 24
Finished Jul 05 05:29:00 PM PDT 24
Peak memory 208988 kb
Host smart-22831a40-e2d0-483f-b2e0-afa449b3d4b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987278074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.3987278074
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.1159579806
Short name T324
Test name
Test status
Simulation time 3067695319 ps
CPU time 8.25 seconds
Started Jul 05 05:28:59 PM PDT 24
Finished Jul 05 05:29:09 PM PDT 24
Peak memory 218256 kb
Host smart-5fc2feef-f0b5-4bc4-a44d-7c2ef76720f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159579806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1159579806
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.3161777556
Short name T24
Test name
Test status
Simulation time 4830832148 ps
CPU time 12.93 seconds
Started Jul 05 05:28:58 PM PDT 24
Finished Jul 05 05:29:13 PM PDT 24
Peak memory 217712 kb
Host smart-cc7a6cc4-94b9-420b-ab33-48586112ed48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161777556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.3161777556
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.4080348397
Short name T247
Test name
Test status
Simulation time 53841873 ps
CPU time 2.48 seconds
Started Jul 05 05:28:55 PM PDT 24
Finished Jul 05 05:28:59 PM PDT 24
Peak memory 218240 kb
Host smart-9835975a-9bf1-4287-93f0-5bdbb0a87ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080348397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.4080348397
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1442638349
Short name T681
Test name
Test status
Simulation time 1138211435 ps
CPU time 10.96 seconds
Started Jul 05 05:28:55 PM PDT 24
Finished Jul 05 05:29:08 PM PDT 24
Peak memory 219032 kb
Host smart-9c527e9a-02e8-4ebf-af1d-fa8fc17292fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442638349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1442638349
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2444241796
Short name T687
Test name
Test status
Simulation time 3792218086 ps
CPU time 13.69 seconds
Started Jul 05 05:28:59 PM PDT 24
Finished Jul 05 05:29:14 PM PDT 24
Peak memory 226116 kb
Host smart-d7505052-5b61-44cd-93f6-9fa66b5a2fa8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444241796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2444241796
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.2710695293
Short name T60
Test name
Test status
Simulation time 1132124114 ps
CPU time 9.07 seconds
Started Jul 05 05:28:54 PM PDT 24
Finished Jul 05 05:29:04 PM PDT 24
Peak memory 226048 kb
Host smart-c4436a5d-f53d-485b-a1c1-dddbfbcd8717
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710695293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
2710695293
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2359858368
Short name T399
Test name
Test status
Simulation time 983371256 ps
CPU time 6.93 seconds
Started Jul 05 05:28:54 PM PDT 24
Finished Jul 05 05:29:02 PM PDT 24
Peak memory 224500 kb
Host smart-51721415-cef9-45b3-8777-e67902f94fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359858368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2359858368
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1929077707
Short name T82
Test name
Test status
Simulation time 180401923 ps
CPU time 3.1 seconds
Started Jul 05 05:28:56 PM PDT 24
Finished Jul 05 05:29:01 PM PDT 24
Peak memory 215152 kb
Host smart-b571b5cf-2624-4040-bc62-ed565c1b7e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929077707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1929077707
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.434639677
Short name T52
Test name
Test status
Simulation time 618189048 ps
CPU time 31.61 seconds
Started Jul 05 05:28:59 PM PDT 24
Finished Jul 05 05:29:32 PM PDT 24
Peak memory 250960 kb
Host smart-bf74acf4-d6f2-48bc-b0b2-c01ec43355d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434639677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.434639677
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.961334920
Short name T579
Test name
Test status
Simulation time 418277679 ps
CPU time 7.04 seconds
Started Jul 05 05:28:55 PM PDT 24
Finished Jul 05 05:29:03 PM PDT 24
Peak memory 246720 kb
Host smart-72d9dc1c-f3c7-4494-9a22-ffb045abce40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961334920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.961334920
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.61054944
Short name T869
Test name
Test status
Simulation time 45495798219 ps
CPU time 339.93 seconds
Started Jul 05 05:28:58 PM PDT 24
Finished Jul 05 05:34:39 PM PDT 24
Peak memory 273640 kb
Host smart-a1f2fc8b-a476-4746-b9e7-1e432df37cbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61054944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.lc_ctrl_stress_all.61054944
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.261279865
Short name T532
Test name
Test status
Simulation time 140658307 ps
CPU time 1.01 seconds
Started Jul 05 05:28:58 PM PDT 24
Finished Jul 05 05:29:01 PM PDT 24
Peak memory 212972 kb
Host smart-799cd579-d0a8-44d2-ab94-a8a82b792dc9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261279865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.261279865
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.3952204320
Short name T372
Test name
Test status
Simulation time 85139267 ps
CPU time 0.98 seconds
Started Jul 05 05:29:02 PM PDT 24
Finished Jul 05 05:29:05 PM PDT 24
Peak memory 209092 kb
Host smart-afdbd0b4-4fb3-4142-a977-e2e4dd9dab07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952204320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.3952204320
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2881722506
Short name T777
Test name
Test status
Simulation time 1388152382 ps
CPU time 12.26 seconds
Started Jul 05 05:29:05 PM PDT 24
Finished Jul 05 05:29:19 PM PDT 24
Peak memory 218060 kb
Host smart-68e8e21e-e72b-4230-a63d-9b5ffde3be96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881722506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2881722506
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.3835614928
Short name T728
Test name
Test status
Simulation time 635144377 ps
CPU time 2.64 seconds
Started Jul 05 05:29:13 PM PDT 24
Finished Jul 05 05:29:17 PM PDT 24
Peak memory 217112 kb
Host smart-67460fec-711c-494b-90af-6b2bd796c4ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835614928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.3835614928
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.4176124706
Short name T259
Test name
Test status
Simulation time 49371121 ps
CPU time 2.82 seconds
Started Jul 05 05:29:01 PM PDT 24
Finished Jul 05 05:29:05 PM PDT 24
Peak memory 218196 kb
Host smart-f1c23b2d-7492-491d-93d9-a38ab1fbdde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176124706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.4176124706
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.274709090
Short name T272
Test name
Test status
Simulation time 4918655505 ps
CPU time 11.55 seconds
Started Jul 05 05:29:00 PM PDT 24
Finished Jul 05 05:29:13 PM PDT 24
Peak memory 226012 kb
Host smart-95867ede-6039-463b-8448-301d9c342e06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274709090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_di
gest.274709090
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.4121602031
Short name T719
Test name
Test status
Simulation time 829594118 ps
CPU time 9.99 seconds
Started Jul 05 05:29:03 PM PDT 24
Finished Jul 05 05:29:15 PM PDT 24
Peak memory 218268 kb
Host smart-e5062b1d-adb3-4627-ae8f-973647f4ec49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121602031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
4121602031
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.1649787959
Short name T437
Test name
Test status
Simulation time 1118720179 ps
CPU time 7.32 seconds
Started Jul 05 05:29:03 PM PDT 24
Finished Jul 05 05:29:12 PM PDT 24
Peak memory 225984 kb
Host smart-a065e266-6a05-405c-916f-fe3a6aa88dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649787959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1649787959
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.4184452361
Short name T355
Test name
Test status
Simulation time 53664326 ps
CPU time 1.11 seconds
Started Jul 05 05:28:58 PM PDT 24
Finished Jul 05 05:29:00 PM PDT 24
Peak memory 212236 kb
Host smart-c6d75bd5-2f0a-4c23-a334-3df4d8b31c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184452361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.4184452361
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.1172477805
Short name T242
Test name
Test status
Simulation time 255400516 ps
CPU time 18.84 seconds
Started Jul 05 05:28:57 PM PDT 24
Finished Jul 05 05:29:17 PM PDT 24
Peak memory 251104 kb
Host smart-45079969-48dc-4b3f-bf64-3aa3c95564ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172477805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1172477805
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.2707193028
Short name T386
Test name
Test status
Simulation time 321047169 ps
CPU time 6.7 seconds
Started Jul 05 05:29:08 PM PDT 24
Finished Jul 05 05:29:16 PM PDT 24
Peak memory 250488 kb
Host smart-1ded700c-7f32-4616-8210-bba17ce6457e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707193028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.2707193028
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3403486626
Short name T440
Test name
Test status
Simulation time 4341193298 ps
CPU time 104.24 seconds
Started Jul 05 05:29:14 PM PDT 24
Finished Jul 05 05:30:59 PM PDT 24
Peak memory 250688 kb
Host smart-53cc7ba3-72a6-4dce-a532-2ec3a1c7b957
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403486626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3403486626
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.4013820905
Short name T240
Test name
Test status
Simulation time 13244746 ps
CPU time 1.03 seconds
Started Jul 05 05:28:59 PM PDT 24
Finished Jul 05 05:29:01 PM PDT 24
Peak memory 211956 kb
Host smart-cf0fe4de-07a5-4a86-8410-9ac43a998f66
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013820905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.4013820905
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.65199436
Short name T778
Test name
Test status
Simulation time 117776015 ps
CPU time 0.87 seconds
Started Jul 05 05:29:04 PM PDT 24
Finished Jul 05 05:29:06 PM PDT 24
Peak memory 208768 kb
Host smart-676b0fc9-97d6-4c9c-a7e1-e2a92b3c625e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65199436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.65199436
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3090985820
Short name T527
Test name
Test status
Simulation time 521001427 ps
CPU time 11.62 seconds
Started Jul 05 05:29:02 PM PDT 24
Finished Jul 05 05:29:15 PM PDT 24
Peak memory 218224 kb
Host smart-f230ee3f-d050-4823-bbcb-cdc0613b5f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090985820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3090985820
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2423537452
Short name T852
Test name
Test status
Simulation time 690195546 ps
CPU time 9.18 seconds
Started Jul 05 05:29:01 PM PDT 24
Finished Jul 05 05:29:11 PM PDT 24
Peak memory 217316 kb
Host smart-c33f50c4-a408-496a-ad12-8027ce4e17eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423537452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2423537452
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.162623747
Short name T821
Test name
Test status
Simulation time 50116544 ps
CPU time 2.28 seconds
Started Jul 05 05:29:02 PM PDT 24
Finished Jul 05 05:29:06 PM PDT 24
Peak memory 218232 kb
Host smart-d4294cc5-0589-4eb1-9310-b35cdb7c2c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162623747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.162623747
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.1165058052
Short name T530
Test name
Test status
Simulation time 3076316571 ps
CPU time 21.07 seconds
Started Jul 05 05:29:04 PM PDT 24
Finished Jul 05 05:29:26 PM PDT 24
Peak memory 226104 kb
Host smart-108473f1-8767-4ee5-9b37-a405fb0712e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165058052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1165058052
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3998049118
Short name T571
Test name
Test status
Simulation time 4579973516 ps
CPU time 15.7 seconds
Started Jul 05 05:29:01 PM PDT 24
Finished Jul 05 05:29:18 PM PDT 24
Peak memory 226112 kb
Host smart-e11915b1-b124-42dc-b11f-cdbfbf537398
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998049118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.3998049118
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2675480216
Short name T610
Test name
Test status
Simulation time 969582543 ps
CPU time 12.45 seconds
Started Jul 05 05:29:07 PM PDT 24
Finished Jul 05 05:29:20 PM PDT 24
Peak memory 218248 kb
Host smart-dec6867a-92ae-43c4-b5a5-32ff4a6cee8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675480216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2675480216
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.605336429
Short name T525
Test name
Test status
Simulation time 891748174 ps
CPU time 7.16 seconds
Started Jul 05 05:29:03 PM PDT 24
Finished Jul 05 05:29:12 PM PDT 24
Peak memory 226044 kb
Host smart-4398ba69-f190-42a5-9d29-f22241cc6aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605336429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.605336429
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.4114388882
Short name T410
Test name
Test status
Simulation time 658003937 ps
CPU time 4.99 seconds
Started Jul 05 05:29:01 PM PDT 24
Finished Jul 05 05:29:07 PM PDT 24
Peak memory 217636 kb
Host smart-6447ecd9-c057-44bd-9eb0-6180477f57c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114388882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.4114388882
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.3980322777
Short name T389
Test name
Test status
Simulation time 225169318 ps
CPU time 21.01 seconds
Started Jul 05 05:29:03 PM PDT 24
Finished Jul 05 05:29:26 PM PDT 24
Peak memory 250944 kb
Host smart-46c1c8e7-d8bf-4c06-a695-e2cbbe4be2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980322777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3980322777
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3041996381
Short name T612
Test name
Test status
Simulation time 110543065 ps
CPU time 9.25 seconds
Started Jul 05 05:29:02 PM PDT 24
Finished Jul 05 05:29:13 PM PDT 24
Peak memory 250488 kb
Host smart-fe820e83-b40b-4d8a-99c3-d281c6725320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041996381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3041996381
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.2506861011
Short name T204
Test name
Test status
Simulation time 18612938922 ps
CPU time 112.61 seconds
Started Jul 05 05:29:00 PM PDT 24
Finished Jul 05 05:30:54 PM PDT 24
Peak memory 276964 kb
Host smart-4ded19a7-d004-40e7-9431-dcba12854982
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506861011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.2506861011
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.919175298
Short name T351
Test name
Test status
Simulation time 13125851 ps
CPU time 0.91 seconds
Started Jul 05 05:29:04 PM PDT 24
Finished Jul 05 05:29:07 PM PDT 24
Peak memory 211892 kb
Host smart-df4119a4-a56b-43c3-98ba-702df342c9fc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919175298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ct
rl_volatile_unlock_smoke.919175298
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.4089026845
Short name T793
Test name
Test status
Simulation time 70969873 ps
CPU time 0.97 seconds
Started Jul 05 05:29:14 PM PDT 24
Finished Jul 05 05:29:16 PM PDT 24
Peak memory 209028 kb
Host smart-698dac40-3445-4d23-badd-f131c8f92f8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089026845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.4089026845
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.3929207367
Short name T586
Test name
Test status
Simulation time 1945828440 ps
CPU time 10.61 seconds
Started Jul 05 05:29:07 PM PDT 24
Finished Jul 05 05:29:18 PM PDT 24
Peak memory 217664 kb
Host smart-f333980c-52e0-4bc1-baf7-2cbd3c0723c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929207367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.3929207367
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1442660864
Short name T316
Test name
Test status
Simulation time 88661798 ps
CPU time 1.98 seconds
Started Jul 05 05:29:05 PM PDT 24
Finished Jul 05 05:29:08 PM PDT 24
Peak memory 222120 kb
Host smart-51e154d1-1afc-4235-8733-413f3812ba12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442660864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1442660864
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.3714675106
Short name T161
Test name
Test status
Simulation time 820124236 ps
CPU time 11.52 seconds
Started Jul 05 05:29:02 PM PDT 24
Finished Jul 05 05:29:14 PM PDT 24
Peak memory 226044 kb
Host smart-08b7ba67-3e9d-4b26-8d68-6843dc7e8ac3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714675106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.3714675106
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1719561545
Short name T691
Test name
Test status
Simulation time 3789772246 ps
CPU time 18.72 seconds
Started Jul 05 05:29:05 PM PDT 24
Finished Jul 05 05:29:25 PM PDT 24
Peak memory 226040 kb
Host smart-66deeeb9-a478-495f-92bc-fdde096bd62c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719561545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1719561545
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1808327316
Short name T174
Test name
Test status
Simulation time 260986395 ps
CPU time 9.11 seconds
Started Jul 05 05:29:06 PM PDT 24
Finished Jul 05 05:29:16 PM PDT 24
Peak memory 218252 kb
Host smart-2bd8a055-5d1f-4b5e-86d9-e54d4ce3f5af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808327316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1808327316
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.609123137
Short name T818
Test name
Test status
Simulation time 3304471784 ps
CPU time 7.02 seconds
Started Jul 05 05:29:07 PM PDT 24
Finished Jul 05 05:29:15 PM PDT 24
Peak memory 225884 kb
Host smart-2f7a36de-dc9d-47b9-a2e8-8edd9751fb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609123137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.609123137
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.394002321
Short name T434
Test name
Test status
Simulation time 511825195 ps
CPU time 7.66 seconds
Started Jul 05 05:29:14 PM PDT 24
Finished Jul 05 05:29:22 PM PDT 24
Peak memory 217460 kb
Host smart-f6b980d8-d7fc-4dc1-be7c-b949a4fb72eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394002321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.394002321
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.3323684466
Short name T755
Test name
Test status
Simulation time 623251314 ps
CPU time 29.78 seconds
Started Jul 05 05:29:14 PM PDT 24
Finished Jul 05 05:29:45 PM PDT 24
Peak memory 251004 kb
Host smart-cdef5ebb-1a3c-4537-8e0a-619b09793972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323684466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.3323684466
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.4172549777
Short name T375
Test name
Test status
Simulation time 146487691 ps
CPU time 10.02 seconds
Started Jul 05 05:29:03 PM PDT 24
Finished Jul 05 05:29:15 PM PDT 24
Peak memory 250956 kb
Host smart-4c7a988d-71f3-45a1-84f8-7173968471b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172549777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.4172549777
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3166742849
Short name T847
Test name
Test status
Simulation time 3222948016 ps
CPU time 98.28 seconds
Started Jul 05 05:29:01 PM PDT 24
Finished Jul 05 05:30:41 PM PDT 24
Peak memory 226092 kb
Host smart-262a32c7-e566-49ba-b27c-5e09fd051381
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166742849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3166742849
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.3024905033
Short name T36
Test name
Test status
Simulation time 86808784019 ps
CPU time 728.68 seconds
Started Jul 05 05:29:03 PM PDT 24
Finished Jul 05 05:41:14 PM PDT 24
Peak memory 422020 kb
Host smart-f76e19cc-f52a-45bb-893e-41a73317f587
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3024905033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.3024905033
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.4075679075
Short name T271
Test name
Test status
Simulation time 104547377 ps
CPU time 0.96 seconds
Started Jul 05 05:29:03 PM PDT 24
Finished Jul 05 05:29:05 PM PDT 24
Peak memory 211856 kb
Host smart-9da99f94-f595-486d-b0f9-fc23893e27d0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075679075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.4075679075
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.4199355128
Short name T840
Test name
Test status
Simulation time 51599481 ps
CPU time 1.03 seconds
Started Jul 05 05:29:14 PM PDT 24
Finished Jul 05 05:29:16 PM PDT 24
Peak memory 208652 kb
Host smart-030f5403-57f4-4bf4-bb51-3d1cb69abe62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199355128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.4199355128
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.567668147
Short name T311
Test name
Test status
Simulation time 709780072 ps
CPU time 10.55 seconds
Started Jul 05 05:29:02 PM PDT 24
Finished Jul 05 05:29:15 PM PDT 24
Peak memory 218220 kb
Host smart-fc29799a-d2f2-4cc5-b7a0-c4d4fcf70282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567668147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.567668147
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.1266020653
Short name T546
Test name
Test status
Simulation time 78370956 ps
CPU time 1.68 seconds
Started Jul 05 05:29:06 PM PDT 24
Finished Jul 05 05:29:09 PM PDT 24
Peak memory 217216 kb
Host smart-0f66fdcd-3194-4d89-a6ce-e255a9abcc6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266020653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.1266020653
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1320244388
Short name T480
Test name
Test status
Simulation time 134564443 ps
CPU time 3.82 seconds
Started Jul 05 05:29:02 PM PDT 24
Finished Jul 05 05:29:07 PM PDT 24
Peak memory 222556 kb
Host smart-5a60cad6-010d-4301-98a0-790eb62baf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320244388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1320244388
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.1512826570
Short name T37
Test name
Test status
Simulation time 2213867956 ps
CPU time 14.38 seconds
Started Jul 05 05:29:03 PM PDT 24
Finished Jul 05 05:29:19 PM PDT 24
Peak memory 226220 kb
Host smart-825d11ec-a92f-4f98-bce2-779e74bee60c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512826570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1512826570
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1768008812
Short name T404
Test name
Test status
Simulation time 316130529 ps
CPU time 11.85 seconds
Started Jul 05 05:29:00 PM PDT 24
Finished Jul 05 05:29:13 PM PDT 24
Peak memory 226040 kb
Host smart-14d2dd64-8285-47d2-b4be-8f7af4e90904
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768008812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1768008812
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.2880295474
Short name T171
Test name
Test status
Simulation time 811796498 ps
CPU time 11.7 seconds
Started Jul 05 05:29:02 PM PDT 24
Finished Jul 05 05:29:16 PM PDT 24
Peak memory 225460 kb
Host smart-92012188-8e64-42c8-8ae9-dfb6c6317abf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880295474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
2880295474
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1402441309
Short name T667
Test name
Test status
Simulation time 284936615 ps
CPU time 12.48 seconds
Started Jul 05 05:29:05 PM PDT 24
Finished Jul 05 05:29:19 PM PDT 24
Peak memory 226048 kb
Host smart-8f341be7-fac9-4e00-9730-818d94b47cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402441309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1402441309
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3262215209
Short name T748
Test name
Test status
Simulation time 77218063 ps
CPU time 3 seconds
Started Jul 05 05:29:03 PM PDT 24
Finished Jul 05 05:29:08 PM PDT 24
Peak memory 214572 kb
Host smart-f0acd506-ac4c-4824-a1c8-513bdd41e7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262215209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3262215209
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.1605375982
Short name T331
Test name
Test status
Simulation time 1259945039 ps
CPU time 30.01 seconds
Started Jul 05 05:29:07 PM PDT 24
Finished Jul 05 05:29:38 PM PDT 24
Peak memory 250752 kb
Host smart-44f95359-845c-428c-bd80-9f0b8e226068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605375982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.1605375982
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.3033398997
Short name T258
Test name
Test status
Simulation time 112223057 ps
CPU time 3.73 seconds
Started Jul 05 05:29:07 PM PDT 24
Finished Jul 05 05:29:11 PM PDT 24
Peak memory 226408 kb
Host smart-95fedc86-5341-4b73-b14d-d904b48afa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033398997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3033398997
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.993219967
Short name T401
Test name
Test status
Simulation time 5625690656 ps
CPU time 110.98 seconds
Started Jul 05 05:29:04 PM PDT 24
Finished Jul 05 05:30:57 PM PDT 24
Peak memory 281832 kb
Host smart-6a0fff13-c9b2-4762-be9d-b52afcd01eff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993219967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.993219967
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.2048667868
Short name T152
Test name
Test status
Simulation time 64429509960 ps
CPU time 501.29 seconds
Started Jul 05 05:29:04 PM PDT 24
Finished Jul 05 05:37:27 PM PDT 24
Peak memory 422184 kb
Host smart-38ef8d7c-5d3a-487b-9e19-4f088caed06c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2048667868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.2048667868
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.315300175
Short name T256
Test name
Test status
Simulation time 16917441 ps
CPU time 0.93 seconds
Started Jul 05 05:29:04 PM PDT 24
Finished Jul 05 05:29:06 PM PDT 24
Peak memory 211968 kb
Host smart-c8f0ea64-75a6-4cf7-b1ee-0cf52a1dd48e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315300175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ct
rl_volatile_unlock_smoke.315300175
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.2758272860
Short name T383
Test name
Test status
Simulation time 295815146 ps
CPU time 0.98 seconds
Started Jul 05 05:29:12 PM PDT 24
Finished Jul 05 05:29:14 PM PDT 24
Peak memory 208960 kb
Host smart-d03df804-49d8-4661-8ba2-cd211a6f6479
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758272860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2758272860
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.3423139106
Short name T279
Test name
Test status
Simulation time 1565286134 ps
CPU time 17.29 seconds
Started Jul 05 05:29:10 PM PDT 24
Finished Jul 05 05:29:28 PM PDT 24
Peak memory 226044 kb
Host smart-ba5269e7-47e6-401c-aa99-15016bac35cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423139106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3423139106
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1950773648
Short name T712
Test name
Test status
Simulation time 1127942821 ps
CPU time 4.04 seconds
Started Jul 05 05:29:13 PM PDT 24
Finished Jul 05 05:29:18 PM PDT 24
Peak memory 217156 kb
Host smart-b0901a4a-39ee-426f-b2f8-ea1318ff75c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950773648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1950773648
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.1359361380
Short name T391
Test name
Test status
Simulation time 1526370344 ps
CPU time 6.6 seconds
Started Jul 05 05:29:13 PM PDT 24
Finished Jul 05 05:29:21 PM PDT 24
Peak memory 218168 kb
Host smart-158049ef-08c2-4c7e-baf7-5c19675e6644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359361380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1359361380
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.1110592727
Short name T730
Test name
Test status
Simulation time 2020807172 ps
CPU time 11.49 seconds
Started Jul 05 05:29:11 PM PDT 24
Finished Jul 05 05:29:23 PM PDT 24
Peak memory 226048 kb
Host smart-f341e13b-fddd-45e8-b3e6-8bc7623df04b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110592727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.1110592727
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1443705471
Short name T709
Test name
Test status
Simulation time 2062470808 ps
CPU time 11.41 seconds
Started Jul 05 05:29:12 PM PDT 24
Finished Jul 05 05:29:24 PM PDT 24
Peak memory 226044 kb
Host smart-1295964a-61bf-435f-b451-5a8ff14bef49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443705471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1443705471
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3526112772
Short name T768
Test name
Test status
Simulation time 352005014 ps
CPU time 8.35 seconds
Started Jul 05 05:29:12 PM PDT 24
Finished Jul 05 05:29:21 PM PDT 24
Peak memory 218296 kb
Host smart-1cadd973-ded5-4c2f-822d-99998af36e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526112772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3526112772
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.407005384
Short name T460
Test name
Test status
Simulation time 195903043 ps
CPU time 2.99 seconds
Started Jul 05 05:29:08 PM PDT 24
Finished Jul 05 05:29:11 PM PDT 24
Peak memory 217724 kb
Host smart-efdca4a5-7df6-4053-80f7-667014bb2cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407005384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.407005384
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1147972579
Short name T540
Test name
Test status
Simulation time 481043333 ps
CPU time 32.7 seconds
Started Jul 05 05:29:12 PM PDT 24
Finished Jul 05 05:29:46 PM PDT 24
Peak memory 250952 kb
Host smart-92138be4-b85a-4ffd-901d-6a1dc9665325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147972579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1147972579
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.3122283084
Short name T643
Test name
Test status
Simulation time 265110847 ps
CPU time 6.46 seconds
Started Jul 05 05:29:09 PM PDT 24
Finished Jul 05 05:29:16 PM PDT 24
Peak memory 247068 kb
Host smart-d5c9afbe-6a54-4b8f-a9aa-59dcf7aec7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122283084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.3122283084
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1073188646
Short name T715
Test name
Test status
Simulation time 48292005789 ps
CPU time 277.46 seconds
Started Jul 05 05:29:11 PM PDT 24
Finished Jul 05 05:33:50 PM PDT 24
Peak memory 253996 kb
Host smart-4fa35b99-47f8-41f1-8f49-98785606be81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073188646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1073188646
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.4124668904
Short name T724
Test name
Test status
Simulation time 31110073 ps
CPU time 0.92 seconds
Started Jul 05 05:29:06 PM PDT 24
Finished Jul 05 05:29:08 PM PDT 24
Peak memory 211888 kb
Host smart-21d48be8-f2ca-4f2e-b2ff-4343e48848d5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124668904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.4124668904
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.1888191368
Short name T626
Test name
Test status
Simulation time 20273540 ps
CPU time 1.22 seconds
Started Jul 05 05:29:17 PM PDT 24
Finished Jul 05 05:29:19 PM PDT 24
Peak memory 209064 kb
Host smart-c21f5950-21f4-4fcb-a0e9-cf418c10a2f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888191368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.1888191368
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.2946329501
Short name T16
Test name
Test status
Simulation time 974730452 ps
CPU time 20.12 seconds
Started Jul 05 05:29:10 PM PDT 24
Finished Jul 05 05:29:30 PM PDT 24
Peak memory 218176 kb
Host smart-031994b7-e464-4fe1-9a0a-81f6b67bd4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946329501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2946329501
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1542341516
Short name T181
Test name
Test status
Simulation time 624102982 ps
CPU time 15.56 seconds
Started Jul 05 05:29:12 PM PDT 24
Finished Jul 05 05:29:28 PM PDT 24
Peak memory 217364 kb
Host smart-50586179-3b18-41ee-942e-767be8313f01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542341516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1542341516
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.4204542059
Short name T785
Test name
Test status
Simulation time 129805358 ps
CPU time 3.48 seconds
Started Jul 05 05:29:13 PM PDT 24
Finished Jul 05 05:29:17 PM PDT 24
Peak memory 222652 kb
Host smart-bd835278-15dd-4cfb-ad19-31789a7d4667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204542059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.4204542059
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.579736138
Short name T445
Test name
Test status
Simulation time 1430449252 ps
CPU time 11.88 seconds
Started Jul 05 05:29:10 PM PDT 24
Finished Jul 05 05:29:22 PM PDT 24
Peak memory 226024 kb
Host smart-62ed234b-c09e-4a8d-aa9f-5839c520fbca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579736138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_di
gest.579736138
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.1181923227
Short name T786
Test name
Test status
Simulation time 2501831412 ps
CPU time 13.08 seconds
Started Jul 05 05:29:10 PM PDT 24
Finished Jul 05 05:29:23 PM PDT 24
Peak memory 226104 kb
Host smart-02ee87f8-25a8-4136-8642-9eb2cd50e66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181923227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1181923227
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.4034578214
Short name T479
Test name
Test status
Simulation time 37895179 ps
CPU time 2.68 seconds
Started Jul 05 05:29:12 PM PDT 24
Finished Jul 05 05:29:16 PM PDT 24
Peak memory 214072 kb
Host smart-29cebd76-f964-472f-acc2-10d4662a052c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034578214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.4034578214
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3158347758
Short name T754
Test name
Test status
Simulation time 315095927 ps
CPU time 33.24 seconds
Started Jul 05 05:29:10 PM PDT 24
Finished Jul 05 05:29:44 PM PDT 24
Peak memory 250992 kb
Host smart-59bfbd27-394c-4ccf-bc93-715574b9ce28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158347758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3158347758
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3313446190
Short name T485
Test name
Test status
Simulation time 60361909 ps
CPU time 6.94 seconds
Started Jul 05 05:29:11 PM PDT 24
Finished Jul 05 05:29:19 PM PDT 24
Peak memory 244488 kb
Host smart-a279a90b-2afe-4201-b150-759ec5f6e265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313446190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3313446190
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.1632692658
Short name T816
Test name
Test status
Simulation time 7136689535 ps
CPU time 40.63 seconds
Started Jul 05 05:29:12 PM PDT 24
Finished Jul 05 05:29:54 PM PDT 24
Peak memory 251044 kb
Host smart-0fd70b23-5137-4de1-b344-90c9625d7729
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632692658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.1632692658
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3528515982
Short name T345
Test name
Test status
Simulation time 15289261 ps
CPU time 1.1 seconds
Started Jul 05 05:29:11 PM PDT 24
Finished Jul 05 05:29:13 PM PDT 24
Peak memory 211900 kb
Host smart-3f4cc2c2-d4e1-4196-8b16-8122b72c25fc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528515982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.3528515982
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.4036021709
Short name T100
Test name
Test status
Simulation time 30359840 ps
CPU time 0.92 seconds
Started Jul 05 05:29:24 PM PDT 24
Finished Jul 05 05:29:27 PM PDT 24
Peak memory 208952 kb
Host smart-fa05f79e-a428-4911-8072-1470bb5620e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036021709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.4036021709
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3733230669
Short name T554
Test name
Test status
Simulation time 937954928 ps
CPU time 10.64 seconds
Started Jul 05 05:29:19 PM PDT 24
Finished Jul 05 05:29:32 PM PDT 24
Peak memory 226048 kb
Host smart-a47e5a39-1f78-42f4-b7cb-a3ad007a5c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733230669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3733230669
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.4257104039
Short name T318
Test name
Test status
Simulation time 74219887 ps
CPU time 1.41 seconds
Started Jul 05 05:29:18 PM PDT 24
Finished Jul 05 05:29:20 PM PDT 24
Peak memory 217100 kb
Host smart-4c5061fa-39fb-4e75-9205-11e3665320e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257104039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.4257104039
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.3248691048
Short name T417
Test name
Test status
Simulation time 46093664 ps
CPU time 1.94 seconds
Started Jul 05 05:29:19 PM PDT 24
Finished Jul 05 05:29:23 PM PDT 24
Peak memory 218244 kb
Host smart-826a3ea2-d219-48dc-b0c1-e61c49541d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248691048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3248691048
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3560173689
Short name T239
Test name
Test status
Simulation time 1098939365 ps
CPU time 11.05 seconds
Started Jul 05 05:29:22 PM PDT 24
Finished Jul 05 05:29:35 PM PDT 24
Peak memory 225968 kb
Host smart-d3b2f024-201b-4fcc-948e-0c1eb4299895
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560173689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.3560173689
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3737383399
Short name T312
Test name
Test status
Simulation time 557044991 ps
CPU time 8.87 seconds
Started Jul 05 05:29:18 PM PDT 24
Finished Jul 05 05:29:28 PM PDT 24
Peak memory 218252 kb
Host smart-cb8e2f18-26f4-44d1-8df1-0d3a7ca32ada
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737383399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3737383399
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.884777102
Short name T745
Test name
Test status
Simulation time 525947163 ps
CPU time 10.13 seconds
Started Jul 05 05:29:19 PM PDT 24
Finished Jul 05 05:29:30 PM PDT 24
Peak memory 225936 kb
Host smart-d0190123-1cb3-4ce5-b4f9-97c55afd54c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884777102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.884777102
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2163033937
Short name T633
Test name
Test status
Simulation time 84085141 ps
CPU time 3.07 seconds
Started Jul 05 05:29:18 PM PDT 24
Finished Jul 05 05:29:21 PM PDT 24
Peak memory 214864 kb
Host smart-9c7da020-156e-4bff-9af5-1e2a912d415e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163033937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2163033937
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.2088426668
Short name T849
Test name
Test status
Simulation time 293220194 ps
CPU time 22.41 seconds
Started Jul 05 05:29:27 PM PDT 24
Finished Jul 05 05:29:52 PM PDT 24
Peak memory 250796 kb
Host smart-2678d869-27d6-4bd0-be44-c3b6514b977d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088426668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2088426668
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2442966199
Short name T807
Test name
Test status
Simulation time 2309303126 ps
CPU time 9.68 seconds
Started Jul 05 05:29:23 PM PDT 24
Finished Jul 05 05:29:35 PM PDT 24
Peak memory 250972 kb
Host smart-6d916f9c-bf9a-4b7c-b6d5-2df2c3bc5c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442966199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2442966199
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.1741682647
Short name T493
Test name
Test status
Simulation time 6430942141 ps
CPU time 31.2 seconds
Started Jul 05 05:29:17 PM PDT 24
Finished Jul 05 05:29:49 PM PDT 24
Peak memory 220240 kb
Host smart-dc78bae7-f0ab-4b4a-be22-3d73a57f74c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741682647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.1741682647
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.433689945
Short name T536
Test name
Test status
Simulation time 44857760 ps
CPU time 0.96 seconds
Started Jul 05 05:29:28 PM PDT 24
Finished Jul 05 05:29:32 PM PDT 24
Peak memory 211760 kb
Host smart-297c5aed-bc47-4e8a-882f-535602bba7ff
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433689945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ct
rl_volatile_unlock_smoke.433689945
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.3421328079
Short name T302
Test name
Test status
Simulation time 28030309 ps
CPU time 1.43 seconds
Started Jul 05 05:29:20 PM PDT 24
Finished Jul 05 05:29:23 PM PDT 24
Peak memory 209040 kb
Host smart-c4784868-c9bf-491d-8154-f7ff21cc4604
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421328079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.3421328079
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3390786632
Short name T796
Test name
Test status
Simulation time 2645548725 ps
CPU time 10.08 seconds
Started Jul 05 05:29:19 PM PDT 24
Finished Jul 05 05:29:31 PM PDT 24
Peak memory 218228 kb
Host smart-668ae41b-45ed-432a-8074-3d4311b6f4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390786632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3390786632
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2762473048
Short name T820
Test name
Test status
Simulation time 43039785 ps
CPU time 1.83 seconds
Started Jul 05 05:29:20 PM PDT 24
Finished Jul 05 05:29:24 PM PDT 24
Peak memory 217584 kb
Host smart-17e8fd93-bb73-4a75-9304-29a7418448de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762473048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2762473048
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.2433788138
Short name T815
Test name
Test status
Simulation time 63569086 ps
CPU time 2.9 seconds
Started Jul 05 05:29:20 PM PDT 24
Finished Jul 05 05:29:25 PM PDT 24
Peak memory 218456 kb
Host smart-7b39411f-3bc5-428a-bcfc-36fd408d8b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433788138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.2433788138
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.2939952231
Short name T505
Test name
Test status
Simulation time 217906505 ps
CPU time 9.98 seconds
Started Jul 05 05:29:18 PM PDT 24
Finished Jul 05 05:29:29 PM PDT 24
Peak memory 225936 kb
Host smart-dc6f271d-fddd-41ba-b85e-29765d49ba1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939952231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.2939952231
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1419023371
Short name T241
Test name
Test status
Simulation time 296342221 ps
CPU time 14.13 seconds
Started Jul 05 05:29:20 PM PDT 24
Finished Jul 05 05:29:36 PM PDT 24
Peak memory 218244 kb
Host smart-3587fd9c-f2f7-46f2-87f6-5d90a7e01252
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419023371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1419023371
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.2667965995
Short name T305
Test name
Test status
Simulation time 1141265286 ps
CPU time 7.82 seconds
Started Jul 05 05:29:20 PM PDT 24
Finished Jul 05 05:29:30 PM PDT 24
Peak memory 218248 kb
Host smart-a20fa575-08d0-4986-b100-e40f875ab059
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667965995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
2667965995
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.132283086
Short name T461
Test name
Test status
Simulation time 1016989237 ps
CPU time 12.36 seconds
Started Jul 05 05:29:18 PM PDT 24
Finished Jul 05 05:29:32 PM PDT 24
Peak memory 218188 kb
Host smart-adc8732f-25ba-4fdb-b194-208e527f0db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132283086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.132283086
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.4028568477
Short name T419
Test name
Test status
Simulation time 76835748 ps
CPU time 1.82 seconds
Started Jul 05 05:29:20 PM PDT 24
Finished Jul 05 05:29:23 PM PDT 24
Peak memory 213968 kb
Host smart-4ba9b899-21bf-4098-bdc3-0d61cd0a70ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028568477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.4028568477
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.2151140182
Short name T615
Test name
Test status
Simulation time 477440410 ps
CPU time 28.7 seconds
Started Jul 05 05:29:19 PM PDT 24
Finished Jul 05 05:29:49 PM PDT 24
Peak memory 250876 kb
Host smart-c4b3205a-1498-4047-a509-2e8c7a423538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151140182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2151140182
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.851832131
Short name T538
Test name
Test status
Simulation time 337881992 ps
CPU time 7.09 seconds
Started Jul 05 05:29:18 PM PDT 24
Finished Jul 05 05:29:27 PM PDT 24
Peak memory 250984 kb
Host smart-3f617ec8-0501-4232-a630-febe3e48b39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851832131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.851832131
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.3847114151
Short name T797
Test name
Test status
Simulation time 20680687375 ps
CPU time 170.17 seconds
Started Jul 05 05:29:19 PM PDT 24
Finished Jul 05 05:32:11 PM PDT 24
Peak memory 251040 kb
Host smart-3ab1cbe1-e1df-4a84-bc33-e3b2a404e698
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847114151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.3847114151
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.706083783
Short name T809
Test name
Test status
Simulation time 45183403 ps
CPU time 0.84 seconds
Started Jul 05 05:29:20 PM PDT 24
Finished Jul 05 05:29:23 PM PDT 24
Peak memory 212136 kb
Host smart-26c3a5a8-e663-4e25-9a07-19180a64cef3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706083783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct
rl_volatile_unlock_smoke.706083783
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1114248400
Short name T706
Test name
Test status
Simulation time 22612145 ps
CPU time 0.96 seconds
Started Jul 05 05:27:46 PM PDT 24
Finished Jul 05 05:27:48 PM PDT 24
Peak memory 209060 kb
Host smart-dacf5c44-80b3-4006-90eb-7fd526163ebf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114248400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1114248400
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3601124229
Short name T430
Test name
Test status
Simulation time 13705189 ps
CPU time 0.84 seconds
Started Jul 05 05:28:08 PM PDT 24
Finished Jul 05 05:28:10 PM PDT 24
Peak memory 208720 kb
Host smart-43995528-73ba-4691-9a1d-2bf102704100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601124229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3601124229
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2522285035
Short name T604
Test name
Test status
Simulation time 1565493545 ps
CPU time 17.97 seconds
Started Jul 05 05:27:40 PM PDT 24
Finished Jul 05 05:28:00 PM PDT 24
Peak memory 225924 kb
Host smart-8528bc18-8620-4fd8-8495-745049da4675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522285035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2522285035
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3880747631
Short name T379
Test name
Test status
Simulation time 6906960926 ps
CPU time 5.17 seconds
Started Jul 05 05:27:44 PM PDT 24
Finished Jul 05 05:27:50 PM PDT 24
Peak memory 217688 kb
Host smart-7a16dc87-6d6e-4597-9da7-cde2ebe85c74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880747631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3880747631
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.1234718835
Short name T489
Test name
Test status
Simulation time 6337836014 ps
CPU time 20.88 seconds
Started Jul 05 05:27:45 PM PDT 24
Finished Jul 05 05:28:07 PM PDT 24
Peak memory 218872 kb
Host smart-e7782c37-af1d-4761-ba43-654142d272c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234718835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.1234718835
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1969850357
Short name T266
Test name
Test status
Simulation time 364640305 ps
CPU time 10.7 seconds
Started Jul 05 05:27:46 PM PDT 24
Finished Jul 05 05:27:58 PM PDT 24
Peak memory 222980 kb
Host smart-2648156c-85d1-45c8-9067-e568d60f4ee7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969850357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1969850357
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1370690347
Short name T373
Test name
Test status
Simulation time 827377428 ps
CPU time 12.06 seconds
Started Jul 05 05:27:44 PM PDT 24
Finished Jul 05 05:27:56 PM PDT 24
Peak memory 217696 kb
Host smart-69da9828-1ef7-4c20-be05-eb71cc4b2c90
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370690347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1370690347
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.4191531360
Short name T584
Test name
Test status
Simulation time 658577329 ps
CPU time 8.73 seconds
Started Jul 05 05:27:45 PM PDT 24
Finished Jul 05 05:27:55 PM PDT 24
Peak memory 217712 kb
Host smart-8356838e-623e-45c3-804b-278ad635d741
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191531360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
4191531360
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1259520324
Short name T424
Test name
Test status
Simulation time 25607293702 ps
CPU time 73.96 seconds
Started Jul 05 05:27:47 PM PDT 24
Finished Jul 05 05:29:01 PM PDT 24
Peak memory 268736 kb
Host smart-ca435dd6-f447-4ab3-a798-1278f10bb469
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259520324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.1259520324
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.3002103279
Short name T175
Test name
Test status
Simulation time 527306128 ps
CPU time 16.28 seconds
Started Jul 05 05:27:46 PM PDT 24
Finished Jul 05 05:28:03 PM PDT 24
Peak memory 250948 kb
Host smart-52bee512-e326-4dfb-9f16-9e541594cc3f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002103279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.3002103279
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1294349812
Short name T186
Test name
Test status
Simulation time 546523984 ps
CPU time 2.78 seconds
Started Jul 05 05:27:40 PM PDT 24
Finished Jul 05 05:27:45 PM PDT 24
Peak memory 218116 kb
Host smart-878b509b-223d-4975-9736-73c0e7b4745b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294349812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1294349812
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.4024862020
Short name T207
Test name
Test status
Simulation time 1220882176 ps
CPU time 17.53 seconds
Started Jul 05 05:27:40 PM PDT 24
Finished Jul 05 05:28:00 PM PDT 24
Peak memory 217740 kb
Host smart-aef7fe1b-c7e6-4d52-a437-91d139f17a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024862020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.4024862020
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1802508202
Short name T88
Test name
Test status
Simulation time 731243668 ps
CPU time 25.52 seconds
Started Jul 05 05:27:45 PM PDT 24
Finished Jul 05 05:28:12 PM PDT 24
Peak memory 267880 kb
Host smart-54c2644a-cb3b-47f6-af46-c820df978dc6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802508202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1802508202
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.4081736515
Short name T859
Test name
Test status
Simulation time 483544824 ps
CPU time 12.06 seconds
Started Jul 05 05:27:47 PM PDT 24
Finished Jul 05 05:28:00 PM PDT 24
Peak memory 226044 kb
Host smart-6cdc60cf-20bb-4ae5-ba13-680957aa43d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081736515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.4081736515
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.4022062807
Short name T443
Test name
Test status
Simulation time 3865427823 ps
CPU time 9.82 seconds
Started Jul 05 05:27:44 PM PDT 24
Finished Jul 05 05:27:55 PM PDT 24
Peak memory 226104 kb
Host smart-f8714724-e544-41c1-86b8-252218e74b99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022062807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.4
022062807
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.1682668486
Short name T329
Test name
Test status
Simulation time 4152070492 ps
CPU time 10.06 seconds
Started Jul 05 05:27:41 PM PDT 24
Finished Jul 05 05:27:53 PM PDT 24
Peak memory 226108 kb
Host smart-0008fd10-3cec-481c-a212-3982e5b31a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682668486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1682668486
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.2132922507
Short name T543
Test name
Test status
Simulation time 55787732 ps
CPU time 2.46 seconds
Started Jul 05 05:27:38 PM PDT 24
Finished Jul 05 05:27:44 PM PDT 24
Peak memory 214692 kb
Host smart-fd4acfa1-5d01-4621-bfde-5f37c59d8d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132922507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2132922507
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.2815234887
Short name T635
Test name
Test status
Simulation time 290609294 ps
CPU time 23.84 seconds
Started Jul 05 05:27:44 PM PDT 24
Finished Jul 05 05:28:08 PM PDT 24
Peak memory 250992 kb
Host smart-8b35b7c4-4181-4be0-9a34-6c9760bc988e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815234887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2815234887
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.3720602389
Short name T85
Test name
Test status
Simulation time 65834339 ps
CPU time 3.55 seconds
Started Jul 05 05:27:44 PM PDT 24
Finished Jul 05 05:27:48 PM PDT 24
Peak memory 222156 kb
Host smart-577548fb-0eb3-4263-9cc5-b9875c93f99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720602389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3720602389
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1611151296
Short name T366
Test name
Test status
Simulation time 43546121092 ps
CPU time 97.7 seconds
Started Jul 05 05:27:48 PM PDT 24
Finished Jul 05 05:29:26 PM PDT 24
Peak memory 283816 kb
Host smart-a658b047-34ef-4d55-aa38-6bb3873ac708
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611151296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1611151296
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2505258059
Short name T376
Test name
Test status
Simulation time 12014363 ps
CPU time 1.01 seconds
Started Jul 05 05:27:41 PM PDT 24
Finished Jul 05 05:27:44 PM PDT 24
Peak memory 211868 kb
Host smart-2588ecde-01d6-4f7a-9928-016590aa8b00
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505258059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2505258059
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1248553890
Short name T725
Test name
Test status
Simulation time 15472515 ps
CPU time 1.07 seconds
Started Jul 05 05:29:27 PM PDT 24
Finished Jul 05 05:29:32 PM PDT 24
Peak memory 209060 kb
Host smart-5f48728f-f608-4177-9979-3db6566d5005
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248553890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1248553890
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.3276226048
Short name T453
Test name
Test status
Simulation time 321707635 ps
CPU time 9.07 seconds
Started Jul 05 05:29:19 PM PDT 24
Finished Jul 05 05:29:30 PM PDT 24
Peak memory 218236 kb
Host smart-5241b103-7d76-4690-a54a-958c16091d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276226048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3276226048
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.1036835505
Short name T6
Test name
Test status
Simulation time 1673496417 ps
CPU time 5.97 seconds
Started Jul 05 05:29:20 PM PDT 24
Finished Jul 05 05:29:28 PM PDT 24
Peak memory 217648 kb
Host smart-afd423be-a44d-4324-b05f-3919e037d590
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036835505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.1036835505
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.1658473655
Short name T839
Test name
Test status
Simulation time 551122202 ps
CPU time 3.09 seconds
Started Jul 05 05:29:22 PM PDT 24
Finished Jul 05 05:29:27 PM PDT 24
Peak memory 218208 kb
Host smart-5d906059-40b4-4c49-a349-fd1a1dcdde85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658473655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.1658473655
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.123833262
Short name T660
Test name
Test status
Simulation time 286443383 ps
CPU time 12.3 seconds
Started Jul 05 05:29:19 PM PDT 24
Finished Jul 05 05:29:32 PM PDT 24
Peak memory 226044 kb
Host smart-9da925fd-9fe7-46be-b7c9-8c2e34fa40cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123833262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.123833262
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.4054424932
Short name T744
Test name
Test status
Simulation time 184482153 ps
CPU time 8.4 seconds
Started Jul 05 05:29:18 PM PDT 24
Finished Jul 05 05:29:27 PM PDT 24
Peak memory 226004 kb
Host smart-fde94941-6d44-48a5-9e47-4f40a854b61d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054424932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.4054424932
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.429260943
Short name T385
Test name
Test status
Simulation time 4103371742 ps
CPU time 10.77 seconds
Started Jul 05 05:29:28 PM PDT 24
Finished Jul 05 05:29:42 PM PDT 24
Peak memory 218772 kb
Host smart-0f9f4bc8-04ad-4fc4-b086-af46c63fe72a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429260943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.429260943
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.3947928029
Short name T184
Test name
Test status
Simulation time 1804466550 ps
CPU time 10.05 seconds
Started Jul 05 05:29:20 PM PDT 24
Finished Jul 05 05:29:32 PM PDT 24
Peak memory 226044 kb
Host smart-b9999353-7a96-4987-9960-2847a6509277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947928029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3947928029
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.3984473273
Short name T841
Test name
Test status
Simulation time 1071733180 ps
CPU time 2.43 seconds
Started Jul 05 05:29:28 PM PDT 24
Finished Jul 05 05:29:34 PM PDT 24
Peak memory 214556 kb
Host smart-ac55e678-52e5-4d82-b662-362195926bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984473273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3984473273
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.1772141665
Short name T845
Test name
Test status
Simulation time 307380019 ps
CPU time 26.42 seconds
Started Jul 05 05:29:27 PM PDT 24
Finished Jul 05 05:29:57 PM PDT 24
Peak memory 250780 kb
Host smart-8fe7ff67-3e2d-4e21-8678-0822d91afb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772141665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.1772141665
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.4197729787
Short name T414
Test name
Test status
Simulation time 156792970 ps
CPU time 7.32 seconds
Started Jul 05 05:29:19 PM PDT 24
Finished Jul 05 05:29:27 PM PDT 24
Peak memory 246724 kb
Host smart-e6f03528-2540-4d34-b7bd-0004428e1d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197729787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.4197729787
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.2372937811
Short name T663
Test name
Test status
Simulation time 14667062222 ps
CPU time 235.79 seconds
Started Jul 05 05:29:27 PM PDT 24
Finished Jul 05 05:33:27 PM PDT 24
Peak memory 289612 kb
Host smart-33d0e116-14b6-4fd5-8f6a-281416021392
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372937811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.2372937811
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2171967024
Short name T668
Test name
Test status
Simulation time 15628093 ps
CPU time 0.88 seconds
Started Jul 05 05:29:20 PM PDT 24
Finished Jul 05 05:29:23 PM PDT 24
Peak memory 211888 kb
Host smart-e5fa784e-68ca-4400-bd52-a9ee4621ab6d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171967024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.2171967024
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.1596601883
Short name T308
Test name
Test status
Simulation time 25705261 ps
CPU time 0.98 seconds
Started Jul 05 05:29:26 PM PDT 24
Finished Jul 05 05:29:30 PM PDT 24
Peak memory 208960 kb
Host smart-bc6ca45b-d9f3-4b6e-936d-c2cbf3871b43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596601883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1596601883
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.70575503
Short name T500
Test name
Test status
Simulation time 2361884444 ps
CPU time 14.15 seconds
Started Jul 05 05:29:29 PM PDT 24
Finished Jul 05 05:29:46 PM PDT 24
Peak memory 218880 kb
Host smart-32c5c544-4488-40fa-875e-79c3831832a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70575503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.70575503
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3345010290
Short name T729
Test name
Test status
Simulation time 422821971 ps
CPU time 5.68 seconds
Started Jul 05 05:29:29 PM PDT 24
Finished Jul 05 05:29:38 PM PDT 24
Peak memory 217108 kb
Host smart-94ba2f24-5996-4553-9d6e-611425093bbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345010290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3345010290
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.2020831874
Short name T851
Test name
Test status
Simulation time 68803164 ps
CPU time 3 seconds
Started Jul 05 05:29:27 PM PDT 24
Finished Jul 05 05:29:33 PM PDT 24
Peak memory 218228 kb
Host smart-d9eda833-7df9-45ee-9b63-59cc79eaa470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020831874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.2020831874
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.4196789262
Short name T787
Test name
Test status
Simulation time 246186327 ps
CPU time 12.22 seconds
Started Jul 05 05:29:26 PM PDT 24
Finished Jul 05 05:29:41 PM PDT 24
Peak memory 218928 kb
Host smart-066ed4f8-67d8-4f8e-ad05-d7da5b99be01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196789262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.4196789262
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1009981045
Short name T788
Test name
Test status
Simulation time 1930750286 ps
CPU time 16.79 seconds
Started Jul 05 05:29:28 PM PDT 24
Finished Jul 05 05:29:48 PM PDT 24
Peak memory 225944 kb
Host smart-70b32298-9463-4fb8-b1a5-7b413f909d8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009981045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.1009981045
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1492912897
Short name T195
Test name
Test status
Simulation time 216391588 ps
CPU time 8.09 seconds
Started Jul 05 05:29:31 PM PDT 24
Finished Jul 05 05:29:41 PM PDT 24
Peak memory 218248 kb
Host smart-3710b916-41a9-4cfe-99ca-fc29d0144847
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492912897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
1492912897
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.3962558422
Short name T507
Test name
Test status
Simulation time 635992764 ps
CPU time 14.23 seconds
Started Jul 05 05:29:29 PM PDT 24
Finished Jul 05 05:29:46 PM PDT 24
Peak memory 225968 kb
Host smart-2f0b1466-4a2f-4b35-9208-e84aba0eda38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962558422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3962558422
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3976524582
Short name T765
Test name
Test status
Simulation time 77104640 ps
CPU time 1.32 seconds
Started Jul 05 05:29:28 PM PDT 24
Finished Jul 05 05:29:33 PM PDT 24
Peak memory 217840 kb
Host smart-b4cc33e8-7203-424a-b91a-8927a7e75f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976524582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3976524582
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.3485921625
Short name T638
Test name
Test status
Simulation time 197846681 ps
CPU time 23.67 seconds
Started Jul 05 05:29:28 PM PDT 24
Finished Jul 05 05:29:55 PM PDT 24
Peak memory 250988 kb
Host smart-78dc2bec-adaf-4a77-9c89-4234122dacd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485921625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.3485921625
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3647160221
Short name T261
Test name
Test status
Simulation time 94778034 ps
CPU time 5.96 seconds
Started Jul 05 05:29:28 PM PDT 24
Finished Jul 05 05:29:37 PM PDT 24
Peak memory 250416 kb
Host smart-0e11fc08-ded8-4d33-b21b-180881677832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647160221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3647160221
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.2233484173
Short name T694
Test name
Test status
Simulation time 302185443 ps
CPU time 10.7 seconds
Started Jul 05 05:29:29 PM PDT 24
Finished Jul 05 05:29:43 PM PDT 24
Peak memory 226052 kb
Host smart-d5967475-dd3a-443e-97b9-172b74c11902
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233484173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.2233484173
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2855686909
Short name T713
Test name
Test status
Simulation time 14951679 ps
CPU time 1.06 seconds
Started Jul 05 05:29:27 PM PDT 24
Finished Jul 05 05:29:31 PM PDT 24
Peak memory 212012 kb
Host smart-01feb27f-2215-4d76-a3a2-b61f0bf99611
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855686909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2855686909
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.2570284239
Short name T654
Test name
Test status
Simulation time 59465147 ps
CPU time 0.95 seconds
Started Jul 05 05:29:28 PM PDT 24
Finished Jul 05 05:29:33 PM PDT 24
Peak memory 208912 kb
Host smart-0cc20e80-2ad5-432c-968d-f9916ab8c8f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570284239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.2570284239
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.1743325373
Short name T435
Test name
Test status
Simulation time 551619733 ps
CPU time 12.34 seconds
Started Jul 05 05:29:27 PM PDT 24
Finished Jul 05 05:29:43 PM PDT 24
Peak memory 218192 kb
Host smart-48bfa305-fef1-4807-b54b-4df98ecf7b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743325373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.1743325373
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.1266337186
Short name T669
Test name
Test status
Simulation time 126430795 ps
CPU time 4.16 seconds
Started Jul 05 05:29:28 PM PDT 24
Finished Jul 05 05:29:36 PM PDT 24
Peak memory 217068 kb
Host smart-a499713a-9110-474e-b93f-164497c2a150
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266337186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.1266337186
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.1793350147
Short name T377
Test name
Test status
Simulation time 299125042 ps
CPU time 3.71 seconds
Started Jul 05 05:29:28 PM PDT 24
Finished Jul 05 05:29:35 PM PDT 24
Peak memory 218256 kb
Host smart-f319d532-9e32-4995-9ecb-1eafb0a6ec08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793350147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1793350147
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.534511101
Short name T826
Test name
Test status
Simulation time 671119112 ps
CPU time 10.31 seconds
Started Jul 05 05:29:29 PM PDT 24
Finished Jul 05 05:29:42 PM PDT 24
Peak memory 225988 kb
Host smart-1a08a911-cd99-4018-b8ab-108b84d7439c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534511101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.534511101
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2960519888
Short name T857
Test name
Test status
Simulation time 379624789 ps
CPU time 15.08 seconds
Started Jul 05 05:29:26 PM PDT 24
Finished Jul 05 05:29:44 PM PDT 24
Peak memory 226052 kb
Host smart-888399d0-bc2d-40ef-ad92-e7accbf5ca9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960519888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2960519888
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.2289279505
Short name T444
Test name
Test status
Simulation time 369280480 ps
CPU time 11.05 seconds
Started Jul 05 05:29:27 PM PDT 24
Finished Jul 05 05:29:41 PM PDT 24
Peak memory 226044 kb
Host smart-a3ace96d-8655-4121-a974-255aef21802f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289279505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
2289279505
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.9992475
Short name T835
Test name
Test status
Simulation time 3466046850 ps
CPU time 10.95 seconds
Started Jul 05 05:29:29 PM PDT 24
Finished Jul 05 05:29:43 PM PDT 24
Peak memory 226096 kb
Host smart-819a51ca-765f-4ad7-bb84-e3c1b93198d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9992475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.9992475
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.4145696670
Short name T855
Test name
Test status
Simulation time 144963617 ps
CPU time 2.45 seconds
Started Jul 05 05:29:27 PM PDT 24
Finished Jul 05 05:29:32 PM PDT 24
Peak memory 214792 kb
Host smart-7037d1f0-fafe-49c8-82bf-03254fc2f701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145696670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.4145696670
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.629029760
Short name T371
Test name
Test status
Simulation time 1205268847 ps
CPU time 21.53 seconds
Started Jul 05 05:29:29 PM PDT 24
Finished Jul 05 05:29:54 PM PDT 24
Peak memory 250980 kb
Host smart-ea139bb4-f7df-4221-a77b-b266ccee635e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629029760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.629029760
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.3169406854
Short name T494
Test name
Test status
Simulation time 385316702 ps
CPU time 10.22 seconds
Started Jul 05 05:29:31 PM PDT 24
Finished Jul 05 05:29:43 PM PDT 24
Peak memory 250980 kb
Host smart-deaa4a84-46b6-446c-8ac6-f507982fb573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169406854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3169406854
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1419596503
Short name T799
Test name
Test status
Simulation time 3528445246 ps
CPU time 109.75 seconds
Started Jul 05 05:29:29 PM PDT 24
Finished Jul 05 05:31:22 PM PDT 24
Peak memory 273616 kb
Host smart-22668fbe-e751-4385-8c81-3f5578bd1b37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419596503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1419596503
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.4003712731
Short name T103
Test name
Test status
Simulation time 29044559185 ps
CPU time 907.84 seconds
Started Jul 05 05:29:32 PM PDT 24
Finished Jul 05 05:44:41 PM PDT 24
Peak memory 405768 kb
Host smart-a1d37a90-6d6f-4564-b759-35de54b08103
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4003712731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.4003712731
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2131437342
Short name T594
Test name
Test status
Simulation time 187172584 ps
CPU time 0.83 seconds
Started Jul 05 05:29:30 PM PDT 24
Finished Jul 05 05:29:33 PM PDT 24
Peak memory 211988 kb
Host smart-86578495-4b81-4d7a-b0e7-65deb7615b2e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131437342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.2131437342
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.604626700
Short name T368
Test name
Test status
Simulation time 68328717 ps
CPU time 0.95 seconds
Started Jul 05 05:29:36 PM PDT 24
Finished Jul 05 05:29:38 PM PDT 24
Peak memory 209060 kb
Host smart-3f45b027-21e8-4df9-8ff6-38fd6f0e05a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604626700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.604626700
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.1344472324
Short name T717
Test name
Test status
Simulation time 261471630 ps
CPU time 11.94 seconds
Started Jul 05 05:29:37 PM PDT 24
Finished Jul 05 05:29:50 PM PDT 24
Peak memory 218236 kb
Host smart-090575b4-c693-4433-b114-f5711ed4c4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344472324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1344472324
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.2339629514
Short name T356
Test name
Test status
Simulation time 207422496 ps
CPU time 1.97 seconds
Started Jul 05 05:29:35 PM PDT 24
Finished Jul 05 05:29:37 PM PDT 24
Peak memory 217036 kb
Host smart-204f9dae-eb76-4729-8b8f-fcaf1dd4a2da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339629514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.2339629514
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2290682343
Short name T825
Test name
Test status
Simulation time 71345907 ps
CPU time 2.56 seconds
Started Jul 05 05:29:37 PM PDT 24
Finished Jul 05 05:29:41 PM PDT 24
Peak memory 218172 kb
Host smart-f275e8b1-a921-4c51-b3d7-4149bfae64fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290682343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2290682343
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.2507465714
Short name T170
Test name
Test status
Simulation time 485222953 ps
CPU time 14.95 seconds
Started Jul 05 05:29:39 PM PDT 24
Finished Jul 05 05:29:55 PM PDT 24
Peak memory 218820 kb
Host smart-96c7bdf4-78cd-4fec-ba44-7ae81f57700a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507465714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2507465714
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.4105024053
Short name T297
Test name
Test status
Simulation time 1367763432 ps
CPU time 9.55 seconds
Started Jul 05 05:29:36 PM PDT 24
Finished Jul 05 05:29:47 PM PDT 24
Peak memory 226044 kb
Host smart-ccf6ff36-c6b7-495b-be37-4c28d71627cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105024053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.4105024053
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.1719223820
Short name T253
Test name
Test status
Simulation time 1217850645 ps
CPU time 7.88 seconds
Started Jul 05 05:29:38 PM PDT 24
Finished Jul 05 05:29:47 PM PDT 24
Peak memory 225968 kb
Host smart-1b129740-e58d-4c1d-a6a9-6497c47cad12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719223820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
1719223820
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.1736809078
Short name T794
Test name
Test status
Simulation time 1579350797 ps
CPU time 9.41 seconds
Started Jul 05 05:29:39 PM PDT 24
Finished Jul 05 05:29:49 PM PDT 24
Peak memory 226044 kb
Host smart-dcbbb394-1560-414e-a1be-7ba5908fb66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736809078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.1736809078
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.1203973522
Short name T670
Test name
Test status
Simulation time 22222029 ps
CPU time 1.04 seconds
Started Jul 05 05:29:27 PM PDT 24
Finished Jul 05 05:29:31 PM PDT 24
Peak memory 212204 kb
Host smart-a27ad8cc-a7f2-4871-abb6-e52b51748a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203973522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1203973522
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.4072119935
Short name T733
Test name
Test status
Simulation time 1011578670 ps
CPU time 22.55 seconds
Started Jul 05 05:29:33 PM PDT 24
Finished Jul 05 05:29:56 PM PDT 24
Peak memory 250964 kb
Host smart-c7bff9d9-d81b-4d14-8ffd-1b377662520f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072119935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.4072119935
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.2583359807
Short name T632
Test name
Test status
Simulation time 375610251 ps
CPU time 7.94 seconds
Started Jul 05 05:29:27 PM PDT 24
Finished Jul 05 05:29:38 PM PDT 24
Peak memory 247380 kb
Host smart-971c8131-2a04-44e2-a03e-73cb43ef319a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583359807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2583359807
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.2944741496
Short name T363
Test name
Test status
Simulation time 3961878190 ps
CPU time 82.63 seconds
Started Jul 05 05:29:37 PM PDT 24
Finished Jul 05 05:31:01 PM PDT 24
Peak memory 225988 kb
Host smart-1681ff21-41af-4234-97a3-b5e6556b380c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944741496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.2944741496
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.250042465
Short name T166
Test name
Test status
Simulation time 89293523622 ps
CPU time 1139.53 seconds
Started Jul 05 05:29:37 PM PDT 24
Finished Jul 05 05:48:38 PM PDT 24
Peak memory 287728 kb
Host smart-d7833e05-33b8-4fe0-a575-d98f379388b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=250042465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.250042465
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2569784878
Short name T394
Test name
Test status
Simulation time 31834208 ps
CPU time 0.87 seconds
Started Jul 05 05:29:26 PM PDT 24
Finished Jul 05 05:29:30 PM PDT 24
Peak memory 211752 kb
Host smart-629ed7d4-4826-49ef-9b00-d8038965da8e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569784878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.2569784878
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.3338479805
Short name T844
Test name
Test status
Simulation time 41606579 ps
CPU time 1.02 seconds
Started Jul 05 05:29:39 PM PDT 24
Finished Jul 05 05:29:40 PM PDT 24
Peak memory 208940 kb
Host smart-056c0da3-633a-499a-a24e-7b09e6abce30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338479805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3338479805
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2564575248
Short name T185
Test name
Test status
Simulation time 1096692744 ps
CPU time 14.46 seconds
Started Jul 05 05:29:36 PM PDT 24
Finished Jul 05 05:29:51 PM PDT 24
Peak memory 218296 kb
Host smart-1bb59b84-3eed-44df-92ec-d69695203d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564575248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2564575248
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.4145914502
Short name T770
Test name
Test status
Simulation time 1481043279 ps
CPU time 5.09 seconds
Started Jul 05 05:29:40 PM PDT 24
Finished Jul 05 05:29:45 PM PDT 24
Peak memory 217188 kb
Host smart-98f90b31-3be3-43f9-b0df-6fd39ded9fe8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145914502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.4145914502
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.282915393
Short name T306
Test name
Test status
Simulation time 28913763 ps
CPU time 1.86 seconds
Started Jul 05 05:29:37 PM PDT 24
Finished Jul 05 05:29:40 PM PDT 24
Peak memory 218220 kb
Host smart-73cb8940-9ffa-426f-bdcd-7fd69b6d3e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282915393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.282915393
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.315004427
Short name T644
Test name
Test status
Simulation time 349169125 ps
CPU time 16.2 seconds
Started Jul 05 05:29:37 PM PDT 24
Finished Jul 05 05:29:54 PM PDT 24
Peak memory 226104 kb
Host smart-77158946-df47-40f2-a8b0-b1d4fd2c214e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315004427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.315004427
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2438436661
Short name T776
Test name
Test status
Simulation time 254441440 ps
CPU time 11.12 seconds
Started Jul 05 05:29:39 PM PDT 24
Finished Jul 05 05:29:51 PM PDT 24
Peak memory 226048 kb
Host smart-ad5d3ada-5e48-491b-a7f5-27de513888e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438436661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.2438436661
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2433066022
Short name T686
Test name
Test status
Simulation time 508501911 ps
CPU time 9.18 seconds
Started Jul 05 05:29:37 PM PDT 24
Finished Jul 05 05:29:48 PM PDT 24
Peak memory 218168 kb
Host smart-9fa61cbb-bca9-4cd1-9d02-463f2379bac8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433066022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2433066022
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.1690280491
Short name T288
Test name
Test status
Simulation time 1500611359 ps
CPU time 14.56 seconds
Started Jul 05 05:29:37 PM PDT 24
Finished Jul 05 05:29:52 PM PDT 24
Peak memory 226116 kb
Host smart-439acb58-89a1-433e-90b8-5d51987cd02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690280491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.1690280491
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.4082397035
Short name T59
Test name
Test status
Simulation time 172926447 ps
CPU time 2.91 seconds
Started Jul 05 05:29:37 PM PDT 24
Finished Jul 05 05:29:41 PM PDT 24
Peak memory 214896 kb
Host smart-10e8a2d4-287f-4206-90fa-85b2d640b2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082397035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.4082397035
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1699579453
Short name T328
Test name
Test status
Simulation time 323876141 ps
CPU time 24.14 seconds
Started Jul 05 05:29:37 PM PDT 24
Finished Jul 05 05:30:02 PM PDT 24
Peak memory 250896 kb
Host smart-af8f1bc7-10bb-4aba-a9fe-5c8ada3c252a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699579453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1699579453
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2573249204
Short name T481
Test name
Test status
Simulation time 180168571 ps
CPU time 8.53 seconds
Started Jul 05 05:29:38 PM PDT 24
Finished Jul 05 05:29:47 PM PDT 24
Peak memory 250988 kb
Host smart-964b56cf-7888-4fc9-a2d5-50c7d463159c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573249204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2573249204
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.957457326
Short name T838
Test name
Test status
Simulation time 41367024605 ps
CPU time 64.27 seconds
Started Jul 05 05:29:40 PM PDT 24
Finished Jul 05 05:30:45 PM PDT 24
Peak memory 276132 kb
Host smart-6dbd8de3-f728-4ea0-8f6c-2f6191d45c3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957457326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.957457326
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2345288865
Short name T801
Test name
Test status
Simulation time 11591707 ps
CPU time 0.76 seconds
Started Jul 05 05:29:35 PM PDT 24
Finished Jul 05 05:29:37 PM PDT 24
Peak memory 207136 kb
Host smart-91e33960-85d8-4853-bba7-65669ee52916
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345288865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2345288865
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.3231769064
Short name T89
Test name
Test status
Simulation time 38526888 ps
CPU time 1.02 seconds
Started Jul 05 05:29:47 PM PDT 24
Finished Jul 05 05:29:50 PM PDT 24
Peak memory 208988 kb
Host smart-ae4d582c-e616-4e08-b4a2-ce94f276b876
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231769064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3231769064
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.2012489772
Short name T464
Test name
Test status
Simulation time 1477319486 ps
CPU time 15.24 seconds
Started Jul 05 05:29:36 PM PDT 24
Finished Jul 05 05:29:53 PM PDT 24
Peak memory 226044 kb
Host smart-e3562609-6f6c-482a-b76f-0d9e5f059593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012489772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.2012489772
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.4234934863
Short name T30
Test name
Test status
Simulation time 3140627678 ps
CPU time 7.05 seconds
Started Jul 05 05:29:37 PM PDT 24
Finished Jul 05 05:29:46 PM PDT 24
Peak memory 217676 kb
Host smart-123d5d4c-dd78-4e19-82ba-eaec0b0a2ec8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234934863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.4234934863
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.3083300577
Short name T774
Test name
Test status
Simulation time 680216556 ps
CPU time 2.88 seconds
Started Jul 05 05:29:38 PM PDT 24
Finished Jul 05 05:29:42 PM PDT 24
Peak memory 222608 kb
Host smart-d548c9ef-88f0-4ffc-a2b9-68d4a2758c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083300577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3083300577
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.262518451
Short name T307
Test name
Test status
Simulation time 1763487373 ps
CPU time 12.89 seconds
Started Jul 05 05:29:39 PM PDT 24
Finished Jul 05 05:29:52 PM PDT 24
Peak memory 218804 kb
Host smart-b9295b9a-fb5f-4589-9734-f85049881da1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262518451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.262518451
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.4137653601
Short name T482
Test name
Test status
Simulation time 2329366439 ps
CPU time 13.2 seconds
Started Jul 05 05:29:40 PM PDT 24
Finished Jul 05 05:29:54 PM PDT 24
Peak memory 226112 kb
Host smart-a2475764-55e0-4fbe-bc9a-6c525c8a8cf1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137653601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.4137653601
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.2612645295
Short name T352
Test name
Test status
Simulation time 327300108 ps
CPU time 8.44 seconds
Started Jul 05 05:29:37 PM PDT 24
Finished Jul 05 05:29:46 PM PDT 24
Peak memory 226044 kb
Host smart-84cf2660-9170-440b-9581-5cef51e4c94d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612645295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
2612645295
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.1143844308
Short name T159
Test name
Test status
Simulation time 1132471436 ps
CPU time 9.62 seconds
Started Jul 05 05:29:37 PM PDT 24
Finished Jul 05 05:29:48 PM PDT 24
Peak memory 225960 kb
Host smart-8ff4b39e-e223-4d67-b451-d646f2f5a6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143844308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.1143844308
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3024909646
Short name T74
Test name
Test status
Simulation time 62056421 ps
CPU time 3.7 seconds
Started Jul 05 05:29:37 PM PDT 24
Finished Jul 05 05:29:42 PM PDT 24
Peak memory 222880 kb
Host smart-46c18f12-5b6a-40cb-b4b6-2e7374d0a14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024909646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3024909646
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.286095881
Short name T590
Test name
Test status
Simulation time 1066500329 ps
CPU time 33.52 seconds
Started Jul 05 05:29:37 PM PDT 24
Finished Jul 05 05:30:12 PM PDT 24
Peak memory 251044 kb
Host smart-b4aed011-43f5-44b3-b4d1-fc231d158961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286095881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.286095881
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.11448433
Short name T708
Test name
Test status
Simulation time 123942498 ps
CPU time 6.42 seconds
Started Jul 05 05:29:35 PM PDT 24
Finished Jul 05 05:29:42 PM PDT 24
Peak memory 246804 kb
Host smart-1dafd35a-bfa5-4e2c-bbdb-60165f716b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11448433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.11448433
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.4173790590
Short name T39
Test name
Test status
Simulation time 22974938339 ps
CPU time 455.61 seconds
Started Jul 05 05:29:37 PM PDT 24
Finished Jul 05 05:37:14 PM PDT 24
Peak memory 333108 kb
Host smart-6e69abdb-57b7-48aa-bf19-9a7cbe1232dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4173790590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.4173790590
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.208921467
Short name T510
Test name
Test status
Simulation time 37097263 ps
CPU time 0.94 seconds
Started Jul 05 05:29:37 PM PDT 24
Finished Jul 05 05:29:39 PM PDT 24
Peak memory 213096 kb
Host smart-23e4e27b-6871-4dd9-9fbb-684a94a1cfd0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208921467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ct
rl_volatile_unlock_smoke.208921467
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3052115286
Short name T758
Test name
Test status
Simulation time 61953875 ps
CPU time 0.87 seconds
Started Jul 05 05:29:48 PM PDT 24
Finished Jul 05 05:29:51 PM PDT 24
Peak memory 209016 kb
Host smart-bcd7d913-a28b-4acf-8269-5fa40eac503a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052115286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3052115286
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.353858875
Short name T563
Test name
Test status
Simulation time 417549351 ps
CPU time 9.73 seconds
Started Jul 05 05:29:47 PM PDT 24
Finished Jul 05 05:29:59 PM PDT 24
Peak memory 218236 kb
Host smart-f2067b3c-d3b6-4feb-a2d5-278f93c558f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353858875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.353858875
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1822562625
Short name T29
Test name
Test status
Simulation time 73710282 ps
CPU time 1.98 seconds
Started Jul 05 05:29:44 PM PDT 24
Finished Jul 05 05:29:46 PM PDT 24
Peak memory 216996 kb
Host smart-063be82a-eb3a-4280-baab-5a6fa3db531e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822562625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1822562625
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.3325689278
Short name T283
Test name
Test status
Simulation time 70699817 ps
CPU time 3.41 seconds
Started Jul 05 05:29:46 PM PDT 24
Finished Jul 05 05:29:52 PM PDT 24
Peak memory 218232 kb
Host smart-38b1cf20-0656-4c6b-a713-fed0642df04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325689278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3325689278
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.4115916316
Short name T397
Test name
Test status
Simulation time 1537346337 ps
CPU time 16.73 seconds
Started Jul 05 05:29:45 PM PDT 24
Finished Jul 05 05:30:03 PM PDT 24
Peak memory 226040 kb
Host smart-9f100f68-590d-4ebc-8d5b-52c365158875
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115916316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.4115916316
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.2941570395
Short name T640
Test name
Test status
Simulation time 1224132714 ps
CPU time 9.96 seconds
Started Jul 05 05:29:46 PM PDT 24
Finished Jul 05 05:29:58 PM PDT 24
Peak memory 226044 kb
Host smart-3b1020ca-08b2-4857-aa6c-c411ebff13b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941570395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.2941570395
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2241947750
Short name T509
Test name
Test status
Simulation time 5439573238 ps
CPU time 9.23 seconds
Started Jul 05 05:29:45 PM PDT 24
Finished Jul 05 05:29:56 PM PDT 24
Peak memory 226016 kb
Host smart-4ce8f12d-f4bd-4b87-a9be-564c7e6f3a9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241947750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2241947750
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.375050856
Short name T790
Test name
Test status
Simulation time 300659538 ps
CPU time 11.33 seconds
Started Jul 05 05:29:48 PM PDT 24
Finished Jul 05 05:30:02 PM PDT 24
Peak memory 218296 kb
Host smart-3b609653-30ab-4391-af48-74a641bdd8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375050856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.375050856
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2507150154
Short name T194
Test name
Test status
Simulation time 26483479 ps
CPU time 2.03 seconds
Started Jul 05 05:29:47 PM PDT 24
Finished Jul 05 05:29:51 PM PDT 24
Peak memory 214176 kb
Host smart-5bc981a1-542d-4caf-9e54-c80c95f376c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507150154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2507150154
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3658122409
Short name T390
Test name
Test status
Simulation time 1171186237 ps
CPU time 36.92 seconds
Started Jul 05 05:29:45 PM PDT 24
Finished Jul 05 05:30:23 PM PDT 24
Peak memory 250872 kb
Host smart-9ec1ed6f-7a8a-4bbe-b09e-cdbfa8553aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658122409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3658122409
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.479019834
Short name T549
Test name
Test status
Simulation time 118564459 ps
CPU time 7.14 seconds
Started Jul 05 05:29:46 PM PDT 24
Finished Jul 05 05:29:55 PM PDT 24
Peak memory 250988 kb
Host smart-f4cb35d9-5417-4121-a095-9bc1b381cd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479019834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.479019834
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2194145138
Short name T105
Test name
Test status
Simulation time 9053671978 ps
CPU time 185.02 seconds
Started Jul 05 05:29:51 PM PDT 24
Finished Jul 05 05:32:57 PM PDT 24
Peak memory 281032 kb
Host smart-b14895be-5791-4b4b-9e4e-b9828a30f226
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194145138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2194145138
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.698750946
Short name T716
Test name
Test status
Simulation time 36052755 ps
CPU time 0.89 seconds
Started Jul 05 05:29:47 PM PDT 24
Finished Jul 05 05:29:50 PM PDT 24
Peak memory 212012 kb
Host smart-bea1408d-bfaa-4ee1-92a0-a8aedea09fa1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698750946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ct
rl_volatile_unlock_smoke.698750946
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3812835680
Short name T265
Test name
Test status
Simulation time 17456435 ps
CPU time 1.14 seconds
Started Jul 05 05:29:45 PM PDT 24
Finished Jul 05 05:29:48 PM PDT 24
Peak memory 208964 kb
Host smart-9e1358a8-0eb2-440f-9cc2-b991174db48e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812835680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3812835680
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.352062250
Short name T41
Test name
Test status
Simulation time 1924944453 ps
CPU time 20.56 seconds
Started Jul 05 05:29:47 PM PDT 24
Finished Jul 05 05:30:10 PM PDT 24
Peak memory 218152 kb
Host smart-da4684e0-4e66-48ef-8e55-0ce0bb0a7f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352062250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.352062250
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.3002141863
Short name T702
Test name
Test status
Simulation time 951029920 ps
CPU time 21.85 seconds
Started Jul 05 05:29:45 PM PDT 24
Finished Jul 05 05:30:08 PM PDT 24
Peak memory 217484 kb
Host smart-6d9d55c6-9e0f-4388-9637-1c367b93ed4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002141863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.3002141863
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3601948341
Short name T573
Test name
Test status
Simulation time 325583295 ps
CPU time 3.34 seconds
Started Jul 05 05:29:48 PM PDT 24
Finished Jul 05 05:29:54 PM PDT 24
Peak memory 218168 kb
Host smart-4f88425d-a2d7-4902-b56d-c33e055ded48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601948341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3601948341
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.4166068001
Short name T517
Test name
Test status
Simulation time 1322319504 ps
CPU time 17.26 seconds
Started Jul 05 05:29:47 PM PDT 24
Finished Jul 05 05:30:06 PM PDT 24
Peak memory 218488 kb
Host smart-005dc42b-7655-47e7-b5fd-e59c871be030
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166068001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.4166068001
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2074754593
Short name T17
Test name
Test status
Simulation time 2511242406 ps
CPU time 22.38 seconds
Started Jul 05 05:29:45 PM PDT 24
Finished Jul 05 05:30:09 PM PDT 24
Peak memory 226104 kb
Host smart-13cb1745-c3e9-4454-a8d2-fdedd1f136b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074754593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2074754593
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.186727721
Short name T593
Test name
Test status
Simulation time 432594774 ps
CPU time 10.02 seconds
Started Jul 05 05:29:48 PM PDT 24
Finished Jul 05 05:30:00 PM PDT 24
Peak memory 226040 kb
Host smart-7c27a0df-34fc-4414-83a0-57e02a9dbbf0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186727721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.186727721
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.2120224295
Short name T614
Test name
Test status
Simulation time 790214096 ps
CPU time 6.19 seconds
Started Jul 05 05:32:13 PM PDT 24
Finished Jul 05 05:32:20 PM PDT 24
Peak memory 224200 kb
Host smart-303ad0ed-3473-48bd-a475-0616aafa4e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120224295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.2120224295
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2710535578
Short name T57
Test name
Test status
Simulation time 20613607 ps
CPU time 1.52 seconds
Started Jul 05 05:29:46 PM PDT 24
Finished Jul 05 05:29:49 PM PDT 24
Peak memory 213956 kb
Host smart-dab1313a-ced2-41f3-a316-b4ae2b7eee91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710535578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2710535578
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3898211307
Short name T488
Test name
Test status
Simulation time 301119332 ps
CPU time 29.15 seconds
Started Jul 05 05:29:49 PM PDT 24
Finished Jul 05 05:30:20 PM PDT 24
Peak memory 250932 kb
Host smart-8de04652-f11d-46bb-804d-00afe575e55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898211307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3898211307
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.3715280139
Short name T463
Test name
Test status
Simulation time 133287022 ps
CPU time 10.15 seconds
Started Jul 05 05:29:46 PM PDT 24
Finished Jul 05 05:29:57 PM PDT 24
Peak memory 250976 kb
Host smart-2f054bcb-1151-4406-b1b9-24767fd925d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715280139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.3715280139
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.1289969347
Short name T863
Test name
Test status
Simulation time 49137357860 ps
CPU time 482.02 seconds
Started Jul 05 05:29:47 PM PDT 24
Finished Jul 05 05:37:51 PM PDT 24
Peak memory 278688 kb
Host smart-39abd02a-c1b4-43cf-bded-3ce260cd8997
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289969347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.1289969347
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.2615587623
Short name T197
Test name
Test status
Simulation time 15441469 ps
CPU time 0.92 seconds
Started Jul 05 05:29:45 PM PDT 24
Finished Jul 05 05:29:47 PM PDT 24
Peak memory 211904 kb
Host smart-858943fa-7d2f-468b-befb-dbf4b3f6a920
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615587623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.2615587623
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3012416662
Short name T674
Test name
Test status
Simulation time 48602213 ps
CPU time 1.07 seconds
Started Jul 05 05:29:47 PM PDT 24
Finished Jul 05 05:29:51 PM PDT 24
Peak memory 208952 kb
Host smart-e2714d7a-ac64-41ea-b0f2-d350ee01ee3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012416662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3012416662
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.3862434590
Short name T467
Test name
Test status
Simulation time 944725590 ps
CPU time 11.4 seconds
Started Jul 05 05:29:45 PM PDT 24
Finished Jul 05 05:29:58 PM PDT 24
Peak memory 218136 kb
Host smart-3d644399-4648-4aac-a359-31af08e2587e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862434590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.3862434590
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3930690143
Short name T183
Test name
Test status
Simulation time 2641676615 ps
CPU time 7.76 seconds
Started Jul 05 05:29:46 PM PDT 24
Finished Jul 05 05:29:56 PM PDT 24
Peak memory 217760 kb
Host smart-874d772b-339e-4d88-98a6-456babf7a7d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930690143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.3930690143
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3109379822
Short name T93
Test name
Test status
Simulation time 82059443 ps
CPU time 2.87 seconds
Started Jul 05 05:29:48 PM PDT 24
Finished Jul 05 05:29:53 PM PDT 24
Peak memory 218252 kb
Host smart-4d94a6a3-71cb-4f4a-8404-cfc176a4f87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109379822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3109379822
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1680329948
Short name T236
Test name
Test status
Simulation time 379020124 ps
CPU time 10.27 seconds
Started Jul 05 05:29:48 PM PDT 24
Finished Jul 05 05:30:00 PM PDT 24
Peak memory 226028 kb
Host smart-fa74022a-cf3d-4719-a520-c90ed105d560
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680329948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1680329948
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2830091527
Short name T661
Test name
Test status
Simulation time 437295374 ps
CPU time 11.26 seconds
Started Jul 05 05:29:46 PM PDT 24
Finished Jul 05 05:30:00 PM PDT 24
Peak memory 226012 kb
Host smart-d701a162-9af4-4ebd-8ae4-06348e4baa63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830091527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.2830091527
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.1523732902
Short name T180
Test name
Test status
Simulation time 388548515 ps
CPU time 12.59 seconds
Started Jul 05 05:29:48 PM PDT 24
Finished Jul 05 05:30:03 PM PDT 24
Peak memory 218236 kb
Host smart-1804e3de-400e-4efe-a62d-79b680e10739
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523732902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
1523732902
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.1783767999
Short name T45
Test name
Test status
Simulation time 267723168 ps
CPU time 7.95 seconds
Started Jul 05 05:29:47 PM PDT 24
Finished Jul 05 05:29:57 PM PDT 24
Peak memory 226040 kb
Host smart-39865073-d5d6-47e2-b85e-c9f5e0be3e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783767999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1783767999
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.2810419812
Short name T740
Test name
Test status
Simulation time 183432398 ps
CPU time 12.69 seconds
Started Jul 05 05:29:47 PM PDT 24
Finished Jul 05 05:30:02 PM PDT 24
Peak memory 217728 kb
Host smart-a9a18b45-78b1-4f41-ab35-d97d3735c44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810419812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.2810419812
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.823881899
Short name T603
Test name
Test status
Simulation time 1361180499 ps
CPU time 23.13 seconds
Started Jul 05 05:29:47 PM PDT 24
Finished Jul 05 05:30:12 PM PDT 24
Peak memory 250880 kb
Host smart-c2556efd-3b6d-48e4-aed7-6dd9957a5f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823881899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.823881899
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3526631992
Short name T621
Test name
Test status
Simulation time 47879147 ps
CPU time 6.11 seconds
Started Jul 05 05:38:48 PM PDT 24
Finished Jul 05 05:38:55 PM PDT 24
Peak memory 246468 kb
Host smart-c51959fc-9371-4275-8ebe-356e9399e6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526631992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3526631992
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.3029631647
Short name T671
Test name
Test status
Simulation time 26855262053 ps
CPU time 120.9 seconds
Started Jul 05 05:29:48 PM PDT 24
Finished Jul 05 05:31:51 PM PDT 24
Peak memory 278464 kb
Host smart-01700ae1-22dd-4996-8236-4650d8e131ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029631647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.3029631647
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.3505732442
Short name T165
Test name
Test status
Simulation time 2474402556 ps
CPU time 83.92 seconds
Started Jul 05 05:29:47 PM PDT 24
Finished Jul 05 05:31:13 PM PDT 24
Peak memory 259356 kb
Host smart-84738f26-2753-4814-b33b-b12841403ade
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3505732442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.3505732442
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2061495929
Short name T693
Test name
Test status
Simulation time 51025866 ps
CPU time 0.89 seconds
Started Jul 05 05:29:48 PM PDT 24
Finished Jul 05 05:29:51 PM PDT 24
Peak memory 211892 kb
Host smart-109fbe13-a073-48a1-bc13-776897733d2b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061495929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.2061495929
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.3037560687
Short name T238
Test name
Test status
Simulation time 21400777 ps
CPU time 0.94 seconds
Started Jul 05 05:29:47 PM PDT 24
Finished Jul 05 05:29:50 PM PDT 24
Peak memory 208976 kb
Host smart-9ccbd1a8-455c-4358-a829-74c07fb64099
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037560687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3037560687
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.1458880528
Short name T384
Test name
Test status
Simulation time 320547923 ps
CPU time 10.74 seconds
Started Jul 05 05:29:47 PM PDT 24
Finished Jul 05 05:30:00 PM PDT 24
Peak memory 218108 kb
Host smart-74e68233-f3f9-4800-983d-0c30d365e52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458880528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1458880528
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3219512548
Short name T364
Test name
Test status
Simulation time 134541485 ps
CPU time 1.17 seconds
Started Jul 05 05:29:47 PM PDT 24
Finished Jul 05 05:29:50 PM PDT 24
Peak memory 217088 kb
Host smart-29889d9f-6702-4a5a-b396-9ebae056ecdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219512548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3219512548
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.3303104497
Short name T627
Test name
Test status
Simulation time 135442472 ps
CPU time 1.89 seconds
Started Jul 05 05:29:45 PM PDT 24
Finished Jul 05 05:29:48 PM PDT 24
Peak memory 218168 kb
Host smart-a0369651-c973-412d-89f8-e918b21af4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303104497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3303104497
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1995818258
Short name T613
Test name
Test status
Simulation time 329900237 ps
CPU time 15.64 seconds
Started Jul 05 05:29:46 PM PDT 24
Finished Jul 05 05:30:04 PM PDT 24
Peak memory 225988 kb
Host smart-5660a5e0-b2f5-4334-9982-9bc78e885744
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995818258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1995818258
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.1763074465
Short name T848
Test name
Test status
Simulation time 4003971963 ps
CPU time 7.03 seconds
Started Jul 05 05:29:53 PM PDT 24
Finished Jul 05 05:30:01 PM PDT 24
Peak memory 226068 kb
Host smart-bcc5edb4-6b24-43cc-a53c-e497226109b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763074465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.1763074465
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2048157470
Short name T406
Test name
Test status
Simulation time 321979909 ps
CPU time 12.53 seconds
Started Jul 05 05:29:53 PM PDT 24
Finished Jul 05 05:30:07 PM PDT 24
Peak memory 226004 kb
Host smart-d0d05783-820a-44ed-8338-f960f14251a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048157470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2048157470
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.1133104891
Short name T413
Test name
Test status
Simulation time 4041132977 ps
CPU time 9.97 seconds
Started Jul 05 05:29:48 PM PDT 24
Finished Jul 05 05:30:00 PM PDT 24
Peak memory 226108 kb
Host smart-1224a5a0-61d4-4079-a602-e65c7fb54fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133104891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.1133104891
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.2939874619
Short name T263
Test name
Test status
Simulation time 114726079 ps
CPU time 3.44 seconds
Started Jul 05 05:29:47 PM PDT 24
Finished Jul 05 05:29:53 PM PDT 24
Peak memory 217592 kb
Host smart-6cdf789c-c7e6-4f60-a12d-653b10c8f871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939874619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.2939874619
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.662758547
Short name T545
Test name
Test status
Simulation time 740965602 ps
CPU time 20.52 seconds
Started Jul 05 05:29:47 PM PDT 24
Finished Jul 05 05:30:10 PM PDT 24
Peak memory 245360 kb
Host smart-e0c98e0f-0d8f-44fb-b4c5-a8783199bbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662758547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.662758547
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.2056006122
Short name T476
Test name
Test status
Simulation time 286856303 ps
CPU time 7.13 seconds
Started Jul 05 05:29:46 PM PDT 24
Finished Jul 05 05:29:56 PM PDT 24
Peak memory 250988 kb
Host smart-d7252d57-ea15-4ad8-ac80-dfa3096bad7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056006122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.2056006122
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1984690265
Short name T541
Test name
Test status
Simulation time 14409143285 ps
CPU time 74.99 seconds
Started Jul 05 05:29:42 PM PDT 24
Finished Jul 05 05:30:57 PM PDT 24
Peak memory 267688 kb
Host smart-6e4837e7-6adb-423b-9e79-c36a7ba057fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984690265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1984690265
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1167436790
Short name T334
Test name
Test status
Simulation time 23169934 ps
CPU time 1 seconds
Started Jul 05 05:29:47 PM PDT 24
Finished Jul 05 05:29:51 PM PDT 24
Peak memory 211932 kb
Host smart-015e581d-1d47-43b6-b898-1d5bf882b9ca
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167436790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1167436790
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2613769063
Short name T67
Test name
Test status
Simulation time 16498131 ps
CPU time 0.97 seconds
Started Jul 05 05:27:54 PM PDT 24
Finished Jul 05 05:27:57 PM PDT 24
Peak memory 208996 kb
Host smart-e7bb1356-7738-47fc-8fc9-7d7654e37433
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613769063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2613769063
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1015492004
Short name T533
Test name
Test status
Simulation time 427532835 ps
CPU time 18.48 seconds
Started Jul 05 05:27:45 PM PDT 24
Finished Jul 05 05:28:05 PM PDT 24
Peak memory 218164 kb
Host smart-91c9632a-7cb5-418c-8edf-fef06bb120be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015492004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1015492004
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1394532999
Short name T28
Test name
Test status
Simulation time 2548648460 ps
CPU time 5.14 seconds
Started Jul 05 05:27:45 PM PDT 24
Finished Jul 05 05:27:51 PM PDT 24
Peak memory 217828 kb
Host smart-e48ae515-5d99-4469-94cc-6eb2d7c5debe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394532999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1394532999
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1599749832
Short name T634
Test name
Test status
Simulation time 2365898991 ps
CPU time 29.55 seconds
Started Jul 05 05:27:44 PM PDT 24
Finished Jul 05 05:28:15 PM PDT 24
Peak memory 219028 kb
Host smart-2b63b725-af0e-4a98-9963-2cbfe5bb8699
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599749832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1599749832
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.1912458581
Short name T858
Test name
Test status
Simulation time 1591360530 ps
CPU time 5.21 seconds
Started Jul 05 05:27:49 PM PDT 24
Finished Jul 05 05:27:55 PM PDT 24
Peak memory 217748 kb
Host smart-1c3664e5-1035-4c72-9e1f-bf64b3cfd661
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912458581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.1
912458581
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1412951529
Short name T301
Test name
Test status
Simulation time 328965282 ps
CPU time 5.23 seconds
Started Jul 05 05:27:50 PM PDT 24
Finished Jul 05 05:27:56 PM PDT 24
Peak memory 218196 kb
Host smart-2244eaf4-5ceb-4996-952a-854e5aa7c157
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412951529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.1412951529
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.143249944
Short name T325
Test name
Test status
Simulation time 4881748124 ps
CPU time 16.48 seconds
Started Jul 05 05:27:55 PM PDT 24
Finished Jul 05 05:28:14 PM PDT 24
Peak memory 217668 kb
Host smart-c3267ed7-1bab-401f-84cb-05d089a0e385
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143249944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_regwen_during_op.143249944
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2318579163
Short name T314
Test name
Test status
Simulation time 3466442412 ps
CPU time 9.97 seconds
Started Jul 05 05:27:45 PM PDT 24
Finished Jul 05 05:27:56 PM PDT 24
Peak memory 217796 kb
Host smart-c8045fbb-73f9-49fd-bf38-bbfd6be63e93
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318579163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2318579163
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.195518754
Short name T827
Test name
Test status
Simulation time 3011178262 ps
CPU time 101.09 seconds
Started Jul 05 05:27:45 PM PDT 24
Finished Jul 05 05:29:27 PM PDT 24
Peak memory 283536 kb
Host smart-03e525fe-6062-416c-96b2-059d17161c9a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195518754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_state_failure.195518754
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.4247743571
Short name T657
Test name
Test status
Simulation time 990143067 ps
CPU time 18.79 seconds
Started Jul 05 05:27:47 PM PDT 24
Finished Jul 05 05:28:07 PM PDT 24
Peak memory 247604 kb
Host smart-bae8f543-69c2-407f-b9d0-76880a920d7c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247743571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.4247743571
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.2181427039
Short name T315
Test name
Test status
Simulation time 103072631 ps
CPU time 1.57 seconds
Started Jul 05 05:27:45 PM PDT 24
Finished Jul 05 05:27:48 PM PDT 24
Peak memory 218224 kb
Host smart-5b9fee44-8bfc-4289-8e38-ed58b780837e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181427039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.2181427039
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1638337192
Short name T206
Test name
Test status
Simulation time 310277084 ps
CPU time 16.7 seconds
Started Jul 05 05:27:48 PM PDT 24
Finished Jul 05 05:28:05 PM PDT 24
Peak memory 214684 kb
Host smart-e843d7ba-5a2f-4fcc-acea-da2c3a90686c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638337192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1638337192
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.161661911
Short name T92
Test name
Test status
Simulation time 250342113 ps
CPU time 37.21 seconds
Started Jul 05 05:27:54 PM PDT 24
Finished Jul 05 05:28:33 PM PDT 24
Peak memory 269992 kb
Host smart-603590d0-aef7-4811-ac95-7941575e6162
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161661911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.161661911
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3481632231
Short name T465
Test name
Test status
Simulation time 1071555731 ps
CPU time 8.23 seconds
Started Jul 05 05:27:54 PM PDT 24
Finished Jul 05 05:28:04 PM PDT 24
Peak memory 226032 kb
Host smart-66610c6c-33f9-4872-8956-e8cf001c189c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481632231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.3481632231
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1506969370
Short name T448
Test name
Test status
Simulation time 1003690547 ps
CPU time 9.29 seconds
Started Jul 05 05:27:54 PM PDT 24
Finished Jul 05 05:28:06 PM PDT 24
Peak memory 218256 kb
Host smart-47e0acec-4035-47e3-bb61-10d7702406f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506969370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.1
506969370
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.3868398850
Short name T574
Test name
Test status
Simulation time 996589880 ps
CPU time 10 seconds
Started Jul 05 05:27:49 PM PDT 24
Finished Jul 05 05:28:00 PM PDT 24
Peak memory 218368 kb
Host smart-c8c8c194-868f-4fbe-b311-fbcebc439551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868398850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3868398850
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.1653602025
Short name T75
Test name
Test status
Simulation time 139963282 ps
CPU time 2.62 seconds
Started Jul 05 05:27:46 PM PDT 24
Finished Jul 05 05:27:49 PM PDT 24
Peak memory 217728 kb
Host smart-ef4c6ee1-6272-4b5d-a6c0-16fc727ddde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653602025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1653602025
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1678775823
Short name T2
Test name
Test status
Simulation time 144104659 ps
CPU time 19.73 seconds
Started Jul 05 05:27:47 PM PDT 24
Finished Jul 05 05:28:08 PM PDT 24
Peak memory 244696 kb
Host smart-4b719680-86a0-43a4-b7dd-d0256b7b7fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678775823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1678775823
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.1101247940
Short name T94
Test name
Test status
Simulation time 316446686 ps
CPU time 7.2 seconds
Started Jul 05 05:27:47 PM PDT 24
Finished Jul 05 05:27:55 PM PDT 24
Peak memory 250980 kb
Host smart-91a98f44-ddd3-42b5-ac87-136a44ed7480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101247940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.1101247940
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.2935101691
Short name T753
Test name
Test status
Simulation time 465880261 ps
CPU time 22.63 seconds
Started Jul 05 05:27:52 PM PDT 24
Finished Jul 05 05:28:15 PM PDT 24
Peak memory 250936 kb
Host smart-07c79c68-ff9f-4a2f-b6b4-f35d61b66b5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935101691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.2935101691
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.69694536
Short name T40
Test name
Test status
Simulation time 19475054341 ps
CPU time 536.27 seconds
Started Jul 05 05:27:55 PM PDT 24
Finished Jul 05 05:36:53 PM PDT 24
Peak memory 496944 kb
Host smart-54d0bb5e-9b81-4405-9ea5-b88a6a94f84d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=69694536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.69694536
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2314926645
Short name T248
Test name
Test status
Simulation time 22261705 ps
CPU time 1.28 seconds
Started Jul 05 05:27:47 PM PDT 24
Finished Jul 05 05:27:49 PM PDT 24
Peak memory 217728 kb
Host smart-64fdbeb4-fa38-4e65-8bc2-7be7a4ec0594
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314926645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.2314926645
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.2544098514
Short name T779
Test name
Test status
Simulation time 18274876 ps
CPU time 1.14 seconds
Started Jul 05 05:29:54 PM PDT 24
Finished Jul 05 05:29:57 PM PDT 24
Peak memory 208976 kb
Host smart-3aa352a6-3e72-44bc-83fd-f9a77c7135e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544098514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.2544098514
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.641777060
Short name T823
Test name
Test status
Simulation time 2555537682 ps
CPU time 8.03 seconds
Started Jul 05 05:29:52 PM PDT 24
Finished Jul 05 05:30:01 PM PDT 24
Peak memory 226104 kb
Host smart-513fffd1-519b-4f79-8fae-cfa32fc34e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641777060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.641777060
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.2469506446
Short name T611
Test name
Test status
Simulation time 880548058 ps
CPU time 5.8 seconds
Started Jul 05 05:29:52 PM PDT 24
Finished Jul 05 05:29:58 PM PDT 24
Peak memory 217196 kb
Host smart-bc7b84de-e292-4e7b-8909-a3574edd098e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469506446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.2469506446
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.2758767490
Short name T487
Test name
Test status
Simulation time 73478472 ps
CPU time 3.78 seconds
Started Jul 05 05:29:52 PM PDT 24
Finished Jul 05 05:29:57 PM PDT 24
Peak memory 218200 kb
Host smart-cfc78559-c48b-434c-a2f3-8da9b99b2873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758767490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2758767490
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1187436935
Short name T395
Test name
Test status
Simulation time 239243080 ps
CPU time 9.23 seconds
Started Jul 05 05:29:55 PM PDT 24
Finished Jul 05 05:30:06 PM PDT 24
Peak memory 225988 kb
Host smart-6c45b795-60e8-41f7-b910-e20dda3fd40a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187436935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1187436935
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1970691490
Short name T673
Test name
Test status
Simulation time 547670979 ps
CPU time 12.06 seconds
Started Jul 05 05:30:00 PM PDT 24
Finished Jul 05 05:30:13 PM PDT 24
Peak memory 226032 kb
Host smart-f7511530-cc17-43c9-b1ce-390c52b9833d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970691490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1970691490
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3286832988
Short name T250
Test name
Test status
Simulation time 751936320 ps
CPU time 13.81 seconds
Started Jul 05 05:29:56 PM PDT 24
Finished Jul 05 05:30:11 PM PDT 24
Peak memory 218228 kb
Host smart-1d5b53b5-06c8-4d3e-87db-931c8ebd5e4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286832988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
3286832988
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.3194764474
Short name T330
Test name
Test status
Simulation time 278839451 ps
CPU time 8.32 seconds
Started Jul 05 05:29:54 PM PDT 24
Finished Jul 05 05:30:04 PM PDT 24
Peak memory 218176 kb
Host smart-3e8b2c73-7277-4558-b42f-4a510f73f1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194764474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3194764474
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.2812973646
Short name T62
Test name
Test status
Simulation time 237100783 ps
CPU time 8.06 seconds
Started Jul 05 05:29:47 PM PDT 24
Finished Jul 05 05:29:57 PM PDT 24
Peak memory 217744 kb
Host smart-d32be71a-9271-4562-b476-0e4abf1a1f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812973646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.2812973646
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.1334194935
Short name T732
Test name
Test status
Simulation time 1204203191 ps
CPU time 28.73 seconds
Started Jul 05 05:29:48 PM PDT 24
Finished Jul 05 05:30:19 PM PDT 24
Peak memory 251048 kb
Host smart-ff948fa2-1243-4eec-b460-6384bfe7b4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334194935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.1334194935
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.3434312738
Short name T451
Test name
Test status
Simulation time 232756307 ps
CPU time 6.83 seconds
Started Jul 05 05:29:53 PM PDT 24
Finished Jul 05 05:30:01 PM PDT 24
Peak memory 246764 kb
Host smart-2e9126ed-78ee-4d19-9807-e6ef562b9c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434312738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.3434312738
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.3615620411
Short name T867
Test name
Test status
Simulation time 57779383275 ps
CPU time 128.26 seconds
Started Jul 05 05:29:59 PM PDT 24
Finished Jul 05 05:32:09 PM PDT 24
Peak memory 251760 kb
Host smart-436e38f9-7911-4170-b5c5-30e1ffb7a8b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615620411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.3615620411
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.3456595131
Short name T164
Test name
Test status
Simulation time 16596098260 ps
CPU time 509.83 seconds
Started Jul 05 05:29:54 PM PDT 24
Finished Jul 05 05:38:26 PM PDT 24
Peak memory 267544 kb
Host smart-fafcf26f-89e2-4ce0-b05e-8c6305480682
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3456595131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.3456595131
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3104221145
Short name T551
Test name
Test status
Simulation time 14048108 ps
CPU time 0.92 seconds
Started Jul 05 05:29:53 PM PDT 24
Finished Jul 05 05:29:55 PM PDT 24
Peak memory 211940 kb
Host smart-85d3aa43-7fd1-48cc-a993-18794f094666
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104221145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3104221145
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.354098469
Short name T664
Test name
Test status
Simulation time 299809756 ps
CPU time 0.99 seconds
Started Jul 05 05:29:59 PM PDT 24
Finished Jul 05 05:30:02 PM PDT 24
Peak memory 208908 kb
Host smart-41de83fb-e8b7-44eb-b588-2cdd7a0b8f1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354098469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.354098469
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2648745434
Short name T427
Test name
Test status
Simulation time 968218896 ps
CPU time 10.91 seconds
Started Jul 05 05:29:53 PM PDT 24
Finished Jul 05 05:30:05 PM PDT 24
Peak memory 225972 kb
Host smart-1c037048-9d2a-477b-a00f-2c7565fb4dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648745434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2648745434
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2279062079
Short name T642
Test name
Test status
Simulation time 3010003676 ps
CPU time 13.71 seconds
Started Jul 05 05:29:59 PM PDT 24
Finished Jul 05 05:30:13 PM PDT 24
Peak memory 217548 kb
Host smart-95b9c3bc-4661-4e56-b526-63fc4804ef22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279062079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.2279062079
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.4033740343
Short name T513
Test name
Test status
Simulation time 207087259 ps
CPU time 2.8 seconds
Started Jul 05 05:29:58 PM PDT 24
Finished Jul 05 05:30:01 PM PDT 24
Peak memory 218172 kb
Host smart-a03b6dca-d6c6-480f-9753-6883d901621d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033740343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.4033740343
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.3664264211
Short name T162
Test name
Test status
Simulation time 1560100651 ps
CPU time 10.23 seconds
Started Jul 05 05:29:55 PM PDT 24
Finished Jul 05 05:30:06 PM PDT 24
Peak memory 218228 kb
Host smart-0e48fdb6-cda5-4954-b64d-73c1f83ad62e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664264211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.3664264211
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.69965706
Short name T254
Test name
Test status
Simulation time 1995076438 ps
CPU time 11.15 seconds
Started Jul 05 05:29:54 PM PDT 24
Finished Jul 05 05:30:06 PM PDT 24
Peak memory 225932 kb
Host smart-f14afdc4-c23d-453b-bc9a-4f5742ce163c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69965706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_dig
est.69965706
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.834270544
Short name T61
Test name
Test status
Simulation time 635629296 ps
CPU time 12.92 seconds
Started Jul 05 05:29:58 PM PDT 24
Finished Jul 05 05:30:12 PM PDT 24
Peak memory 218208 kb
Host smart-2dfe62d6-6d59-437a-ba2b-3b9bdc55bc06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834270544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.834270544
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.1379790611
Short name T739
Test name
Test status
Simulation time 593167214 ps
CPU time 11.16 seconds
Started Jul 05 05:29:58 PM PDT 24
Finished Jul 05 05:30:10 PM PDT 24
Peak memory 226028 kb
Host smart-6b46a850-e114-47ba-aceb-c7b18492e326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379790611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.1379790611
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2040764743
Short name T408
Test name
Test status
Simulation time 34332878 ps
CPU time 2.09 seconds
Started Jul 05 05:29:54 PM PDT 24
Finished Jul 05 05:29:57 PM PDT 24
Peak memory 214248 kb
Host smart-75d3e5aa-d9ef-4b28-aa72-fc3f11b7aab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040764743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2040764743
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.1189643774
Short name T700
Test name
Test status
Simulation time 267456711 ps
CPU time 25.5 seconds
Started Jul 05 05:29:56 PM PDT 24
Finished Jul 05 05:30:22 PM PDT 24
Peak memory 250976 kb
Host smart-9836d647-f789-429c-ac69-b81b49ad548c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189643774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1189643774
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.2135242431
Short name T866
Test name
Test status
Simulation time 54420529 ps
CPU time 6.8 seconds
Started Jul 05 05:29:54 PM PDT 24
Finished Jul 05 05:30:02 PM PDT 24
Peak memory 246932 kb
Host smart-d272cd5b-367d-4f62-a208-9479f9e1afed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135242431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.2135242431
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2825064515
Short name T80
Test name
Test status
Simulation time 51051370725 ps
CPU time 304.65 seconds
Started Jul 05 05:29:54 PM PDT 24
Finished Jul 05 05:35:00 PM PDT 24
Peak memory 278856 kb
Host smart-56122e91-f32a-4972-9401-69df85ff3b04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825064515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2825064515
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1205204546
Short name T102
Test name
Test status
Simulation time 34502845 ps
CPU time 0.92 seconds
Started Jul 05 05:29:52 PM PDT 24
Finished Jul 05 05:29:54 PM PDT 24
Peak memory 211856 kb
Host smart-06d5da14-2c04-4de8-9715-a90dda265383
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205204546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1205204546
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.3518651490
Short name T455
Test name
Test status
Simulation time 22366160 ps
CPU time 1.03 seconds
Started Jul 05 05:29:55 PM PDT 24
Finished Jul 05 05:29:57 PM PDT 24
Peak memory 208980 kb
Host smart-b1d87b66-4aa0-4da9-bfbc-356c4d1b64d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518651490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3518651490
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2623337738
Short name T320
Test name
Test status
Simulation time 791205544 ps
CPU time 10.48 seconds
Started Jul 05 05:29:56 PM PDT 24
Finished Jul 05 05:30:07 PM PDT 24
Peak memory 226020 kb
Host smart-dc47861a-3fa9-4ab6-a258-b2bdd076b46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623337738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2623337738
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.2539119182
Short name T504
Test name
Test status
Simulation time 1119781387 ps
CPU time 25.8 seconds
Started Jul 05 05:29:56 PM PDT 24
Finished Jul 05 05:30:23 PM PDT 24
Peak memory 217476 kb
Host smart-15ce173e-c29e-4bd1-895e-a8e50e22f455
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539119182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.2539119182
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.156662974
Short name T342
Test name
Test status
Simulation time 146949413 ps
CPU time 2.34 seconds
Started Jul 05 05:29:55 PM PDT 24
Finished Jul 05 05:29:59 PM PDT 24
Peak memory 218140 kb
Host smart-c329ce7c-608e-4e2e-8b19-633e1f4cabc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156662974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.156662974
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.3705651151
Short name T519
Test name
Test status
Simulation time 2112233651 ps
CPU time 13.81 seconds
Started Jul 05 05:29:58 PM PDT 24
Finished Jul 05 05:30:12 PM PDT 24
Peak memory 226004 kb
Host smart-572506a2-a261-439b-9c44-7a71a4d25391
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705651151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.3705651151
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.3595103997
Short name T280
Test name
Test status
Simulation time 745330555 ps
CPU time 13.9 seconds
Started Jul 05 05:29:53 PM PDT 24
Finished Jul 05 05:30:08 PM PDT 24
Peak memory 225996 kb
Host smart-f13676fc-e9ae-4e9a-9cd2-4e70ab7b26cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595103997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.3595103997
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.282015369
Short name T625
Test name
Test status
Simulation time 1362472146 ps
CPU time 10.2 seconds
Started Jul 05 05:29:59 PM PDT 24
Finished Jul 05 05:30:11 PM PDT 24
Peak memory 218232 kb
Host smart-edb0e55a-658b-4a2d-8c9e-52d1f86ff91c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282015369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.282015369
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.742068659
Short name T760
Test name
Test status
Simulation time 1366982056 ps
CPU time 9.85 seconds
Started Jul 05 05:29:55 PM PDT 24
Finished Jul 05 05:30:06 PM PDT 24
Peak memory 225472 kb
Host smart-e74cfeac-6a32-4cee-ac95-f507d615230b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742068659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.742068659
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2946908803
Short name T457
Test name
Test status
Simulation time 437589885 ps
CPU time 5.15 seconds
Started Jul 05 05:29:53 PM PDT 24
Finished Jul 05 05:29:59 PM PDT 24
Peak memory 217664 kb
Host smart-45c8781a-fc8d-4473-b066-d008dd083de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946908803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2946908803
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.1276958337
Short name T436
Test name
Test status
Simulation time 432336243 ps
CPU time 22.9 seconds
Started Jul 05 05:29:59 PM PDT 24
Finished Jul 05 05:30:23 PM PDT 24
Peak memory 250780 kb
Host smart-49c8d046-6567-42ec-8ef4-2783b4f84e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276958337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1276958337
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.2307773866
Short name T438
Test name
Test status
Simulation time 38967609496 ps
CPU time 217.95 seconds
Started Jul 05 05:29:58 PM PDT 24
Finished Jul 05 05:33:37 PM PDT 24
Peak memory 267392 kb
Host smart-40637c8b-81be-48e0-9d2f-899b8cdcee73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307773866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.2307773866
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.2967961562
Short name T192
Test name
Test status
Simulation time 43121006225 ps
CPU time 734.71 seconds
Started Jul 05 05:29:55 PM PDT 24
Finished Jul 05 05:42:11 PM PDT 24
Peak memory 299068 kb
Host smart-8246a2ba-9cbd-4d6e-93c2-7785b844d7b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2967961562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.2967961562
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.929912121
Short name T428
Test name
Test status
Simulation time 37190924 ps
CPU time 1.03 seconds
Started Jul 05 05:30:00 PM PDT 24
Finished Jul 05 05:30:03 PM PDT 24
Peak memory 211892 kb
Host smart-1a610d54-0010-4a60-95e5-812d51961916
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929912121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ct
rl_volatile_unlock_smoke.929912121
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2628217901
Short name T537
Test name
Test status
Simulation time 20734170 ps
CPU time 1.21 seconds
Started Jul 05 05:30:08 PM PDT 24
Finished Jul 05 05:30:10 PM PDT 24
Peak memory 208988 kb
Host smart-7f912385-9369-4bfe-9ac9-110837555ab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628217901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2628217901
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.1463487663
Short name T267
Test name
Test status
Simulation time 330722717 ps
CPU time 15.55 seconds
Started Jul 05 05:29:59 PM PDT 24
Finished Jul 05 05:30:15 PM PDT 24
Peak memory 225988 kb
Host smart-8f4df5e3-92e7-4c63-97cc-9fb555fe490d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463487663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.1463487663
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.4161184229
Short name T299
Test name
Test status
Simulation time 125560485 ps
CPU time 1.68 seconds
Started Jul 05 05:30:00 PM PDT 24
Finished Jul 05 05:30:03 PM PDT 24
Peak memory 217008 kb
Host smart-58621369-b3ca-4eb6-a8be-a84c6ad5e4ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161184229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.4161184229
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.537940269
Short name T685
Test name
Test status
Simulation time 143504156 ps
CPU time 2.02 seconds
Started Jul 05 05:29:56 PM PDT 24
Finished Jul 05 05:30:00 PM PDT 24
Peak memory 218172 kb
Host smart-2a3342aa-d9f6-4f4a-8161-86a6ed9bc873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537940269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.537940269
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.1130538052
Short name T270
Test name
Test status
Simulation time 1461777147 ps
CPU time 10.99 seconds
Started Jul 05 05:30:00 PM PDT 24
Finished Jul 05 05:30:12 PM PDT 24
Peak memory 225984 kb
Host smart-1cdc8874-6fac-4049-a539-7652a8c5d1fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130538052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.1130538052
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1747944812
Short name T469
Test name
Test status
Simulation time 363615137 ps
CPU time 10.26 seconds
Started Jul 05 05:29:54 PM PDT 24
Finished Jul 05 05:30:06 PM PDT 24
Peak memory 226048 kb
Host smart-33ea7a17-58b6-43c8-85a4-f5c9fe5fce07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747944812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.1747944812
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1198442867
Short name T800
Test name
Test status
Simulation time 1358586870 ps
CPU time 8.26 seconds
Started Jul 05 05:29:55 PM PDT 24
Finished Jul 05 05:30:04 PM PDT 24
Peak memory 218160 kb
Host smart-587a3cf0-2635-4908-a004-fd78a99740bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198442867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1198442867
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2528985950
Short name T775
Test name
Test status
Simulation time 462022459 ps
CPU time 9.66 seconds
Started Jul 05 05:29:56 PM PDT 24
Finished Jul 05 05:30:07 PM PDT 24
Peak memory 225960 kb
Host smart-ea761566-a2cb-42c7-a06e-070c205e5b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528985950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2528985950
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.884133683
Short name T359
Test name
Test status
Simulation time 97593649 ps
CPU time 1.76 seconds
Started Jul 05 05:29:58 PM PDT 24
Finished Jul 05 05:30:01 PM PDT 24
Peak memory 217556 kb
Host smart-bef24a43-db93-40e4-9ad8-9b53ab756965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884133683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.884133683
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.590044481
Short name T798
Test name
Test status
Simulation time 312740033 ps
CPU time 33.72 seconds
Started Jul 05 05:29:56 PM PDT 24
Finished Jul 05 05:30:30 PM PDT 24
Peak memory 250964 kb
Host smart-5a97cf6e-d619-44e4-8770-73c1cb57265e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590044481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.590044481
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.3598068707
Short name T411
Test name
Test status
Simulation time 280472835 ps
CPU time 3.24 seconds
Started Jul 05 05:29:59 PM PDT 24
Finished Jul 05 05:30:04 PM PDT 24
Peak memory 218164 kb
Host smart-402b9c80-9fd8-4150-acf9-956de2459fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598068707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3598068707
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.381444478
Short name T516
Test name
Test status
Simulation time 9335905018 ps
CPU time 71.48 seconds
Started Jul 05 05:29:56 PM PDT 24
Finished Jul 05 05:31:09 PM PDT 24
Peak memory 275788 kb
Host smart-a626fb82-7043-495d-989c-cf36a08ac4d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381444478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.381444478
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.958642455
Short name T678
Test name
Test status
Simulation time 29238629685 ps
CPU time 873.03 seconds
Started Jul 05 05:30:01 PM PDT 24
Finished Jul 05 05:44:36 PM PDT 24
Peak memory 333116 kb
Host smart-295e0aff-c0cf-42e5-984e-b6db18a83309
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=958642455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.958642455
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.919921523
Short name T349
Test name
Test status
Simulation time 36542510 ps
CPU time 0.93 seconds
Started Jul 05 05:29:56 PM PDT 24
Finished Jul 05 05:29:58 PM PDT 24
Peak memory 211888 kb
Host smart-b53b0070-7374-421f-a4a6-9fe4637b24b5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919921523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ct
rl_volatile_unlock_smoke.919921523
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.3348178770
Short name T812
Test name
Test status
Simulation time 794570737 ps
CPU time 11.74 seconds
Started Jul 05 05:30:44 PM PDT 24
Finished Jul 05 05:30:58 PM PDT 24
Peak memory 218168 kb
Host smart-9649872f-c9bd-49b9-8acc-eae0d79534e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348178770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.3348178770
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.4289448400
Short name T508
Test name
Test status
Simulation time 180485752 ps
CPU time 2.32 seconds
Started Jul 05 05:30:04 PM PDT 24
Finished Jul 05 05:30:07 PM PDT 24
Peak memory 217092 kb
Host smart-cef195fc-6dee-41eb-8b39-6d64e4dde599
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289448400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.4289448400
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.4274572537
Short name T576
Test name
Test status
Simulation time 474713476 ps
CPU time 2.94 seconds
Started Jul 05 05:30:03 PM PDT 24
Finished Jul 05 05:30:07 PM PDT 24
Peak memory 218228 kb
Host smart-c9433d26-0dce-43b5-8878-234b622d1fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274572537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.4274572537
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.3288580787
Short name T864
Test name
Test status
Simulation time 305476498 ps
CPU time 11.81 seconds
Started Jul 05 05:30:01 PM PDT 24
Finished Jul 05 05:30:15 PM PDT 24
Peak memory 226040 kb
Host smart-a2115b50-e513-4fbe-bcb1-0b94d6bf1d91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288580787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3288580787
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1419553715
Short name T346
Test name
Test status
Simulation time 322964903 ps
CPU time 9.23 seconds
Started Jul 05 05:30:00 PM PDT 24
Finished Jul 05 05:30:10 PM PDT 24
Peak memory 218252 kb
Host smart-6d3fabc5-a809-4755-b787-3b1f2d880a1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419553715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1419553715
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.4121815061
Short name T286
Test name
Test status
Simulation time 1688510266 ps
CPU time 15.23 seconds
Started Jul 05 05:30:03 PM PDT 24
Finished Jul 05 05:30:20 PM PDT 24
Peak memory 226040 kb
Host smart-66bfe3f2-d967-464c-899a-75a8bfa942ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121815061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.4121815061
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.4277042531
Short name T843
Test name
Test status
Simulation time 24224716 ps
CPU time 1.85 seconds
Started Jul 05 05:30:01 PM PDT 24
Finished Jul 05 05:30:05 PM PDT 24
Peak memory 214060 kb
Host smart-e5776888-ef74-440a-bc71-ee09251fb12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277042531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.4277042531
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.1494215620
Short name T33
Test name
Test status
Simulation time 165147776 ps
CPU time 24.11 seconds
Started Jul 05 05:29:59 PM PDT 24
Finished Jul 05 05:30:25 PM PDT 24
Peak memory 251052 kb
Host smart-bb2131b6-5e2a-4add-8890-7ed4e8c7546c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494215620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.1494215620
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3292924395
Short name T486
Test name
Test status
Simulation time 67035022 ps
CPU time 8.26 seconds
Started Jul 05 05:30:01 PM PDT 24
Finished Jul 05 05:30:10 PM PDT 24
Peak memory 250872 kb
Host smart-1835801b-6bc2-4111-ac2e-32d88426f862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292924395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3292924395
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.418249944
Short name T680
Test name
Test status
Simulation time 3839328987 ps
CPU time 159.26 seconds
Started Jul 05 05:30:02 PM PDT 24
Finished Jul 05 05:32:42 PM PDT 24
Peak memory 275532 kb
Host smart-2a224e27-5b52-41aa-8232-9b0fbde43a66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418249944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.418249944
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2188757382
Short name T762
Test name
Test status
Simulation time 41915464 ps
CPU time 1.08 seconds
Started Jul 05 05:30:00 PM PDT 24
Finished Jul 05 05:30:03 PM PDT 24
Peak memory 211772 kb
Host smart-42e337c5-b324-474f-bb8f-4e0c7e8782bb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188757382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.2188757382
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.4121401264
Short name T870
Test name
Test status
Simulation time 270637615 ps
CPU time 0.94 seconds
Started Jul 05 05:30:02 PM PDT 24
Finished Jul 05 05:30:05 PM PDT 24
Peak memory 208984 kb
Host smart-204cb697-c2b1-4025-9b02-639d73d17f5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121401264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.4121401264
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.212167886
Short name T13
Test name
Test status
Simulation time 1146121772 ps
CPU time 14.71 seconds
Started Jul 05 05:30:00 PM PDT 24
Finished Jul 05 05:30:16 PM PDT 24
Peak memory 218232 kb
Host smart-e5a6ad7f-ee6e-4bbe-990e-e48ec87f9f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212167886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.212167886
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.3170866241
Short name T198
Test name
Test status
Simulation time 4563429299 ps
CPU time 7.1 seconds
Started Jul 05 05:30:02 PM PDT 24
Finished Jul 05 05:30:11 PM PDT 24
Peak memory 217712 kb
Host smart-764c8624-dbef-4ab1-86dd-8c366e7ba922
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170866241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3170866241
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.1840495196
Short name T561
Test name
Test status
Simulation time 1188803788 ps
CPU time 3.6 seconds
Started Jul 05 05:30:04 PM PDT 24
Finished Jul 05 05:30:09 PM PDT 24
Peak memory 218228 kb
Host smart-8736f3c9-8717-409a-9c3d-601359e9abbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840495196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.1840495196
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.958574798
Short name T201
Test name
Test status
Simulation time 351005862 ps
CPU time 14.5 seconds
Started Jul 05 05:30:01 PM PDT 24
Finished Jul 05 05:30:16 PM PDT 24
Peak memory 226040 kb
Host smart-6bcaeb4e-357b-4ebc-b173-8255f24ea27f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958574798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_di
gest.958574798
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.766998491
Short name T721
Test name
Test status
Simulation time 560197602 ps
CPU time 10.63 seconds
Started Jul 05 05:30:04 PM PDT 24
Finished Jul 05 05:30:16 PM PDT 24
Peak memory 218256 kb
Host smart-96762f19-40ca-4414-b04b-2435b4c363c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766998491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.766998491
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.4058644508
Short name T647
Test name
Test status
Simulation time 130320655 ps
CPU time 0.99 seconds
Started Jul 05 05:30:03 PM PDT 24
Finished Jul 05 05:30:05 PM PDT 24
Peak memory 217716 kb
Host smart-99fa2250-0a1a-4ef2-9ca7-82a0a67c14a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058644508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.4058644508
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.2164404225
Short name T84
Test name
Test status
Simulation time 197160347 ps
CPU time 22.81 seconds
Started Jul 05 05:30:00 PM PDT 24
Finished Jul 05 05:30:25 PM PDT 24
Peak memory 251000 kb
Host smart-9577b3fa-c59d-48f8-bbc0-6f42f31acd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164404225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.2164404225
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.898470509
Short name T303
Test name
Test status
Simulation time 193888037 ps
CPU time 7.71 seconds
Started Jul 05 05:30:00 PM PDT 24
Finished Jul 05 05:30:09 PM PDT 24
Peak memory 250820 kb
Host smart-2d534c72-fc07-4a80-84d3-94d73d668a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898470509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.898470509
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.1366058362
Short name T77
Test name
Test status
Simulation time 43806611805 ps
CPU time 348.84 seconds
Started Jul 05 05:30:01 PM PDT 24
Finished Jul 05 05:35:51 PM PDT 24
Peak memory 316132 kb
Host smart-3ef520cf-7767-4efd-a0bd-612b029d91c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366058362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.1366058362
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.4254218250
Short name T154
Test name
Test status
Simulation time 99550948918 ps
CPU time 656.45 seconds
Started Jul 05 05:30:03 PM PDT 24
Finished Jul 05 05:41:01 PM PDT 24
Peak memory 283888 kb
Host smart-bdff4d18-6d1e-4fb3-aad4-159619343543
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4254218250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.4254218250
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.850810861
Short name T229
Test name
Test status
Simulation time 17011001 ps
CPU time 0.96 seconds
Started Jul 05 05:30:02 PM PDT 24
Finished Jul 05 05:30:04 PM PDT 24
Peak memory 211904 kb
Host smart-8a0f6160-f962-42fa-9c99-44ebf7d9ddd5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850810861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ct
rl_volatile_unlock_smoke.850810861
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3705600265
Short name T402
Test name
Test status
Simulation time 21686327 ps
CPU time 1.19 seconds
Started Jul 05 05:30:12 PM PDT 24
Finished Jul 05 05:30:16 PM PDT 24
Peak memory 208916 kb
Host smart-69161e5c-fa4b-40c0-92bf-dc934b162cc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705600265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3705600265
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2940920406
Short name T249
Test name
Test status
Simulation time 378858547 ps
CPU time 12.19 seconds
Started Jul 05 05:30:01 PM PDT 24
Finished Jul 05 05:30:14 PM PDT 24
Peak memory 218176 kb
Host smart-074e6783-ac7e-4a3a-b160-787909ae8399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940920406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2940920406
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1714117698
Short name T193
Test name
Test status
Simulation time 358415493 ps
CPU time 5.09 seconds
Started Jul 05 05:30:03 PM PDT 24
Finished Jul 05 05:30:10 PM PDT 24
Peak memory 217452 kb
Host smart-a0d85ec1-96a4-4302-9b45-5ce29a29fc39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714117698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.1714117698
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3778166291
Short name T506
Test name
Test status
Simulation time 27527329 ps
CPU time 2.24 seconds
Started Jul 05 05:30:01 PM PDT 24
Finished Jul 05 05:30:05 PM PDT 24
Peak memory 218204 kb
Host smart-195a99d5-94d2-4d28-829d-b57ce8a73d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778166291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3778166291
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1669732189
Short name T167
Test name
Test status
Simulation time 536418405 ps
CPU time 15.22 seconds
Started Jul 05 05:30:11 PM PDT 24
Finished Jul 05 05:30:28 PM PDT 24
Peak memory 226044 kb
Host smart-cfeae464-7fc9-4bd9-ae59-6103543a6710
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669732189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.1669732189
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.1223453167
Short name T521
Test name
Test status
Simulation time 273888351 ps
CPU time 6.85 seconds
Started Jul 05 05:30:09 PM PDT 24
Finished Jul 05 05:30:16 PM PDT 24
Peak memory 218248 kb
Host smart-7d55a042-4759-4093-97e2-f11e17f9568c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223453167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
1223453167
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.2808881730
Short name T403
Test name
Test status
Simulation time 293772242 ps
CPU time 13.15 seconds
Started Jul 05 05:30:00 PM PDT 24
Finished Jul 05 05:30:15 PM PDT 24
Peak memory 218300 kb
Host smart-c94965a3-6900-4665-af2a-2de84a597fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808881730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.2808881730
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.3157653501
Short name T79
Test name
Test status
Simulation time 134927976 ps
CPU time 2.29 seconds
Started Jul 05 05:30:04 PM PDT 24
Finished Jul 05 05:30:07 PM PDT 24
Peak memory 217692 kb
Host smart-7488b335-acab-473f-9899-b8e70e380050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157653501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.3157653501
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.649981186
Short name T583
Test name
Test status
Simulation time 1567418025 ps
CPU time 34.41 seconds
Started Jul 05 05:30:03 PM PDT 24
Finished Jul 05 05:30:39 PM PDT 24
Peak memory 250988 kb
Host smart-d62c6001-c28d-44d4-a5a9-6ae565b0d56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649981186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.649981186
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.3966637280
Short name T666
Test name
Test status
Simulation time 81925872 ps
CPU time 3.08 seconds
Started Jul 05 05:30:03 PM PDT 24
Finished Jul 05 05:30:07 PM PDT 24
Peak memory 226404 kb
Host smart-4eecd1f0-00e4-48b4-a321-7ec0da2c21ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966637280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3966637280
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.721997233
Short name T190
Test name
Test status
Simulation time 50958826747 ps
CPU time 368.85 seconds
Started Jul 05 05:30:11 PM PDT 24
Finished Jul 05 05:36:23 PM PDT 24
Peak memory 250888 kb
Host smart-a634d308-591e-483c-b249-d0b23fac097c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721997233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.721997233
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3811172407
Short name T343
Test name
Test status
Simulation time 41905592 ps
CPU time 0.97 seconds
Started Jul 05 05:30:02 PM PDT 24
Finished Jul 05 05:30:05 PM PDT 24
Peak memory 211864 kb
Host smart-dae07f4d-d85c-4369-89a3-c74ea48e316f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811172407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3811172407
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.1525530019
Short name T783
Test name
Test status
Simulation time 77055522 ps
CPU time 0.93 seconds
Started Jul 05 05:30:11 PM PDT 24
Finished Jul 05 05:30:15 PM PDT 24
Peak memory 208980 kb
Host smart-279c05dc-8c2d-4848-9288-f595505838f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525530019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1525530019
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1385935953
Short name T515
Test name
Test status
Simulation time 1690730949 ps
CPU time 15.72 seconds
Started Jul 05 05:30:12 PM PDT 24
Finished Jul 05 05:30:31 PM PDT 24
Peak memory 218232 kb
Host smart-ddcdf1aa-a6a4-46ca-8018-17878df9e1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385935953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1385935953
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.645850462
Short name T690
Test name
Test status
Simulation time 705758532 ps
CPU time 5.54 seconds
Started Jul 05 05:30:11 PM PDT 24
Finished Jul 05 05:30:19 PM PDT 24
Peak memory 217224 kb
Host smart-15b424af-77cc-40ce-b7be-80b22bea531a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645850462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.645850462
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.1747878198
Short name T200
Test name
Test status
Simulation time 61077197 ps
CPU time 1.61 seconds
Started Jul 05 05:30:11 PM PDT 24
Finished Jul 05 05:30:16 PM PDT 24
Peak memory 218116 kb
Host smart-dfc59a70-e77f-4862-95f6-e0a595e2cf56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747878198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1747878198
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.2485326456
Short name T310
Test name
Test status
Simulation time 748292540 ps
CPU time 10.31 seconds
Started Jul 05 05:30:12 PM PDT 24
Finished Jul 05 05:30:25 PM PDT 24
Peak memory 226044 kb
Host smart-38021130-6e9b-4a77-9398-0a91d3bcaeb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485326456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.2485326456
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3617736410
Short name T268
Test name
Test status
Simulation time 919063390 ps
CPU time 9.8 seconds
Started Jul 05 05:30:10 PM PDT 24
Finished Jul 05 05:30:21 PM PDT 24
Peak memory 218208 kb
Host smart-9f10ecb9-be8a-4eff-9fba-e2dd05e38111
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617736410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3617736410
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.567534559
Short name T828
Test name
Test status
Simulation time 433862503 ps
CPU time 10.44 seconds
Started Jul 05 05:30:13 PM PDT 24
Finished Jul 05 05:30:26 PM PDT 24
Peak memory 226044 kb
Host smart-ced4e246-d014-437e-b801-04f834a111f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567534559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.567534559
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.4077603090
Short name T178
Test name
Test status
Simulation time 14794364 ps
CPU time 1.26 seconds
Started Jul 05 05:30:11 PM PDT 24
Finished Jul 05 05:30:15 PM PDT 24
Peak memory 212220 kb
Host smart-47995aea-3dba-4110-8701-c71d5f9daf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077603090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.4077603090
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.806743941
Short name T792
Test name
Test status
Simulation time 829476624 ps
CPU time 27.33 seconds
Started Jul 05 05:30:12 PM PDT 24
Finished Jul 05 05:30:42 PM PDT 24
Peak memory 250884 kb
Host smart-d3630041-fe6e-40d7-92c0-8383f6dc1b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806743941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.806743941
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2059681126
Short name T565
Test name
Test status
Simulation time 65458823 ps
CPU time 8.11 seconds
Started Jul 05 05:30:12 PM PDT 24
Finished Jul 05 05:30:23 PM PDT 24
Peak memory 243436 kb
Host smart-26636028-097e-4111-9ee4-4b36cac83092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059681126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2059681126
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.1033761692
Short name T534
Test name
Test status
Simulation time 16102670004 ps
CPU time 170.88 seconds
Started Jul 05 05:30:12 PM PDT 24
Finished Jul 05 05:33:05 PM PDT 24
Peak memory 282320 kb
Host smart-bd210c14-55ca-4575-aae3-d6f0108ece60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033761692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.1033761692
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.303078192
Short name T246
Test name
Test status
Simulation time 15616036 ps
CPU time 0.76 seconds
Started Jul 05 05:30:11 PM PDT 24
Finished Jul 05 05:30:12 PM PDT 24
Peak memory 207160 kb
Host smart-bfa73931-72af-4664-b29e-9f01544bf7af
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303078192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.303078192
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1118101579
Short name T90
Test name
Test status
Simulation time 26299043 ps
CPU time 1.01 seconds
Started Jul 05 05:30:12 PM PDT 24
Finished Jul 05 05:30:16 PM PDT 24
Peak memory 208932 kb
Host smart-515f125b-1560-4207-966f-c287dff74a9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118101579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1118101579
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.2426363828
Short name T704
Test name
Test status
Simulation time 452624156 ps
CPU time 10.7 seconds
Started Jul 05 05:30:11 PM PDT 24
Finished Jul 05 05:30:24 PM PDT 24
Peak memory 218120 kb
Host smart-f0b86bea-779e-42b5-9e58-3a00d1b33c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426363828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.2426363828
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.566969184
Short name T269
Test name
Test status
Simulation time 112475174 ps
CPU time 1.63 seconds
Started Jul 05 05:30:13 PM PDT 24
Finished Jul 05 05:30:17 PM PDT 24
Peak memory 216968 kb
Host smart-37a4553c-922a-4ac1-807c-8e250b573774
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566969184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.566969184
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.1004686552
Short name T243
Test name
Test status
Simulation time 136383882 ps
CPU time 2.19 seconds
Started Jul 05 05:30:12 PM PDT 24
Finished Jul 05 05:30:17 PM PDT 24
Peak memory 218040 kb
Host smart-ed6f28e5-f8ac-4883-b163-97983febe688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004686552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.1004686552
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.1487935843
Short name T326
Test name
Test status
Simulation time 892869291 ps
CPU time 8.85 seconds
Started Jul 05 05:30:13 PM PDT 24
Finished Jul 05 05:30:24 PM PDT 24
Peak memory 218124 kb
Host smart-494a57ed-986b-4b95-bf86-e4eaa93fc6a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487935843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.1487935843
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.2339737741
Short name T409
Test name
Test status
Simulation time 1158655417 ps
CPU time 16.26 seconds
Started Jul 05 05:30:11 PM PDT 24
Finished Jul 05 05:30:30 PM PDT 24
Peak memory 218236 kb
Host smart-fd262b9d-5177-4b09-9cd4-a7fcbffcb1af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339737741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.2339737741
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1016806552
Short name T491
Test name
Test status
Simulation time 422116908 ps
CPU time 14.26 seconds
Started Jul 05 05:32:56 PM PDT 24
Finished Jul 05 05:33:10 PM PDT 24
Peak memory 218208 kb
Host smart-9de20c07-ed89-45b5-b71a-162154d618e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016806552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1016806552
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.4251860394
Short name T558
Test name
Test status
Simulation time 1685133283 ps
CPU time 14.99 seconds
Started Jul 05 05:30:12 PM PDT 24
Finished Jul 05 05:30:30 PM PDT 24
Peak memory 225868 kb
Host smart-837255fd-5e4f-4109-8517-01bf7f771605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251860394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.4251860394
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.3754349526
Short name T309
Test name
Test status
Simulation time 64552926 ps
CPU time 3.55 seconds
Started Jul 05 05:30:12 PM PDT 24
Finished Jul 05 05:30:18 PM PDT 24
Peak memory 217724 kb
Host smart-dc1eb4bb-455d-4fcc-b4c9-1fb654b76bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754349526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3754349526
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.45681189
Short name T86
Test name
Test status
Simulation time 715068919 ps
CPU time 27.43 seconds
Started Jul 05 05:30:13 PM PDT 24
Finished Jul 05 05:30:42 PM PDT 24
Peak memory 250924 kb
Host smart-a38f49f6-c686-44dd-b5e4-0c003b854369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45681189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.45681189
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.1228033513
Short name T400
Test name
Test status
Simulation time 245747027 ps
CPU time 5.83 seconds
Started Jul 05 05:30:12 PM PDT 24
Finished Jul 05 05:30:21 PM PDT 24
Peak memory 246460 kb
Host smart-28ba9563-7ced-4f1e-8384-f46f8b21d6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228033513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.1228033513
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3530402146
Short name T319
Test name
Test status
Simulation time 4729538205 ps
CPU time 78.58 seconds
Started Jul 05 05:30:11 PM PDT 24
Finished Jul 05 05:31:32 PM PDT 24
Peak memory 276480 kb
Host smart-b5a50555-ce30-49d2-bb67-06cb75e4947d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530402146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3530402146
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.3864076613
Short name T156
Test name
Test status
Simulation time 17464805955 ps
CPU time 435.14 seconds
Started Jul 05 05:30:12 PM PDT 24
Finished Jul 05 05:37:30 PM PDT 24
Peak memory 496908 kb
Host smart-266a26f8-a63f-45ff-b73a-1b1bd2098a27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3864076613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.3864076613
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1540585787
Short name T503
Test name
Test status
Simulation time 83602266 ps
CPU time 0.86 seconds
Started Jul 05 05:30:11 PM PDT 24
Finished Jul 05 05:30:15 PM PDT 24
Peak memory 211868 kb
Host smart-c250488f-8cf8-4e38-80aa-935c5433e8c8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540585787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.1540585787
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.1604895247
Short name T304
Test name
Test status
Simulation time 46505058 ps
CPU time 1.3 seconds
Started Jul 05 05:30:20 PM PDT 24
Finished Jul 05 05:30:22 PM PDT 24
Peak memory 209116 kb
Host smart-c4281406-4e98-4144-81eb-a60b976fc720
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604895247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.1604895247
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3851028047
Short name T191
Test name
Test status
Simulation time 326845101 ps
CPU time 12.09 seconds
Started Jul 05 05:30:19 PM PDT 24
Finished Jul 05 05:30:32 PM PDT 24
Peak memory 218136 kb
Host smart-b3ed6cf9-98ad-4566-aeca-84ea1132a2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851028047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3851028047
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.3837474025
Short name T5
Test name
Test status
Simulation time 113382285 ps
CPU time 3.39 seconds
Started Jul 05 05:30:19 PM PDT 24
Finished Jul 05 05:30:23 PM PDT 24
Peak memory 217104 kb
Host smart-2a159dd4-5d44-4a8e-8e3d-1119d6fe7eae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837474025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.3837474025
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.396613563
Short name T539
Test name
Test status
Simulation time 333341822 ps
CPU time 3.32 seconds
Started Jul 05 05:30:10 PM PDT 24
Finished Jul 05 05:30:14 PM PDT 24
Peak memory 218168 kb
Host smart-ee2c52cf-8c89-4b5f-91a6-0adc7177f9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396613563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.396613563
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1846064688
Short name T439
Test name
Test status
Simulation time 407593517 ps
CPU time 9.12 seconds
Started Jul 05 05:30:20 PM PDT 24
Finished Jul 05 05:30:30 PM PDT 24
Peak memory 226040 kb
Host smart-379f4488-e00d-4325-a47e-94249e27fb13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846064688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1846064688
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.4025933278
Short name T290
Test name
Test status
Simulation time 553482461 ps
CPU time 6.53 seconds
Started Jul 05 05:30:26 PM PDT 24
Finished Jul 05 05:30:34 PM PDT 24
Peak memory 218220 kb
Host smart-736adfb3-422e-4449-aa5f-6af556506f32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025933278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
4025933278
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.2810924577
Short name T658
Test name
Test status
Simulation time 652242003 ps
CPU time 6.08 seconds
Started Jul 05 05:30:25 PM PDT 24
Finished Jul 05 05:30:31 PM PDT 24
Peak memory 226040 kb
Host smart-c0245569-7f16-42a9-9ccc-d443684d91ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810924577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.2810924577
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.4225906743
Short name T292
Test name
Test status
Simulation time 64870890 ps
CPU time 1.57 seconds
Started Jul 05 05:30:10 PM PDT 24
Finished Jul 05 05:30:12 PM PDT 24
Peak memory 217836 kb
Host smart-1d2ddc00-f2f9-4ffd-b087-ba88bd786b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225906743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.4225906743
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.2759867167
Short name T360
Test name
Test status
Simulation time 267841446 ps
CPU time 24.41 seconds
Started Jul 05 05:30:10 PM PDT 24
Finished Jul 05 05:30:36 PM PDT 24
Peak memory 250980 kb
Host smart-f9c70b4b-97d9-44b3-86ee-fbad8452358f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759867167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.2759867167
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.3845777843
Short name T846
Test name
Test status
Simulation time 712136459 ps
CPU time 7.82 seconds
Started Jul 05 05:30:12 PM PDT 24
Finished Jul 05 05:30:23 PM PDT 24
Peak memory 244460 kb
Host smart-a28d7f5a-1d5d-468d-8cf5-635e3c4f846a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845777843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3845777843
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3108715077
Short name T684
Test name
Test status
Simulation time 9544366456 ps
CPU time 36.33 seconds
Started Jul 05 05:30:28 PM PDT 24
Finished Jul 05 05:31:05 PM PDT 24
Peak memory 267596 kb
Host smart-6356660e-f263-43ec-9def-9a119de24540
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108715077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3108715077
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.876435404
Short name T109
Test name
Test status
Simulation time 29727964881 ps
CPU time 590.74 seconds
Started Jul 05 05:30:25 PM PDT 24
Finished Jul 05 05:40:17 PM PDT 24
Peak memory 267476 kb
Host smart-d4c04a70-471a-4c60-8ff5-7bfc502249ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=876435404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.876435404
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2966980070
Short name T425
Test name
Test status
Simulation time 20645689 ps
CPU time 1.03 seconds
Started Jul 05 05:30:13 PM PDT 24
Finished Jul 05 05:30:17 PM PDT 24
Peak memory 211992 kb
Host smart-cc7d20d6-816e-4bcc-b7d2-aed9f32a0deb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966980070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.2966980070
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.549652983
Short name T289
Test name
Test status
Simulation time 59193321 ps
CPU time 0.97 seconds
Started Jul 05 05:27:54 PM PDT 24
Finished Jul 05 05:27:57 PM PDT 24
Peak memory 208980 kb
Host smart-29925c66-bee7-43ad-8e37-7fe3ea92864b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549652983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.549652983
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.498305188
Short name T327
Test name
Test status
Simulation time 1290976609 ps
CPU time 14.16 seconds
Started Jul 05 05:27:53 PM PDT 24
Finished Jul 05 05:28:08 PM PDT 24
Peak memory 218136 kb
Host smart-3b43ce74-647a-4bd1-ac22-e926d1464c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498305188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.498305188
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3869562297
Short name T688
Test name
Test status
Simulation time 1232220206 ps
CPU time 3.56 seconds
Started Jul 05 05:27:51 PM PDT 24
Finished Jul 05 05:27:55 PM PDT 24
Peak memory 217508 kb
Host smart-46e7cc59-2cfb-483e-b1bd-8166e840d462
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869562297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3869562297
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.447531797
Short name T814
Test name
Test status
Simulation time 11870161940 ps
CPU time 98.56 seconds
Started Jul 05 05:27:53 PM PDT 24
Finished Jul 05 05:29:33 PM PDT 24
Peak memory 219944 kb
Host smart-7d93dccd-4aad-49a9-9e34-bb4fec35abfe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447531797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.447531797
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.1622161012
Short name T378
Test name
Test status
Simulation time 3074549589 ps
CPU time 7.17 seconds
Started Jul 05 05:27:52 PM PDT 24
Finished Jul 05 05:28:00 PM PDT 24
Peak memory 217876 kb
Host smart-d3a6b2ed-d61b-4057-9f1d-1275284c8050
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622161012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.1
622161012
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1720294030
Short name T528
Test name
Test status
Simulation time 284694980 ps
CPU time 2.94 seconds
Started Jul 05 05:27:58 PM PDT 24
Finished Jul 05 05:28:01 PM PDT 24
Peak memory 218252 kb
Host smart-d656aacc-389a-4647-821c-46a0a6df3eb7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720294030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.1720294030
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.4239017542
Short name T597
Test name
Test status
Simulation time 6651039386 ps
CPU time 17.61 seconds
Started Jul 05 05:27:54 PM PDT 24
Finished Jul 05 05:28:13 PM PDT 24
Peak memory 217788 kb
Host smart-9f5ae807-0c33-4ba0-afc3-c9c1db7e0cb7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239017542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.4239017542
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1735141433
Short name T810
Test name
Test status
Simulation time 221100761 ps
CPU time 4.2 seconds
Started Jul 05 05:27:55 PM PDT 24
Finished Jul 05 05:28:01 PM PDT 24
Peak memory 217580 kb
Host smart-770119bf-5ac9-45a4-9195-6b50730f4e87
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735141433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1735141433
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3160885626
Short name T317
Test name
Test status
Simulation time 1195948673 ps
CPU time 50.51 seconds
Started Jul 05 05:27:54 PM PDT 24
Finished Jul 05 05:28:47 PM PDT 24
Peak memory 275664 kb
Host smart-d572740c-ae7d-49fa-835b-4a21754fe944
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160885626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3160885626
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2386322791
Short name T602
Test name
Test status
Simulation time 3526361736 ps
CPU time 25.97 seconds
Started Jul 05 05:27:51 PM PDT 24
Finished Jul 05 05:28:18 PM PDT 24
Peak memory 226488 kb
Host smart-de03b3d9-38be-4574-8c4f-b7ff000f40d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386322791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2386322791
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3724712728
Short name T18
Test name
Test status
Simulation time 395850064 ps
CPU time 4.4 seconds
Started Jul 05 05:27:52 PM PDT 24
Finished Jul 05 05:27:57 PM PDT 24
Peak memory 218112 kb
Host smart-33d093db-0070-4d94-af79-6d0176436913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724712728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3724712728
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.3774143250
Short name T203
Test name
Test status
Simulation time 1539848532 ps
CPU time 25.17 seconds
Started Jul 05 05:27:53 PM PDT 24
Finished Jul 05 05:28:20 PM PDT 24
Peak memory 217724 kb
Host smart-404f5997-5b2e-441b-b973-7aca5448c84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774143250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.3774143250
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.18807824
Short name T433
Test name
Test status
Simulation time 3163495075 ps
CPU time 13.8 seconds
Started Jul 05 05:27:53 PM PDT 24
Finished Jul 05 05:28:07 PM PDT 24
Peak memory 219492 kb
Host smart-97b7ee1d-3566-48ba-8dc8-dc55dec7619f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18807824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.18807824
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.1112147332
Short name T492
Test name
Test status
Simulation time 3229495323 ps
CPU time 16.08 seconds
Started Jul 05 05:27:54 PM PDT 24
Finished Jul 05 05:28:11 PM PDT 24
Peak memory 218284 kb
Host smart-92a1ba40-1d4f-4efb-ba3e-04ebdd581efc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112147332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.1112147332
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3031126882
Short name T722
Test name
Test status
Simulation time 5137536528 ps
CPU time 17.24 seconds
Started Jul 05 05:27:51 PM PDT 24
Finished Jul 05 05:28:09 PM PDT 24
Peak memory 226044 kb
Host smart-a800ba75-fc94-449f-809e-e22a00c4c375
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031126882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
031126882
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.2536824700
Short name T233
Test name
Test status
Simulation time 524609078 ps
CPU time 10.76 seconds
Started Jul 05 05:27:55 PM PDT 24
Finished Jul 05 05:28:08 PM PDT 24
Peak memory 226016 kb
Host smart-95f98e64-c4fe-4a4e-9719-278c5a4f6c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536824700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.2536824700
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.172776277
Short name T606
Test name
Test status
Simulation time 1057957454 ps
CPU time 3 seconds
Started Jul 05 05:27:56 PM PDT 24
Finished Jul 05 05:28:01 PM PDT 24
Peak memory 217728 kb
Host smart-ebbc1f94-1179-4093-ac77-7c14fa138f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172776277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.172776277
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.452944927
Short name T412
Test name
Test status
Simulation time 684097593 ps
CPU time 31.03 seconds
Started Jul 05 05:27:53 PM PDT 24
Finished Jul 05 05:28:25 PM PDT 24
Peak memory 250896 kb
Host smart-00032551-8a97-4605-8bac-1a014b482519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452944927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.452944927
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.3745388554
Short name T696
Test name
Test status
Simulation time 87831402 ps
CPU time 9.75 seconds
Started Jul 05 05:27:52 PM PDT 24
Finished Jul 05 05:28:02 PM PDT 24
Peak memory 250884 kb
Host smart-934cc8a2-3568-41d6-842e-0c29f12820c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745388554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.3745388554
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.780494455
Short name T187
Test name
Test status
Simulation time 24365089921 ps
CPU time 129.15 seconds
Started Jul 05 05:27:55 PM PDT 24
Finished Jul 05 05:30:06 PM PDT 24
Peak memory 226944 kb
Host smart-f47db94f-567a-4a1e-9bf3-73f2b6ccf782
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780494455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.780494455
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.2957442708
Short name T153
Test name
Test status
Simulation time 33408443981 ps
CPU time 1175.89 seconds
Started Jul 05 05:27:51 PM PDT 24
Finished Jul 05 05:47:28 PM PDT 24
Peak memory 422432 kb
Host smart-51c330ee-cb20-490b-8f1c-f251a54b3c83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2957442708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.2957442708
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3018869915
Short name T244
Test name
Test status
Simulation time 12108067 ps
CPU time 0.95 seconds
Started Jul 05 05:27:53 PM PDT 24
Finished Jul 05 05:27:54 PM PDT 24
Peak memory 211988 kb
Host smart-c7a8ab5c-bd0d-40e1-8ba5-057931a3dfe2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018869915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.3018869915
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.2962655222
Short name T471
Test name
Test status
Simulation time 42614057 ps
CPU time 0.98 seconds
Started Jul 05 05:28:01 PM PDT 24
Finished Jul 05 05:28:04 PM PDT 24
Peak memory 209016 kb
Host smart-e88ee8b9-3b5a-4b76-93f6-ed281306b973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962655222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2962655222
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3094389574
Short name T780
Test name
Test status
Simulation time 30447448 ps
CPU time 0.92 seconds
Started Jul 05 05:27:50 PM PDT 24
Finished Jul 05 05:27:51 PM PDT 24
Peak memory 208960 kb
Host smart-21b502e4-0b07-4af5-bde1-51674f911f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094389574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3094389574
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.1562394987
Short name T871
Test name
Test status
Simulation time 1509093931 ps
CPU time 18.47 seconds
Started Jul 05 05:27:55 PM PDT 24
Finished Jul 05 05:28:15 PM PDT 24
Peak memory 218168 kb
Host smart-a212764d-e4a3-4434-8b40-e31df51fc7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562394987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1562394987
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.3440931771
Short name T27
Test name
Test status
Simulation time 4079504105 ps
CPU time 9.26 seconds
Started Jul 05 05:28:01 PM PDT 24
Finished Jul 05 05:28:12 PM PDT 24
Peak memory 217764 kb
Host smart-0f559b24-f2a8-481b-98b4-fb327ee295fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440931771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.3440931771
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.375055806
Short name T746
Test name
Test status
Simulation time 15719654736 ps
CPU time 24.75 seconds
Started Jul 05 05:28:04 PM PDT 24
Finished Jul 05 05:28:29 PM PDT 24
Peak memory 226116 kb
Host smart-c9e77d23-1700-49ef-a998-477c191acfda
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375055806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_err
ors.375055806
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1117437056
Short name T662
Test name
Test status
Simulation time 5307570420 ps
CPU time 6.08 seconds
Started Jul 05 05:28:02 PM PDT 24
Finished Jul 05 05:28:10 PM PDT 24
Peak memory 217856 kb
Host smart-cf10df9e-45f3-470a-bbb3-4f16157c25e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117437056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
117437056
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.820876322
Short name T473
Test name
Test status
Simulation time 612008415 ps
CPU time 17.78 seconds
Started Jul 05 05:28:03 PM PDT 24
Finished Jul 05 05:28:22 PM PDT 24
Peak memory 224384 kb
Host smart-5ef1db2e-120d-4d4e-8a7f-3d1b20563f43
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820876322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
prog_failure.820876322
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3438124210
Short name T659
Test name
Test status
Simulation time 3377795595 ps
CPU time 12.22 seconds
Started Jul 05 05:28:01 PM PDT 24
Finished Jul 05 05:28:15 PM PDT 24
Peak memory 217804 kb
Host smart-530c5956-bec7-467d-8470-3d0d54ac609d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438124210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.3438124210
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.812862255
Short name T675
Test name
Test status
Simulation time 395085274 ps
CPU time 5.2 seconds
Started Jul 05 05:27:52 PM PDT 24
Finished Jul 05 05:27:58 PM PDT 24
Peak memory 217732 kb
Host smart-cc1e4852-ae8a-4586-8a9a-ba62c72305ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812862255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.812862255
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.4251529358
Short name T544
Test name
Test status
Simulation time 8036166184 ps
CPU time 76.93 seconds
Started Jul 05 05:27:56 PM PDT 24
Finished Jul 05 05:29:15 PM PDT 24
Peak memory 276068 kb
Host smart-6d5cd17f-d41f-4407-b93d-e68935271863
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251529358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.4251529358
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2532176587
Short name T750
Test name
Test status
Simulation time 290940028 ps
CPU time 11.61 seconds
Started Jul 05 05:27:51 PM PDT 24
Finished Jul 05 05:28:03 PM PDT 24
Peak memory 251008 kb
Host smart-16c8e78a-235a-4327-bd67-9f5fcb4c22dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532176587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.2532176587
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3083846033
Short name T365
Test name
Test status
Simulation time 85243574 ps
CPU time 1.75 seconds
Started Jul 05 05:27:55 PM PDT 24
Finished Jul 05 05:27:59 PM PDT 24
Peak memory 218192 kb
Host smart-507c06f8-1937-4ff9-a472-2f58cf117da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083846033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3083846033
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.1137189162
Short name T205
Test name
Test status
Simulation time 1196226859 ps
CPU time 9.73 seconds
Started Jul 05 05:27:52 PM PDT 24
Finished Jul 05 05:28:02 PM PDT 24
Peak memory 223084 kb
Host smart-605afa4d-ebce-4031-892b-f3dde05dd7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137189162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1137189162
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.3128855960
Short name T588
Test name
Test status
Simulation time 250179343 ps
CPU time 10.66 seconds
Started Jul 05 05:28:01 PM PDT 24
Finished Jul 05 05:28:13 PM PDT 24
Peak memory 218868 kb
Host smart-1a0cb90f-807a-40c2-ab86-688a712cfa6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128855960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3128855960
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.159119756
Short name T805
Test name
Test status
Simulation time 368994496 ps
CPU time 12.06 seconds
Started Jul 05 05:28:00 PM PDT 24
Finished Jul 05 05:28:14 PM PDT 24
Peak memory 226104 kb
Host smart-d58f693e-9f24-4a0d-af0f-1918ebf7b877
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159119756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dig
est.159119756
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.4276014679
Short name T361
Test name
Test status
Simulation time 739949972 ps
CPU time 13.46 seconds
Started Jul 05 05:28:02 PM PDT 24
Finished Jul 05 05:28:17 PM PDT 24
Peak memory 218136 kb
Host smart-11f573dc-6c0f-4875-a1b0-714a37ffaf81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276014679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.4
276014679
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.1762026354
Short name T484
Test name
Test status
Simulation time 4019138644 ps
CPU time 12.38 seconds
Started Jul 05 05:27:55 PM PDT 24
Finished Jul 05 05:28:09 PM PDT 24
Peak memory 218360 kb
Host smart-071276a3-54b9-4805-bc8e-65475d93da3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762026354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1762026354
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.209571884
Short name T370
Test name
Test status
Simulation time 203140237 ps
CPU time 2.11 seconds
Started Jul 05 05:27:55 PM PDT 24
Finished Jul 05 05:27:59 PM PDT 24
Peak memory 214244 kb
Host smart-162a5c9d-acaa-4f0d-94e3-c08dfd8aa5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209571884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.209571884
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3331833231
Short name T631
Test name
Test status
Simulation time 285939795 ps
CPU time 21.99 seconds
Started Jul 05 05:27:53 PM PDT 24
Finished Jul 05 05:28:17 PM PDT 24
Peak memory 250988 kb
Host smart-fe0696ab-4804-449d-bb7f-75357a8ff05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331833231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3331833231
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.1989552940
Short name T429
Test name
Test status
Simulation time 254808409 ps
CPU time 3.25 seconds
Started Jul 05 05:27:54 PM PDT 24
Finished Jul 05 05:27:59 PM PDT 24
Peak memory 222508 kb
Host smart-47a2f8de-81fa-4f2d-a0ec-ca532a1f435d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989552940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.1989552940
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.1381150321
Short name T850
Test name
Test status
Simulation time 19227406100 ps
CPU time 54.89 seconds
Started Jul 05 05:28:02 PM PDT 24
Finished Jul 05 05:28:59 PM PDT 24
Peak memory 251024 kb
Host smart-fb8b0bf4-52c3-4e01-b076-8428c7b51f9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381150321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.1381150321
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.583761650
Short name T567
Test name
Test status
Simulation time 31225074439 ps
CPU time 171.59 seconds
Started Jul 05 05:28:06 PM PDT 24
Finished Jul 05 05:30:58 PM PDT 24
Peak memory 283940 kb
Host smart-e12d8579-51f8-494d-9503-ff31f077c1c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=583761650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.583761650
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.4122704228
Short name T10
Test name
Test status
Simulation time 42764670 ps
CPU time 0.92 seconds
Started Jul 05 05:27:55 PM PDT 24
Finished Jul 05 05:27:58 PM PDT 24
Peak memory 211824 kb
Host smart-6aa7308c-76cb-426e-a780-db30a32dc29a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122704228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.4122704228
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.664566050
Short name T483
Test name
Test status
Simulation time 26473327 ps
CPU time 0.98 seconds
Started Jul 05 05:28:04 PM PDT 24
Finished Jul 05 05:28:06 PM PDT 24
Peak memory 209032 kb
Host smart-2487d534-02f4-471c-8410-8167d1126106
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664566050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.664566050
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3224831430
Short name T577
Test name
Test status
Simulation time 52684729 ps
CPU time 0.79 seconds
Started Jul 05 05:28:00 PM PDT 24
Finished Jul 05 05:28:02 PM PDT 24
Peak memory 208964 kb
Host smart-5a0bce96-ba6d-4714-aced-18134a770a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224831430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3224831430
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.3753106720
Short name T679
Test name
Test status
Simulation time 1791641146 ps
CPU time 14.03 seconds
Started Jul 05 05:28:02 PM PDT 24
Finished Jul 05 05:28:17 PM PDT 24
Peak memory 218136 kb
Host smart-4277028a-5d03-41f5-b75f-d8a787ef0c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753106720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3753106720
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.3928728566
Short name T182
Test name
Test status
Simulation time 801844347 ps
CPU time 10.76 seconds
Started Jul 05 05:28:02 PM PDT 24
Finished Jul 05 05:28:14 PM PDT 24
Peak memory 217248 kb
Host smart-ddc8a59c-1eeb-4186-bcca-42c09a7e9300
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928728566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.3928728566
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.2918515561
Short name T557
Test name
Test status
Simulation time 12008929565 ps
CPU time 54.46 seconds
Started Jul 05 05:28:01 PM PDT 24
Finished Jul 05 05:28:57 PM PDT 24
Peak memory 219776 kb
Host smart-9fe541ee-8ff2-4391-a97a-2acab9a3b8b9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918515561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.2918515561
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.1093729914
Short name T834
Test name
Test status
Simulation time 98116024 ps
CPU time 3.32 seconds
Started Jul 05 05:28:01 PM PDT 24
Finished Jul 05 05:28:05 PM PDT 24
Peak memory 217740 kb
Host smart-a69356da-f6be-4dc1-a3fa-4bbcd56fac50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093729914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.1
093729914
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2491359461
Short name T456
Test name
Test status
Simulation time 143603989 ps
CPU time 3.55 seconds
Started Jul 05 05:28:00 PM PDT 24
Finished Jul 05 05:28:05 PM PDT 24
Peak memory 218140 kb
Host smart-5155dd5e-e5db-4443-b665-d808eb1af1a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491359461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.2491359461
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1908588314
Short name T69
Test name
Test status
Simulation time 2336856978 ps
CPU time 15.87 seconds
Started Jul 05 05:28:02 PM PDT 24
Finished Jul 05 05:28:20 PM PDT 24
Peak memory 217784 kb
Host smart-3db95e86-ebc5-4bd4-a857-315c98556e3b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908588314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.1908588314
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1896250547
Short name T63
Test name
Test status
Simulation time 1562498434 ps
CPU time 11.32 seconds
Started Jul 05 05:28:00 PM PDT 24
Finished Jul 05 05:28:11 PM PDT 24
Peak memory 217728 kb
Host smart-24e75ec6-5830-48f9-afb0-40f085f564fb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896250547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1896250547
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1883181487
Short name T99
Test name
Test status
Simulation time 5011369230 ps
CPU time 87.17 seconds
Started Jul 05 05:28:00 PM PDT 24
Finished Jul 05 05:29:27 PM PDT 24
Peak memory 283820 kb
Host smart-b4edbf39-b4a1-417c-b789-498480a02708
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883181487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1883181487
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2142809997
Short name T607
Test name
Test status
Simulation time 2742928737 ps
CPU time 20.36 seconds
Started Jul 05 05:28:02 PM PDT 24
Finished Jul 05 05:28:23 PM PDT 24
Peak memory 226112 kb
Host smart-d6195f20-6561-4aa5-b5cd-eb91783c2ad1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142809997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2142809997
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.4045133506
Short name T199
Test name
Test status
Simulation time 613449678 ps
CPU time 6.12 seconds
Started Jul 05 05:28:02 PM PDT 24
Finished Jul 05 05:28:10 PM PDT 24
Peak memory 222360 kb
Host smart-5f49acb8-605e-49c7-8d18-9a23f61c8932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045133506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.4045133506
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.2878092482
Short name T393
Test name
Test status
Simulation time 468880387 ps
CPU time 6.38 seconds
Started Jul 05 05:28:02 PM PDT 24
Finished Jul 05 05:28:09 PM PDT 24
Peak memory 222996 kb
Host smart-87eb87bf-3ebb-40a0-b5b8-2f7e734bdcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878092482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.2878092482
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.1517330813
Short name T38
Test name
Test status
Simulation time 538272011 ps
CPU time 13.52 seconds
Started Jul 05 05:28:02 PM PDT 24
Finished Jul 05 05:28:17 PM PDT 24
Peak memory 218748 kb
Host smart-4b1afd75-bcea-439e-900b-de86bba75ff3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517330813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.1517330813
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3393639435
Short name T264
Test name
Test status
Simulation time 294057054 ps
CPU time 11.83 seconds
Started Jul 05 05:28:03 PM PDT 24
Finished Jul 05 05:28:16 PM PDT 24
Peak memory 226036 kb
Host smart-2392d69e-a37d-41c7-8a18-a61ae6115e3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393639435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3393639435
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.3679343520
Short name T734
Test name
Test status
Simulation time 336110910 ps
CPU time 12.43 seconds
Started Jul 05 05:28:05 PM PDT 24
Finished Jul 05 05:28:18 PM PDT 24
Peak memory 226040 kb
Host smart-c5fb6bdb-c529-4a1c-ba6c-83c02c638446
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679343520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.3
679343520
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.56254004
Short name T392
Test name
Test status
Simulation time 461668718 ps
CPU time 10.3 seconds
Started Jul 05 05:28:03 PM PDT 24
Finished Jul 05 05:28:15 PM PDT 24
Peak memory 225364 kb
Host smart-d56ccba7-3a32-4369-8bff-7f954f8b037b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56254004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.56254004
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2529127432
Short name T285
Test name
Test status
Simulation time 75659113 ps
CPU time 2.38 seconds
Started Jul 05 05:28:07 PM PDT 24
Finished Jul 05 05:28:11 PM PDT 24
Peak memory 214224 kb
Host smart-cd888f31-5d57-42ec-a1ef-64df15a649af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529127432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2529127432
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.765489618
Short name T559
Test name
Test status
Simulation time 233093272 ps
CPU time 19.07 seconds
Started Jul 05 05:28:01 PM PDT 24
Finished Jul 05 05:28:21 PM PDT 24
Peak memory 250864 kb
Host smart-a9e4650b-cc20-4ecc-b0a9-88bfcb1fd680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765489618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.765489618
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.953947326
Short name T274
Test name
Test status
Simulation time 174127927 ps
CPU time 10.75 seconds
Started Jul 05 05:28:00 PM PDT 24
Finished Jul 05 05:28:12 PM PDT 24
Peak memory 251012 kb
Host smart-1427cde8-9cd9-4c42-8bcf-a5c0531a7f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953947326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.953947326
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.1405191216
Short name T598
Test name
Test status
Simulation time 6785751714 ps
CPU time 67.46 seconds
Started Jul 05 05:28:03 PM PDT 24
Finished Jul 05 05:29:12 PM PDT 24
Peak memory 273604 kb
Host smart-5ea5a05a-688e-4dee-b5de-5663a3837f43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405191216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.1405191216
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.4171897486
Short name T495
Test name
Test status
Simulation time 32704762 ps
CPU time 0.87 seconds
Started Jul 05 05:28:04 PM PDT 24
Finished Jul 05 05:28:05 PM PDT 24
Peak memory 211836 kb
Host smart-a8773e9f-e507-4d0e-a2ad-a52c82a04c23
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171897486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.4171897486
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.541234039
Short name T757
Test name
Test status
Simulation time 35907820 ps
CPU time 0.94 seconds
Started Jul 05 05:28:07 PM PDT 24
Finished Jul 05 05:28:09 PM PDT 24
Peak memory 208896 kb
Host smart-4d65c036-cdc3-46b8-8f77-8e2177806c7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541234039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.541234039
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.4251765587
Short name T232
Test name
Test status
Simulation time 21283157 ps
CPU time 0.98 seconds
Started Jul 05 05:28:09 PM PDT 24
Finished Jul 05 05:28:12 PM PDT 24
Peak memory 209268 kb
Host smart-e53ddf72-010b-49de-931e-4bfddbf3f326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251765587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.4251765587
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.2803958756
Short name T646
Test name
Test status
Simulation time 3904289973 ps
CPU time 9.58 seconds
Started Jul 05 05:28:14 PM PDT 24
Finished Jul 05 05:28:25 PM PDT 24
Peak memory 226112 kb
Host smart-c9261667-03ac-4ea4-bb29-f2261a05d997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803958756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.2803958756
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.3883425489
Short name T478
Test name
Test status
Simulation time 534099091 ps
CPU time 13.57 seconds
Started Jul 05 05:28:10 PM PDT 24
Finished Jul 05 05:28:25 PM PDT 24
Peak memory 217440 kb
Host smart-ce041877-80a1-45b9-adf3-6fa98489c893
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883425489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3883425489
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.828934531
Short name T752
Test name
Test status
Simulation time 2192798523 ps
CPU time 42.68 seconds
Started Jul 05 05:28:09 PM PDT 24
Finished Jul 05 05:28:53 PM PDT 24
Peak memory 226108 kb
Host smart-d5fd185f-1ec4-45f7-a2c4-e4c65625d3ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828934531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_err
ors.828934531
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.994696972
Short name T808
Test name
Test status
Simulation time 204860269 ps
CPU time 1.89 seconds
Started Jul 05 05:28:07 PM PDT 24
Finished Jul 05 05:28:10 PM PDT 24
Peak memory 217768 kb
Host smart-d331bb19-7a84-47f8-9251-f399df6f7828
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994696972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.994696972
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.758056907
Short name T446
Test name
Test status
Simulation time 1207669367 ps
CPU time 6.25 seconds
Started Jul 05 05:28:08 PM PDT 24
Finished Jul 05 05:28:16 PM PDT 24
Peak memory 218244 kb
Host smart-4ab74bdc-2b70-49c3-adab-d437a1ea247f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758056907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
prog_failure.758056907
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2603124497
Short name T727
Test name
Test status
Simulation time 665455000 ps
CPU time 20.95 seconds
Started Jul 05 05:28:07 PM PDT 24
Finished Jul 05 05:28:30 PM PDT 24
Peak memory 217740 kb
Host smart-c572c157-43b0-4a79-bedd-5197576f7bb0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603124497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.2603124497
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.516577203
Short name T23
Test name
Test status
Simulation time 506147936 ps
CPU time 7.72 seconds
Started Jul 05 05:28:08 PM PDT 24
Finished Jul 05 05:28:17 PM PDT 24
Peak memory 217720 kb
Host smart-b6dcb21d-7181-417b-a7fa-5f79aa6ca166
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516577203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.516577203
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3922522118
Short name T295
Test name
Test status
Simulation time 1489679522 ps
CPU time 71.02 seconds
Started Jul 05 05:28:06 PM PDT 24
Finished Jul 05 05:29:18 PM PDT 24
Peak memory 268152 kb
Host smart-761b057a-aca0-4c55-a747-10a3c26366d1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922522118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.3922522118
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.956190213
Short name T502
Test name
Test status
Simulation time 1752115956 ps
CPU time 15.46 seconds
Started Jul 05 05:28:07 PM PDT 24
Finished Jul 05 05:28:23 PM PDT 24
Peak memory 251004 kb
Host smart-2d7cb08a-81e1-4e11-b837-c6929ab0d9d1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956190213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_state_post_trans.956190213
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.3233858531
Short name T836
Test name
Test status
Simulation time 107546547 ps
CPU time 2.91 seconds
Started Jul 05 05:28:06 PM PDT 24
Finished Jul 05 05:28:09 PM PDT 24
Peak memory 218228 kb
Host smart-7974655a-a21d-4747-9ea4-aa93ae3b26a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233858531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3233858531
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3373628270
Short name T499
Test name
Test status
Simulation time 307505849 ps
CPU time 11.93 seconds
Started Jul 05 05:28:06 PM PDT 24
Finished Jul 05 05:28:19 PM PDT 24
Peak memory 217724 kb
Host smart-e51eb8bb-d98f-49a5-9c40-21a8d41aa2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373628270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3373628270
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.740676631
Short name T341
Test name
Test status
Simulation time 508231453 ps
CPU time 11.77 seconds
Started Jul 05 05:28:10 PM PDT 24
Finished Jul 05 05:28:23 PM PDT 24
Peak memory 225980 kb
Host smart-56152f6d-6b2a-42ad-8d25-eb762d9dd119
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740676631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.740676631
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.1702318114
Short name T441
Test name
Test status
Simulation time 463359401 ps
CPU time 10.73 seconds
Started Jul 05 05:28:11 PM PDT 24
Finished Jul 05 05:28:23 PM PDT 24
Peak memory 226028 kb
Host smart-5e4583f8-cd8d-4d79-b15d-705bbdfe586a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702318114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.1702318114
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.1777078278
Short name T718
Test name
Test status
Simulation time 561735723 ps
CPU time 8.09 seconds
Started Jul 05 05:28:08 PM PDT 24
Finished Jul 05 05:28:17 PM PDT 24
Peak memory 218204 kb
Host smart-f3a62d1e-b920-4cc6-9750-5d5e84f7f473
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777078278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.1
777078278
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.907797369
Short name T601
Test name
Test status
Simulation time 878966712 ps
CPU time 6.96 seconds
Started Jul 05 05:28:07 PM PDT 24
Finished Jul 05 05:28:16 PM PDT 24
Peak memory 225904 kb
Host smart-1a107a70-4328-46cd-925c-106248f88c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907797369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.907797369
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.1733701720
Short name T470
Test name
Test status
Simulation time 415151648 ps
CPU time 3.83 seconds
Started Jul 05 05:28:02 PM PDT 24
Finished Jul 05 05:28:07 PM PDT 24
Peak memory 217724 kb
Host smart-44fcab10-9830-49a7-9004-aa9411bc7954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733701720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.1733701720
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.2567888518
Short name T756
Test name
Test status
Simulation time 362312579 ps
CPU time 30.93 seconds
Started Jul 05 05:28:09 PM PDT 24
Finished Jul 05 05:28:41 PM PDT 24
Peak memory 250992 kb
Host smart-8bd90f10-4031-4c32-b8c3-1094f311b4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567888518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2567888518
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.630434795
Short name T511
Test name
Test status
Simulation time 196642481 ps
CPU time 6.51 seconds
Started Jul 05 05:28:06 PM PDT 24
Finished Jul 05 05:28:14 PM PDT 24
Peak memory 247116 kb
Host smart-c39a645d-336c-4745-90fc-8dcbf6e5dc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630434795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.630434795
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3375598380
Short name T196
Test name
Test status
Simulation time 34782541878 ps
CPU time 348.79 seconds
Started Jul 05 05:28:07 PM PDT 24
Finished Jul 05 05:33:57 PM PDT 24
Peak memory 283696 kb
Host smart-1cdc4043-60e8-4a47-811b-56914bccd499
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375598380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3375598380
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.390066365
Short name T155
Test name
Test status
Simulation time 94891035818 ps
CPU time 905.3 seconds
Started Jul 05 05:28:07 PM PDT 24
Finished Jul 05 05:43:14 PM PDT 24
Peak memory 389276 kb
Host smart-6acbd9a8-b533-4854-a5f9-0dbcf017ccea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=390066365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.390066365
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1876953027
Short name T636
Test name
Test status
Simulation time 24547457 ps
CPU time 0.92 seconds
Started Jul 05 05:28:15 PM PDT 24
Finished Jul 05 05:28:18 PM PDT 24
Peak memory 211792 kb
Host smart-e79f2d24-d9fa-4bb3-8c98-b5df2acec0a9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876953027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.1876953027
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.2954276887
Short name T637
Test name
Test status
Simulation time 49891525 ps
CPU time 0.87 seconds
Started Jul 05 05:28:09 PM PDT 24
Finished Jul 05 05:28:11 PM PDT 24
Peak memory 208932 kb
Host smart-dad67901-fd6c-4cb8-8453-cef70bd28215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954276887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.2954276887
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.112030632
Short name T68
Test name
Test status
Simulation time 11082064 ps
CPU time 0.85 seconds
Started Jul 05 05:28:09 PM PDT 24
Finished Jul 05 05:28:10 PM PDT 24
Peak memory 208896 kb
Host smart-fe66cecd-70d0-4235-b7ad-81b7f859f907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112030632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.112030632
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.540765858
Short name T837
Test name
Test status
Simulation time 3430142603 ps
CPU time 13.48 seconds
Started Jul 05 05:28:08 PM PDT 24
Finished Jul 05 05:28:22 PM PDT 24
Peak memory 218928 kb
Host smart-fadefac3-2a12-47eb-9cf2-52002f8dd746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540765858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.540765858
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.1964033867
Short name T726
Test name
Test status
Simulation time 3852099759 ps
CPU time 23.05 seconds
Started Jul 05 05:28:09 PM PDT 24
Finished Jul 05 05:28:34 PM PDT 24
Peak memory 217756 kb
Host smart-164a6382-be6b-48f9-88b6-82bec8aef55f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964033867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.1964033867
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1444748326
Short name T524
Test name
Test status
Simulation time 3568395119 ps
CPU time 50.4 seconds
Started Jul 05 05:28:08 PM PDT 24
Finished Jul 05 05:29:00 PM PDT 24
Peak memory 219092 kb
Host smart-0eb3e289-8af3-4db9-860b-0d0e3e96d9db
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444748326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1444748326
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.1553318285
Short name T714
Test name
Test status
Simulation time 251897099 ps
CPU time 3.12 seconds
Started Jul 05 05:28:11 PM PDT 24
Finished Jul 05 05:28:15 PM PDT 24
Peak memory 217692 kb
Host smart-bd8f6648-8f77-4de4-8a83-949e23cc7f4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553318285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.1
553318285
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1018919986
Short name T25
Test name
Test status
Simulation time 709946133 ps
CPU time 6.06 seconds
Started Jul 05 05:28:12 PM PDT 24
Finished Jul 05 05:28:19 PM PDT 24
Peak memory 223024 kb
Host smart-3bba9674-0801-4fae-a393-1ae6428cb84e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018919986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.1018919986
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1749552834
Short name T831
Test name
Test status
Simulation time 846207611 ps
CPU time 11.66 seconds
Started Jul 05 05:28:07 PM PDT 24
Finished Jul 05 05:28:20 PM PDT 24
Peak memory 217736 kb
Host smart-f7b6167b-5b29-4d0f-9210-07a51e1b7bd4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749552834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.1749552834
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.3390512921
Short name T65
Test name
Test status
Simulation time 379190981 ps
CPU time 2.93 seconds
Started Jul 05 05:28:06 PM PDT 24
Finished Jul 05 05:28:10 PM PDT 24
Peak memory 217752 kb
Host smart-49474746-2a47-401c-94b4-b820c4aff5e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390512921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
3390512921
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.4067297999
Short name T767
Test name
Test status
Simulation time 6669195563 ps
CPU time 131.17 seconds
Started Jul 05 05:28:06 PM PDT 24
Finished Jul 05 05:30:19 PM PDT 24
Peak memory 279944 kb
Host smart-70b98d56-2d66-4322-a9dc-349c9f023801
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067297999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.4067297999
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.4058869365
Short name T416
Test name
Test status
Simulation time 879584861 ps
CPU time 29.23 seconds
Started Jul 05 05:28:07 PM PDT 24
Finished Jul 05 05:28:37 PM PDT 24
Peak memory 250412 kb
Host smart-de687b64-8474-443f-b4b4-e84b38202e42
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058869365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.4058869365
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1181566077
Short name T731
Test name
Test status
Simulation time 77659881 ps
CPU time 1.68 seconds
Started Jul 05 05:28:06 PM PDT 24
Finished Jul 05 05:28:09 PM PDT 24
Peak memory 218208 kb
Host smart-e15205f8-d938-44cb-89b7-ae26c4858073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181566077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1181566077
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1940760289
Short name T300
Test name
Test status
Simulation time 951410092 ps
CPU time 13.97 seconds
Started Jul 05 05:28:14 PM PDT 24
Finished Jul 05 05:28:30 PM PDT 24
Peak memory 214616 kb
Host smart-cb93fd72-4a9c-4833-b660-1e0502cd83ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940760289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1940760289
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.4218273724
Short name T707
Test name
Test status
Simulation time 263056394 ps
CPU time 13.66 seconds
Started Jul 05 05:28:06 PM PDT 24
Finished Jul 05 05:28:21 PM PDT 24
Peak memory 218380 kb
Host smart-01c4c41d-39a2-4adf-a2fe-dd7c328273da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218273724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.4218273724
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2267300049
Short name T163
Test name
Test status
Simulation time 264575632 ps
CPU time 9.95 seconds
Started Jul 05 05:28:09 PM PDT 24
Finished Jul 05 05:28:20 PM PDT 24
Peak memory 226052 kb
Host smart-fd539724-2d0c-46f5-a929-952e5582259f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267300049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2267300049
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3711364067
Short name T556
Test name
Test status
Simulation time 325329114 ps
CPU time 12.06 seconds
Started Jul 05 05:28:09 PM PDT 24
Finished Jul 05 05:28:22 PM PDT 24
Peak memory 218252 kb
Host smart-eee4330a-a299-490c-b240-ce09d5638ed6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711364067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3
711364067
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.400575796
Short name T188
Test name
Test status
Simulation time 255932388 ps
CPU time 9.36 seconds
Started Jul 05 05:28:10 PM PDT 24
Finished Jul 05 05:28:20 PM PDT 24
Peak memory 226040 kb
Host smart-8aa4c93d-10a0-4a34-a865-a44ee0273d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400575796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.400575796
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.96816959
Short name T743
Test name
Test status
Simulation time 168083134 ps
CPU time 3.58 seconds
Started Jul 05 05:28:12 PM PDT 24
Finished Jul 05 05:28:16 PM PDT 24
Peak memory 217604 kb
Host smart-f009c4fa-edae-4e95-9278-029156e82d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96816959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.96816959
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.398566263
Short name T581
Test name
Test status
Simulation time 195597039 ps
CPU time 15.06 seconds
Started Jul 05 05:28:12 PM PDT 24
Finished Jul 05 05:28:28 PM PDT 24
Peak memory 250904 kb
Host smart-45d4bfc5-871e-45c7-8bc4-354e99907feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398566263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.398566263
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.2548063770
Short name T323
Test name
Test status
Simulation time 58020366 ps
CPU time 5.92 seconds
Started Jul 05 05:28:08 PM PDT 24
Finished Jul 05 05:28:15 PM PDT 24
Peak memory 246120 kb
Host smart-009f7088-8452-48a0-b429-17f85ed9ec07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548063770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.2548063770
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3694780631
Short name T44
Test name
Test status
Simulation time 19143818956 ps
CPU time 363.34 seconds
Started Jul 05 05:28:07 PM PDT 24
Finished Jul 05 05:34:12 PM PDT 24
Peak memory 226108 kb
Host smart-5a479cea-4f2a-4544-9c05-13c9ba546173
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694780631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3694780631
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2464098718
Short name T367
Test name
Test status
Simulation time 15283446 ps
CPU time 0.93 seconds
Started Jul 05 05:28:07 PM PDT 24
Finished Jul 05 05:28:09 PM PDT 24
Peak memory 217736 kb
Host smart-c58e2661-c5fa-4542-bba9-28d43829191b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464098718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.2464098718
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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