Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

93513012

1

T1

22347

T2

22704

T3

29765

auto[1]

1333692

1

T1

1584

T13

2871

T15

2376

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

93553168

1

T1

23139

T2

22704

T3

29765

auto[1]

1293536

1

T1

792

T12

99

T13

2970

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6472244	1			T1	6843		T2	6443		T3	81
auto[IdleSt]	20334368	1			T1	1999		T2	2242		T3	29684
auto[ClkMuxSt]	32364	1			T1	59		T2	70		T4	12
auto[CntIncrSt]	32095	1			T1	59		T2	70		T4	12
auto[CntProgSt]	1620042	1			T1	893		T2	2507		T4	29
auto[TransCheckSt]	25013	1			T1	46		T2	70		T4	12
auto[TokenHashSt]	38342946	1			T1	1595		T2	788		T4	231
auto[FlashRmaSt]	32863	1			T1	126		T4	44		T11	79
auto[TokenCheck0St]	11382	1			T1	38		T4	12		T11	20
auto[TokenCheck1St]	8475	1			T1	25		T4	12		T11	4
auto[TransProgSt]	451620	1			T1	619		T4	29		T6	130
auto[PostTransSt]	11464420	1			T1	7798		T2	10514		T4	926
auto[ScrapSt]	122405	1			T6	334		T18	732		T36	27
auto[EscalateSt]	6070159	1			T1	3014		T12	106		T13	8111
auto[InvalidSt]	9824594	1			T1	817		T13	8203		T15	4565

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1714	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	9824594	1			T1	817		T13	8203		T15	4565
EscalateSt	6070159	1			T1	3014		T12	106		T13	8111
ScrapSt	122405	1			T6	334		T18	732		T36	27
PostTransSt	11464420	1			T1	7798		T2	10514		T4	926
TransProgSt	451620	1			T1	619		T4	29		T6	130
TokenCheck1St	8475	1			T1	25		T4	12		T11	4
TokenCheck0St	11382	1			T1	38		T4	12		T11	20
FlashRmaSt	32863	1			T1	126		T4	44		T11	79
TokenHashSt	38342946	1			T1	1595		T2	788		T4	231
TransCheckSt	25013	1			T1	46		T2	70		T4	12
CntProgSt	1620042	1			T1	893		T2	2507		T4	29
CntIncrSt	32095	1			T1	59		T2	70		T4	12
ClkMuxSt	32364	1			T1	59		T2	70		T4	12
IdleSt	20334368	1			T1	1999		T2	2242		T3	29684
ResetSt	6472244	1			T1	6843		T2	6443		T3	81
arcs[ResetSt=>IdleSt]	48991	1			T1	71		T2	71		T3	1
arcs[IdleSt=>ScrapSt]	238	1			T6	1		T18	1		T36	2
arcs[IdleSt=>ClkMuxSt]	32161	1			T1	59		T2	70		T4	12
arcs[ClkMuxSt=>CntIncrSt]	32095	1			T1	59		T2	70		T4	12
arcs[CntIncrSt=>PostTransSt]	1554	1			T6	13		T16	8		T17	16
arcs[CntIncrSt=>CntProgSt]	30462	1			T1	59		T2	70		T4	12
arcs[CntProgSt=>PostTransSt]	4417	1			T1	13		T12	1		T6	34
arcs[CntProgSt=>TransCheckSt]	25013	1			T1	46		T2	70		T4	12
arcs[TransCheckSt=>PostTransSt]	3431	1			T11	38		T20	34		T6	11
arcs[TransCheckSt=>TokenHashSt]	21458	1			T1	46		T2	70		T4	12
arcs[TokenHashSt=>PostTransSt]	9271	1			T1	8		T2	70		T11	9
arcs[TokenHashSt=>FlashRmaSt]	11482	1			T1	38		T4	12		T11	20
arcs[FlashRmaSt=>TokenCheck0St]	11382	1			T1	38		T4	12		T11	20
arcs[TokenCheck0St=>PostTransSt]	2880	1			T1	13		T11	16		T20	14
arcs[TokenCheck0St=>TokenCheck1St]	8475	1			T1	25		T4	12		T11	4
arcs[TokenCheck1St=>PostTransSt]	620	1			T11	4		T20	11		T6	1
arcs[TransProgSt=>PostTransSt]	6956	1			T1	25		T4	12		T6	65
arcs[IdleSt=>EscalateSt]	201	1			T19	3		T46	8		T47	8
arcs[ClkMuxSt=>EscalateSt]	66	1			T19	1		T46	3		T22	2
arcs[CntIncrSt=>EscalateSt]	79	1			T19	2		T46	2		T47	1
arcs[CntProgSt=>EscalateSt]	1032	1			T19	4		T46	32		T47	7
arcs[TransCheckSt=>EscalateSt]	124	1			T19	6		T47	5		T22	7
arcs[TokenHashSt=>EscalateSt]	704	1			T6	3		T19	23		T46	11
arcs[FlashRmaSt=>EscalateSt]	100	1			T19	1		T46	1		T22	1
arcs[TokenCheck0St=>EscalateSt]	27	1			T47	1		T22	1		T53	1
arcs[TokenCheck1St=>EscalateSt]	157	1			T19	4		T46	4		T47	6
arcs[TransProgSt=>EscalateSt]	742	1			T19	5		T46	19		T47	5
arcs[PostTransSt=>EscalateSt]	4684	1			T1	13		T12	1		T6	34
arcs[InvalidSt=>EscalateSt]	12612	1			T1	11		T13	59		T15	61

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6472095	1			T1	6843		T2	6443		T3	81
auto[0]	auto[IdleSt]	20334236	1			T1	1999		T2	2242		T3	29684
auto[0]	auto[ClkMuxSt]	32312	1			T1	59		T2	70		T4	12
auto[0]	auto[CntIncrSt]	32048	1			T1	59		T2	70		T4	12
auto[0]	auto[CntProgSt]	1619341	1			T1	893		T2	2507		T4	29
auto[0]	auto[TransCheckSt]	24934	1			T1	46		T2	70		T4	12
auto[0]	auto[TokenHashSt]	38342475	1			T1	1595		T2	788		T4	231
auto[0]	auto[FlashRmaSt]	32791	1			T1	126		T4	44		T11	79
auto[0]	auto[TokenCheck0St]	11364	1			T1	38		T4	12		T11	20
auto[0]	auto[TokenCheck1St]	8363	1			T1	25		T4	12		T11	4
auto[0]	auto[TransProgSt]	451114	1			T1	619		T4	29		T6	130
auto[0]	auto[PostTransSt]	11462051	1			T1	7790		T2	10514		T4	926
auto[0]	auto[ScrapSt]	122376	1			T6	334		T18	732		T36	27
auto[0]	auto[EscalateSt]	4747656	1			T1	1446		T12	106		T13	5269
auto[0]	auto[InvalidSt]	9818142	1			T1	809		T13	8174		T15	4541
auto[1]	auto[ResetSt]	149	1			T19	4		T46	6		T47	1
auto[1]	auto[IdleSt]	132	1			T19	1		T46	4		T47	7
auto[1]	auto[ClkMuxSt]	52	1			T19	1		T46	2		T22	1
auto[1]	auto[CntIncrSt]	47	1			T19	2		T22	1		T48	1
auto[1]	auto[CntProgSt]	701	1			T19	3		T46	24		T47	4
auto[1]	auto[TransCheckSt]	79	1			T19	4		T47	5		T22	5
auto[1]	auto[TokenHashSt]	471	1			T6	3		T19	14		T46	8
auto[1]	auto[FlashRmaSt]	72	1			T19	1		T22	1		T48	2
auto[1]	auto[TokenCheck0St]	18	1			T47	1		T53	1		T208	1
auto[1]	auto[TokenCheck1St]	112	1			T19	2		T46	4		T47	2
auto[1]	auto[TransProgSt]	506	1			T19	4		T46	14		T47	3
auto[1]	auto[PostTransSt]	2369	1			T1	8		T6	15		T23	7
auto[1]	auto[ScrapSt]	29	1			T47	2		T49	1		T209	1
auto[1]	auto[EscalateSt]	1322503	1			T1	1568		T13	2842		T15	2352
auto[1]	auto[InvalidSt]	6452	1			T1	8		T13	29		T15	24

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6472100	1			T1	6843		T2	6443		T3	81
auto[0]	auto[IdleSt]	20334224	1			T1	1999		T2	2242		T3	29684
auto[0]	auto[ClkMuxSt]	32327	1			T1	59		T2	70		T4	12
auto[0]	auto[CntIncrSt]	32037	1			T1	59		T2	70		T4	12
auto[0]	auto[CntProgSt]	1619348	1			T1	893		T2	2507		T4	29
auto[0]	auto[TransCheckSt]	24933	1			T1	46		T2	70		T4	12
auto[0]	auto[TokenHashSt]	38342490	1			T1	1595		T2	788		T4	231
auto[0]	auto[FlashRmaSt]	32803	1			T1	126		T4	44		T11	79
auto[0]	auto[TokenCheck0St]	11360	1			T1	38		T4	12		T11	20
auto[0]	auto[TokenCheck1St]	8375	1			T1	25		T4	12		T11	4
auto[0]	auto[TransProgSt]	451134	1			T1	619		T4	29		T6	130
auto[0]	auto[PostTransSt]	11462025	1			T1	7793		T2	10514		T4	926
auto[0]	auto[ScrapSt]	122363	1			T6	334		T18	732		T36	27
auto[0]	auto[EscalateSt]	4787501	1			T1	2230		T12	8		T13	5171
auto[0]	auto[InvalidSt]	9818434	1			T1	814		T13	8173		T15	4528
auto[1]	auto[ResetSt]	144	1			T19	2		T46	8		T47	1
auto[1]	auto[IdleSt]	144	1			T19	2		T46	6		T47	5
auto[1]	auto[ClkMuxSt]	37	1			T19	1		T46	2		T22	2
auto[1]	auto[CntIncrSt]	58	1			T19	1		T46	2		T47	1
auto[1]	auto[CntProgSt]	694	1			T19	3		T46	23		T47	6
auto[1]	auto[TransCheckSt]	80	1			T19	3		T22	4		T53	2
auto[1]	auto[TokenHashSt]	456	1			T19	17		T46	8		T47	9
auto[1]	auto[FlashRmaSt]	60	1			T19	1		T46	1		T22	1
auto[1]	auto[TokenCheck0St]	22	1			T47	1		T22	1		T208	1
auto[1]	auto[TokenCheck1St]	100	1			T19	3		T46	2		T47	5
auto[1]	auto[TransProgSt]	486	1			T19	3		T46	11		T47	4
auto[1]	auto[PostTransSt]	2395	1			T1	5		T12	1		T6	19
auto[1]	auto[ScrapSt]	42	1			T47	1		T48	1		T49	1
auto[1]	auto[EscalateSt]	1282658	1			T1	784		T12	98		T13	2940
auto[1]	auto[InvalidSt]	6160	1			T1	3		T13	30		T15	37