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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.23 97.92 95.56 93.38 100.00 98.52 98.76 96.47


Total test records in report: 987
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T811 /workspace/coverage/default/25.lc_ctrl_jtag_access.1265586052 Jul 06 06:30:47 PM PDT 24 Jul 06 06:30:51 PM PDT 24 1161731763 ps
T812 /workspace/coverage/default/19.lc_ctrl_smoke.3708060447 Jul 06 06:30:35 PM PDT 24 Jul 06 06:30:41 PM PDT 24 309473447 ps
T813 /workspace/coverage/default/40.lc_ctrl_alert_test.791128292 Jul 06 06:31:29 PM PDT 24 Jul 06 06:31:31 PM PDT 24 169250422 ps
T814 /workspace/coverage/default/42.lc_ctrl_security_escalation.138059120 Jul 06 06:31:28 PM PDT 24 Jul 06 06:31:41 PM PDT 24 662989324 ps
T815 /workspace/coverage/default/4.lc_ctrl_smoke.662319235 Jul 06 06:29:39 PM PDT 24 Jul 06 06:29:50 PM PDT 24 361374025 ps
T816 /workspace/coverage/default/26.lc_ctrl_alert_test.3072532440 Jul 06 06:31:03 PM PDT 24 Jul 06 06:31:05 PM PDT 24 21364099 ps
T817 /workspace/coverage/default/34.lc_ctrl_state_failure.2519769152 Jul 06 06:31:16 PM PDT 24 Jul 06 06:31:36 PM PDT 24 634349538 ps
T818 /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2108897266 Jul 06 06:30:30 PM PDT 24 Jul 06 06:30:51 PM PDT 24 2215109497 ps
T819 /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2861831163 Jul 06 06:30:49 PM PDT 24 Jul 06 06:31:00 PM PDT 24 1105532290 ps
T820 /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1100477449 Jul 06 06:29:39 PM PDT 24 Jul 06 06:30:03 PM PDT 24 792158024 ps
T821 /workspace/coverage/default/15.lc_ctrl_stress_all.49121489 Jul 06 06:30:19 PM PDT 24 Jul 06 06:30:38 PM PDT 24 3239907131 ps
T822 /workspace/coverage/default/18.lc_ctrl_jtag_access.440489599 Jul 06 06:30:30 PM PDT 24 Jul 06 06:30:35 PM PDT 24 1097870641 ps
T823 /workspace/coverage/default/19.lc_ctrl_security_escalation.4231683924 Jul 06 06:30:35 PM PDT 24 Jul 06 06:30:44 PM PDT 24 1316048065 ps
T824 /workspace/coverage/default/42.lc_ctrl_alert_test.2352670541 Jul 06 06:31:32 PM PDT 24 Jul 06 06:31:34 PM PDT 24 20761632 ps
T825 /workspace/coverage/default/12.lc_ctrl_prog_failure.3956653824 Jul 06 06:30:09 PM PDT 24 Jul 06 06:30:12 PM PDT 24 77919508 ps
T826 /workspace/coverage/default/36.lc_ctrl_state_failure.3968420003 Jul 06 06:31:21 PM PDT 24 Jul 06 06:31:40 PM PDT 24 994674935 ps
T827 /workspace/coverage/default/2.lc_ctrl_claim_transition_if.272283529 Jul 06 06:29:34 PM PDT 24 Jul 06 06:29:35 PM PDT 24 10776762 ps
T828 /workspace/coverage/default/6.lc_ctrl_alert_test.890877037 Jul 06 06:29:50 PM PDT 24 Jul 06 06:29:52 PM PDT 24 100345913 ps
T829 /workspace/coverage/default/29.lc_ctrl_stress_all.260269175 Jul 06 06:31:03 PM PDT 24 Jul 06 06:36:49 PM PDT 24 46830629681 ps
T830 /workspace/coverage/default/43.lc_ctrl_errors.4133577609 Jul 06 06:31:35 PM PDT 24 Jul 06 06:31:46 PM PDT 24 216617604 ps
T831 /workspace/coverage/default/16.lc_ctrl_sec_token_digest.627511275 Jul 06 06:30:30 PM PDT 24 Jul 06 06:30:38 PM PDT 24 724076438 ps
T832 /workspace/coverage/default/16.lc_ctrl_smoke.2897183943 Jul 06 06:30:21 PM PDT 24 Jul 06 06:30:25 PM PDT 24 166163361 ps
T833 /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1049074419 Jul 06 06:29:53 PM PDT 24 Jul 06 06:30:19 PM PDT 24 3161089633 ps
T834 /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.4089818130 Jul 06 06:30:01 PM PDT 24 Jul 06 06:30:12 PM PDT 24 317926907 ps
T835 /workspace/coverage/default/17.lc_ctrl_state_post_trans.2108969029 Jul 06 06:30:27 PM PDT 24 Jul 06 06:30:35 PM PDT 24 809469369 ps
T836 /workspace/coverage/default/32.lc_ctrl_smoke.569050711 Jul 06 06:31:03 PM PDT 24 Jul 06 06:31:06 PM PDT 24 19389174 ps
T837 /workspace/coverage/default/15.lc_ctrl_state_failure.4093456648 Jul 06 06:30:15 PM PDT 24 Jul 06 06:30:44 PM PDT 24 932120173 ps
T838 /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.903592226 Jul 06 06:29:38 PM PDT 24 Jul 06 06:29:54 PM PDT 24 930011358 ps
T839 /workspace/coverage/default/8.lc_ctrl_errors.1448200839 Jul 06 06:30:00 PM PDT 24 Jul 06 06:30:15 PM PDT 24 1908898590 ps
T840 /workspace/coverage/default/5.lc_ctrl_alert_test.1448772691 Jul 06 06:29:51 PM PDT 24 Jul 06 06:29:53 PM PDT 24 24512612 ps
T69 /workspace/coverage/default/41.lc_ctrl_alert_test.999342550 Jul 06 06:31:32 PM PDT 24 Jul 06 06:31:33 PM PDT 24 61828018 ps
T841 /workspace/coverage/default/4.lc_ctrl_stress_all.320190842 Jul 06 06:29:39 PM PDT 24 Jul 06 06:30:34 PM PDT 24 25317377388 ps
T842 /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2108314281 Jul 06 06:31:00 PM PDT 24 Jul 06 06:31:07 PM PDT 24 769282009 ps
T843 /workspace/coverage/default/45.lc_ctrl_stress_all.3909442699 Jul 06 06:31:37 PM PDT 24 Jul 06 06:33:14 PM PDT 24 3172686377 ps
T844 /workspace/coverage/default/40.lc_ctrl_sec_mubi.1731992253 Jul 06 06:31:27 PM PDT 24 Jul 06 06:31:41 PM PDT 24 1561406997 ps
T845 /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3465887754 Jul 06 06:30:38 PM PDT 24 Jul 06 06:30:50 PM PDT 24 1256843275 ps
T846 /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1638217639 Jul 06 06:30:12 PM PDT 24 Jul 06 06:30:26 PM PDT 24 1432754167 ps
T847 /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2589174977 Jul 06 06:30:28 PM PDT 24 Jul 06 06:30:29 PM PDT 24 45478931 ps
T848 /workspace/coverage/default/49.lc_ctrl_sec_mubi.2196441204 Jul 06 06:31:45 PM PDT 24 Jul 06 06:31:55 PM PDT 24 2581479558 ps
T849 /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.882115690 Jul 06 06:29:50 PM PDT 24 Jul 06 06:29:54 PM PDT 24 346816789 ps
T850 /workspace/coverage/default/2.lc_ctrl_jtag_priority.292096539 Jul 06 06:29:42 PM PDT 24 Jul 06 06:29:53 PM PDT 24 431031448 ps
T851 /workspace/coverage/default/26.lc_ctrl_sec_token_mux.2789328475 Jul 06 06:30:47 PM PDT 24 Jul 06 06:30:54 PM PDT 24 1137337275 ps
T852 /workspace/coverage/default/34.lc_ctrl_security_escalation.1253520500 Jul 06 06:31:12 PM PDT 24 Jul 06 06:31:22 PM PDT 24 449411024 ps
T70 /workspace/coverage/default/2.lc_ctrl_regwen_during_op.3735324961 Jul 06 06:29:31 PM PDT 24 Jul 06 06:29:41 PM PDT 24 663326636 ps
T853 /workspace/coverage/default/5.lc_ctrl_jtag_priority.2835307096 Jul 06 06:29:47 PM PDT 24 Jul 06 06:29:58 PM PDT 24 3685582926 ps
T854 /workspace/coverage/default/33.lc_ctrl_prog_failure.847556311 Jul 06 06:31:09 PM PDT 24 Jul 06 06:31:13 PM PDT 24 164191936 ps
T855 /workspace/coverage/default/30.lc_ctrl_alert_test.3827780151 Jul 06 06:31:02 PM PDT 24 Jul 06 06:31:04 PM PDT 24 23790004 ps
T856 /workspace/coverage/default/43.lc_ctrl_sec_mubi.2326854219 Jul 06 06:31:33 PM PDT 24 Jul 06 06:31:49 PM PDT 24 294974123 ps
T205 /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3908898253 Jul 06 06:29:34 PM PDT 24 Jul 06 06:29:35 PM PDT 24 11381618 ps
T857 /workspace/coverage/default/0.lc_ctrl_sec_token_mux.311723246 Jul 06 06:29:26 PM PDT 24 Jul 06 06:29:35 PM PDT 24 239223082 ps
T858 /workspace/coverage/default/5.lc_ctrl_security_escalation.1713220036 Jul 06 06:29:50 PM PDT 24 Jul 06 06:29:59 PM PDT 24 1083138160 ps
T859 /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1394052803 Jul 06 06:29:31 PM PDT 24 Jul 06 06:29:48 PM PDT 24 633328472 ps
T112 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.22428166 Jul 06 06:25:40 PM PDT 24 Jul 06 06:25:44 PM PDT 24 557839621 ps
T109 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.62771867 Jul 06 06:25:44 PM PDT 24 Jul 06 06:25:47 PM PDT 24 147512061 ps
T119 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2728222440 Jul 06 06:25:48 PM PDT 24 Jul 06 06:25:59 PM PDT 24 2337221255 ps
T142 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3935970485 Jul 06 06:25:57 PM PDT 24 Jul 06 06:26:12 PM PDT 24 1806218075 ps
T136 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2779522781 Jul 06 06:26:13 PM PDT 24 Jul 06 06:26:14 PM PDT 24 26101515 ps
T113 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3127150193 Jul 06 06:26:11 PM PDT 24 Jul 06 06:26:14 PM PDT 24 142724921 ps
T860 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.467149797 Jul 06 06:25:58 PM PDT 24 Jul 06 06:25:59 PM PDT 24 208824205 ps
T110 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.604927228 Jul 06 06:26:16 PM PDT 24 Jul 06 06:26:21 PM PDT 24 353037738 ps
T114 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2381466271 Jul 06 06:26:16 PM PDT 24 Jul 06 06:26:18 PM PDT 24 43085629 ps
T190 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3797690667 Jul 06 06:26:07 PM PDT 24 Jul 06 06:26:09 PM PDT 24 14985237 ps
T191 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1761999808 Jul 06 06:25:54 PM PDT 24 Jul 06 06:25:55 PM PDT 24 13634820 ps
T200 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.4127972262 Jul 06 06:25:55 PM PDT 24 Jul 06 06:26:09 PM PDT 24 2492427443 ps
T180 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.596015463 Jul 06 06:25:45 PM PDT 24 Jul 06 06:25:47 PM PDT 24 14989551 ps
T111 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1526987054 Jul 06 06:26:14 PM PDT 24 Jul 06 06:26:16 PM PDT 24 218758056 ps
T151 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2653886120 Jul 06 06:25:48 PM PDT 24 Jul 06 06:25:50 PM PDT 24 249999461 ps
T126 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2523641816 Jul 06 06:25:39 PM PDT 24 Jul 06 06:25:43 PM PDT 24 302642215 ps
T192 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3783773162 Jul 06 06:26:07 PM PDT 24 Jul 06 06:26:09 PM PDT 24 87880863 ps
T140 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.35564073 Jul 06 06:26:04 PM PDT 24 Jul 06 06:26:07 PM PDT 24 199546762 ps
T193 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.879200585 Jul 06 06:25:57 PM PDT 24 Jul 06 06:25:59 PM PDT 24 30570517 ps
T141 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2780990489 Jul 06 06:25:47 PM PDT 24 Jul 06 06:25:50 PM PDT 24 108241703 ps
T181 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1084573939 Jul 06 06:26:11 PM PDT 24 Jul 06 06:26:12 PM PDT 24 18632203 ps
T861 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.933824938 Jul 06 06:25:55 PM PDT 24 Jul 06 06:25:57 PM PDT 24 47467384 ps
T862 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2033746918 Jul 06 06:25:44 PM PDT 24 Jul 06 06:25:45 PM PDT 24 115528913 ps
T130 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3127135470 Jul 06 06:26:07 PM PDT 24 Jul 06 06:26:08 PM PDT 24 31760262 ps
T137 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2734450234 Jul 06 06:25:39 PM PDT 24 Jul 06 06:25:42 PM PDT 24 57211412 ps
T115 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1388234129 Jul 06 06:25:38 PM PDT 24 Jul 06 06:25:40 PM PDT 24 79153533 ps
T116 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.754331685 Jul 06 06:25:58 PM PDT 24 Jul 06 06:26:01 PM PDT 24 28383663 ps
T118 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.768540029 Jul 06 06:26:06 PM PDT 24 Jul 06 06:26:10 PM PDT 24 274055135 ps
T194 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1501436634 Jul 06 06:25:39 PM PDT 24 Jul 06 06:25:40 PM PDT 24 53979934 ps
T863 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3878930883 Jul 06 06:25:39 PM PDT 24 Jul 06 06:25:41 PM PDT 24 74577682 ps
T195 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3671610031 Jul 06 06:26:12 PM PDT 24 Jul 06 06:26:14 PM PDT 24 61189413 ps
T122 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4018022239 Jul 06 06:26:01 PM PDT 24 Jul 06 06:26:05 PM PDT 24 252379398 ps
T138 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.505524028 Jul 06 06:25:54 PM PDT 24 Jul 06 06:25:56 PM PDT 24 102550834 ps
T125 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.476936837 Jul 06 06:26:06 PM PDT 24 Jul 06 06:26:10 PM PDT 24 173382515 ps
T864 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2003555427 Jul 06 06:25:57 PM PDT 24 Jul 06 06:26:00 PM PDT 24 70831754 ps
T152 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1174953099 Jul 06 06:26:14 PM PDT 24 Jul 06 06:26:15 PM PDT 24 31522931 ps
T153 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.938812233 Jul 06 06:26:18 PM PDT 24 Jul 06 06:26:21 PM PDT 24 464067178 ps
T154 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1824635944 Jul 06 06:25:57 PM PDT 24 Jul 06 06:25:58 PM PDT 24 101631087 ps
T196 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.126951839 Jul 06 06:25:40 PM PDT 24 Jul 06 06:25:41 PM PDT 24 72777842 ps
T139 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2316828123 Jul 06 06:26:02 PM PDT 24 Jul 06 06:26:05 PM PDT 24 56272633 ps
T865 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2539768583 Jul 06 06:26:08 PM PDT 24 Jul 06 06:26:10 PM PDT 24 204424715 ps
T866 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3724703138 Jul 06 06:25:30 PM PDT 24 Jul 06 06:25:31 PM PDT 24 837585286 ps
T867 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1036739360 Jul 06 06:26:03 PM PDT 24 Jul 06 06:26:10 PM PDT 24 431674878 ps
T868 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3559465757 Jul 06 06:25:44 PM PDT 24 Jul 06 06:25:48 PM PDT 24 235570946 ps
T197 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.684443950 Jul 06 06:25:47 PM PDT 24 Jul 06 06:25:49 PM PDT 24 140349321 ps
T869 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2298942229 Jul 06 06:25:39 PM PDT 24 Jul 06 06:25:40 PM PDT 24 149224159 ps
T870 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2899029599 Jul 06 06:26:12 PM PDT 24 Jul 06 06:26:14 PM PDT 24 21531458 ps
T871 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2121160782 Jul 06 06:25:40 PM PDT 24 Jul 06 06:26:05 PM PDT 24 1161034858 ps
T872 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2916502106 Jul 06 06:26:00 PM PDT 24 Jul 06 06:26:01 PM PDT 24 37513130 ps
T873 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2785615347 Jul 06 06:25:35 PM PDT 24 Jul 06 06:25:36 PM PDT 24 11807011 ps
T874 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2963041176 Jul 06 06:26:01 PM PDT 24 Jul 06 06:26:19 PM PDT 24 700974975 ps
T875 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.711146201 Jul 06 06:26:12 PM PDT 24 Jul 06 06:26:15 PM PDT 24 151740522 ps
T876 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.4113524036 Jul 06 06:25:31 PM PDT 24 Jul 06 06:25:33 PM PDT 24 160282994 ps
T877 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4126475387 Jul 06 06:25:58 PM PDT 24 Jul 06 06:26:03 PM PDT 24 411209234 ps
T878 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2355467043 Jul 06 06:25:52 PM PDT 24 Jul 06 06:25:54 PM PDT 24 75922028 ps
T182 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.620110032 Jul 06 06:25:35 PM PDT 24 Jul 06 06:25:36 PM PDT 24 12943655 ps
T879 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3550611461 Jul 06 06:26:01 PM PDT 24 Jul 06 06:26:03 PM PDT 24 152230562 ps
T880 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2475765528 Jul 06 06:25:44 PM PDT 24 Jul 06 06:25:46 PM PDT 24 23778488 ps
T881 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.4098049342 Jul 06 06:26:02 PM PDT 24 Jul 06 06:26:09 PM PDT 24 1158120895 ps
T882 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2156626850 Jul 06 06:25:30 PM PDT 24 Jul 06 06:25:44 PM PDT 24 3308034214 ps
T883 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.358505228 Jul 06 06:25:43 PM PDT 24 Jul 06 06:25:46 PM PDT 24 274167454 ps
T884 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2978105063 Jul 06 06:25:44 PM PDT 24 Jul 06 06:25:46 PM PDT 24 100677409 ps
T885 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2613288986 Jul 06 06:26:10 PM PDT 24 Jul 06 06:26:11 PM PDT 24 46505547 ps
T886 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3710862996 Jul 06 06:25:56 PM PDT 24 Jul 06 06:25:58 PM PDT 24 75416002 ps
T887 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1273731622 Jul 06 06:26:10 PM PDT 24 Jul 06 06:26:11 PM PDT 24 16309345 ps
T888 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3323758889 Jul 06 06:25:53 PM PDT 24 Jul 06 06:25:54 PM PDT 24 33259947 ps
T889 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1520871436 Jul 06 06:26:12 PM PDT 24 Jul 06 06:26:14 PM PDT 24 57303161 ps
T183 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3076235338 Jul 06 06:26:16 PM PDT 24 Jul 06 06:26:18 PM PDT 24 34686456 ps
T184 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.722201116 Jul 06 06:25:58 PM PDT 24 Jul 06 06:25:59 PM PDT 24 14445719 ps
T890 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3233814068 Jul 06 06:25:43 PM PDT 24 Jul 06 06:25:45 PM PDT 24 767309207 ps
T891 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.650626471 Jul 06 06:26:16 PM PDT 24 Jul 06 06:26:18 PM PDT 24 43900082 ps
T892 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2340206715 Jul 06 06:25:43 PM PDT 24 Jul 06 06:25:44 PM PDT 24 16688465 ps
T893 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3285217323 Jul 06 06:25:48 PM PDT 24 Jul 06 06:25:50 PM PDT 24 107444828 ps
T894 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3576408313 Jul 06 06:26:04 PM PDT 24 Jul 06 06:26:06 PM PDT 24 177549588 ps
T895 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.239441760 Jul 06 06:26:02 PM PDT 24 Jul 06 06:26:04 PM PDT 24 19056958 ps
T896 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3356383064 Jul 06 06:25:53 PM PDT 24 Jul 06 06:25:55 PM PDT 24 230915888 ps
T897 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.719542827 Jul 06 06:25:43 PM PDT 24 Jul 06 06:25:44 PM PDT 24 35671018 ps
T898 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3931528421 Jul 06 06:26:12 PM PDT 24 Jul 06 06:26:14 PM PDT 24 92347938 ps
T899 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1187409786 Jul 06 06:26:00 PM PDT 24 Jul 06 06:26:03 PM PDT 24 1395593522 ps
T900 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.4233616918 Jul 06 06:25:30 PM PDT 24 Jul 06 06:25:40 PM PDT 24 748184714 ps
T901 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3664154312 Jul 06 06:26:04 PM PDT 24 Jul 06 06:26:09 PM PDT 24 1629540540 ps
T902 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.161459221 Jul 06 06:25:51 PM PDT 24 Jul 06 06:25:55 PM PDT 24 301098066 ps
T903 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3909324913 Jul 06 06:25:30 PM PDT 24 Jul 06 06:25:31 PM PDT 24 325552506 ps
T123 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1035165133 Jul 06 06:26:07 PM PDT 24 Jul 06 06:26:11 PM PDT 24 116615465 ps
T904 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2703676209 Jul 06 06:26:09 PM PDT 24 Jul 06 06:26:11 PM PDT 24 45900708 ps
T905 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3996344343 Jul 06 06:25:46 PM PDT 24 Jul 06 06:25:48 PM PDT 24 45733577 ps
T127 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3979189262 Jul 06 06:26:07 PM PDT 24 Jul 06 06:26:10 PM PDT 24 206675906 ps
T906 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.581069497 Jul 06 06:26:04 PM PDT 24 Jul 06 06:26:06 PM PDT 24 409713798 ps
T185 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.370186653 Jul 06 06:25:50 PM PDT 24 Jul 06 06:25:52 PM PDT 24 41803931 ps
T907 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2080935509 Jul 06 06:25:35 PM PDT 24 Jul 06 06:25:38 PM PDT 24 375156881 ps
T908 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2614411178 Jul 06 06:26:11 PM PDT 24 Jul 06 06:26:13 PM PDT 24 189298994 ps
T909 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1794390038 Jul 06 06:25:54 PM PDT 24 Jul 06 06:25:57 PM PDT 24 168073505 ps
T910 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2425878419 Jul 06 06:25:35 PM PDT 24 Jul 06 06:25:52 PM PDT 24 5427491080 ps
T911 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2809353608 Jul 06 06:26:18 PM PDT 24 Jul 06 06:26:20 PM PDT 24 46838760 ps
T186 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.271418420 Jul 06 06:26:06 PM PDT 24 Jul 06 06:26:07 PM PDT 24 39614359 ps
T129 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1448587582 Jul 06 06:26:12 PM PDT 24 Jul 06 06:26:15 PM PDT 24 206405832 ps
T187 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2957385865 Jul 06 06:25:40 PM PDT 24 Jul 06 06:25:41 PM PDT 24 52546602 ps
T912 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.906926040 Jul 06 06:25:44 PM PDT 24 Jul 06 06:25:46 PM PDT 24 85553011 ps
T913 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.53367739 Jul 06 06:26:12 PM PDT 24 Jul 06 06:26:13 PM PDT 24 19080674 ps
T914 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2716283615 Jul 06 06:25:36 PM PDT 24 Jul 06 06:25:37 PM PDT 24 30365870 ps
T915 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1076126347 Jul 06 06:26:18 PM PDT 24 Jul 06 06:26:19 PM PDT 24 25525587 ps
T916 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1536715982 Jul 06 06:26:11 PM PDT 24 Jul 06 06:26:12 PM PDT 24 258853035 ps
T917 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2068438536 Jul 06 06:26:04 PM PDT 24 Jul 06 06:26:06 PM PDT 24 202360893 ps
T918 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3021956312 Jul 06 06:25:55 PM PDT 24 Jul 06 06:25:56 PM PDT 24 55363131 ps
T919 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2581762685 Jul 06 06:25:59 PM PDT 24 Jul 06 06:26:00 PM PDT 24 56021483 ps
T920 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1763255530 Jul 06 06:25:35 PM PDT 24 Jul 06 06:25:38 PM PDT 24 90953147 ps
T921 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3303186723 Jul 06 06:26:02 PM PDT 24 Jul 06 06:26:04 PM PDT 24 16732567 ps
T133 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.711711319 Jul 06 06:25:35 PM PDT 24 Jul 06 06:25:38 PM PDT 24 129930835 ps
T132 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3006815775 Jul 06 06:26:11 PM PDT 24 Jul 06 06:26:14 PM PDT 24 63980329 ps
T922 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.164312824 Jul 06 06:25:44 PM PDT 24 Jul 06 06:25:46 PM PDT 24 23523257 ps
T923 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2193232491 Jul 06 06:25:58 PM PDT 24 Jul 06 06:26:07 PM PDT 24 632185766 ps
T128 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2438627735 Jul 06 06:25:58 PM PDT 24 Jul 06 06:26:01 PM PDT 24 114638520 ps
T134 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2384603050 Jul 06 06:25:51 PM PDT 24 Jul 06 06:25:54 PM PDT 24 108910551 ps
T188 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2229124429 Jul 06 06:26:07 PM PDT 24 Jul 06 06:26:08 PM PDT 24 33821682 ps
T924 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.218708791 Jul 06 06:26:02 PM PDT 24 Jul 06 06:26:15 PM PDT 24 8420535225 ps
T925 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1360313949 Jul 06 06:26:09 PM PDT 24 Jul 06 06:26:11 PM PDT 24 110664620 ps
T926 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2585684795 Jul 06 06:25:58 PM PDT 24 Jul 06 06:26:00 PM PDT 24 110301459 ps
T927 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3333962930 Jul 06 06:26:06 PM PDT 24 Jul 06 06:26:10 PM PDT 24 231002568 ps
T928 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.4135250707 Jul 06 06:25:59 PM PDT 24 Jul 06 06:26:01 PM PDT 24 59918445 ps
T189 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1051384319 Jul 06 06:25:36 PM PDT 24 Jul 06 06:25:38 PM PDT 24 53741257 ps
T929 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3969158683 Jul 06 06:26:14 PM PDT 24 Jul 06 06:26:16 PM PDT 24 227962093 ps
T930 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1438260845 Jul 06 06:25:56 PM PDT 24 Jul 06 06:25:59 PM PDT 24 557881006 ps
T931 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1778083548 Jul 06 06:25:46 PM PDT 24 Jul 06 06:25:48 PM PDT 24 161353099 ps
T932 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3298061652 Jul 06 06:25:57 PM PDT 24 Jul 06 06:25:58 PM PDT 24 19581009 ps
T933 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1643630296 Jul 06 06:26:10 PM PDT 24 Jul 06 06:26:14 PM PDT 24 55190268 ps
T934 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2340939243 Jul 06 06:26:10 PM PDT 24 Jul 06 06:26:12 PM PDT 24 67188779 ps
T131 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1232522794 Jul 06 06:26:07 PM PDT 24 Jul 06 06:26:10 PM PDT 24 105029433 ps
T935 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1454951113 Jul 06 06:25:46 PM PDT 24 Jul 06 06:25:48 PM PDT 24 333817593 ps
T124 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3683165898 Jul 06 06:26:07 PM PDT 24 Jul 06 06:26:11 PM PDT 24 118367953 ps
T936 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.897682603 Jul 06 06:26:07 PM PDT 24 Jul 06 06:26:08 PM PDT 24 97088212 ps
T937 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2106321401 Jul 06 06:25:55 PM PDT 24 Jul 06 06:25:57 PM PDT 24 22516970 ps
T938 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.4041369077 Jul 06 06:25:48 PM PDT 24 Jul 06 06:25:50 PM PDT 24 180953560 ps
T939 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1857569485 Jul 06 06:25:35 PM PDT 24 Jul 06 06:25:45 PM PDT 24 1420017607 ps
T121 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.246747400 Jul 06 06:26:19 PM PDT 24 Jul 06 06:26:23 PM PDT 24 79870650 ps
T940 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3107481439 Jul 06 06:26:10 PM PDT 24 Jul 06 06:26:12 PM PDT 24 21766101 ps
T941 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3772984265 Jul 06 06:25:53 PM PDT 24 Jul 06 06:26:02 PM PDT 24 337832278 ps
T942 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3505707226 Jul 06 06:25:38 PM PDT 24 Jul 06 06:25:40 PM PDT 24 14583184 ps
T943 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1698864939 Jul 06 06:26:02 PM PDT 24 Jul 06 06:26:03 PM PDT 24 78668530 ps
T944 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2923438362 Jul 06 06:25:35 PM PDT 24 Jul 06 06:25:38 PM PDT 24 98824202 ps
T945 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.180502372 Jul 06 06:26:11 PM PDT 24 Jul 06 06:26:12 PM PDT 24 43396017 ps
T946 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3412947009 Jul 06 06:26:13 PM PDT 24 Jul 06 06:26:14 PM PDT 24 15623332 ps
T947 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3465867453 Jul 06 06:26:01 PM PDT 24 Jul 06 06:26:03 PM PDT 24 222935567 ps
T948 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.34179334 Jul 06 06:25:30 PM PDT 24 Jul 06 06:25:31 PM PDT 24 75792796 ps
T949 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3629100282 Jul 06 06:25:59 PM PDT 24 Jul 06 06:26:01 PM PDT 24 175892098 ps
T117 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2618978189 Jul 06 06:26:07 PM PDT 24 Jul 06 06:26:10 PM PDT 24 64821530 ps
T950 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3663336552 Jul 06 06:25:45 PM PDT 24 Jul 06 06:25:47 PM PDT 24 39389625 ps
T951 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.640212073 Jul 06 06:25:49 PM PDT 24 Jul 06 06:25:50 PM PDT 24 42585101 ps
T952 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2025549644 Jul 06 06:25:47 PM PDT 24 Jul 06 06:25:52 PM PDT 24 191227908 ps
T953 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1105530006 Jul 06 06:26:11 PM PDT 24 Jul 06 06:26:13 PM PDT 24 103728545 ps
T120 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3215350817 Jul 06 06:26:02 PM PDT 24 Jul 06 06:26:05 PM PDT 24 577896857 ps
T954 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.560901642 Jul 06 06:25:42 PM PDT 24 Jul 06 06:25:45 PM PDT 24 34939405 ps
T955 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3442983901 Jul 06 06:26:12 PM PDT 24 Jul 06 06:26:13 PM PDT 24 43919502 ps
T956 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.555113859 Jul 06 06:25:36 PM PDT 24 Jul 06 06:25:39 PM PDT 24 115260766 ps
T957 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3648544065 Jul 06 06:25:50 PM PDT 24 Jul 06 06:25:52 PM PDT 24 56918568 ps
T958 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2871318641 Jul 06 06:25:39 PM PDT 24 Jul 06 06:25:59 PM PDT 24 1667209774 ps
T959 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3552694142 Jul 06 06:26:16 PM PDT 24 Jul 06 06:26:18 PM PDT 24 34987293 ps
T960 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1779950973 Jul 06 06:26:03 PM PDT 24 Jul 06 06:26:05 PM PDT 24 55041240 ps
T961 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2186181497 Jul 06 06:25:51 PM PDT 24 Jul 06 06:25:53 PM PDT 24 38720704 ps
T962 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1275038112 Jul 06 06:25:47 PM PDT 24 Jul 06 06:25:49 PM PDT 24 332092898 ps
T963 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.162618268 Jul 06 06:25:47 PM PDT 24 Jul 06 06:25:48 PM PDT 24 190866992 ps
T964 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3390714206 Jul 06 06:26:02 PM PDT 24 Jul 06 06:26:04 PM PDT 24 111862773 ps
T965 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3844520207 Jul 06 06:25:35 PM PDT 24 Jul 06 06:25:38 PM PDT 24 63888788 ps
T966 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1085201410 Jul 06 06:25:54 PM PDT 24 Jul 06 06:25:56 PM PDT 24 204048383 ps
T967 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1079597169 Jul 06 06:26:12 PM PDT 24 Jul 06 06:26:16 PM PDT 24 251331746 ps
T968 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3838323981 Jul 06 06:25:44 PM PDT 24 Jul 06 06:26:07 PM PDT 24 3324232351 ps
T969 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.4027177795 Jul 06 06:26:09 PM PDT 24 Jul 06 06:26:11 PM PDT 24 243767732 ps
T970 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.64256039 Jul 06 06:25:56 PM PDT 24 Jul 06 06:25:57 PM PDT 24 18872987 ps
T971 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1297102327 Jul 06 06:26:06 PM PDT 24 Jul 06 06:26:08 PM PDT 24 16008053 ps
T972 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1127646516 Jul 06 06:25:57 PM PDT 24 Jul 06 06:25:59 PM PDT 24 306193623 ps
T973 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3617208190 Jul 06 06:25:51 PM PDT 24 Jul 06 06:25:52 PM PDT 24 35113669 ps
T974 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1985519705 Jul 06 06:25:34 PM PDT 24 Jul 06 06:25:36 PM PDT 24 167643827 ps
T975 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.623011153 Jul 06 06:25:33 PM PDT 24 Jul 06 06:25:35 PM PDT 24 19443028 ps
T976 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.170750040 Jul 06 06:26:13 PM PDT 24 Jul 06 06:26:15 PM PDT 24 69164250 ps
T977 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3617758168 Jul 06 06:25:41 PM PDT 24 Jul 06 06:25:43 PM PDT 24 41269463 ps
T978 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1040111756 Jul 06 06:25:47 PM PDT 24 Jul 06 06:25:50 PM PDT 24 107682819 ps
T979 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2631691175 Jul 06 06:25:33 PM PDT 24 Jul 06 06:25:35 PM PDT 24 30932050 ps
T980 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3561074653 Jul 06 06:26:03 PM PDT 24 Jul 06 06:26:16 PM PDT 24 491165672 ps
T981 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1461939963 Jul 06 06:25:48 PM PDT 24 Jul 06 06:25:49 PM PDT 24 12758959 ps
T982 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2251688702 Jul 06 06:26:07 PM PDT 24 Jul 06 06:26:09 PM PDT 24 244320115 ps
T983 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3787934441 Jul 06 06:25:30 PM PDT 24 Jul 06 06:25:32 PM PDT 24 148155115 ps
T984 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1776276359 Jul 06 06:25:53 PM PDT 24 Jul 06 06:26:02 PM PDT 24 1015089163 ps
T985 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1379926159 Jul 06 06:25:45 PM PDT 24 Jul 06 06:25:46 PM PDT 24 20831033 ps
T986 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.33805873 Jul 06 06:25:54 PM PDT 24 Jul 06 06:25:57 PM PDT 24 197949375 ps
T135 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.315305121 Jul 06 06:26:12 PM PDT 24 Jul 06 06:26:15 PM PDT 24 255147646 ps
T987 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1376952164 Jul 06 06:25:44 PM PDT 24 Jul 06 06:25:46 PM PDT 24 20496881 ps

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.1490175871
Short name T1
Test name
Test status
Simulation time 957307832 ps
CPU time 10.02 seconds
Started Jul 06 06:31:08 PM PDT 24
Finished Jul 06 06:31:18 PM PDT 24
Peak memory 226008 kb
Host smart-4c77b8d1-51a6-4d7a-a3d5-a770a24ac1b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490175871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.1490175871
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.2195810349
Short name T18
Test name
Test status
Simulation time 7260666169 ps
CPU time 141.19 seconds
Started Jul 06 06:31:05 PM PDT 24
Finished Jul 06 06:33:28 PM PDT 24
Peak memory 283328 kb
Host smart-f0d86deb-aade-4216-bdf7-cf8bc35b6256
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2195810349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.2195810349
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.4245594329
Short name T19
Test name
Test status
Simulation time 297639298 ps
CPU time 7.78 seconds
Started Jul 06 06:29:40 PM PDT 24
Finished Jul 06 06:29:48 PM PDT 24
Peak memory 224664 kb
Host smart-f29232c7-e5ca-4883-bdf4-95f41a01949f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245594329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.4245594329
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.3663622296
Short name T57
Test name
Test status
Simulation time 14906477414 ps
CPU time 328.78 seconds
Started Jul 06 06:31:21 PM PDT 24
Finished Jul 06 06:36:50 PM PDT 24
Peak memory 283736 kb
Host smart-8a208735-00c3-44b5-8b74-9a244074a357
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3663622296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.3663622296
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.760884373
Short name T47
Test name
Test status
Simulation time 522077961 ps
CPU time 7.71 seconds
Started Jul 06 06:29:38 PM PDT 24
Finished Jul 06 06:29:46 PM PDT 24
Peak memory 224816 kb
Host smart-6c55d6b3-ab8d-4334-ba64-aab109f506ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760884373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.760884373
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.229522822
Short name T145
Test name
Test status
Simulation time 10139509099 ps
CPU time 336.92 seconds
Started Jul 06 06:30:24 PM PDT 24
Finished Jul 06 06:36:01 PM PDT 24
Peak memory 263544 kb
Host smart-0627fb09-bbeb-4033-967f-4d2c0ab00d1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=229522822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.229522822
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.3975665621
Short name T52
Test name
Test status
Simulation time 673784614 ps
CPU time 23.72 seconds
Started Jul 06 06:29:23 PM PDT 24
Finished Jul 06 06:29:47 PM PDT 24
Peak memory 284360 kb
Host smart-3d3f185a-98e2-4157-a8f5-f1cc4c6e11fc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975665621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3975665621
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3055822339
Short name T11
Test name
Test status
Simulation time 225887163 ps
CPU time 8.73 seconds
Started Jul 06 06:30:02 PM PDT 24
Finished Jul 06 06:30:11 PM PDT 24
Peak memory 218180 kb
Host smart-691e1625-57ba-4edf-b5bb-a933ca5be284
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055822339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3055822339
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.62771867
Short name T109
Test name
Test status
Simulation time 147512061 ps
CPU time 1.92 seconds
Started Jul 06 06:25:44 PM PDT 24
Finished Jul 06 06:25:47 PM PDT 24
Peak memory 221760 kb
Host smart-ba185448-379b-4c5b-b21f-6c095e5030f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62771867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_er
r.62771867
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.542216066
Short name T9
Test name
Test status
Simulation time 1332032098 ps
CPU time 5.25 seconds
Started Jul 06 06:31:35 PM PDT 24
Finished Jul 06 06:31:40 PM PDT 24
Peak memory 217388 kb
Host smart-87125b71-4e3e-4f37-870f-dfd786a64c02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542216066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.542216066
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4018022239
Short name T122
Test name
Test status
Simulation time 252379398 ps
CPU time 3.95 seconds
Started Jul 06 06:26:01 PM PDT 24
Finished Jul 06 06:26:05 PM PDT 24
Peak memory 217740 kb
Host smart-f86e0e9a-d09f-4455-9073-bbee66ca7bd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401802
2239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4018022239
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.2576502063
Short name T164
Test name
Test status
Simulation time 819771607 ps
CPU time 16.39 seconds
Started Jul 06 06:30:59 PM PDT 24
Finished Jul 06 06:31:16 PM PDT 24
Peak memory 226044 kb
Host smart-94ca7ef0-1161-47db-9fc4-0c61f2d50065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576502063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2576502063
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.4248380708
Short name T81
Test name
Test status
Simulation time 24016966 ps
CPU time 0.86 seconds
Started Jul 06 06:31:36 PM PDT 24
Finished Jul 06 06:31:38 PM PDT 24
Peak memory 208772 kb
Host smart-5ce7a711-3eac-4f39-ac72-47beeb7df4e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248380708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.4248380708
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.620110032
Short name T182
Test name
Test status
Simulation time 12943655 ps
CPU time 1.15 seconds
Started Jul 06 06:25:35 PM PDT 24
Finished Jul 06 06:25:36 PM PDT 24
Peak memory 210012 kb
Host smart-21528982-87df-45b1-b38a-7b4b861add3d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620110032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset
.620110032
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.280094865
Short name T38
Test name
Test status
Simulation time 85686999921 ps
CPU time 2158.69 seconds
Started Jul 06 06:31:21 PM PDT 24
Finished Jul 06 07:07:20 PM PDT 24
Peak memory 630396 kb
Host smart-da3fac89-0ed0-43ee-b9b1-c6808fdd7665
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=280094865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.280094865
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.768540029
Short name T118
Test name
Test status
Simulation time 274055135 ps
CPU time 3.57 seconds
Started Jul 06 06:26:06 PM PDT 24
Finished Jul 06 06:26:10 PM PDT 24
Peak memory 217436 kb
Host smart-439a5db3-8881-4870-b944-11874061aed4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768540029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.768540029
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.246747400
Short name T121
Test name
Test status
Simulation time 79870650 ps
CPU time 3.75 seconds
Started Jul 06 06:26:19 PM PDT 24
Finished Jul 06 06:26:23 PM PDT 24
Peak memory 217584 kb
Host smart-58f5b95c-c23e-47eb-9b7b-670e8bf1b998
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246747400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_
err.246747400
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3935471336
Short name T6
Test name
Test status
Simulation time 51166741523 ps
CPU time 203.52 seconds
Started Jul 06 06:31:04 PM PDT 24
Finished Jul 06 06:34:28 PM PDT 24
Peak memory 249248 kb
Host smart-6200f029-cdd9-4051-aaeb-ce43cd045dd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935471336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3935471336
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1035165133
Short name T123
Test name
Test status
Simulation time 116615465 ps
CPU time 3.16 seconds
Started Jul 06 06:26:07 PM PDT 24
Finished Jul 06 06:26:11 PM PDT 24
Peak memory 222524 kb
Host smart-8830dbfc-27a7-4bce-8722-e913b83de624
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035165133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1035165133
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1448587582
Short name T129
Test name
Test status
Simulation time 206405832 ps
CPU time 1.98 seconds
Started Jul 06 06:26:12 PM PDT 24
Finished Jul 06 06:26:15 PM PDT 24
Peak memory 221636 kb
Host smart-f3ad6b28-71d0-43a6-9c26-6d5a8e960fc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448587582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1448587582
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.126951839
Short name T196
Test name
Test status
Simulation time 72777842 ps
CPU time 1.21 seconds
Started Jul 06 06:25:40 PM PDT 24
Finished Jul 06 06:25:41 PM PDT 24
Peak memory 209364 kb
Host smart-2a18b90f-5f4d-4ca8-afe2-bc28e75b4b54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126951839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.126951839
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.831242012
Short name T89
Test name
Test status
Simulation time 132065022613 ps
CPU time 1254.13 seconds
Started Jul 06 06:30:27 PM PDT 24
Finished Jul 06 06:51:22 PM PDT 24
Peak memory 709940 kb
Host smart-0c7bc56d-c7cb-460d-b6e8-c25a2a6fb812
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=831242012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.831242012
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.3170901854
Short name T201
Test name
Test status
Simulation time 71030557 ps
CPU time 0.89 seconds
Started Jul 06 06:30:52 PM PDT 24
Finished Jul 06 06:30:53 PM PDT 24
Peak memory 211912 kb
Host smart-61778cbb-593c-4df6-b521-e226c79f195b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170901854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.3170901854
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.604927228
Short name T110
Test name
Test status
Simulation time 353037738 ps
CPU time 4.07 seconds
Started Jul 06 06:26:16 PM PDT 24
Finished Jul 06 06:26:21 PM PDT 24
Peak memory 217564 kb
Host smart-35f46ded-75bc-48fe-8468-35d637c84714
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604927228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg_
err.604927228
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2734450234
Short name T137
Test name
Test status
Simulation time 57211412 ps
CPU time 2.13 seconds
Started Jul 06 06:25:39 PM PDT 24
Finished Jul 06 06:25:42 PM PDT 24
Peak memory 209288 kb
Host smart-4697160d-20ad-4c9e-994e-8b16026644db
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734450234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.2734450234
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2438627735
Short name T128
Test name
Test status
Simulation time 114638520 ps
CPU time 2.98 seconds
Started Jul 06 06:25:58 PM PDT 24
Finished Jul 06 06:26:01 PM PDT 24
Peak memory 217536 kb
Host smart-2f70352c-4bc1-48b4-aea6-67b8d1232b3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438627735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2438627735
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3299462550
Short name T204
Test name
Test status
Simulation time 30111643 ps
CPU time 0.89 seconds
Started Jul 06 06:29:31 PM PDT 24
Finished Jul 06 06:29:33 PM PDT 24
Peak memory 208976 kb
Host smart-afa25086-d065-4c99-a2b9-d527e0f031dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299462550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3299462550
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.241852003
Short name T173
Test name
Test status
Simulation time 12727762 ps
CPU time 0.88 seconds
Started Jul 06 06:29:36 PM PDT 24
Finished Jul 06 06:29:37 PM PDT 24
Peak memory 208748 kb
Host smart-04511ac5-7fc1-4309-a4a8-7d8d51dc08b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241852003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.241852003
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.1747720241
Short name T206
Test name
Test status
Simulation time 21891992 ps
CPU time 0.97 seconds
Started Jul 06 06:30:03 PM PDT 24
Finished Jul 06 06:30:04 PM PDT 24
Peak memory 208968 kb
Host smart-418b1948-0d7c-48ab-b33d-cfe24cadcf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747720241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.1747720241
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2244195004
Short name T207
Test name
Test status
Simulation time 16125756 ps
CPU time 0.88 seconds
Started Jul 06 06:29:52 PM PDT 24
Finished Jul 06 06:29:53 PM PDT 24
Peak memory 209008 kb
Host smart-12d86ee2-b0bf-41c2-8198-0e303adb701c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244195004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2244195004
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.2080959384
Short name T203
Test name
Test status
Simulation time 115259946 ps
CPU time 0.8 seconds
Started Jul 06 06:30:05 PM PDT 24
Finished Jul 06 06:30:07 PM PDT 24
Peak memory 209024 kb
Host smart-35acc9ce-7018-476c-8d57-b677a13b7143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080959384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2080959384
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.50116369
Short name T149
Test name
Test status
Simulation time 35329987 ps
CPU time 1.73 seconds
Started Jul 06 06:29:26 PM PDT 24
Finished Jul 06 06:29:28 PM PDT 24
Peak memory 221852 kb
Host smart-7bc3979e-95c5-4ee1-b637-27cc1f480d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50116369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.50116369
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.711711319
Short name T133
Test name
Test status
Simulation time 129930835 ps
CPU time 2.03 seconds
Started Jul 06 06:25:35 PM PDT 24
Finished Jul 06 06:25:38 PM PDT 24
Peak memory 221916 kb
Host smart-8c499ab9-1d58-4769-a227-e2dfea4c55a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711711319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.711711319
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2618978189
Short name T117
Test name
Test status
Simulation time 64821530 ps
CPU time 2.75 seconds
Started Jul 06 06:26:07 PM PDT 24
Finished Jul 06 06:26:10 PM PDT 24
Peak memory 217528 kb
Host smart-cff46a85-191c-4440-b93a-85cd1e0c7aa0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618978189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.2618978189
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3006815775
Short name T132
Test name
Test status
Simulation time 63980329 ps
CPU time 2.01 seconds
Started Jul 06 06:26:11 PM PDT 24
Finished Jul 06 06:26:14 PM PDT 24
Peak memory 221588 kb
Host smart-aeb04370-f6e8-49ce-8fb0-b473cc0d6138
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006815775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.3006815775
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.315305121
Short name T135
Test name
Test status
Simulation time 255147646 ps
CPU time 2.66 seconds
Started Jul 06 06:26:12 PM PDT 24
Finished Jul 06 06:26:15 PM PDT 24
Peak memory 217568 kb
Host smart-5b2a21de-1f3c-4239-84bb-a60cd64123f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315305121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.315305121
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2384603050
Short name T134
Test name
Test status
Simulation time 108910551 ps
CPU time 2.87 seconds
Started Jul 06 06:25:51 PM PDT 24
Finished Jul 06 06:25:54 PM PDT 24
Peak memory 222364 kb
Host smart-0f464d74-926d-4dbe-9713-619eb8b10807
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384603050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.2384603050
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3215350817
Short name T120
Test name
Test status
Simulation time 577896857 ps
CPU time 3.29 seconds
Started Jul 06 06:26:02 PM PDT 24
Finished Jul 06 06:26:05 PM PDT 24
Peak memory 222368 kb
Host smart-f3f0d5a3-77b5-46b0-af85-9e2ad5b1b7dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215350817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3215350817
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3979189262
Short name T127
Test name
Test status
Simulation time 206675906 ps
CPU time 3.29 seconds
Started Jul 06 06:26:07 PM PDT 24
Finished Jul 06 06:26:10 PM PDT 24
Peak memory 222552 kb
Host smart-12251ae6-bd5d-49a5-bb75-4126365d801d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979189262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3979189262
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.3003646652
Short name T35
Test name
Test status
Simulation time 220202810 ps
CPU time 10.97 seconds
Started Jul 06 06:31:21 PM PDT 24
Finished Jul 06 06:31:32 PM PDT 24
Peak memory 219588 kb
Host smart-02b93ddd-e42c-4ca2-a2cb-e84165abab53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003646652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.3003646652
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1051384319
Short name T189
Test name
Test status
Simulation time 53741257 ps
CPU time 1.32 seconds
Started Jul 06 06:25:36 PM PDT 24
Finished Jul 06 06:25:38 PM PDT 24
Peak memory 209440 kb
Host smart-eb226273-2b28-4a4b-b79b-0dfdb27b6641
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051384319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.1051384319
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2923438362
Short name T944
Test name
Test status
Simulation time 98824202 ps
CPU time 1.55 seconds
Started Jul 06 06:25:35 PM PDT 24
Finished Jul 06 06:25:38 PM PDT 24
Peak memory 209312 kb
Host smart-1c6c6ab9-6326-4013-a78f-07d4b368085e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923438362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.2923438362
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2631691175
Short name T979
Test name
Test status
Simulation time 30932050 ps
CPU time 1.53 seconds
Started Jul 06 06:25:33 PM PDT 24
Finished Jul 06 06:25:35 PM PDT 24
Peak memory 217648 kb
Host smart-2870d555-0b44-457e-9a47-8479c1f82ea1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631691175 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2631691175
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2785615347
Short name T873
Test name
Test status
Simulation time 11807011 ps
CPU time 0.96 seconds
Started Jul 06 06:25:35 PM PDT 24
Finished Jul 06 06:25:36 PM PDT 24
Peak memory 209352 kb
Host smart-62e3a0ec-4695-4a9f-bdae-9f1e3d8137cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785615347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2785615347
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3787934441
Short name T983
Test name
Test status
Simulation time 148155115 ps
CPU time 1.49 seconds
Started Jul 06 06:25:30 PM PDT 24
Finished Jul 06 06:25:32 PM PDT 24
Peak memory 208780 kb
Host smart-fe2426b7-8007-4179-bc7c-ac715107951a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787934441 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3787934441
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.4233616918
Short name T900
Test name
Test status
Simulation time 748184714 ps
CPU time 9.26 seconds
Started Jul 06 06:25:30 PM PDT 24
Finished Jul 06 06:25:40 PM PDT 24
Peak memory 209256 kb
Host smart-928be6e8-22f2-48b1-847b-d5e6c110bfaf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233616918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.4233616918
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2156626850
Short name T882
Test name
Test status
Simulation time 3308034214 ps
CPU time 13.43 seconds
Started Jul 06 06:25:30 PM PDT 24
Finished Jul 06 06:25:44 PM PDT 24
Peak memory 209368 kb
Host smart-a33b7f97-a0b5-4140-87b3-95aadbf51329
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156626850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2156626850
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3909324913
Short name T903
Test name
Test status
Simulation time 325552506 ps
CPU time 1.67 seconds
Started Jul 06 06:25:30 PM PDT 24
Finished Jul 06 06:25:31 PM PDT 24
Peak memory 210936 kb
Host smart-a6892522-fe78-4bcd-a050-3a3b621a4a5a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909324913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3909324913
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.34179334
Short name T948
Test name
Test status
Simulation time 75792796 ps
CPU time 1.4 seconds
Started Jul 06 06:25:30 PM PDT 24
Finished Jul 06 06:25:31 PM PDT 24
Peak memory 218768 kb
Host smart-555813ce-e4d0-4104-ad0c-0452b998f24d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341793
34 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.34179334
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3724703138
Short name T866
Test name
Test status
Simulation time 837585286 ps
CPU time 1.26 seconds
Started Jul 06 06:25:30 PM PDT 24
Finished Jul 06 06:25:31 PM PDT 24
Peak memory 209208 kb
Host smart-2c6487b0-730d-48cb-b3d7-d226fcf03959
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724703138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3724703138
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.4113524036
Short name T876
Test name
Test status
Simulation time 160282994 ps
CPU time 1.03 seconds
Started Jul 06 06:25:31 PM PDT 24
Finished Jul 06 06:25:33 PM PDT 24
Peak memory 209344 kb
Host smart-7ebf961c-cadc-4b95-8cec-7bf681295f91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113524036 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.4113524036
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.623011153
Short name T975
Test name
Test status
Simulation time 19443028 ps
CPU time 1.18 seconds
Started Jul 06 06:25:33 PM PDT 24
Finished Jul 06 06:25:35 PM PDT 24
Peak memory 209380 kb
Host smart-c0282132-837f-4aa5-80f4-9f1a0fe48f39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623011153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
same_csr_outstanding.623011153
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2080935509
Short name T907
Test name
Test status
Simulation time 375156881 ps
CPU time 3.07 seconds
Started Jul 06 06:25:35 PM PDT 24
Finished Jul 06 06:25:38 PM PDT 24
Peak memory 217456 kb
Host smart-5ab5dfa1-09a3-4710-b2fc-bccf58622220
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080935509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.2080935509
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3505707226
Short name T942
Test name
Test status
Simulation time 14583184 ps
CPU time 0.99 seconds
Started Jul 06 06:25:38 PM PDT 24
Finished Jul 06 06:25:40 PM PDT 24
Peak memory 217560 kb
Host smart-411c9a47-b7a7-403b-bd88-3a4824b3e2f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505707226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3505707226
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2978105063
Short name T884
Test name
Test status
Simulation time 100677409 ps
CPU time 1.16 seconds
Started Jul 06 06:25:44 PM PDT 24
Finished Jul 06 06:25:46 PM PDT 24
Peak memory 209252 kb
Host smart-349d450c-6cbc-4ec8-b1b7-b4862900cf8f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978105063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2978105063
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.719542827
Short name T897
Test name
Test status
Simulation time 35671018 ps
CPU time 0.91 seconds
Started Jul 06 06:25:43 PM PDT 24
Finished Jul 06 06:25:44 PM PDT 24
Peak memory 209644 kb
Host smart-1a525df9-cf82-43dc-a465-b7168814c58c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719542827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset
.719542827
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2298942229
Short name T869
Test name
Test status
Simulation time 149224159 ps
CPU time 1.02 seconds
Started Jul 06 06:25:39 PM PDT 24
Finished Jul 06 06:25:40 PM PDT 24
Peak memory 218608 kb
Host smart-dba0faa2-8052-43f8-aef4-e58d263d7822
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298942229 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2298942229
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2957385865
Short name T187
Test name
Test status
Simulation time 52546602 ps
CPU time 0.87 seconds
Started Jul 06 06:25:40 PM PDT 24
Finished Jul 06 06:25:41 PM PDT 24
Peak memory 209376 kb
Host smart-04207ec1-86f8-4c98-b2b1-23c00b74e88d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957385865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2957385865
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.555113859
Short name T956
Test name
Test status
Simulation time 115260766 ps
CPU time 3.1 seconds
Started Jul 06 06:25:36 PM PDT 24
Finished Jul 06 06:25:39 PM PDT 24
Peak memory 209164 kb
Host smart-dd7a7756-35b3-46cb-b41b-3809d6234aa1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555113859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.555113859
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2425878419
Short name T910
Test name
Test status
Simulation time 5427491080 ps
CPU time 16.13 seconds
Started Jul 06 06:25:35 PM PDT 24
Finished Jul 06 06:25:52 PM PDT 24
Peak memory 209048 kb
Host smart-65d43ea6-6c4e-4d11-9740-0159f013395e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425878419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2425878419
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1857569485
Short name T939
Test name
Test status
Simulation time 1420017607 ps
CPU time 9.44 seconds
Started Jul 06 06:25:35 PM PDT 24
Finished Jul 06 06:25:45 PM PDT 24
Peak memory 208940 kb
Host smart-a8c7e6e7-b9fe-44aa-9dad-9e9900ff7c47
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857569485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1857569485
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1985519705
Short name T974
Test name
Test status
Simulation time 167643827 ps
CPU time 1.8 seconds
Started Jul 06 06:25:34 PM PDT 24
Finished Jul 06 06:25:36 PM PDT 24
Peak memory 210960 kb
Host smart-17207860-940f-41cb-b5aa-63ca566ca8d3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985519705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1985519705
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1763255530
Short name T920
Test name
Test status
Simulation time 90953147 ps
CPU time 2.28 seconds
Started Jul 06 06:25:35 PM PDT 24
Finished Jul 06 06:25:38 PM PDT 24
Peak memory 217656 kb
Host smart-2c80146e-8755-4e92-9a80-d48de2a52173
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176325
5530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1763255530
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3844520207
Short name T965
Test name
Test status
Simulation time 63888788 ps
CPU time 2.27 seconds
Started Jul 06 06:25:35 PM PDT 24
Finished Jul 06 06:25:38 PM PDT 24
Peak memory 209368 kb
Host smart-abb4cef5-d137-4709-b7ec-b1f80446a2f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844520207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.3844520207
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2716283615
Short name T914
Test name
Test status
Simulation time 30365870 ps
CPU time 1.09 seconds
Started Jul 06 06:25:36 PM PDT 24
Finished Jul 06 06:25:37 PM PDT 24
Peak memory 209336 kb
Host smart-1049eede-95cd-4463-aa1b-edb3be0ccd24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716283615 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.2716283615
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1388234129
Short name T115
Test name
Test status
Simulation time 79153533 ps
CPU time 1.88 seconds
Started Jul 06 06:25:38 PM PDT 24
Finished Jul 06 06:25:40 PM PDT 24
Peak memory 217584 kb
Host smart-0c3d30ee-5991-4c68-9592-dcc44dbb35a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388234129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1388234129
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2523641816
Short name T126
Test name
Test status
Simulation time 302642215 ps
CPU time 2.87 seconds
Started Jul 06 06:25:39 PM PDT 24
Finished Jul 06 06:25:43 PM PDT 24
Peak memory 217888 kb
Host smart-0a443974-7dc7-4db5-a1bc-0c0efad27d82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523641816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2523641816
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3127135470
Short name T130
Test name
Test status
Simulation time 31760262 ps
CPU time 1.08 seconds
Started Jul 06 06:26:07 PM PDT 24
Finished Jul 06 06:26:08 PM PDT 24
Peak memory 219556 kb
Host smart-179ff0bf-0f4e-440f-8606-3022aa408a5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127135470 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.3127135470
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2229124429
Short name T188
Test name
Test status
Simulation time 33821682 ps
CPU time 0.96 seconds
Started Jul 06 06:26:07 PM PDT 24
Finished Jul 06 06:26:08 PM PDT 24
Peak memory 209408 kb
Host smart-7a76175c-6564-46e5-bef4-3c83b31e0542
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229124429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2229124429
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3783773162
Short name T192
Test name
Test status
Simulation time 87880863 ps
CPU time 1.03 seconds
Started Jul 06 06:26:07 PM PDT 24
Finished Jul 06 06:26:09 PM PDT 24
Peak memory 209376 kb
Host smart-2c0ca8df-8cf0-470a-83d0-a9cf27eabfa9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783773162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3783773162
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.711146201
Short name T875
Test name
Test status
Simulation time 151740522 ps
CPU time 2.2 seconds
Started Jul 06 06:26:12 PM PDT 24
Finished Jul 06 06:26:15 PM PDT 24
Peak memory 218532 kb
Host smart-8757ded3-66de-40e2-bc0a-3eeeddc2922b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711146201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.711146201
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1232522794
Short name T131
Test name
Test status
Simulation time 105029433 ps
CPU time 2.88 seconds
Started Jul 06 06:26:07 PM PDT 24
Finished Jul 06 06:26:10 PM PDT 24
Peak memory 221768 kb
Host smart-1cd1a097-297c-4eec-9610-6c73796f32c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232522794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1232522794
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2703676209
Short name T904
Test name
Test status
Simulation time 45900708 ps
CPU time 1.27 seconds
Started Jul 06 06:26:09 PM PDT 24
Finished Jul 06 06:26:11 PM PDT 24
Peak memory 219748 kb
Host smart-75f69700-d6a1-45a0-b203-640f6c07d251
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703676209 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.2703676209
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1174953099
Short name T152
Test name
Test status
Simulation time 31522931 ps
CPU time 1.14 seconds
Started Jul 06 06:26:14 PM PDT 24
Finished Jul 06 06:26:15 PM PDT 24
Peak memory 209356 kb
Host smart-60bdb110-e228-4bdf-a0dd-da7da06355c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174953099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1174953099
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1360313949
Short name T925
Test name
Test status
Simulation time 110664620 ps
CPU time 1.39 seconds
Started Jul 06 06:26:09 PM PDT 24
Finished Jul 06 06:26:11 PM PDT 24
Peak memory 217560 kb
Host smart-7065d4db-d921-46b7-b1e3-dd6867faff9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360313949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1360313949
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.476936837
Short name T125
Test name
Test status
Simulation time 173382515 ps
CPU time 3.92 seconds
Started Jul 06 06:26:06 PM PDT 24
Finished Jul 06 06:26:10 PM PDT 24
Peak memory 217540 kb
Host smart-67114767-a34b-4299-afb1-523327836d39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476936837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.476936837
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1273731622
Short name T887
Test name
Test status
Simulation time 16309345 ps
CPU time 1.16 seconds
Started Jul 06 06:26:10 PM PDT 24
Finished Jul 06 06:26:11 PM PDT 24
Peak memory 218656 kb
Host smart-9261fa6b-3ea8-489b-9dc3-4593af5641f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273731622 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.1273731622
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3797690667
Short name T190
Test name
Test status
Simulation time 14985237 ps
CPU time 0.93 seconds
Started Jul 06 06:26:07 PM PDT 24
Finished Jul 06 06:26:09 PM PDT 24
Peak memory 209012 kb
Host smart-80f2eb47-628a-461b-9cd5-01f16932337f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797690667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.3797690667
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1297102327
Short name T971
Test name
Test status
Simulation time 16008053 ps
CPU time 1.22 seconds
Started Jul 06 06:26:06 PM PDT 24
Finished Jul 06 06:26:08 PM PDT 24
Peak memory 209476 kb
Host smart-b8e41728-f9c8-4350-beef-17c58d02f8bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297102327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.1297102327
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.170750040
Short name T976
Test name
Test status
Simulation time 69164250 ps
CPU time 1.42 seconds
Started Jul 06 06:26:13 PM PDT 24
Finished Jul 06 06:26:15 PM PDT 24
Peak memory 219840 kb
Host smart-2ec94fc6-722c-400b-a8f4-ce53f8044142
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170750040 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.170750040
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1084573939
Short name T181
Test name
Test status
Simulation time 18632203 ps
CPU time 0.85 seconds
Started Jul 06 06:26:11 PM PDT 24
Finished Jul 06 06:26:12 PM PDT 24
Peak memory 208996 kb
Host smart-2699abca-610e-449b-b966-68ccde88ce54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084573939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.1084573939
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2251688702
Short name T982
Test name
Test status
Simulation time 244320115 ps
CPU time 1.94 seconds
Started Jul 06 06:26:07 PM PDT 24
Finished Jul 06 06:26:09 PM PDT 24
Peak memory 209352 kb
Host smart-a2378452-fa0f-431a-a6c2-6ba91b91180c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251688702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2251688702
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2539768583
Short name T865
Test name
Test status
Simulation time 204424715 ps
CPU time 2.01 seconds
Started Jul 06 06:26:08 PM PDT 24
Finished Jul 06 06:26:10 PM PDT 24
Peak memory 217508 kb
Host smart-e5d39850-13c6-4af3-a8d3-bf93328eeb8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539768583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2539768583
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3683165898
Short name T124
Test name
Test status
Simulation time 118367953 ps
CPU time 2.9 seconds
Started Jul 06 06:26:07 PM PDT 24
Finished Jul 06 06:26:11 PM PDT 24
Peak memory 222308 kb
Host smart-4a9206a2-3355-40f8-bb17-cb201ea1a477
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683165898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.3683165898
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3107481439
Short name T940
Test name
Test status
Simulation time 21766101 ps
CPU time 1.38 seconds
Started Jul 06 06:26:10 PM PDT 24
Finished Jul 06 06:26:12 PM PDT 24
Peak memory 219312 kb
Host smart-d5d359ce-6a08-4f91-b769-a11a4952a51d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107481439 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.3107481439
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1536715982
Short name T916
Test name
Test status
Simulation time 258853035 ps
CPU time 1.04 seconds
Started Jul 06 06:26:11 PM PDT 24
Finished Jul 06 06:26:12 PM PDT 24
Peak memory 209332 kb
Host smart-a8330899-c977-425a-9251-19bfc99671c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536715982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1536715982
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2899029599
Short name T870
Test name
Test status
Simulation time 21531458 ps
CPU time 1.5 seconds
Started Jul 06 06:26:12 PM PDT 24
Finished Jul 06 06:26:14 PM PDT 24
Peak memory 217532 kb
Host smart-257c43ad-8dc0-4102-a705-19cd73d8d2d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899029599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2899029599
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1643630296
Short name T933
Test name
Test status
Simulation time 55190268 ps
CPU time 3.74 seconds
Started Jul 06 06:26:10 PM PDT 24
Finished Jul 06 06:26:14 PM PDT 24
Peak memory 218500 kb
Host smart-a7fdd363-7c45-481e-9a68-6c56c67760eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643630296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.1643630296
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2613288986
Short name T885
Test name
Test status
Simulation time 46505547 ps
CPU time 0.94 seconds
Started Jul 06 06:26:10 PM PDT 24
Finished Jul 06 06:26:11 PM PDT 24
Peak memory 217580 kb
Host smart-79d8db38-da25-4700-91d2-689f3c5319a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613288986 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2613288986
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1076126347
Short name T915
Test name
Test status
Simulation time 25525587 ps
CPU time 0.9 seconds
Started Jul 06 06:26:18 PM PDT 24
Finished Jul 06 06:26:19 PM PDT 24
Peak memory 209216 kb
Host smart-6fc116d3-626e-4ea1-a524-f73bd8934d53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076126347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.1076126347
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2779522781
Short name T136
Test name
Test status
Simulation time 26101515 ps
CPU time 1.04 seconds
Started Jul 06 06:26:13 PM PDT 24
Finished Jul 06 06:26:14 PM PDT 24
Peak memory 217500 kb
Host smart-b8fea582-e0de-4a15-998d-19ba7bf45995
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779522781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.2779522781
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3127150193
Short name T113
Test name
Test status
Simulation time 142724921 ps
CPU time 1.75 seconds
Started Jul 06 06:26:11 PM PDT 24
Finished Jul 06 06:26:14 PM PDT 24
Peak memory 218616 kb
Host smart-884bb4d1-74e7-414c-839b-27759ad67775
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127150193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.3127150193
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.180502372
Short name T945
Test name
Test status
Simulation time 43396017 ps
CPU time 1.22 seconds
Started Jul 06 06:26:11 PM PDT 24
Finished Jul 06 06:26:12 PM PDT 24
Peak memory 218604 kb
Host smart-08feafaa-551d-439a-b954-f2fa20ee6afc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180502372 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.180502372
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1520871436
Short name T889
Test name
Test status
Simulation time 57303161 ps
CPU time 0.79 seconds
Started Jul 06 06:26:12 PM PDT 24
Finished Jul 06 06:26:14 PM PDT 24
Peak memory 208540 kb
Host smart-e6880c4c-079e-4bab-8ec2-98cd6bcba448
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520871436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1520871436
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3931528421
Short name T898
Test name
Test status
Simulation time 92347938 ps
CPU time 1.07 seconds
Started Jul 06 06:26:12 PM PDT 24
Finished Jul 06 06:26:14 PM PDT 24
Peak memory 209460 kb
Host smart-f6759edd-8a99-43fd-a640-dcbd6fc08ad5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931528421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3931528421
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3969158683
Short name T929
Test name
Test status
Simulation time 227962093 ps
CPU time 2.4 seconds
Started Jul 06 06:26:14 PM PDT 24
Finished Jul 06 06:26:16 PM PDT 24
Peak memory 217504 kb
Host smart-757c1354-a8d0-4654-a727-37e58e50d3e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969158683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3969158683
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.4027177795
Short name T969
Test name
Test status
Simulation time 243767732 ps
CPU time 1.16 seconds
Started Jul 06 06:26:09 PM PDT 24
Finished Jul 06 06:26:11 PM PDT 24
Peak memory 217664 kb
Host smart-7070d2f9-06fb-4491-8703-dd77d4c13dad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027177795 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.4027177795
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.53367739
Short name T913
Test name
Test status
Simulation time 19080674 ps
CPU time 0.91 seconds
Started Jul 06 06:26:12 PM PDT 24
Finished Jul 06 06:26:13 PM PDT 24
Peak memory 209352 kb
Host smart-b8098536-cfd1-4f17-9f0d-51985ad83990
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53367739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.53367739
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3442983901
Short name T955
Test name
Test status
Simulation time 43919502 ps
CPU time 1.06 seconds
Started Jul 06 06:26:12 PM PDT 24
Finished Jul 06 06:26:13 PM PDT 24
Peak memory 209312 kb
Host smart-ea432645-e7e0-4b6b-a892-e33d264d3ab2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442983901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.3442983901
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2614411178
Short name T908
Test name
Test status
Simulation time 189298994 ps
CPU time 1.73 seconds
Started Jul 06 06:26:11 PM PDT 24
Finished Jul 06 06:26:13 PM PDT 24
Peak memory 217512 kb
Host smart-93c0d176-b488-4652-af7b-799bbd08ff76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614411178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2614411178
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2340939243
Short name T934
Test name
Test status
Simulation time 67188779 ps
CPU time 1.99 seconds
Started Jul 06 06:26:10 PM PDT 24
Finished Jul 06 06:26:12 PM PDT 24
Peak memory 222024 kb
Host smart-7fe513a9-11b5-41bd-a4dc-b57a625baf31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340939243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.2340939243
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2381466271
Short name T114
Test name
Test status
Simulation time 43085629 ps
CPU time 1.51 seconds
Started Jul 06 06:26:16 PM PDT 24
Finished Jul 06 06:26:18 PM PDT 24
Peak memory 217632 kb
Host smart-aa4c24d7-bace-4607-b254-87410eaedcb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381466271 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.2381466271
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3412947009
Short name T946
Test name
Test status
Simulation time 15623332 ps
CPU time 0.94 seconds
Started Jul 06 06:26:13 PM PDT 24
Finished Jul 06 06:26:14 PM PDT 24
Peak memory 209372 kb
Host smart-f2a21d09-3551-4b0c-9370-f5bed0307d2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412947009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3412947009
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1105530006
Short name T953
Test name
Test status
Simulation time 103728545 ps
CPU time 1.42 seconds
Started Jul 06 06:26:11 PM PDT 24
Finished Jul 06 06:26:13 PM PDT 24
Peak memory 211316 kb
Host smart-8af6e0d4-102c-41cf-b290-46b6c774630a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105530006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.1105530006
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1079597169
Short name T967
Test name
Test status
Simulation time 251331746 ps
CPU time 3.67 seconds
Started Jul 06 06:26:12 PM PDT 24
Finished Jul 06 06:26:16 PM PDT 24
Peak memory 217812 kb
Host smart-73182a5d-4ba3-45dc-840e-31ae66db415c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079597169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1079597169
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.650626471
Short name T891
Test name
Test status
Simulation time 43900082 ps
CPU time 1.56 seconds
Started Jul 06 06:26:16 PM PDT 24
Finished Jul 06 06:26:18 PM PDT 24
Peak memory 217676 kb
Host smart-ca240649-a6b0-4bdf-8d9d-203ebc278880
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650626471 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.650626471
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3076235338
Short name T183
Test name
Test status
Simulation time 34686456 ps
CPU time 0.95 seconds
Started Jul 06 06:26:16 PM PDT 24
Finished Jul 06 06:26:18 PM PDT 24
Peak memory 209000 kb
Host smart-98cda1f1-acfd-444b-84bb-c22327cc69aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076235338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.3076235338
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2809353608
Short name T911
Test name
Test status
Simulation time 46838760 ps
CPU time 2.02 seconds
Started Jul 06 06:26:18 PM PDT 24
Finished Jul 06 06:26:20 PM PDT 24
Peak memory 217604 kb
Host smart-535224b4-221d-4f3b-a2dd-c6b6190b23ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809353608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2809353608
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.938812233
Short name T153
Test name
Test status
Simulation time 464067178 ps
CPU time 2.62 seconds
Started Jul 06 06:26:18 PM PDT 24
Finished Jul 06 06:26:21 PM PDT 24
Peak memory 217488 kb
Host smart-274fa970-3bf1-44ca-9ef2-39d120bf7b61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938812233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.938812233
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1778083548
Short name T931
Test name
Test status
Simulation time 161353099 ps
CPU time 1.62 seconds
Started Jul 06 06:25:46 PM PDT 24
Finished Jul 06 06:25:48 PM PDT 24
Peak memory 209368 kb
Host smart-1210ec26-8b08-488e-a8c3-deba0d2595a2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778083548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.1778083548
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3663336552
Short name T950
Test name
Test status
Simulation time 39389625 ps
CPU time 1.95 seconds
Started Jul 06 06:25:45 PM PDT 24
Finished Jul 06 06:25:47 PM PDT 24
Peak memory 209016 kb
Host smart-a8b68fbd-14cd-44d8-91d3-7099d414b0dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663336552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.3663336552
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3996344343
Short name T905
Test name
Test status
Simulation time 45733577 ps
CPU time 1.08 seconds
Started Jul 06 06:25:46 PM PDT 24
Finished Jul 06 06:25:48 PM PDT 24
Peak memory 211564 kb
Host smart-98dd4d05-bbcb-4200-aae8-3cd1bd24d8d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996344343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3996344343
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.164312824
Short name T922
Test name
Test status
Simulation time 23523257 ps
CPU time 1.52 seconds
Started Jul 06 06:25:44 PM PDT 24
Finished Jul 06 06:25:46 PM PDT 24
Peak memory 217768 kb
Host smart-371c4b72-498f-4728-b5a9-33730ef4b1c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164312824 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.164312824
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1461939963
Short name T981
Test name
Test status
Simulation time 12758959 ps
CPU time 0.81 seconds
Started Jul 06 06:25:48 PM PDT 24
Finished Jul 06 06:25:49 PM PDT 24
Peak memory 208552 kb
Host smart-ffc02c26-5612-4ce1-b0f9-11566c7d6db5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461939963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1461939963
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3878930883
Short name T863
Test name
Test status
Simulation time 74577682 ps
CPU time 0.91 seconds
Started Jul 06 06:25:39 PM PDT 24
Finished Jul 06 06:25:41 PM PDT 24
Peak memory 209168 kb
Host smart-34585067-f429-4524-b873-69c888d8d3ae
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878930883 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3878930883
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2121160782
Short name T871
Test name
Test status
Simulation time 1161034858 ps
CPU time 25.26 seconds
Started Jul 06 06:25:40 PM PDT 24
Finished Jul 06 06:26:05 PM PDT 24
Peak memory 209012 kb
Host smart-b4743781-1f61-4868-9efd-b78307bf7ff4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121160782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.2121160782
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2871318641
Short name T958
Test name
Test status
Simulation time 1667209774 ps
CPU time 19.53 seconds
Started Jul 06 06:25:39 PM PDT 24
Finished Jul 06 06:25:59 PM PDT 24
Peak memory 209076 kb
Host smart-d0e7a16d-aee6-4693-a900-8e026eb2a15d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871318641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.2871318641
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.906926040
Short name T912
Test name
Test status
Simulation time 85553011 ps
CPU time 1.86 seconds
Started Jul 06 06:25:44 PM PDT 24
Finished Jul 06 06:25:46 PM PDT 24
Peak memory 217440 kb
Host smart-c4e0aad9-d6ef-4da2-8d7d-255abe14b285
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906926040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.906926040
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.22428166
Short name T112
Test name
Test status
Simulation time 557839621 ps
CPU time 3.9 seconds
Started Jul 06 06:25:40 PM PDT 24
Finished Jul 06 06:25:44 PM PDT 24
Peak memory 221816 kb
Host smart-0fcfbb7f-136c-4a4c-9e51-5aad3ab59a42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224281
66 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.22428166
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1501436634
Short name T194
Test name
Test status
Simulation time 53979934 ps
CPU time 0.97 seconds
Started Jul 06 06:25:39 PM PDT 24
Finished Jul 06 06:25:40 PM PDT 24
Peak memory 209472 kb
Host smart-174b5558-6ebf-4835-863a-1a2959a65001
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501436634 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1501436634
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2475765528
Short name T880
Test name
Test status
Simulation time 23778488 ps
CPU time 1.56 seconds
Started Jul 06 06:25:44 PM PDT 24
Finished Jul 06 06:25:46 PM PDT 24
Peak memory 211416 kb
Host smart-970d6275-59f1-44e4-98ba-b512c042966e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475765528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.2475765528
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3617758168
Short name T977
Test name
Test status
Simulation time 41269463 ps
CPU time 1.75 seconds
Started Jul 06 06:25:41 PM PDT 24
Finished Jul 06 06:25:43 PM PDT 24
Peak memory 217588 kb
Host smart-a36b24ad-fc67-4a91-886a-5833cab55fc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617758168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.3617758168
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1526987054
Short name T111
Test name
Test status
Simulation time 218758056 ps
CPU time 2.03 seconds
Started Jul 06 06:26:14 PM PDT 24
Finished Jul 06 06:26:16 PM PDT 24
Peak memory 221708 kb
Host smart-5cc7ab5b-f50e-4844-8c29-23988da55c9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526987054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1526987054
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2033746918
Short name T862
Test name
Test status
Simulation time 115528913 ps
CPU time 1.29 seconds
Started Jul 06 06:25:44 PM PDT 24
Finished Jul 06 06:25:45 PM PDT 24
Peak memory 209388 kb
Host smart-69c18ca1-cb31-40a7-8084-f4f26c93bcff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033746918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.2033746918
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1376952164
Short name T987
Test name
Test status
Simulation time 20496881 ps
CPU time 1.38 seconds
Started Jul 06 06:25:44 PM PDT 24
Finished Jul 06 06:25:46 PM PDT 24
Peak memory 209384 kb
Host smart-1c0c6c99-c5ba-4857-992e-40159c79adc0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376952164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.1376952164
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1379926159
Short name T985
Test name
Test status
Simulation time 20831033 ps
CPU time 0.92 seconds
Started Jul 06 06:25:45 PM PDT 24
Finished Jul 06 06:25:46 PM PDT 24
Peak memory 209792 kb
Host smart-6d1492be-c1b8-482d-9c8b-1ab33b1a0ad2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379926159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.1379926159
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3648544065
Short name T957
Test name
Test status
Simulation time 56918568 ps
CPU time 1.07 seconds
Started Jul 06 06:25:50 PM PDT 24
Finished Jul 06 06:25:52 PM PDT 24
Peak memory 217636 kb
Host smart-e4015daf-d328-4fbc-b25c-8d99ea4ae8f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648544065 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3648544065
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.596015463
Short name T180
Test name
Test status
Simulation time 14989551 ps
CPU time 1.07 seconds
Started Jul 06 06:25:45 PM PDT 24
Finished Jul 06 06:25:47 PM PDT 24
Peak memory 217540 kb
Host smart-c406f1ff-7b84-4538-a00f-45ba661fc423
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596015463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.596015463
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1454951113
Short name T935
Test name
Test status
Simulation time 333817593 ps
CPU time 1.53 seconds
Started Jul 06 06:25:46 PM PDT 24
Finished Jul 06 06:25:48 PM PDT 24
Peak memory 209204 kb
Host smart-2ae0a832-5696-4630-8ed7-921931ec2734
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454951113 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.1454951113
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3664154312
Short name T901
Test name
Test status
Simulation time 1629540540 ps
CPU time 5.12 seconds
Started Jul 06 06:26:04 PM PDT 24
Finished Jul 06 06:26:09 PM PDT 24
Peak memory 209028 kb
Host smart-31871a54-7be2-4070-b557-ab64952c90dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664154312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3664154312
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3838323981
Short name T968
Test name
Test status
Simulation time 3324232351 ps
CPU time 21.85 seconds
Started Jul 06 06:25:44 PM PDT 24
Finished Jul 06 06:26:07 PM PDT 24
Peak memory 209396 kb
Host smart-60770ddf-7066-4f2b-ac3f-92043c500f28
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838323981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3838323981
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.358505228
Short name T883
Test name
Test status
Simulation time 274167454 ps
CPU time 1.87 seconds
Started Jul 06 06:25:43 PM PDT 24
Finished Jul 06 06:25:46 PM PDT 24
Peak memory 210800 kb
Host smart-021de634-f78b-4bdd-b4ce-418259f08648
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358505228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.358505228
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3559465757
Short name T868
Test name
Test status
Simulation time 235570946 ps
CPU time 3.75 seconds
Started Jul 06 06:25:44 PM PDT 24
Finished Jul 06 06:25:48 PM PDT 24
Peak memory 217708 kb
Host smart-85778058-30da-4984-b1ae-258416047400
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355946
5757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3559465757
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3233814068
Short name T890
Test name
Test status
Simulation time 767309207 ps
CPU time 1.39 seconds
Started Jul 06 06:25:43 PM PDT 24
Finished Jul 06 06:25:45 PM PDT 24
Peak memory 209216 kb
Host smart-31bbe255-39eb-4d58-98a2-466898ce49a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233814068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.3233814068
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2340206715
Short name T892
Test name
Test status
Simulation time 16688465 ps
CPU time 1.02 seconds
Started Jul 06 06:25:43 PM PDT 24
Finished Jul 06 06:25:44 PM PDT 24
Peak memory 209352 kb
Host smart-91c1f309-d167-4018-a169-c9e04a26ab1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340206715 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2340206715
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2186181497
Short name T961
Test name
Test status
Simulation time 38720704 ps
CPU time 1.4 seconds
Started Jul 06 06:25:51 PM PDT 24
Finished Jul 06 06:25:53 PM PDT 24
Peak memory 209492 kb
Host smart-e0dab1ad-f171-46c3-a140-9aae36549949
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186181497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.2186181497
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.560901642
Short name T954
Test name
Test status
Simulation time 34939405 ps
CPU time 2.5 seconds
Started Jul 06 06:25:42 PM PDT 24
Finished Jul 06 06:25:45 PM PDT 24
Peak memory 217516 kb
Host smart-a2767333-4ebd-4b98-90a4-fc996fc7ca1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560901642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.560901642
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.370186653
Short name T185
Test name
Test status
Simulation time 41803931 ps
CPU time 1.4 seconds
Started Jul 06 06:25:50 PM PDT 24
Finished Jul 06 06:25:52 PM PDT 24
Peak memory 209488 kb
Host smart-39c6e26a-c9f0-47c9-a974-05854a6fe161
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370186653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasing
.370186653
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.4041369077
Short name T938
Test name
Test status
Simulation time 180953560 ps
CPU time 1.4 seconds
Started Jul 06 06:25:48 PM PDT 24
Finished Jul 06 06:25:50 PM PDT 24
Peak memory 217248 kb
Host smart-123b590e-3076-4b6e-ab31-2f86091a7e57
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041369077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.4041369077
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.640212073
Short name T951
Test name
Test status
Simulation time 42585101 ps
CPU time 0.97 seconds
Started Jul 06 06:25:49 PM PDT 24
Finished Jul 06 06:25:50 PM PDT 24
Peak memory 210480 kb
Host smart-b023720c-be49-4717-a686-cf84bbcad5bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640212073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_reset
.640212073
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3021956312
Short name T918
Test name
Test status
Simulation time 55363131 ps
CPU time 1.29 seconds
Started Jul 06 06:25:55 PM PDT 24
Finished Jul 06 06:25:56 PM PDT 24
Peak memory 219104 kb
Host smart-d2e3ff75-3a93-4482-a7da-6a647a7edef3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021956312 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3021956312
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3617208190
Short name T973
Test name
Test status
Simulation time 35113669 ps
CPU time 0.83 seconds
Started Jul 06 06:25:51 PM PDT 24
Finished Jul 06 06:25:52 PM PDT 24
Peak memory 209292 kb
Host smart-a7d0e10c-7d65-4c42-89e3-23da59be42c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617208190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3617208190
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1275038112
Short name T962
Test name
Test status
Simulation time 332092898 ps
CPU time 1.17 seconds
Started Jul 06 06:25:47 PM PDT 24
Finished Jul 06 06:25:49 PM PDT 24
Peak memory 209168 kb
Host smart-d776bcf0-68b4-4e95-9c34-12435bae2a02
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275038112 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1275038112
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2025549644
Short name T952
Test name
Test status
Simulation time 191227908 ps
CPU time 4.73 seconds
Started Jul 06 06:25:47 PM PDT 24
Finished Jul 06 06:25:52 PM PDT 24
Peak memory 209296 kb
Host smart-3c81f22e-2b3f-403a-bb0c-d57cf66e4ed8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025549644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2025549644
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2728222440
Short name T119
Test name
Test status
Simulation time 2337221255 ps
CPU time 10.5 seconds
Started Jul 06 06:25:48 PM PDT 24
Finished Jul 06 06:25:59 PM PDT 24
Peak memory 209432 kb
Host smart-4bce63e8-d4c8-4703-b929-684ff4d57b35
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728222440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.2728222440
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2780990489
Short name T141
Test name
Test status
Simulation time 108241703 ps
CPU time 1.78 seconds
Started Jul 06 06:25:47 PM PDT 24
Finished Jul 06 06:25:50 PM PDT 24
Peak memory 210952 kb
Host smart-79b08cf1-d30a-42f4-865c-9c06f95ca8c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780990489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2780990489
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.161459221
Short name T902
Test name
Test status
Simulation time 301098066 ps
CPU time 3.76 seconds
Started Jul 06 06:25:51 PM PDT 24
Finished Jul 06 06:25:55 PM PDT 24
Peak memory 219236 kb
Host smart-fc3ad805-d1ce-48f8-9bd7-445b50188f55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161459
221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.161459221
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3285217323
Short name T893
Test name
Test status
Simulation time 107444828 ps
CPU time 1.23 seconds
Started Jul 06 06:25:48 PM PDT 24
Finished Jul 06 06:25:50 PM PDT 24
Peak memory 209336 kb
Host smart-6cf35b2d-9462-4ee0-abe4-5678dde21ce0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285217323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.3285217323
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.162618268
Short name T963
Test name
Test status
Simulation time 190866992 ps
CPU time 0.98 seconds
Started Jul 06 06:25:47 PM PDT 24
Finished Jul 06 06:25:48 PM PDT 24
Peak memory 209472 kb
Host smart-8ce21a95-9e17-47f2-b4b6-ee3bf407c729
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162618268 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.162618268
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.684443950
Short name T197
Test name
Test status
Simulation time 140349321 ps
CPU time 1.3 seconds
Started Jul 06 06:25:47 PM PDT 24
Finished Jul 06 06:25:49 PM PDT 24
Peak memory 209376 kb
Host smart-42164873-1702-48d0-ad9e-c23fbd14a092
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684443950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
same_csr_outstanding.684443950
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1040111756
Short name T978
Test name
Test status
Simulation time 107682819 ps
CPU time 2.85 seconds
Started Jul 06 06:25:47 PM PDT 24
Finished Jul 06 06:25:50 PM PDT 24
Peak memory 217480 kb
Host smart-dd749cf4-d6a8-41b7-b502-b0b420e34159
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040111756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1040111756
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2653886120
Short name T151
Test name
Test status
Simulation time 249999461 ps
CPU time 2.12 seconds
Started Jul 06 06:25:48 PM PDT 24
Finished Jul 06 06:25:50 PM PDT 24
Peak memory 221992 kb
Host smart-ae7fda1d-6106-48dc-900c-95cc814dfc74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653886120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.2653886120
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2106321401
Short name T937
Test name
Test status
Simulation time 22516970 ps
CPU time 1.21 seconds
Started Jul 06 06:25:55 PM PDT 24
Finished Jul 06 06:25:57 PM PDT 24
Peak memory 218756 kb
Host smart-d954503d-45e9-4e94-ab2a-c3b6f21824a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106321401 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2106321401
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1761999808
Short name T191
Test name
Test status
Simulation time 13634820 ps
CPU time 0.89 seconds
Started Jul 06 06:25:54 PM PDT 24
Finished Jul 06 06:25:55 PM PDT 24
Peak memory 209320 kb
Host smart-15fbe8d0-97cb-4a0d-b509-0a22006f08d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761999808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1761999808
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1085201410
Short name T966
Test name
Test status
Simulation time 204048383 ps
CPU time 1.9 seconds
Started Jul 06 06:25:54 PM PDT 24
Finished Jul 06 06:25:56 PM PDT 24
Peak memory 208800 kb
Host smart-275c4931-7e73-4f76-9afa-f187e18c4f74
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085201410 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1085201410
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1776276359
Short name T984
Test name
Test status
Simulation time 1015089163 ps
CPU time 9.08 seconds
Started Jul 06 06:25:53 PM PDT 24
Finished Jul 06 06:26:02 PM PDT 24
Peak memory 216992 kb
Host smart-69b1c77a-3749-4cf6-939d-6740ad2a9569
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776276359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.1776276359
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3935970485
Short name T142
Test name
Test status
Simulation time 1806218075 ps
CPU time 15.14 seconds
Started Jul 06 06:25:57 PM PDT 24
Finished Jul 06 06:26:12 PM PDT 24
Peak memory 217128 kb
Host smart-b34d8f5a-e6e4-45b2-a2d1-7bfea27dd2e4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935970485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3935970485
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.33805873
Short name T986
Test name
Test status
Simulation time 197949375 ps
CPU time 3.11 seconds
Started Jul 06 06:25:54 PM PDT 24
Finished Jul 06 06:25:57 PM PDT 24
Peak memory 217500 kb
Host smart-cbfe1b20-1b7d-4918-a294-b0b5d9d1b8d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33805873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.33805873
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1127646516
Short name T972
Test name
Test status
Simulation time 306193623 ps
CPU time 1.52 seconds
Started Jul 06 06:25:57 PM PDT 24
Finished Jul 06 06:25:59 PM PDT 24
Peak memory 218668 kb
Host smart-8b9bb4da-909d-4ca7-a0cb-9b6286bb6806
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112764
6516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1127646516
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3323758889
Short name T888
Test name
Test status
Simulation time 33259947 ps
CPU time 1.09 seconds
Started Jul 06 06:25:53 PM PDT 24
Finished Jul 06 06:25:54 PM PDT 24
Peak memory 217256 kb
Host smart-ec6eed6b-a30d-40b8-8e6e-7447f87902bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323758889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3323758889
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3710862996
Short name T886
Test name
Test status
Simulation time 75416002 ps
CPU time 1.88 seconds
Started Jul 06 06:25:56 PM PDT 24
Finished Jul 06 06:25:58 PM PDT 24
Peak memory 217572 kb
Host smart-be4595ce-648b-4eed-9888-4a6e240737ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710862996 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3710862996
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.64256039
Short name T970
Test name
Test status
Simulation time 18872987 ps
CPU time 1 seconds
Started Jul 06 06:25:56 PM PDT 24
Finished Jul 06 06:25:57 PM PDT 24
Peak memory 209184 kb
Host smart-223a7330-8f77-428d-b975-42d5aeef382b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64256039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_s
ame_csr_outstanding.64256039
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1794390038
Short name T909
Test name
Test status
Simulation time 168073505 ps
CPU time 2.17 seconds
Started Jul 06 06:25:54 PM PDT 24
Finished Jul 06 06:25:57 PM PDT 24
Peak memory 217476 kb
Host smart-88af2267-5495-41f9-b990-cd5599463ee7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794390038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.1794390038
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2916502106
Short name T872
Test name
Test status
Simulation time 37513130 ps
CPU time 1.08 seconds
Started Jul 06 06:26:00 PM PDT 24
Finished Jul 06 06:26:01 PM PDT 24
Peak memory 217644 kb
Host smart-c5fe82e1-a87a-4174-89a7-0c518d86b574
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916502106 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2916502106
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3298061652
Short name T932
Test name
Test status
Simulation time 19581009 ps
CPU time 0.96 seconds
Started Jul 06 06:25:57 PM PDT 24
Finished Jul 06 06:25:58 PM PDT 24
Peak memory 209316 kb
Host smart-5c5b04d8-71e3-44a0-a3f2-60774b242524
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298061652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3298061652
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.4135250707
Short name T928
Test name
Test status
Simulation time 59918445 ps
CPU time 2.04 seconds
Started Jul 06 06:25:59 PM PDT 24
Finished Jul 06 06:26:01 PM PDT 24
Peak memory 209192 kb
Host smart-594f6dcc-a9fe-401f-b42e-7e76c96af61e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135250707 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.4135250707
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3772984265
Short name T941
Test name
Test status
Simulation time 337832278 ps
CPU time 8.65 seconds
Started Jul 06 06:25:53 PM PDT 24
Finished Jul 06 06:26:02 PM PDT 24
Peak memory 209036 kb
Host smart-c8c860ae-45d7-4a14-8c2e-4b1dd22203eb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772984265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3772984265
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.4127972262
Short name T200
Test name
Test status
Simulation time 2492427443 ps
CPU time 13.8 seconds
Started Jul 06 06:25:55 PM PDT 24
Finished Jul 06 06:26:09 PM PDT 24
Peak memory 209416 kb
Host smart-a999d3ec-f300-44b8-bdd4-580b544aa851
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127972262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.4127972262
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.505524028
Short name T138
Test name
Test status
Simulation time 102550834 ps
CPU time 1.37 seconds
Started Jul 06 06:25:54 PM PDT 24
Finished Jul 06 06:25:56 PM PDT 24
Peak memory 210708 kb
Host smart-32cba41d-c78a-4e9d-b30c-f8e53c924507
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505524028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.505524028
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3390714206
Short name T964
Test name
Test status
Simulation time 111862773 ps
CPU time 1.88 seconds
Started Jul 06 06:26:02 PM PDT 24
Finished Jul 06 06:26:04 PM PDT 24
Peak memory 218656 kb
Host smart-fac41f42-9616-43f4-9a26-b4c630c8307a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339071
4206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3390714206
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3356383064
Short name T896
Test name
Test status
Simulation time 230915888 ps
CPU time 2.14 seconds
Started Jul 06 06:25:53 PM PDT 24
Finished Jul 06 06:25:55 PM PDT 24
Peak memory 209292 kb
Host smart-4eddbb19-cad9-4cd9-94cf-d1d52bc0df14
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356383064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.3356383064
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2355467043
Short name T878
Test name
Test status
Simulation time 75922028 ps
CPU time 1.43 seconds
Started Jul 06 06:25:52 PM PDT 24
Finished Jul 06 06:25:54 PM PDT 24
Peak memory 209352 kb
Host smart-67bff5b7-8ad4-4d0d-acee-444ab69eef10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355467043 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.2355467043
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1824635944
Short name T154
Test name
Test status
Simulation time 101631087 ps
CPU time 1.1 seconds
Started Jul 06 06:25:57 PM PDT 24
Finished Jul 06 06:25:58 PM PDT 24
Peak memory 209380 kb
Host smart-91b8516d-9d27-4404-bef0-f289e88e47dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824635944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.1824635944
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2003555427
Short name T864
Test name
Test status
Simulation time 70831754 ps
CPU time 2.27 seconds
Started Jul 06 06:25:57 PM PDT 24
Finished Jul 06 06:26:00 PM PDT 24
Peak memory 217508 kb
Host smart-9796da84-c60e-41b5-8b95-7e570a833a7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003555427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2003555427
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3629100282
Short name T949
Test name
Test status
Simulation time 175892098 ps
CPU time 2.2 seconds
Started Jul 06 06:25:59 PM PDT 24
Finished Jul 06 06:26:01 PM PDT 24
Peak memory 221864 kb
Host smart-95c1c99c-e83c-4702-8f5c-c32ce5b4ae39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629100282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.3629100282
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.754331685
Short name T116
Test name
Test status
Simulation time 28383663 ps
CPU time 2.12 seconds
Started Jul 06 06:25:58 PM PDT 24
Finished Jul 06 06:26:01 PM PDT 24
Peak memory 217680 kb
Host smart-ab67bab4-e508-439d-b88a-90a263767c80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754331685 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.754331685
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.722201116
Short name T184
Test name
Test status
Simulation time 14445719 ps
CPU time 0.89 seconds
Started Jul 06 06:25:58 PM PDT 24
Finished Jul 06 06:25:59 PM PDT 24
Peak memory 209332 kb
Host smart-2c7e27ac-55f1-4be5-b514-ed5b3b905556
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722201116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.722201116
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.467149797
Short name T860
Test name
Test status
Simulation time 208824205 ps
CPU time 1.09 seconds
Started Jul 06 06:25:58 PM PDT 24
Finished Jul 06 06:25:59 PM PDT 24
Peak memory 208616 kb
Host smart-0d44f418-5f0e-4537-9e28-71788a23350b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467149797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.lc_ctrl_jtag_alert_test.467149797
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2193232491
Short name T923
Test name
Test status
Simulation time 632185766 ps
CPU time 8.12 seconds
Started Jul 06 06:25:58 PM PDT 24
Finished Jul 06 06:26:07 PM PDT 24
Peak memory 209072 kb
Host smart-b80c212e-5147-40a3-b27a-3bfca8c88a61
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193232491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2193232491
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.218708791
Short name T924
Test name
Test status
Simulation time 8420535225 ps
CPU time 13.26 seconds
Started Jul 06 06:26:02 PM PDT 24
Finished Jul 06 06:26:15 PM PDT 24
Peak memory 209232 kb
Host smart-3016ea98-c0f4-4e96-b8d9-71c57d2eb4bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218708791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.218708791
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1438260845
Short name T930
Test name
Test status
Simulation time 557881006 ps
CPU time 1.99 seconds
Started Jul 06 06:25:56 PM PDT 24
Finished Jul 06 06:25:59 PM PDT 24
Peak memory 210916 kb
Host smart-7b17fde0-1b55-439e-9f15-ef56fc46741c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438260845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1438260845
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4126475387
Short name T877
Test name
Test status
Simulation time 411209234 ps
CPU time 4.17 seconds
Started Jul 06 06:25:58 PM PDT 24
Finished Jul 06 06:26:03 PM PDT 24
Peak memory 218652 kb
Host smart-9ed805f7-239a-486a-ac85-eccfd233b729
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412647
5387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4126475387
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.933824938
Short name T861
Test name
Test status
Simulation time 47467384 ps
CPU time 1.53 seconds
Started Jul 06 06:25:55 PM PDT 24
Finished Jul 06 06:25:57 PM PDT 24
Peak memory 209280 kb
Host smart-7741f1b5-1a3e-4b4d-90da-7946a0600f2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933824938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.933824938
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2581762685
Short name T919
Test name
Test status
Simulation time 56021483 ps
CPU time 1.1 seconds
Started Jul 06 06:25:59 PM PDT 24
Finished Jul 06 06:26:00 PM PDT 24
Peak memory 209352 kb
Host smart-be0e66c1-930f-4420-8a2c-75774c8e0df3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581762685 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2581762685
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.879200585
Short name T193
Test name
Test status
Simulation time 30570517 ps
CPU time 1.25 seconds
Started Jul 06 06:25:57 PM PDT 24
Finished Jul 06 06:25:59 PM PDT 24
Peak memory 209296 kb
Host smart-e70a856d-6aec-459d-b9fc-41fecf012b54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879200585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
same_csr_outstanding.879200585
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2585684795
Short name T926
Test name
Test status
Simulation time 110301459 ps
CPU time 2.07 seconds
Started Jul 06 06:25:58 PM PDT 24
Finished Jul 06 06:26:00 PM PDT 24
Peak memory 217628 kb
Host smart-08fd692a-5691-4d8f-a930-49bc78f4daa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585684795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.2585684795
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.239441760
Short name T895
Test name
Test status
Simulation time 19056958 ps
CPU time 1.41 seconds
Started Jul 06 06:26:02 PM PDT 24
Finished Jul 06 06:26:04 PM PDT 24
Peak memory 217812 kb
Host smart-3453fcc4-169b-4f49-9cef-59395431b745
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239441760 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.239441760
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.271418420
Short name T186
Test name
Test status
Simulation time 39614359 ps
CPU time 0.84 seconds
Started Jul 06 06:26:06 PM PDT 24
Finished Jul 06 06:26:07 PM PDT 24
Peak memory 208748 kb
Host smart-65cc841f-564b-4a03-9e55-044de3af867c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271418420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.271418420
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3550611461
Short name T879
Test name
Test status
Simulation time 152230562 ps
CPU time 0.85 seconds
Started Jul 06 06:26:01 PM PDT 24
Finished Jul 06 06:26:03 PM PDT 24
Peak memory 209020 kb
Host smart-7b135235-21de-4a69-a768-a6b74a43461f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550611461 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3550611461
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.4098049342
Short name T881
Test name
Test status
Simulation time 1158120895 ps
CPU time 6.76 seconds
Started Jul 06 06:26:02 PM PDT 24
Finished Jul 06 06:26:09 PM PDT 24
Peak memory 217084 kb
Host smart-919b09c6-b06f-4b0e-ba13-3b2c84548b9a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098049342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.4098049342
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2963041176
Short name T874
Test name
Test status
Simulation time 700974975 ps
CPU time 17.69 seconds
Started Jul 06 06:26:01 PM PDT 24
Finished Jul 06 06:26:19 PM PDT 24
Peak memory 208948 kb
Host smart-f44f961c-e9ab-4a04-b617-755da92db144
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963041176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.2963041176
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2316828123
Short name T139
Test name
Test status
Simulation time 56272633 ps
CPU time 2.14 seconds
Started Jul 06 06:26:02 PM PDT 24
Finished Jul 06 06:26:05 PM PDT 24
Peak memory 210840 kb
Host smart-10f2f56a-f02d-4cc7-adab-24ecc63f5096
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316828123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2316828123
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1779950973
Short name T960
Test name
Test status
Simulation time 55041240 ps
CPU time 2.11 seconds
Started Jul 06 06:26:03 PM PDT 24
Finished Jul 06 06:26:05 PM PDT 24
Peak memory 217376 kb
Host smart-c887ae2d-7dae-414c-a393-92ac5ecc9966
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779950973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.1779950973
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3576408313
Short name T894
Test name
Test status
Simulation time 177549588 ps
CPU time 1.98 seconds
Started Jul 06 06:26:04 PM PDT 24
Finished Jul 06 06:26:06 PM PDT 24
Peak memory 209424 kb
Host smart-f1d65435-ef02-404f-acbf-5dc43bd2ed4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576408313 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3576408313
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3303186723
Short name T921
Test name
Test status
Simulation time 16732567 ps
CPU time 1.28 seconds
Started Jul 06 06:26:02 PM PDT 24
Finished Jul 06 06:26:04 PM PDT 24
Peak memory 209340 kb
Host smart-6dec93d8-9a3f-4b20-98fc-7e440df211a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303186723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.3303186723
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.581069497
Short name T906
Test name
Test status
Simulation time 409713798 ps
CPU time 1.7 seconds
Started Jul 06 06:26:04 PM PDT 24
Finished Jul 06 06:26:06 PM PDT 24
Peak memory 217532 kb
Host smart-fe561699-24e4-41c7-a8f3-0af71bdb9a89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581069497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.581069497
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3552694142
Short name T959
Test name
Test status
Simulation time 34987293 ps
CPU time 1.1 seconds
Started Jul 06 06:26:16 PM PDT 24
Finished Jul 06 06:26:18 PM PDT 24
Peak memory 218820 kb
Host smart-da6fc240-e5d2-4df8-8586-336de05b4a95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552694142 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3552694142
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3671610031
Short name T195
Test name
Test status
Simulation time 61189413 ps
CPU time 1 seconds
Started Jul 06 06:26:12 PM PDT 24
Finished Jul 06 06:26:14 PM PDT 24
Peak memory 209032 kb
Host smart-d24f1e2c-4a4a-4fe9-9298-d9b34212a031
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671610031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3671610031
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1698864939
Short name T943
Test name
Test status
Simulation time 78668530 ps
CPU time 0.96 seconds
Started Jul 06 06:26:02 PM PDT 24
Finished Jul 06 06:26:03 PM PDT 24
Peak memory 209148 kb
Host smart-865f364f-8467-4736-a830-6cf786dde56c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698864939 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1698864939
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3333962930
Short name T927
Test name
Test status
Simulation time 231002568 ps
CPU time 3.01 seconds
Started Jul 06 06:26:06 PM PDT 24
Finished Jul 06 06:26:10 PM PDT 24
Peak memory 209000 kb
Host smart-2c588194-5e03-4428-b39b-06a5624126f5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333962930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3333962930
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3561074653
Short name T980
Test name
Test status
Simulation time 491165672 ps
CPU time 12.5 seconds
Started Jul 06 06:26:03 PM PDT 24
Finished Jul 06 06:26:16 PM PDT 24
Peak memory 209232 kb
Host smart-ca303043-507f-421f-8f3e-593d8e6a909a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561074653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.3561074653
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.35564073
Short name T140
Test name
Test status
Simulation time 199546762 ps
CPU time 2.76 seconds
Started Jul 06 06:26:04 PM PDT 24
Finished Jul 06 06:26:07 PM PDT 24
Peak memory 210896 kb
Host smart-8c964b60-f3cb-41e2-9a3c-e8d4e0277066
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35564073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.35564073
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1036739360
Short name T867
Test name
Test status
Simulation time 431674878 ps
CPU time 6.34 seconds
Started Jul 06 06:26:03 PM PDT 24
Finished Jul 06 06:26:10 PM PDT 24
Peak memory 218612 kb
Host smart-dd1f28d4-b6ba-4803-a88a-145228bc689b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103673
9360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1036739360
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2068438536
Short name T917
Test name
Test status
Simulation time 202360893 ps
CPU time 1.87 seconds
Started Jul 06 06:26:04 PM PDT 24
Finished Jul 06 06:26:06 PM PDT 24
Peak memory 217436 kb
Host smart-908e3841-aefb-42c1-91b2-468898e9a825
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068438536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.2068438536
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3465867453
Short name T947
Test name
Test status
Simulation time 222935567 ps
CPU time 1.86 seconds
Started Jul 06 06:26:01 PM PDT 24
Finished Jul 06 06:26:03 PM PDT 24
Peak memory 209332 kb
Host smart-1d9d19ea-9b7b-4b3f-9166-054d79119963
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465867453 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3465867453
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.897682603
Short name T936
Test name
Test status
Simulation time 97088212 ps
CPU time 1.11 seconds
Started Jul 06 06:26:07 PM PDT 24
Finished Jul 06 06:26:08 PM PDT 24
Peak memory 209364 kb
Host smart-66800036-cfd9-49b9-b930-9c8a086c7299
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897682603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
same_csr_outstanding.897682603
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1187409786
Short name T899
Test name
Test status
Simulation time 1395593522 ps
CPU time 3.04 seconds
Started Jul 06 06:26:00 PM PDT 24
Finished Jul 06 06:26:03 PM PDT 24
Peak memory 217636 kb
Host smart-291bad2c-e76f-4af9-9714-c5a2bb6034ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187409786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1187409786
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.2785891040
Short name T376
Test name
Test status
Simulation time 51188700 ps
CPU time 1.09 seconds
Started Jul 06 06:29:30 PM PDT 24
Finished Jul 06 06:29:31 PM PDT 24
Peak memory 208968 kb
Host smart-c280a6dd-7256-4d88-b515-c3ad96a61294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785891040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2785891040
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.3021189887
Short name T559
Test name
Test status
Simulation time 273216077 ps
CPU time 11.36 seconds
Started Jul 06 06:29:24 PM PDT 24
Finished Jul 06 06:29:35 PM PDT 24
Peak memory 226052 kb
Host smart-d8889de9-6741-4762-a498-4d03d814b5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021189887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.3021189887
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.978896632
Short name T444
Test name
Test status
Simulation time 10142501156 ps
CPU time 16.68 seconds
Started Jul 06 06:29:31 PM PDT 24
Finished Jul 06 06:29:48 PM PDT 24
Peak memory 217740 kb
Host smart-9e24b1dd-409e-4b92-8659-8ff97a5d22ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978896632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.978896632
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3950422637
Short name T398
Test name
Test status
Simulation time 2702307160 ps
CPU time 76 seconds
Started Jul 06 06:29:35 PM PDT 24
Finished Jul 06 06:30:51 PM PDT 24
Peak memory 226064 kb
Host smart-a483a0f3-ca6e-4270-ad04-52a79faf1963
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950422637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3950422637
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.791951645
Short name T763
Test name
Test status
Simulation time 1043324562 ps
CPU time 6.66 seconds
Started Jul 06 06:29:27 PM PDT 24
Finished Jul 06 06:29:35 PM PDT 24
Peak memory 217752 kb
Host smart-5a564657-a726-4af7-9d09-62ff7f876bc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791951645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.791951645
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.646940636
Short name T566
Test name
Test status
Simulation time 3236870457 ps
CPU time 15.77 seconds
Started Jul 06 06:29:25 PM PDT 24
Finished Jul 06 06:29:42 PM PDT 24
Peak memory 218324 kb
Host smart-dcd9a9aa-4bbd-4cec-8d06-daa6052872f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646940636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
prog_failure.646940636
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3903292301
Short name T746
Test name
Test status
Simulation time 2124769050 ps
CPU time 36.45 seconds
Started Jul 06 06:29:25 PM PDT 24
Finished Jul 06 06:30:02 PM PDT 24
Peak memory 217696 kb
Host smart-62338569-5656-4232-8f86-768873b3fc51
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903292301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.3903292301
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3035098766
Short name T680
Test name
Test status
Simulation time 3432209574 ps
CPU time 4.33 seconds
Started Jul 06 06:29:31 PM PDT 24
Finished Jul 06 06:29:36 PM PDT 24
Peak memory 217816 kb
Host smart-2ad71ff0-0d05-46f5-adc0-e15348e45c60
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035098766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3035098766
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.813302737
Short name T738
Test name
Test status
Simulation time 2611735752 ps
CPU time 93.98 seconds
Started Jul 06 06:29:26 PM PDT 24
Finished Jul 06 06:31:00 PM PDT 24
Peak memory 272352 kb
Host smart-1bc52b5a-9a1a-4389-9471-43097f81f314
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813302737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_state_failure.813302737
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.4156448688
Short name T560
Test name
Test status
Simulation time 341007776 ps
CPU time 15.17 seconds
Started Jul 06 06:29:28 PM PDT 24
Finished Jul 06 06:29:44 PM PDT 24
Peak memory 246344 kb
Host smart-fcf6f4bf-f3e7-497d-80db-e8ce6feeb240
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156448688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.4156448688
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1984282232
Short name T212
Test name
Test status
Simulation time 119117379 ps
CPU time 2.66 seconds
Started Jul 06 06:29:23 PM PDT 24
Finished Jul 06 06:29:26 PM PDT 24
Peak memory 218200 kb
Host smart-93f594e8-819b-4491-809c-d30dd801d876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984282232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1984282232
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3327866624
Short name T610
Test name
Test status
Simulation time 350797260 ps
CPU time 12.81 seconds
Started Jul 06 06:29:31 PM PDT 24
Finished Jul 06 06:29:44 PM PDT 24
Peak memory 217728 kb
Host smart-45375677-cf50-4771-a9dd-eef383d61428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327866624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3327866624
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.1132195301
Short name T513
Test name
Test status
Simulation time 669982432 ps
CPU time 14.51 seconds
Started Jul 06 06:29:30 PM PDT 24
Finished Jul 06 06:29:45 PM PDT 24
Peak memory 225996 kb
Host smart-ae85f65e-a1f0-476e-97ff-f4da9b0568b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132195301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.1132195301
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2771487038
Short name T100
Test name
Test status
Simulation time 674274038 ps
CPU time 14.4 seconds
Started Jul 06 06:29:27 PM PDT 24
Finished Jul 06 06:29:42 PM PDT 24
Peak memory 225988 kb
Host smart-61bc82dc-fbde-446c-9f82-2c0a1affe89a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771487038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2771487038
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.311723246
Short name T857
Test name
Test status
Simulation time 239223082 ps
CPU time 8.97 seconds
Started Jul 06 06:29:26 PM PDT 24
Finished Jul 06 06:29:35 PM PDT 24
Peak memory 218248 kb
Host smart-90efc7e2-4949-45ab-83c5-0e0084c709d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311723246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.311723246
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.2041282611
Short name T592
Test name
Test status
Simulation time 601609631 ps
CPU time 7.94 seconds
Started Jul 06 06:29:28 PM PDT 24
Finished Jul 06 06:29:37 PM PDT 24
Peak memory 225988 kb
Host smart-fa8151b0-9368-45d1-881c-7795a7d700bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041282611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2041282611
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.879788338
Short name T545
Test name
Test status
Simulation time 126702469 ps
CPU time 2.02 seconds
Started Jul 06 06:29:23 PM PDT 24
Finished Jul 06 06:29:25 PM PDT 24
Peak memory 214380 kb
Host smart-1bdd0153-d02b-4d19-9d62-cd2f8b80c0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879788338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.879788338
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.699208381
Short name T453
Test name
Test status
Simulation time 155187540 ps
CPU time 15.41 seconds
Started Jul 06 06:29:31 PM PDT 24
Finished Jul 06 06:29:47 PM PDT 24
Peak memory 245952 kb
Host smart-303d6789-7b89-4def-ae99-e792d8f37212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699208381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.699208381
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1507047079
Short name T801
Test name
Test status
Simulation time 145701184 ps
CPU time 6.59 seconds
Started Jul 06 06:29:27 PM PDT 24
Finished Jul 06 06:29:34 PM PDT 24
Peak memory 250128 kb
Host smart-1530f90e-6037-4a26-944c-e03289f399c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507047079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1507047079
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.3171250279
Short name T235
Test name
Test status
Simulation time 4494460637 ps
CPU time 121.84 seconds
Started Jul 06 06:29:27 PM PDT 24
Finished Jul 06 06:31:30 PM PDT 24
Peak memory 250716 kb
Host smart-739151e6-a9e2-47f8-93e1-c37faeea7bce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171250279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.3171250279
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.3691894735
Short name T143
Test name
Test status
Simulation time 253296746074 ps
CPU time 549.43 seconds
Started Jul 06 06:29:26 PM PDT 24
Finished Jul 06 06:38:35 PM PDT 24
Peak memory 294016 kb
Host smart-13ccdc2e-fe40-4278-90c1-de7374736a19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3691894735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.3691894735
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3359685165
Short name T234
Test name
Test status
Simulation time 44138583 ps
CPU time 1.03 seconds
Started Jul 06 06:29:28 PM PDT 24
Finished Jul 06 06:29:29 PM PDT 24
Peak memory 211944 kb
Host smart-0bd2547f-e29b-4e63-9a0b-64e66aca6e5f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359685165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.3359685165
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1531582463
Short name T62
Test name
Test status
Simulation time 61189613 ps
CPU time 0.82 seconds
Started Jul 06 06:29:31 PM PDT 24
Finished Jul 06 06:29:33 PM PDT 24
Peak memory 209024 kb
Host smart-9ca0d441-15a1-40f5-a73d-698994b1852e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531582463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1531582463
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1687947572
Short name T502
Test name
Test status
Simulation time 12672296 ps
CPU time 0.84 seconds
Started Jul 06 06:29:30 PM PDT 24
Finished Jul 06 06:29:31 PM PDT 24
Peak memory 208976 kb
Host smart-17461bf5-40cf-4db7-88cb-43b522acce8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687947572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.1687947572
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1669710526
Short name T588
Test name
Test status
Simulation time 1024324908 ps
CPU time 11.8 seconds
Started Jul 06 06:29:32 PM PDT 24
Finished Jul 06 06:29:44 PM PDT 24
Peak memory 218224 kb
Host smart-412ac084-4c25-4505-91cd-569d4e292e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669710526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1669710526
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.2169570267
Short name T441
Test name
Test status
Simulation time 474674424 ps
CPU time 6.29 seconds
Started Jul 06 06:29:34 PM PDT 24
Finished Jul 06 06:29:40 PM PDT 24
Peak memory 217692 kb
Host smart-3c59f4c2-ad08-429b-90ce-3d5eef3afd1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169570267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2169570267
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2757015770
Short name T641
Test name
Test status
Simulation time 1956063437 ps
CPU time 32.23 seconds
Started Jul 06 06:29:32 PM PDT 24
Finished Jul 06 06:30:05 PM PDT 24
Peak memory 225972 kb
Host smart-b5963719-54aa-489f-93e4-b0d499abf7e7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757015770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2757015770
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.4016279193
Short name T292
Test name
Test status
Simulation time 1643824322 ps
CPU time 16.37 seconds
Started Jul 06 06:29:29 PM PDT 24
Finished Jul 06 06:29:45 PM PDT 24
Peak memory 217772 kb
Host smart-3192bfa0-028e-43c0-88a5-4867262a798e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016279193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.4
016279193
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2567036358
Short name T386
Test name
Test status
Simulation time 338698243 ps
CPU time 6.29 seconds
Started Jul 06 06:29:33 PM PDT 24
Finished Jul 06 06:29:39 PM PDT 24
Peak memory 223044 kb
Host smart-ab5ff8b4-75c0-456c-9dfd-f773e22d3cf0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567036358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2567036358
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1102989239
Short name T790
Test name
Test status
Simulation time 1020721493 ps
CPU time 30.19 seconds
Started Jul 06 06:29:33 PM PDT 24
Finished Jul 06 06:30:04 PM PDT 24
Peak memory 217752 kb
Host smart-4a417b40-8a1d-4191-8680-b007d70f5114
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102989239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.1102989239
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.706558650
Short name T27
Test name
Test status
Simulation time 61165890 ps
CPU time 1.62 seconds
Started Jul 06 06:29:41 PM PDT 24
Finished Jul 06 06:29:43 PM PDT 24
Peak memory 217724 kb
Host smart-6cd461ed-c264-4ef3-9a7b-e8f43799df02
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706558650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.706558650
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.1111062322
Short name T158
Test name
Test status
Simulation time 18951351287 ps
CPU time 70.24 seconds
Started Jul 06 06:29:32 PM PDT 24
Finished Jul 06 06:30:43 PM PDT 24
Peak memory 267440 kb
Host smart-d9e1f18b-9a1c-4578-baf0-9e1bb117ef9e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111062322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.1111062322
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1394052803
Short name T859
Test name
Test status
Simulation time 633328472 ps
CPU time 16.06 seconds
Started Jul 06 06:29:31 PM PDT 24
Finished Jul 06 06:29:48 PM PDT 24
Peak memory 250992 kb
Host smart-08c6154c-87ef-4372-b64c-9c8f752c4ca0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394052803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1394052803
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.748293722
Short name T56
Test name
Test status
Simulation time 994890706 ps
CPU time 23.67 seconds
Started Jul 06 06:29:32 PM PDT 24
Finished Jul 06 06:29:56 PM PDT 24
Peak memory 217712 kb
Host smart-871504aa-aab4-400f-b849-cf94745f5201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748293722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.748293722
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.3609153963
Short name T51
Test name
Test status
Simulation time 612654919 ps
CPU time 36.59 seconds
Started Jul 06 06:29:43 PM PDT 24
Finished Jul 06 06:30:19 PM PDT 24
Peak memory 268160 kb
Host smart-edd64499-6a1a-424f-85a8-f441cc99674c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609153963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.3609153963
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.2311677549
Short name T301
Test name
Test status
Simulation time 644827322 ps
CPU time 16.53 seconds
Started Jul 06 06:29:43 PM PDT 24
Finished Jul 06 06:30:00 PM PDT 24
Peak memory 218892 kb
Host smart-52e4c53c-0eb1-4ff7-8dc8-d609cb9f7ccf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311677549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2311677549
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.978384138
Short name T411
Test name
Test status
Simulation time 2745563313 ps
CPU time 25.39 seconds
Started Jul 06 06:29:43 PM PDT 24
Finished Jul 06 06:30:09 PM PDT 24
Peak memory 226112 kb
Host smart-e86e1841-af48-4d65-a22f-715db069c93e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978384138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dig
est.978384138
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2796099441
Short name T480
Test name
Test status
Simulation time 406676071 ps
CPU time 13.18 seconds
Started Jul 06 06:29:33 PM PDT 24
Finished Jul 06 06:29:47 PM PDT 24
Peak memory 218244 kb
Host smart-44227a73-116d-4bc5-bd5d-4aa8b94fc3bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796099441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
796099441
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3541217463
Short name T388
Test name
Test status
Simulation time 1734036511 ps
CPU time 15.73 seconds
Started Jul 06 06:29:27 PM PDT 24
Finished Jul 06 06:29:43 PM PDT 24
Peak memory 226060 kb
Host smart-05f38e91-2e28-4876-9988-be36909edef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541217463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3541217463
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.3342468605
Short name T366
Test name
Test status
Simulation time 145614436 ps
CPU time 2.31 seconds
Started Jul 06 06:29:29 PM PDT 24
Finished Jul 06 06:29:32 PM PDT 24
Peak memory 214384 kb
Host smart-fb2427ee-394d-48c8-bb5c-f0fb33421bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342468605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.3342468605
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.1061622535
Short name T445
Test name
Test status
Simulation time 527965721 ps
CPU time 29.13 seconds
Started Jul 06 06:29:30 PM PDT 24
Finished Jul 06 06:29:59 PM PDT 24
Peak memory 251012 kb
Host smart-3c0d7256-28fe-4ca5-9769-f29419b8403e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061622535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1061622535
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1358328366
Short name T319
Test name
Test status
Simulation time 182263001 ps
CPU time 8.53 seconds
Started Jul 06 06:29:26 PM PDT 24
Finished Jul 06 06:29:35 PM PDT 24
Peak memory 250992 kb
Host smart-f5d4d76b-26b9-4def-ab65-6bd42ed60fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358328366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1358328366
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.967979629
Short name T541
Test name
Test status
Simulation time 39616475412 ps
CPU time 170.85 seconds
Started Jul 06 06:29:29 PM PDT 24
Finished Jul 06 06:32:20 PM PDT 24
Peak memory 259344 kb
Host smart-6b3614b6-0544-40ea-b575-cd47e02f9945
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967979629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.967979629
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1996431997
Short name T785
Test name
Test status
Simulation time 27985832 ps
CPU time 0.94 seconds
Started Jul 06 06:29:30 PM PDT 24
Finished Jul 06 06:29:31 PM PDT 24
Peak memory 211896 kb
Host smart-0c66eebc-72df-4528-9848-63256dda309d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996431997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1996431997
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.3258981731
Short name T170
Test name
Test status
Simulation time 29308944 ps
CPU time 1.05 seconds
Started Jul 06 06:30:06 PM PDT 24
Finished Jul 06 06:30:08 PM PDT 24
Peak memory 208952 kb
Host smart-22de56a7-cf2b-47cb-b34a-4db1446d29e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258981731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3258981731
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.1425098370
Short name T710
Test name
Test status
Simulation time 984372366 ps
CPU time 9.61 seconds
Started Jul 06 06:29:55 PM PDT 24
Finished Jul 06 06:30:05 PM PDT 24
Peak memory 218160 kb
Host smart-53d5dd20-283b-4248-8b4e-32ecfc646ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425098370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1425098370
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.3128815622
Short name T354
Test name
Test status
Simulation time 3021878668 ps
CPU time 17.8 seconds
Started Jul 06 06:30:02 PM PDT 24
Finished Jul 06 06:30:20 PM PDT 24
Peak memory 217600 kb
Host smart-82ea06a1-738b-4b35-917d-45dae7f79b53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128815622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.3128815622
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.3605799052
Short name T676
Test name
Test status
Simulation time 1458612170 ps
CPU time 31.75 seconds
Started Jul 06 06:30:08 PM PDT 24
Finished Jul 06 06:30:40 PM PDT 24
Peak memory 218112 kb
Host smart-b32ef07b-2704-4fda-8505-6ebf63ef1cf7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605799052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.3605799052
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.4089818130
Short name T834
Test name
Test status
Simulation time 317926907 ps
CPU time 10.69 seconds
Started Jul 06 06:30:01 PM PDT 24
Finished Jul 06 06:30:12 PM PDT 24
Peak memory 223160 kb
Host smart-e6a25d75-a281-442c-a163-4af2dc656e3a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089818130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.4089818130
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.765197042
Short name T67
Test name
Test status
Simulation time 1881115466 ps
CPU time 12.64 seconds
Started Jul 06 06:30:08 PM PDT 24
Finished Jul 06 06:30:21 PM PDT 24
Peak memory 217740 kb
Host smart-5898e46c-f278-4463-87d4-fc5123ae95e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765197042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke.
765197042
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1109035368
Short name T26
Test name
Test status
Simulation time 3891881917 ps
CPU time 23 seconds
Started Jul 06 06:30:02 PM PDT 24
Finished Jul 06 06:30:26 PM PDT 24
Peak memory 251032 kb
Host smart-8fa65b14-5f57-438c-a291-eda1ac88ab00
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109035368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1109035368
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2530167522
Short name T107
Test name
Test status
Simulation time 335991093 ps
CPU time 14.32 seconds
Started Jul 06 06:30:03 PM PDT 24
Finished Jul 06 06:30:17 PM PDT 24
Peak memory 246492 kb
Host smart-bf90b4dc-e2f4-40be-ba77-e5ca80417517
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530167522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.2530167522
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.458446278
Short name T415
Test name
Test status
Simulation time 95303052 ps
CPU time 3.32 seconds
Started Jul 06 06:29:54 PM PDT 24
Finished Jul 06 06:29:58 PM PDT 24
Peak memory 222276 kb
Host smart-a0bf0241-2985-4960-9786-2da55a026cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458446278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.458446278
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1866325252
Short name T281
Test name
Test status
Simulation time 760346279 ps
CPU time 10.71 seconds
Started Jul 06 06:30:08 PM PDT 24
Finished Jul 06 06:30:19 PM PDT 24
Peak memory 226008 kb
Host smart-940956f4-08c9-4c91-80df-858354cb4cb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866325252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1866325252
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1822480381
Short name T776
Test name
Test status
Simulation time 1758296845 ps
CPU time 15.27 seconds
Started Jul 06 06:30:04 PM PDT 24
Finished Jul 06 06:30:20 PM PDT 24
Peak memory 218144 kb
Host smart-3b7cee6d-c86c-492b-8209-7d44d558c678
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822480381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1822480381
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1182269244
Short name T208
Test name
Test status
Simulation time 661491019 ps
CPU time 8.64 seconds
Started Jul 06 06:30:10 PM PDT 24
Finished Jul 06 06:30:19 PM PDT 24
Peak memory 226064 kb
Host smart-f8e40e4d-d876-4c95-a0c0-ffd86957feed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182269244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1182269244
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.2525662515
Short name T277
Test name
Test status
Simulation time 363536876 ps
CPU time 6.3 seconds
Started Jul 06 06:29:57 PM PDT 24
Finished Jul 06 06:30:04 PM PDT 24
Peak memory 217640 kb
Host smart-64386440-062b-4e1a-b678-3584a059583b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525662515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.2525662515
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.277095045
Short name T94
Test name
Test status
Simulation time 302951389 ps
CPU time 26.91 seconds
Started Jul 06 06:30:09 PM PDT 24
Finished Jul 06 06:30:36 PM PDT 24
Peak memory 251008 kb
Host smart-a2e1761b-c7b7-4317-a56f-20f96c022dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277095045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.277095045
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2341408632
Short name T587
Test name
Test status
Simulation time 45794735 ps
CPU time 7.68 seconds
Started Jul 06 06:30:10 PM PDT 24
Finished Jul 06 06:30:18 PM PDT 24
Peak memory 242824 kb
Host smart-2f33dfbd-81c1-4d04-8992-33789fd31678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341408632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2341408632
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.3332096223
Short name T218
Test name
Test status
Simulation time 3759186448 ps
CPU time 138.46 seconds
Started Jul 06 06:30:07 PM PDT 24
Finished Jul 06 06:32:26 PM PDT 24
Peak memory 283844 kb
Host smart-090225e8-3992-4150-ae0c-f26b2db350aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332096223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.3332096223
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.3909740166
Short name T709
Test name
Test status
Simulation time 43337309925 ps
CPU time 679.71 seconds
Started Jul 06 06:30:04 PM PDT 24
Finished Jul 06 06:41:24 PM PDT 24
Peak memory 292300 kb
Host smart-b93fa61a-b084-4bec-b2e9-5bb60bb4ac55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3909740166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.3909740166
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3373735435
Short name T273
Test name
Test status
Simulation time 13416054 ps
CPU time 0.86 seconds
Started Jul 06 06:30:02 PM PDT 24
Finished Jul 06 06:30:04 PM PDT 24
Peak memory 211928 kb
Host smart-21191014-220e-4c74-ba5f-a80540a569b8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373735435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3373735435
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.3427966038
Short name T263
Test name
Test status
Simulation time 14105121 ps
CPU time 0.97 seconds
Started Jul 06 06:30:16 PM PDT 24
Finished Jul 06 06:30:17 PM PDT 24
Peak memory 209056 kb
Host smart-32020120-a2d2-4b2c-8932-4267521c6dd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427966038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3427966038
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.25091355
Short name T168
Test name
Test status
Simulation time 465542688 ps
CPU time 15.2 seconds
Started Jul 06 06:30:05 PM PDT 24
Finished Jul 06 06:30:20 PM PDT 24
Peak memory 218240 kb
Host smart-1105201a-2fbc-4fc1-89b9-06eb1aa9f29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25091355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.25091355
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.2647075967
Short name T8
Test name
Test status
Simulation time 543793368 ps
CPU time 5.97 seconds
Started Jul 06 06:30:03 PM PDT 24
Finished Jul 06 06:30:10 PM PDT 24
Peak memory 217276 kb
Host smart-aeccd1b3-7190-4e62-bef5-e42e0b5003ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647075967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.2647075967
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.512742941
Short name T485
Test name
Test status
Simulation time 3312586210 ps
CPU time 52.94 seconds
Started Jul 06 06:30:05 PM PDT 24
Finished Jul 06 06:30:58 PM PDT 24
Peak memory 218940 kb
Host smart-8f52aa22-a488-477a-8c22-85cd1f8157d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512742941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_er
rors.512742941
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2098806789
Short name T596
Test name
Test status
Simulation time 779774299 ps
CPU time 5.55 seconds
Started Jul 06 06:30:01 PM PDT 24
Finished Jul 06 06:30:07 PM PDT 24
Peak memory 218188 kb
Host smart-de3507cd-0c59-4b3e-b491-bde86722196e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098806789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.2098806789
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.4241611969
Short name T76
Test name
Test status
Simulation time 812713687 ps
CPU time 11.47 seconds
Started Jul 06 06:30:02 PM PDT 24
Finished Jul 06 06:30:14 PM PDT 24
Peak memory 217712 kb
Host smart-2b2783c9-b18c-4bbe-96e0-72f691696f52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241611969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.4241611969
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2646094225
Short name T279
Test name
Test status
Simulation time 5157495056 ps
CPU time 36.34 seconds
Started Jul 06 06:30:05 PM PDT 24
Finished Jul 06 06:30:42 PM PDT 24
Peak memory 270948 kb
Host smart-76ccb21e-05cf-4b3e-adba-ea1e6e46ff75
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646094225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.2646094225
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1852519722
Short name T640
Test name
Test status
Simulation time 1223958814 ps
CPU time 25.65 seconds
Started Jul 06 06:30:02 PM PDT 24
Finished Jul 06 06:30:28 PM PDT 24
Peak memory 251004 kb
Host smart-004de27b-ec38-4b2f-8e39-390b39042102
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852519722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.1852519722
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2431776160
Short name T451
Test name
Test status
Simulation time 103675636 ps
CPU time 2.76 seconds
Started Jul 06 06:30:05 PM PDT 24
Finished Jul 06 06:30:08 PM PDT 24
Peak memory 218236 kb
Host smart-c91923d2-2319-45b1-af82-9e493c65effd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431776160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2431776160
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.350503354
Short name T555
Test name
Test status
Simulation time 238787560 ps
CPU time 10.42 seconds
Started Jul 06 06:30:12 PM PDT 24
Finished Jul 06 06:30:23 PM PDT 24
Peak memory 218252 kb
Host smart-8d377f48-f9c6-46ae-8c92-a604840f292b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350503354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_di
gest.350503354
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1804869519
Short name T551
Test name
Test status
Simulation time 1032038761 ps
CPU time 10.95 seconds
Started Jul 06 06:30:06 PM PDT 24
Finished Jul 06 06:30:18 PM PDT 24
Peak memory 226064 kb
Host smart-74b8e45b-ea4a-42b7-9cb3-de2bf1b6544d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804869519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1804869519
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.1715973308
Short name T664
Test name
Test status
Simulation time 18793082 ps
CPU time 1.5 seconds
Started Jul 06 06:30:02 PM PDT 24
Finished Jul 06 06:30:04 PM PDT 24
Peak memory 217736 kb
Host smart-dcc73c72-2cfc-46b4-a270-4ef53a81c19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715973308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.1715973308
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.2614175376
Short name T617
Test name
Test status
Simulation time 1449294730 ps
CPU time 31.16 seconds
Started Jul 06 06:30:09 PM PDT 24
Finished Jul 06 06:30:40 PM PDT 24
Peak memory 250952 kb
Host smart-1e78c075-c753-4771-8800-657a7edbb2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614175376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.2614175376
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.2057567397
Short name T603
Test name
Test status
Simulation time 82884319 ps
CPU time 3.5 seconds
Started Jul 06 06:30:01 PM PDT 24
Finished Jul 06 06:30:05 PM PDT 24
Peak memory 221876 kb
Host smart-2fa1141d-0b8a-4db2-bef8-229ffbaf6c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057567397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.2057567397
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.196792586
Short name T711
Test name
Test status
Simulation time 6249566407 ps
CPU time 51.92 seconds
Started Jul 06 06:30:16 PM PDT 24
Finished Jul 06 06:31:08 PM PDT 24
Peak memory 243872 kb
Host smart-e841b0b0-86f9-4f83-8f00-70e1237406cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196792586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.196792586
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2823229173
Short name T739
Test name
Test status
Simulation time 25920160 ps
CPU time 0.89 seconds
Started Jul 06 06:30:07 PM PDT 24
Finished Jul 06 06:30:08 PM PDT 24
Peak memory 211900 kb
Host smart-cd36780d-db0f-4abb-8823-64cf674d8a88
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823229173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2823229173
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.2843552563
Short name T199
Test name
Test status
Simulation time 170983900 ps
CPU time 0.99 seconds
Started Jul 06 06:30:10 PM PDT 24
Finished Jul 06 06:30:11 PM PDT 24
Peak memory 208884 kb
Host smart-4d565912-58ba-46b6-83ea-e7ad95509b09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843552563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.2843552563
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.4142973730
Short name T477
Test name
Test status
Simulation time 1586957734 ps
CPU time 10.42 seconds
Started Jul 06 06:30:17 PM PDT 24
Finished Jul 06 06:30:28 PM PDT 24
Peak memory 226036 kb
Host smart-8465ec71-9450-43d4-9cb8-863559b05466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142973730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.4142973730
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.3842636900
Short name T534
Test name
Test status
Simulation time 138220096 ps
CPU time 4.07 seconds
Started Jul 06 06:30:10 PM PDT 24
Finished Jul 06 06:30:14 PM PDT 24
Peak memory 216988 kb
Host smart-a1a7a54d-03bd-4ec1-b467-cc8b7bc7a0b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842636900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3842636900
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3447797120
Short name T460
Test name
Test status
Simulation time 10826004327 ps
CPU time 41.91 seconds
Started Jul 06 06:30:10 PM PDT 24
Finished Jul 06 06:30:52 PM PDT 24
Peak memory 218860 kb
Host smart-defbafb2-102f-410c-b534-066de0e9d765
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447797120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3447797120
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3575044195
Short name T604
Test name
Test status
Simulation time 2186146450 ps
CPU time 8.17 seconds
Started Jul 06 06:30:15 PM PDT 24
Finished Jul 06 06:30:23 PM PDT 24
Peak memory 224212 kb
Host smart-d87ff17d-010c-4ab9-abff-8d23c4d3faa7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575044195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.3575044195
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3627962115
Short name T747
Test name
Test status
Simulation time 1828959689 ps
CPU time 12.81 seconds
Started Jul 06 06:30:06 PM PDT 24
Finished Jul 06 06:30:19 PM PDT 24
Peak memory 217720 kb
Host smart-8fe5bb91-21ed-42f9-8a80-0fd7b7313262
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627962115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.3627962115
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3391693914
Short name T350
Test name
Test status
Simulation time 2749543875 ps
CPU time 36.59 seconds
Started Jul 06 06:30:06 PM PDT 24
Finished Jul 06 06:30:43 PM PDT 24
Peak memory 254316 kb
Host smart-282fda31-6126-40f0-abf9-802fecb95cb1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391693914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3391693914
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.4233748876
Short name T227
Test name
Test status
Simulation time 1792594544 ps
CPU time 15.27 seconds
Started Jul 06 06:30:04 PM PDT 24
Finished Jul 06 06:30:20 PM PDT 24
Peak memory 226400 kb
Host smart-0f3d231a-5573-4f71-b2fd-177863267bea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233748876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.4233748876
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.3956653824
Short name T825
Test name
Test status
Simulation time 77919508 ps
CPU time 3.21 seconds
Started Jul 06 06:30:09 PM PDT 24
Finished Jul 06 06:30:12 PM PDT 24
Peak memory 222476 kb
Host smart-976ed10d-729c-40a1-add1-6af71d0e6b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956653824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3956653824
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.1465618554
Short name T618
Test name
Test status
Simulation time 838020003 ps
CPU time 13.78 seconds
Started Jul 06 06:30:09 PM PDT 24
Finished Jul 06 06:30:23 PM PDT 24
Peak memory 226052 kb
Host smart-f467cafc-82fd-423b-b06a-a73534058522
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465618554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1465618554
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2704156092
Short name T505
Test name
Test status
Simulation time 999001718 ps
CPU time 10.89 seconds
Started Jul 06 06:30:14 PM PDT 24
Finished Jul 06 06:30:25 PM PDT 24
Peak memory 226016 kb
Host smart-e63f044e-9be2-4a01-a3d7-29ea6c040d35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704156092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.2704156092
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1638217639
Short name T846
Test name
Test status
Simulation time 1432754167 ps
CPU time 13.96 seconds
Started Jul 06 06:30:12 PM PDT 24
Finished Jul 06 06:30:26 PM PDT 24
Peak memory 218256 kb
Host smart-6b6a13a8-c7f7-4e09-a5ee-b392359ce59b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638217639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1638217639
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.828935186
Short name T410
Test name
Test status
Simulation time 1051278581 ps
CPU time 10.81 seconds
Started Jul 06 06:30:06 PM PDT 24
Finished Jul 06 06:30:17 PM PDT 24
Peak memory 218392 kb
Host smart-978298f6-313c-4d5a-978e-a8338a768796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828935186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.828935186
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.3432663285
Short name T419
Test name
Test status
Simulation time 45381519 ps
CPU time 3.11 seconds
Started Jul 06 06:30:10 PM PDT 24
Finished Jul 06 06:30:13 PM PDT 24
Peak memory 214912 kb
Host smart-976ac35a-7fc2-40c0-aecc-3e6a3acfd665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432663285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.3432663285
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2031269399
Short name T743
Test name
Test status
Simulation time 173085776 ps
CPU time 23.12 seconds
Started Jul 06 06:30:11 PM PDT 24
Finished Jul 06 06:30:34 PM PDT 24
Peak memory 247592 kb
Host smart-54991798-567c-4856-b2d3-4d27846d7c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031269399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2031269399
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.393163524
Short name T768
Test name
Test status
Simulation time 55674072 ps
CPU time 7.71 seconds
Started Jul 06 06:30:06 PM PDT 24
Finished Jul 06 06:30:14 PM PDT 24
Peak memory 250980 kb
Host smart-eb67f9c9-6943-4ef8-ac2f-1add20d69ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393163524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.393163524
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.3328989043
Short name T670
Test name
Test status
Simulation time 3295280178 ps
CPU time 129.89 seconds
Started Jul 06 06:30:09 PM PDT 24
Finished Jul 06 06:32:19 PM PDT 24
Peak memory 275656 kb
Host smart-8e9ec661-e158-4e10-be00-5a5ce190ef16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328989043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.3328989043
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1791893560
Short name T323
Test name
Test status
Simulation time 28535742 ps
CPU time 0.8 seconds
Started Jul 06 06:30:21 PM PDT 24
Finished Jul 06 06:30:22 PM PDT 24
Peak memory 208316 kb
Host smart-854f0c0e-4582-4844-9530-1f0d4a62edea
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791893560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.1791893560
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3330144785
Short name T86
Test name
Test status
Simulation time 216657350 ps
CPU time 1.28 seconds
Started Jul 06 06:30:16 PM PDT 24
Finished Jul 06 06:30:18 PM PDT 24
Peak memory 209016 kb
Host smart-0c9c296f-4024-4ba1-9914-3aeb73bf68d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330144785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3330144785
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.3510450976
Short name T476
Test name
Test status
Simulation time 173265827 ps
CPU time 9.29 seconds
Started Jul 06 06:30:18 PM PDT 24
Finished Jul 06 06:30:27 PM PDT 24
Peak memory 226040 kb
Host smart-cba7b483-4d16-449a-a013-3b3977c9996a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510450976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.3510450976
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.1496622142
Short name T722
Test name
Test status
Simulation time 225143095 ps
CPU time 6.33 seconds
Started Jul 06 06:30:20 PM PDT 24
Finished Jul 06 06:30:27 PM PDT 24
Peak memory 217284 kb
Host smart-ae6f641a-cc15-46c8-9195-074d27693df3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496622142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.1496622142
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.1330459656
Short name T430
Test name
Test status
Simulation time 9753703819 ps
CPU time 41.4 seconds
Started Jul 06 06:30:22 PM PDT 24
Finished Jul 06 06:31:03 PM PDT 24
Peak memory 218988 kb
Host smart-5d89fe79-d158-4e1c-9902-346d8bf74ea3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330459656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.1330459656
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1409776746
Short name T515
Test name
Test status
Simulation time 378779278 ps
CPU time 11.95 seconds
Started Jul 06 06:30:11 PM PDT 24
Finished Jul 06 06:30:23 PM PDT 24
Peak memory 218260 kb
Host smart-32d19c21-40a3-48da-a277-013fdfdc3a27
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409776746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.1409776746
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.80256942
Short name T61
Test name
Test status
Simulation time 4337358184 ps
CPU time 7.46 seconds
Started Jul 06 06:30:18 PM PDT 24
Finished Jul 06 06:30:26 PM PDT 24
Peak memory 217784 kb
Host smart-0d9835ca-eb37-4b78-9a52-70363aa8d601
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80256942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.80256942
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3423212952
Short name T270
Test name
Test status
Simulation time 2674995450 ps
CPU time 28.64 seconds
Started Jul 06 06:30:11 PM PDT 24
Finished Jul 06 06:30:39 PM PDT 24
Peak memory 251148 kb
Host smart-200325e7-1397-40af-b3d5-38f21d961869
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423212952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3423212952
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.4136451583
Short name T10
Test name
Test status
Simulation time 690896357 ps
CPU time 10.32 seconds
Started Jul 06 06:30:13 PM PDT 24
Finished Jul 06 06:30:24 PM PDT 24
Peak memory 247428 kb
Host smart-fdc0210b-a982-48ef-a4f7-41f2bb001e4b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136451583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.4136451583
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.848828363
Short name T695
Test name
Test status
Simulation time 37451790 ps
CPU time 2.01 seconds
Started Jul 06 06:30:12 PM PDT 24
Finished Jul 06 06:30:15 PM PDT 24
Peak memory 218308 kb
Host smart-af2cccbb-4e5c-4ee3-b73c-012296818dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848828363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.848828363
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.2490081065
Short name T698
Test name
Test status
Simulation time 202714078 ps
CPU time 8.77 seconds
Started Jul 06 06:30:11 PM PDT 24
Finished Jul 06 06:30:20 PM PDT 24
Peak memory 226116 kb
Host smart-09ba65e6-c2f4-48e0-a9f7-6e691d30c845
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490081065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.2490081065
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.3099385302
Short name T690
Test name
Test status
Simulation time 1096323357 ps
CPU time 19.85 seconds
Started Jul 06 06:30:17 PM PDT 24
Finished Jul 06 06:30:37 PM PDT 24
Peak memory 226036 kb
Host smart-e39d2b1c-aea7-418e-bc01-acfbcf07dc18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099385302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.3099385302
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2685351564
Short name T689
Test name
Test status
Simulation time 757517679 ps
CPU time 14.24 seconds
Started Jul 06 06:30:18 PM PDT 24
Finished Jul 06 06:30:33 PM PDT 24
Peak memory 218244 kb
Host smart-8a184cd9-07c2-4be7-92e5-772f99fcd217
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685351564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
2685351564
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.4259823260
Short name T380
Test name
Test status
Simulation time 456007858 ps
CPU time 7.69 seconds
Started Jul 06 06:30:19 PM PDT 24
Finished Jul 06 06:30:27 PM PDT 24
Peak memory 218288 kb
Host smart-fb2a3f23-d0b6-44e3-8913-270d60e04f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259823260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.4259823260
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1732400386
Short name T418
Test name
Test status
Simulation time 92758507 ps
CPU time 3.35 seconds
Started Jul 06 06:30:15 PM PDT 24
Finished Jul 06 06:30:19 PM PDT 24
Peak memory 217692 kb
Host smart-dd5c7b3c-3e1e-4ae3-985d-1d0a7349cd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732400386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1732400386
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2751295683
Short name T509
Test name
Test status
Simulation time 259901203 ps
CPU time 25.44 seconds
Started Jul 06 06:30:12 PM PDT 24
Finished Jul 06 06:30:38 PM PDT 24
Peak memory 250992 kb
Host smart-899f817d-3014-4b2b-9b1c-2b2a1c18433c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751295683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2751295683
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.2514654599
Short name T349
Test name
Test status
Simulation time 44930334 ps
CPU time 9.55 seconds
Started Jul 06 06:30:18 PM PDT 24
Finished Jul 06 06:30:27 PM PDT 24
Peak memory 250960 kb
Host smart-33fdb85a-0dad-419b-873c-235a2fbf161f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514654599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2514654599
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3607718911
Short name T452
Test name
Test status
Simulation time 22241685219 ps
CPU time 163.33 seconds
Started Jul 06 06:30:22 PM PDT 24
Finished Jul 06 06:33:05 PM PDT 24
Peak memory 259204 kb
Host smart-5d166357-8205-4f8b-be14-25e7d932f350
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607718911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3607718911
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.4123781664
Short name T251
Test name
Test status
Simulation time 19311214 ps
CPU time 1.02 seconds
Started Jul 06 06:30:16 PM PDT 24
Finished Jul 06 06:30:17 PM PDT 24
Peak memory 212960 kb
Host smart-cd51a944-4364-4547-9a89-7ad793e2818a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123781664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.4123781664
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.561721431
Short name T264
Test name
Test status
Simulation time 26455059 ps
CPU time 1.02 seconds
Started Jul 06 06:30:14 PM PDT 24
Finished Jul 06 06:30:16 PM PDT 24
Peak memory 209004 kb
Host smart-b3b92535-c478-4f4a-a67c-7cf7c640e898
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561721431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.561721431
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2641840939
Short name T162
Test name
Test status
Simulation time 1315909367 ps
CPU time 15.57 seconds
Started Jul 06 06:30:18 PM PDT 24
Finished Jul 06 06:30:34 PM PDT 24
Peak memory 226040 kb
Host smart-0d16b1f7-ea58-4728-9b1a-eabe9c3aef89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641840939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2641840939
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.1305959277
Short name T34
Test name
Test status
Simulation time 195796958 ps
CPU time 1.98 seconds
Started Jul 06 06:30:25 PM PDT 24
Finished Jul 06 06:30:28 PM PDT 24
Peak memory 217088 kb
Host smart-d13240f4-c3c9-4e04-9d38-48bae225af5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305959277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.1305959277
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.3191171575
Short name T626
Test name
Test status
Simulation time 1973554325 ps
CPU time 35.34 seconds
Started Jul 06 06:30:15 PM PDT 24
Finished Jul 06 06:30:51 PM PDT 24
Peak memory 218244 kb
Host smart-93eff12f-5f98-49a8-9862-7134efb6899f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191171575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.3191171575
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1995599335
Short name T254
Test name
Test status
Simulation time 604954138 ps
CPU time 5.13 seconds
Started Jul 06 06:30:21 PM PDT 24
Finished Jul 06 06:30:26 PM PDT 24
Peak memory 218232 kb
Host smart-c896f9d3-7cd9-4ab1-99f4-2c528a5c7762
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995599335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.1995599335
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.628276340
Short name T377
Test name
Test status
Simulation time 119242903 ps
CPU time 4.02 seconds
Started Jul 06 06:30:27 PM PDT 24
Finished Jul 06 06:30:31 PM PDT 24
Peak memory 217700 kb
Host smart-7cb8a85d-7478-4b7b-810a-62073a360207
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628276340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke.
628276340
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.592162643
Short name T265
Test name
Test status
Simulation time 3481531282 ps
CPU time 36.48 seconds
Started Jul 06 06:30:15 PM PDT 24
Finished Jul 06 06:30:52 PM PDT 24
Peak memory 252044 kb
Host smart-08671c60-24d8-46c6-a941-4f7010488d6f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592162643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_state_failure.592162643
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.575579433
Short name T298
Test name
Test status
Simulation time 994877998 ps
CPU time 12.85 seconds
Started Jul 06 06:30:13 PM PDT 24
Finished Jul 06 06:30:26 PM PDT 24
Peak memory 250684 kb
Host smart-0c20d170-8825-426c-81a2-b63d39619eac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575579433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.575579433
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2065862991
Short name T373
Test name
Test status
Simulation time 391402369 ps
CPU time 3.4 seconds
Started Jul 06 06:30:14 PM PDT 24
Finished Jul 06 06:30:18 PM PDT 24
Peak memory 218272 kb
Host smart-f396be90-3274-4e8c-a0c8-e799cffed455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065862991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2065862991
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.2376970966
Short name T717
Test name
Test status
Simulation time 472971801 ps
CPU time 10.58 seconds
Started Jul 06 06:30:14 PM PDT 24
Finished Jul 06 06:30:25 PM PDT 24
Peak memory 218324 kb
Host smart-80e02c5a-643b-49bd-a0d1-74929b5261b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376970966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2376970966
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.838870916
Short name T580
Test name
Test status
Simulation time 1377155543 ps
CPU time 10.04 seconds
Started Jul 06 06:30:13 PM PDT 24
Finished Jul 06 06:30:23 PM PDT 24
Peak memory 225948 kb
Host smart-b3a687fe-d090-4e20-8da9-8ed4bdb4762c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838870916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di
gest.838870916
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.3785526385
Short name T741
Test name
Test status
Simulation time 696136921 ps
CPU time 9.02 seconds
Started Jul 06 06:30:20 PM PDT 24
Finished Jul 06 06:30:29 PM PDT 24
Peak memory 218208 kb
Host smart-f2e53055-722e-417d-83ac-600e770b9eb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785526385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
3785526385
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.232472434
Short name T500
Test name
Test status
Simulation time 836742907 ps
CPU time 8.34 seconds
Started Jul 06 06:30:19 PM PDT 24
Finished Jul 06 06:30:28 PM PDT 24
Peak memory 226040 kb
Host smart-758226fc-1e08-4501-994d-c7933ba1e8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232472434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.232472434
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3287869674
Short name T658
Test name
Test status
Simulation time 114233441 ps
CPU time 8.27 seconds
Started Jul 06 06:30:17 PM PDT 24
Finished Jul 06 06:30:26 PM PDT 24
Peak memory 217684 kb
Host smart-292322dd-65e7-4b33-9b38-fdf47af7765e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287869674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3287869674
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.782721707
Short name T802
Test name
Test status
Simulation time 2000813195 ps
CPU time 26.73 seconds
Started Jul 06 06:30:19 PM PDT 24
Finished Jul 06 06:30:46 PM PDT 24
Peak memory 250976 kb
Host smart-6d86387c-04f6-426f-89e8-e9e319eb90c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782721707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.782721707
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.650659419
Short name T433
Test name
Test status
Simulation time 71662214 ps
CPU time 2.92 seconds
Started Jul 06 06:30:14 PM PDT 24
Finished Jul 06 06:30:17 PM PDT 24
Peak memory 222540 kb
Host smart-e9692be8-3ba7-40cc-b408-c14f7763fdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650659419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.650659419
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.158906357
Short name T769
Test name
Test status
Simulation time 72154487427 ps
CPU time 301.18 seconds
Started Jul 06 06:30:15 PM PDT 24
Finished Jul 06 06:35:17 PM PDT 24
Peak memory 271456 kb
Host smart-581167d7-0d7a-427e-9ab5-5ecf4818afec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158906357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.158906357
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1759222081
Short name T238
Test name
Test status
Simulation time 35680153 ps
CPU time 0.93 seconds
Started Jul 06 06:30:15 PM PDT 24
Finished Jul 06 06:30:17 PM PDT 24
Peak memory 213004 kb
Host smart-a54dd0d6-bbfc-41bb-a308-2d0f98ce1210
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759222081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1759222081
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.4007659263
Short name T701
Test name
Test status
Simulation time 54396821 ps
CPU time 0.81 seconds
Started Jul 06 06:30:23 PM PDT 24
Finished Jul 06 06:30:24 PM PDT 24
Peak memory 208760 kb
Host smart-808659f5-ce9b-4513-9cbd-5d4440983d54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007659263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.4007659263
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.1655896025
Short name T756
Test name
Test status
Simulation time 1380981238 ps
CPU time 13.05 seconds
Started Jul 06 06:30:13 PM PDT 24
Finished Jul 06 06:30:27 PM PDT 24
Peak memory 218232 kb
Host smart-5fbf9e82-d183-4a3d-befa-1fcf524aae4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655896025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.1655896025
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.3993917696
Short name T729
Test name
Test status
Simulation time 2890353436 ps
CPU time 17.93 seconds
Started Jul 06 06:30:20 PM PDT 24
Finished Jul 06 06:30:38 PM PDT 24
Peak memory 217740 kb
Host smart-f42de960-a004-43bf-a6cb-635ebefbec63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993917696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.3993917696
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.872426032
Short name T308
Test name
Test status
Simulation time 7276629646 ps
CPU time 28.52 seconds
Started Jul 06 06:30:25 PM PDT 24
Finished Jul 06 06:30:54 PM PDT 24
Peak memory 218988 kb
Host smart-8250027f-9417-4e25-b0fa-44d08dcc07bb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872426032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_er
rors.872426032
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.1225905596
Short name T103
Test name
Test status
Simulation time 12920157869 ps
CPU time 18.14 seconds
Started Jul 06 06:30:18 PM PDT 24
Finished Jul 06 06:30:37 PM PDT 24
Peak memory 218304 kb
Host smart-0ae3de5c-123b-45c8-831f-83c29c9b0ded
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225905596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.1225905596
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3164048400
Short name T753
Test name
Test status
Simulation time 213829815 ps
CPU time 3.48 seconds
Started Jul 06 06:30:20 PM PDT 24
Finished Jul 06 06:30:24 PM PDT 24
Peak memory 217696 kb
Host smart-e06e14a1-bbab-48d0-aaeb-c356f9b05658
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164048400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.3164048400
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2855816105
Short name T243
Test name
Test status
Simulation time 8047199936 ps
CPU time 35.11 seconds
Started Jul 06 06:30:19 PM PDT 24
Finished Jul 06 06:30:55 PM PDT 24
Peak memory 275860 kb
Host smart-32b5dc50-b3e6-4e91-8d0b-53e6a0b371ea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855816105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.2855816105
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.804615786
Short name T781
Test name
Test status
Simulation time 2033010799 ps
CPU time 15.04 seconds
Started Jul 06 06:30:27 PM PDT 24
Finished Jul 06 06:30:43 PM PDT 24
Peak memory 250964 kb
Host smart-93e64163-0516-4ea2-bf70-150c06cb20fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804615786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_state_post_trans.804615786
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.538437258
Short name T740
Test name
Test status
Simulation time 78761186 ps
CPU time 3.32 seconds
Started Jul 06 06:30:15 PM PDT 24
Finished Jul 06 06:30:18 PM PDT 24
Peak memory 218200 kb
Host smart-05005619-b101-40f7-9333-6d60c5713ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538437258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.538437258
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.321103466
Short name T40
Test name
Test status
Simulation time 679911228 ps
CPU time 16.55 seconds
Started Jul 06 06:30:27 PM PDT 24
Finished Jul 06 06:30:44 PM PDT 24
Peak memory 218904 kb
Host smart-1be80858-d3ec-45b2-a45f-7b453a09139c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321103466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.321103466
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.1180148142
Short name T216
Test name
Test status
Simulation time 353151706 ps
CPU time 13.55 seconds
Started Jul 06 06:30:19 PM PDT 24
Finished Jul 06 06:30:33 PM PDT 24
Peak memory 226052 kb
Host smart-ccd25846-c562-4b31-b7fe-0e925db81ba1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180148142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.1180148142
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.3191661122
Short name T313
Test name
Test status
Simulation time 902051839 ps
CPU time 8.21 seconds
Started Jul 06 06:30:18 PM PDT 24
Finished Jul 06 06:30:27 PM PDT 24
Peak memory 218180 kb
Host smart-4b39af80-d2cb-46c9-9ab2-3fdd769f5c73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191661122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
3191661122
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.1666216202
Short name T678
Test name
Test status
Simulation time 1022882963 ps
CPU time 7.49 seconds
Started Jul 06 06:30:19 PM PDT 24
Finished Jul 06 06:30:27 PM PDT 24
Peak memory 224976 kb
Host smart-544fe3c3-55e0-49d5-879a-ef94b6d74072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666216202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.1666216202
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1488609316
Short name T636
Test name
Test status
Simulation time 458839048 ps
CPU time 5.35 seconds
Started Jul 06 06:30:15 PM PDT 24
Finished Jul 06 06:30:21 PM PDT 24
Peak memory 217724 kb
Host smart-d9eac4c3-f545-4ec2-82cb-62a7651d50c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488609316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1488609316
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.4093456648
Short name T837
Test name
Test status
Simulation time 932120173 ps
CPU time 28.74 seconds
Started Jul 06 06:30:15 PM PDT 24
Finished Jul 06 06:30:44 PM PDT 24
Peak memory 250960 kb
Host smart-2833d648-b391-4ff2-9838-c07c30de6acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093456648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.4093456648
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1743686041
Short name T167
Test name
Test status
Simulation time 91167570 ps
CPU time 7.05 seconds
Started Jul 06 06:30:12 PM PDT 24
Finished Jul 06 06:30:19 PM PDT 24
Peak memory 251000 kb
Host smart-4478f202-7ba9-4776-8dde-05fcf8033a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743686041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1743686041
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.49121489
Short name T821
Test name
Test status
Simulation time 3239907131 ps
CPU time 18.86 seconds
Started Jul 06 06:30:19 PM PDT 24
Finished Jul 06 06:30:38 PM PDT 24
Peak memory 251028 kb
Host smart-692659f7-7483-4096-968e-4b9660e4b12f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49121489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.lc_ctrl_stress_all.49121489
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1501741894
Short name T616
Test name
Test status
Simulation time 20395074 ps
CPU time 0.83 seconds
Started Jul 06 06:30:20 PM PDT 24
Finished Jul 06 06:30:21 PM PDT 24
Peak memory 211904 kb
Host smart-dad39f8e-1fd5-499c-ad47-3ac8fd684cb0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501741894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.1501741894
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.810162713
Short name T239
Test name
Test status
Simulation time 16727346 ps
CPU time 0.95 seconds
Started Jul 06 06:30:23 PM PDT 24
Finished Jul 06 06:30:24 PM PDT 24
Peak memory 209044 kb
Host smart-0ce2b859-6f28-4fbd-b936-fa61d156e451
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810162713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.810162713
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.1240324148
Short name T482
Test name
Test status
Simulation time 389079533 ps
CPU time 10.94 seconds
Started Jul 06 06:30:23 PM PDT 24
Finished Jul 06 06:30:34 PM PDT 24
Peak memory 226044 kb
Host smart-1849619b-c015-4e23-8a89-5a70366a7d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240324148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1240324148
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.3533782706
Short name T516
Test name
Test status
Simulation time 1434937634 ps
CPU time 7.52 seconds
Started Jul 06 06:30:26 PM PDT 24
Finished Jul 06 06:30:33 PM PDT 24
Peak memory 217440 kb
Host smart-3a285194-7abd-4017-98e7-0abd1bbb4a14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533782706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.3533782706
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3632607881
Short name T156
Test name
Test status
Simulation time 6244978775 ps
CPU time 27.9 seconds
Started Jul 06 06:30:24 PM PDT 24
Finished Jul 06 06:30:52 PM PDT 24
Peak memory 218608 kb
Host smart-d1756573-1f64-4826-9090-81acdb0b7833
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632607881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3632607881
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1676209506
Short name T638
Test name
Test status
Simulation time 108518820 ps
CPU time 2.53 seconds
Started Jul 06 06:30:33 PM PDT 24
Finished Jul 06 06:30:36 PM PDT 24
Peak memory 221556 kb
Host smart-bde82535-cffd-4e07-ac38-edae9fc0aec6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676209506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1676209506
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2288757148
Short name T77
Test name
Test status
Simulation time 66012174 ps
CPU time 2.51 seconds
Started Jul 06 06:30:24 PM PDT 24
Finished Jul 06 06:30:27 PM PDT 24
Peak memory 217836 kb
Host smart-55fd87b2-11b7-410e-b510-bbe9270f72bb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288757148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2288757148
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.205782715
Short name T675
Test name
Test status
Simulation time 1419823003 ps
CPU time 41.14 seconds
Started Jul 06 06:30:22 PM PDT 24
Finished Jul 06 06:31:03 PM PDT 24
Peak memory 267388 kb
Host smart-10e0b0db-6cff-46c2-95cc-366f7683785d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205782715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_state_failure.205782715
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.2864378417
Short name T716
Test name
Test status
Simulation time 2145794187 ps
CPU time 21.21 seconds
Started Jul 06 06:30:24 PM PDT 24
Finished Jul 06 06:30:45 PM PDT 24
Peak memory 250896 kb
Host smart-157f5881-7f26-4bd4-b358-5bb7ffea7b09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864378417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.2864378417
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.1459091147
Short name T791
Test name
Test status
Simulation time 258678518 ps
CPU time 3.92 seconds
Started Jul 06 06:30:22 PM PDT 24
Finished Jul 06 06:30:26 PM PDT 24
Peak memory 218252 kb
Host smart-15e1b4ad-bd3d-4dc7-8707-8cf0af4c89ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459091147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1459091147
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.627511275
Short name T831
Test name
Test status
Simulation time 724076438 ps
CPU time 7.34 seconds
Started Jul 06 06:30:30 PM PDT 24
Finished Jul 06 06:30:38 PM PDT 24
Peak memory 225996 kb
Host smart-42e5237e-0eed-4ae1-99da-4ce9fffb0102
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627511275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_di
gest.627511275
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3105521360
Short name T771
Test name
Test status
Simulation time 1110784569 ps
CPU time 10.49 seconds
Started Jul 06 06:30:27 PM PDT 24
Finished Jul 06 06:30:38 PM PDT 24
Peak memory 226068 kb
Host smart-0907e661-cb50-4393-961d-e0a93d9d290c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105521360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
3105521360
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.3620970318
Short name T621
Test name
Test status
Simulation time 619300121 ps
CPU time 9.73 seconds
Started Jul 06 06:30:25 PM PDT 24
Finished Jul 06 06:30:35 PM PDT 24
Peak memory 218276 kb
Host smart-0c2da1cd-bdda-41e2-b6f2-9fa86f4d85a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620970318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.3620970318
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.2897183943
Short name T832
Test name
Test status
Simulation time 166163361 ps
CPU time 4.44 seconds
Started Jul 06 06:30:21 PM PDT 24
Finished Jul 06 06:30:25 PM PDT 24
Peak memory 217712 kb
Host smart-3f201353-5574-4f8a-b1b6-ec95c8e846df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897183943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.2897183943
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2265903598
Short name T15
Test name
Test status
Simulation time 467422172 ps
CPU time 27.98 seconds
Started Jul 06 06:30:18 PM PDT 24
Finished Jul 06 06:30:47 PM PDT 24
Peak memory 251048 kb
Host smart-4795b6a0-54cf-4761-8b81-4cdd9dfdb0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265903598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2265903598
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.2665432481
Short name T320
Test name
Test status
Simulation time 113683841 ps
CPU time 6.86 seconds
Started Jul 06 06:30:29 PM PDT 24
Finished Jul 06 06:30:36 PM PDT 24
Peak memory 247160 kb
Host smart-18ffdade-0fed-4df1-bb2c-40d16696548b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665432481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.2665432481
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1087589092
Short name T247
Test name
Test status
Simulation time 18818471037 ps
CPU time 58.75 seconds
Started Jul 06 06:30:24 PM PDT 24
Finished Jul 06 06:31:23 PM PDT 24
Peak memory 283848 kb
Host smart-03c8b62e-2f0c-4d48-bf7b-d77100c04b5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087589092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1087589092
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.842992617
Short name T395
Test name
Test status
Simulation time 59276564 ps
CPU time 0.86 seconds
Started Jul 06 06:30:23 PM PDT 24
Finished Jul 06 06:30:25 PM PDT 24
Peak memory 211884 kb
Host smart-edea7bc2-7814-40d0-a813-475d69ef3706
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842992617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.842992617
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.3129264478
Short name T494
Test name
Test status
Simulation time 22537579 ps
CPU time 1.02 seconds
Started Jul 06 06:30:27 PM PDT 24
Finished Jul 06 06:30:29 PM PDT 24
Peak memory 208696 kb
Host smart-50fb7b6d-f5c6-4729-a51a-ce9328ac3b06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129264478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.3129264478
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.3305448721
Short name T473
Test name
Test status
Simulation time 1097594442 ps
CPU time 22.87 seconds
Started Jul 06 06:30:34 PM PDT 24
Finished Jul 06 06:30:57 PM PDT 24
Peak memory 218256 kb
Host smart-39a8a720-8fb4-4186-a7a8-584620371f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305448721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3305448721
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.2865634522
Short name T455
Test name
Test status
Simulation time 5253072938 ps
CPU time 3.81 seconds
Started Jul 06 06:30:29 PM PDT 24
Finished Jul 06 06:30:33 PM PDT 24
Peak memory 217784 kb
Host smart-a5e5daf4-e6b1-4437-a9a7-7004ebcb6abf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865634522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.2865634522
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.1783062880
Short name T83
Test name
Test status
Simulation time 2797297907 ps
CPU time 42.87 seconds
Started Jul 06 06:30:28 PM PDT 24
Finished Jul 06 06:31:11 PM PDT 24
Peak memory 218316 kb
Host smart-4b351c4d-eeba-48d4-a457-a7f1955cf062
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783062880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.1783062880
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.916197581
Short name T229
Test name
Test status
Simulation time 3205018204 ps
CPU time 5.8 seconds
Started Jul 06 06:30:32 PM PDT 24
Finished Jul 06 06:30:38 PM PDT 24
Peak memory 218376 kb
Host smart-ebb7dee3-af63-482c-bdcc-b6408d7c233c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916197581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.916197581
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.3012627095
Short name T772
Test name
Test status
Simulation time 1966411945 ps
CPU time 12.83 seconds
Started Jul 06 06:30:28 PM PDT 24
Finished Jul 06 06:30:41 PM PDT 24
Peak memory 217696 kb
Host smart-183f8a04-41d4-42ad-abc5-ba2763e28e26
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012627095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.3012627095
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1969084991
Short name T499
Test name
Test status
Simulation time 6360230246 ps
CPU time 55.14 seconds
Started Jul 06 06:30:34 PM PDT 24
Finished Jul 06 06:31:30 PM PDT 24
Peak memory 283768 kb
Host smart-ab42885f-d57e-497c-8d39-6b86bb8f57ee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969084991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.1969084991
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2060529826
Short name T780
Test name
Test status
Simulation time 990134887 ps
CPU time 9.21 seconds
Started Jul 06 06:30:28 PM PDT 24
Finished Jul 06 06:30:37 PM PDT 24
Peak memory 223284 kb
Host smart-d299b0af-a52a-49b8-bd4f-12cac2959531
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060529826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.2060529826
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.3650178483
Short name T628
Test name
Test status
Simulation time 54468857 ps
CPU time 3.12 seconds
Started Jul 06 06:30:27 PM PDT 24
Finished Jul 06 06:30:31 PM PDT 24
Peak memory 217828 kb
Host smart-e4a225cc-9bb6-46fc-9fb5-e285572b71db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650178483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3650178483
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.2270973463
Short name T602
Test name
Test status
Simulation time 366449405 ps
CPU time 9.8 seconds
Started Jul 06 06:30:28 PM PDT 24
Finished Jul 06 06:30:38 PM PDT 24
Peak memory 226032 kb
Host smart-fc9acb00-7ca4-43c4-86dd-b32e1fc917b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270973463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.2270973463
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.2940882968
Short name T443
Test name
Test status
Simulation time 887015543 ps
CPU time 9.3 seconds
Started Jul 06 06:30:31 PM PDT 24
Finished Jul 06 06:30:41 PM PDT 24
Peak memory 226048 kb
Host smart-89fae283-7475-4a91-a601-ff3909ce03d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940882968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.2940882968
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3734224694
Short name T770
Test name
Test status
Simulation time 1284364868 ps
CPU time 11.46 seconds
Started Jul 06 06:30:32 PM PDT 24
Finished Jul 06 06:30:44 PM PDT 24
Peak memory 218224 kb
Host smart-e4e173fb-84a8-457d-bff9-18d5029644ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734224694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
3734224694
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3357157721
Short name T726
Test name
Test status
Simulation time 389213098 ps
CPU time 15.22 seconds
Started Jul 06 06:30:30 PM PDT 24
Finished Jul 06 06:30:46 PM PDT 24
Peak memory 226048 kb
Host smart-a92a602d-6190-441f-9f57-f6035d67dc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357157721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3357157721
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.1954071981
Short name T333
Test name
Test status
Simulation time 40537593 ps
CPU time 2.6 seconds
Started Jul 06 06:30:23 PM PDT 24
Finished Jul 06 06:30:26 PM PDT 24
Peak memory 214740 kb
Host smart-0216ea79-4a76-438e-9e10-b4cdd5d6ce19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954071981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1954071981
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2427802000
Short name T652
Test name
Test status
Simulation time 297124560 ps
CPU time 28.4 seconds
Started Jul 06 06:30:31 PM PDT 24
Finished Jul 06 06:31:00 PM PDT 24
Peak memory 250956 kb
Host smart-6e611a19-4ed7-46cd-a183-96952c0d1c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427802000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2427802000
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.2108969029
Short name T835
Test name
Test status
Simulation time 809469369 ps
CPU time 6.87 seconds
Started Jul 06 06:30:27 PM PDT 24
Finished Jul 06 06:30:35 PM PDT 24
Peak memory 246700 kb
Host smart-d4c09106-e1d9-4b3f-9258-720854e320b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108969029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2108969029
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.4214840311
Short name T600
Test name
Test status
Simulation time 2095389955 ps
CPU time 31.23 seconds
Started Jul 06 06:30:26 PM PDT 24
Finished Jul 06 06:30:58 PM PDT 24
Peak memory 215924 kb
Host smart-30a12b14-5ab4-40e4-8fc1-39cae07f8f62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214840311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.4214840311
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.702603417
Short name T694
Test name
Test status
Simulation time 30467101 ps
CPU time 0.87 seconds
Started Jul 06 06:30:28 PM PDT 24
Finished Jul 06 06:30:30 PM PDT 24
Peak memory 211876 kb
Host smart-426b2d96-b687-4ac5-af3f-03be75590e3a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702603417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.702603417
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3080833288
Short name T436
Test name
Test status
Simulation time 73972712 ps
CPU time 0.95 seconds
Started Jul 06 06:30:33 PM PDT 24
Finished Jul 06 06:30:35 PM PDT 24
Peak memory 208832 kb
Host smart-cf24e68a-46b1-4089-869f-5e803f58d630
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080833288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3080833288
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3646306617
Short name T684
Test name
Test status
Simulation time 589864767 ps
CPU time 13.98 seconds
Started Jul 06 06:30:31 PM PDT 24
Finished Jul 06 06:30:45 PM PDT 24
Peak memory 218200 kb
Host smart-f005db6b-0ca3-490e-bfff-8fb0b18aa000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646306617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3646306617
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.440489599
Short name T822
Test name
Test status
Simulation time 1097870641 ps
CPU time 4.47 seconds
Started Jul 06 06:30:30 PM PDT 24
Finished Jul 06 06:30:35 PM PDT 24
Peak memory 217400 kb
Host smart-c4619893-6d52-4039-a778-1e3a2a880d8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440489599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.440489599
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2490127553
Short name T609
Test name
Test status
Simulation time 1347062256 ps
CPU time 22.06 seconds
Started Jul 06 06:30:35 PM PDT 24
Finished Jul 06 06:30:57 PM PDT 24
Peak memory 225652 kb
Host smart-8eeb9742-1173-4ed5-b745-1cc71b75642c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490127553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2490127553
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3403672328
Short name T359
Test name
Test status
Simulation time 1183662115 ps
CPU time 2.73 seconds
Started Jul 06 06:30:30 PM PDT 24
Finished Jul 06 06:30:33 PM PDT 24
Peak memory 218200 kb
Host smart-403c5d4a-48c5-4d90-af90-21d80b920488
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403672328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3403672328
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.3651698929
Short name T272
Test name
Test status
Simulation time 1376289138 ps
CPU time 9.86 seconds
Started Jul 06 06:30:29 PM PDT 24
Finished Jul 06 06:30:39 PM PDT 24
Peak memory 217744 kb
Host smart-406d2a39-0406-46e2-86b5-a4472b30faa5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651698929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.3651698929
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.2196475364
Short name T219
Test name
Test status
Simulation time 3941886219 ps
CPU time 43.49 seconds
Started Jul 06 06:30:29 PM PDT 24
Finished Jul 06 06:31:13 PM PDT 24
Peak memory 250972 kb
Host smart-2d85ddba-673d-41ca-aae1-b18e7dd1b267
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196475364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.2196475364
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3165989389
Short name T106
Test name
Test status
Simulation time 2293130699 ps
CPU time 15.51 seconds
Started Jul 06 06:30:30 PM PDT 24
Finished Jul 06 06:30:46 PM PDT 24
Peak memory 250348 kb
Host smart-f6c3e1fa-3253-46c0-a7cc-b0ae69c8d00b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165989389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.3165989389
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.2870291560
Short name T407
Test name
Test status
Simulation time 275754520 ps
CPU time 3.09 seconds
Started Jul 06 06:30:28 PM PDT 24
Finished Jul 06 06:30:32 PM PDT 24
Peak memory 218220 kb
Host smart-123a024d-d39e-4eb5-b514-b7db9ea670c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870291560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2870291560
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.2268601839
Short name T357
Test name
Test status
Simulation time 244551297 ps
CPU time 12.56 seconds
Started Jul 06 06:30:32 PM PDT 24
Finished Jul 06 06:30:46 PM PDT 24
Peak memory 226040 kb
Host smart-52806d5a-92bf-4a68-9a19-424310ebccd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268601839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2268601839
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.2180465415
Short name T612
Test name
Test status
Simulation time 845469451 ps
CPU time 8.97 seconds
Started Jul 06 06:30:31 PM PDT 24
Finished Jul 06 06:30:40 PM PDT 24
Peak memory 225996 kb
Host smart-f891e072-067e-45c4-96a6-bc541109080d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180465415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.2180465415
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3059202999
Short name T548
Test name
Test status
Simulation time 1247218193 ps
CPU time 8.46 seconds
Started Jul 06 06:30:32 PM PDT 24
Finished Jul 06 06:30:42 PM PDT 24
Peak memory 226040 kb
Host smart-12f5b143-f09b-4528-86fb-f99e7c27f571
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059202999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
3059202999
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2379630567
Short name T527
Test name
Test status
Simulation time 231351221 ps
CPU time 6.91 seconds
Started Jul 06 06:30:31 PM PDT 24
Finished Jul 06 06:30:38 PM PDT 24
Peak memory 225100 kb
Host smart-cc8a417a-28b6-45db-85d8-f687b27e1c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379630567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2379630567
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.950323875
Short name T767
Test name
Test status
Simulation time 775136702 ps
CPU time 6.32 seconds
Started Jul 06 06:30:31 PM PDT 24
Finished Jul 06 06:30:37 PM PDT 24
Peak memory 217700 kb
Host smart-0267b841-2f82-429e-a00c-78257e2262d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950323875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.950323875
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2484742239
Short name T634
Test name
Test status
Simulation time 307910359 ps
CPU time 27.95 seconds
Started Jul 06 06:30:27 PM PDT 24
Finished Jul 06 06:30:56 PM PDT 24
Peak memory 250952 kb
Host smart-1e64ac1a-5ad4-48c8-b4c8-824a14e2dfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484742239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2484742239
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.942918373
Short name T497
Test name
Test status
Simulation time 246407686 ps
CPU time 3.34 seconds
Started Jul 06 06:30:32 PM PDT 24
Finished Jul 06 06:30:36 PM PDT 24
Peak memory 222452 kb
Host smart-d4887ce6-3734-4d67-8d3f-8dc9fdbbe2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942918373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.942918373
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2035958127
Short name T165
Test name
Test status
Simulation time 28512870716 ps
CPU time 922 seconds
Started Jul 06 06:30:32 PM PDT 24
Finished Jul 06 06:45:55 PM PDT 24
Peak memory 316604 kb
Host smart-62ff9629-23c3-4c0e-b7ac-42261d6eeced
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035958127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2035958127
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2589174977
Short name T847
Test name
Test status
Simulation time 45478931 ps
CPU time 0.91 seconds
Started Jul 06 06:30:28 PM PDT 24
Finished Jul 06 06:30:29 PM PDT 24
Peak memory 211924 kb
Host smart-37bc1cb7-8ed3-44bd-bf64-386bb39f4b32
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589174977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.2589174977
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.3043205609
Short name T653
Test name
Test status
Simulation time 20990037 ps
CPU time 1.17 seconds
Started Jul 06 06:31:02 PM PDT 24
Finished Jul 06 06:31:04 PM PDT 24
Peak memory 208964 kb
Host smart-1789fe98-f1a7-4037-8ae8-11ff9c4d6e8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043205609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.3043205609
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.705696012
Short name T491
Test name
Test status
Simulation time 214376148 ps
CPU time 9.75 seconds
Started Jul 06 06:30:31 PM PDT 24
Finished Jul 06 06:30:42 PM PDT 24
Peak memory 218228 kb
Host smart-33ca4df2-823c-423e-8ed4-e01f5f3d0f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705696012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.705696012
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.1254534616
Short name T337
Test name
Test status
Simulation time 1040342211 ps
CPU time 2.08 seconds
Started Jul 06 06:30:35 PM PDT 24
Finished Jul 06 06:30:37 PM PDT 24
Peak memory 217100 kb
Host smart-b96d8541-1592-498d-a0a1-482cf69f2c42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254534616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.1254534616
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.1327436661
Short name T493
Test name
Test status
Simulation time 2087751699 ps
CPU time 33.75 seconds
Started Jul 06 06:30:41 PM PDT 24
Finished Jul 06 06:31:16 PM PDT 24
Peak memory 226052 kb
Host smart-8fed7ead-cca7-4219-adb3-e77c2dee3090
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327436661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.1327436661
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1028264117
Short name T363
Test name
Test status
Simulation time 167346065 ps
CPU time 2.98 seconds
Started Jul 06 06:30:35 PM PDT 24
Finished Jul 06 06:30:39 PM PDT 24
Peak memory 218256 kb
Host smart-9d0b47c3-a3d2-4461-ba80-198499c28818
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028264117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.1028264117
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.4076789673
Short name T484
Test name
Test status
Simulation time 298414495 ps
CPU time 2.41 seconds
Started Jul 06 06:30:32 PM PDT 24
Finished Jul 06 06:30:35 PM PDT 24
Peak memory 217764 kb
Host smart-6303b14c-e6e1-4c9d-9f86-48cb92570f55
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076789673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.4076789673
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.4206071604
Short name T304
Test name
Test status
Simulation time 2532690165 ps
CPU time 49.62 seconds
Started Jul 06 06:30:41 PM PDT 24
Finished Jul 06 06:31:32 PM PDT 24
Peak memory 267488 kb
Host smart-d01ceb3a-05c8-4b1e-831a-21549d6d26d0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206071604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.4206071604
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2108897266
Short name T818
Test name
Test status
Simulation time 2215109497 ps
CPU time 21.05 seconds
Started Jul 06 06:30:30 PM PDT 24
Finished Jul 06 06:30:51 PM PDT 24
Peak memory 251076 kb
Host smart-caea242a-a05d-493c-be53-4140ba4b5a29
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108897266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.2108897266
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.2785325289
Short name T691
Test name
Test status
Simulation time 114018031 ps
CPU time 2.79 seconds
Started Jul 06 06:30:35 PM PDT 24
Finished Jul 06 06:30:39 PM PDT 24
Peak memory 218476 kb
Host smart-9b4e47f0-ca63-4edd-abbb-1431abf6a089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785325289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.2785325289
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.2636030111
Short name T446
Test name
Test status
Simulation time 459326482 ps
CPU time 19.16 seconds
Started Jul 06 06:30:32 PM PDT 24
Finished Jul 06 06:30:53 PM PDT 24
Peak memory 225996 kb
Host smart-7028469b-ed92-45f5-a2b3-f648b16aaa5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636030111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.2636030111
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2861831163
Short name T819
Test name
Test status
Simulation time 1105532290 ps
CPU time 11 seconds
Started Jul 06 06:30:49 PM PDT 24
Finished Jul 06 06:31:00 PM PDT 24
Peak memory 226068 kb
Host smart-95c01826-185d-4291-8eb3-870ca05bb0e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861831163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.2861831163
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.436178780
Short name T316
Test name
Test status
Simulation time 1407496469 ps
CPU time 13.56 seconds
Started Jul 06 06:30:35 PM PDT 24
Finished Jul 06 06:30:49 PM PDT 24
Peak memory 218236 kb
Host smart-b9fe6b91-34bf-492e-b562-b16a9fe4f231
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436178780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.436178780
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.4231683924
Short name T823
Test name
Test status
Simulation time 1316048065 ps
CPU time 8.92 seconds
Started Jul 06 06:30:35 PM PDT 24
Finished Jul 06 06:30:44 PM PDT 24
Peak memory 224772 kb
Host smart-d983e6ea-92c7-41b8-9cc9-89ce29eede2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231683924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.4231683924
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.3708060447
Short name T812
Test name
Test status
Simulation time 309473447 ps
CPU time 5.64 seconds
Started Jul 06 06:30:35 PM PDT 24
Finished Jul 06 06:30:41 PM PDT 24
Peak memory 223440 kb
Host smart-352e9ee8-b603-44ac-b9d1-ac05919bd0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708060447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3708060447
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1719887333
Short name T657
Test name
Test status
Simulation time 221471542 ps
CPU time 17.19 seconds
Started Jul 06 06:30:32 PM PDT 24
Finished Jul 06 06:30:49 PM PDT 24
Peak memory 245336 kb
Host smart-430573bd-63a3-400f-bcda-3a0d491fbfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719887333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1719887333
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.3954310487
Short name T464
Test name
Test status
Simulation time 113679368 ps
CPU time 7.71 seconds
Started Jul 06 06:30:32 PM PDT 24
Finished Jul 06 06:30:41 PM PDT 24
Peak memory 251000 kb
Host smart-90c6da5e-0b9c-4aa2-a1ad-0dd7c3f4d282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954310487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3954310487
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.807766729
Short name T17
Test name
Test status
Simulation time 39229980502 ps
CPU time 196.83 seconds
Started Jul 06 06:30:33 PM PDT 24
Finished Jul 06 06:33:50 PM PDT 24
Peak memory 251044 kb
Host smart-4d97b836-95a6-43fb-93db-f3ad026e604f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807766729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.807766729
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3201614800
Short name T699
Test name
Test status
Simulation time 41031274 ps
CPU time 0.86 seconds
Started Jul 06 06:30:41 PM PDT 24
Finished Jul 06 06:30:44 PM PDT 24
Peak memory 211812 kb
Host smart-f3880d52-1596-4960-a959-b67dd94c4652
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201614800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3201614800
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.510563901
Short name T226
Test name
Test status
Simulation time 11710749 ps
CPU time 1.01 seconds
Started Jul 06 06:29:38 PM PDT 24
Finished Jul 06 06:29:40 PM PDT 24
Peak memory 209024 kb
Host smart-5d88720a-480e-49e5-9cdd-d983ad8b5233
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510563901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.510563901
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.272283529
Short name T827
Test name
Test status
Simulation time 10776762 ps
CPU time 0.82 seconds
Started Jul 06 06:29:34 PM PDT 24
Finished Jul 06 06:29:35 PM PDT 24
Peak memory 208752 kb
Host smart-77e34e7f-d0e9-44fc-9847-e947dc1ad0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272283529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.272283529
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.558957167
Short name T507
Test name
Test status
Simulation time 288625481 ps
CPU time 12.9 seconds
Started Jul 06 06:29:36 PM PDT 24
Finished Jul 06 06:29:49 PM PDT 24
Peak memory 226000 kb
Host smart-663a1cf6-8e54-4663-89af-81dfa0082441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558957167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.558957167
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.2320214872
Short name T163
Test name
Test status
Simulation time 472302144 ps
CPU time 5.67 seconds
Started Jul 06 06:29:31 PM PDT 24
Finished Jul 06 06:29:37 PM PDT 24
Peak memory 217716 kb
Host smart-ab818b88-a9e7-4061-b7dc-1ca156eacc89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320214872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.2320214872
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1249732820
Short name T390
Test name
Test status
Simulation time 14846648855 ps
CPU time 70.34 seconds
Started Jul 06 06:29:41 PM PDT 24
Finished Jul 06 06:30:51 PM PDT 24
Peak memory 218732 kb
Host smart-4c6f05f6-2bd1-4a87-832c-e20a366a6dc1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249732820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1249732820
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.292096539
Short name T850
Test name
Test status
Simulation time 431031448 ps
CPU time 10.85 seconds
Started Jul 06 06:29:42 PM PDT 24
Finished Jul 06 06:29:53 PM PDT 24
Peak memory 217692 kb
Host smart-b3a7eb74-b0f4-4a6b-a8dd-8a04149a0746
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292096539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.292096539
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.1693359561
Short name T175
Test name
Test status
Simulation time 69793196 ps
CPU time 2.91 seconds
Started Jul 06 06:29:52 PM PDT 24
Finished Jul 06 06:29:55 PM PDT 24
Peak memory 218204 kb
Host smart-72ccf3b3-4886-46ac-af2e-e0607d5e0cc5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693359561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.1693359561
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1084542205
Short name T25
Test name
Test status
Simulation time 1130926690 ps
CPU time 15.97 seconds
Started Jul 06 06:29:33 PM PDT 24
Finished Jul 06 06:29:49 PM PDT 24
Peak memory 217852 kb
Host smart-4cd51799-6e42-41b4-9637-37f6f91eb65f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084542205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.1084542205
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1877338062
Short name T425
Test name
Test status
Simulation time 458505312 ps
CPU time 4.08 seconds
Started Jul 06 06:29:38 PM PDT 24
Finished Jul 06 06:29:43 PM PDT 24
Peak memory 217712 kb
Host smart-e908ae5c-8411-40b2-ae54-708998623e0c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877338062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1877338062
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.4055171064
Short name T256
Test name
Test status
Simulation time 9492708914 ps
CPU time 53.7 seconds
Started Jul 06 06:29:54 PM PDT 24
Finished Jul 06 06:30:48 PM PDT 24
Peak memory 276012 kb
Host smart-e93d8ee6-0017-415a-b90d-c39ac6bb9273
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055171064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.4055171064
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2237348255
Short name T774
Test name
Test status
Simulation time 722097870 ps
CPU time 15.01 seconds
Started Jul 06 06:29:48 PM PDT 24
Finished Jul 06 06:30:03 PM PDT 24
Peak memory 250024 kb
Host smart-57a36e3e-5272-49b2-83ef-ee4c79a2250b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237348255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.2237348255
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2339223831
Short name T714
Test name
Test status
Simulation time 48837135 ps
CPU time 2.21 seconds
Started Jul 06 06:29:30 PM PDT 24
Finished Jul 06 06:29:32 PM PDT 24
Peak memory 222096 kb
Host smart-2f61ad31-d70f-4de3-add3-06eafc961053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339223831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2339223831
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.3735324961
Short name T70
Test name
Test status
Simulation time 663326636 ps
CPU time 9.86 seconds
Started Jul 06 06:29:31 PM PDT 24
Finished Jul 06 06:29:41 PM PDT 24
Peak memory 214468 kb
Host smart-5730ac6a-2059-4e4d-bc52-4a32d6afc0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735324961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3735324961
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2428136560
Short name T97
Test name
Test status
Simulation time 113424210 ps
CPU time 22.87 seconds
Started Jul 06 06:29:34 PM PDT 24
Finished Jul 06 06:29:57 PM PDT 24
Peak memory 284496 kb
Host smart-d27d2a99-3b92-48f8-a44b-9f9de68a48bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428136560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2428136560
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.1139468971
Short name T267
Test name
Test status
Simulation time 532739090 ps
CPU time 14.69 seconds
Started Jul 06 06:29:47 PM PDT 24
Finished Jul 06 06:30:02 PM PDT 24
Peak memory 225848 kb
Host smart-41ba9dd3-9455-45ee-a76e-eaae23086ce0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139468971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1139468971
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2756365172
Short name T102
Test name
Test status
Simulation time 790054533 ps
CPU time 16.22 seconds
Started Jul 06 06:29:37 PM PDT 24
Finished Jul 06 06:29:53 PM PDT 24
Peak memory 226000 kb
Host smart-f634e268-4354-40b5-87b7-f77725b065de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756365172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2756365172
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2524323128
Short name T60
Test name
Test status
Simulation time 1491676940 ps
CPU time 8.5 seconds
Started Jul 06 06:29:42 PM PDT 24
Finished Jul 06 06:29:50 PM PDT 24
Peak memory 226044 kb
Host smart-fd5b954e-a31c-497f-a34e-ce4136d95447
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524323128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
524323128
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.1192333765
Short name T667
Test name
Test status
Simulation time 144916948 ps
CPU time 2.72 seconds
Started Jul 06 06:29:33 PM PDT 24
Finished Jul 06 06:29:36 PM PDT 24
Peak memory 214768 kb
Host smart-d90e609b-344c-45f9-90d4-0be56aa71a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192333765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1192333765
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.1761862216
Short name T475
Test name
Test status
Simulation time 885457072 ps
CPU time 28.8 seconds
Started Jul 06 06:29:29 PM PDT 24
Finished Jul 06 06:29:58 PM PDT 24
Peak memory 250928 kb
Host smart-798889c5-c6d2-41b0-b307-d7602d967c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761862216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1761862216
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.2229295319
Short name T777
Test name
Test status
Simulation time 110913738 ps
CPU time 6.41 seconds
Started Jul 06 06:29:33 PM PDT 24
Finished Jul 06 06:29:40 PM PDT 24
Peak memory 250380 kb
Host smart-190dce31-5790-4da6-a14f-9015fae0ef29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229295319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2229295319
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.359276365
Short name T288
Test name
Test status
Simulation time 2604630945 ps
CPU time 53.11 seconds
Started Jul 06 06:29:42 PM PDT 24
Finished Jul 06 06:30:35 PM PDT 24
Peak memory 226120 kb
Host smart-4725aee5-9a1f-4df2-b321-04c38c0887aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359276365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.359276365
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.3027903330
Short name T788
Test name
Test status
Simulation time 7492217647 ps
CPU time 256.51 seconds
Started Jul 06 06:29:44 PM PDT 24
Finished Jul 06 06:34:01 PM PDT 24
Peak memory 272632 kb
Host smart-cc064dcf-1597-46a8-aae9-2d16efc384cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3027903330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.3027903330
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.4187681126
Short name T358
Test name
Test status
Simulation time 13010497 ps
CPU time 0.92 seconds
Started Jul 06 06:29:31 PM PDT 24
Finished Jul 06 06:29:32 PM PDT 24
Peak memory 211992 kb
Host smart-64f1fd50-cfbc-497d-a862-0eb9bea71a81
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187681126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.4187681126
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1266255351
Short name T85
Test name
Test status
Simulation time 122632147 ps
CPU time 1.33 seconds
Started Jul 06 06:30:36 PM PDT 24
Finished Jul 06 06:30:38 PM PDT 24
Peak memory 208976 kb
Host smart-c96c99bc-7e88-4534-85c9-e20ce7d57bba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266255351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1266255351
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.2043912329
Short name T704
Test name
Test status
Simulation time 596129838 ps
CPU time 16.42 seconds
Started Jul 06 06:30:43 PM PDT 24
Finished Jul 06 06:31:01 PM PDT 24
Peak memory 218196 kb
Host smart-7f825f24-ea82-4633-8487-33a3d22252ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043912329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2043912329
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.1387986041
Short name T369
Test name
Test status
Simulation time 7280630197 ps
CPU time 20.27 seconds
Started Jul 06 06:30:35 PM PDT 24
Finished Jul 06 06:30:55 PM PDT 24
Peak memory 217672 kb
Host smart-f041e47b-6305-4341-b6f1-2f9d8ac25a32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387986041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.1387986041
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.3739699773
Short name T492
Test name
Test status
Simulation time 76425214 ps
CPU time 2.17 seconds
Started Jul 06 06:30:44 PM PDT 24
Finished Jul 06 06:30:47 PM PDT 24
Peak memory 218188 kb
Host smart-cd074fb7-a2c3-40b3-8078-d20787db3f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739699773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.3739699773
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.3379103985
Short name T627
Test name
Test status
Simulation time 2009797517 ps
CPU time 19.45 seconds
Started Jul 06 06:30:39 PM PDT 24
Finished Jul 06 06:30:59 PM PDT 24
Peak memory 218864 kb
Host smart-3788b9e8-283b-4676-8558-1a3b93aeaed0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379103985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.3379103985
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.307097837
Short name T660
Test name
Test status
Simulation time 608258447 ps
CPU time 8.18 seconds
Started Jul 06 06:30:37 PM PDT 24
Finished Jul 06 06:30:45 PM PDT 24
Peak memory 226036 kb
Host smart-121d5ce5-24fb-47bd-abd7-838fbcd40015
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307097837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_di
gest.307097837
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.68737568
Short name T285
Test name
Test status
Simulation time 747440914 ps
CPU time 22.28 seconds
Started Jul 06 06:30:37 PM PDT 24
Finished Jul 06 06:31:00 PM PDT 24
Peak memory 218252 kb
Host smart-3dabb9a9-1ced-4d4b-8ad7-553c332c32bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68737568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.68737568
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.2466407432
Short name T286
Test name
Test status
Simulation time 296116006 ps
CPU time 4.32 seconds
Started Jul 06 06:30:41 PM PDT 24
Finished Jul 06 06:30:47 PM PDT 24
Peak memory 217740 kb
Host smart-018a4a42-6bcf-484f-88f2-f9f033fec466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466407432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.2466407432
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.1305108867
Short name T82
Test name
Test status
Simulation time 286914118 ps
CPU time 24.75 seconds
Started Jul 06 06:30:33 PM PDT 24
Finished Jul 06 06:30:58 PM PDT 24
Peak memory 250960 kb
Host smart-bfe9c1f8-d7de-4ac9-9ba7-d3cc2e2677a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305108867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1305108867
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.68180629
Short name T405
Test name
Test status
Simulation time 118936082 ps
CPU time 6.36 seconds
Started Jul 06 06:30:35 PM PDT 24
Finished Jul 06 06:30:42 PM PDT 24
Peak memory 250924 kb
Host smart-63c1801b-b29d-464c-aece-4b11b1ed44a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68180629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.68180629
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3193708706
Short name T688
Test name
Test status
Simulation time 12942434466 ps
CPU time 222.34 seconds
Started Jul 06 06:30:38 PM PDT 24
Finished Jul 06 06:34:20 PM PDT 24
Peak memory 226828 kb
Host smart-d3a4ad27-4481-4eca-9950-e42ff467a357
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193708706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3193708706
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1937674090
Short name T202
Test name
Test status
Simulation time 12161087 ps
CPU time 1.01 seconds
Started Jul 06 06:30:32 PM PDT 24
Finished Jul 06 06:30:34 PM PDT 24
Peak memory 211832 kb
Host smart-8705bf34-634f-49d7-8d84-7e17a4c9dfe5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937674090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1937674090
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.3328705281
Short name T713
Test name
Test status
Simulation time 37163885 ps
CPU time 0.87 seconds
Started Jul 06 06:31:04 PM PDT 24
Finished Jul 06 06:31:06 PM PDT 24
Peak memory 208932 kb
Host smart-ebaf1de6-895f-4f8b-b86e-1a88faf75bfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328705281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.3328705281
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.508229898
Short name T29
Test name
Test status
Simulation time 1766090932 ps
CPU time 6.31 seconds
Started Jul 06 06:30:37 PM PDT 24
Finished Jul 06 06:30:44 PM PDT 24
Peak memory 217736 kb
Host smart-78c495d5-a9f4-42d9-87b6-76abcf467bba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508229898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.508229898
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.849863220
Short name T608
Test name
Test status
Simulation time 41374252 ps
CPU time 1.44 seconds
Started Jul 06 06:30:35 PM PDT 24
Finished Jul 06 06:30:37 PM PDT 24
Peak memory 218248 kb
Host smart-d701e3cb-af87-4d7e-b771-ce9e2bab2b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849863220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.849863220
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.3801625763
Short name T686
Test name
Test status
Simulation time 292148365 ps
CPU time 11.15 seconds
Started Jul 06 06:30:40 PM PDT 24
Finished Jul 06 06:30:53 PM PDT 24
Peak memory 218884 kb
Host smart-d47f87c5-f20e-441e-9449-1a9d264d9592
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801625763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3801625763
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.3641192683
Short name T2
Test name
Test status
Simulation time 391460873 ps
CPU time 10.19 seconds
Started Jul 06 06:30:40 PM PDT 24
Finished Jul 06 06:30:50 PM PDT 24
Peak memory 225980 kb
Host smart-115aecc2-9fa1-43c1-a606-cf9916f10fe0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641192683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.3641192683
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3465887754
Short name T845
Test name
Test status
Simulation time 1256843275 ps
CPU time 11.69 seconds
Started Jul 06 06:30:38 PM PDT 24
Finished Jul 06 06:30:50 PM PDT 24
Peak memory 218240 kb
Host smart-4d1d3665-bf93-4a0c-bda5-1fb3934470e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465887754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3465887754
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.862188122
Short name T343
Test name
Test status
Simulation time 1648413559 ps
CPU time 13.94 seconds
Started Jul 06 06:30:40 PM PDT 24
Finished Jul 06 06:30:54 PM PDT 24
Peak memory 218312 kb
Host smart-b396b357-2c51-48a1-a3f2-fd671bc7c75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862188122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.862188122
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.3282337336
Short name T752
Test name
Test status
Simulation time 501951950 ps
CPU time 7.57 seconds
Started Jul 06 06:30:36 PM PDT 24
Finished Jul 06 06:30:44 PM PDT 24
Peak memory 217760 kb
Host smart-3a7bebc3-5ed9-4156-aded-d9d206e79c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282337336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3282337336
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.3170795939
Short name T693
Test name
Test status
Simulation time 254908260 ps
CPU time 33.8 seconds
Started Jul 06 06:30:37 PM PDT 24
Finished Jul 06 06:31:11 PM PDT 24
Peak memory 250988 kb
Host smart-33b7d82c-7919-41fd-9a18-4fcc865e48ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170795939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3170795939
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.1916927624
Short name T751
Test name
Test status
Simulation time 171725799 ps
CPU time 6.5 seconds
Started Jul 06 06:30:43 PM PDT 24
Finished Jul 06 06:30:50 PM PDT 24
Peak memory 250400 kb
Host smart-dc1f469e-642d-4141-817f-86930cb53d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916927624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1916927624
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.2647919893
Short name T400
Test name
Test status
Simulation time 35014763582 ps
CPU time 231.39 seconds
Started Jul 06 06:30:36 PM PDT 24
Finished Jul 06 06:34:28 PM PDT 24
Peak memory 278196 kb
Host smart-aee8684d-c5d1-4096-a8d1-eae5c1869671
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647919893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.2647919893
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.359259388
Short name T619
Test name
Test status
Simulation time 14294605 ps
CPU time 0.93 seconds
Started Jul 06 06:30:39 PM PDT 24
Finished Jul 06 06:30:40 PM PDT 24
Peak memory 212876 kb
Host smart-7f239289-f6d5-44a1-b793-8b77a16f83e5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359259388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.359259388
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.1482833084
Short name T506
Test name
Test status
Simulation time 18679008 ps
CPU time 1.11 seconds
Started Jul 06 06:30:40 PM PDT 24
Finished Jul 06 06:30:43 PM PDT 24
Peak memory 209088 kb
Host smart-1ee363a4-8347-4b94-b2a1-c8b93baed6be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482833084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1482833084
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.629082622
Short name T795
Test name
Test status
Simulation time 412063815 ps
CPU time 9.82 seconds
Started Jul 06 06:30:40 PM PDT 24
Finished Jul 06 06:30:52 PM PDT 24
Peak memory 218240 kb
Host smart-a58eb94c-7eec-4333-97cc-cf22c48c9200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629082622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.629082622
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.4033288763
Short name T32
Test name
Test status
Simulation time 244286488 ps
CPU time 2.01 seconds
Started Jul 06 06:30:40 PM PDT 24
Finished Jul 06 06:30:44 PM PDT 24
Peak memory 217080 kb
Host smart-15f20244-4de3-4bea-94de-5953418389b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033288763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.4033288763
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.1879032377
Short name T59
Test name
Test status
Simulation time 174038753 ps
CPU time 2.49 seconds
Started Jul 06 06:30:42 PM PDT 24
Finished Jul 06 06:30:46 PM PDT 24
Peak memory 218156 kb
Host smart-4a33bbac-d4f3-4b83-ac85-a532631e7c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879032377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1879032377
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.2918966804
Short name T23
Test name
Test status
Simulation time 402590891 ps
CPU time 7.38 seconds
Started Jul 06 06:30:44 PM PDT 24
Finished Jul 06 06:30:53 PM PDT 24
Peak memory 218264 kb
Host smart-4bf962f7-683d-4018-a307-3b8c7513f28a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918966804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2918966804
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.2940802298
Short name T261
Test name
Test status
Simulation time 1840263146 ps
CPU time 12.27 seconds
Started Jul 06 06:30:42 PM PDT 24
Finished Jul 06 06:30:55 PM PDT 24
Peak memory 226032 kb
Host smart-7e84f71a-da3f-4df6-a595-10de6defb388
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940802298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.2940802298
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.514298169
Short name T632
Test name
Test status
Simulation time 375623108 ps
CPU time 10.47 seconds
Started Jul 06 06:30:39 PM PDT 24
Finished Jul 06 06:30:50 PM PDT 24
Peak memory 218288 kb
Host smart-76cec654-9081-4e9b-af1d-6e4d5a21b46c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514298169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.514298169
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.1225221945
Short name T381
Test name
Test status
Simulation time 483491991 ps
CPU time 11.02 seconds
Started Jul 06 06:30:47 PM PDT 24
Finished Jul 06 06:30:58 PM PDT 24
Peak memory 226028 kb
Host smart-9d9843c8-2baf-49f4-982f-15b0bc42f90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225221945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1225221945
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.3796866565
Short name T389
Test name
Test status
Simulation time 393702911 ps
CPU time 1.85 seconds
Started Jul 06 06:30:43 PM PDT 24
Finished Jul 06 06:30:46 PM PDT 24
Peak memory 214036 kb
Host smart-0ee5f538-cd18-4eb5-a8e8-bff94b82a4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796866565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3796866565
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.785790650
Short name T294
Test name
Test status
Simulation time 436651462 ps
CPU time 30.37 seconds
Started Jul 06 06:30:35 PM PDT 24
Finished Jul 06 06:31:06 PM PDT 24
Peak memory 251000 kb
Host smart-5f678ed3-55c9-49e0-9ed7-f258993e4fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785790650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.785790650
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.3055202847
Short name T230
Test name
Test status
Simulation time 83985895 ps
CPU time 6.06 seconds
Started Jul 06 06:30:39 PM PDT 24
Finished Jul 06 06:30:46 PM PDT 24
Peak memory 250496 kb
Host smart-b04606e7-208c-4eee-a0b6-0cf1eb448049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055202847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3055202847
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1473915397
Short name T470
Test name
Test status
Simulation time 5554465724 ps
CPU time 57.82 seconds
Started Jul 06 06:30:40 PM PDT 24
Finished Jul 06 06:31:39 PM PDT 24
Peak memory 254116 kb
Host smart-ea1c7188-839e-4a2a-b4b1-bc256d5c12f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473915397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.1473915397
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2871976088
Short name T245
Test name
Test status
Simulation time 22602699 ps
CPU time 0.99 seconds
Started Jul 06 06:30:43 PM PDT 24
Finished Jul 06 06:30:45 PM PDT 24
Peak memory 211920 kb
Host smart-b808daf5-4724-4f26-9583-0bc0c4278e6e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871976088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2871976088
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1151336977
Short name T233
Test name
Test status
Simulation time 83840034 ps
CPU time 0.92 seconds
Started Jul 06 06:30:42 PM PDT 24
Finished Jul 06 06:30:44 PM PDT 24
Peak memory 208984 kb
Host smart-ccf49220-e3ea-449d-a9c1-eb28eef273a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151336977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1151336977
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3656375053
Short name T715
Test name
Test status
Simulation time 1043019158 ps
CPU time 12.37 seconds
Started Jul 06 06:30:43 PM PDT 24
Finished Jul 06 06:30:56 PM PDT 24
Peak memory 218236 kb
Host smart-f50f1806-6ebe-4862-acd3-0f4603e61cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656375053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3656375053
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.3281818026
Short name T595
Test name
Test status
Simulation time 1085488237 ps
CPU time 6.82 seconds
Started Jul 06 06:30:42 PM PDT 24
Finished Jul 06 06:30:50 PM PDT 24
Peak memory 217240 kb
Host smart-78251f81-e5e8-46e2-8fca-958ba0a09513
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281818026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.3281818026
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.642798219
Short name T593
Test name
Test status
Simulation time 178095656 ps
CPU time 2.12 seconds
Started Jul 06 06:30:42 PM PDT 24
Finished Jul 06 06:30:45 PM PDT 24
Peak memory 218196 kb
Host smart-fd6a37a7-52f6-4f3a-aaea-8955b3cb5b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642798219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.642798219
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.577206974
Short name T297
Test name
Test status
Simulation time 748102560 ps
CPU time 10.09 seconds
Started Jul 06 06:30:40 PM PDT 24
Finished Jul 06 06:30:51 PM PDT 24
Peak memory 225996 kb
Host smart-690992c5-3886-4ca4-92a2-d47096637993
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577206974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di
gest.577206974
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3455881813
Short name T681
Test name
Test status
Simulation time 1051867647 ps
CPU time 12.18 seconds
Started Jul 06 06:30:43 PM PDT 24
Finished Jul 06 06:30:57 PM PDT 24
Peak memory 225960 kb
Host smart-8b654207-0e09-4268-bd1a-7137baa8b25f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455881813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
3455881813
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.3245262696
Short name T310
Test name
Test status
Simulation time 700473888 ps
CPU time 12.69 seconds
Started Jul 06 06:30:41 PM PDT 24
Finished Jul 06 06:30:55 PM PDT 24
Peak memory 226036 kb
Host smart-d4de9ae5-d3f8-4292-b7ed-06b92031b3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245262696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3245262696
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.2672496765
Short name T414
Test name
Test status
Simulation time 234343826 ps
CPU time 2.7 seconds
Started Jul 06 06:30:44 PM PDT 24
Finished Jul 06 06:30:48 PM PDT 24
Peak memory 214600 kb
Host smart-e511cbdb-7a5a-4b92-abda-4ca28f6d31dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672496765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2672496765
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.1895620625
Short name T90
Test name
Test status
Simulation time 2686999582 ps
CPU time 29.92 seconds
Started Jul 06 06:30:42 PM PDT 24
Finished Jul 06 06:31:13 PM PDT 24
Peak memory 251036 kb
Host smart-3f621599-76f6-480a-b169-86037870d08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895620625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1895620625
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3888761079
Short name T275
Test name
Test status
Simulation time 136955409 ps
CPU time 6.49 seconds
Started Jul 06 06:30:41 PM PDT 24
Finished Jul 06 06:30:49 PM PDT 24
Peak memory 250948 kb
Host smart-e93c4a8b-fe4b-4515-a941-ec18102f24b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888761079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3888761079
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.130054554
Short name T75
Test name
Test status
Simulation time 3771828335 ps
CPU time 57.72 seconds
Started Jul 06 06:30:41 PM PDT 24
Finished Jul 06 06:31:40 PM PDT 24
Peak memory 247772 kb
Host smart-258c281e-0d2d-4418-8b14-4eda88ae4797
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130054554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.130054554
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2703984721
Short name T553
Test name
Test status
Simulation time 13992358 ps
CPU time 1.15 seconds
Started Jul 06 06:30:42 PM PDT 24
Finished Jul 06 06:30:45 PM PDT 24
Peak memory 211816 kb
Host smart-68765b52-07df-4ec1-9433-69c5d4b45c3b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703984721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.2703984721
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.3566600263
Short name T362
Test name
Test status
Simulation time 62094317 ps
CPU time 1.07 seconds
Started Jul 06 06:30:46 PM PDT 24
Finished Jul 06 06:30:47 PM PDT 24
Peak memory 209132 kb
Host smart-8dc9c936-bead-4fc7-9d62-c8b7054a1101
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566600263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3566600263
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2854351889
Short name T399
Test name
Test status
Simulation time 1746259257 ps
CPU time 14.92 seconds
Started Jul 06 06:30:46 PM PDT 24
Finished Jul 06 06:31:01 PM PDT 24
Peak memory 218216 kb
Host smart-a80ab911-a87a-487f-a5b4-6c3cd5a90272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854351889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2854351889
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.252637298
Short name T176
Test name
Test status
Simulation time 1673296003 ps
CPU time 10.48 seconds
Started Jul 06 06:30:44 PM PDT 24
Finished Jul 06 06:30:56 PM PDT 24
Peak memory 217136 kb
Host smart-4c6843a1-3ccb-469f-82d9-515a9243dd8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252637298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.252637298
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1276207544
Short name T773
Test name
Test status
Simulation time 248745012 ps
CPU time 3.39 seconds
Started Jul 06 06:30:44 PM PDT 24
Finished Jul 06 06:30:48 PM PDT 24
Peak memory 222488 kb
Host smart-1a4af83e-55ad-4bac-9f1f-510fc4ab4ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276207544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1276207544
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.1904470096
Short name T384
Test name
Test status
Simulation time 2463449955 ps
CPU time 14.69 seconds
Started Jul 06 06:30:43 PM PDT 24
Finished Jul 06 06:30:59 PM PDT 24
Peak memory 226116 kb
Host smart-63078e47-4311-41c7-af8b-dac30542f522
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904470096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.1904470096
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1947220215
Short name T526
Test name
Test status
Simulation time 515728871 ps
CPU time 12.87 seconds
Started Jul 06 06:30:43 PM PDT 24
Finished Jul 06 06:30:57 PM PDT 24
Peak memory 225972 kb
Host smart-a91534ef-3843-4f0d-b337-7ace2d11077c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947220215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1947220215
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2608279593
Short name T601
Test name
Test status
Simulation time 333707378 ps
CPU time 13.26 seconds
Started Jul 06 06:30:42 PM PDT 24
Finished Jul 06 06:30:57 PM PDT 24
Peak memory 218276 kb
Host smart-bb18ceca-9233-4649-a2da-9e45042dac82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608279593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
2608279593
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.572408978
Short name T379
Test name
Test status
Simulation time 1180815692 ps
CPU time 9.93 seconds
Started Jul 06 06:30:44 PM PDT 24
Finished Jul 06 06:30:55 PM PDT 24
Peak memory 225224 kb
Host smart-31dd9104-2aee-4db1-8e59-49e6aa169d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572408978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.572408978
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2393920771
Short name T412
Test name
Test status
Simulation time 93308637 ps
CPU time 3.35 seconds
Started Jul 06 06:30:42 PM PDT 24
Finished Jul 06 06:30:47 PM PDT 24
Peak memory 217784 kb
Host smart-8a1162c2-d38a-4e10-bb4d-775397593aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393920771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2393920771
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.3607212280
Short name T654
Test name
Test status
Simulation time 1410639001 ps
CPU time 33.66 seconds
Started Jul 06 06:30:43 PM PDT 24
Finished Jul 06 06:31:18 PM PDT 24
Peak memory 250992 kb
Host smart-c7744376-5d1d-408d-aa0b-e58198560538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607212280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.3607212280
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.1340859129
Short name T529
Test name
Test status
Simulation time 63665345 ps
CPU time 6.27 seconds
Started Jul 06 06:30:40 PM PDT 24
Finished Jul 06 06:30:48 PM PDT 24
Peak memory 242796 kb
Host smart-916a949a-f155-4584-8b5f-5344ef592bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340859129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1340859129
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3487475146
Short name T804
Test name
Test status
Simulation time 2630497630 ps
CPU time 58.23 seconds
Started Jul 06 06:30:44 PM PDT 24
Finished Jul 06 06:31:43 PM PDT 24
Peak memory 269876 kb
Host smart-d0432aee-0f68-4510-bfce-44fc788e1450
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487475146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3487475146
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1912724096
Short name T225
Test name
Test status
Simulation time 105575747 ps
CPU time 0.87 seconds
Started Jul 06 06:30:40 PM PDT 24
Finished Jul 06 06:30:42 PM PDT 24
Peak memory 212920 kb
Host smart-f9bfb8a8-3e8c-4673-846c-070db749cd38
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912724096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.1912724096
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.4211447480
Short name T483
Test name
Test status
Simulation time 26162306 ps
CPU time 0.83 seconds
Started Jul 06 06:30:49 PM PDT 24
Finished Jul 06 06:30:51 PM PDT 24
Peak memory 208732 kb
Host smart-a97ba102-2b75-4bc3-ad76-15f05f87bf69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211447480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.4211447480
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.1892506262
Short name T44
Test name
Test status
Simulation time 439354815 ps
CPU time 13.48 seconds
Started Jul 06 06:30:46 PM PDT 24
Finished Jul 06 06:31:00 PM PDT 24
Peak memory 226048 kb
Host smart-1ba69df6-0985-4c66-9b1e-a32e00d3f7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892506262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1892506262
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.1265586052
Short name T811
Test name
Test status
Simulation time 1161731763 ps
CPU time 3.29 seconds
Started Jul 06 06:30:47 PM PDT 24
Finished Jul 06 06:30:51 PM PDT 24
Peak memory 217056 kb
Host smart-04bc49b0-ca68-4080-80ab-f638775dde76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265586052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.1265586052
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.3214962996
Short name T12
Test name
Test status
Simulation time 23062587 ps
CPU time 1.56 seconds
Started Jul 06 06:30:44 PM PDT 24
Finished Jul 06 06:30:47 PM PDT 24
Peak memory 218172 kb
Host smart-8a956283-24e7-4cce-bb2c-ad22e5fd6ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214962996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.3214962996
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.534201879
Short name T322
Test name
Test status
Simulation time 333147615 ps
CPU time 14.72 seconds
Started Jul 06 06:30:47 PM PDT 24
Finished Jul 06 06:31:02 PM PDT 24
Peak memory 225988 kb
Host smart-cbfd96ff-600b-48bf-a228-5dba38115486
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534201879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.534201879
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1678289864
Short name T169
Test name
Test status
Simulation time 306055566 ps
CPU time 12.02 seconds
Started Jul 06 06:30:49 PM PDT 24
Finished Jul 06 06:31:02 PM PDT 24
Peak memory 226060 kb
Host smart-a807c829-4ab4-4794-a4a3-916e11e13c2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678289864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1678289864
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.359449457
Short name T246
Test name
Test status
Simulation time 308129292 ps
CPU time 9.2 seconds
Started Jul 06 06:30:51 PM PDT 24
Finished Jul 06 06:31:00 PM PDT 24
Peak memory 218240 kb
Host smart-100f4df2-9aa5-4818-908b-7a524e1859aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359449457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.359449457
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.2167327280
Short name T209
Test name
Test status
Simulation time 967071295 ps
CPU time 6.34 seconds
Started Jul 06 06:30:44 PM PDT 24
Finished Jul 06 06:30:52 PM PDT 24
Peak memory 218192 kb
Host smart-59b0d534-33ad-41ff-a863-05049b3010ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167327280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2167327280
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.797301451
Short name T241
Test name
Test status
Simulation time 108308790 ps
CPU time 1.64 seconds
Started Jul 06 06:30:49 PM PDT 24
Finished Jul 06 06:30:51 PM PDT 24
Peak memory 213976 kb
Host smart-1dfd54ba-8408-4124-9bee-08c49fb10d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797301451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.797301451
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.2958298763
Short name T677
Test name
Test status
Simulation time 323059401 ps
CPU time 34.49 seconds
Started Jul 06 06:30:45 PM PDT 24
Finished Jul 06 06:31:20 PM PDT 24
Peak memory 250960 kb
Host smart-9062b554-dc4f-4f01-80d9-2815a9b54496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958298763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2958298763
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.2626979036
Short name T328
Test name
Test status
Simulation time 70259343 ps
CPU time 3.05 seconds
Started Jul 06 06:30:46 PM PDT 24
Finished Jul 06 06:30:50 PM PDT 24
Peak memory 226412 kb
Host smart-87176601-25b9-423c-bcb4-2cf4c8b173b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626979036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.2626979036
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.3383470890
Short name T387
Test name
Test status
Simulation time 7757404100 ps
CPU time 216.85 seconds
Started Jul 06 06:30:50 PM PDT 24
Finished Jul 06 06:34:27 PM PDT 24
Peak memory 283828 kb
Host smart-b48ffccb-95b9-4860-88ee-431779661d4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383470890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.3383470890
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.4223023822
Short name T144
Test name
Test status
Simulation time 137051409065 ps
CPU time 631.43 seconds
Started Jul 06 06:30:50 PM PDT 24
Finished Jul 06 06:41:22 PM PDT 24
Peak memory 292784 kb
Host smart-26560b4b-e7d5-4558-8f37-85c9566b3fa6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4223023822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.4223023822
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.302721754
Short name T315
Test name
Test status
Simulation time 12921905 ps
CPU time 0.91 seconds
Started Jul 06 06:30:47 PM PDT 24
Finished Jul 06 06:30:48 PM PDT 24
Peak memory 211840 kb
Host smart-cc5399da-598c-4513-99a9-aab9c8f87fdd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302721754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ct
rl_volatile_unlock_smoke.302721754
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.3072532440
Short name T816
Test name
Test status
Simulation time 21364099 ps
CPU time 1 seconds
Started Jul 06 06:31:03 PM PDT 24
Finished Jul 06 06:31:05 PM PDT 24
Peak memory 208996 kb
Host smart-a11215bf-4128-4e48-8dc2-e962208cad06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072532440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.3072532440
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.2137545369
Short name T16
Test name
Test status
Simulation time 1446723935 ps
CPU time 12.72 seconds
Started Jul 06 06:30:49 PM PDT 24
Finished Jul 06 06:31:02 PM PDT 24
Peak memory 218236 kb
Host smart-f6fb97a4-5567-4a53-bc16-c41b4cc2664e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137545369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.2137545369
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.2814823667
Short name T539
Test name
Test status
Simulation time 390010659 ps
CPU time 11.09 seconds
Started Jul 06 06:30:49 PM PDT 24
Finished Jul 06 06:31:00 PM PDT 24
Peak memory 217348 kb
Host smart-49f8b501-6cf3-456f-a15e-8ad32efb622f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814823667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.2814823667
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.1754021929
Short name T300
Test name
Test status
Simulation time 98748053 ps
CPU time 4.26 seconds
Started Jul 06 06:30:48 PM PDT 24
Finished Jul 06 06:30:53 PM PDT 24
Peak memory 218172 kb
Host smart-d40d97d3-db5e-454d-811a-0722bff4215c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754021929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1754021929
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.148542441
Short name T782
Test name
Test status
Simulation time 360273471 ps
CPU time 15.66 seconds
Started Jul 06 06:30:48 PM PDT 24
Finished Jul 06 06:31:04 PM PDT 24
Peak memory 225984 kb
Host smart-952f4384-fa97-4e97-b213-0e653f213fe9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148542441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.148542441
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.1917594181
Short name T799
Test name
Test status
Simulation time 2393231945 ps
CPU time 13.48 seconds
Started Jul 06 06:30:51 PM PDT 24
Finished Jul 06 06:31:04 PM PDT 24
Peak memory 226108 kb
Host smart-d86570b6-6604-46fe-989a-c2c7f6dc501a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917594181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.1917594181
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.2789328475
Short name T851
Test name
Test status
Simulation time 1137337275 ps
CPU time 5.87 seconds
Started Jul 06 06:30:47 PM PDT 24
Finished Jul 06 06:30:54 PM PDT 24
Peak memory 218276 kb
Host smart-4e1245a7-5553-4d60-8391-46fc4edd7195
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789328475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
2789328475
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3390459844
Short name T48
Test name
Test status
Simulation time 1588967257 ps
CPU time 10.64 seconds
Started Jul 06 06:30:49 PM PDT 24
Finished Jul 06 06:31:00 PM PDT 24
Peak memory 225996 kb
Host smart-634796d0-d146-4fbc-b563-fdd2eb62caf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390459844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3390459844
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.1240518886
Short name T58
Test name
Test status
Simulation time 83417636 ps
CPU time 2.87 seconds
Started Jul 06 06:30:49 PM PDT 24
Finished Jul 06 06:30:53 PM PDT 24
Peak memory 214668 kb
Host smart-96dd1d68-81c4-47fe-9863-4d80c042ad53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240518886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1240518886
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3953632898
Short name T462
Test name
Test status
Simulation time 261825391 ps
CPU time 32.01 seconds
Started Jul 06 06:30:50 PM PDT 24
Finished Jul 06 06:31:22 PM PDT 24
Peak memory 250988 kb
Host smart-62800ba8-fc95-4b91-b1fd-6efb7de17bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953632898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3953632898
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.1334698906
Short name T210
Test name
Test status
Simulation time 189645793 ps
CPU time 3.49 seconds
Started Jul 06 06:30:49 PM PDT 24
Finished Jul 06 06:30:53 PM PDT 24
Peak memory 226460 kb
Host smart-59f8b1c1-7bf6-49cd-aff9-a8fc9b172ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334698906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1334698906
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.13648848
Short name T563
Test name
Test status
Simulation time 6790958089 ps
CPU time 96.09 seconds
Started Jul 06 06:30:51 PM PDT 24
Finished Jul 06 06:32:27 PM PDT 24
Peak memory 272480 kb
Host smart-6d7f4de2-c702-4efb-a155-5880deedc031
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13648848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.lc_ctrl_stress_all.13648848
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.1162566371
Short name T260
Test name
Test status
Simulation time 91519904 ps
CPU time 1.24 seconds
Started Jul 06 06:31:01 PM PDT 24
Finished Jul 06 06:31:02 PM PDT 24
Peak memory 209036 kb
Host smart-3e06a75e-441b-40f0-9e22-83cb9bd26861
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162566371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.1162566371
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.3553655807
Short name T579
Test name
Test status
Simulation time 1044132506 ps
CPU time 14.56 seconds
Started Jul 06 06:30:54 PM PDT 24
Finished Jul 06 06:31:09 PM PDT 24
Peak memory 218220 kb
Host smart-1053dca0-9cde-42f1-9114-ca19b1ef76ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553655807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.3553655807
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.2258279650
Short name T488
Test name
Test status
Simulation time 159589863 ps
CPU time 1.37 seconds
Started Jul 06 06:30:54 PM PDT 24
Finished Jul 06 06:30:56 PM PDT 24
Peak memory 217184 kb
Host smart-4f59baa7-9d82-4734-a213-f14f85c23e16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258279650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.2258279650
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.2760295602
Short name T307
Test name
Test status
Simulation time 686986204 ps
CPU time 2.83 seconds
Started Jul 06 06:30:53 PM PDT 24
Finished Jul 06 06:30:56 PM PDT 24
Peak memory 218124 kb
Host smart-4a30eb3b-61fa-4afa-b357-729ee5babe1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760295602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.2760295602
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.2182494452
Short name T41
Test name
Test status
Simulation time 2601426524 ps
CPU time 12.46 seconds
Started Jul 06 06:30:54 PM PDT 24
Finished Jul 06 06:31:07 PM PDT 24
Peak memory 219200 kb
Host smart-56006cd4-88a3-401a-a14a-3af4aa9bfeff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182494452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2182494452
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2275484027
Short name T463
Test name
Test status
Simulation time 342143621 ps
CPU time 13.69 seconds
Started Jul 06 06:30:54 PM PDT 24
Finished Jul 06 06:31:08 PM PDT 24
Peak memory 226052 kb
Host smart-a941085a-4df6-4412-8166-1a6ab098ecd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275484027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2275484027
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2108314281
Short name T842
Test name
Test status
Simulation time 769282009 ps
CPU time 6.12 seconds
Started Jul 06 06:31:00 PM PDT 24
Finished Jul 06 06:31:07 PM PDT 24
Peak memory 218244 kb
Host smart-41971266-8ce1-43cf-9613-8b2f0fcb8ba5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108314281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2108314281
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.3428180631
Short name T793
Test name
Test status
Simulation time 3373955658 ps
CPU time 7.85 seconds
Started Jul 06 06:30:54 PM PDT 24
Finished Jul 06 06:31:02 PM PDT 24
Peak memory 226104 kb
Host smart-126c05b0-64d5-4319-81e8-38ed02d19f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428180631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3428180631
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.153335882
Short name T429
Test name
Test status
Simulation time 63050187 ps
CPU time 1.37 seconds
Started Jul 06 06:30:55 PM PDT 24
Finished Jul 06 06:30:56 PM PDT 24
Peak memory 217736 kb
Host smart-e461083a-7064-4353-a288-9ee5a81fec57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153335882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.153335882
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.1336304854
Short name T504
Test name
Test status
Simulation time 705360307 ps
CPU time 33.65 seconds
Started Jul 06 06:30:53 PM PDT 24
Finished Jul 06 06:31:27 PM PDT 24
Peak memory 246932 kb
Host smart-9df30d46-d135-4e88-947c-331e31c27cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336304854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1336304854
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3821588790
Short name T514
Test name
Test status
Simulation time 274246892 ps
CPU time 6.52 seconds
Started Jul 06 06:30:54 PM PDT 24
Finished Jul 06 06:31:01 PM PDT 24
Peak memory 250428 kb
Host smart-73173954-d1fd-4538-ab86-99197554f614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821588790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3821588790
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.4024001705
Short name T692
Test name
Test status
Simulation time 16687939764 ps
CPU time 530.48 seconds
Started Jul 06 06:30:56 PM PDT 24
Finished Jul 06 06:39:47 PM PDT 24
Peak memory 283792 kb
Host smart-575b7608-0714-49a9-aec1-98ca9faf7174
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024001705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.4024001705
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.333140292
Short name T148
Test name
Test status
Simulation time 21550263271 ps
CPU time 268.28 seconds
Started Jul 06 06:31:02 PM PDT 24
Finished Jul 06 06:35:31 PM PDT 24
Peak memory 283036 kb
Host smart-60e68376-e312-42e8-973c-14e2e6ec3810
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=333140292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.333140292
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1532226249
Short name T171
Test name
Test status
Simulation time 13887611 ps
CPU time 1.1 seconds
Started Jul 06 06:30:52 PM PDT 24
Finished Jul 06 06:30:53 PM PDT 24
Peak memory 211932 kb
Host smart-3eadbc7d-c5df-45b7-ad58-293905271eed
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532226249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.1532226249
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.4074780313
Short name T213
Test name
Test status
Simulation time 23570285 ps
CPU time 1.11 seconds
Started Jul 06 06:30:57 PM PDT 24
Finished Jul 06 06:30:59 PM PDT 24
Peak memory 209028 kb
Host smart-5a39b950-6b30-47d3-a773-d3cb07ccb906
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074780313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.4074780313
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.209924082
Short name T37
Test name
Test status
Simulation time 355675055 ps
CPU time 17.06 seconds
Started Jul 06 06:30:57 PM PDT 24
Finished Jul 06 06:31:14 PM PDT 24
Peak memory 226060 kb
Host smart-0b1fca17-6c86-4816-a485-0a368efacd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209924082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.209924082
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.2528834342
Short name T731
Test name
Test status
Simulation time 111013983 ps
CPU time 1.93 seconds
Started Jul 06 06:30:55 PM PDT 24
Finished Jul 06 06:30:58 PM PDT 24
Peak memory 217020 kb
Host smart-554eb9ef-bd1b-4003-9a85-2539feb45526
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528834342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.2528834342
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.3396484248
Short name T104
Test name
Test status
Simulation time 166605106 ps
CPU time 2.46 seconds
Started Jul 06 06:30:56 PM PDT 24
Finished Jul 06 06:30:59 PM PDT 24
Peak memory 218236 kb
Host smart-637d197d-603e-452d-a180-be39cece06e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396484248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3396484248
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.1664849179
Short name T232
Test name
Test status
Simulation time 336600919 ps
CPU time 10.1 seconds
Started Jul 06 06:30:56 PM PDT 24
Finished Jul 06 06:31:06 PM PDT 24
Peak memory 226024 kb
Host smart-474c147c-b397-4af7-a47d-99a05ce1e2b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664849179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1664849179
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2733188274
Short name T761
Test name
Test status
Simulation time 791363359 ps
CPU time 9.81 seconds
Started Jul 06 06:30:54 PM PDT 24
Finished Jul 06 06:31:04 PM PDT 24
Peak memory 226028 kb
Host smart-ab2770da-750a-4479-930d-2e3226e9bbf2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733188274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.2733188274
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.755356332
Short name T598
Test name
Test status
Simulation time 5574080610 ps
CPU time 13.11 seconds
Started Jul 06 06:30:55 PM PDT 24
Finished Jul 06 06:31:08 PM PDT 24
Peak memory 218312 kb
Host smart-ebe52961-5a78-42b1-9d3f-bcabaa113724
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755356332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.755356332
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.4021217184
Short name T567
Test name
Test status
Simulation time 901429757 ps
CPU time 14.77 seconds
Started Jul 06 06:31:00 PM PDT 24
Finished Jul 06 06:31:16 PM PDT 24
Peak memory 226036 kb
Host smart-9ca3e2ae-1082-4641-8ffd-8a69df3407b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021217184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.4021217184
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.3568400315
Short name T91
Test name
Test status
Simulation time 57593554 ps
CPU time 2.75 seconds
Started Jul 06 06:31:00 PM PDT 24
Finished Jul 06 06:31:03 PM PDT 24
Peak memory 214944 kb
Host smart-8e1f7c34-fc1d-465b-8058-8b4e927596c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568400315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.3568400315
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.454402082
Short name T757
Test name
Test status
Simulation time 1535010724 ps
CPU time 29.66 seconds
Started Jul 06 06:30:52 PM PDT 24
Finished Jul 06 06:31:22 PM PDT 24
Peak memory 250984 kb
Host smart-d9f67731-bc45-4852-b532-df5a913c5f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454402082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.454402082
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.70655742
Short name T330
Test name
Test status
Simulation time 320266689 ps
CPU time 8.65 seconds
Started Jul 06 06:30:59 PM PDT 24
Finished Jul 06 06:31:08 PM PDT 24
Peak memory 250804 kb
Host smart-58f4427e-7cb4-416e-84f1-3631bdec7295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70655742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.70655742
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3444892149
Short name T586
Test name
Test status
Simulation time 4677100163 ps
CPU time 122.16 seconds
Started Jul 06 06:30:56 PM PDT 24
Finished Jul 06 06:32:59 PM PDT 24
Peak memory 251064 kb
Host smart-9b7dab10-765f-41fd-8b9f-76cb9bcabcbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444892149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3444892149
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3153464884
Short name T361
Test name
Test status
Simulation time 19440822 ps
CPU time 0.91 seconds
Started Jul 06 06:30:56 PM PDT 24
Finished Jul 06 06:30:58 PM PDT 24
Peak memory 211840 kb
Host smart-bfd3a96f-8c23-4b29-9fe6-b8d0b9a7a8a8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153464884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3153464884
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.1194145383
Short name T211
Test name
Test status
Simulation time 16641841 ps
CPU time 0.92 seconds
Started Jul 06 06:30:57 PM PDT 24
Finished Jul 06 06:30:59 PM PDT 24
Peak memory 208944 kb
Host smart-51e15e74-a7ef-4df1-96eb-2b1a99f2919d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194145383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.1194145383
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.2149416093
Short name T329
Test name
Test status
Simulation time 187553225 ps
CPU time 8.35 seconds
Started Jul 06 06:30:57 PM PDT 24
Finished Jul 06 06:31:06 PM PDT 24
Peak memory 218300 kb
Host smart-6cbb85c5-3801-4706-a313-8e1d854dff02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149416093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2149416093
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.8258759
Short name T521
Test name
Test status
Simulation time 263519956 ps
CPU time 3.62 seconds
Started Jul 06 06:30:58 PM PDT 24
Finished Jul 06 06:31:02 PM PDT 24
Peak memory 217132 kb
Host smart-5cb1ab17-51fc-4e71-9d9c-fc2df0377067
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8258759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.8258759
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.552410002
Short name T589
Test name
Test status
Simulation time 168466960 ps
CPU time 4.21 seconds
Started Jul 06 06:31:01 PM PDT 24
Finished Jul 06 06:31:06 PM PDT 24
Peak memory 218220 kb
Host smart-f78a5b55-c9ef-4ca0-9cda-27d7971a829c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552410002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.552410002
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1028634968
Short name T221
Test name
Test status
Simulation time 248168180 ps
CPU time 11.1 seconds
Started Jul 06 06:30:58 PM PDT 24
Finished Jul 06 06:31:10 PM PDT 24
Peak memory 226052 kb
Host smart-a893d94b-54e3-40f3-a4c7-448f64d572ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028634968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1028634968
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.120160900
Short name T259
Test name
Test status
Simulation time 2208547154 ps
CPU time 9.82 seconds
Started Jul 06 06:30:58 PM PDT 24
Finished Jul 06 06:31:08 PM PDT 24
Peak memory 218252 kb
Host smart-fe425510-65db-4c02-b3b5-b6f808b22d51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120160900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.120160900
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.4146936448
Short name T340
Test name
Test status
Simulation time 1748244962 ps
CPU time 15.74 seconds
Started Jul 06 06:31:03 PM PDT 24
Finished Jul 06 06:31:19 PM PDT 24
Peak memory 226052 kb
Host smart-b3196eef-1477-4ea8-80f1-ba9f3f39b5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146936448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.4146936448
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1688661100
Short name T468
Test name
Test status
Simulation time 67756131 ps
CPU time 3.12 seconds
Started Jul 06 06:31:03 PM PDT 24
Finished Jul 06 06:31:07 PM PDT 24
Peak memory 217736 kb
Host smart-08f5faff-7574-4e85-8225-c755365da766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688661100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1688661100
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.3713521244
Short name T501
Test name
Test status
Simulation time 1322046009 ps
CPU time 32.02 seconds
Started Jul 06 06:30:58 PM PDT 24
Finished Jul 06 06:31:30 PM PDT 24
Peak memory 250952 kb
Host smart-9e62ebfa-24f7-41fd-a881-2baca6b7c267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713521244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.3713521244
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.3567752804
Short name T510
Test name
Test status
Simulation time 406840464 ps
CPU time 7.16 seconds
Started Jul 06 06:31:00 PM PDT 24
Finished Jul 06 06:31:08 PM PDT 24
Peak memory 242944 kb
Host smart-e2c17077-8e38-4d17-9dba-b9fc144ac58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567752804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3567752804
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.260269175
Short name T829
Test name
Test status
Simulation time 46830629681 ps
CPU time 345 seconds
Started Jul 06 06:31:03 PM PDT 24
Finished Jul 06 06:36:49 PM PDT 24
Peak memory 283780 kb
Host smart-de5960e7-fac9-4d23-abbd-bd0c4385ab3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260269175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.260269175
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3720422854
Short name T159
Test name
Test status
Simulation time 14349533 ps
CPU time 0.82 seconds
Started Jul 06 06:31:03 PM PDT 24
Finished Jul 06 06:31:05 PM PDT 24
Peak memory 208696 kb
Host smart-5bb00adc-f099-4dac-b05d-17795e3c1885
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720422854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3720422854
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.3052622231
Short name T620
Test name
Test status
Simulation time 25401528 ps
CPU time 0.89 seconds
Started Jul 06 06:29:38 PM PDT 24
Finished Jul 06 06:29:39 PM PDT 24
Peak memory 208988 kb
Host smart-595ab17e-ff59-46f7-ba7a-fee7b2a3a742
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052622231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3052622231
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3908898253
Short name T205
Test name
Test status
Simulation time 11381618 ps
CPU time 0.83 seconds
Started Jul 06 06:29:34 PM PDT 24
Finished Jul 06 06:29:35 PM PDT 24
Peak memory 208768 kb
Host smart-65c43e7b-5d3a-480f-9ec2-d29bef87a723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908898253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3908898253
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2366782051
Short name T42
Test name
Test status
Simulation time 1603147997 ps
CPU time 19.62 seconds
Started Jul 06 06:29:33 PM PDT 24
Finished Jul 06 06:29:53 PM PDT 24
Peak memory 218080 kb
Host smart-9b2018e8-6d54-4f8f-82d4-5a88a9e38317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366782051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2366782051
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.4112153802
Short name T31
Test name
Test status
Simulation time 463770170 ps
CPU time 6.34 seconds
Started Jul 06 06:29:38 PM PDT 24
Finished Jul 06 06:29:44 PM PDT 24
Peak memory 217404 kb
Host smart-d37fc928-e4b0-4194-af92-e3ee6357fe3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112153802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.4112153802
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.4021085962
Short name T656
Test name
Test status
Simulation time 13213687047 ps
CPU time 53.45 seconds
Started Jul 06 06:29:33 PM PDT 24
Finished Jul 06 06:30:27 PM PDT 24
Peak memory 218972 kb
Host smart-62fbcec2-d25d-4ecd-8549-4569986275b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021085962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.4021085962
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.1497763653
Short name T798
Test name
Test status
Simulation time 12267312323 ps
CPU time 6.82 seconds
Started Jul 06 06:29:33 PM PDT 24
Finished Jul 06 06:29:41 PM PDT 24
Peak memory 217824 kb
Host smart-81baac76-69a3-4732-af68-fd5aa160eab2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497763653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.1
497763653
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.4103105884
Short name T810
Test name
Test status
Simulation time 872264838 ps
CPU time 12.64 seconds
Started Jul 06 06:29:48 PM PDT 24
Finished Jul 06 06:30:01 PM PDT 24
Peak memory 224176 kb
Host smart-762c7f64-9a8f-486b-bf43-7f11aa0df458
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103105884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.4103105884
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2529393649
Short name T24
Test name
Test status
Simulation time 5179567808 ps
CPU time 16.59 seconds
Started Jul 06 06:29:35 PM PDT 24
Finished Jul 06 06:29:52 PM PDT 24
Peak memory 217828 kb
Host smart-b2eaa8b6-04fb-4fca-b093-560e3029fe6c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529393649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2529393649
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1993586429
Short name T309
Test name
Test status
Simulation time 1324274939 ps
CPU time 2.13 seconds
Started Jul 06 06:29:36 PM PDT 24
Finished Jul 06 06:29:39 PM PDT 24
Peak memory 217732 kb
Host smart-46a05e52-a8f6-4bf9-b6ea-6b033fb13357
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993586429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1993586429
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2724684509
Short name T88
Test name
Test status
Simulation time 13975467195 ps
CPU time 102.1 seconds
Started Jul 06 06:29:41 PM PDT 24
Finished Jul 06 06:31:29 PM PDT 24
Peak memory 275776 kb
Host smart-78516a23-5097-4a8e-9ac7-ba6427c31894
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724684509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2724684509
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.1924778453
Short name T442
Test name
Test status
Simulation time 368016122 ps
CPU time 13.13 seconds
Started Jul 06 06:29:36 PM PDT 24
Finished Jul 06 06:29:49 PM PDT 24
Peak memory 250796 kb
Host smart-eb87749a-9032-4600-96da-583b14c8382a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924778453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.1924778453
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.3207372319
Short name T302
Test name
Test status
Simulation time 243592738 ps
CPU time 2.52 seconds
Started Jul 06 06:29:55 PM PDT 24
Finished Jul 06 06:30:02 PM PDT 24
Peak memory 218216 kb
Host smart-662508e1-53dd-411c-8607-307218af320a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207372319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.3207372319
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1299259292
Short name T511
Test name
Test status
Simulation time 247470611 ps
CPU time 10.09 seconds
Started Jul 06 06:29:51 PM PDT 24
Finished Jul 06 06:30:02 PM PDT 24
Peak memory 214632 kb
Host smart-df86dacd-71a8-40b6-b3eb-7b5c8350421d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299259292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1299259292
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1045287704
Short name T50
Test name
Test status
Simulation time 105239065 ps
CPU time 23.34 seconds
Started Jul 06 06:29:39 PM PDT 24
Finished Jul 06 06:30:03 PM PDT 24
Peak memory 269352 kb
Host smart-ed3c77ab-d960-461c-9ea5-b56df96687a8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045287704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1045287704
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2958714381
Short name T733
Test name
Test status
Simulation time 804728936 ps
CPU time 8.69 seconds
Started Jul 06 06:29:41 PM PDT 24
Finished Jul 06 06:29:50 PM PDT 24
Peak memory 225860 kb
Host smart-e8154bad-2367-4f53-8bc9-de0a420eb072
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958714381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2958714381
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.769566553
Short name T607
Test name
Test status
Simulation time 237695812 ps
CPU time 7.46 seconds
Started Jul 06 06:29:45 PM PDT 24
Finished Jul 06 06:29:53 PM PDT 24
Peak memory 218276 kb
Host smart-c5d50e21-e447-4dd9-a517-4cb65717c3ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769566553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.769566553
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.98333446
Short name T557
Test name
Test status
Simulation time 637764030 ps
CPU time 6.83 seconds
Started Jul 06 06:29:51 PM PDT 24
Finished Jul 06 06:29:58 PM PDT 24
Peak memory 226052 kb
Host smart-4f34ed3c-a4a2-43aa-acb5-49bea7358110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98333446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.98333446
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.4036648979
Short name T4
Test name
Test status
Simulation time 38911525 ps
CPU time 2.42 seconds
Started Jul 06 06:29:47 PM PDT 24
Finished Jul 06 06:29:50 PM PDT 24
Peak memory 214528 kb
Host smart-95b8bbe2-7ee0-44fc-9389-21bf4f5e0427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036648979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.4036648979
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.2648878314
Short name T631
Test name
Test status
Simulation time 662252571 ps
CPU time 23.74 seconds
Started Jul 06 06:29:36 PM PDT 24
Finished Jul 06 06:30:00 PM PDT 24
Peak memory 250976 kb
Host smart-76128fc9-0745-4776-b770-bbc0c11a9e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648878314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2648878314
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.4244609894
Short name T420
Test name
Test status
Simulation time 82706508 ps
CPU time 3.36 seconds
Started Jul 06 06:29:56 PM PDT 24
Finished Jul 06 06:30:00 PM PDT 24
Peak memory 226396 kb
Host smart-92c7addf-88d7-4396-96d8-1b1e8cf87da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244609894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.4244609894
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.2128165027
Short name T437
Test name
Test status
Simulation time 7015311237 ps
CPU time 117.93 seconds
Started Jul 06 06:29:48 PM PDT 24
Finished Jul 06 06:31:46 PM PDT 24
Peak memory 280408 kb
Host smart-1af49ae5-6623-436a-b0fb-0e2814b51f5c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128165027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.2128165027
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.579586446
Short name T150
Test name
Test status
Simulation time 48803341802 ps
CPU time 420.23 seconds
Started Jul 06 06:29:36 PM PDT 24
Finished Jul 06 06:36:36 PM PDT 24
Peak memory 292044 kb
Host smart-3b77cf59-045d-46f2-a4ad-c8b3f8346702
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=579586446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.579586446
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2752196445
Short name T421
Test name
Test status
Simulation time 13632998 ps
CPU time 1.01 seconds
Started Jul 06 06:29:36 PM PDT 24
Finished Jul 06 06:29:37 PM PDT 24
Peak memory 211968 kb
Host smart-5a5c55c6-f959-4ae3-991f-0ed2a51efd37
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752196445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2752196445
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.3827780151
Short name T855
Test name
Test status
Simulation time 23790004 ps
CPU time 1.03 seconds
Started Jul 06 06:31:02 PM PDT 24
Finished Jul 06 06:31:04 PM PDT 24
Peak memory 209064 kb
Host smart-7b670482-4517-40a0-9df8-858fc798dfff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827780151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.3827780151
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.1202382524
Short name T495
Test name
Test status
Simulation time 302175447 ps
CPU time 12.15 seconds
Started Jul 06 06:30:58 PM PDT 24
Finished Jul 06 06:31:11 PM PDT 24
Peak memory 218192 kb
Host smart-b34fa5bc-afa0-4fcc-8bc5-246482cc7ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202382524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1202382524
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.3138926816
Short name T487
Test name
Test status
Simulation time 2551002635 ps
CPU time 15.7 seconds
Started Jul 06 06:30:59 PM PDT 24
Finished Jul 06 06:31:15 PM PDT 24
Peak memory 217788 kb
Host smart-58aa2cf8-f9b3-4a57-a490-4711256c323a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138926816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.3138926816
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3699965795
Short name T448
Test name
Test status
Simulation time 204499629 ps
CPU time 2.54 seconds
Started Jul 06 06:31:02 PM PDT 24
Finished Jul 06 06:31:06 PM PDT 24
Peak memory 222268 kb
Host smart-b3cacd83-e80c-4a21-927e-85be4e3ac40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699965795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3699965795
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.1030278901
Short name T528
Test name
Test status
Simulation time 852068331 ps
CPU time 13.14 seconds
Started Jul 06 06:30:58 PM PDT 24
Finished Jul 06 06:31:11 PM PDT 24
Peak memory 226028 kb
Host smart-239e374e-8507-4c32-ad83-80b25eca2008
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030278901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.1030278901
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.3666137687
Short name T590
Test name
Test status
Simulation time 3947496604 ps
CPU time 27.8 seconds
Started Jul 06 06:31:03 PM PDT 24
Finished Jul 06 06:31:32 PM PDT 24
Peak memory 226096 kb
Host smart-3ac9f388-5425-455c-bbed-bc3ff2d95a05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666137687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.3666137687
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.2615426496
Short name T454
Test name
Test status
Simulation time 352771917 ps
CPU time 13.25 seconds
Started Jul 06 06:31:04 PM PDT 24
Finished Jul 06 06:31:18 PM PDT 24
Peak memory 226060 kb
Host smart-137e585a-007c-4839-b36e-fbf7b52b8000
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615426496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
2615426496
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.2568245874
Short name T258
Test name
Test status
Simulation time 1266830134 ps
CPU time 7.89 seconds
Started Jul 06 06:30:56 PM PDT 24
Finished Jul 06 06:31:05 PM PDT 24
Peak memory 225100 kb
Host smart-b3ce7cbb-60e5-4e30-a0d1-a50a8bcb88b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568245874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.2568245874
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.201423759
Short name T66
Test name
Test status
Simulation time 58476120 ps
CPU time 3.28 seconds
Started Jul 06 06:30:58 PM PDT 24
Finished Jul 06 06:31:02 PM PDT 24
Peak memory 214812 kb
Host smart-0a06cb8f-2179-4a6e-8cbe-345398c7505e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201423759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.201423759
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.3256759127
Short name T520
Test name
Test status
Simulation time 413584665 ps
CPU time 18.54 seconds
Started Jul 06 06:31:00 PM PDT 24
Finished Jul 06 06:31:19 PM PDT 24
Peak memory 250928 kb
Host smart-125d15b8-bb19-4cfe-ae28-02e8293ce0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256759127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3256759127
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.2940357934
Short name T174
Test name
Test status
Simulation time 55191883 ps
CPU time 6.95 seconds
Started Jul 06 06:31:01 PM PDT 24
Finished Jul 06 06:31:08 PM PDT 24
Peak memory 250560 kb
Host smart-9886708d-a15c-4230-94a1-6557f607f615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940357934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2940357934
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.4142357697
Short name T423
Test name
Test status
Simulation time 12546692499 ps
CPU time 148.89 seconds
Started Jul 06 06:31:04 PM PDT 24
Finished Jul 06 06:33:34 PM PDT 24
Peak memory 280968 kb
Host smart-ffa9cd89-4b47-4c3c-98cc-3a8220f6e243
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142357697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.4142357697
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.1534998394
Short name T775
Test name
Test status
Simulation time 17809055238 ps
CPU time 428.89 seconds
Started Jul 06 06:31:02 PM PDT 24
Finished Jul 06 06:38:12 PM PDT 24
Peak memory 405028 kb
Host smart-7a91e9a2-4eb6-45fd-adb2-c470eaebd082
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1534998394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.1534998394
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.4070915438
Short name T14
Test name
Test status
Simulation time 11393011 ps
CPU time 0.96 seconds
Started Jul 06 06:30:58 PM PDT 24
Finished Jul 06 06:30:59 PM PDT 24
Peak memory 211992 kb
Host smart-b516fc00-a40b-4ae0-bd39-905d7e5e0220
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070915438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.4070915438
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.1484930229
Short name T645
Test name
Test status
Simulation time 15137542 ps
CPU time 1.11 seconds
Started Jul 06 06:31:03 PM PDT 24
Finished Jul 06 06:31:05 PM PDT 24
Peak memory 208968 kb
Host smart-e48f5a6a-3948-473c-b488-5c6ee4634d0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484930229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1484930229
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.2463670751
Short name T417
Test name
Test status
Simulation time 472291535 ps
CPU time 7.67 seconds
Started Jul 06 06:31:06 PM PDT 24
Finished Jul 06 06:31:14 PM PDT 24
Peak memory 218240 kb
Host smart-2cb851bc-92e3-4cce-92fb-22c5241c9a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463670751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.2463670751
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.2250588412
Short name T732
Test name
Test status
Simulation time 1725237316 ps
CPU time 3.87 seconds
Started Jul 06 06:31:06 PM PDT 24
Finished Jul 06 06:31:11 PM PDT 24
Peak memory 217260 kb
Host smart-2a7fa965-235b-45c9-8ba6-51e4930facd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250588412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.2250588412
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3862991679
Short name T744
Test name
Test status
Simulation time 114541031 ps
CPU time 3.45 seconds
Started Jul 06 06:31:02 PM PDT 24
Finished Jul 06 06:31:06 PM PDT 24
Peak memory 222388 kb
Host smart-079e48ba-3411-4fd0-ade9-72c707b8d78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862991679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3862991679
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.3095718730
Short name T651
Test name
Test status
Simulation time 926913391 ps
CPU time 18.9 seconds
Started Jul 06 06:31:01 PM PDT 24
Finished Jul 06 06:31:21 PM PDT 24
Peak memory 226048 kb
Host smart-306ddb03-01e1-4498-9c5c-9b724b8170eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095718730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.3095718730
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3193848352
Short name T532
Test name
Test status
Simulation time 3236112744 ps
CPU time 11.14 seconds
Started Jul 06 06:31:03 PM PDT 24
Finished Jul 06 06:31:16 PM PDT 24
Peak memory 226024 kb
Host smart-c27fc844-a2f3-4d57-b22d-8dd52dc120e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193848352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.3193848352
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3245888924
Short name T289
Test name
Test status
Simulation time 560025443 ps
CPU time 13.7 seconds
Started Jul 06 06:31:04 PM PDT 24
Finished Jul 06 06:31:18 PM PDT 24
Peak memory 218260 kb
Host smart-de1a3a7d-be43-404e-8aaf-a63186307956
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245888924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
3245888924
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.965452200
Short name T46
Test name
Test status
Simulation time 7744124276 ps
CPU time 9.57 seconds
Started Jul 06 06:31:05 PM PDT 24
Finished Jul 06 06:31:16 PM PDT 24
Peak memory 226120 kb
Host smart-08bce40a-ed3d-4ebb-9310-a29eeabdd6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965452200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.965452200
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.385046860
Short name T269
Test name
Test status
Simulation time 30212866 ps
CPU time 1.52 seconds
Started Jul 06 06:31:04 PM PDT 24
Finished Jul 06 06:31:06 PM PDT 24
Peak memory 213924 kb
Host smart-a7c14b4e-9351-4ae9-b7de-4c589a88f860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385046860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.385046860
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.74997274
Short name T13
Test name
Test status
Simulation time 272438222 ps
CPU time 27.73 seconds
Started Jul 06 06:31:04 PM PDT 24
Finished Jul 06 06:31:32 PM PDT 24
Peak memory 251000 kb
Host smart-d80e81c5-aff6-4101-b937-76a557421431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74997274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.74997274
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.163350597
Short name T440
Test name
Test status
Simulation time 142188967 ps
CPU time 8.33 seconds
Started Jul 06 06:31:03 PM PDT 24
Finished Jul 06 06:31:12 PM PDT 24
Peak memory 250504 kb
Host smart-e0761cf8-5d3f-450d-9e9c-dad0852aba53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163350597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.163350597
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3942277831
Short name T597
Test name
Test status
Simulation time 14081471 ps
CPU time 1.08 seconds
Started Jul 06 06:31:04 PM PDT 24
Finished Jul 06 06:31:06 PM PDT 24
Peak memory 211904 kb
Host smart-e1ba074d-50b5-4010-bd81-28bc5f29b3a4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942277831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3942277831
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3957444810
Short name T266
Test name
Test status
Simulation time 40315753 ps
CPU time 1.19 seconds
Started Jul 06 06:31:06 PM PDT 24
Finished Jul 06 06:31:08 PM PDT 24
Peak memory 208976 kb
Host smart-b37042f4-e298-4ef0-bcce-bfd192f6f83d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957444810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3957444810
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2092182714
Short name T303
Test name
Test status
Simulation time 365415160 ps
CPU time 12.87 seconds
Started Jul 06 06:31:02 PM PDT 24
Finished Jul 06 06:31:16 PM PDT 24
Peak memory 218260 kb
Host smart-ff378cca-4946-43e8-9c34-c6503eed48d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092182714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2092182714
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.3496781021
Short name T28
Test name
Test status
Simulation time 510704821 ps
CPU time 12.46 seconds
Started Jul 06 06:31:07 PM PDT 24
Finished Jul 06 06:31:20 PM PDT 24
Peak memory 217508 kb
Host smart-51477eb0-1326-4df7-8c1f-2eee55289ea9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496781021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.3496781021
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.922364711
Short name T224
Test name
Test status
Simulation time 64345883 ps
CPU time 1.75 seconds
Started Jul 06 06:31:03 PM PDT 24
Finished Jul 06 06:31:06 PM PDT 24
Peak memory 218220 kb
Host smart-16fee1ba-7739-49f5-8e6f-644b099b1884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922364711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.922364711
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.130267688
Short name T342
Test name
Test status
Simulation time 560906147 ps
CPU time 11.3 seconds
Started Jul 06 06:31:06 PM PDT 24
Finished Jul 06 06:31:18 PM PDT 24
Peak memory 226040 kb
Host smart-5d579128-11b0-476f-982f-fc15d55b37e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130267688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_di
gest.130267688
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.3204383825
Short name T665
Test name
Test status
Simulation time 249616264 ps
CPU time 9.32 seconds
Started Jul 06 06:31:06 PM PDT 24
Finished Jul 06 06:31:16 PM PDT 24
Peak memory 218264 kb
Host smart-2f951fc6-0307-41df-abc1-bd48b2681865
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204383825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
3204383825
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3367480830
Short name T650
Test name
Test status
Simulation time 932890911 ps
CPU time 17.52 seconds
Started Jul 06 06:31:05 PM PDT 24
Finished Jul 06 06:31:23 PM PDT 24
Peak memory 218296 kb
Host smart-381ce57f-5c66-4959-93ef-cd35c445287d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367480830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3367480830
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.569050711
Short name T836
Test name
Test status
Simulation time 19389174 ps
CPU time 1.51 seconds
Started Jul 06 06:31:03 PM PDT 24
Finished Jul 06 06:31:06 PM PDT 24
Peak memory 213752 kb
Host smart-74643195-b5fa-434d-99ee-13f172158568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569050711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.569050711
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.2707295998
Short name T393
Test name
Test status
Simulation time 377956661 ps
CPU time 24.65 seconds
Started Jul 06 06:31:03 PM PDT 24
Finished Jul 06 06:31:28 PM PDT 24
Peak memory 250992 kb
Host smart-fe1b8905-79d9-4994-b4f1-06aa628ba7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707295998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.2707295998
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1321140217
Short name T312
Test name
Test status
Simulation time 212682904 ps
CPU time 2.84 seconds
Started Jul 06 06:31:03 PM PDT 24
Finished Jul 06 06:31:06 PM PDT 24
Peak memory 222632 kb
Host smart-ac63e2c7-2868-43ed-b194-863171b5d648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321140217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1321140217
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.2735700993
Short name T544
Test name
Test status
Simulation time 5403731209 ps
CPU time 168.01 seconds
Started Jul 06 06:31:07 PM PDT 24
Finished Jul 06 06:33:55 PM PDT 24
Peak memory 282748 kb
Host smart-fab54c8f-65fe-406d-ad31-3f39e0061207
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735700993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.2735700993
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3393698557
Short name T718
Test name
Test status
Simulation time 66564964 ps
CPU time 0.95 seconds
Started Jul 06 06:31:02 PM PDT 24
Finished Jul 06 06:31:03 PM PDT 24
Peak memory 212996 kb
Host smart-3013efd4-a7b3-4dbd-8597-b697a8c89d4d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393698557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.3393698557
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.2035952440
Short name T549
Test name
Test status
Simulation time 14181759 ps
CPU time 0.88 seconds
Started Jul 06 06:31:15 PM PDT 24
Finished Jul 06 06:31:16 PM PDT 24
Peak memory 208780 kb
Host smart-b0814c16-1ab3-45b6-b388-242b37d112af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035952440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2035952440
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.546900155
Short name T404
Test name
Test status
Simulation time 2862371722 ps
CPU time 13.62 seconds
Started Jul 06 06:31:03 PM PDT 24
Finished Jul 06 06:31:18 PM PDT 24
Peak memory 218948 kb
Host smart-e8db7677-0c73-483d-b3a2-c704d663ee05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546900155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.546900155
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.590971782
Short name T5
Test name
Test status
Simulation time 740882871 ps
CPU time 5.12 seconds
Started Jul 06 06:31:14 PM PDT 24
Finished Jul 06 06:31:20 PM PDT 24
Peak memory 217188 kb
Host smart-8634b79b-8ede-4bae-952c-a0188dd22d88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590971782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.590971782
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.847556311
Short name T854
Test name
Test status
Simulation time 164191936 ps
CPU time 3.88 seconds
Started Jul 06 06:31:09 PM PDT 24
Finished Jul 06 06:31:13 PM PDT 24
Peak memory 218220 kb
Host smart-cb0eb98b-1c93-41ff-816f-45141456bbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847556311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.847556311
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3800151899
Short name T345
Test name
Test status
Simulation time 754712487 ps
CPU time 10.53 seconds
Started Jul 06 06:31:14 PM PDT 24
Finished Jul 06 06:31:25 PM PDT 24
Peak memory 225968 kb
Host smart-d6b459fa-f33f-408e-9bcb-bb88332eef4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800151899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.3800151899
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3058538448
Short name T629
Test name
Test status
Simulation time 825037767 ps
CPU time 9.94 seconds
Started Jul 06 06:31:16 PM PDT 24
Finished Jul 06 06:31:26 PM PDT 24
Peak memory 218272 kb
Host smart-4777c77d-e6da-49a2-8ebc-0fe7d8887dde
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058538448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3058538448
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.159027084
Short name T53
Test name
Test status
Simulation time 3910687004 ps
CPU time 8 seconds
Started Jul 06 06:31:11 PM PDT 24
Finished Jul 06 06:31:20 PM PDT 24
Peak memory 225668 kb
Host smart-3206978e-8980-481d-bf99-2560b6a6aee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159027084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.159027084
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.3143542358
Short name T659
Test name
Test status
Simulation time 19404935 ps
CPU time 1.12 seconds
Started Jul 06 06:31:04 PM PDT 24
Finished Jul 06 06:31:06 PM PDT 24
Peak memory 212096 kb
Host smart-015dea46-2c7a-41ed-872a-364820535fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143542358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3143542358
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.1540257010
Short name T394
Test name
Test status
Simulation time 2564442475 ps
CPU time 29.51 seconds
Started Jul 06 06:31:05 PM PDT 24
Finished Jul 06 06:31:36 PM PDT 24
Peak memory 251060 kb
Host smart-57df1fb0-fbde-440d-94f2-aeef045fcdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540257010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.1540257010
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3661381650
Short name T262
Test name
Test status
Simulation time 201188255 ps
CPU time 6.69 seconds
Started Jul 06 06:31:07 PM PDT 24
Finished Jul 06 06:31:14 PM PDT 24
Peak memory 246936 kb
Host smart-c2444609-53a1-41cc-bc5c-8e048f02c808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661381650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3661381650
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1809274384
Short name T305
Test name
Test status
Simulation time 38882111837 ps
CPU time 206.02 seconds
Started Jul 06 06:31:16 PM PDT 24
Finished Jul 06 06:34:43 PM PDT 24
Peak memory 276524 kb
Host smart-3328369d-873d-4bd3-9812-5ecb3d99a6ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809274384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1809274384
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2680242653
Short name T538
Test name
Test status
Simulation time 37198636 ps
CPU time 0.96 seconds
Started Jul 06 06:31:06 PM PDT 24
Finished Jul 06 06:31:08 PM PDT 24
Peak memory 211944 kb
Host smart-1881b00a-90c7-46fa-916b-1b2469414e09
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680242653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.2680242653
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.370845570
Short name T655
Test name
Test status
Simulation time 16001385 ps
CPU time 1.04 seconds
Started Jul 06 06:31:17 PM PDT 24
Finished Jul 06 06:31:19 PM PDT 24
Peak memory 208964 kb
Host smart-be53ef39-f92b-4bc8-92cb-3be5bc0a761c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370845570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.370845570
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.3940594900
Short name T155
Test name
Test status
Simulation time 203396724 ps
CPU time 10.67 seconds
Started Jul 06 06:31:12 PM PDT 24
Finished Jul 06 06:31:23 PM PDT 24
Peak memory 218176 kb
Host smart-fee8dd16-260a-4dbf-8b1e-abdb30c4475a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940594900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.3940594900
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.1756733292
Short name T346
Test name
Test status
Simulation time 3029421860 ps
CPU time 7.84 seconds
Started Jul 06 06:31:15 PM PDT 24
Finished Jul 06 06:31:23 PM PDT 24
Peak memory 217396 kb
Host smart-5cbad564-4ab4-46fe-b7ff-aa962d4ae6e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756733292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.1756733292
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.3248139078
Short name T735
Test name
Test status
Simulation time 113235720 ps
CPU time 1.97 seconds
Started Jul 06 06:31:16 PM PDT 24
Finished Jul 06 06:31:18 PM PDT 24
Peak memory 218272 kb
Host smart-2cf72d7e-f19d-4c4a-90d3-bd16ac4a8001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248139078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3248139078
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.1487427491
Short name T644
Test name
Test status
Simulation time 7625630614 ps
CPU time 13 seconds
Started Jul 06 06:31:13 PM PDT 24
Finished Jul 06 06:31:27 PM PDT 24
Peak memory 226092 kb
Host smart-60056d0b-e4be-44cc-ad14-08f783d56ec8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487427491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1487427491
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.4134344306
Short name T54
Test name
Test status
Simulation time 476816293 ps
CPU time 16.68 seconds
Started Jul 06 06:31:21 PM PDT 24
Finished Jul 06 06:31:38 PM PDT 24
Peak memory 226044 kb
Host smart-a1ac657b-7d35-4715-9ccf-85c6ce6cf469
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134344306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.4134344306
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2169323721
Short name T449
Test name
Test status
Simulation time 194476698 ps
CPU time 8.36 seconds
Started Jul 06 06:31:14 PM PDT 24
Finished Jul 06 06:31:22 PM PDT 24
Peak memory 218304 kb
Host smart-a2ce9376-ea1f-4166-963f-7f498556c24f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169323721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2169323721
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.1253520500
Short name T852
Test name
Test status
Simulation time 449411024 ps
CPU time 9.33 seconds
Started Jul 06 06:31:12 PM PDT 24
Finished Jul 06 06:31:22 PM PDT 24
Peak memory 218308 kb
Host smart-28f969af-3edd-4d72-9b06-ad05d6276b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253520500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.1253520500
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.1780845933
Short name T71
Test name
Test status
Simulation time 122322374 ps
CPU time 2.22 seconds
Started Jul 06 06:31:16 PM PDT 24
Finished Jul 06 06:31:19 PM PDT 24
Peak memory 214496 kb
Host smart-16460d46-a418-402d-9aad-99da31590284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780845933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.1780845933
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.2519769152
Short name T817
Test name
Test status
Simulation time 634349538 ps
CPU time 20.06 seconds
Started Jul 06 06:31:16 PM PDT 24
Finished Jul 06 06:31:36 PM PDT 24
Peak memory 250972 kb
Host smart-831a66e8-ae8a-4d54-8501-9ee1c19c58ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519769152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.2519769152
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.207776848
Short name T496
Test name
Test status
Simulation time 191584400 ps
CPU time 3.15 seconds
Started Jul 06 06:31:18 PM PDT 24
Finished Jul 06 06:31:21 PM PDT 24
Peak memory 222320 kb
Host smart-3d7309a2-6228-44d5-a71c-c03d1bb31d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207776848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.207776848
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.2436376615
Short name T296
Test name
Test status
Simulation time 7193797257 ps
CPU time 44.37 seconds
Started Jul 06 06:31:21 PM PDT 24
Finished Jul 06 06:32:06 PM PDT 24
Peak memory 267460 kb
Host smart-1d6b6852-99b2-4cd5-b0b7-b7181562a664
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436376615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.2436376615
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2012275661
Short name T439
Test name
Test status
Simulation time 12027444 ps
CPU time 1.04 seconds
Started Jul 06 06:31:12 PM PDT 24
Finished Jul 06 06:31:13 PM PDT 24
Peak memory 211884 kb
Host smart-4cd8aa27-ab34-4704-b1d6-fa8927dcf76d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012275661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2012275661
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.4115568970
Short name T635
Test name
Test status
Simulation time 18624390 ps
CPU time 0.97 seconds
Started Jul 06 06:31:18 PM PDT 24
Finished Jul 06 06:31:19 PM PDT 24
Peak memory 208936 kb
Host smart-c96f326d-218a-499f-8372-3338352a5bbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115568970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.4115568970
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.1171018666
Short name T469
Test name
Test status
Simulation time 1838038582 ps
CPU time 13.93 seconds
Started Jul 06 06:31:15 PM PDT 24
Finished Jul 06 06:31:30 PM PDT 24
Peak memory 225972 kb
Host smart-a82bbd8c-5964-4db6-906b-86177982c7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171018666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.1171018666
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.329295994
Short name T314
Test name
Test status
Simulation time 2035405572 ps
CPU time 7.18 seconds
Started Jul 06 06:31:21 PM PDT 24
Finished Jul 06 06:31:28 PM PDT 24
Peak memory 217344 kb
Host smart-7f8fdf32-f08f-4f8e-81a6-65c44b500736
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329295994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.329295994
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.3211800253
Short name T666
Test name
Test status
Simulation time 156891005 ps
CPU time 4.49 seconds
Started Jul 06 06:31:21 PM PDT 24
Finished Jul 06 06:31:26 PM PDT 24
Peak memory 218236 kb
Host smart-6c52708a-98e0-4f11-8ed1-fb803827bf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211800253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3211800253
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.1657232771
Short name T356
Test name
Test status
Simulation time 6695547515 ps
CPU time 17.15 seconds
Started Jul 06 06:31:19 PM PDT 24
Finished Jul 06 06:31:37 PM PDT 24
Peak memory 220008 kb
Host smart-ca70e3c7-6601-4c1a-af1d-bd605245f001
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657232771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.1657232771
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3474243276
Short name T633
Test name
Test status
Simulation time 602617928 ps
CPU time 15.91 seconds
Started Jul 06 06:31:20 PM PDT 24
Finished Jul 06 06:31:36 PM PDT 24
Peak memory 226056 kb
Host smart-e2ac142e-e1e1-4878-a9ca-55e443efe6bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474243276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3474243276
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.4123404644
Short name T472
Test name
Test status
Simulation time 1175319886 ps
CPU time 9.6 seconds
Started Jul 06 06:31:23 PM PDT 24
Finished Jul 06 06:31:33 PM PDT 24
Peak memory 218212 kb
Host smart-b7fd8f64-b501-476f-b89a-4287cca658ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123404644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
4123404644
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.2529722296
Short name T317
Test name
Test status
Simulation time 429439789 ps
CPU time 11.36 seconds
Started Jul 06 06:31:17 PM PDT 24
Finished Jul 06 06:31:28 PM PDT 24
Peak memory 226012 kb
Host smart-f2ff34f7-3378-41c3-a52c-329fc0826090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529722296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2529722296
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3700518720
Short name T355
Test name
Test status
Simulation time 402134914 ps
CPU time 2.93 seconds
Started Jul 06 06:31:17 PM PDT 24
Finished Jul 06 06:31:20 PM PDT 24
Peak memory 223140 kb
Host smart-8cf4c82a-b268-459f-9f49-afb03931ddcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700518720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3700518720
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.2389496362
Short name T268
Test name
Test status
Simulation time 234412979 ps
CPU time 27.72 seconds
Started Jul 06 06:31:20 PM PDT 24
Finished Jul 06 06:31:48 PM PDT 24
Peak memory 250952 kb
Host smart-7874c152-8ea9-4ce3-b8e6-974ecd96b142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389496362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.2389496362
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.3799493804
Short name T807
Test name
Test status
Simulation time 469233917 ps
CPU time 3.63 seconds
Started Jul 06 06:31:15 PM PDT 24
Finished Jul 06 06:31:19 PM PDT 24
Peak memory 222400 kb
Host smart-2edb7511-a41c-46bc-bbb3-c68f7ee04f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799493804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.3799493804
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.739719117
Short name T668
Test name
Test status
Simulation time 2751430294 ps
CPU time 53.84 seconds
Started Jul 06 06:31:16 PM PDT 24
Finished Jul 06 06:32:11 PM PDT 24
Peak memory 252484 kb
Host smart-cda67bf5-2776-442c-a1ff-f25af488dec0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739719117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.739719117
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2674735413
Short name T749
Test name
Test status
Simulation time 31192372 ps
CPU time 0.84 seconds
Started Jul 06 06:31:22 PM PDT 24
Finished Jul 06 06:31:23 PM PDT 24
Peak memory 211912 kb
Host smart-1ce8c3ed-43d0-400d-8825-f843e25a9628
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674735413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2674735413
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.1582570723
Short name T742
Test name
Test status
Simulation time 27023158 ps
CPU time 0.91 seconds
Started Jul 06 06:31:17 PM PDT 24
Finished Jul 06 06:31:18 PM PDT 24
Peak memory 209008 kb
Host smart-8057b305-618b-421f-9c86-3401529f1dad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582570723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.1582570723
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.537809952
Short name T33
Test name
Test status
Simulation time 292411188 ps
CPU time 8.44 seconds
Started Jul 06 06:31:20 PM PDT 24
Finished Jul 06 06:31:29 PM PDT 24
Peak memory 217352 kb
Host smart-482cb54b-4338-4ab4-b3ab-e9d35e84dae4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537809952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.537809952
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.3689009889
Short name T570
Test name
Test status
Simulation time 123917355 ps
CPU time 2.84 seconds
Started Jul 06 06:31:16 PM PDT 24
Finished Jul 06 06:31:19 PM PDT 24
Peak memory 218272 kb
Host smart-cea87166-7968-4dc9-a057-ff2b88c862e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689009889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3689009889
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3078225098
Short name T615
Test name
Test status
Simulation time 298475543 ps
CPU time 10.92 seconds
Started Jul 06 06:31:18 PM PDT 24
Finished Jul 06 06:31:29 PM PDT 24
Peak memory 226040 kb
Host smart-d1fd92f3-9e4e-4c55-9184-f3394af39211
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078225098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.3078225098
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2725012582
Short name T721
Test name
Test status
Simulation time 368735805 ps
CPU time 7.61 seconds
Started Jul 06 06:31:18 PM PDT 24
Finished Jul 06 06:31:25 PM PDT 24
Peak memory 218252 kb
Host smart-24ccb7d2-d97e-4ed7-a27d-04bbf909032f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725012582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2725012582
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1936720022
Short name T416
Test name
Test status
Simulation time 350907742 ps
CPU time 7.85 seconds
Started Jul 06 06:31:23 PM PDT 24
Finished Jul 06 06:31:31 PM PDT 24
Peak memory 218256 kb
Host smart-27125912-74e1-43d4-94a6-74a7083a6598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936720022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1936720022
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.3489432625
Short name T72
Test name
Test status
Simulation time 53090906 ps
CPU time 1.43 seconds
Started Jul 06 06:31:15 PM PDT 24
Finished Jul 06 06:31:17 PM PDT 24
Peak memory 213632 kb
Host smart-d09e256f-15b9-4625-9988-ea5741a7c2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489432625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.3489432625
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3968420003
Short name T826
Test name
Test status
Simulation time 994674935 ps
CPU time 18.74 seconds
Started Jul 06 06:31:21 PM PDT 24
Finished Jul 06 06:31:40 PM PDT 24
Peak memory 250956 kb
Host smart-8981f925-79f0-4eb6-baee-a33259cc9e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968420003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3968420003
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.358540770
Short name T382
Test name
Test status
Simulation time 72247480 ps
CPU time 8.45 seconds
Started Jul 06 06:31:19 PM PDT 24
Finished Jul 06 06:31:27 PM PDT 24
Peak memory 250920 kb
Host smart-5414e3cf-e1b6-4629-bc38-da02fcb68921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358540770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.358540770
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.3544653166
Short name T360
Test name
Test status
Simulation time 6384419829 ps
CPU time 117.52 seconds
Started Jul 06 06:31:15 PM PDT 24
Finished Jul 06 06:33:13 PM PDT 24
Peak memory 276936 kb
Host smart-c548c45a-0ae4-4cf0-b34c-72b3015c2991
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544653166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.3544653166
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2699653566
Short name T283
Test name
Test status
Simulation time 19392056 ps
CPU time 0.94 seconds
Started Jul 06 06:31:21 PM PDT 24
Finished Jul 06 06:31:23 PM PDT 24
Peak memory 211912 kb
Host smart-9db95f8d-4026-41d3-9b39-04be3705b0f0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699653566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.2699653566
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.1134142575
Short name T458
Test name
Test status
Simulation time 21207847 ps
CPU time 1.24 seconds
Started Jul 06 06:31:21 PM PDT 24
Finished Jul 06 06:31:23 PM PDT 24
Peak memory 209088 kb
Host smart-5c4432df-94e4-4a10-9231-f6bd4e022a6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134142575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.1134142575
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1945352028
Short name T368
Test name
Test status
Simulation time 273562278 ps
CPU time 10.93 seconds
Started Jul 06 06:31:23 PM PDT 24
Finished Jul 06 06:31:34 PM PDT 24
Peak memory 226052 kb
Host smart-e28be826-207a-4901-b18d-626d40b562d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945352028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1945352028
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.2393202073
Short name T326
Test name
Test status
Simulation time 1260326983 ps
CPU time 29.06 seconds
Started Jul 06 06:31:22 PM PDT 24
Finished Jul 06 06:31:52 PM PDT 24
Peak memory 217540 kb
Host smart-53ce24c8-2875-4e45-9b9b-6634c44f19af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393202073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.2393202073
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.4250245253
Short name T647
Test name
Test status
Simulation time 385424909 ps
CPU time 4.12 seconds
Started Jul 06 06:31:18 PM PDT 24
Finished Jul 06 06:31:23 PM PDT 24
Peak memory 218224 kb
Host smart-49da13f1-36e0-4bda-81a7-06869c9b833e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250245253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.4250245253
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.1309100691
Short name T673
Test name
Test status
Simulation time 1580800291 ps
CPU time 16.85 seconds
Started Jul 06 06:31:22 PM PDT 24
Finished Jul 06 06:31:39 PM PDT 24
Peak memory 226024 kb
Host smart-078e07f3-7596-4d01-8ddf-20c4151f3d1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309100691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.1309100691
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.375070292
Short name T214
Test name
Test status
Simulation time 221481741 ps
CPU time 6.44 seconds
Started Jul 06 06:31:20 PM PDT 24
Finished Jul 06 06:31:27 PM PDT 24
Peak memory 226048 kb
Host smart-cba6eb19-4c9b-40e8-813a-6d395a742ea2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375070292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.375070292
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.844432128
Short name T546
Test name
Test status
Simulation time 1466123282 ps
CPU time 8.53 seconds
Started Jul 06 06:31:19 PM PDT 24
Finished Jul 06 06:31:28 PM PDT 24
Peak memory 225984 kb
Host smart-eebb3148-0069-4b80-a663-162a84c67921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844432128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.844432128
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.3031813421
Short name T422
Test name
Test status
Simulation time 196364954 ps
CPU time 3.48 seconds
Started Jul 06 06:31:16 PM PDT 24
Finished Jul 06 06:31:20 PM PDT 24
Peak memory 217752 kb
Host smart-c744e937-8375-418f-848b-eccc9a0908c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031813421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.3031813421
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.2052104354
Short name T554
Test name
Test status
Simulation time 216437687 ps
CPU time 23.15 seconds
Started Jul 06 06:31:23 PM PDT 24
Finished Jul 06 06:31:46 PM PDT 24
Peak memory 250948 kb
Host smart-0d486ceb-2997-4e84-b9df-8b42ba8f3cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052104354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2052104354
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1337792113
Short name T474
Test name
Test status
Simulation time 326197690 ps
CPU time 3.08 seconds
Started Jul 06 06:31:22 PM PDT 24
Finished Jul 06 06:31:25 PM PDT 24
Peak memory 222292 kb
Host smart-52f4a611-e64c-4975-b103-0313c93acb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337792113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1337792113
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.3903613624
Short name T478
Test name
Test status
Simulation time 7551094357 ps
CPU time 46.58 seconds
Started Jul 06 06:31:21 PM PDT 24
Finished Jul 06 06:32:08 PM PDT 24
Peak memory 267444 kb
Host smart-8221f9bb-eccb-4bde-898e-c4542dc8f87f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903613624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.3903613624
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3999996856
Short name T271
Test name
Test status
Simulation time 113511977 ps
CPU time 0.98 seconds
Started Jul 06 06:31:14 PM PDT 24
Finished Jul 06 06:31:15 PM PDT 24
Peak memory 213064 kb
Host smart-fdc245a3-4ded-4807-aca8-037398305622
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999996856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3999996856
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3297782678
Short name T565
Test name
Test status
Simulation time 38734822 ps
CPU time 0.94 seconds
Started Jul 06 06:31:20 PM PDT 24
Finished Jul 06 06:31:22 PM PDT 24
Peak memory 208936 kb
Host smart-c031b84a-60ff-40c6-a3fb-52cc5047a3cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297782678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3297782678
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.4150753579
Short name T489
Test name
Test status
Simulation time 353636029 ps
CPU time 11.07 seconds
Started Jul 06 06:31:22 PM PDT 24
Finished Jul 06 06:31:34 PM PDT 24
Peak memory 218180 kb
Host smart-e382120f-d29e-42c5-bd0a-6e49d8071ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150753579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.4150753579
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.872899990
Short name T576
Test name
Test status
Simulation time 2253785250 ps
CPU time 7.51 seconds
Started Jul 06 06:31:26 PM PDT 24
Finished Jul 06 06:31:34 PM PDT 24
Peak memory 217176 kb
Host smart-ac277eb3-7b8d-4773-8ca1-8d5013d4c554
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872899990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.872899990
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.71700816
Short name T249
Test name
Test status
Simulation time 92515968 ps
CPU time 3.92 seconds
Started Jul 06 06:31:22 PM PDT 24
Finished Jul 06 06:31:26 PM PDT 24
Peak memory 218224 kb
Host smart-95acc50c-72dd-4cde-a580-2f7c42c6a4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71700816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.71700816
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.3860219114
Short name T720
Test name
Test status
Simulation time 1194724485 ps
CPU time 11.03 seconds
Started Jul 06 06:31:22 PM PDT 24
Finished Jul 06 06:31:34 PM PDT 24
Peak memory 226008 kb
Host smart-868ca02d-ebf8-4761-863f-1f8450bbea1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860219114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.3860219114
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.61576511
Short name T250
Test name
Test status
Simulation time 927973706 ps
CPU time 9.01 seconds
Started Jul 06 06:31:27 PM PDT 24
Finished Jul 06 06:31:37 PM PDT 24
Peak memory 225996 kb
Host smart-0df93acc-b311-4cb6-9f5d-83d814d36bd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61576511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_dig
est.61576511
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3538888281
Short name T522
Test name
Test status
Simulation time 206820183 ps
CPU time 8.65 seconds
Started Jul 06 06:31:21 PM PDT 24
Finished Jul 06 06:31:30 PM PDT 24
Peak memory 225980 kb
Host smart-a673ce69-2e59-43b5-8497-fd3eaa75e449
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538888281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3538888281
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.3782292463
Short name T22
Test name
Test status
Simulation time 1056759915 ps
CPU time 10.34 seconds
Started Jul 06 06:31:22 PM PDT 24
Finished Jul 06 06:31:33 PM PDT 24
Peak memory 226004 kb
Host smart-77d61ca9-2d35-4e20-b7c4-0c822cff53a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782292463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3782292463
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.3084425201
Short name T74
Test name
Test status
Simulation time 91663139 ps
CPU time 2.71 seconds
Started Jul 06 06:31:22 PM PDT 24
Finished Jul 06 06:31:25 PM PDT 24
Peak memory 214608 kb
Host smart-8e03b5c9-3909-4fbd-ab9d-1e5caba16e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084425201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.3084425201
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.2019642898
Short name T625
Test name
Test status
Simulation time 484265118 ps
CPU time 27.61 seconds
Started Jul 06 06:31:19 PM PDT 24
Finished Jul 06 06:31:47 PM PDT 24
Peak memory 250940 kb
Host smart-c0ac009e-8ee6-483c-869e-9768eaf0c9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019642898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2019642898
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2105179830
Short name T572
Test name
Test status
Simulation time 792576193 ps
CPU time 7.53 seconds
Started Jul 06 06:31:27 PM PDT 24
Finished Jul 06 06:31:35 PM PDT 24
Peak memory 243028 kb
Host smart-09e81dd0-af66-4171-ada4-f579736d1dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105179830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2105179830
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.1770907601
Short name T157
Test name
Test status
Simulation time 5712761717 ps
CPU time 54.05 seconds
Started Jul 06 06:31:22 PM PDT 24
Finished Jul 06 06:32:16 PM PDT 24
Peak memory 251064 kb
Host smart-33994b6c-475f-4984-ad1b-40ad4af99302
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770907601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.1770907601
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.1744620497
Short name T661
Test name
Test status
Simulation time 381977297068 ps
CPU time 597.82 seconds
Started Jul 06 06:31:21 PM PDT 24
Finished Jul 06 06:41:19 PM PDT 24
Peak memory 529724 kb
Host smart-576ee36c-8e9c-48b6-8f84-6b5072430b13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1744620497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.1744620497
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3680369631
Short name T401
Test name
Test status
Simulation time 13323739 ps
CPU time 0.9 seconds
Started Jul 06 06:31:20 PM PDT 24
Finished Jul 06 06:31:21 PM PDT 24
Peak memory 217748 kb
Host smart-8a40f8d5-4c49-4642-9806-9d1f50d8219a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680369631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.3680369631
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.3679230688
Short name T65
Test name
Test status
Simulation time 40028823 ps
CPU time 0.84 seconds
Started Jul 06 06:31:23 PM PDT 24
Finished Jul 06 06:31:24 PM PDT 24
Peak memory 209236 kb
Host smart-32f886d2-8e47-4828-95f2-4405ba37f51c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679230688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3679230688
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.3421945609
Short name T240
Test name
Test status
Simulation time 330017381 ps
CPU time 15.2 seconds
Started Jul 06 06:31:28 PM PDT 24
Finished Jul 06 06:31:44 PM PDT 24
Peak memory 218180 kb
Host smart-453dd512-3291-4b83-9610-513eeb4102f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421945609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3421945609
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2381757437
Short name T432
Test name
Test status
Simulation time 93252288 ps
CPU time 3.05 seconds
Started Jul 06 06:31:25 PM PDT 24
Finished Jul 06 06:31:28 PM PDT 24
Peak memory 217076 kb
Host smart-6aacdc37-a3ae-4f6f-aacd-476a2f655a24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381757437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2381757437
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.318275642
Short name T662
Test name
Test status
Simulation time 184763857 ps
CPU time 4.5 seconds
Started Jul 06 06:31:26 PM PDT 24
Finished Jul 06 06:31:31 PM PDT 24
Peak memory 222756 kb
Host smart-172ea15e-6eac-49fc-96b2-611ee062e0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318275642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.318275642
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1285118075
Short name T787
Test name
Test status
Simulation time 1373006268 ps
CPU time 11.85 seconds
Started Jul 06 06:31:27 PM PDT 24
Finished Jul 06 06:31:40 PM PDT 24
Peak memory 226056 kb
Host smart-6fd40136-9e95-46f6-bb2d-2b41435e0a68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285118075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1285118075
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.87644558
Short name T459
Test name
Test status
Simulation time 218688386 ps
CPU time 6.78 seconds
Started Jul 06 06:31:23 PM PDT 24
Finished Jul 06 06:31:30 PM PDT 24
Peak memory 226288 kb
Host smart-e304865a-3af8-4b0b-ae82-02e16d9b71c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87644558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_dig
est.87644558
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3501034169
Short name T372
Test name
Test status
Simulation time 277739194 ps
CPU time 8.28 seconds
Started Jul 06 06:31:24 PM PDT 24
Finished Jul 06 06:31:32 PM PDT 24
Peak memory 226060 kb
Host smart-50c18354-337a-4774-81c5-c2a999f95bdc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501034169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
3501034169
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3722597384
Short name T745
Test name
Test status
Simulation time 716522602 ps
CPU time 9.38 seconds
Started Jul 06 06:31:24 PM PDT 24
Finished Jul 06 06:31:33 PM PDT 24
Peak memory 218304 kb
Host smart-9f34536d-23c7-4ce2-ac17-9ed9c4a17f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722597384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3722597384
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.4196264359
Short name T36
Test name
Test status
Simulation time 37548260 ps
CPU time 2.31 seconds
Started Jul 06 06:31:28 PM PDT 24
Finished Jul 06 06:31:30 PM PDT 24
Peak memory 217672 kb
Host smart-f1a9ddc5-c34d-47cc-8fb4-4bad6128612b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196264359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.4196264359
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.2921412595
Short name T530
Test name
Test status
Simulation time 283891001 ps
CPU time 29.67 seconds
Started Jul 06 06:31:20 PM PDT 24
Finished Jul 06 06:31:50 PM PDT 24
Peak memory 251128 kb
Host smart-85e81d81-b946-4c01-80d6-15b725117289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921412595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2921412595
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.1482194024
Short name T101
Test name
Test status
Simulation time 806577427 ps
CPU time 6.95 seconds
Started Jul 06 06:31:28 PM PDT 24
Finished Jul 06 06:31:35 PM PDT 24
Peak memory 250388 kb
Host smart-052c1864-71c8-4eb9-a9d1-0dc8e9c92e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482194024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.1482194024
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1996225762
Short name T179
Test name
Test status
Simulation time 17559966538 ps
CPU time 175.76 seconds
Started Jul 06 06:31:25 PM PDT 24
Finished Jul 06 06:34:21 PM PDT 24
Peak memory 249556 kb
Host smart-2c1fb9e2-a471-468c-bbab-112621b75423
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996225762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1996225762
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.3799322706
Short name T146
Test name
Test status
Simulation time 11976594199 ps
CPU time 339.86 seconds
Started Jul 06 06:31:28 PM PDT 24
Finished Jul 06 06:37:08 PM PDT 24
Peak memory 283908 kb
Host smart-5e574385-104a-4a09-a137-8c9134e775d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3799322706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.3799322706
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.4185021636
Short name T594
Test name
Test status
Simulation time 32058864 ps
CPU time 0.9 seconds
Started Jul 06 06:31:19 PM PDT 24
Finished Jul 06 06:31:21 PM PDT 24
Peak memory 211872 kb
Host smart-fd10d193-fc73-4a22-929c-eed92fb257be
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185021636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.4185021636
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.3482372046
Short name T344
Test name
Test status
Simulation time 75127081 ps
CPU time 1.06 seconds
Started Jul 06 06:29:37 PM PDT 24
Finished Jul 06 06:29:38 PM PDT 24
Peak memory 209000 kb
Host smart-ad3f8ac0-1e2e-4d25-a96d-93b2d442f7d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482372046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3482372046
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3973796638
Short name T574
Test name
Test status
Simulation time 412408166 ps
CPU time 10.04 seconds
Started Jul 06 06:29:33 PM PDT 24
Finished Jul 06 06:29:44 PM PDT 24
Peak memory 218240 kb
Host smart-1fee0175-c63e-40ae-82f4-0368708ee0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973796638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3973796638
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.499366923
Short name T624
Test name
Test status
Simulation time 867766303 ps
CPU time 3.38 seconds
Started Jul 06 06:29:54 PM PDT 24
Finished Jul 06 06:29:58 PM PDT 24
Peak memory 217124 kb
Host smart-264b6031-8e96-43e7-ad0b-e10cdb93c828
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499366923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.499366923
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.580107871
Short name T764
Test name
Test status
Simulation time 5093645450 ps
CPU time 27.54 seconds
Started Jul 06 06:29:38 PM PDT 24
Finished Jul 06 06:30:06 PM PDT 24
Peak memory 218896 kb
Host smart-e1697c69-85c4-4f4b-8b7d-72d1e9050ae5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580107871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_err
ors.580107871
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2463054029
Short name T7
Test name
Test status
Simulation time 2659374621 ps
CPU time 6.32 seconds
Started Jul 06 06:29:37 PM PDT 24
Finished Jul 06 06:29:44 PM PDT 24
Peak memory 217864 kb
Host smart-c0ba9063-785e-4dc8-90e1-39ea1e568799
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463054029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.2
463054029
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.987508137
Short name T334
Test name
Test status
Simulation time 106451971 ps
CPU time 1.88 seconds
Started Jul 06 06:29:41 PM PDT 24
Finished Jul 06 06:29:43 PM PDT 24
Peak memory 221276 kb
Host smart-433e4b15-979d-4f2a-97a5-83479d4dd3ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987508137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.987508137
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1100477449
Short name T820
Test name
Test status
Simulation time 792158024 ps
CPU time 24.36 seconds
Started Jul 06 06:29:39 PM PDT 24
Finished Jul 06 06:30:03 PM PDT 24
Peak memory 217724 kb
Host smart-1966abd7-3fd7-4d98-a0fb-b93ef2e33737
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100477449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1100477449
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2746178994
Short name T78
Test name
Test status
Simulation time 869634296 ps
CPU time 3.64 seconds
Started Jul 06 06:29:45 PM PDT 24
Finished Jul 06 06:29:49 PM PDT 24
Peak memory 217696 kb
Host smart-ac2270f4-111d-4b27-a2ce-7ccdc902568b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746178994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2746178994
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2621793911
Short name T605
Test name
Test status
Simulation time 8850713889 ps
CPU time 50.8 seconds
Started Jul 06 06:29:40 PM PDT 24
Finished Jul 06 06:30:31 PM PDT 24
Peak memory 251056 kb
Host smart-4120b189-392d-441c-ac88-1437c29865fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621793911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2621793911
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1671939478
Short name T806
Test name
Test status
Simulation time 544053978 ps
CPU time 16.1 seconds
Started Jul 06 06:29:41 PM PDT 24
Finished Jul 06 06:29:57 PM PDT 24
Peak memory 250592 kb
Host smart-69912ad1-4454-4f93-be11-fa88f00285e4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671939478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1671939478
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3812210583
Short name T471
Test name
Test status
Simulation time 56417033 ps
CPU time 3.39 seconds
Started Jul 06 06:29:35 PM PDT 24
Finished Jul 06 06:29:39 PM PDT 24
Peak memory 218168 kb
Host smart-23c28ffd-58c4-400d-a775-fac52e853052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812210583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3812210583
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1798977498
Short name T643
Test name
Test status
Simulation time 743909810 ps
CPU time 19.52 seconds
Started Jul 06 06:29:46 PM PDT 24
Finished Jul 06 06:30:06 PM PDT 24
Peak memory 217780 kb
Host smart-50c81aa2-851e-4e93-ac61-a30e49d09703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798977498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1798977498
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3235307382
Short name T84
Test name
Test status
Simulation time 1530979822 ps
CPU time 26.27 seconds
Started Jul 06 06:29:48 PM PDT 24
Finished Jul 06 06:30:15 PM PDT 24
Peak memory 269612 kb
Host smart-7d0aa2a1-0c4a-4003-a951-8b271f0b834b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235307382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3235307382
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.2515088501
Short name T784
Test name
Test status
Simulation time 440535604 ps
CPU time 18.12 seconds
Started Jul 06 06:29:37 PM PDT 24
Finished Jul 06 06:29:56 PM PDT 24
Peak memory 218872 kb
Host smart-8a2dabae-312b-4fcc-800f-922ef71a55ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515088501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.2515088501
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1148938399
Short name T613
Test name
Test status
Simulation time 1518812746 ps
CPU time 16.67 seconds
Started Jul 06 06:29:37 PM PDT 24
Finished Jul 06 06:29:54 PM PDT 24
Peak memory 218232 kb
Host smart-d81e2815-2c8e-47e1-8652-8f30ca90eb38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148938399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1148938399
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.3310833000
Short name T642
Test name
Test status
Simulation time 1152215485 ps
CPU time 10.34 seconds
Started Jul 06 06:29:47 PM PDT 24
Finished Jul 06 06:29:57 PM PDT 24
Peak memory 226040 kb
Host smart-8dc5464a-10a0-492f-81b0-709a00ac6d29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310833000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.3
310833000
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.662319235
Short name T815
Test name
Test status
Simulation time 361374025 ps
CPU time 10.27 seconds
Started Jul 06 06:29:39 PM PDT 24
Finished Jul 06 06:29:50 PM PDT 24
Peak memory 217740 kb
Host smart-bcb44d3a-5bd7-4233-8482-0518eaa7b15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662319235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.662319235
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1299633707
Short name T568
Test name
Test status
Simulation time 591274973 ps
CPU time 26.64 seconds
Started Jul 06 06:29:50 PM PDT 24
Finished Jul 06 06:30:17 PM PDT 24
Peak memory 250940 kb
Host smart-ec73d6b8-5127-48c6-b629-156a82a4ea43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299633707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1299633707
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.1382419907
Short name T450
Test name
Test status
Simulation time 677814748 ps
CPU time 7.52 seconds
Started Jul 06 06:29:38 PM PDT 24
Finished Jul 06 06:29:46 PM PDT 24
Peak memory 250980 kb
Host smart-fcb34c81-29dc-443a-9431-d8204f77956b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382419907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.1382419907
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.320190842
Short name T841
Test name
Test status
Simulation time 25317377388 ps
CPU time 54.69 seconds
Started Jul 06 06:29:39 PM PDT 24
Finished Jul 06 06:30:34 PM PDT 24
Peak memory 269788 kb
Host smart-03f5cbf4-d1d5-485b-9eef-5406083ae8d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320190842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.320190842
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.2027910465
Short name T808
Test name
Test status
Simulation time 61752251177 ps
CPU time 568.51 seconds
Started Jul 06 06:30:00 PM PDT 24
Finished Jul 06 06:39:29 PM PDT 24
Peak memory 283932 kb
Host smart-9b47d0af-ac20-4afd-b370-2140a4155eca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2027910465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.2027910465
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1430519119
Short name T481
Test name
Test status
Simulation time 27234514 ps
CPU time 0.91 seconds
Started Jul 06 06:29:44 PM PDT 24
Finished Jul 06 06:29:45 PM PDT 24
Peak memory 213044 kb
Host smart-dec32879-d30b-4a58-95f5-8568bb3f8f69
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430519119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.1430519119
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.791128292
Short name T813
Test name
Test status
Simulation time 169250422 ps
CPU time 1.27 seconds
Started Jul 06 06:31:29 PM PDT 24
Finished Jul 06 06:31:31 PM PDT 24
Peak memory 209084 kb
Host smart-e248b55c-158b-4324-9f8f-7f53d3a4e8cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791128292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.791128292
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.1881645013
Short name T556
Test name
Test status
Simulation time 541386906 ps
CPU time 11.87 seconds
Started Jul 06 06:31:22 PM PDT 24
Finished Jul 06 06:31:35 PM PDT 24
Peak memory 225944 kb
Host smart-7676c9ea-0593-4e38-8903-8daa05305abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881645013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1881645013
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.815191666
Short name T367
Test name
Test status
Simulation time 282780185 ps
CPU time 4.12 seconds
Started Jul 06 06:31:24 PM PDT 24
Finished Jul 06 06:31:29 PM PDT 24
Peak memory 217276 kb
Host smart-5c64d382-94cb-4ff1-953d-da7c3ed0e077
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815191666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.815191666
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3502466034
Short name T353
Test name
Test status
Simulation time 859535258 ps
CPU time 3.25 seconds
Started Jul 06 06:31:26 PM PDT 24
Finished Jul 06 06:31:29 PM PDT 24
Peak memory 218208 kb
Host smart-d5b14d2a-34e9-4a06-b401-cbd533913a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502466034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3502466034
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1731992253
Short name T844
Test name
Test status
Simulation time 1561406997 ps
CPU time 13.3 seconds
Started Jul 06 06:31:27 PM PDT 24
Finished Jul 06 06:31:41 PM PDT 24
Peak memory 218848 kb
Host smart-42154406-e7a1-4ffb-bb91-6a36a7c53b31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731992253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1731992253
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1314439229
Short name T428
Test name
Test status
Simulation time 1030380502 ps
CPU time 7.68 seconds
Started Jul 06 06:31:22 PM PDT 24
Finished Jul 06 06:31:30 PM PDT 24
Peak memory 226016 kb
Host smart-e573c8b4-3300-49d9-a30c-5e3a37f0ce82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314439229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1314439229
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.459000826
Short name T737
Test name
Test status
Simulation time 611620089 ps
CPU time 7.71 seconds
Started Jul 06 06:31:26 PM PDT 24
Finished Jul 06 06:31:34 PM PDT 24
Peak memory 218236 kb
Host smart-5d191b4b-a1f3-423a-acca-777c02d4a8d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459000826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.459000826
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.3675374480
Short name T49
Test name
Test status
Simulation time 1086192800 ps
CPU time 7.58 seconds
Started Jul 06 06:31:25 PM PDT 24
Finished Jul 06 06:31:33 PM PDT 24
Peak memory 224824 kb
Host smart-f2582836-dd17-42d3-903a-d44846da80da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675374480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3675374480
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1022044828
Short name T719
Test name
Test status
Simulation time 360358082 ps
CPU time 5.69 seconds
Started Jul 06 06:31:26 PM PDT 24
Finished Jul 06 06:31:31 PM PDT 24
Peak memory 217736 kb
Host smart-98298dd0-a5bb-458c-8e43-6aaabd5f7176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022044828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1022044828
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3401915776
Short name T248
Test name
Test status
Simulation time 790731632 ps
CPU time 31.07 seconds
Started Jul 06 06:31:27 PM PDT 24
Finished Jul 06 06:31:59 PM PDT 24
Peak memory 250996 kb
Host smart-c3a9d2f7-8938-48b2-8f59-5b4c6b2885ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401915776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3401915776
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.1265124507
Short name T217
Test name
Test status
Simulation time 190044939 ps
CPU time 3.71 seconds
Started Jul 06 06:31:24 PM PDT 24
Finished Jul 06 06:31:28 PM PDT 24
Peak memory 222612 kb
Host smart-5baeb9c9-3ff1-41f8-8dbe-211777e5e629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265124507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.1265124507
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.2711695612
Short name T438
Test name
Test status
Simulation time 4875467255 ps
CPU time 53.33 seconds
Started Jul 06 06:31:25 PM PDT 24
Finished Jul 06 06:32:18 PM PDT 24
Peak memory 220284 kb
Host smart-2991ac77-2941-4483-aadd-9c313e777b2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711695612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.2711695612
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.4151052369
Short name T276
Test name
Test status
Simulation time 25356882 ps
CPU time 1 seconds
Started Jul 06 06:31:28 PM PDT 24
Finished Jul 06 06:31:30 PM PDT 24
Peak memory 212884 kb
Host smart-08e6f7f1-4a52-4139-b9b5-620ad9045d36
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151052369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.4151052369
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.999342550
Short name T69
Test name
Test status
Simulation time 61828018 ps
CPU time 0.91 seconds
Started Jul 06 06:31:32 PM PDT 24
Finished Jul 06 06:31:33 PM PDT 24
Peak memory 208912 kb
Host smart-129b9677-c2cf-4bde-b6cb-6020513174f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999342550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.999342550
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.916131746
Short name T552
Test name
Test status
Simulation time 643268861 ps
CPU time 10.54 seconds
Started Jul 06 06:31:28 PM PDT 24
Finished Jul 06 06:31:39 PM PDT 24
Peak memory 218228 kb
Host smart-5cdef470-8fd9-4a07-877d-197867fd6ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916131746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.916131746
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.1456435817
Short name T30
Test name
Test status
Simulation time 441483435 ps
CPU time 5.3 seconds
Started Jul 06 06:31:27 PM PDT 24
Finished Jul 06 06:31:33 PM PDT 24
Peak memory 217252 kb
Host smart-a65d63aa-6224-444a-bcdc-e64d30feb0c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456435817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.1456435817
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.415331213
Short name T712
Test name
Test status
Simulation time 69162203 ps
CPU time 1.52 seconds
Started Jul 06 06:31:29 PM PDT 24
Finished Jul 06 06:31:31 PM PDT 24
Peak memory 218208 kb
Host smart-6c88bfb4-fde4-441d-943e-ead8dd483cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415331213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.415331213
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.1686423453
Short name T547
Test name
Test status
Simulation time 3270896093 ps
CPU time 12.15 seconds
Started Jul 06 06:31:31 PM PDT 24
Finished Jul 06 06:31:43 PM PDT 24
Peak memory 226052 kb
Host smart-95c2bc9d-36d9-400a-b0b6-997fe000826c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686423453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.1686423453
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.1642533245
Short name T20
Test name
Test status
Simulation time 1177527862 ps
CPU time 9.5 seconds
Started Jul 06 06:31:38 PM PDT 24
Finished Jul 06 06:31:48 PM PDT 24
Peak memory 218196 kb
Host smart-8c80f094-0638-44cd-83a2-1c4a5a4cf4bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642533245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
1642533245
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.1144400774
Short name T512
Test name
Test status
Simulation time 375719512 ps
CPU time 9.93 seconds
Started Jul 06 06:31:40 PM PDT 24
Finished Jul 06 06:31:51 PM PDT 24
Peak memory 225200 kb
Host smart-6e80a622-9da2-4481-bc70-9bc7c6c41f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144400774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.1144400774
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.3476493468
Short name T558
Test name
Test status
Simulation time 70483462 ps
CPU time 2.18 seconds
Started Jul 06 06:31:28 PM PDT 24
Finished Jul 06 06:31:31 PM PDT 24
Peak memory 217728 kb
Host smart-e160b5c1-d973-4f0d-99da-63abb30721bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476493468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.3476493468
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.656710420
Short name T99
Test name
Test status
Simulation time 327485757 ps
CPU time 33.24 seconds
Started Jul 06 06:31:32 PM PDT 24
Finished Jul 06 06:32:05 PM PDT 24
Peak memory 251024 kb
Host smart-8c575b1f-dffb-41b8-9c5e-0537bf5c26ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656710420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.656710420
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.1880644630
Short name T639
Test name
Test status
Simulation time 117033686 ps
CPU time 3.8 seconds
Started Jul 06 06:31:29 PM PDT 24
Finished Jul 06 06:31:33 PM PDT 24
Peak memory 222708 kb
Host smart-cd32a1fa-f68a-4a22-a0ca-d68fc0a2496b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880644630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.1880644630
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.469125317
Short name T479
Test name
Test status
Simulation time 8625531081 ps
CPU time 300.61 seconds
Started Jul 06 06:31:28 PM PDT 24
Finished Jul 06 06:36:29 PM PDT 24
Peak memory 316540 kb
Host smart-67afc783-ddd7-4bd7-9eb4-beca721ee70f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469125317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.469125317
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.286674907
Short name T723
Test name
Test status
Simulation time 41477900674 ps
CPU time 890.1 seconds
Started Jul 06 06:31:30 PM PDT 24
Finished Jul 06 06:46:21 PM PDT 24
Peak memory 284052 kb
Host smart-812a3f4c-1d85-4833-9626-5af70f1a8f41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=286674907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.286674907
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1591175277
Short name T762
Test name
Test status
Simulation time 14150487 ps
CPU time 1.1 seconds
Started Jul 06 06:31:32 PM PDT 24
Finished Jul 06 06:31:33 PM PDT 24
Peak memory 211792 kb
Host smart-1e8a3fc4-3d0a-47a9-822b-8d33702551dc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591175277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1591175277
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.2352670541
Short name T824
Test name
Test status
Simulation time 20761632 ps
CPU time 1.14 seconds
Started Jul 06 06:31:32 PM PDT 24
Finished Jul 06 06:31:34 PM PDT 24
Peak memory 208956 kb
Host smart-37a75f7e-5c95-40e9-ac00-30bec063a5d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352670541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.2352670541
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3052397804
Short name T39
Test name
Test status
Simulation time 1201391561 ps
CPU time 14.88 seconds
Started Jul 06 06:31:31 PM PDT 24
Finished Jul 06 06:31:46 PM PDT 24
Peak memory 218044 kb
Host smart-adcea432-5c00-453c-a164-95e249042215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052397804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3052397804
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.1918870353
Short name T705
Test name
Test status
Simulation time 967349142 ps
CPU time 4.84 seconds
Started Jul 06 06:31:27 PM PDT 24
Finished Jul 06 06:31:32 PM PDT 24
Peak memory 217348 kb
Host smart-5d29f55f-abe0-4beb-98b8-e3dcd54471a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918870353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.1918870353
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.1830072098
Short name T703
Test name
Test status
Simulation time 118045736 ps
CPU time 3.62 seconds
Started Jul 06 06:31:29 PM PDT 24
Finished Jul 06 06:31:33 PM PDT 24
Peak memory 222696 kb
Host smart-4cdc9443-b525-447d-a99e-c8c8cc20bd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830072098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1830072098
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.1637424318
Short name T800
Test name
Test status
Simulation time 1386236438 ps
CPU time 13.5 seconds
Started Jul 06 06:31:31 PM PDT 24
Finished Jul 06 06:31:45 PM PDT 24
Peak memory 219960 kb
Host smart-16daee31-6165-426d-b42b-4439b1d508fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637424318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1637424318
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2501518757
Short name T682
Test name
Test status
Simulation time 1612421581 ps
CPU time 10.36 seconds
Started Jul 06 06:31:30 PM PDT 24
Finished Jul 06 06:31:40 PM PDT 24
Peak memory 225996 kb
Host smart-1157ad80-bab8-485c-8946-b09fe445af03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501518757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2501518757
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.644770
Short name T375
Test name
Test status
Simulation time 1449701769 ps
CPU time 12.99 seconds
Started Jul 06 06:31:32 PM PDT 24
Finished Jul 06 06:31:45 PM PDT 24
Peak memory 218208 kb
Host smart-09ea835f-6107-40b5-84a4-d0c5a290eabe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.644770
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.138059120
Short name T814
Test name
Test status
Simulation time 662989324 ps
CPU time 12.29 seconds
Started Jul 06 06:31:28 PM PDT 24
Finished Jul 06 06:31:41 PM PDT 24
Peak memory 218372 kb
Host smart-47d8390e-1075-4f44-a7f5-0f72f8574240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138059120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.138059120
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.695499201
Short name T630
Test name
Test status
Simulation time 114117644 ps
CPU time 3.76 seconds
Started Jul 06 06:31:30 PM PDT 24
Finished Jul 06 06:31:34 PM PDT 24
Peak memory 217692 kb
Host smart-2e951af9-9f8e-41d9-adfb-74d3be6a4c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695499201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.695499201
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.2844080923
Short name T583
Test name
Test status
Simulation time 3772168277 ps
CPU time 31.1 seconds
Started Jul 06 06:31:32 PM PDT 24
Finished Jul 06 06:32:03 PM PDT 24
Peak memory 250980 kb
Host smart-e1d80b32-0b84-42df-a8b0-96566c567247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844080923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.2844080923
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.4238013771
Short name T95
Test name
Test status
Simulation time 909695335 ps
CPU time 7.36 seconds
Started Jul 06 06:31:30 PM PDT 24
Finished Jul 06 06:31:38 PM PDT 24
Peak memory 250464 kb
Host smart-afcf7a8a-a454-4b5d-8005-f08ae5bd9639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238013771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.4238013771
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.2153166157
Short name T434
Test name
Test status
Simulation time 3545111213 ps
CPU time 143.12 seconds
Started Jul 06 06:31:31 PM PDT 24
Finished Jul 06 06:33:55 PM PDT 24
Peak memory 283380 kb
Host smart-83e6e064-84ad-4718-ade0-d9ba2014a6cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153166157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.2153166157
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2278322987
Short name T327
Test name
Test status
Simulation time 37974958 ps
CPU time 0.82 seconds
Started Jul 06 06:31:30 PM PDT 24
Finished Jul 06 06:31:31 PM PDT 24
Peak memory 211884 kb
Host smart-f40d9e71-0489-436b-be66-ddac084da4d7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278322987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2278322987
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.1942427600
Short name T564
Test name
Test status
Simulation time 38279908 ps
CPU time 0.91 seconds
Started Jul 06 06:31:33 PM PDT 24
Finished Jul 06 06:31:34 PM PDT 24
Peak memory 208936 kb
Host smart-bdedf997-8afc-43fd-abab-e905e3de1336
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942427600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.1942427600
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.4133577609
Short name T830
Test name
Test status
Simulation time 216617604 ps
CPU time 11.49 seconds
Started Jul 06 06:31:35 PM PDT 24
Finished Jul 06 06:31:46 PM PDT 24
Peak memory 218184 kb
Host smart-6ceda51d-695b-4e55-84df-8b1b98a283d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133577609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.4133577609
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3045659074
Short name T531
Test name
Test status
Simulation time 174949431 ps
CPU time 2.22 seconds
Started Jul 06 06:31:34 PM PDT 24
Finished Jul 06 06:31:36 PM PDT 24
Peak memory 217048 kb
Host smart-7e133a51-a28e-46e7-9474-7224326b531e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045659074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.3045659074
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.1477576033
Short name T383
Test name
Test status
Simulation time 133780783 ps
CPU time 1.97 seconds
Started Jul 06 06:31:33 PM PDT 24
Finished Jul 06 06:31:36 PM PDT 24
Peak memory 218236 kb
Host smart-44ec8655-f199-4e50-8554-657080090023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477576033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1477576033
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.2326854219
Short name T856
Test name
Test status
Simulation time 294974123 ps
CPU time 15.44 seconds
Started Jul 06 06:31:33 PM PDT 24
Finished Jul 06 06:31:49 PM PDT 24
Peak memory 226080 kb
Host smart-3a6d773f-31f2-43e0-8237-e3e60cfb18f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326854219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2326854219
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2020132531
Short name T706
Test name
Test status
Simulation time 228112265 ps
CPU time 11.13 seconds
Started Jul 06 06:31:36 PM PDT 24
Finished Jul 06 06:31:48 PM PDT 24
Peak memory 226000 kb
Host smart-71c456e0-5327-4883-bc74-e0eda2256683
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020132531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.2020132531
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2331144689
Short name T231
Test name
Test status
Simulation time 2484534873 ps
CPU time 17.23 seconds
Started Jul 06 06:31:35 PM PDT 24
Finished Jul 06 06:31:53 PM PDT 24
Peak memory 218256 kb
Host smart-171d4682-7df6-449a-8c3d-041a666438f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331144689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2331144689
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2983749348
Short name T336
Test name
Test status
Simulation time 320412674 ps
CPU time 13.25 seconds
Started Jul 06 06:31:47 PM PDT 24
Finished Jul 06 06:32:01 PM PDT 24
Peak memory 226056 kb
Host smart-f4d3df1a-db83-402f-87e4-eaa690809292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983749348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2983749348
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.486782193
Short name T490
Test name
Test status
Simulation time 22307894 ps
CPU time 1.82 seconds
Started Jul 06 06:31:34 PM PDT 24
Finished Jul 06 06:31:36 PM PDT 24
Peak memory 223544 kb
Host smart-4742be3f-d677-4009-9cd3-5920d4703b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486782193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.486782193
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.2136307061
Short name T87
Test name
Test status
Simulation time 645795162 ps
CPU time 22.76 seconds
Started Jul 06 06:31:37 PM PDT 24
Finished Jul 06 06:32:00 PM PDT 24
Peak memory 250988 kb
Host smart-2b275e37-8193-4768-a103-ca1fe767766e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136307061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.2136307061
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.3227188472
Short name T409
Test name
Test status
Simulation time 335944336 ps
CPU time 3.58 seconds
Started Jul 06 06:31:33 PM PDT 24
Finished Jul 06 06:31:37 PM PDT 24
Peak memory 222608 kb
Host smart-4946f957-3c84-4346-95da-ce63fbdef01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227188472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3227188472
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.818370355
Short name T108
Test name
Test status
Simulation time 12346660739 ps
CPU time 74.47 seconds
Started Jul 06 06:31:36 PM PDT 24
Finished Jul 06 06:32:51 PM PDT 24
Peak memory 280880 kb
Host smart-f754d1fa-6d90-4367-9322-201fbc7c0774
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818370355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.818370355
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.2416855757
Short name T147
Test name
Test status
Simulation time 44904515724 ps
CPU time 250.82 seconds
Started Jul 06 06:31:33 PM PDT 24
Finished Jul 06 06:35:44 PM PDT 24
Peak memory 234452 kb
Host smart-a65467cd-bedd-4ced-b798-2430dd44d20b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2416855757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.2416855757
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1410650515
Short name T374
Test name
Test status
Simulation time 32343435 ps
CPU time 0.92 seconds
Started Jul 06 06:31:33 PM PDT 24
Finished Jul 06 06:31:35 PM PDT 24
Peak memory 211884 kb
Host smart-23ca80ca-cb92-4d42-a012-d17982fd7e27
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410650515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1410650515
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1436629684
Short name T533
Test name
Test status
Simulation time 37250684 ps
CPU time 0.9 seconds
Started Jul 06 06:31:37 PM PDT 24
Finished Jul 06 06:31:39 PM PDT 24
Peak memory 208972 kb
Host smart-f279fb51-bf67-45ee-bff2-b5981567f73b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436629684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1436629684
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.3919241655
Short name T748
Test name
Test status
Simulation time 3939803782 ps
CPU time 17.14 seconds
Started Jul 06 06:31:33 PM PDT 24
Finished Jul 06 06:31:51 PM PDT 24
Peak memory 218228 kb
Host smart-949b45b6-45cf-4258-b6cd-d51a53a02be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919241655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.3919241655
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.1998631617
Short name T540
Test name
Test status
Simulation time 326855331 ps
CPU time 2.91 seconds
Started Jul 06 06:31:35 PM PDT 24
Finished Jul 06 06:31:39 PM PDT 24
Peak memory 218244 kb
Host smart-c888bf4d-9c61-4511-8407-ae8bfdf5f702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998631617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1998631617
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.3286183805
Short name T671
Test name
Test status
Simulation time 333676694 ps
CPU time 17.46 seconds
Started Jul 06 06:31:37 PM PDT 24
Finished Jul 06 06:31:55 PM PDT 24
Peak memory 226056 kb
Host smart-72cff369-4f58-46cb-8b79-cb7d76a6a9e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286183805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3286183805
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.1748053703
Short name T796
Test name
Test status
Simulation time 481653263 ps
CPU time 9.63 seconds
Started Jul 06 06:31:34 PM PDT 24
Finished Jul 06 06:31:44 PM PDT 24
Peak memory 226028 kb
Host smart-49b470cd-fc25-46e1-a5ad-16e338ea8440
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748053703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.1748053703
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.167303678
Short name T524
Test name
Test status
Simulation time 426704725 ps
CPU time 7.22 seconds
Started Jul 06 06:31:39 PM PDT 24
Finished Jul 06 06:31:46 PM PDT 24
Peak memory 218184 kb
Host smart-fb9cdd06-3062-403c-a3f8-1a1759495717
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167303678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.167303678
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.681086746
Short name T755
Test name
Test status
Simulation time 307334936 ps
CPU time 12.05 seconds
Started Jul 06 06:31:34 PM PDT 24
Finished Jul 06 06:31:46 PM PDT 24
Peak memory 226036 kb
Host smart-e5ab7e1f-1419-4b4d-820b-2d7096f4ab4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681086746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.681086746
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.4117658745
Short name T523
Test name
Test status
Simulation time 331072293 ps
CPU time 3.27 seconds
Started Jul 06 06:31:34 PM PDT 24
Finished Jul 06 06:31:38 PM PDT 24
Peak memory 217688 kb
Host smart-e5642367-d7df-458d-aa00-95655159f7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117658745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.4117658745
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.1179986466
Short name T649
Test name
Test status
Simulation time 1600766189 ps
CPU time 20.76 seconds
Started Jul 06 06:31:34 PM PDT 24
Finished Jul 06 06:31:55 PM PDT 24
Peak memory 251016 kb
Host smart-8d849dbf-0ad4-410e-97b5-866b75971687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179986466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.1179986466
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3620882232
Short name T461
Test name
Test status
Simulation time 282838002 ps
CPU time 7.52 seconds
Started Jul 06 06:31:32 PM PDT 24
Finished Jul 06 06:31:40 PM PDT 24
Peak memory 247304 kb
Host smart-fd86df28-8999-4a09-82fd-effd687cef41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620882232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3620882232
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2444344160
Short name T255
Test name
Test status
Simulation time 60902433626 ps
CPU time 503.53 seconds
Started Jul 06 06:31:37 PM PDT 24
Finished Jul 06 06:40:01 PM PDT 24
Peak memory 268268 kb
Host smart-1c9f03b8-e238-4825-be3e-a1509ab02098
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444344160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2444344160
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2906090157
Short name T663
Test name
Test status
Simulation time 47658882 ps
CPU time 0.88 seconds
Started Jul 06 06:31:34 PM PDT 24
Finished Jul 06 06:31:35 PM PDT 24
Peak memory 211972 kb
Host smart-f5eb283a-88c0-4573-b000-c0e5ad1266ec
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906090157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.2906090157
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.3193048580
Short name T786
Test name
Test status
Simulation time 491615703 ps
CPU time 14.76 seconds
Started Jul 06 06:31:39 PM PDT 24
Finished Jul 06 06:31:54 PM PDT 24
Peak memory 218236 kb
Host smart-6b46fd10-7c04-4b83-bda4-9cad955512f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193048580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.3193048580
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.1506831348
Short name T352
Test name
Test status
Simulation time 1344843908 ps
CPU time 17.45 seconds
Started Jul 06 06:31:40 PM PDT 24
Finished Jul 06 06:31:57 PM PDT 24
Peak memory 217528 kb
Host smart-a963dd96-2a13-45ad-bc3b-dcb6f34bd905
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506831348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.1506831348
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.915878497
Short name T577
Test name
Test status
Simulation time 265324211 ps
CPU time 1.7 seconds
Started Jul 06 06:31:39 PM PDT 24
Finished Jul 06 06:31:40 PM PDT 24
Peak memory 218324 kb
Host smart-18ee77af-a431-431e-9856-cf102ffb2691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915878497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.915878497
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.851911605
Short name T403
Test name
Test status
Simulation time 259235447 ps
CPU time 10.75 seconds
Started Jul 06 06:31:37 PM PDT 24
Finished Jul 06 06:31:49 PM PDT 24
Peak memory 218160 kb
Host smart-ab5f0508-ed11-43f8-9ecd-53651a254c6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851911605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.851911605
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3497443443
Short name T338
Test name
Test status
Simulation time 3471066851 ps
CPU time 17.61 seconds
Started Jul 06 06:31:37 PM PDT 24
Finished Jul 06 06:31:55 PM PDT 24
Peak memory 226120 kb
Host smart-3ef22192-7439-4d4e-be8c-9f25c14c60f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497443443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3497443443
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2026380796
Short name T789
Test name
Test status
Simulation time 352315438 ps
CPU time 8.91 seconds
Started Jul 06 06:31:38 PM PDT 24
Finished Jul 06 06:31:48 PM PDT 24
Peak memory 218248 kb
Host smart-d2d6374f-38cc-4b41-a769-e061ca764c80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026380796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
2026380796
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.640944812
Short name T783
Test name
Test status
Simulation time 5009607998 ps
CPU time 6.85 seconds
Started Jul 06 06:31:38 PM PDT 24
Finished Jul 06 06:31:45 PM PDT 24
Peak memory 225200 kb
Host smart-03691961-da5d-4468-a440-c5e44bbeea48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640944812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.640944812
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.74285350
Short name T287
Test name
Test status
Simulation time 143721071 ps
CPU time 2.41 seconds
Started Jul 06 06:31:38 PM PDT 24
Finished Jul 06 06:31:40 PM PDT 24
Peak memory 217788 kb
Host smart-49d75274-88a6-406d-ba72-d60206059975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74285350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.74285350
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1937285331
Short name T543
Test name
Test status
Simulation time 311967434 ps
CPU time 32.2 seconds
Started Jul 06 06:31:36 PM PDT 24
Finished Jul 06 06:32:09 PM PDT 24
Peak memory 247844 kb
Host smart-2f51131d-79c4-4880-a28a-d7f4337e6397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937285331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1937285331
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2250629749
Short name T223
Test name
Test status
Simulation time 43045978 ps
CPU time 6.03 seconds
Started Jul 06 06:31:37 PM PDT 24
Finished Jul 06 06:31:44 PM PDT 24
Peak memory 246620 kb
Host smart-8da8f2da-60d5-43ba-9a06-a19205e2bf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250629749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2250629749
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.3909442699
Short name T843
Test name
Test status
Simulation time 3172686377 ps
CPU time 96.79 seconds
Started Jul 06 06:31:37 PM PDT 24
Finished Jul 06 06:33:14 PM PDT 24
Peak memory 274316 kb
Host smart-06275486-9c28-4ee7-90ae-823fd29bc7b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909442699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.3909442699
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.2225200748
Short name T80
Test name
Test status
Simulation time 40087354663 ps
CPU time 378.67 seconds
Started Jul 06 06:31:42 PM PDT 24
Finished Jul 06 06:38:01 PM PDT 24
Peak memory 283804 kb
Host smart-db3a6510-6f99-4d29-85f6-b9d4ab416d12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2225200748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.2225200748
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1841968669
Short name T536
Test name
Test status
Simulation time 17186944 ps
CPU time 0.94 seconds
Started Jul 06 06:31:47 PM PDT 24
Finished Jul 06 06:31:48 PM PDT 24
Peak memory 211960 kb
Host smart-f138e13a-5e2e-4753-a472-90e6bde64d11
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841968669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1841968669
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3169411429
Short name T282
Test name
Test status
Simulation time 65603573 ps
CPU time 1.18 seconds
Started Jul 06 06:31:45 PM PDT 24
Finished Jul 06 06:31:46 PM PDT 24
Peak memory 208988 kb
Host smart-70a815ce-e937-4281-ab0d-6634dbd03337
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169411429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3169411429
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.1530451184
Short name T697
Test name
Test status
Simulation time 3415668019 ps
CPU time 20.6 seconds
Started Jul 06 06:31:45 PM PDT 24
Finished Jul 06 06:32:06 PM PDT 24
Peak memory 218908 kb
Host smart-4d8caa2a-fba8-4b9b-b8c0-965d511462f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530451184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1530451184
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.2085021460
Short name T177
Test name
Test status
Simulation time 2435291049 ps
CPU time 7.35 seconds
Started Jul 06 06:31:39 PM PDT 24
Finished Jul 06 06:31:46 PM PDT 24
Peak memory 217564 kb
Host smart-1e192db1-3f3b-469f-82b5-1da32b9b0e1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085021460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.2085021460
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.292868087
Short name T424
Test name
Test status
Simulation time 79472972 ps
CPU time 3.07 seconds
Started Jul 06 06:31:40 PM PDT 24
Finished Jul 06 06:31:44 PM PDT 24
Peak memory 218352 kb
Host smart-dc558ef1-a6fd-4a4f-a67e-19c01c996946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292868087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.292868087
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.1775022658
Short name T672
Test name
Test status
Simulation time 454510239 ps
CPU time 10.64 seconds
Started Jul 06 06:31:39 PM PDT 24
Finished Jul 06 06:31:50 PM PDT 24
Peak memory 226072 kb
Host smart-6bc92e3d-532d-4018-be87-91d00ba36fda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775022658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1775022658
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1566595549
Short name T508
Test name
Test status
Simulation time 9576743122 ps
CPU time 23.06 seconds
Started Jul 06 06:31:40 PM PDT 24
Finished Jul 06 06:32:03 PM PDT 24
Peak memory 226116 kb
Host smart-8d31f833-23b5-4980-aced-a5ec2a212fb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566595549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.1566595549
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.2603960919
Short name T325
Test name
Test status
Simulation time 829405343 ps
CPU time 6.12 seconds
Started Jul 06 06:31:37 PM PDT 24
Finished Jul 06 06:31:44 PM PDT 24
Peak memory 218260 kb
Host smart-0d3b5b56-18c3-4425-aa82-bea3afd1ef97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603960919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
2603960919
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.179424427
Short name T348
Test name
Test status
Simulation time 845846449 ps
CPU time 14.81 seconds
Started Jul 06 06:31:39 PM PDT 24
Finished Jul 06 06:31:54 PM PDT 24
Peak memory 226032 kb
Host smart-9063bc95-0f34-42cc-9f67-3ebda9282387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179424427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.179424427
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.4068869984
Short name T278
Test name
Test status
Simulation time 53136917 ps
CPU time 2.07 seconds
Started Jul 06 06:31:46 PM PDT 24
Finished Jul 06 06:31:49 PM PDT 24
Peak memory 217680 kb
Host smart-901a9f14-d4fd-414e-91e6-1a74820e6531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068869984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.4068869984
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.994590791
Short name T93
Test name
Test status
Simulation time 193409388 ps
CPU time 23.45 seconds
Started Jul 06 06:31:41 PM PDT 24
Finished Jul 06 06:32:05 PM PDT 24
Peak memory 250952 kb
Host smart-1d525a39-5f85-490a-bce9-90dd23bb0bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994590791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.994590791
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.4196585940
Short name T648
Test name
Test status
Simulation time 74675671 ps
CPU time 7.08 seconds
Started Jul 06 06:31:46 PM PDT 24
Finished Jul 06 06:31:54 PM PDT 24
Peak memory 250932 kb
Host smart-b85c5c38-ba14-4756-9094-fabf6965acc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196585940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.4196585940
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.2926407395
Short name T166
Test name
Test status
Simulation time 68692493689 ps
CPU time 498.22 seconds
Started Jul 06 06:31:43 PM PDT 24
Finished Jul 06 06:40:01 PM PDT 24
Peak memory 251012 kb
Host smart-03ee3350-4475-4c53-adc3-772ef723a78f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926407395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.2926407395
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2875522218
Short name T392
Test name
Test status
Simulation time 36303161 ps
CPU time 0.94 seconds
Started Jul 06 06:31:40 PM PDT 24
Finished Jul 06 06:31:42 PM PDT 24
Peak memory 211920 kb
Host smart-6078220a-6fa8-40e8-9037-6b8934ef48ea
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875522218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.2875522218
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.1130288697
Short name T550
Test name
Test status
Simulation time 33958145 ps
CPU time 0.97 seconds
Started Jul 06 06:31:43 PM PDT 24
Finished Jul 06 06:31:44 PM PDT 24
Peak memory 208984 kb
Host smart-7d291879-f8c5-45f1-8274-83e4b0b30ac8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130288697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1130288697
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.3251372221
Short name T518
Test name
Test status
Simulation time 1576184291 ps
CPU time 11.07 seconds
Started Jul 06 06:31:41 PM PDT 24
Finished Jul 06 06:31:52 PM PDT 24
Peak memory 218176 kb
Host smart-ca2da29f-f9c7-4cd6-a6f5-c33fce6dc868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251372221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.3251372221
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.275980677
Short name T178
Test name
Test status
Simulation time 91914325 ps
CPU time 1.8 seconds
Started Jul 06 06:31:43 PM PDT 24
Finished Jul 06 06:31:45 PM PDT 24
Peak memory 217200 kb
Host smart-74ac503b-ae33-4d9b-ad78-09cc8956ef3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275980677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.275980677
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2677361592
Short name T503
Test name
Test status
Simulation time 136811101 ps
CPU time 1.96 seconds
Started Jul 06 06:31:40 PM PDT 24
Finished Jul 06 06:31:43 PM PDT 24
Peak memory 218208 kb
Host smart-0901b4db-df31-46fd-85fd-64583c5d93c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677361592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2677361592
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.2044574840
Short name T486
Test name
Test status
Simulation time 5557240994 ps
CPU time 9.91 seconds
Started Jul 06 06:31:40 PM PDT 24
Finished Jul 06 06:31:51 PM PDT 24
Peak memory 226096 kb
Host smart-1d595196-41f0-4f32-a3ee-b59590d8bf1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044574840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.2044574840
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1580108759
Short name T236
Test name
Test status
Simulation time 413264857 ps
CPU time 9.04 seconds
Started Jul 06 06:31:47 PM PDT 24
Finished Jul 06 06:31:57 PM PDT 24
Peak memory 225976 kb
Host smart-72d2e064-10ef-4d1e-98d3-2343f437c226
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580108759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1580108759
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.890128624
Short name T809
Test name
Test status
Simulation time 1047597296 ps
CPU time 7.34 seconds
Started Jul 06 06:31:40 PM PDT 24
Finished Jul 06 06:31:48 PM PDT 24
Peak memory 218248 kb
Host smart-3ba0aaf1-6dd5-4b4a-a845-4174733e1bf0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890128624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.890128624
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.4211078797
Short name T274
Test name
Test status
Simulation time 1222372437 ps
CPU time 11.18 seconds
Started Jul 06 06:31:57 PM PDT 24
Finished Jul 06 06:32:09 PM PDT 24
Peak memory 218244 kb
Host smart-fbf0d5e3-f9d2-4706-931d-ecc28cf1450a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211078797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.4211078797
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2617680120
Short name T427
Test name
Test status
Simulation time 74783496 ps
CPU time 1.33 seconds
Started Jul 06 06:31:58 PM PDT 24
Finished Jul 06 06:31:59 PM PDT 24
Peak memory 213648 kb
Host smart-b6aac900-a2c8-4de3-915d-7983158fe854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617680120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2617680120
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.2330439850
Short name T397
Test name
Test status
Simulation time 507306975 ps
CPU time 30.04 seconds
Started Jul 06 06:31:42 PM PDT 24
Finished Jul 06 06:32:12 PM PDT 24
Peak memory 251016 kb
Host smart-8a84e2ed-b4f3-4370-b06d-34d3d446f5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330439850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.2330439850
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3793446215
Short name T252
Test name
Test status
Simulation time 76792662 ps
CPU time 3.19 seconds
Started Jul 06 06:31:43 PM PDT 24
Finished Jul 06 06:31:47 PM PDT 24
Peak memory 222452 kb
Host smart-a27d7f63-69af-4c0b-81eb-8e99405b876e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793446215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3793446215
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.1568972141
Short name T63
Test name
Test status
Simulation time 15646189512 ps
CPU time 87.61 seconds
Started Jul 06 06:31:41 PM PDT 24
Finished Jul 06 06:33:09 PM PDT 24
Peak memory 282128 kb
Host smart-ee443d25-8a5c-4ded-91eb-7579c1d17e98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568972141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.1568972141
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2590575909
Short name T759
Test name
Test status
Simulation time 140831792 ps
CPU time 0.79 seconds
Started Jul 06 06:31:43 PM PDT 24
Finished Jul 06 06:31:44 PM PDT 24
Peak memory 211864 kb
Host smart-158d9665-c266-4894-a781-74614170dc41
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590575909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2590575909
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.4038533662
Short name T707
Test name
Test status
Simulation time 22460108 ps
CPU time 1.19 seconds
Started Jul 06 06:31:45 PM PDT 24
Finished Jul 06 06:31:47 PM PDT 24
Peak memory 208972 kb
Host smart-b1305331-c904-402e-b696-72b70250bfe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038533662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.4038533662
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.462083800
Short name T318
Test name
Test status
Simulation time 686564423 ps
CPU time 12.15 seconds
Started Jul 06 06:31:41 PM PDT 24
Finished Jul 06 06:31:53 PM PDT 24
Peak memory 218160 kb
Host smart-653431a9-2f8d-4082-8817-06d2e5454b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462083800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.462083800
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.1687583726
Short name T456
Test name
Test status
Simulation time 610375509 ps
CPU time 2.61 seconds
Started Jul 06 06:31:41 PM PDT 24
Finished Jul 06 06:31:44 PM PDT 24
Peak memory 217148 kb
Host smart-90dff803-da78-4641-970c-9e7f2ce5f07c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687583726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.1687583726
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.1727635928
Short name T306
Test name
Test status
Simulation time 230477369 ps
CPU time 2.38 seconds
Started Jul 06 06:31:47 PM PDT 24
Finished Jul 06 06:31:50 PM PDT 24
Peak memory 218156 kb
Host smart-92977a00-9ea0-4230-bb20-055b10e508c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727635928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.1727635928
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.2487850799
Short name T215
Test name
Test status
Simulation time 390055040 ps
CPU time 15.16 seconds
Started Jul 06 06:31:47 PM PDT 24
Finished Jul 06 06:32:03 PM PDT 24
Peak memory 225976 kb
Host smart-bb8e4469-4cb9-4d45-b32f-1f06683b1aef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487850799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.2487850799
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.4289269834
Short name T385
Test name
Test status
Simulation time 261235693 ps
CPU time 10.11 seconds
Started Jul 06 06:31:55 PM PDT 24
Finished Jul 06 06:32:06 PM PDT 24
Peak memory 218164 kb
Host smart-071999ac-a4db-4787-a69e-a5ce2e536ae9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289269834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
4289269834
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.944225216
Short name T402
Test name
Test status
Simulation time 609560244 ps
CPU time 11.98 seconds
Started Jul 06 06:31:41 PM PDT 24
Finished Jul 06 06:31:54 PM PDT 24
Peak memory 226060 kb
Host smart-1dbb2728-12f1-4b8c-a453-475cdf27bd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944225216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.944225216
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.470968580
Short name T73
Test name
Test status
Simulation time 68546715 ps
CPU time 2.75 seconds
Started Jul 06 06:31:43 PM PDT 24
Finished Jul 06 06:31:45 PM PDT 24
Peak memory 214664 kb
Host smart-5145bd42-caa1-4a85-a1cc-b55be13ee7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470968580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.470968580
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1226085511
Short name T535
Test name
Test status
Simulation time 1609723162 ps
CPU time 22.46 seconds
Started Jul 06 06:31:43 PM PDT 24
Finished Jul 06 06:32:06 PM PDT 24
Peak memory 250960 kb
Host smart-6faf54c6-93e3-484a-b043-1faa568babd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226085511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1226085511
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.499312005
Short name T702
Test name
Test status
Simulation time 196376660 ps
CPU time 6.58 seconds
Started Jul 06 06:31:40 PM PDT 24
Finished Jul 06 06:31:47 PM PDT 24
Peak memory 251004 kb
Host smart-11eb25b9-24ae-45b7-811f-3bd32215d5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499312005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.499312005
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.2275428441
Short name T599
Test name
Test status
Simulation time 21474041511 ps
CPU time 202.52 seconds
Started Jul 06 06:31:41 PM PDT 24
Finished Jul 06 06:35:04 PM PDT 24
Peak memory 251072 kb
Host smart-7beb4791-a2a9-4bf2-b2bf-43db5689594d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275428441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.2275428441
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3266843237
Short name T290
Test name
Test status
Simulation time 27977721 ps
CPU time 0.91 seconds
Started Jul 06 06:31:55 PM PDT 24
Finished Jul 06 06:31:57 PM PDT 24
Peak memory 217660 kb
Host smart-6fb3ce8d-efaf-4832-ae5d-5619664b51e5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266843237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3266843237
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.1170546110
Short name T569
Test name
Test status
Simulation time 88964376 ps
CPU time 1.2 seconds
Started Jul 06 06:31:46 PM PDT 24
Finished Jul 06 06:31:48 PM PDT 24
Peak memory 209140 kb
Host smart-c887ef1f-3677-46fa-8ad2-45b18f86d161
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170546110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.1170546110
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2352120348
Short name T571
Test name
Test status
Simulation time 892259996 ps
CPU time 10.9 seconds
Started Jul 06 06:31:49 PM PDT 24
Finished Jul 06 06:32:00 PM PDT 24
Peak memory 226052 kb
Host smart-4a83edab-a0cd-43ce-91c0-8fdd40bcf4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352120348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2352120348
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1584552257
Short name T370
Test name
Test status
Simulation time 2753859944 ps
CPU time 7.58 seconds
Started Jul 06 06:31:47 PM PDT 24
Finished Jul 06 06:31:56 PM PDT 24
Peak memory 217788 kb
Host smart-ac4bd637-ad0d-4cb9-ac66-906549ea97f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584552257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.1584552257
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.4250724839
Short name T562
Test name
Test status
Simulation time 209821488 ps
CPU time 2.03 seconds
Started Jul 06 06:31:46 PM PDT 24
Finished Jul 06 06:31:49 PM PDT 24
Peak memory 218088 kb
Host smart-12836e0b-8e54-4c25-b8a4-2a7f7652af4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250724839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.4250724839
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.2196441204
Short name T848
Test name
Test status
Simulation time 2581479558 ps
CPU time 10.16 seconds
Started Jul 06 06:31:45 PM PDT 24
Finished Jul 06 06:31:55 PM PDT 24
Peak memory 226076 kb
Host smart-e43b8fb8-1a66-493c-91bc-ffe72b292ab8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196441204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2196441204
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.3289159025
Short name T803
Test name
Test status
Simulation time 570032275 ps
CPU time 7.86 seconds
Started Jul 06 06:31:44 PM PDT 24
Finished Jul 06 06:31:52 PM PDT 24
Peak memory 226052 kb
Host smart-f94f759a-5bdb-4c65-be18-10099be793d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289159025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.3289159025
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.594562602
Short name T321
Test name
Test status
Simulation time 360312978 ps
CPU time 8.41 seconds
Started Jul 06 06:31:46 PM PDT 24
Finished Jul 06 06:31:55 PM PDT 24
Peak memory 218240 kb
Host smart-729c4415-1cc9-48fc-9eef-37f62c6aedfe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594562602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.594562602
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.2520029859
Short name T365
Test name
Test status
Simulation time 698415024 ps
CPU time 13.99 seconds
Started Jul 06 06:31:49 PM PDT 24
Finished Jul 06 06:32:03 PM PDT 24
Peak memory 218240 kb
Host smart-bb2e708f-f008-404c-98de-a50b3318f9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520029859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.2520029859
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.1306641200
Short name T431
Test name
Test status
Simulation time 52713861 ps
CPU time 1.89 seconds
Started Jul 06 06:31:45 PM PDT 24
Finished Jul 06 06:31:47 PM PDT 24
Peak memory 217712 kb
Host smart-122579c6-af44-42f4-bfd6-6245be7bba3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306641200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1306641200
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.173259354
Short name T725
Test name
Test status
Simulation time 300412600 ps
CPU time 26.3 seconds
Started Jul 06 06:31:47 PM PDT 24
Finished Jul 06 06:32:14 PM PDT 24
Peak memory 250996 kb
Host smart-90087a72-aff7-4d28-aee3-88c9ed6f1642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173259354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.173259354
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.3236737739
Short name T669
Test name
Test status
Simulation time 58150151 ps
CPU time 3.02 seconds
Started Jul 06 06:31:44 PM PDT 24
Finished Jul 06 06:31:48 PM PDT 24
Peak memory 222280 kb
Host smart-58d8dfb5-c2ff-45bb-bc71-401003265fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236737739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3236737739
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.1253308071
Short name T623
Test name
Test status
Simulation time 92917388032 ps
CPU time 155.91 seconds
Started Jul 06 06:31:46 PM PDT 24
Finished Jul 06 06:34:23 PM PDT 24
Peak memory 332976 kb
Host smart-6b5a2bfc-44ef-46bb-b318-0a2a893ebc38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253308071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.1253308071
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1875440107
Short name T696
Test name
Test status
Simulation time 12362456 ps
CPU time 1.01 seconds
Started Jul 06 06:31:46 PM PDT 24
Finished Jul 06 06:31:47 PM PDT 24
Peak memory 211940 kb
Host smart-b6bfa2a0-11fd-416b-9b97-97372fd05860
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875440107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1875440107
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1448772691
Short name T840
Test name
Test status
Simulation time 24512612 ps
CPU time 1.22 seconds
Started Jul 06 06:29:51 PM PDT 24
Finished Jul 06 06:29:53 PM PDT 24
Peak memory 209092 kb
Host smart-de6858e8-065a-48ae-b672-f3c09913e8a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448772691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1448772691
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.3010638630
Short name T161
Test name
Test status
Simulation time 13652103 ps
CPU time 0.78 seconds
Started Jul 06 06:29:48 PM PDT 24
Finished Jul 06 06:29:49 PM PDT 24
Peak memory 208952 kb
Host smart-3d348ddf-9057-49e2-9112-94e5360bb9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010638630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.3010638630
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.2612492962
Short name T792
Test name
Test status
Simulation time 284848613 ps
CPU time 14.93 seconds
Started Jul 06 06:29:50 PM PDT 24
Finished Jul 06 06:30:06 PM PDT 24
Peak memory 218232 kb
Host smart-15d295de-1062-4b9c-a14d-639f450a08a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612492962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.2612492962
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.962349302
Short name T45
Test name
Test status
Simulation time 62385998 ps
CPU time 1.55 seconds
Started Jul 06 06:29:48 PM PDT 24
Finished Jul 06 06:29:50 PM PDT 24
Peak memory 217136 kb
Host smart-a95ccc7a-f535-4b3e-afd8-204ab5c168cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962349302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.962349302
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1575811293
Short name T614
Test name
Test status
Simulation time 5507326121 ps
CPU time 35.91 seconds
Started Jul 06 06:29:41 PM PDT 24
Finished Jul 06 06:30:18 PM PDT 24
Peak memory 219016 kb
Host smart-26ab6bdc-f7d3-40b6-ae41-d31bd717f9e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575811293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1575811293
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2835307096
Short name T853
Test name
Test status
Simulation time 3685582926 ps
CPU time 10.66 seconds
Started Jul 06 06:29:47 PM PDT 24
Finished Jul 06 06:29:58 PM PDT 24
Peak memory 217860 kb
Host smart-b565c66d-c06c-4b61-80cc-e518aa18df18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835307096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
835307096
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3585840740
Short name T679
Test name
Test status
Simulation time 1891925628 ps
CPU time 10.51 seconds
Started Jul 06 06:29:53 PM PDT 24
Finished Jul 06 06:30:04 PM PDT 24
Peak memory 218184 kb
Host smart-ccf19f0b-7fd5-4876-aab4-f9e4174febd6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585840740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3585840740
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2074214353
Short name T582
Test name
Test status
Simulation time 3577487060 ps
CPU time 12.75 seconds
Started Jul 06 06:29:49 PM PDT 24
Finished Jul 06 06:30:02 PM PDT 24
Peak memory 217808 kb
Host smart-5ecb5153-41c5-47df-a7f6-d900db6fbc92
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074214353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.2074214353
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3163588284
Short name T730
Test name
Test status
Simulation time 917562928 ps
CPU time 8.37 seconds
Started Jul 06 06:29:48 PM PDT 24
Finished Jul 06 06:29:57 PM PDT 24
Peak memory 217664 kb
Host smart-62762f68-0351-4df9-9531-716e8fb53fe4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163588284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3163588284
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.858988176
Short name T750
Test name
Test status
Simulation time 1758611648 ps
CPU time 51.64 seconds
Started Jul 06 06:29:49 PM PDT 24
Finished Jul 06 06:30:41 PM PDT 24
Peak memory 267320 kb
Host smart-73d30093-e3e7-4988-8ffe-bb03c068c5bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858988176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_state_failure.858988176
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.903592226
Short name T838
Test name
Test status
Simulation time 930011358 ps
CPU time 15.55 seconds
Started Jul 06 06:29:38 PM PDT 24
Finished Jul 06 06:29:54 PM PDT 24
Peak memory 218196 kb
Host smart-3bdae85c-f961-41e0-849c-6053f08b81ae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903592226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_state_post_trans.903592226
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.156101798
Short name T766
Test name
Test status
Simulation time 45841604 ps
CPU time 2.72 seconds
Started Jul 06 06:29:38 PM PDT 24
Finished Jul 06 06:29:41 PM PDT 24
Peak memory 218224 kb
Host smart-6eb171b5-5b71-4a1e-a5fb-2f21389b30c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156101798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.156101798
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.728898158
Short name T198
Test name
Test status
Simulation time 1018375996 ps
CPU time 10.58 seconds
Started Jul 06 06:29:48 PM PDT 24
Finished Jul 06 06:29:59 PM PDT 24
Peak memory 214164 kb
Host smart-fd36e404-223b-4ff7-9fb1-d9b160694d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728898158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.728898158
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.429567678
Short name T758
Test name
Test status
Simulation time 1174729761 ps
CPU time 18.33 seconds
Started Jul 06 06:29:52 PM PDT 24
Finished Jul 06 06:30:11 PM PDT 24
Peak memory 226036 kb
Host smart-a33466f9-c857-42ad-bd9c-f57cd8e37315
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429567678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.429567678
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2082262213
Short name T228
Test name
Test status
Simulation time 2373475221 ps
CPU time 12.46 seconds
Started Jul 06 06:29:53 PM PDT 24
Finished Jul 06 06:30:06 PM PDT 24
Peak memory 226040 kb
Host smart-3afd1f01-7f13-4ff8-aa90-340845370e97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082262213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.2082262213
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.2761690933
Short name T257
Test name
Test status
Simulation time 236644542 ps
CPU time 8.08 seconds
Started Jul 06 06:29:48 PM PDT 24
Finished Jul 06 06:29:56 PM PDT 24
Peak memory 226032 kb
Host smart-f56cdbed-9b69-4bb4-b395-d546ea2eb8bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761690933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.2
761690933
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1713220036
Short name T858
Test name
Test status
Simulation time 1083138160 ps
CPU time 9.57 seconds
Started Jul 06 06:29:50 PM PDT 24
Finished Jul 06 06:29:59 PM PDT 24
Peak memory 225468 kb
Host smart-50ad4710-a9a0-4019-8889-166d016914ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713220036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1713220036
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.3204268203
Short name T646
Test name
Test status
Simulation time 124512872 ps
CPU time 1.84 seconds
Started Jul 06 06:29:48 PM PDT 24
Finished Jul 06 06:29:51 PM PDT 24
Peak memory 214288 kb
Host smart-bad18b4e-a18f-4c5c-bbfc-32a0350f7753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204268203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3204268203
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.2490965840
Short name T237
Test name
Test status
Simulation time 606876280 ps
CPU time 30.31 seconds
Started Jul 06 06:29:37 PM PDT 24
Finished Jul 06 06:30:08 PM PDT 24
Peak memory 250952 kb
Host smart-577822e9-5f2c-4a89-b9fb-d816787c88cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490965840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.2490965840
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.3000514797
Short name T96
Test name
Test status
Simulation time 263753879 ps
CPU time 3.47 seconds
Started Jul 06 06:29:35 PM PDT 24
Finished Jul 06 06:29:39 PM PDT 24
Peak memory 222508 kb
Host smart-e1923ea5-a6ca-4ec2-95aa-50f3664d0ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000514797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.3000514797
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.966010876
Short name T324
Test name
Test status
Simulation time 496657942 ps
CPU time 39.1 seconds
Started Jul 06 06:29:41 PM PDT 24
Finished Jul 06 06:30:21 PM PDT 24
Peak memory 248984 kb
Host smart-29036078-34ab-4ecc-b728-0fa28049ab4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966010876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.966010876
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3952917547
Short name T685
Test name
Test status
Simulation time 36156213 ps
CPU time 0.92 seconds
Started Jul 06 06:29:40 PM PDT 24
Finished Jul 06 06:29:41 PM PDT 24
Peak memory 211872 kb
Host smart-799b0665-2f89-483c-ac70-295cc3aea6ba
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952917547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.3952917547
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.890877037
Short name T828
Test name
Test status
Simulation time 100345913 ps
CPU time 1.14 seconds
Started Jul 06 06:29:50 PM PDT 24
Finished Jul 06 06:29:52 PM PDT 24
Peak memory 208944 kb
Host smart-77f9c006-f954-4bdf-929e-cc34f4d253eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890877037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.890877037
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.1978944155
Short name T805
Test name
Test status
Simulation time 1275841063 ps
CPU time 10.79 seconds
Started Jul 06 06:29:53 PM PDT 24
Finished Jul 06 06:30:04 PM PDT 24
Peak memory 218120 kb
Host smart-d7d586e8-a587-4a36-9671-c188d2e05082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978944155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1978944155
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1865808688
Short name T794
Test name
Test status
Simulation time 31400637 ps
CPU time 1.51 seconds
Started Jul 06 06:29:54 PM PDT 24
Finished Jul 06 06:29:56 PM PDT 24
Peak memory 217196 kb
Host smart-6ea29aff-7ccd-425e-86f9-9c2503a9d2b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865808688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1865808688
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.474142395
Short name T299
Test name
Test status
Simulation time 11443849987 ps
CPU time 80.32 seconds
Started Jul 06 06:29:54 PM PDT 24
Finished Jul 06 06:31:15 PM PDT 24
Peak memory 218784 kb
Host smart-fd47d558-4dc5-42ad-86b7-b9485150bd1e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474142395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_err
ors.474142395
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.3953606456
Short name T3
Test name
Test status
Simulation time 310095840 ps
CPU time 7.54 seconds
Started Jul 06 06:29:50 PM PDT 24
Finished Jul 06 06:29:58 PM PDT 24
Peak memory 217600 kb
Host smart-4ea0aba5-1d6d-4b21-a643-2a25facf77b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953606456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.3
953606456
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.460655348
Short name T55
Test name
Test status
Simulation time 1097118994 ps
CPU time 6.64 seconds
Started Jul 06 06:29:57 PM PDT 24
Finished Jul 06 06:30:04 PM PDT 24
Peak memory 218164 kb
Host smart-7488b835-87ec-4a10-869d-ae0a72d74771
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460655348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
prog_failure.460655348
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.4042287434
Short name T466
Test name
Test status
Simulation time 4738769372 ps
CPU time 32.08 seconds
Started Jul 06 06:29:52 PM PDT 24
Finished Jul 06 06:30:25 PM PDT 24
Peak memory 217720 kb
Host smart-935b5222-c08f-4782-8ef0-22f676cd67c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042287434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.4042287434
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3819522577
Short name T291
Test name
Test status
Simulation time 248556041 ps
CPU time 4.74 seconds
Started Jul 06 06:29:48 PM PDT 24
Finished Jul 06 06:29:53 PM PDT 24
Peak memory 217732 kb
Host smart-07255113-9887-4112-97ea-6c15abee2ad8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819522577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3819522577
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.4135662573
Short name T339
Test name
Test status
Simulation time 1850957833 ps
CPU time 52.65 seconds
Started Jul 06 06:29:48 PM PDT 24
Finished Jul 06 06:30:41 PM PDT 24
Peak memory 251012 kb
Host smart-ad1741c4-7012-46ce-ba68-bf37d8264c36
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135662573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.4135662573
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2829174997
Short name T371
Test name
Test status
Simulation time 334401491 ps
CPU time 14.74 seconds
Started Jul 06 06:29:51 PM PDT 24
Finished Jul 06 06:30:07 PM PDT 24
Peak memory 243016 kb
Host smart-4e6772d6-dfe0-4774-b6a2-748669861a08
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829174997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.2829174997
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1112953743
Short name T683
Test name
Test status
Simulation time 487556452 ps
CPU time 4.03 seconds
Started Jul 06 06:29:46 PM PDT 24
Finished Jul 06 06:29:50 PM PDT 24
Peak memory 218232 kb
Host smart-965064c8-2648-4324-a6d3-80d4bc7358aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112953743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1112953743
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.694668335
Short name T293
Test name
Test status
Simulation time 1030757491 ps
CPU time 9.31 seconds
Started Jul 06 06:29:43 PM PDT 24
Finished Jul 06 06:29:53 PM PDT 24
Peak memory 217692 kb
Host smart-81ad549e-7469-4f5e-b749-9cded61e5d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694668335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.694668335
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.187105779
Short name T573
Test name
Test status
Simulation time 1070302034 ps
CPU time 13.76 seconds
Started Jul 06 06:29:51 PM PDT 24
Finished Jul 06 06:30:06 PM PDT 24
Peak memory 218240 kb
Host smart-220012e0-fa0c-4cd7-8d85-e1b299a96b08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187105779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.187105779
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.676660171
Short name T21
Test name
Test status
Simulation time 500676565 ps
CPU time 16.95 seconds
Started Jul 06 06:30:07 PM PDT 24
Finished Jul 06 06:30:24 PM PDT 24
Peak memory 226028 kb
Host smart-fdad4e12-cc62-42b8-b75c-e5fd466330e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676660171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dig
est.676660171
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3673451209
Short name T687
Test name
Test status
Simulation time 637514351 ps
CPU time 12.07 seconds
Started Jul 06 06:29:57 PM PDT 24
Finished Jul 06 06:30:09 PM PDT 24
Peak memory 226020 kb
Host smart-86109233-e169-4cf7-9213-431d1db4e950
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673451209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3
673451209
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.1674731671
Short name T92
Test name
Test status
Simulation time 822914522 ps
CPU time 9.48 seconds
Started Jul 06 06:29:46 PM PDT 24
Finished Jul 06 06:29:56 PM PDT 24
Peak memory 226072 kb
Host smart-35a0740d-1835-4072-9af3-3fcefa5b897a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674731671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1674731671
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.3595966335
Short name T335
Test name
Test status
Simulation time 104798880 ps
CPU time 3.56 seconds
Started Jul 06 06:29:50 PM PDT 24
Finished Jul 06 06:29:54 PM PDT 24
Peak memory 217728 kb
Host smart-5b36fd04-3897-4b5a-b1c0-21e52bb164dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595966335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3595966335
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3560223069
Short name T498
Test name
Test status
Simulation time 240296435 ps
CPU time 25.18 seconds
Started Jul 06 06:29:50 PM PDT 24
Finished Jul 06 06:30:16 PM PDT 24
Peak memory 251080 kb
Host smart-350067de-b62b-4ae6-bf5c-20899410732e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560223069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3560223069
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3993887740
Short name T364
Test name
Test status
Simulation time 115439356 ps
CPU time 8.75 seconds
Started Jul 06 06:29:52 PM PDT 24
Finished Jul 06 06:30:01 PM PDT 24
Peak memory 251016 kb
Host smart-d9bbe9af-362b-43d8-9c94-35e09e72b97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993887740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3993887740
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.1841250069
Short name T779
Test name
Test status
Simulation time 5458515995 ps
CPU time 178.2 seconds
Started Jul 06 06:29:58 PM PDT 24
Finished Jul 06 06:32:56 PM PDT 24
Peak memory 279984 kb
Host smart-ddb32961-700d-46e8-96aa-d3c9965bf36a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841250069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.1841250069
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.4113533977
Short name T778
Test name
Test status
Simulation time 16452974 ps
CPU time 0.92 seconds
Started Jul 06 06:29:58 PM PDT 24
Finished Jul 06 06:29:59 PM PDT 24
Peak memory 212032 kb
Host smart-0f1c47c0-16de-47e1-acaf-ee76d42f9e50
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113533977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.4113533977
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.3178260606
Short name T765
Test name
Test status
Simulation time 24555899 ps
CPU time 0.97 seconds
Started Jul 06 06:29:48 PM PDT 24
Finished Jul 06 06:29:50 PM PDT 24
Peak memory 208992 kb
Host smart-45b0e2da-663d-4c54-841b-4bda36b0350f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178260606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.3178260606
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1124472058
Short name T457
Test name
Test status
Simulation time 255112176 ps
CPU time 12.63 seconds
Started Jul 06 06:29:58 PM PDT 24
Finished Jul 06 06:30:10 PM PDT 24
Peak memory 225992 kb
Host smart-b3a7424c-2125-4816-bbaf-39e1063c0d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124472058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1124472058
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.1037850566
Short name T341
Test name
Test status
Simulation time 1131918022 ps
CPU time 3.12 seconds
Started Jul 06 06:29:51 PM PDT 24
Finished Jul 06 06:29:54 PM PDT 24
Peak memory 217112 kb
Host smart-0ebd14ff-9710-4bb8-8bbb-a0ff79de006e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037850566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.1037850566
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.1287688358
Short name T98
Test name
Test status
Simulation time 5241275014 ps
CPU time 136.72 seconds
Started Jul 06 06:29:53 PM PDT 24
Finished Jul 06 06:32:10 PM PDT 24
Peak memory 226116 kb
Host smart-11471471-5b13-40aa-a154-7550ba7ead67
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287688358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.1287688358
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.3281649359
Short name T517
Test name
Test status
Simulation time 515026801 ps
CPU time 2.32 seconds
Started Jul 06 06:29:52 PM PDT 24
Finished Jul 06 06:29:55 PM PDT 24
Peak memory 217752 kb
Host smart-2820503d-c609-4201-8a39-5dbe927aded2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281649359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.3
281649359
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1267330699
Short name T637
Test name
Test status
Simulation time 227396789 ps
CPU time 4.08 seconds
Started Jul 06 06:29:47 PM PDT 24
Finished Jul 06 06:29:51 PM PDT 24
Peak memory 218212 kb
Host smart-2c0657ce-2231-49c7-9698-fd4757a45881
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267330699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1267330699
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.231760173
Short name T280
Test name
Test status
Simulation time 5170386721 ps
CPU time 15.7 seconds
Started Jul 06 06:30:05 PM PDT 24
Finished Jul 06 06:30:22 PM PDT 24
Peak memory 217824 kb
Host smart-14f772f1-5267-4a6c-86d4-6c1366366d91
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231760173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.231760173
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.2584525618
Short name T64
Test name
Test status
Simulation time 177332742 ps
CPU time 4.87 seconds
Started Jul 06 06:29:53 PM PDT 24
Finished Jul 06 06:29:58 PM PDT 24
Peak memory 217632 kb
Host smart-60d24f1d-b0ad-4bd6-b7ed-2eeefc85fcbc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584525618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
2584525618
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.122494980
Short name T611
Test name
Test status
Simulation time 1699714742 ps
CPU time 43.1 seconds
Started Jul 06 06:29:54 PM PDT 24
Finished Jul 06 06:30:38 PM PDT 24
Peak memory 283604 kb
Host smart-ef5aacce-4a48-4331-bc1a-0c2dc5cdbcc0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122494980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_state_failure.122494980
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.1685667608
Short name T734
Test name
Test status
Simulation time 2211659443 ps
CPU time 22.3 seconds
Started Jul 06 06:29:49 PM PDT 24
Finished Jul 06 06:30:11 PM PDT 24
Peak memory 251020 kb
Host smart-f1f18e15-aae5-426b-82d8-a91cfae18198
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685667608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.1685667608
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1452939450
Short name T391
Test name
Test status
Simulation time 289074680 ps
CPU time 2.9 seconds
Started Jul 06 06:29:56 PM PDT 24
Finished Jul 06 06:29:59 PM PDT 24
Peak memory 222312 kb
Host smart-8971137c-4b65-4d59-a47e-2af4eb600438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452939450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1452939450
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.2536693
Short name T754
Test name
Test status
Simulation time 665687572 ps
CPU time 8.01 seconds
Started Jul 06 06:30:00 PM PDT 24
Finished Jul 06 06:30:08 PM PDT 24
Peak memory 217712 kb
Host smart-b2a018ab-a478-4955-98e2-34e698afe2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.2536693
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.392921058
Short name T253
Test name
Test status
Simulation time 307398655 ps
CPU time 12.36 seconds
Started Jul 06 06:29:52 PM PDT 24
Finished Jul 06 06:30:05 PM PDT 24
Peak memory 219492 kb
Host smart-f12256bc-4caf-4e20-b958-15df86bd68ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392921058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.392921058
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3129989064
Short name T378
Test name
Test status
Simulation time 323073827 ps
CPU time 10.91 seconds
Started Jul 06 06:29:47 PM PDT 24
Finished Jul 06 06:29:59 PM PDT 24
Peak memory 226036 kb
Host smart-86ede73d-298a-4254-a96f-f6c53ad10025
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129989064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3129989064
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2593915556
Short name T242
Test name
Test status
Simulation time 3352500679 ps
CPU time 9.7 seconds
Started Jul 06 06:30:02 PM PDT 24
Finished Jul 06 06:30:12 PM PDT 24
Peak memory 218220 kb
Host smart-f54c4024-9030-4ede-a132-cec7017390ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593915556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2
593915556
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.1359478441
Short name T674
Test name
Test status
Simulation time 695378284 ps
CPU time 8.94 seconds
Started Jul 06 06:29:50 PM PDT 24
Finished Jul 06 06:30:00 PM PDT 24
Peak memory 218316 kb
Host smart-4b6269e7-84af-4052-909e-aa4693aa6c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359478441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1359478441
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.365764544
Short name T413
Test name
Test status
Simulation time 43927546 ps
CPU time 3.07 seconds
Started Jul 06 06:29:59 PM PDT 24
Finished Jul 06 06:30:03 PM PDT 24
Peak memory 214812 kb
Host smart-6af72f85-2ebe-4ede-9644-74d79635f04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365764544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.365764544
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.2002797715
Short name T426
Test name
Test status
Simulation time 188384548 ps
CPU time 20.86 seconds
Started Jul 06 06:29:48 PM PDT 24
Finished Jul 06 06:30:09 PM PDT 24
Peak memory 250984 kb
Host smart-00e99b54-9441-4971-98a7-f411d115e492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002797715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.2002797715
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1857671057
Short name T622
Test name
Test status
Simulation time 256727099 ps
CPU time 6.12 seconds
Started Jul 06 06:29:44 PM PDT 24
Finished Jul 06 06:29:51 PM PDT 24
Peak memory 246908 kb
Host smart-dcae4ae5-b8c4-47ba-a314-00e02b24c382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857671057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1857671057
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.4163237714
Short name T760
Test name
Test status
Simulation time 7368624598 ps
CPU time 96.22 seconds
Started Jul 06 06:30:00 PM PDT 24
Finished Jul 06 06:31:37 PM PDT 24
Peak memory 242316 kb
Host smart-81117038-c0be-4987-a1d8-9b5baa0b33b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163237714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.4163237714
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.4142489411
Short name T561
Test name
Test status
Simulation time 64357957829 ps
CPU time 794.21 seconds
Started Jul 06 06:29:52 PM PDT 24
Finished Jul 06 06:43:07 PM PDT 24
Peak memory 293264 kb
Host smart-cb8e5178-6b18-4853-a1d0-6fb32a988711
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4142489411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.4142489411
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2334022128
Short name T736
Test name
Test status
Simulation time 15153599 ps
CPU time 0.91 seconds
Started Jul 06 06:29:54 PM PDT 24
Finished Jul 06 06:29:55 PM PDT 24
Peak memory 211836 kb
Host smart-ea61315f-d50d-4cdc-a468-a86887027ffa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334022128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.2334022128
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.603318373
Short name T284
Test name
Test status
Simulation time 23379424 ps
CPU time 1.18 seconds
Started Jul 06 06:30:06 PM PDT 24
Finished Jul 06 06:30:07 PM PDT 24
Peak memory 209004 kb
Host smart-f1495954-8408-410c-888c-a85937b20640
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603318373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.603318373
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.1448200839
Short name T839
Test name
Test status
Simulation time 1908898590 ps
CPU time 14.59 seconds
Started Jul 06 06:30:00 PM PDT 24
Finished Jul 06 06:30:15 PM PDT 24
Peak memory 218260 kb
Host smart-ffb4cc2a-6c34-43bd-804e-fd84fe111278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448200839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1448200839
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1558273859
Short name T578
Test name
Test status
Simulation time 538908398 ps
CPU time 6.41 seconds
Started Jul 06 06:29:55 PM PDT 24
Finished Jul 06 06:30:02 PM PDT 24
Peak memory 217380 kb
Host smart-417de3c6-f377-465c-a551-c2e200ad31ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558273859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1558273859
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1308196510
Short name T724
Test name
Test status
Simulation time 1476834685 ps
CPU time 46.11 seconds
Started Jul 06 06:29:56 PM PDT 24
Finished Jul 06 06:30:42 PM PDT 24
Peak memory 218864 kb
Host smart-b5765898-8c4a-4fb4-96de-d2b19d46005b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308196510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1308196510
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.859063029
Short name T332
Test name
Test status
Simulation time 1044053638 ps
CPU time 5.68 seconds
Started Jul 06 06:29:56 PM PDT 24
Finished Jul 06 06:30:02 PM PDT 24
Peak memory 217512 kb
Host smart-8bbab224-0491-407a-8a47-5e4558f05770
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859063029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.859063029
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.882115690
Short name T849
Test name
Test status
Simulation time 346816789 ps
CPU time 3.55 seconds
Started Jul 06 06:29:50 PM PDT 24
Finished Jul 06 06:29:54 PM PDT 24
Peak memory 218104 kb
Host smart-cafb95de-3288-4f08-92d0-51c2e74f93ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882115690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
prog_failure.882115690
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.4293739263
Short name T347
Test name
Test status
Simulation time 1222338595 ps
CPU time 20.22 seconds
Started Jul 06 06:29:50 PM PDT 24
Finished Jul 06 06:30:11 PM PDT 24
Peak memory 217840 kb
Host smart-42c813d6-0324-4009-afd2-b18ec8c5231d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293739263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.4293739263
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.411220887
Short name T700
Test name
Test status
Simulation time 238103191 ps
CPU time 1.59 seconds
Started Jul 06 06:29:56 PM PDT 24
Finished Jul 06 06:29:58 PM PDT 24
Peak memory 217700 kb
Host smart-e98c635f-9f83-4840-b3b7-a6b6a0200f1b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411220887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.411220887
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.306030875
Short name T311
Test name
Test status
Simulation time 3196201323 ps
CPU time 44.98 seconds
Started Jul 06 06:30:12 PM PDT 24
Finished Jul 06 06:30:57 PM PDT 24
Peak memory 251004 kb
Host smart-fe7936bb-18de-48c2-a1f4-259a7602c01a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306030875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_state_failure.306030875
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1049074419
Short name T833
Test name
Test status
Simulation time 3161089633 ps
CPU time 25.56 seconds
Started Jul 06 06:29:53 PM PDT 24
Finished Jul 06 06:30:19 PM PDT 24
Peak memory 249168 kb
Host smart-2a5fd2bd-11e7-4f43-8613-1cb9a991c461
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049074419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.1049074419
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2712296119
Short name T220
Test name
Test status
Simulation time 88608197 ps
CPU time 3.24 seconds
Started Jul 06 06:29:50 PM PDT 24
Finished Jul 06 06:29:53 PM PDT 24
Peak memory 222364 kb
Host smart-2d8ff19b-b4a5-4698-a099-f4e3e3a369a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712296119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2712296119
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3524687276
Short name T525
Test name
Test status
Simulation time 952907174 ps
CPU time 15.73 seconds
Started Jul 06 06:29:53 PM PDT 24
Finished Jul 06 06:30:09 PM PDT 24
Peak memory 214656 kb
Host smart-1f8a93dc-29a8-4548-b9f5-f2019764845b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524687276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3524687276
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3062461049
Short name T606
Test name
Test status
Simulation time 491491833 ps
CPU time 18.93 seconds
Started Jul 06 06:29:57 PM PDT 24
Finished Jul 06 06:30:16 PM PDT 24
Peak memory 226056 kb
Host smart-6464b0da-2d3e-4f97-8a85-ce0db1551379
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062461049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3062461049
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.3147839804
Short name T465
Test name
Test status
Simulation time 799832381 ps
CPU time 9.87 seconds
Started Jul 06 06:30:10 PM PDT 24
Finished Jul 06 06:30:20 PM PDT 24
Peak memory 226024 kb
Host smart-b46d9592-7ea1-4d33-aac0-5a674c9a8420
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147839804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.3147839804
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.1732594795
Short name T222
Test name
Test status
Simulation time 4371892822 ps
CPU time 6.34 seconds
Started Jul 06 06:30:05 PM PDT 24
Finished Jul 06 06:30:11 PM PDT 24
Peak memory 218320 kb
Host smart-5f529688-82ec-4147-a695-d98fe9809dba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732594795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.1
732594795
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.1265452748
Short name T581
Test name
Test status
Simulation time 1601619080 ps
CPU time 13.26 seconds
Started Jul 06 06:29:55 PM PDT 24
Finished Jul 06 06:30:09 PM PDT 24
Peak memory 225940 kb
Host smart-2b3343ea-180e-43ae-98a5-21e86c5fff86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265452748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.1265452748
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.104528673
Short name T537
Test name
Test status
Simulation time 19089343 ps
CPU time 1.71 seconds
Started Jul 06 06:29:51 PM PDT 24
Finished Jul 06 06:29:53 PM PDT 24
Peak memory 223384 kb
Host smart-5c5173d6-3800-4b19-962c-5176e7a47366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104528673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.104528673
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.2963783077
Short name T295
Test name
Test status
Simulation time 732715268 ps
CPU time 30.27 seconds
Started Jul 06 06:29:51 PM PDT 24
Finished Jul 06 06:30:22 PM PDT 24
Peak memory 251056 kb
Host smart-ba983986-19cb-4bf4-bce1-5c70e902923d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963783077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2963783077
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3372534755
Short name T105
Test name
Test status
Simulation time 275551788 ps
CPU time 6.2 seconds
Started Jul 06 06:29:50 PM PDT 24
Finished Jul 06 06:29:57 PM PDT 24
Peak memory 246744 kb
Host smart-3c12bd37-086e-458e-8212-7ebd4368d032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372534755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3372534755
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.1518513941
Short name T408
Test name
Test status
Simulation time 9624705916 ps
CPU time 247.03 seconds
Started Jul 06 06:30:01 PM PDT 24
Finished Jul 06 06:34:08 PM PDT 24
Peak memory 283936 kb
Host smart-609a836b-5c77-4065-a7da-8a16844e6781
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518513941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.1518513941
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3278009273
Short name T244
Test name
Test status
Simulation time 44986696 ps
CPU time 0.96 seconds
Started Jul 06 06:29:53 PM PDT 24
Finished Jul 06 06:29:54 PM PDT 24
Peak memory 212004 kb
Host smart-242ea5e7-f36c-44b6-b62d-70b69fd9514d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278009273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3278009273
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.1209341575
Short name T519
Test name
Test status
Simulation time 27356655 ps
CPU time 1.21 seconds
Started Jul 06 06:29:54 PM PDT 24
Finished Jul 06 06:29:55 PM PDT 24
Peak memory 209004 kb
Host smart-74338d7e-ee9e-4362-827a-f248702c164a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209341575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.1209341575
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.581925451
Short name T68
Test name
Test status
Simulation time 13061874 ps
CPU time 0.85 seconds
Started Jul 06 06:29:54 PM PDT 24
Finished Jul 06 06:29:55 PM PDT 24
Peak memory 208824 kb
Host smart-efdc187d-30ab-4da0-8f70-c2695c89386f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581925451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.581925451
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.991170299
Short name T728
Test name
Test status
Simulation time 500502864 ps
CPU time 11.42 seconds
Started Jul 06 06:29:51 PM PDT 24
Finished Jul 06 06:30:03 PM PDT 24
Peak memory 218232 kb
Host smart-44f12a80-0bea-4f01-ae46-99efd0bd6660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991170299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.991170299
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3881622933
Short name T542
Test name
Test status
Simulation time 287681714 ps
CPU time 1.62 seconds
Started Jul 06 06:29:49 PM PDT 24
Finished Jul 06 06:29:51 PM PDT 24
Peak memory 217100 kb
Host smart-08230cd7-ce37-4581-a44b-15bb5ca61c37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881622933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3881622933
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.2212735165
Short name T43
Test name
Test status
Simulation time 7256882898 ps
CPU time 49.7 seconds
Started Jul 06 06:30:03 PM PDT 24
Finished Jul 06 06:30:53 PM PDT 24
Peak memory 218312 kb
Host smart-3fe7c74c-e23a-45d6-b7af-eac967fed6a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212735165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.2212735165
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.1768712525
Short name T447
Test name
Test status
Simulation time 1336441875 ps
CPU time 8.13 seconds
Started Jul 06 06:29:56 PM PDT 24
Finished Jul 06 06:30:04 PM PDT 24
Peak memory 217696 kb
Host smart-accd94c3-0064-4966-8ee0-4c0d65efbdf1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768712525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.1
768712525
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.93876218
Short name T396
Test name
Test status
Simulation time 322398726 ps
CPU time 10.17 seconds
Started Jul 06 06:29:57 PM PDT 24
Finished Jul 06 06:30:08 PM PDT 24
Peak memory 223536 kb
Host smart-98634f45-07ae-410f-b448-7c75307a15af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93876218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_p
rog_failure.93876218
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1900045192
Short name T727
Test name
Test status
Simulation time 1618804354 ps
CPU time 15.81 seconds
Started Jul 06 06:29:56 PM PDT 24
Finished Jul 06 06:30:12 PM PDT 24
Peak memory 217656 kb
Host smart-b60b5f20-c8ae-40d2-913e-48a3d3ae5d8e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900045192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.1900045192
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.3193357851
Short name T331
Test name
Test status
Simulation time 310946322 ps
CPU time 10.01 seconds
Started Jul 06 06:29:51 PM PDT 24
Finished Jul 06 06:30:02 PM PDT 24
Peak memory 217720 kb
Host smart-0902b0aa-0197-4c15-aedf-545fd9c95921
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193357851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
3193357851
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.2567654930
Short name T160
Test name
Test status
Simulation time 9387286635 ps
CPU time 41.67 seconds
Started Jul 06 06:29:50 PM PDT 24
Finished Jul 06 06:30:32 PM PDT 24
Peak memory 251360 kb
Host smart-9be65e28-8af4-450e-99be-fa607d6ac5cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567654930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.2567654930
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.131813608
Short name T406
Test name
Test status
Simulation time 1564810908 ps
CPU time 12.08 seconds
Started Jul 06 06:29:59 PM PDT 24
Finished Jul 06 06:30:11 PM PDT 24
Peak memory 250720 kb
Host smart-25e2df17-f7d8-411b-987c-2ae89866a6fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131813608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_state_post_trans.131813608
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1551355988
Short name T351
Test name
Test status
Simulation time 113976211 ps
CPU time 5.04 seconds
Started Jul 06 06:30:00 PM PDT 24
Finished Jul 06 06:30:05 PM PDT 24
Peak memory 218208 kb
Host smart-edd1e983-138e-48f0-8fb3-0e4041cd6d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551355988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1551355988
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.2579571371
Short name T797
Test name
Test status
Simulation time 948867971 ps
CPU time 13.85 seconds
Started Jul 06 06:29:58 PM PDT 24
Finished Jul 06 06:30:12 PM PDT 24
Peak memory 217708 kb
Host smart-e2bdfaa7-d6e3-46f9-834f-64a45bafc30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579571371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2579571371
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.3481570871
Short name T584
Test name
Test status
Simulation time 610419566 ps
CPU time 9.26 seconds
Started Jul 06 06:29:51 PM PDT 24
Finished Jul 06 06:30:01 PM PDT 24
Peak memory 226004 kb
Host smart-5d1591a6-8f87-47e1-8d12-ee56fe926254
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481570871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.3481570871
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.3268152705
Short name T467
Test name
Test status
Simulation time 882211498 ps
CPU time 11.36 seconds
Started Jul 06 06:30:04 PM PDT 24
Finished Jul 06 06:30:15 PM PDT 24
Peak memory 226028 kb
Host smart-5d73260f-7863-4f6e-a09e-e287f62d4cde
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268152705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.3268152705
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1789060080
Short name T591
Test name
Test status
Simulation time 1365038445 ps
CPU time 7.69 seconds
Started Jul 06 06:29:54 PM PDT 24
Finished Jul 06 06:30:02 PM PDT 24
Peak memory 218272 kb
Host smart-d39e9ba2-6c7f-4bec-9505-2acd08937e44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789060080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.1
789060080
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.3563559083
Short name T708
Test name
Test status
Simulation time 766691163 ps
CPU time 7.89 seconds
Started Jul 06 06:30:08 PM PDT 24
Finished Jul 06 06:30:17 PM PDT 24
Peak memory 226052 kb
Host smart-9f982542-bc4f-4272-8499-2b3d64655d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563559083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.3563559083
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.2442592190
Short name T79
Test name
Test status
Simulation time 41242323 ps
CPU time 1.66 seconds
Started Jul 06 06:29:52 PM PDT 24
Finished Jul 06 06:29:54 PM PDT 24
Peak memory 217720 kb
Host smart-16f0fd49-8fa4-420b-8e90-d7f2cc359ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442592190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.2442592190
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.3391373062
Short name T435
Test name
Test status
Simulation time 735003181 ps
CPU time 31.53 seconds
Started Jul 06 06:30:12 PM PDT 24
Finished Jul 06 06:30:44 PM PDT 24
Peak memory 251048 kb
Host smart-dc83e521-3448-4f83-a955-6d259207d355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391373062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.3391373062
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.2983328104
Short name T575
Test name
Test status
Simulation time 99410274 ps
CPU time 8.88 seconds
Started Jul 06 06:29:58 PM PDT 24
Finished Jul 06 06:30:07 PM PDT 24
Peak memory 250992 kb
Host smart-d2382f51-f82c-49a5-a0ea-0b46ba1ea3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983328104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.2983328104
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.2797192357
Short name T172
Test name
Test status
Simulation time 28176511173 ps
CPU time 276.09 seconds
Started Jul 06 06:30:09 PM PDT 24
Finished Jul 06 06:34:45 PM PDT 24
Peak memory 283820 kb
Host smart-d73ce89a-c06e-4497-9850-224a9cdb1c73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797192357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.2797192357
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2632060612
Short name T585
Test name
Test status
Simulation time 68997344 ps
CPU time 0.95 seconds
Started Jul 06 06:29:51 PM PDT 24
Finished Jul 06 06:29:52 PM PDT 24
Peak memory 213020 kb
Host smart-62afe6ca-db78-49d3-b64c-df695c3b92f9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632060612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.2632060612
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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