Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48614 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
63 |
auto[1] |
1660 |
1 |
|
|
T16 |
4 |
|
T17 |
15 |
|
T18 |
14 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49707 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
50 |
auto[1] |
567 |
1 |
|
|
T3 |
13 |
|
T37 |
12 |
|
T60 |
7 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48543 |
1 |
|
|
T1 |
12 |
|
T2 |
2 |
|
T3 |
63 |
auto[1] |
1731 |
1 |
|
|
T1 |
1 |
|
T14 |
12 |
|
T16 |
10 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48472 |
1 |
|
|
T1 |
11 |
|
T2 |
2 |
|
T3 |
63 |
auto[1] |
1802 |
1 |
|
|
T1 |
2 |
|
T14 |
6 |
|
T15 |
1 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48454 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
63 |
auto[1] |
1820 |
1 |
|
|
T14 |
14 |
|
T15 |
2 |
|
T16 |
10 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
45657 |
1 |
|
|
T1 |
9 |
|
T2 |
2 |
|
T3 |
63 |
no_err_inj |
4617 |
1 |
|
|
T1 |
4 |
|
T11 |
18 |
|
T15 |
9 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48618 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
63 |
auto[1] |
1656 |
1 |
|
|
T16 |
14 |
|
T17 |
15 |
|
T18 |
10 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49707 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
45 |
auto[1] |
567 |
1 |
|
|
T3 |
18 |
|
T37 |
7 |
|
T60 |
9 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
34365 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
63 |
auto[1] |
15909 |
1 |
|
|
T10 |
8 |
|
T16 |
161 |
|
T27 |
202 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48441 |
1 |
|
|
T1 |
12 |
|
T2 |
2 |
|
T3 |
63 |
auto[1] |
1833 |
1 |
|
|
T1 |
1 |
|
T14 |
9 |
|
T15 |
1 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48434 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
63 |
auto[1] |
1840 |
1 |
|
|
T14 |
3 |
|
T16 |
9 |
|
T59 |
7 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48455 |
1 |
|
|
T1 |
9 |
|
T2 |
2 |
|
T3 |
63 |
auto[1] |
1819 |
1 |
|
|
T1 |
4 |
|
T14 |
5 |
|
T16 |
6 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48739 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
63 |
auto[1] |
1535 |
1 |
|
|
T16 |
13 |
|
T17 |
12 |
|
T18 |
11 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48081 |
1 |
|
|
T1 |
13 |
|
T3 |
63 |
|
T11 |
18 |
auto[1] |
2193 |
1 |
|
|
T2 |
2 |
|
T25 |
12 |
|
T16 |
21 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49672 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
48 |
auto[1] |
602 |
1 |
|
|
T3 |
15 |
|
T37 |
9 |
|
T60 |
14 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49675 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
53 |
auto[1] |
599 |
1 |
|
|
T3 |
10 |
|
T37 |
14 |
|
T60 |
6 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49688 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
56 |
auto[1] |
586 |
1 |
|
|
T3 |
7 |
|
T37 |
9 |
|
T60 |
15 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47654 |
1 |
|
|
T2 |
2 |
|
T3 |
63 |
|
T11 |
18 |
auto[1] |
2620 |
1 |
|
|
T1 |
13 |
|
T15 |
15 |
|
T16 |
15 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46629 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
63 |
auto[1] |
3645 |
1 |
|
|
T12 |
96 |
|
T24 |
72 |
|
T47 |
97 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48528 |
1 |
|
|
T1 |
12 |
|
T2 |
2 |
|
T3 |
63 |
auto[1] |
1746 |
1 |
|
|
T1 |
1 |
|
T14 |
8 |
|
T16 |
7 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48449 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
63 |
auto[1] |
1825 |
1 |
|
|
T14 |
12 |
|
T15 |
2 |
|
T16 |
6 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48472 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
63 |
auto[1] |
1802 |
1 |
|
|
T14 |
7 |
|
T16 |
13 |
|
T59 |
3 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48615 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
63 |
auto[1] |
1659 |
1 |
|
|
T16 |
9 |
|
T17 |
9 |
|
T18 |
8 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
44878 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
63 |
auto[1] |
5396 |
1 |
|
|
T16 |
5 |
|
T221 |
70 |
|
T17 |
11 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46420 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
63 |
auto[1] |
3854 |
1 |
|
|
T44 |
61 |
|
T54 |
72 |
|
T58 |
98 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50274 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
63 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48551 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
63 |
auto[1] |
1723 |
1 |
|
|
T16 |
10 |
|
T17 |
15 |
|
T18 |
10 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48650 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
63 |
auto[1] |
1624 |
1 |
|
|
T16 |
8 |
|
T17 |
13 |
|
T18 |
12 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48701 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
63 |
auto[1] |
1573 |
1 |
|
|
T16 |
7 |
|
T17 |
7 |
|
T18 |
11 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
44355 |
1 |
|
|
T2 |
2 |
|
T3 |
63 |
|
T12 |
96 |
auto[0] |
no_err_inj |
3299 |
1 |
|
|
T11 |
18 |
|
T10 |
8 |
|
T21 |
20 |
auto[1] |
err_inj |
1302 |
1 |
|
|
T1 |
9 |
|
T15 |
6 |
|
T16 |
7 |
auto[1] |
no_err_inj |
1318 |
1 |
|
|
T1 |
4 |
|
T15 |
9 |
|
T16 |
8 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
45946 |
1 |
|
|
T2 |
2 |
|
T3 |
63 |
|
T11 |
18 |
auto[0] |
auto[1] |
1708 |
1 |
|
|
T14 |
12 |
|
T16 |
6 |
|
T59 |
6 |
auto[1] |
auto[0] |
2503 |
1 |
|
|
T1 |
13 |
|
T15 |
13 |
|
T16 |
15 |
auto[1] |
auto[1] |
117 |
1 |
|
|
T15 |
2 |
|
T29 |
2 |
|
T84 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
45984 |
1 |
|
|
T2 |
2 |
|
T3 |
63 |
|
T11 |
18 |
auto[0] |
auto[1] |
1670 |
1 |
|
|
T14 |
3 |
|
T16 |
9 |
|
T59 |
7 |
auto[1] |
auto[0] |
2450 |
1 |
|
|
T1 |
13 |
|
T15 |
15 |
|
T16 |
15 |
auto[1] |
auto[1] |
170 |
1 |
|
|
T79 |
2 |
|
T27 |
4 |
|
T29 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
45993 |
1 |
|
|
T2 |
2 |
|
T3 |
63 |
|
T11 |
18 |
auto[0] |
auto[1] |
1661 |
1 |
|
|
T14 |
7 |
|
T16 |
11 |
|
T59 |
3 |
auto[1] |
auto[0] |
2479 |
1 |
|
|
T1 |
13 |
|
T15 |
15 |
|
T16 |
13 |
auto[1] |
auto[1] |
141 |
1 |
|
|
T16 |
2 |
|
T160 |
3 |
|
T222 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
45999 |
1 |
|
|
T2 |
2 |
|
T3 |
63 |
|
T11 |
18 |
auto[0] |
auto[1] |
1655 |
1 |
|
|
T14 |
6 |
|
T16 |
11 |
|
T59 |
3 |
auto[1] |
auto[0] |
2473 |
1 |
|
|
T1 |
11 |
|
T15 |
14 |
|
T16 |
15 |
auto[1] |
auto[1] |
147 |
1 |
|
|
T1 |
2 |
|
T15 |
1 |
|
T79 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
45995 |
1 |
|
|
T2 |
2 |
|
T3 |
63 |
|
T11 |
18 |
auto[0] |
auto[1] |
1659 |
1 |
|
|
T14 |
14 |
|
T16 |
8 |
|
T59 |
5 |
auto[1] |
auto[0] |
2459 |
1 |
|
|
T1 |
13 |
|
T15 |
13 |
|
T16 |
13 |
auto[1] |
auto[1] |
161 |
1 |
|
|
T15 |
2 |
|
T16 |
2 |
|
T79 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
46047 |
1 |
|
|
T2 |
2 |
|
T3 |
63 |
|
T11 |
18 |
auto[0] |
auto[1] |
1607 |
1 |
|
|
T14 |
12 |
|
T16 |
10 |
|
T59 |
9 |
auto[1] |
auto[0] |
2496 |
1 |
|
|
T1 |
12 |
|
T15 |
15 |
|
T16 |
15 |
auto[1] |
auto[1] |
124 |
1 |
|
|
T1 |
1 |
|
T29 |
1 |
|
T223 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33343 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
63 |
auto[0] |
auto[1] |
1022 |
1 |
|
|
T17 |
15 |
|
T18 |
14 |
|
T84 |
12 |
auto[1] |
auto[0] |
15271 |
1 |
|
|
T10 |
8 |
|
T16 |
157 |
|
T27 |
202 |
auto[1] |
auto[1] |
638 |
1 |
|
|
T16 |
4 |
|
T28 |
10 |
|
T29 |
10 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33398 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
63 |
auto[0] |
auto[1] |
967 |
1 |
|
|
T17 |
15 |
|
T18 |
10 |
|
T84 |
6 |
auto[1] |
auto[0] |
15220 |
1 |
|
|
T10 |
8 |
|
T16 |
147 |
|
T27 |
202 |
auto[1] |
auto[1] |
689 |
1 |
|
|
T16 |
14 |
|
T28 |
10 |
|
T29 |
18 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33187 |
1 |
|
|
T1 |
13 |
|
T3 |
63 |
|
T11 |
18 |
auto[0] |
auto[1] |
1178 |
1 |
|
|
T2 |
2 |
|
T25 |
12 |
|
T65 |
7 |
auto[1] |
auto[0] |
14894 |
1 |
|
|
T10 |
8 |
|
T16 |
140 |
|
T27 |
202 |
auto[1] |
auto[1] |
1015 |
1 |
|
|
T16 |
21 |
|
T224 |
15 |
|
T84 |
34 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33398 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
63 |
auto[0] |
auto[1] |
967 |
1 |
|
|
T17 |
12 |
|
T18 |
11 |
|
T84 |
6 |
auto[1] |
auto[0] |
15341 |
1 |
|
|
T10 |
8 |
|
T16 |
148 |
|
T27 |
202 |
auto[1] |
auto[1] |
568 |
1 |
|
|
T16 |
13 |
|
T28 |
16 |
|
T29 |
14 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
29620 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
63 |
auto[0] |
auto[1] |
4745 |
1 |
|
|
T221 |
70 |
|
T17 |
11 |
|
T18 |
14 |
auto[1] |
auto[0] |
15258 |
1 |
|
|
T10 |
8 |
|
T16 |
156 |
|
T27 |
202 |
auto[1] |
auto[1] |
651 |
1 |
|
|
T16 |
5 |
|
T28 |
10 |
|
T29 |
12 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33410 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
63 |
auto[0] |
auto[1] |
955 |
1 |
|
|
T14 |
12 |
|
T15 |
2 |
|
T59 |
6 |
auto[1] |
auto[0] |
15039 |
1 |
|
|
T10 |
8 |
|
T16 |
155 |
|
T27 |
175 |
auto[1] |
auto[1] |
870 |
1 |
|
|
T16 |
6 |
|
T27 |
27 |
|
T225 |
1 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33457 |
1 |
|
|
T1 |
12 |
|
T2 |
2 |
|
T3 |
63 |
auto[0] |
auto[1] |
908 |
1 |
|
|
T1 |
1 |
|
T14 |
8 |
|
T16 |
1 |
auto[1] |
auto[0] |
15071 |
1 |
|
|
T10 |
8 |
|
T16 |
155 |
|
T27 |
186 |
auto[1] |
auto[1] |
838 |
1 |
|
|
T16 |
6 |
|
T27 |
16 |
|
T225 |
2 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33439 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
63 |
auto[0] |
auto[1] |
926 |
1 |
|
|
T14 |
3 |
|
T59 |
7 |
|
T79 |
2 |
auto[1] |
auto[0] |
14995 |
1 |
|
|
T10 |
8 |
|
T16 |
152 |
|
T27 |
181 |
auto[1] |
auto[1] |
914 |
1 |
|
|
T16 |
9 |
|
T27 |
21 |
|
T226 |
3 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33390 |
1 |
|
|
T1 |
12 |
|
T2 |
2 |
|
T3 |
63 |
auto[0] |
auto[1] |
975 |
1 |
|
|
T1 |
1 |
|
T14 |
9 |
|
T15 |
1 |
auto[1] |
auto[0] |
15051 |
1 |
|
|
T10 |
8 |
|
T16 |
157 |
|
T27 |
181 |
auto[1] |
auto[1] |
858 |
1 |
|
|
T16 |
4 |
|
T27 |
21 |
|
T223 |
23 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33440 |
1 |
|
|
T1 |
11 |
|
T2 |
2 |
|
T3 |
63 |
auto[0] |
auto[1] |
925 |
1 |
|
|
T1 |
2 |
|
T14 |
6 |
|
T15 |
1 |
auto[1] |
auto[0] |
15032 |
1 |
|
|
T10 |
8 |
|
T16 |
150 |
|
T27 |
177 |
auto[1] |
auto[1] |
877 |
1 |
|
|
T16 |
11 |
|
T27 |
25 |
|
T225 |
2 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33440 |
1 |
|
|
T1 |
12 |
|
T2 |
2 |
|
T3 |
63 |
auto[0] |
auto[1] |
925 |
1 |
|
|
T1 |
1 |
|
T14 |
12 |
|
T59 |
9 |
auto[1] |
auto[0] |
15103 |
1 |
|
|
T10 |
8 |
|
T16 |
151 |
|
T27 |
182 |
auto[1] |
auto[1] |
806 |
1 |
|
|
T16 |
10 |
|
T27 |
20 |
|
T223 |
25 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33417 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
63 |
auto[0] |
auto[1] |
948 |
1 |
|
|
T17 |
7 |
|
T18 |
11 |
|
T84 |
9 |
auto[1] |
auto[0] |
15284 |
1 |
|
|
T10 |
8 |
|
T16 |
154 |
|
T27 |
202 |
auto[1] |
auto[1] |
625 |
1 |
|
|
T16 |
7 |
|
T28 |
10 |
|
T29 |
7 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33375 |
1 |
|
|
T1 |
13 |
|
T2 |
2 |
|
T3 |
63 |
auto[0] |
auto[1] |
990 |
1 |
|
|
T17 |
13 |
|
T18 |
12 |
|
T84 |
8 |
auto[1] |
auto[0] |
15275 |
1 |
|
|
T10 |
8 |
|
T16 |
153 |
|
T27 |
202 |
auto[1] |
auto[1] |
634 |
1 |
|
|
T16 |
8 |
|
T28 |
7 |
|
T29 |
19 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32893 |
1 |
|
|
T2 |
2 |
|
T3 |
63 |
|
T11 |
18 |
auto[0] |
auto[1] |
1472 |
1 |
|
|
T1 |
13 |
|
T15 |
15 |
|
T16 |
15 |
auto[1] |
auto[0] |
14761 |
1 |
|
|
T10 |
8 |
|
T16 |
161 |
|
T27 |
174 |
auto[1] |
auto[1] |
1148 |
1 |
|
|
T27 |
28 |
|
T225 |
15 |
|
T226 |
11 |