Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

93592784

1

T1

6665

T2

1987

T3

30334

auto[1]

1316385

1

T1

99

T2

99

T3

990

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

93580263

1

T1

6368

T2

1987

T3

30037

auto[1]

1328906

1

T1

396

T2

99

T3

1287

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7144270	1			T1	1858		T2	272		T3	6418
auto[IdleSt]	20786965	1			T1	1186		T2	1310		T3	7099
auto[ClkMuxSt]	33054	1			T1	4		T2	2		T3	53
auto[CntIncrSt]	32841	1			T1	4		T2	2		T3	53
auto[CntProgSt]	1548750	1			T1	8		T2	24		T3	549
auto[TransCheckSt]	25684	1			T1	4		T3	40		T11	17
auto[TokenHashSt]	33380734	1			T1	76		T3	2651		T11	192
auto[FlashRmaSt]	33135	1			T1	27		T3	123		T11	54
auto[TokenCheck0St]	11637	1			T1	4		T3	38		T11	17
auto[TokenCheck1St]	8579	1			T1	4		T3	20		T11	17
auto[TransProgSt]	361383	1			T1	8		T3	297		T11	6403
auto[PostTransSt]	12365506	1			T1	1198		T2	167		T3	8760
auto[ScrapSt]	111836	1			T11	48		T12	6		T16	55
auto[EscalateSt]	6799117	1			T1	1466		T2	309		T3	3323
auto[InvalidSt]	12263774	1			T1	917		T3	1900		T14	8825

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1904	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12263774	1			T1	917		T3	1900		T14	8825
EscalateSt	6799117	1			T1	1466		T2	309		T3	3323
ScrapSt	111836	1			T11	48		T12	6		T16	55
PostTransSt	12365506	1			T1	1198		T2	167		T3	8760
TransProgSt	361383	1			T1	8		T3	297		T11	6403
TokenCheck1St	8579	1			T1	4		T3	20		T11	17
TokenCheck0St	11637	1			T1	4		T3	38		T11	17
FlashRmaSt	33135	1			T1	27		T3	123		T11	54
TokenHashSt	33380734	1			T1	76		T3	2651		T11	192
TransCheckSt	25684	1			T1	4		T3	40		T11	17
CntProgSt	1548750	1			T1	8		T2	24		T3	549
CntIncrSt	32841	1			T1	4		T2	2		T3	53
ClkMuxSt	33054	1			T1	4		T2	2		T3	53
IdleSt	20786965	1			T1	1186		T2	1310		T3	7099
ResetSt	7144270	1			T1	1858		T2	272		T3	6418
arcs[ResetSt=>IdleSt]	50456	1			T1	10		T2	3		T3	64
arcs[IdleSt=>ScrapSt]	279	1			T11	1		T12	2		T16	2
arcs[IdleSt=>ClkMuxSt]	32898	1			T1	4		T2	2		T3	53
arcs[ClkMuxSt=>CntIncrSt]	32841	1			T1	4		T2	2		T3	53
arcs[CntIncrSt=>PostTransSt]	1627	1			T16	8		T17	13		T18	12
arcs[CntIncrSt=>CntProgSt]	31151	1			T1	4		T2	2		T3	53
arcs[CntProgSt=>PostTransSt]	4389	1			T2	2		T3	13		T25	12
arcs[CntProgSt=>TransCheckSt]	25684	1			T1	4		T3	40		T11	17
arcs[TransCheckSt=>PostTransSt]	3540	1			T16	7		T17	7		T18	11
arcs[TransCheckSt=>TokenHashSt]	22043	1			T1	4		T3	40		T11	17
arcs[TokenHashSt=>PostTransSt]	9646	1			T3	2		T22	1		T23	1
arcs[TokenHashSt=>FlashRmaSt]	11750	1			T1	4		T3	38		T11	17
arcs[FlashRmaSt=>TokenCheck0St]	11637	1			T1	4		T3	38		T11	17
arcs[TokenCheck0St=>PostTransSt]	3029	1			T3	18		T16	13		T37	5
arcs[TokenCheck0St=>TokenCheck1St]	8579	1			T1	4		T3	20		T11	17
arcs[TokenCheck1St=>PostTransSt]	580	1			T16	1		T18	2		T29	2
arcs[TransProgSt=>PostTransSt]	7110	1			T1	4		T3	20		T11	17
arcs[IdleSt=>EscalateSt]	167	1			T12	9		T24	7		T47	7
arcs[ClkMuxSt=>EscalateSt]	57	1			T24	1		T45	2		T46	1
arcs[CntIncrSt=>EscalateSt]	63	1			T12	4		T24	2		T47	2
arcs[CntProgSt=>EscalateSt]	1078	1			T12	21		T24	7		T47	43
arcs[TransCheckSt=>EscalateSt]	101	1			T24	2		T48	9		T53	1
arcs[TokenHashSt=>EscalateSt]	647	1			T12	16		T24	18		T29	1
arcs[FlashRmaSt=>EscalateSt]	113	1			T12	7		T47	4		T48	3
arcs[TokenCheck0St=>EscalateSt]	29	1			T48	3		T52	1		T53	1
arcs[TokenCheck1St=>EscalateSt]	145	1			T12	6		T24	2		T47	6
arcs[TransProgSt=>EscalateSt]	744	1			T12	21		T24	12		T47	20
arcs[PostTransSt=>EscalateSt]	4599	1			T2	2		T3	13		T25	12
arcs[InvalidSt=>EscalateSt]	13209	1			T1	5		T3	10		T14	64

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7144123	1			T1	1858		T2	272		T3	6418
auto[0]	auto[IdleSt]	20786853	1			T1	1186		T2	1310		T3	7099
auto[0]	auto[ClkMuxSt]	33012	1			T1	4		T2	2		T3	53
auto[0]	auto[CntIncrSt]	32810	1			T1	4		T2	2		T3	53
auto[0]	auto[CntProgSt]	1548035	1			T1	8		T2	24		T3	549
auto[0]	auto[TransCheckSt]	25616	1			T1	4		T3	40		T11	17
auto[0]	auto[TokenHashSt]	33380304	1			T1	76		T3	2651		T11	192
auto[0]	auto[FlashRmaSt]	33055	1			T1	27		T3	123		T11	54
auto[0]	auto[TokenCheck0St]	11612	1			T1	4		T3	38		T11	17
auto[0]	auto[TokenCheck1St]	8488	1			T1	4		T3	20		T11	17
auto[0]	auto[TransProgSt]	360884	1			T1	8		T3	297		T11	6403
auto[0]	auto[PostTransSt]	12363181	1			T1	1198		T2	166		T3	8754
auto[0]	auto[ScrapSt]	111787	1			T11	48		T12	4		T16	55
auto[0]	auto[EscalateSt]	5493942	1			T1	1368		T2	211		T3	2343
auto[0]	auto[InvalidSt]	12257178	1			T1	916		T3	1896		T14	8795
auto[1]	auto[ResetSt]	147	1			T12	7		T24	6		T48	2
auto[1]	auto[IdleSt]	112	1			T12	6		T24	5		T47	4
auto[1]	auto[ClkMuxSt]	42	1			T45	2		T46	1		T220	1
auto[1]	auto[CntIncrSt]	31	1			T12	1		T47	2		T48	1
auto[1]	auto[CntProgSt]	715	1			T12	15		T24	5		T47	28
auto[1]	auto[TransCheckSt]	68	1			T24	1		T48	6		T220	2
auto[1]	auto[TokenHashSt]	430	1			T12	10		T24	11		T47	9
auto[1]	auto[FlashRmaSt]	80	1			T12	4		T47	2		T48	1
auto[1]	auto[TokenCheck0St]	25	1			T48	3		T52	1		T53	1
auto[1]	auto[TokenCheck1St]	91	1			T12	5		T47	3		T48	1
auto[1]	auto[TransProgSt]	499	1			T12	15		T24	7		T47	15
auto[1]	auto[PostTransSt]	2325	1			T2	1		T3	6		T25	6
auto[1]	auto[ScrapSt]	49	1			T12	2		T24	1		T47	1
auto[1]	auto[EscalateSt]	1305175	1			T1	98		T2	98		T3	980
auto[1]	auto[InvalidSt]	6596	1			T1	1		T3	4		T14	30

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7144097	1			T1	1858		T2	272		T3	6418
auto[0]	auto[IdleSt]	20786848	1			T1	1186		T2	1310		T3	7099
auto[0]	auto[ClkMuxSt]	33020	1			T1	4		T2	2		T3	53
auto[0]	auto[CntIncrSt]	32794	1			T1	4		T2	2		T3	53
auto[0]	auto[CntProgSt]	1548015	1			T1	8		T2	24		T3	549
auto[0]	auto[TransCheckSt]	25617	1			T1	4		T3	40		T11	17
auto[0]	auto[TokenHashSt]	33380309	1			T1	76		T3	2651		T11	192
auto[0]	auto[FlashRmaSt]	33070	1			T1	27		T3	123		T11	54
auto[0]	auto[TokenCheck0St]	11617	1			T1	4		T3	38		T11	17
auto[0]	auto[TokenCheck1St]	8486	1			T1	4		T3	20		T11	17
auto[0]	auto[TransProgSt]	360883	1			T1	8		T3	297		T11	6403
auto[0]	auto[PostTransSt]	12363173	1			T1	1198		T2	166		T3	8753
auto[0]	auto[ScrapSt]	111780	1			T11	48		T12	4		T16	55
auto[0]	auto[EscalateSt]	5481489	1			T1	1074		T2	211		T3	2049
auto[0]	auto[InvalidSt]	12257161	1			T1	913		T3	1894		T14	8791
auto[1]	auto[ResetSt]	173	1			T12	8		T24	6		T47	3
auto[1]	auto[IdleSt]	117	1			T12	8		T24	6		T47	7
auto[1]	auto[ClkMuxSt]	34	1			T24	1		T45	2		T220	1
auto[1]	auto[CntIncrSt]	47	1			T12	4		T24	2		T47	2
auto[1]	auto[CntProgSt]	735	1			T12	15		T24	3		T47	29
auto[1]	auto[TransCheckSt]	67	1			T24	1		T48	7		T53	1
auto[1]	auto[TokenHashSt]	425	1			T12	11		T24	13		T29	1
auto[1]	auto[FlashRmaSt]	65	1			T12	5		T47	2		T48	2
auto[1]	auto[TokenCheck0St]	20	1			T48	2		T52	1		T53	1
auto[1]	auto[TokenCheck1St]	93	1			T12	3		T24	2		T47	5
auto[1]	auto[TransProgSt]	500	1			T12	16		T24	9		T47	15
auto[1]	auto[PostTransSt]	2333	1			T2	1		T3	7		T25	6
auto[1]	auto[ScrapSt]	56	1			T12	2		T24	1		T52	2
auto[1]	auto[EscalateSt]	1317628	1			T1	392		T2	98		T3	1274
auto[1]	auto[InvalidSt]	6613	1			T1	4		T3	6		T14	34